1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sc7280 fragment for devices with Chrome bootloader 4 * 5 * This file mainly tries to abstract out the memory protections put into 6 * place by the Chrome bootloader which are different than what's put into 7 * place by Qualcomm's typical bootloader. It also has a smattering of other 8 * things that will hold true for any conceivable Chrome design 9 * 10 * Copyright 2022 Google LLC. 11 */ 12 13/* 14 * Reserved memory changes 15 * 16 * Delete all unused memory nodes and define the peripheral memory regions 17 * required by the setup for Chrome boards. 18 */ 19 20/delete-node/ &cdsp_mem; 21/delete-node/ &domain_idle_states; 22/delete-node/ &gpu_zap_mem; 23/delete-node/ &gpu_zap_shader; 24/delete-node/ &hyp_mem; 25/delete-node/ &xbl_mem; 26/delete-node/ &reserved_xbl_uefi_log; 27/delete-node/ &sec_apps_mem; 28 29/ { 30 cpus { 31 domain_idle_states: domain-idle-states { 32 cluster_sleep_0: cluster-sleep-0 { 33 compatible = "domain-idle-state"; 34 arm,psci-suspend-param = <0x40003444>; 35 entry-latency-us = <2752>; 36 exit-latency-us = <6562>; 37 min-residency-us = <9926>; 38 }; 39 }; 40 }; 41 42 reserved-memory { 43 camera_mem: memory@8ad00000 { 44 reg = <0x0 0x8ad00000 0x0 0x500000>; 45 no-map; 46 }; 47 }; 48}; 49 50&cluster_pd { 51 domain-idle-states = <&cluster_sleep_0>; 52}; 53 54&gpu { 55 status = "okay"; 56}; 57 58&lpass_aon { 59 status = "okay"; 60}; 61 62&lpass_core { 63 status = "okay"; 64}; 65 66&lpass_hm { 67 status = "okay"; 68}; 69 70&lpasscc { 71 status = "okay"; 72}; 73 74&pdc_reset { 75 status = "okay"; 76}; 77 78/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */ 79&pmk8350_pon { 80 status = "disabled"; 81}; 82 83/* 84 * Chrome designs always boot from SPI flash hooked up to the qspi. 85 * 86 * It's expected that all boards will support "dual SPI" at 37.5 MHz. 87 * If some boards need a different speed or have a package that allows 88 * Quad SPI together with WP then those boards can easily override. 89 */ 90&qspi { 91 status = "okay"; 92 pinctrl-names = "default", "sleep"; 93 pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; 94 pinctrl-1 = <&qspi_sleep>; 95 96 spi_flash: flash@0 { 97 compatible = "jedec,spi-nor"; 98 reg = <0>; 99 100 spi-max-frequency = <37500000>; 101 spi-tx-bus-width = <2>; 102 spi-rx-bus-width = <2>; 103 }; 104}; 105 106/* Currently not used */ 107&remoteproc_cdsp { 108 /delete-property/ memory-region; 109}; 110 111&remoteproc_wpss { 112 compatible = "qcom,sc7280-wpss-pil"; 113 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 114 <&gcc GCC_WPSS_AHB_CLK>, 115 <&gcc GCC_WPSS_RSCP_CLK>, 116 <&rpmhcc RPMH_CXO_CLK>; 117 clock-names = "ahb_bdg", 118 "ahb", 119 "rscp", 120 "xo"; 121 122 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 123 <&pdc_reset PDC_WPSS_SYNC_RESET>; 124 reset-names = "restart", "pdc_sync"; 125 126 qcom,halt-regs = <&tcsr_1 0x17000>; 127 128 firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt"; 129 130 status = "okay"; 131}; 132 133&scm { 134 /* TF-A firmware maps memory cached so mark dma-coherent to match. */ 135 dma-coherent; 136}; 137 138&venus { 139 iommus = <&apps_smmu 0x2180 0x20>, 140 <&apps_smmu 0x2184 0x20>; 141 142 status = "okay"; 143 144 video-firmware { 145 iommus = <&apps_smmu 0x21a2 0x0>; 146 }; 147}; 148 149&watchdog { 150 status = "okay"; 151}; 152 153&wifi { 154 status = "okay"; 155 156 wifi-firmware { 157 iommus = <&apps_smmu 0x1c02 0x1>; 158 }; 159}; 160 161/* PINCTRL - chrome-common pinctrl */ 162 163&tlmm { 164 qspi_sleep: qspi-sleep-state { 165 pins = "gpio12", "gpio13", "gpio14", "gpio15"; 166 167 /* 168 * When we're not actively transferring we want pins as GPIOs 169 * with output disabled so that the quad SPI IP block stops 170 * driving them. We rely on the normal pulls configured in 171 * the active state and don't redefine them here. Also note 172 * that we don't need the reverse (output-enable) in the 173 * normal mode since the "output-enable" only matters for 174 * GPIO function. 175 */ 176 function = "gpio"; 177 output-disable; 178 }; 179}; 180