1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,sc7180.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/phy/phy-qcom-qusb2.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/reset/qcom,sdm845-aoss.h> 23#include <dt-bindings/reset/qcom,sdm845-pdc.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/soc/qcom,apr.h> 26#include <dt-bindings/sound/qcom,q6afe.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 aliases { 36 mmc1 = &sdhc_1; 37 mmc2 = &sdhc_2; 38 i2c0 = &i2c0; 39 i2c1 = &i2c1; 40 i2c2 = &i2c2; 41 i2c3 = &i2c3; 42 i2c4 = &i2c4; 43 i2c5 = &i2c5; 44 i2c6 = &i2c6; 45 i2c7 = &i2c7; 46 i2c8 = &i2c8; 47 i2c9 = &i2c9; 48 i2c10 = &i2c10; 49 i2c11 = &i2c11; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi3 = &spi3; 53 spi5 = &spi5; 54 spi6 = &spi6; 55 spi8 = &spi8; 56 spi10 = &spi10; 57 spi11 = &spi11; 58 }; 59 60 chosen { }; 61 62 clocks { 63 xo_board: xo-board { 64 compatible = "fixed-clock"; 65 clock-frequency = <38400000>; 66 #clock-cells = <0>; 67 }; 68 69 sleep_clk: sleep-clk { 70 compatible = "fixed-clock"; 71 clock-frequency = <32764>; 72 #clock-cells = <0>; 73 }; 74 }; 75 76 cpus { 77 #address-cells = <2>; 78 #size-cells = <0>; 79 80 cpu0: cpu@0 { 81 device_type = "cpu"; 82 compatible = "qcom,kryo468"; 83 reg = <0x0 0x0>; 84 clocks = <&cpufreq_hw 0>; 85 enable-method = "psci"; 86 power-domains = <&cpu_pd0>; 87 power-domain-names = "psci"; 88 capacity-dmips-mhz = <415>; 89 dynamic-power-coefficient = <137>; 90 operating-points-v2 = <&cpu0_opp_table>; 91 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 92 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 93 next-level-cache = <&l2_0>; 94 #cooling-cells = <2>; 95 qcom,freq-domain = <&cpufreq_hw 0>; 96 l2_0: l2-cache { 97 compatible = "cache"; 98 cache-level = <2>; 99 cache-unified; 100 next-level-cache = <&l3_0>; 101 l3_0: l3-cache { 102 compatible = "cache"; 103 cache-level = <3>; 104 cache-unified; 105 }; 106 }; 107 }; 108 109 cpu1: cpu@100 { 110 device_type = "cpu"; 111 compatible = "qcom,kryo468"; 112 reg = <0x0 0x100>; 113 clocks = <&cpufreq_hw 0>; 114 enable-method = "psci"; 115 power-domains = <&cpu_pd1>; 116 power-domain-names = "psci"; 117 capacity-dmips-mhz = <415>; 118 dynamic-power-coefficient = <137>; 119 next-level-cache = <&l2_100>; 120 operating-points-v2 = <&cpu0_opp_table>; 121 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 122 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 123 #cooling-cells = <2>; 124 qcom,freq-domain = <&cpufreq_hw 0>; 125 l2_100: l2-cache { 126 compatible = "cache"; 127 cache-level = <2>; 128 cache-unified; 129 next-level-cache = <&l3_0>; 130 }; 131 }; 132 133 cpu2: cpu@200 { 134 device_type = "cpu"; 135 compatible = "qcom,kryo468"; 136 reg = <0x0 0x200>; 137 clocks = <&cpufreq_hw 0>; 138 enable-method = "psci"; 139 power-domains = <&cpu_pd2>; 140 power-domain-names = "psci"; 141 capacity-dmips-mhz = <415>; 142 dynamic-power-coefficient = <137>; 143 next-level-cache = <&l2_200>; 144 operating-points-v2 = <&cpu0_opp_table>; 145 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 146 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 147 #cooling-cells = <2>; 148 qcom,freq-domain = <&cpufreq_hw 0>; 149 l2_200: l2-cache { 150 compatible = "cache"; 151 cache-level = <2>; 152 cache-unified; 153 next-level-cache = <&l3_0>; 154 }; 155 }; 156 157 cpu3: cpu@300 { 158 device_type = "cpu"; 159 compatible = "qcom,kryo468"; 160 reg = <0x0 0x300>; 161 clocks = <&cpufreq_hw 0>; 162 enable-method = "psci"; 163 power-domains = <&cpu_pd3>; 164 power-domain-names = "psci"; 165 capacity-dmips-mhz = <415>; 166 dynamic-power-coefficient = <137>; 167 next-level-cache = <&l2_300>; 168 operating-points-v2 = <&cpu0_opp_table>; 169 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 170 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 171 #cooling-cells = <2>; 172 qcom,freq-domain = <&cpufreq_hw 0>; 173 l2_300: l2-cache { 174 compatible = "cache"; 175 cache-level = <2>; 176 cache-unified; 177 next-level-cache = <&l3_0>; 178 }; 179 }; 180 181 cpu4: cpu@400 { 182 device_type = "cpu"; 183 compatible = "qcom,kryo468"; 184 reg = <0x0 0x400>; 185 clocks = <&cpufreq_hw 0>; 186 enable-method = "psci"; 187 power-domains = <&cpu_pd4>; 188 power-domain-names = "psci"; 189 capacity-dmips-mhz = <415>; 190 dynamic-power-coefficient = <137>; 191 next-level-cache = <&l2_400>; 192 operating-points-v2 = <&cpu0_opp_table>; 193 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 194 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 195 #cooling-cells = <2>; 196 qcom,freq-domain = <&cpufreq_hw 0>; 197 l2_400: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 cache-unified; 201 next-level-cache = <&l3_0>; 202 }; 203 }; 204 205 cpu5: cpu@500 { 206 device_type = "cpu"; 207 compatible = "qcom,kryo468"; 208 reg = <0x0 0x500>; 209 clocks = <&cpufreq_hw 0>; 210 enable-method = "psci"; 211 power-domains = <&cpu_pd5>; 212 power-domain-names = "psci"; 213 capacity-dmips-mhz = <415>; 214 dynamic-power-coefficient = <137>; 215 next-level-cache = <&l2_500>; 216 operating-points-v2 = <&cpu0_opp_table>; 217 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 218 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 219 #cooling-cells = <2>; 220 qcom,freq-domain = <&cpufreq_hw 0>; 221 l2_500: l2-cache { 222 compatible = "cache"; 223 cache-level = <2>; 224 cache-unified; 225 next-level-cache = <&l3_0>; 226 }; 227 }; 228 229 cpu6: cpu@600 { 230 device_type = "cpu"; 231 compatible = "qcom,kryo468"; 232 reg = <0x0 0x600>; 233 clocks = <&cpufreq_hw 1>; 234 enable-method = "psci"; 235 power-domains = <&cpu_pd6>; 236 power-domain-names = "psci"; 237 capacity-dmips-mhz = <1024>; 238 dynamic-power-coefficient = <480>; 239 next-level-cache = <&l2_600>; 240 operating-points-v2 = <&cpu6_opp_table>; 241 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 242 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 243 #cooling-cells = <2>; 244 qcom,freq-domain = <&cpufreq_hw 1>; 245 l2_600: l2-cache { 246 compatible = "cache"; 247 cache-level = <2>; 248 cache-unified; 249 next-level-cache = <&l3_0>; 250 }; 251 }; 252 253 cpu7: cpu@700 { 254 device_type = "cpu"; 255 compatible = "qcom,kryo468"; 256 reg = <0x0 0x700>; 257 clocks = <&cpufreq_hw 1>; 258 enable-method = "psci"; 259 power-domains = <&cpu_pd7>; 260 power-domain-names = "psci"; 261 capacity-dmips-mhz = <1024>; 262 dynamic-power-coefficient = <480>; 263 next-level-cache = <&l2_700>; 264 operating-points-v2 = <&cpu6_opp_table>; 265 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 266 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 267 #cooling-cells = <2>; 268 qcom,freq-domain = <&cpufreq_hw 1>; 269 l2_700: l2-cache { 270 compatible = "cache"; 271 cache-level = <2>; 272 cache-unified; 273 next-level-cache = <&l3_0>; 274 }; 275 }; 276 277 cpu-map { 278 cluster0 { 279 core0 { 280 cpu = <&cpu0>; 281 }; 282 283 core1 { 284 cpu = <&cpu1>; 285 }; 286 287 core2 { 288 cpu = <&cpu2>; 289 }; 290 291 core3 { 292 cpu = <&cpu3>; 293 }; 294 295 core4 { 296 cpu = <&cpu4>; 297 }; 298 299 core5 { 300 cpu = <&cpu5>; 301 }; 302 303 core6 { 304 cpu = <&cpu6>; 305 }; 306 307 core7 { 308 cpu = <&cpu7>; 309 }; 310 }; 311 }; 312 313 idle_states: idle-states { 314 entry-method = "psci"; 315 316 little_cpu_sleep_0: cpu-sleep-0-0 { 317 compatible = "arm,idle-state"; 318 idle-state-name = "little-power-down"; 319 arm,psci-suspend-param = <0x40000003>; 320 entry-latency-us = <549>; 321 exit-latency-us = <901>; 322 min-residency-us = <1774>; 323 local-timer-stop; 324 }; 325 326 little_cpu_sleep_1: cpu-sleep-0-1 { 327 compatible = "arm,idle-state"; 328 idle-state-name = "little-rail-power-down"; 329 arm,psci-suspend-param = <0x40000004>; 330 entry-latency-us = <702>; 331 exit-latency-us = <915>; 332 min-residency-us = <4001>; 333 local-timer-stop; 334 }; 335 336 big_cpu_sleep_0: cpu-sleep-1-0 { 337 compatible = "arm,idle-state"; 338 idle-state-name = "big-power-down"; 339 arm,psci-suspend-param = <0x40000003>; 340 entry-latency-us = <523>; 341 exit-latency-us = <1244>; 342 min-residency-us = <2207>; 343 local-timer-stop; 344 }; 345 346 big_cpu_sleep_1: cpu-sleep-1-1 { 347 compatible = "arm,idle-state"; 348 idle-state-name = "big-rail-power-down"; 349 arm,psci-suspend-param = <0x40000004>; 350 entry-latency-us = <526>; 351 exit-latency-us = <1854>; 352 min-residency-us = <5555>; 353 local-timer-stop; 354 }; 355 }; 356 357 domain_idle_states: domain-idle-states { 358 cluster_sleep_pc: cluster-sleep-0 { 359 compatible = "domain-idle-state"; 360 arm,psci-suspend-param = <0x41000044>; 361 entry-latency-us = <2752>; 362 exit-latency-us = <3048>; 363 min-residency-us = <6118>; 364 }; 365 366 cluster_sleep_cx_ret: cluster-sleep-1 { 367 compatible = "domain-idle-state"; 368 arm,psci-suspend-param = <0x41001244>; 369 entry-latency-us = <3638>; 370 exit-latency-us = <4562>; 371 min-residency-us = <8467>; 372 }; 373 374 cluster_aoss_sleep: cluster-sleep-2 { 375 compatible = "domain-idle-state"; 376 arm,psci-suspend-param = <0x4100b244>; 377 entry-latency-us = <3263>; 378 exit-latency-us = <6562>; 379 min-residency-us = <9826>; 380 }; 381 }; 382 }; 383 384 firmware { 385 scm: scm { 386 compatible = "qcom,scm-sc7180", "qcom,scm"; 387 }; 388 }; 389 390 memory@80000000 { 391 device_type = "memory"; 392 /* We expect the bootloader to fill in the size */ 393 reg = <0 0x80000000 0 0>; 394 }; 395 396 cpu0_opp_table: opp-table-cpu0 { 397 compatible = "operating-points-v2"; 398 opp-shared; 399 400 cpu0_opp1: opp-300000000 { 401 opp-hz = /bits/ 64 <300000000>; 402 opp-peak-kBps = <1200000 4800000>; 403 }; 404 405 cpu0_opp2: opp-576000000 { 406 opp-hz = /bits/ 64 <576000000>; 407 opp-peak-kBps = <1200000 4800000>; 408 }; 409 410 cpu0_opp3: opp-768000000 { 411 opp-hz = /bits/ 64 <768000000>; 412 opp-peak-kBps = <1200000 4800000>; 413 }; 414 415 cpu0_opp4: opp-1017600000 { 416 opp-hz = /bits/ 64 <1017600000>; 417 opp-peak-kBps = <1804000 8908800>; 418 }; 419 420 cpu0_opp5: opp-1248000000 { 421 opp-hz = /bits/ 64 <1248000000>; 422 opp-peak-kBps = <2188000 12902400>; 423 }; 424 425 cpu0_opp6: opp-1324800000 { 426 opp-hz = /bits/ 64 <1324800000>; 427 opp-peak-kBps = <2188000 12902400>; 428 }; 429 430 cpu0_opp7: opp-1516800000 { 431 opp-hz = /bits/ 64 <1516800000>; 432 opp-peak-kBps = <3072000 15052800>; 433 }; 434 435 cpu0_opp8: opp-1612800000 { 436 opp-hz = /bits/ 64 <1612800000>; 437 opp-peak-kBps = <3072000 15052800>; 438 }; 439 440 cpu0_opp9: opp-1708800000 { 441 opp-hz = /bits/ 64 <1708800000>; 442 opp-peak-kBps = <3072000 15052800>; 443 }; 444 445 cpu0_opp10: opp-1804800000 { 446 opp-hz = /bits/ 64 <1804800000>; 447 opp-peak-kBps = <4068000 22425600>; 448 }; 449 }; 450 451 cpu6_opp_table: opp-table-cpu6 { 452 compatible = "operating-points-v2"; 453 opp-shared; 454 455 cpu6_opp1: opp-300000000 { 456 opp-hz = /bits/ 64 <300000000>; 457 opp-peak-kBps = <2188000 8908800>; 458 }; 459 460 cpu6_opp2: opp-652800000 { 461 opp-hz = /bits/ 64 <652800000>; 462 opp-peak-kBps = <2188000 8908800>; 463 }; 464 465 cpu6_opp3: opp-825600000 { 466 opp-hz = /bits/ 64 <825600000>; 467 opp-peak-kBps = <2188000 8908800>; 468 }; 469 470 cpu6_opp4: opp-979200000 { 471 opp-hz = /bits/ 64 <979200000>; 472 opp-peak-kBps = <2188000 8908800>; 473 }; 474 475 cpu6_opp5: opp-1113600000 { 476 opp-hz = /bits/ 64 <1113600000>; 477 opp-peak-kBps = <2188000 8908800>; 478 }; 479 480 cpu6_opp6: opp-1267200000 { 481 opp-hz = /bits/ 64 <1267200000>; 482 opp-peak-kBps = <4068000 12902400>; 483 }; 484 485 cpu6_opp7: opp-1555200000 { 486 opp-hz = /bits/ 64 <1555200000>; 487 opp-peak-kBps = <4068000 15052800>; 488 }; 489 490 cpu6_opp8: opp-1708800000 { 491 opp-hz = /bits/ 64 <1708800000>; 492 opp-peak-kBps = <6220000 19353600>; 493 }; 494 495 cpu6_opp9: opp-1843200000 { 496 opp-hz = /bits/ 64 <1843200000>; 497 opp-peak-kBps = <6220000 19353600>; 498 }; 499 500 cpu6_opp10: opp-1900800000 { 501 opp-hz = /bits/ 64 <1900800000>; 502 opp-peak-kBps = <6220000 22425600>; 503 }; 504 505 cpu6_opp11: opp-1996800000 { 506 opp-hz = /bits/ 64 <1996800000>; 507 opp-peak-kBps = <6220000 22425600>; 508 }; 509 510 cpu6_opp12: opp-2112000000 { 511 opp-hz = /bits/ 64 <2112000000>; 512 opp-peak-kBps = <6220000 22425600>; 513 }; 514 515 cpu6_opp13: opp-2208000000 { 516 opp-hz = /bits/ 64 <2208000000>; 517 opp-peak-kBps = <7216000 22425600>; 518 }; 519 520 cpu6_opp14: opp-2323200000 { 521 opp-hz = /bits/ 64 <2323200000>; 522 opp-peak-kBps = <7216000 22425600>; 523 }; 524 525 cpu6_opp15: opp-2400000000 { 526 opp-hz = /bits/ 64 <2400000000>; 527 opp-peak-kBps = <8532000 23347200>; 528 }; 529 530 cpu6_opp16: opp-2553600000 { 531 opp-hz = /bits/ 64 <2553600000>; 532 opp-peak-kBps = <8532000 23347200>; 533 }; 534 }; 535 536 qspi_opp_table: opp-table-qspi { 537 compatible = "operating-points-v2"; 538 539 opp-75000000 { 540 opp-hz = /bits/ 64 <75000000>; 541 required-opps = <&rpmhpd_opp_low_svs>; 542 }; 543 544 opp-150000000 { 545 opp-hz = /bits/ 64 <150000000>; 546 required-opps = <&rpmhpd_opp_svs>; 547 }; 548 549 opp-300000000 { 550 opp-hz = /bits/ 64 <300000000>; 551 required-opps = <&rpmhpd_opp_nom>; 552 }; 553 }; 554 555 qup_opp_table: opp-table-qup { 556 compatible = "operating-points-v2"; 557 558 opp-75000000 { 559 opp-hz = /bits/ 64 <75000000>; 560 required-opps = <&rpmhpd_opp_low_svs>; 561 }; 562 563 opp-100000000 { 564 opp-hz = /bits/ 64 <100000000>; 565 required-opps = <&rpmhpd_opp_svs>; 566 }; 567 568 opp-128000000 { 569 opp-hz = /bits/ 64 <128000000>; 570 required-opps = <&rpmhpd_opp_nom>; 571 }; 572 }; 573 574 pmu { 575 compatible = "arm,armv8-pmuv3"; 576 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 577 }; 578 579 psci { 580 compatible = "arm,psci-1.0"; 581 method = "smc"; 582 583 cpu_pd0: cpu0 { 584 #power-domain-cells = <0>; 585 power-domains = <&cluster_pd>; 586 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 587 }; 588 589 cpu_pd1: cpu1 { 590 #power-domain-cells = <0>; 591 power-domains = <&cluster_pd>; 592 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 593 }; 594 595 cpu_pd2: cpu2 { 596 #power-domain-cells = <0>; 597 power-domains = <&cluster_pd>; 598 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 599 }; 600 601 cpu_pd3: cpu3 { 602 #power-domain-cells = <0>; 603 power-domains = <&cluster_pd>; 604 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 605 }; 606 607 cpu_pd4: cpu4 { 608 #power-domain-cells = <0>; 609 power-domains = <&cluster_pd>; 610 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 611 }; 612 613 cpu_pd5: cpu5 { 614 #power-domain-cells = <0>; 615 power-domains = <&cluster_pd>; 616 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 617 }; 618 619 cpu_pd6: cpu6 { 620 #power-domain-cells = <0>; 621 power-domains = <&cluster_pd>; 622 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 623 }; 624 625 cpu_pd7: cpu7 { 626 #power-domain-cells = <0>; 627 power-domains = <&cluster_pd>; 628 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 629 }; 630 631 cluster_pd: cpu-cluster0 { 632 #power-domain-cells = <0>; 633 domain-idle-states = <&cluster_sleep_pc 634 &cluster_sleep_cx_ret 635 &cluster_aoss_sleep>; 636 }; 637 }; 638 639 reserved_memory: reserved-memory { 640 #address-cells = <2>; 641 #size-cells = <2>; 642 ranges; 643 644 hyp_mem: memory@80000000 { 645 reg = <0x0 0x80000000 0x0 0x600000>; 646 no-map; 647 }; 648 649 xbl_mem: memory@80600000 { 650 reg = <0x0 0x80600000 0x0 0x200000>; 651 no-map; 652 }; 653 654 aop_mem: memory@80800000 { 655 reg = <0x0 0x80800000 0x0 0x20000>; 656 no-map; 657 }; 658 659 aop_cmd_db_mem: memory@80820000 { 660 reg = <0x0 0x80820000 0x0 0x20000>; 661 compatible = "qcom,cmd-db"; 662 no-map; 663 }; 664 665 sec_apps_mem: memory@808ff000 { 666 reg = <0x0 0x808ff000 0x0 0x1000>; 667 no-map; 668 }; 669 670 smem_mem: memory@80900000 { 671 reg = <0x0 0x80900000 0x0 0x200000>; 672 no-map; 673 }; 674 675 tz_mem: memory@80b00000 { 676 reg = <0x0 0x80b00000 0x0 0x3900000>; 677 no-map; 678 }; 679 680 ipa_fw_mem: memory@8b700000 { 681 reg = <0 0x8b700000 0 0x10000>; 682 no-map; 683 }; 684 685 rmtfs_mem: memory@94600000 { 686 compatible = "qcom,rmtfs-mem"; 687 reg = <0x0 0x94600000 0x0 0x200000>; 688 no-map; 689 690 qcom,client-id = <1>; 691 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 692 }; 693 }; 694 695 smem { 696 compatible = "qcom,smem"; 697 memory-region = <&smem_mem>; 698 hwlocks = <&tcsr_mutex 3>; 699 }; 700 701 smp2p-cdsp { 702 compatible = "qcom,smp2p"; 703 qcom,smem = <94>, <432>; 704 705 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 706 707 mboxes = <&apss_shared 6>; 708 709 qcom,local-pid = <0>; 710 qcom,remote-pid = <5>; 711 712 cdsp_smp2p_out: master-kernel { 713 qcom,entry-name = "master-kernel"; 714 #qcom,smem-state-cells = <1>; 715 }; 716 717 cdsp_smp2p_in: slave-kernel { 718 qcom,entry-name = "slave-kernel"; 719 720 interrupt-controller; 721 #interrupt-cells = <2>; 722 }; 723 }; 724 725 smp2p-lpass { 726 compatible = "qcom,smp2p"; 727 qcom,smem = <443>, <429>; 728 729 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 730 731 mboxes = <&apss_shared 10>; 732 733 qcom,local-pid = <0>; 734 qcom,remote-pid = <2>; 735 736 adsp_smp2p_out: master-kernel { 737 qcom,entry-name = "master-kernel"; 738 #qcom,smem-state-cells = <1>; 739 }; 740 741 adsp_smp2p_in: slave-kernel { 742 qcom,entry-name = "slave-kernel"; 743 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 }; 748 749 smp2p-mpss { 750 compatible = "qcom,smp2p"; 751 qcom,smem = <435>, <428>; 752 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 753 mboxes = <&apss_shared 14>; 754 qcom,local-pid = <0>; 755 qcom,remote-pid = <1>; 756 757 modem_smp2p_out: master-kernel { 758 qcom,entry-name = "master-kernel"; 759 #qcom,smem-state-cells = <1>; 760 }; 761 762 modem_smp2p_in: slave-kernel { 763 qcom,entry-name = "slave-kernel"; 764 interrupt-controller; 765 #interrupt-cells = <2>; 766 }; 767 768 ipa_smp2p_out: ipa-ap-to-modem { 769 qcom,entry-name = "ipa"; 770 #qcom,smem-state-cells = <1>; 771 }; 772 773 ipa_smp2p_in: ipa-modem-to-ap { 774 qcom,entry-name = "ipa"; 775 interrupt-controller; 776 #interrupt-cells = <2>; 777 }; 778 }; 779 780 soc: soc@0 { 781 #address-cells = <2>; 782 #size-cells = <2>; 783 ranges = <0 0 0 0 0x10 0>; 784 dma-ranges = <0 0 0 0 0x10 0>; 785 compatible = "simple-bus"; 786 787 gcc: clock-controller@100000 { 788 compatible = "qcom,gcc-sc7180"; 789 reg = <0 0x00100000 0 0x1f0000>; 790 clocks = <&rpmhcc RPMH_CXO_CLK>, 791 <&rpmhcc RPMH_CXO_CLK_A>, 792 <&sleep_clk>; 793 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 794 #clock-cells = <1>; 795 #reset-cells = <1>; 796 #power-domain-cells = <1>; 797 power-domains = <&rpmhpd SC7180_CX>; 798 }; 799 800 qfprom: efuse@784000 { 801 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 802 reg = <0 0x00784000 0 0x7a0>, 803 <0 0x00780000 0 0x7a0>, 804 <0 0x00782000 0 0x100>, 805 <0 0x00786000 0 0x1fff>; 806 807 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 808 clock-names = "core"; 809 #address-cells = <1>; 810 #size-cells = <1>; 811 812 qusb2p_hstx_trim: hstx-trim-primary@25b { 813 reg = <0x25b 0x1>; 814 bits = <1 3>; 815 }; 816 817 gpu_speed_bin: gpu-speed-bin@1d2 { 818 reg = <0x1d2 0x2>; 819 bits = <5 8>; 820 }; 821 }; 822 823 sdhc_1: mmc@7c4000 { 824 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 825 reg = <0 0x007c4000 0 0x1000>, 826 <0 0x007c5000 0 0x1000>; 827 reg-names = "hc", "cqhci"; 828 829 iommus = <&apps_smmu 0x60 0x0>; 830 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 832 interrupt-names = "hc_irq", "pwr_irq"; 833 834 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 835 <&gcc GCC_SDCC1_APPS_CLK>, 836 <&rpmhcc RPMH_CXO_CLK>; 837 clock-names = "iface", "core", "xo"; 838 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 839 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 840 interconnect-names = "sdhc-ddr","cpu-sdhc"; 841 power-domains = <&rpmhpd SC7180_CX>; 842 operating-points-v2 = <&sdhc1_opp_table>; 843 844 bus-width = <8>; 845 non-removable; 846 supports-cqe; 847 848 mmc-ddr-1_8v; 849 mmc-hs200-1_8v; 850 mmc-hs400-1_8v; 851 mmc-hs400-enhanced-strobe; 852 853 status = "disabled"; 854 855 sdhc1_opp_table: opp-table { 856 compatible = "operating-points-v2"; 857 858 opp-100000000 { 859 opp-hz = /bits/ 64 <100000000>; 860 required-opps = <&rpmhpd_opp_low_svs>; 861 opp-peak-kBps = <1800000 600000>; 862 opp-avg-kBps = <100000 0>; 863 }; 864 865 opp-384000000 { 866 opp-hz = /bits/ 64 <384000000>; 867 required-opps = <&rpmhpd_opp_nom>; 868 opp-peak-kBps = <5400000 1600000>; 869 opp-avg-kBps = <390000 0>; 870 }; 871 }; 872 }; 873 874 qupv3_id_0: geniqup@8c0000 { 875 compatible = "qcom,geni-se-qup"; 876 reg = <0 0x008c0000 0 0x6000>; 877 clock-names = "m-ahb", "s-ahb"; 878 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 879 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 880 #address-cells = <2>; 881 #size-cells = <2>; 882 ranges; 883 iommus = <&apps_smmu 0x43 0x0>; 884 status = "disabled"; 885 886 i2c0: i2c@880000 { 887 compatible = "qcom,geni-i2c"; 888 reg = <0 0x00880000 0 0x4000>; 889 clock-names = "se"; 890 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&qup_i2c0_default>; 893 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 897 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 898 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 899 interconnect-names = "qup-core", "qup-config", 900 "qup-memory"; 901 power-domains = <&rpmhpd SC7180_CX>; 902 required-opps = <&rpmhpd_opp_low_svs>; 903 status = "disabled"; 904 }; 905 906 spi0: spi@880000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0 0x00880000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>; 913 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 power-domains = <&rpmhpd SC7180_CX>; 917 operating-points-v2 = <&qup_opp_table>; 918 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 919 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 920 interconnect-names = "qup-core", "qup-config"; 921 status = "disabled"; 922 }; 923 924 uart0: serial@880000 { 925 compatible = "qcom,geni-uart"; 926 reg = <0 0x00880000 0 0x4000>; 927 clock-names = "se"; 928 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 929 pinctrl-names = "default"; 930 pinctrl-0 = <&qup_uart0_default>; 931 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 932 power-domains = <&rpmhpd SC7180_CX>; 933 operating-points-v2 = <&qup_opp_table>; 934 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 935 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 936 interconnect-names = "qup-core", "qup-config"; 937 status = "disabled"; 938 }; 939 940 i2c1: i2c@884000 { 941 compatible = "qcom,geni-i2c"; 942 reg = <0 0x00884000 0 0x4000>; 943 clock-names = "se"; 944 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 945 pinctrl-names = "default"; 946 pinctrl-0 = <&qup_i2c1_default>; 947 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 951 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 952 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 953 interconnect-names = "qup-core", "qup-config", 954 "qup-memory"; 955 power-domains = <&rpmhpd SC7180_CX>; 956 required-opps = <&rpmhpd_opp_low_svs>; 957 status = "disabled"; 958 }; 959 960 spi1: spi@884000 { 961 compatible = "qcom,geni-spi"; 962 reg = <0 0x00884000 0 0x4000>; 963 clock-names = "se"; 964 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>; 967 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 power-domains = <&rpmhpd SC7180_CX>; 971 operating-points-v2 = <&qup_opp_table>; 972 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 974 interconnect-names = "qup-core", "qup-config"; 975 status = "disabled"; 976 }; 977 978 uart1: serial@884000 { 979 compatible = "qcom,geni-uart"; 980 reg = <0 0x00884000 0 0x4000>; 981 clock-names = "se"; 982 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 983 pinctrl-names = "default"; 984 pinctrl-0 = <&qup_uart1_default>; 985 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 986 power-domains = <&rpmhpd SC7180_CX>; 987 operating-points-v2 = <&qup_opp_table>; 988 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 989 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 990 interconnect-names = "qup-core", "qup-config"; 991 status = "disabled"; 992 }; 993 994 i2c2: i2c@888000 { 995 compatible = "qcom,geni-i2c"; 996 reg = <0 0x00888000 0 0x4000>; 997 clock-names = "se"; 998 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_i2c2_default>; 1001 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1005 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1006 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1007 interconnect-names = "qup-core", "qup-config", 1008 "qup-memory"; 1009 power-domains = <&rpmhpd SC7180_CX>; 1010 required-opps = <&rpmhpd_opp_low_svs>; 1011 status = "disabled"; 1012 }; 1013 1014 uart2: serial@888000 { 1015 compatible = "qcom,geni-uart"; 1016 reg = <0 0x00888000 0 0x4000>; 1017 clock-names = "se"; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_uart2_default>; 1021 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1022 power-domains = <&rpmhpd SC7180_CX>; 1023 operating-points-v2 = <&qup_opp_table>; 1024 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1025 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1026 interconnect-names = "qup-core", "qup-config"; 1027 status = "disabled"; 1028 }; 1029 1030 i2c3: i2c@88c000 { 1031 compatible = "qcom,geni-i2c"; 1032 reg = <0 0x0088c000 0 0x4000>; 1033 clock-names = "se"; 1034 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1035 pinctrl-names = "default"; 1036 pinctrl-0 = <&qup_i2c3_default>; 1037 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1041 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1042 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1043 interconnect-names = "qup-core", "qup-config", 1044 "qup-memory"; 1045 power-domains = <&rpmhpd SC7180_CX>; 1046 required-opps = <&rpmhpd_opp_low_svs>; 1047 status = "disabled"; 1048 }; 1049 1050 spi3: spi@88c000 { 1051 compatible = "qcom,geni-spi"; 1052 reg = <0 0x0088c000 0 0x4000>; 1053 clock-names = "se"; 1054 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1055 pinctrl-names = "default"; 1056 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>; 1057 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 power-domains = <&rpmhpd SC7180_CX>; 1061 operating-points-v2 = <&qup_opp_table>; 1062 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1063 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1064 interconnect-names = "qup-core", "qup-config"; 1065 status = "disabled"; 1066 }; 1067 1068 uart3: serial@88c000 { 1069 compatible = "qcom,geni-uart"; 1070 reg = <0 0x0088c000 0 0x4000>; 1071 clock-names = "se"; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1073 pinctrl-names = "default"; 1074 pinctrl-0 = <&qup_uart3_default>; 1075 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1076 power-domains = <&rpmhpd SC7180_CX>; 1077 operating-points-v2 = <&qup_opp_table>; 1078 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1079 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1080 interconnect-names = "qup-core", "qup-config"; 1081 status = "disabled"; 1082 }; 1083 1084 i2c4: i2c@890000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0 0x00890000 0 0x4000>; 1087 clock-names = "se"; 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&qup_i2c4_default>; 1091 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1095 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1096 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1097 interconnect-names = "qup-core", "qup-config", 1098 "qup-memory"; 1099 power-domains = <&rpmhpd SC7180_CX>; 1100 required-opps = <&rpmhpd_opp_low_svs>; 1101 status = "disabled"; 1102 }; 1103 1104 uart4: serial@890000 { 1105 compatible = "qcom,geni-uart"; 1106 reg = <0 0x00890000 0 0x4000>; 1107 clock-names = "se"; 1108 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1109 pinctrl-names = "default"; 1110 pinctrl-0 = <&qup_uart4_default>; 1111 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1112 power-domains = <&rpmhpd SC7180_CX>; 1113 operating-points-v2 = <&qup_opp_table>; 1114 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1115 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1116 interconnect-names = "qup-core", "qup-config"; 1117 status = "disabled"; 1118 }; 1119 1120 i2c5: i2c@894000 { 1121 compatible = "qcom,geni-i2c"; 1122 reg = <0 0x00894000 0 0x4000>; 1123 clock-names = "se"; 1124 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1125 pinctrl-names = "default"; 1126 pinctrl-0 = <&qup_i2c5_default>; 1127 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1131 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1132 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1133 interconnect-names = "qup-core", "qup-config", 1134 "qup-memory"; 1135 power-domains = <&rpmhpd SC7180_CX>; 1136 required-opps = <&rpmhpd_opp_low_svs>; 1137 status = "disabled"; 1138 }; 1139 1140 spi5: spi@894000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0 0x00894000 0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1145 pinctrl-names = "default"; 1146 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>; 1147 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 power-domains = <&rpmhpd SC7180_CX>; 1151 operating-points-v2 = <&qup_opp_table>; 1152 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1153 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1154 interconnect-names = "qup-core", "qup-config"; 1155 status = "disabled"; 1156 }; 1157 1158 uart5: serial@894000 { 1159 compatible = "qcom,geni-uart"; 1160 reg = <0 0x00894000 0 0x4000>; 1161 clock-names = "se"; 1162 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_uart5_default>; 1165 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1166 power-domains = <&rpmhpd SC7180_CX>; 1167 operating-points-v2 = <&qup_opp_table>; 1168 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1169 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1170 interconnect-names = "qup-core", "qup-config"; 1171 status = "disabled"; 1172 }; 1173 }; 1174 1175 qupv3_id_1: geniqup@ac0000 { 1176 compatible = "qcom,geni-se-qup"; 1177 reg = <0 0x00ac0000 0 0x6000>; 1178 clock-names = "m-ahb", "s-ahb"; 1179 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1180 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1181 #address-cells = <2>; 1182 #size-cells = <2>; 1183 ranges; 1184 iommus = <&apps_smmu 0x4c3 0x0>; 1185 status = "disabled"; 1186 1187 i2c6: i2c@a80000 { 1188 compatible = "qcom,geni-i2c"; 1189 reg = <0 0x00a80000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_i2c6_default>; 1194 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1198 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1199 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1200 interconnect-names = "qup-core", "qup-config", 1201 "qup-memory"; 1202 power-domains = <&rpmhpd SC7180_CX>; 1203 required-opps = <&rpmhpd_opp_low_svs>; 1204 status = "disabled"; 1205 }; 1206 1207 spi6: spi@a80000 { 1208 compatible = "qcom,geni-spi"; 1209 reg = <0 0x00a80000 0 0x4000>; 1210 clock-names = "se"; 1211 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>; 1214 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 power-domains = <&rpmhpd SC7180_CX>; 1218 operating-points-v2 = <&qup_opp_table>; 1219 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1220 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1221 interconnect-names = "qup-core", "qup-config"; 1222 status = "disabled"; 1223 }; 1224 1225 uart6: serial@a80000 { 1226 compatible = "qcom,geni-uart"; 1227 reg = <0 0x00a80000 0 0x4000>; 1228 clock-names = "se"; 1229 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1230 pinctrl-names = "default"; 1231 pinctrl-0 = <&qup_uart6_default>; 1232 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1233 power-domains = <&rpmhpd SC7180_CX>; 1234 operating-points-v2 = <&qup_opp_table>; 1235 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1236 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1237 interconnect-names = "qup-core", "qup-config"; 1238 status = "disabled"; 1239 }; 1240 1241 i2c7: i2c@a84000 { 1242 compatible = "qcom,geni-i2c"; 1243 reg = <0 0x00a84000 0 0x4000>; 1244 clock-names = "se"; 1245 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1246 pinctrl-names = "default"; 1247 pinctrl-0 = <&qup_i2c7_default>; 1248 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1252 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1253 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1254 interconnect-names = "qup-core", "qup-config", 1255 "qup-memory"; 1256 power-domains = <&rpmhpd SC7180_CX>; 1257 required-opps = <&rpmhpd_opp_low_svs>; 1258 status = "disabled"; 1259 }; 1260 1261 uart7: serial@a84000 { 1262 compatible = "qcom,geni-uart"; 1263 reg = <0 0x00a84000 0 0x4000>; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&qup_uart7_default>; 1268 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1269 power-domains = <&rpmhpd SC7180_CX>; 1270 operating-points-v2 = <&qup_opp_table>; 1271 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1272 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1273 interconnect-names = "qup-core", "qup-config"; 1274 status = "disabled"; 1275 }; 1276 1277 i2c8: i2c@a88000 { 1278 compatible = "qcom,geni-i2c"; 1279 reg = <0 0x00a88000 0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_i2c8_default>; 1284 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1288 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1289 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1290 interconnect-names = "qup-core", "qup-config", 1291 "qup-memory"; 1292 power-domains = <&rpmhpd SC7180_CX>; 1293 required-opps = <&rpmhpd_opp_low_svs>; 1294 status = "disabled"; 1295 }; 1296 1297 spi8: spi@a88000 { 1298 compatible = "qcom,geni-spi"; 1299 reg = <0 0x00a88000 0 0x4000>; 1300 clock-names = "se"; 1301 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1302 pinctrl-names = "default"; 1303 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>; 1304 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 power-domains = <&rpmhpd SC7180_CX>; 1308 operating-points-v2 = <&qup_opp_table>; 1309 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1310 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1311 interconnect-names = "qup-core", "qup-config"; 1312 status = "disabled"; 1313 }; 1314 1315 uart8: serial@a88000 { 1316 compatible = "qcom,geni-debug-uart"; 1317 reg = <0 0x00a88000 0 0x4000>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_uart8_default>; 1322 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1323 power-domains = <&rpmhpd SC7180_CX>; 1324 operating-points-v2 = <&qup_opp_table>; 1325 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1326 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1327 interconnect-names = "qup-core", "qup-config"; 1328 status = "disabled"; 1329 }; 1330 1331 i2c9: i2c@a8c000 { 1332 compatible = "qcom,geni-i2c"; 1333 reg = <0 0x00a8c000 0 0x4000>; 1334 clock-names = "se"; 1335 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&qup_i2c9_default>; 1338 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1342 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1343 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1344 interconnect-names = "qup-core", "qup-config", 1345 "qup-memory"; 1346 power-domains = <&rpmhpd SC7180_CX>; 1347 required-opps = <&rpmhpd_opp_low_svs>; 1348 status = "disabled"; 1349 }; 1350 1351 uart9: serial@a8c000 { 1352 compatible = "qcom,geni-uart"; 1353 reg = <0 0x00a8c000 0 0x4000>; 1354 clock-names = "se"; 1355 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1356 pinctrl-names = "default"; 1357 pinctrl-0 = <&qup_uart9_default>; 1358 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1359 power-domains = <&rpmhpd SC7180_CX>; 1360 operating-points-v2 = <&qup_opp_table>; 1361 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1362 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1363 interconnect-names = "qup-core", "qup-config"; 1364 status = "disabled"; 1365 }; 1366 1367 i2c10: i2c@a90000 { 1368 compatible = "qcom,geni-i2c"; 1369 reg = <0 0x00a90000 0 0x4000>; 1370 clock-names = "se"; 1371 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&qup_i2c10_default>; 1374 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1378 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1379 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1380 interconnect-names = "qup-core", "qup-config", 1381 "qup-memory"; 1382 power-domains = <&rpmhpd SC7180_CX>; 1383 required-opps = <&rpmhpd_opp_low_svs>; 1384 status = "disabled"; 1385 }; 1386 1387 spi10: spi@a90000 { 1388 compatible = "qcom,geni-spi"; 1389 reg = <0 0x00a90000 0 0x4000>; 1390 clock-names = "se"; 1391 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1392 pinctrl-names = "default"; 1393 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>; 1394 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1395 #address-cells = <1>; 1396 #size-cells = <0>; 1397 power-domains = <&rpmhpd SC7180_CX>; 1398 operating-points-v2 = <&qup_opp_table>; 1399 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1400 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1401 interconnect-names = "qup-core", "qup-config"; 1402 status = "disabled"; 1403 }; 1404 1405 uart10: serial@a90000 { 1406 compatible = "qcom,geni-uart"; 1407 reg = <0 0x00a90000 0 0x4000>; 1408 clock-names = "se"; 1409 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1410 pinctrl-names = "default"; 1411 pinctrl-0 = <&qup_uart10_default>; 1412 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1413 power-domains = <&rpmhpd SC7180_CX>; 1414 operating-points-v2 = <&qup_opp_table>; 1415 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1416 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1417 interconnect-names = "qup-core", "qup-config"; 1418 status = "disabled"; 1419 }; 1420 1421 i2c11: i2c@a94000 { 1422 compatible = "qcom,geni-i2c"; 1423 reg = <0 0x00a94000 0 0x4000>; 1424 clock-names = "se"; 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1426 pinctrl-names = "default"; 1427 pinctrl-0 = <&qup_i2c11_default>; 1428 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1432 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1433 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1434 interconnect-names = "qup-core", "qup-config", 1435 "qup-memory"; 1436 power-domains = <&rpmhpd SC7180_CX>; 1437 required-opps = <&rpmhpd_opp_low_svs>; 1438 status = "disabled"; 1439 }; 1440 1441 spi11: spi@a94000 { 1442 compatible = "qcom,geni-spi"; 1443 reg = <0 0x00a94000 0 0x4000>; 1444 clock-names = "se"; 1445 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1446 pinctrl-names = "default"; 1447 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>; 1448 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 power-domains = <&rpmhpd SC7180_CX>; 1452 operating-points-v2 = <&qup_opp_table>; 1453 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1454 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1455 interconnect-names = "qup-core", "qup-config"; 1456 status = "disabled"; 1457 }; 1458 1459 uart11: serial@a94000 { 1460 compatible = "qcom,geni-uart"; 1461 reg = <0 0x00a94000 0 0x4000>; 1462 clock-names = "se"; 1463 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1464 pinctrl-names = "default"; 1465 pinctrl-0 = <&qup_uart11_default>; 1466 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1467 power-domains = <&rpmhpd SC7180_CX>; 1468 operating-points-v2 = <&qup_opp_table>; 1469 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1470 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1471 interconnect-names = "qup-core", "qup-config"; 1472 status = "disabled"; 1473 }; 1474 }; 1475 1476 config_noc: interconnect@1500000 { 1477 compatible = "qcom,sc7180-config-noc"; 1478 reg = <0 0x01500000 0 0x28000>; 1479 #interconnect-cells = <2>; 1480 qcom,bcm-voters = <&apps_bcm_voter>; 1481 }; 1482 1483 system_noc: interconnect@1620000 { 1484 compatible = "qcom,sc7180-system-noc"; 1485 reg = <0 0x01620000 0 0x17080>; 1486 #interconnect-cells = <2>; 1487 qcom,bcm-voters = <&apps_bcm_voter>; 1488 }; 1489 1490 mc_virt: interconnect@1638000 { 1491 compatible = "qcom,sc7180-mc-virt"; 1492 reg = <0 0x01638000 0 0x1000>; 1493 #interconnect-cells = <2>; 1494 qcom,bcm-voters = <&apps_bcm_voter>; 1495 }; 1496 1497 qup_virt: interconnect@1650000 { 1498 compatible = "qcom,sc7180-qup-virt"; 1499 reg = <0 0x01650000 0 0x1000>; 1500 #interconnect-cells = <2>; 1501 qcom,bcm-voters = <&apps_bcm_voter>; 1502 }; 1503 1504 aggre1_noc: interconnect@16e0000 { 1505 compatible = "qcom,sc7180-aggre1-noc"; 1506 reg = <0 0x016e0000 0 0x15080>; 1507 #interconnect-cells = <2>; 1508 qcom,bcm-voters = <&apps_bcm_voter>; 1509 }; 1510 1511 aggre2_noc: interconnect@1705000 { 1512 compatible = "qcom,sc7180-aggre2-noc"; 1513 reg = <0 0x01705000 0 0x9000>; 1514 #interconnect-cells = <2>; 1515 qcom,bcm-voters = <&apps_bcm_voter>; 1516 }; 1517 1518 compute_noc: interconnect@170e000 { 1519 compatible = "qcom,sc7180-compute-noc"; 1520 reg = <0 0x0170e000 0 0x6000>; 1521 #interconnect-cells = <2>; 1522 qcom,bcm-voters = <&apps_bcm_voter>; 1523 }; 1524 1525 mmss_noc: interconnect@1740000 { 1526 compatible = "qcom,sc7180-mmss-noc"; 1527 reg = <0 0x01740000 0 0x1c100>; 1528 #interconnect-cells = <2>; 1529 qcom,bcm-voters = <&apps_bcm_voter>; 1530 }; 1531 1532 ufs_mem_hc: ufshc@1d84000 { 1533 compatible = "qcom,sc7180-ufshc", "qcom,ufshc", 1534 "jedec,ufs-2.0"; 1535 reg = <0 0x01d84000 0 0x3000>; 1536 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1537 phys = <&ufs_mem_phy>; 1538 phy-names = "ufsphy"; 1539 lanes-per-direction = <1>; 1540 #reset-cells = <1>; 1541 resets = <&gcc GCC_UFS_PHY_BCR>; 1542 reset-names = "rst"; 1543 1544 power-domains = <&gcc UFS_PHY_GDSC>; 1545 1546 iommus = <&apps_smmu 0xa0 0x0>; 1547 1548 clock-names = "core_clk", 1549 "bus_aggr_clk", 1550 "iface_clk", 1551 "core_clk_unipro", 1552 "ref_clk", 1553 "tx_lane0_sync_clk", 1554 "rx_lane0_sync_clk"; 1555 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1556 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1557 <&gcc GCC_UFS_PHY_AHB_CLK>, 1558 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1559 <&rpmhcc RPMH_CXO_CLK>, 1560 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1561 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; 1562 freq-table-hz = <50000000 200000000>, 1563 <0 0>, 1564 <0 0>, 1565 <37500000 150000000>, 1566 <0 0>, 1567 <0 0>, 1568 <0 0>; 1569 1570 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1571 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1572 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1573 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 1574 interconnect-names = "ufs-ddr", "cpu-ufs"; 1575 1576 qcom,ice = <&ice>; 1577 1578 status = "disabled"; 1579 }; 1580 1581 ufs_mem_phy: phy@1d87000 { 1582 compatible = "qcom,sc7180-qmp-ufs-phy"; 1583 reg = <0 0x01d87000 0 0x1000>; 1584 clocks = <&rpmhcc RPMH_CXO_CLK>, 1585 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1586 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1587 clock-names = "ref", 1588 "ref_aux", 1589 "qref"; 1590 power-domains = <&gcc UFS_PHY_GDSC>; 1591 resets = <&ufs_mem_hc 0>; 1592 reset-names = "ufsphy"; 1593 #phy-cells = <0>; 1594 status = "disabled"; 1595 }; 1596 1597 ice: crypto@1d90000 { 1598 compatible = "qcom,sc7180-inline-crypto-engine", 1599 "qcom,inline-crypto-engine"; 1600 reg = <0 0x01d90000 0 0x8000>; 1601 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1602 }; 1603 1604 ipa: ipa@1e40000 { 1605 compatible = "qcom,sc7180-ipa"; 1606 1607 iommus = <&apps_smmu 0x440 0x0>, 1608 <&apps_smmu 0x442 0x0>; 1609 reg = <0 0x01e40000 0 0x7000>, 1610 <0 0x01e47000 0 0x2000>, 1611 <0 0x01e04000 0 0x2c000>; 1612 reg-names = "ipa-reg", 1613 "ipa-shared", 1614 "gsi"; 1615 1616 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1617 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1618 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1619 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1620 interrupt-names = "ipa", 1621 "gsi", 1622 "ipa-clock-query", 1623 "ipa-setup-ready"; 1624 1625 clocks = <&rpmhcc RPMH_IPA_CLK>; 1626 clock-names = "core"; 1627 1628 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1629 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1630 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1631 interconnect-names = "memory", 1632 "imem", 1633 "config"; 1634 1635 qcom,qmp = <&aoss_qmp>; 1636 1637 qcom,smem-states = <&ipa_smp2p_out 0>, 1638 <&ipa_smp2p_out 1>; 1639 qcom,smem-state-names = "ipa-clock-enabled-valid", 1640 "ipa-clock-enabled"; 1641 1642 status = "disabled"; 1643 }; 1644 1645 tcsr_mutex: hwlock@1f40000 { 1646 compatible = "qcom,tcsr-mutex"; 1647 reg = <0 0x01f40000 0 0x20000>; 1648 #hwlock-cells = <1>; 1649 }; 1650 1651 tcsr_regs_1: syscon@1f60000 { 1652 compatible = "qcom,sc7180-tcsr", "syscon"; 1653 reg = <0 0x01f60000 0 0x20000>; 1654 }; 1655 1656 tcsr_regs_2: syscon@1fc0000 { 1657 compatible = "qcom,sc7180-tcsr", "syscon"; 1658 reg = <0 0x01fc0000 0 0x40000>; 1659 }; 1660 1661 tlmm: pinctrl@3500000 { 1662 compatible = "qcom,sc7180-pinctrl"; 1663 reg = <0 0x03500000 0 0x300000>, 1664 <0 0x03900000 0 0x300000>, 1665 <0 0x03d00000 0 0x300000>; 1666 reg-names = "west", "north", "south"; 1667 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1668 gpio-controller; 1669 #gpio-cells = <2>; 1670 interrupt-controller; 1671 #interrupt-cells = <2>; 1672 gpio-ranges = <&tlmm 0 0 120>; 1673 wakeup-parent = <&pdc>; 1674 1675 dp_hot_plug_det: dp-hot-plug-det-state { 1676 pins = "gpio117"; 1677 function = "dp_hot"; 1678 }; 1679 1680 qspi_clk: qspi-clk-state { 1681 pins = "gpio63"; 1682 function = "qspi_clk"; 1683 }; 1684 1685 qspi_cs0: qspi-cs0-state { 1686 pins = "gpio68"; 1687 function = "qspi_cs"; 1688 }; 1689 1690 qspi_cs1: qspi-cs1-state { 1691 pins = "gpio72"; 1692 function = "qspi_cs"; 1693 }; 1694 1695 qspi_data0: qspi-data0-state { 1696 pins = "gpio64"; 1697 function = "qspi_data"; 1698 }; 1699 1700 qspi_data1: qspi-data1-state { 1701 pins = "gpio65"; 1702 function = "qspi_data"; 1703 }; 1704 1705 qspi_data23: qspi-data23-state { 1706 pins = "gpio66", "gpio67"; 1707 function = "qspi_data"; 1708 }; 1709 1710 qup_i2c0_default: qup-i2c0-default-state { 1711 pins = "gpio34", "gpio35"; 1712 function = "qup00"; 1713 }; 1714 1715 qup_i2c1_default: qup-i2c1-default-state { 1716 pins = "gpio0", "gpio1"; 1717 function = "qup01"; 1718 }; 1719 1720 qup_i2c2_default: qup-i2c2-default-state { 1721 pins = "gpio15", "gpio16"; 1722 function = "qup02_i2c"; 1723 }; 1724 1725 qup_i2c3_default: qup-i2c3-default-state { 1726 pins = "gpio38", "gpio39"; 1727 function = "qup03"; 1728 }; 1729 1730 qup_i2c4_default: qup-i2c4-default-state { 1731 pins = "gpio115", "gpio116"; 1732 function = "qup04_i2c"; 1733 }; 1734 1735 qup_i2c5_default: qup-i2c5-default-state { 1736 pins = "gpio25", "gpio26"; 1737 function = "qup05"; 1738 }; 1739 1740 qup_i2c6_default: qup-i2c6-default-state { 1741 pins = "gpio59", "gpio60"; 1742 function = "qup10"; 1743 }; 1744 1745 qup_i2c7_default: qup-i2c7-default-state { 1746 pins = "gpio6", "gpio7"; 1747 function = "qup11_i2c"; 1748 }; 1749 1750 qup_i2c8_default: qup-i2c8-default-state { 1751 pins = "gpio42", "gpio43"; 1752 function = "qup12"; 1753 }; 1754 1755 qup_i2c9_default: qup-i2c9-default-state { 1756 pins = "gpio46", "gpio47"; 1757 function = "qup13_i2c"; 1758 }; 1759 1760 qup_i2c10_default: qup-i2c10-default-state { 1761 pins = "gpio86", "gpio87"; 1762 function = "qup14"; 1763 }; 1764 1765 qup_i2c11_default: qup-i2c11-default-state { 1766 pins = "gpio53", "gpio54"; 1767 function = "qup15"; 1768 }; 1769 1770 qup_spi0_spi: qup-spi0-spi-state { 1771 pins = "gpio34", "gpio35", "gpio36"; 1772 function = "qup00"; 1773 }; 1774 1775 qup_spi0_cs: qup-spi0-cs-state { 1776 pins = "gpio37"; 1777 function = "qup00"; 1778 }; 1779 1780 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 1781 pins = "gpio37"; 1782 function = "gpio"; 1783 }; 1784 1785 qup_spi1_spi: qup-spi1-spi-state { 1786 pins = "gpio0", "gpio1", "gpio2"; 1787 function = "qup01"; 1788 }; 1789 1790 qup_spi1_cs: qup-spi1-cs-state { 1791 pins = "gpio3"; 1792 function = "qup01"; 1793 }; 1794 1795 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 1796 pins = "gpio3"; 1797 function = "gpio"; 1798 }; 1799 1800 qup_spi3_spi: qup-spi3-spi-state { 1801 pins = "gpio38", "gpio39", "gpio40"; 1802 function = "qup03"; 1803 }; 1804 1805 qup_spi3_cs: qup-spi3-cs-state { 1806 pins = "gpio41"; 1807 function = "qup03"; 1808 }; 1809 1810 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 1811 pins = "gpio41"; 1812 function = "gpio"; 1813 }; 1814 1815 qup_spi5_spi: qup-spi5-spi-state { 1816 pins = "gpio25", "gpio26", "gpio27"; 1817 function = "qup05"; 1818 }; 1819 1820 qup_spi5_cs: qup-spi5-cs-state { 1821 pins = "gpio28"; 1822 function = "qup05"; 1823 }; 1824 1825 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 1826 pins = "gpio28"; 1827 function = "gpio"; 1828 }; 1829 1830 qup_spi6_spi: qup-spi6-spi-state { 1831 pins = "gpio59", "gpio60", "gpio61"; 1832 function = "qup10"; 1833 }; 1834 1835 qup_spi6_cs: qup-spi6-cs-state { 1836 pins = "gpio62"; 1837 function = "qup10"; 1838 }; 1839 1840 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1841 pins = "gpio62"; 1842 function = "gpio"; 1843 }; 1844 1845 qup_spi8_spi: qup-spi8-spi-state { 1846 pins = "gpio42", "gpio43", "gpio44"; 1847 function = "qup12"; 1848 }; 1849 1850 qup_spi8_cs: qup-spi8-cs-state { 1851 pins = "gpio45"; 1852 function = "qup12"; 1853 }; 1854 1855 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 1856 pins = "gpio45"; 1857 function = "gpio"; 1858 }; 1859 1860 qup_spi10_spi: qup-spi10-spi-state { 1861 pins = "gpio86", "gpio87", "gpio88"; 1862 function = "qup14"; 1863 }; 1864 1865 qup_spi10_cs: qup-spi10-cs-state { 1866 pins = "gpio89"; 1867 function = "qup14"; 1868 }; 1869 1870 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 1871 pins = "gpio89"; 1872 function = "gpio"; 1873 }; 1874 1875 qup_spi11_spi: qup-spi11-spi-state { 1876 pins = "gpio53", "gpio54", "gpio55"; 1877 function = "qup15"; 1878 }; 1879 1880 qup_spi11_cs: qup-spi11-cs-state { 1881 pins = "gpio56"; 1882 function = "qup15"; 1883 }; 1884 1885 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 1886 pins = "gpio56"; 1887 function = "gpio"; 1888 }; 1889 1890 qup_uart0_default: qup-uart0-default-state { 1891 qup_uart0_cts: cts-pins { 1892 pins = "gpio34"; 1893 function = "qup00"; 1894 }; 1895 1896 qup_uart0_rts: rts-pins { 1897 pins = "gpio35"; 1898 function = "qup00"; 1899 }; 1900 1901 qup_uart0_tx: tx-pins { 1902 pins = "gpio36"; 1903 function = "qup00"; 1904 }; 1905 1906 qup_uart0_rx: rx-pins { 1907 pins = "gpio37"; 1908 function = "qup00"; 1909 }; 1910 }; 1911 1912 qup_uart1_default: qup-uart1-default-state { 1913 qup_uart1_cts: cts-pins { 1914 pins = "gpio0"; 1915 function = "qup01"; 1916 }; 1917 1918 qup_uart1_rts: rts-pins { 1919 pins = "gpio1"; 1920 function = "qup01"; 1921 }; 1922 1923 qup_uart1_tx: tx-pins { 1924 pins = "gpio2"; 1925 function = "qup01"; 1926 }; 1927 1928 qup_uart1_rx: rx-pins { 1929 pins = "gpio3"; 1930 function = "qup01"; 1931 }; 1932 }; 1933 1934 qup_uart2_default: qup-uart2-default-state { 1935 qup_uart2_tx: tx-pins { 1936 pins = "gpio15"; 1937 function = "qup02_uart"; 1938 }; 1939 1940 qup_uart2_rx: rx-pins { 1941 pins = "gpio16"; 1942 function = "qup02_uart"; 1943 }; 1944 }; 1945 1946 qup_uart3_default: qup-uart3-default-state { 1947 qup_uart3_cts: cts-pins { 1948 pins = "gpio38"; 1949 function = "qup03"; 1950 }; 1951 1952 qup_uart3_rts: rts-pins { 1953 pins = "gpio39"; 1954 function = "qup03"; 1955 }; 1956 1957 qup_uart3_tx: tx-pins { 1958 pins = "gpio40"; 1959 function = "qup03"; 1960 }; 1961 1962 qup_uart3_rx: rx-pins { 1963 pins = "gpio41"; 1964 function = "qup03"; 1965 }; 1966 }; 1967 1968 qup_uart4_default: qup-uart4-default-state { 1969 qup_uart4_tx: tx-pins { 1970 pins = "gpio115"; 1971 function = "qup04_uart"; 1972 }; 1973 1974 qup_uart4_rx: rx-pins { 1975 pins = "gpio116"; 1976 function = "qup04_uart"; 1977 }; 1978 }; 1979 1980 qup_uart5_default: qup-uart5-default-state { 1981 qup_uart5_cts: cts-pins { 1982 pins = "gpio25"; 1983 function = "qup05"; 1984 }; 1985 1986 qup_uart5_rts: rts-pins { 1987 pins = "gpio26"; 1988 function = "qup05"; 1989 }; 1990 1991 qup_uart5_tx: tx-pins { 1992 pins = "gpio27"; 1993 function = "qup05"; 1994 }; 1995 1996 qup_uart5_rx: rx-pins { 1997 pins = "gpio28"; 1998 function = "qup05"; 1999 }; 2000 }; 2001 2002 qup_uart6_default: qup-uart6-default-state { 2003 qup_uart6_cts: cts-pins { 2004 pins = "gpio59"; 2005 function = "qup10"; 2006 }; 2007 2008 qup_uart6_rts: rts-pins { 2009 pins = "gpio60"; 2010 function = "qup10"; 2011 }; 2012 2013 qup_uart6_tx: tx-pins { 2014 pins = "gpio61"; 2015 function = "qup10"; 2016 }; 2017 2018 qup_uart6_rx: rx-pins { 2019 pins = "gpio62"; 2020 function = "qup10"; 2021 }; 2022 }; 2023 2024 qup_uart7_default: qup-uart7-default-state { 2025 qup_uart7_tx: tx-pins { 2026 pins = "gpio6"; 2027 function = "qup11_uart"; 2028 }; 2029 2030 qup_uart7_rx: rx-pins { 2031 pins = "gpio7"; 2032 function = "qup11_uart"; 2033 }; 2034 }; 2035 2036 qup_uart8_default: qup-uart8-default-state { 2037 qup_uart8_tx: tx-pins { 2038 pins = "gpio44"; 2039 function = "qup12"; 2040 }; 2041 2042 qup_uart8_rx: rx-pins { 2043 pins = "gpio45"; 2044 function = "qup12"; 2045 }; 2046 }; 2047 2048 qup_uart9_default: qup-uart9-default-state { 2049 qup_uart9_tx: tx-pins { 2050 pins = "gpio46"; 2051 function = "qup13_uart"; 2052 }; 2053 2054 qup_uart9_rx: rx-pins { 2055 pins = "gpio47"; 2056 function = "qup13_uart"; 2057 }; 2058 }; 2059 2060 qup_uart10_default: qup-uart10-default-state { 2061 qup_uart10_cts: cts-pins { 2062 pins = "gpio86"; 2063 function = "qup14"; 2064 }; 2065 2066 qup_uart10_rts: rts-pins { 2067 pins = "gpio87"; 2068 function = "qup14"; 2069 }; 2070 2071 qup_uart10_tx: tx-pins { 2072 pins = "gpio88"; 2073 function = "qup14"; 2074 }; 2075 2076 qup_uart10_rx: rx-pins { 2077 pins = "gpio89"; 2078 function = "qup14"; 2079 }; 2080 }; 2081 2082 qup_uart11_default: qup-uart11-default-state { 2083 qup_uart11_cts: cts-pins { 2084 pins = "gpio53"; 2085 function = "qup15"; 2086 }; 2087 2088 qup_uart11_rts: rts-pins { 2089 pins = "gpio54"; 2090 function = "qup15"; 2091 }; 2092 2093 qup_uart11_tx: tx-pins { 2094 pins = "gpio55"; 2095 function = "qup15"; 2096 }; 2097 2098 qup_uart11_rx: rx-pins { 2099 pins = "gpio56"; 2100 function = "qup15"; 2101 }; 2102 }; 2103 2104 sec_mi2s_active: sec-mi2s-active-state { 2105 pins = "gpio49", "gpio50", "gpio51"; 2106 function = "mi2s_1"; 2107 }; 2108 2109 pri_mi2s_active: pri-mi2s-active-state { 2110 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 2111 function = "mi2s_0"; 2112 }; 2113 2114 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state { 2115 pins = "gpio57"; 2116 function = "lpass_ext"; 2117 }; 2118 2119 ter_mi2s_active: ter-mi2s-active-state { 2120 pins = "gpio63", "gpio64", "gpio65", "gpio66"; 2121 function = "mi2s_2"; 2122 }; 2123 }; 2124 2125 remoteproc_mpss: remoteproc@4080000 { 2126 compatible = "qcom,sc7180-mpss-pas"; 2127 reg = <0 0x04080000 0 0x4040>; 2128 2129 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2130 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2131 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2132 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2133 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2134 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2135 interrupt-names = "wdog", "fatal", "ready", "handover", 2136 "stop-ack", "shutdown-ack"; 2137 2138 clocks = <&rpmhcc RPMH_CXO_CLK>; 2139 clock-names = "xo"; 2140 2141 power-domains = <&rpmhpd SC7180_CX>, 2142 <&rpmhpd SC7180_MX>, 2143 <&rpmhpd SC7180_MSS>; 2144 power-domain-names = "cx", "mx", "mss"; 2145 2146 memory-region = <&mpss_mem>; 2147 2148 qcom,qmp = <&aoss_qmp>; 2149 2150 qcom,smem-states = <&modem_smp2p_out 0>; 2151 qcom,smem-state-names = "stop"; 2152 2153 status = "disabled"; 2154 2155 glink-edge { 2156 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2157 label = "modem"; 2158 qcom,remote-pid = <1>; 2159 mboxes = <&apss_shared 12>; 2160 }; 2161 }; 2162 2163 gpu: gpu@5000000 { 2164 compatible = "qcom,adreno-618.0", "qcom,adreno"; 2165 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 2166 <0 0x05061000 0 0x800>; 2167 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 2168 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2169 iommus = <&adreno_smmu 0>; 2170 operating-points-v2 = <&gpu_opp_table>; 2171 qcom,gmu = <&gmu>; 2172 2173 #cooling-cells = <2>; 2174 2175 nvmem-cells = <&gpu_speed_bin>; 2176 nvmem-cell-names = "speed_bin"; 2177 2178 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2179 interconnect-names = "gfx-mem"; 2180 2181 gpu_opp_table: opp-table { 2182 compatible = "operating-points-v2"; 2183 2184 opp-825000000 { 2185 opp-hz = /bits/ 64 <825000000>; 2186 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2187 opp-peak-kBps = <8532000>; 2188 opp-supported-hw = <0x04>; 2189 }; 2190 2191 opp-800000000 { 2192 opp-hz = /bits/ 64 <800000000>; 2193 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2194 opp-peak-kBps = <8532000>; 2195 opp-supported-hw = <0x07>; 2196 }; 2197 2198 opp-650000000 { 2199 opp-hz = /bits/ 64 <650000000>; 2200 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2201 opp-peak-kBps = <7216000>; 2202 opp-supported-hw = <0x07>; 2203 }; 2204 2205 opp-565000000 { 2206 opp-hz = /bits/ 64 <565000000>; 2207 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2208 opp-peak-kBps = <5412000>; 2209 opp-supported-hw = <0x07>; 2210 }; 2211 2212 opp-430000000 { 2213 opp-hz = /bits/ 64 <430000000>; 2214 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2215 opp-peak-kBps = <5412000>; 2216 opp-supported-hw = <0x07>; 2217 }; 2218 2219 opp-355000000 { 2220 opp-hz = /bits/ 64 <355000000>; 2221 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2222 opp-peak-kBps = <3072000>; 2223 opp-supported-hw = <0x07>; 2224 }; 2225 2226 opp-267000000 { 2227 opp-hz = /bits/ 64 <267000000>; 2228 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2229 opp-peak-kBps = <3072000>; 2230 opp-supported-hw = <0x07>; 2231 }; 2232 2233 opp-180000000 { 2234 opp-hz = /bits/ 64 <180000000>; 2235 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2236 opp-peak-kBps = <1804000>; 2237 opp-supported-hw = <0x07>; 2238 }; 2239 }; 2240 }; 2241 2242 adreno_smmu: iommu@5040000 { 2243 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2244 reg = <0 0x05040000 0 0x10000>; 2245 #iommu-cells = <1>; 2246 #global-interrupts = <2>; 2247 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2248 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2249 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2250 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2251 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2252 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2253 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2254 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2255 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2256 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2257 2258 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2259 <&gcc GCC_GPU_CFG_AHB_CLK>; 2260 clock-names = "bus", "iface"; 2261 2262 power-domains = <&gpucc CX_GDSC>; 2263 }; 2264 2265 gmu: gmu@506a000 { 2266 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2267 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2268 <0 0x0b490000 0 0x10000>; 2269 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2270 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2271 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2272 interrupt-names = "hfi", "gmu"; 2273 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2274 <&gpucc GPU_CC_CXO_CLK>, 2275 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2276 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2277 clock-names = "gmu", "cxo", "axi", "memnoc"; 2278 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2279 power-domain-names = "cx", "gx"; 2280 iommus = <&adreno_smmu 5>; 2281 operating-points-v2 = <&gmu_opp_table>; 2282 2283 gmu_opp_table: opp-table { 2284 compatible = "operating-points-v2"; 2285 2286 opp-200000000 { 2287 opp-hz = /bits/ 64 <200000000>; 2288 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2289 }; 2290 }; 2291 }; 2292 2293 gpucc: clock-controller@5090000 { 2294 compatible = "qcom,sc7180-gpucc"; 2295 reg = <0 0x05090000 0 0x9000>; 2296 clocks = <&rpmhcc RPMH_CXO_CLK>, 2297 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2298 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2299 clock-names = "bi_tcxo", 2300 "gcc_gpu_gpll0_clk_src", 2301 "gcc_gpu_gpll0_div_clk_src"; 2302 #clock-cells = <1>; 2303 #reset-cells = <1>; 2304 #power-domain-cells = <1>; 2305 }; 2306 2307 dma@10a2000 { 2308 compatible = "qcom,sc7180-dcc", "qcom,dcc"; 2309 reg = <0x0 0x010a2000 0x0 0x1000>, 2310 <0x0 0x010ae000 0x0 0x2000>; 2311 status = "disabled"; 2312 }; 2313 2314 stm@6002000 { 2315 compatible = "arm,coresight-stm", "arm,primecell"; 2316 reg = <0 0x06002000 0 0x1000>, 2317 <0 0x16280000 0 0x180000>; 2318 reg-names = "stm-base", "stm-stimulus-base"; 2319 2320 clocks = <&aoss_qmp>; 2321 clock-names = "apb_pclk"; 2322 2323 out-ports { 2324 port { 2325 stm_out: endpoint { 2326 remote-endpoint = <&funnel0_in7>; 2327 }; 2328 }; 2329 }; 2330 }; 2331 2332 funnel@6041000 { 2333 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2334 reg = <0 0x06041000 0 0x1000>; 2335 2336 clocks = <&aoss_qmp>; 2337 clock-names = "apb_pclk"; 2338 2339 out-ports { 2340 port { 2341 funnel0_out: endpoint { 2342 remote-endpoint = <&merge_funnel_in0>; 2343 }; 2344 }; 2345 }; 2346 2347 in-ports { 2348 #address-cells = <1>; 2349 #size-cells = <0>; 2350 2351 port@7 { 2352 reg = <7>; 2353 funnel0_in7: endpoint { 2354 remote-endpoint = <&stm_out>; 2355 }; 2356 }; 2357 }; 2358 }; 2359 2360 funnel@6042000 { 2361 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2362 reg = <0 0x06042000 0 0x1000>; 2363 2364 clocks = <&aoss_qmp>; 2365 clock-names = "apb_pclk"; 2366 2367 out-ports { 2368 port { 2369 funnel1_out: endpoint { 2370 remote-endpoint = <&merge_funnel_in1>; 2371 }; 2372 }; 2373 }; 2374 2375 in-ports { 2376 #address-cells = <1>; 2377 #size-cells = <0>; 2378 2379 port@4 { 2380 reg = <4>; 2381 funnel1_in4: endpoint { 2382 remote-endpoint = <&apss_merge_funnel_out>; 2383 }; 2384 }; 2385 }; 2386 }; 2387 2388 funnel@6045000 { 2389 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2390 reg = <0 0x06045000 0 0x1000>; 2391 2392 clocks = <&aoss_qmp>; 2393 clock-names = "apb_pclk"; 2394 2395 out-ports { 2396 port { 2397 merge_funnel_out: endpoint { 2398 remote-endpoint = <&swao_funnel_in>; 2399 }; 2400 }; 2401 }; 2402 2403 in-ports { 2404 #address-cells = <1>; 2405 #size-cells = <0>; 2406 2407 port@0 { 2408 reg = <0>; 2409 merge_funnel_in0: endpoint { 2410 remote-endpoint = <&funnel0_out>; 2411 }; 2412 }; 2413 2414 port@1 { 2415 reg = <1>; 2416 merge_funnel_in1: endpoint { 2417 remote-endpoint = <&funnel1_out>; 2418 }; 2419 }; 2420 }; 2421 }; 2422 2423 replicator@6046000 { 2424 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2425 reg = <0 0x06046000 0 0x1000>; 2426 2427 clocks = <&aoss_qmp>; 2428 clock-names = "apb_pclk"; 2429 2430 out-ports { 2431 port { 2432 replicator_out: endpoint { 2433 remote-endpoint = <&etr_in>; 2434 }; 2435 }; 2436 }; 2437 2438 in-ports { 2439 port { 2440 replicator_in: endpoint { 2441 remote-endpoint = <&swao_replicator_out>; 2442 }; 2443 }; 2444 }; 2445 }; 2446 2447 etr@6048000 { 2448 compatible = "arm,coresight-tmc", "arm,primecell"; 2449 reg = <0 0x06048000 0 0x1000>; 2450 iommus = <&apps_smmu 0x04a0 0x20>; 2451 2452 clocks = <&aoss_qmp>; 2453 clock-names = "apb_pclk"; 2454 arm,scatter-gather; 2455 2456 in-ports { 2457 port { 2458 etr_in: endpoint { 2459 remote-endpoint = <&replicator_out>; 2460 }; 2461 }; 2462 }; 2463 }; 2464 2465 funnel@6b04000 { 2466 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2467 reg = <0 0x06b04000 0 0x1000>; 2468 2469 clocks = <&aoss_qmp>; 2470 clock-names = "apb_pclk"; 2471 2472 out-ports { 2473 port { 2474 swao_funnel_out: endpoint { 2475 remote-endpoint = <&etf_in>; 2476 }; 2477 }; 2478 }; 2479 2480 in-ports { 2481 #address-cells = <1>; 2482 #size-cells = <0>; 2483 2484 port@7 { 2485 reg = <7>; 2486 swao_funnel_in: endpoint { 2487 remote-endpoint = <&merge_funnel_out>; 2488 }; 2489 }; 2490 }; 2491 }; 2492 2493 etf@6b05000 { 2494 compatible = "arm,coresight-tmc", "arm,primecell"; 2495 reg = <0 0x06b05000 0 0x1000>; 2496 2497 clocks = <&aoss_qmp>; 2498 clock-names = "apb_pclk"; 2499 2500 out-ports { 2501 port { 2502 etf_out: endpoint { 2503 remote-endpoint = <&swao_replicator_in>; 2504 }; 2505 }; 2506 }; 2507 2508 in-ports { 2509 port { 2510 etf_in: endpoint { 2511 remote-endpoint = <&swao_funnel_out>; 2512 }; 2513 }; 2514 }; 2515 }; 2516 2517 replicator@6b06000 { 2518 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2519 reg = <0 0x06b06000 0 0x1000>; 2520 2521 clocks = <&aoss_qmp>; 2522 clock-names = "apb_pclk"; 2523 qcom,replicator-loses-context; 2524 2525 out-ports { 2526 port { 2527 swao_replicator_out: endpoint { 2528 remote-endpoint = <&replicator_in>; 2529 }; 2530 }; 2531 }; 2532 2533 in-ports { 2534 port { 2535 swao_replicator_in: endpoint { 2536 remote-endpoint = <&etf_out>; 2537 }; 2538 }; 2539 }; 2540 }; 2541 2542 etm@7040000 { 2543 compatible = "arm,coresight-etm4x", "arm,primecell"; 2544 reg = <0 0x07040000 0 0x1000>; 2545 2546 cpu = <&cpu0>; 2547 2548 clocks = <&aoss_qmp>; 2549 clock-names = "apb_pclk"; 2550 arm,coresight-loses-context-with-cpu; 2551 qcom,skip-power-up; 2552 2553 out-ports { 2554 port { 2555 etm0_out: endpoint { 2556 remote-endpoint = <&apss_funnel_in0>; 2557 }; 2558 }; 2559 }; 2560 }; 2561 2562 etm@7140000 { 2563 compatible = "arm,coresight-etm4x", "arm,primecell"; 2564 reg = <0 0x07140000 0 0x1000>; 2565 2566 cpu = <&cpu1>; 2567 2568 clocks = <&aoss_qmp>; 2569 clock-names = "apb_pclk"; 2570 arm,coresight-loses-context-with-cpu; 2571 qcom,skip-power-up; 2572 2573 out-ports { 2574 port { 2575 etm1_out: endpoint { 2576 remote-endpoint = <&apss_funnel_in1>; 2577 }; 2578 }; 2579 }; 2580 }; 2581 2582 etm@7240000 { 2583 compatible = "arm,coresight-etm4x", "arm,primecell"; 2584 reg = <0 0x07240000 0 0x1000>; 2585 2586 cpu = <&cpu2>; 2587 2588 clocks = <&aoss_qmp>; 2589 clock-names = "apb_pclk"; 2590 arm,coresight-loses-context-with-cpu; 2591 qcom,skip-power-up; 2592 2593 out-ports { 2594 port { 2595 etm2_out: endpoint { 2596 remote-endpoint = <&apss_funnel_in2>; 2597 }; 2598 }; 2599 }; 2600 }; 2601 2602 etm@7340000 { 2603 compatible = "arm,coresight-etm4x", "arm,primecell"; 2604 reg = <0 0x07340000 0 0x1000>; 2605 2606 cpu = <&cpu3>; 2607 2608 clocks = <&aoss_qmp>; 2609 clock-names = "apb_pclk"; 2610 arm,coresight-loses-context-with-cpu; 2611 qcom,skip-power-up; 2612 2613 out-ports { 2614 port { 2615 etm3_out: endpoint { 2616 remote-endpoint = <&apss_funnel_in3>; 2617 }; 2618 }; 2619 }; 2620 }; 2621 2622 etm@7440000 { 2623 compatible = "arm,coresight-etm4x", "arm,primecell"; 2624 reg = <0 0x07440000 0 0x1000>; 2625 2626 cpu = <&cpu4>; 2627 2628 clocks = <&aoss_qmp>; 2629 clock-names = "apb_pclk"; 2630 arm,coresight-loses-context-with-cpu; 2631 qcom,skip-power-up; 2632 2633 out-ports { 2634 port { 2635 etm4_out: endpoint { 2636 remote-endpoint = <&apss_funnel_in4>; 2637 }; 2638 }; 2639 }; 2640 }; 2641 2642 etm@7540000 { 2643 compatible = "arm,coresight-etm4x", "arm,primecell"; 2644 reg = <0 0x07540000 0 0x1000>; 2645 2646 cpu = <&cpu5>; 2647 2648 clocks = <&aoss_qmp>; 2649 clock-names = "apb_pclk"; 2650 arm,coresight-loses-context-with-cpu; 2651 qcom,skip-power-up; 2652 2653 out-ports { 2654 port { 2655 etm5_out: endpoint { 2656 remote-endpoint = <&apss_funnel_in5>; 2657 }; 2658 }; 2659 }; 2660 }; 2661 2662 etm@7640000 { 2663 compatible = "arm,coresight-etm4x", "arm,primecell"; 2664 reg = <0 0x07640000 0 0x1000>; 2665 2666 cpu = <&cpu6>; 2667 2668 clocks = <&aoss_qmp>; 2669 clock-names = "apb_pclk"; 2670 arm,coresight-loses-context-with-cpu; 2671 qcom,skip-power-up; 2672 2673 out-ports { 2674 port { 2675 etm6_out: endpoint { 2676 remote-endpoint = <&apss_funnel_in6>; 2677 }; 2678 }; 2679 }; 2680 }; 2681 2682 etm@7740000 { 2683 compatible = "arm,coresight-etm4x", "arm,primecell"; 2684 reg = <0 0x07740000 0 0x1000>; 2685 2686 cpu = <&cpu7>; 2687 2688 clocks = <&aoss_qmp>; 2689 clock-names = "apb_pclk"; 2690 arm,coresight-loses-context-with-cpu; 2691 qcom,skip-power-up; 2692 2693 out-ports { 2694 port { 2695 etm7_out: endpoint { 2696 remote-endpoint = <&apss_funnel_in7>; 2697 }; 2698 }; 2699 }; 2700 }; 2701 2702 funnel@7800000 { /* APSS Funnel */ 2703 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2704 reg = <0 0x07800000 0 0x1000>; 2705 2706 clocks = <&aoss_qmp>; 2707 clock-names = "apb_pclk"; 2708 2709 out-ports { 2710 port { 2711 apss_funnel_out: endpoint { 2712 remote-endpoint = <&apss_merge_funnel_in>; 2713 }; 2714 }; 2715 }; 2716 2717 in-ports { 2718 #address-cells = <1>; 2719 #size-cells = <0>; 2720 2721 port@0 { 2722 reg = <0>; 2723 apss_funnel_in0: endpoint { 2724 remote-endpoint = <&etm0_out>; 2725 }; 2726 }; 2727 2728 port@1 { 2729 reg = <1>; 2730 apss_funnel_in1: endpoint { 2731 remote-endpoint = <&etm1_out>; 2732 }; 2733 }; 2734 2735 port@2 { 2736 reg = <2>; 2737 apss_funnel_in2: endpoint { 2738 remote-endpoint = <&etm2_out>; 2739 }; 2740 }; 2741 2742 port@3 { 2743 reg = <3>; 2744 apss_funnel_in3: endpoint { 2745 remote-endpoint = <&etm3_out>; 2746 }; 2747 }; 2748 2749 port@4 { 2750 reg = <4>; 2751 apss_funnel_in4: endpoint { 2752 remote-endpoint = <&etm4_out>; 2753 }; 2754 }; 2755 2756 port@5 { 2757 reg = <5>; 2758 apss_funnel_in5: endpoint { 2759 remote-endpoint = <&etm5_out>; 2760 }; 2761 }; 2762 2763 port@6 { 2764 reg = <6>; 2765 apss_funnel_in6: endpoint { 2766 remote-endpoint = <&etm6_out>; 2767 }; 2768 }; 2769 2770 port@7 { 2771 reg = <7>; 2772 apss_funnel_in7: endpoint { 2773 remote-endpoint = <&etm7_out>; 2774 }; 2775 }; 2776 }; 2777 }; 2778 2779 funnel@7810000 { 2780 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2781 reg = <0 0x07810000 0 0x1000>; 2782 2783 clocks = <&aoss_qmp>; 2784 clock-names = "apb_pclk"; 2785 2786 out-ports { 2787 port { 2788 apss_merge_funnel_out: endpoint { 2789 remote-endpoint = <&funnel1_in4>; 2790 }; 2791 }; 2792 }; 2793 2794 in-ports { 2795 port { 2796 apss_merge_funnel_in: endpoint { 2797 remote-endpoint = <&apss_funnel_out>; 2798 }; 2799 }; 2800 }; 2801 }; 2802 2803 sdhc_2: mmc@8804000 { 2804 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2805 reg = <0 0x08804000 0 0x1000>; 2806 2807 iommus = <&apps_smmu 0x80 0>; 2808 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2809 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2810 interrupt-names = "hc_irq", "pwr_irq"; 2811 2812 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2813 <&gcc GCC_SDCC2_APPS_CLK>, 2814 <&rpmhcc RPMH_CXO_CLK>; 2815 clock-names = "iface", "core", "xo"; 2816 2817 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2818 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2819 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2820 power-domains = <&rpmhpd SC7180_CX>; 2821 operating-points-v2 = <&sdhc2_opp_table>; 2822 2823 bus-width = <4>; 2824 2825 status = "disabled"; 2826 2827 sdhc2_opp_table: opp-table { 2828 compatible = "operating-points-v2"; 2829 2830 opp-100000000 { 2831 opp-hz = /bits/ 64 <100000000>; 2832 required-opps = <&rpmhpd_opp_low_svs>; 2833 opp-peak-kBps = <1800000 600000>; 2834 opp-avg-kBps = <100000 0>; 2835 }; 2836 2837 opp-202000000 { 2838 opp-hz = /bits/ 64 <202000000>; 2839 required-opps = <&rpmhpd_opp_nom>; 2840 opp-peak-kBps = <5400000 1600000>; 2841 opp-avg-kBps = <200000 0>; 2842 }; 2843 }; 2844 }; 2845 2846 qspi: spi@88dc000 { 2847 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; 2848 reg = <0 0x088dc000 0 0x600>; 2849 iommus = <&apps_smmu 0x20 0x0>; 2850 #address-cells = <1>; 2851 #size-cells = <0>; 2852 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2853 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2854 <&gcc GCC_QSPI_CORE_CLK>; 2855 clock-names = "iface", "core"; 2856 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2857 &config_noc SLAVE_QSPI_0 0>; 2858 interconnect-names = "qspi-config"; 2859 power-domains = <&rpmhpd SC7180_CX>; 2860 operating-points-v2 = <&qspi_opp_table>; 2861 status = "disabled"; 2862 }; 2863 2864 usb_1_hsphy: phy@88e3000 { 2865 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2866 reg = <0 0x088e3000 0 0x400>; 2867 status = "disabled"; 2868 #phy-cells = <0>; 2869 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2870 <&rpmhcc RPMH_CXO_CLK>; 2871 clock-names = "cfg_ahb", "ref"; 2872 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2873 2874 nvmem-cells = <&qusb2p_hstx_trim>; 2875 }; 2876 2877 usb_1_qmpphy: phy@88e8000 { 2878 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2879 reg = <0 0x088e8000 0 0x3000>; 2880 status = "disabled"; 2881 2882 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2883 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2884 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2885 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, 2886 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 2887 clock-names = "aux", 2888 "ref", 2889 "com_aux", 2890 "usb3_pipe", 2891 "cfg_ahb"; 2892 2893 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2894 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2895 reset-names = "phy", "common"; 2896 2897 #clock-cells = <1>; 2898 #phy-cells = <1>; 2899 }; 2900 2901 pmu@90b6300 { 2902 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon"; 2903 reg = <0 0x090b6300 0 0x600>; 2904 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2905 2906 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2907 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 2908 operating-points-v2 = <&cpu_bwmon_opp_table>; 2909 2910 cpu_bwmon_opp_table: opp-table { 2911 compatible = "operating-points-v2"; 2912 2913 opp-0 { 2914 opp-peak-kBps = <2288000>; 2915 }; 2916 2917 opp-1 { 2918 opp-peak-kBps = <4577000>; 2919 }; 2920 2921 opp-2 { 2922 opp-peak-kBps = <7110000>; 2923 }; 2924 2925 opp-3 { 2926 opp-peak-kBps = <9155000>; 2927 }; 2928 2929 opp-4 { 2930 opp-peak-kBps = <12298000>; 2931 }; 2932 2933 opp-5 { 2934 opp-peak-kBps = <14236000>; 2935 }; 2936 }; 2937 }; 2938 2939 pmu@90cd000 { 2940 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 2941 reg = <0 0x090cd000 0 0x1000>; 2942 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 2943 2944 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 2945 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2946 operating-points-v2 = <&llcc_bwmon_opp_table>; 2947 2948 llcc_bwmon_opp_table: opp-table { 2949 compatible = "operating-points-v2"; 2950 2951 opp-0 { 2952 opp-peak-kBps = <1144000>; 2953 }; 2954 2955 opp-1 { 2956 opp-peak-kBps = <1720000>; 2957 }; 2958 2959 opp-2 { 2960 opp-peak-kBps = <2086000>; 2961 }; 2962 2963 opp-3 { 2964 opp-peak-kBps = <2929000>; 2965 }; 2966 2967 opp-4 { 2968 opp-peak-kBps = <3879000>; 2969 }; 2970 2971 opp-5 { 2972 opp-peak-kBps = <5931000>; 2973 }; 2974 2975 opp-6 { 2976 opp-peak-kBps = <6881000>; 2977 }; 2978 2979 opp-7 { 2980 opp-peak-kBps = <8137000>; 2981 }; 2982 }; 2983 }; 2984 2985 dc_noc: interconnect@9160000 { 2986 compatible = "qcom,sc7180-dc-noc"; 2987 reg = <0 0x09160000 0 0x03200>; 2988 #interconnect-cells = <2>; 2989 qcom,bcm-voters = <&apps_bcm_voter>; 2990 }; 2991 2992 system-cache-controller@9200000 { 2993 compatible = "qcom,sc7180-llcc"; 2994 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2995 reg-names = "llcc0_base", "llcc_broadcast_base"; 2996 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2997 }; 2998 2999 gem_noc: interconnect@9680000 { 3000 compatible = "qcom,sc7180-gem-noc"; 3001 reg = <0 0x09680000 0 0x3e200>; 3002 #interconnect-cells = <2>; 3003 qcom,bcm-voters = <&apps_bcm_voter>; 3004 }; 3005 3006 npu_noc: interconnect@9990000 { 3007 compatible = "qcom,sc7180-npu-noc"; 3008 reg = <0 0x09990000 0 0x1600>; 3009 #interconnect-cells = <2>; 3010 qcom,bcm-voters = <&apps_bcm_voter>; 3011 }; 3012 3013 usb_1: usb@a6f8800 { 3014 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 3015 reg = <0 0x0a6f8800 0 0x400>; 3016 status = "disabled"; 3017 #address-cells = <2>; 3018 #size-cells = <2>; 3019 ranges; 3020 dma-ranges; 3021 3022 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3023 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3024 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3025 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3026 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3027 clock-names = "cfg_noc", 3028 "core", 3029 "iface", 3030 "sleep", 3031 "mock_utmi"; 3032 3033 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3034 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3035 assigned-clock-rates = <19200000>, <150000000>; 3036 3037 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3038 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3039 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 3040 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3041 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 3042 interrupt-names = "pwr_event", 3043 "hs_phy_irq", 3044 "dp_hs_phy_irq", 3045 "dm_hs_phy_irq", 3046 "ss_phy_irq"; 3047 3048 power-domains = <&gcc USB30_PRIM_GDSC>; 3049 required-opps = <&rpmhpd_opp_nom>; 3050 3051 resets = <&gcc GCC_USB30_PRIM_BCR>; 3052 3053 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 3054 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 3055 interconnect-names = "usb-ddr", "apps-usb"; 3056 3057 wakeup-source; 3058 3059 usb_1_dwc3: usb@a600000 { 3060 compatible = "snps,dwc3"; 3061 reg = <0 0x0a600000 0 0xe000>; 3062 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3063 iommus = <&apps_smmu 0x540 0>; 3064 snps,dis_u2_susphy_quirk; 3065 snps,dis_enblslpm_quirk; 3066 snps,parkmode-disable-ss-quirk; 3067 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3068 phy-names = "usb2-phy", "usb3-phy"; 3069 maximum-speed = "super-speed"; 3070 }; 3071 }; 3072 3073 venus: video-codec@aa00000 { 3074 compatible = "qcom,sc7180-venus"; 3075 reg = <0 0x0aa00000 0 0xff000>; 3076 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3077 power-domains = <&videocc VENUS_GDSC>, 3078 <&videocc VCODEC0_GDSC>, 3079 <&rpmhpd SC7180_CX>; 3080 power-domain-names = "venus", "vcodec0", "cx"; 3081 operating-points-v2 = <&venus_opp_table>; 3082 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3083 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3084 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3085 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3086 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 3087 clock-names = "core", "iface", "bus", 3088 "vcodec0_core", "vcodec0_bus"; 3089 iommus = <&apps_smmu 0x0c00 0x60>; 3090 memory-region = <&venus_mem>; 3091 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 3092 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 3093 interconnect-names = "video-mem", "cpu-cfg"; 3094 3095 video-decoder { 3096 compatible = "venus-decoder"; 3097 }; 3098 3099 video-encoder { 3100 compatible = "venus-encoder"; 3101 }; 3102 3103 venus_opp_table: opp-table { 3104 compatible = "operating-points-v2"; 3105 3106 opp-150000000 { 3107 opp-hz = /bits/ 64 <150000000>; 3108 required-opps = <&rpmhpd_opp_low_svs>; 3109 }; 3110 3111 opp-270000000 { 3112 opp-hz = /bits/ 64 <270000000>; 3113 required-opps = <&rpmhpd_opp_svs>; 3114 }; 3115 3116 opp-340000000 { 3117 opp-hz = /bits/ 64 <340000000>; 3118 required-opps = <&rpmhpd_opp_svs_l1>; 3119 }; 3120 3121 opp-434000000 { 3122 opp-hz = /bits/ 64 <434000000>; 3123 required-opps = <&rpmhpd_opp_nom>; 3124 }; 3125 3126 opp-500000097 { 3127 opp-hz = /bits/ 64 <500000097>; 3128 required-opps = <&rpmhpd_opp_turbo>; 3129 }; 3130 }; 3131 }; 3132 3133 videocc: clock-controller@ab00000 { 3134 compatible = "qcom,sc7180-videocc"; 3135 reg = <0 0x0ab00000 0 0x10000>; 3136 clocks = <&rpmhcc RPMH_CXO_CLK>; 3137 clock-names = "bi_tcxo"; 3138 #clock-cells = <1>; 3139 #reset-cells = <1>; 3140 #power-domain-cells = <1>; 3141 }; 3142 3143 camnoc_virt: interconnect@ac00000 { 3144 compatible = "qcom,sc7180-camnoc-virt"; 3145 reg = <0 0x0ac00000 0 0x1000>; 3146 #interconnect-cells = <2>; 3147 qcom,bcm-voters = <&apps_bcm_voter>; 3148 }; 3149 3150 camcc: clock-controller@ad00000 { 3151 compatible = "qcom,sc7180-camcc"; 3152 reg = <0 0x0ad00000 0 0x10000>; 3153 clocks = <&rpmhcc RPMH_CXO_CLK>, 3154 <&gcc GCC_CAMERA_AHB_CLK>, 3155 <&gcc GCC_CAMERA_XO_CLK>; 3156 clock-names = "bi_tcxo", "iface", "xo"; 3157 #clock-cells = <1>; 3158 #reset-cells = <1>; 3159 #power-domain-cells = <1>; 3160 }; 3161 3162 mdss: display-subsystem@ae00000 { 3163 compatible = "qcom,sc7180-mdss"; 3164 reg = <0 0x0ae00000 0 0x1000>; 3165 reg-names = "mdss"; 3166 3167 power-domains = <&dispcc MDSS_GDSC>; 3168 3169 clocks = <&gcc GCC_DISP_AHB_CLK>, 3170 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3171 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3172 clock-names = "iface", "ahb", "core"; 3173 3174 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3175 interrupt-controller; 3176 #interrupt-cells = <1>; 3177 3178 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 3179 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3180 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3181 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 3182 interconnect-names = "mdp0-mem", 3183 "cpu-cfg"; 3184 3185 iommus = <&apps_smmu 0x800 0x2>; 3186 3187 #address-cells = <2>; 3188 #size-cells = <2>; 3189 ranges; 3190 3191 status = "disabled"; 3192 3193 mdp: display-controller@ae01000 { 3194 compatible = "qcom,sc7180-dpu"; 3195 reg = <0 0x0ae01000 0 0x8f000>, 3196 <0 0x0aeb0000 0 0x2008>; 3197 reg-names = "mdp", "vbif"; 3198 3199 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3200 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3201 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3202 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3203 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3204 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3205 clock-names = "bus", "iface", "rot", "lut", "core", 3206 "vsync"; 3207 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3208 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3209 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3210 assigned-clock-rates = <19200000>, 3211 <19200000>, 3212 <19200000>; 3213 operating-points-v2 = <&mdp_opp_table>; 3214 power-domains = <&rpmhpd SC7180_CX>; 3215 3216 interrupt-parent = <&mdss>; 3217 interrupts = <0>; 3218 3219 ports { 3220 #address-cells = <1>; 3221 #size-cells = <0>; 3222 3223 port@0 { 3224 reg = <0>; 3225 dpu_intf1_out: endpoint { 3226 remote-endpoint = <&mdss_dsi0_in>; 3227 }; 3228 }; 3229 3230 port@2 { 3231 reg = <2>; 3232 dpu_intf0_out: endpoint { 3233 remote-endpoint = <&dp_in>; 3234 }; 3235 }; 3236 }; 3237 3238 mdp_opp_table: opp-table { 3239 compatible = "operating-points-v2"; 3240 3241 opp-200000000 { 3242 opp-hz = /bits/ 64 <200000000>; 3243 required-opps = <&rpmhpd_opp_low_svs>; 3244 }; 3245 3246 opp-300000000 { 3247 opp-hz = /bits/ 64 <300000000>; 3248 required-opps = <&rpmhpd_opp_svs>; 3249 }; 3250 3251 opp-345000000 { 3252 opp-hz = /bits/ 64 <345000000>; 3253 required-opps = <&rpmhpd_opp_svs_l1>; 3254 }; 3255 3256 opp-460000000 { 3257 opp-hz = /bits/ 64 <460000000>; 3258 required-opps = <&rpmhpd_opp_nom>; 3259 }; 3260 }; 3261 }; 3262 3263 mdss_dsi0: dsi@ae94000 { 3264 compatible = "qcom,sc7180-dsi-ctrl", 3265 "qcom,mdss-dsi-ctrl"; 3266 reg = <0 0x0ae94000 0 0x400>; 3267 reg-names = "dsi_ctrl"; 3268 3269 interrupt-parent = <&mdss>; 3270 interrupts = <4>; 3271 3272 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3273 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3274 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3275 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3276 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3277 <&gcc GCC_DISP_HF_AXI_CLK>; 3278 clock-names = "byte", 3279 "byte_intf", 3280 "pixel", 3281 "core", 3282 "iface", 3283 "bus"; 3284 3285 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3286 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 3287 3288 operating-points-v2 = <&dsi_opp_table>; 3289 power-domains = <&rpmhpd SC7180_CX>; 3290 3291 phys = <&mdss_dsi0_phy>; 3292 3293 #address-cells = <1>; 3294 #size-cells = <0>; 3295 3296 status = "disabled"; 3297 3298 ports { 3299 #address-cells = <1>; 3300 #size-cells = <0>; 3301 3302 port@0 { 3303 reg = <0>; 3304 mdss_dsi0_in: endpoint { 3305 remote-endpoint = <&dpu_intf1_out>; 3306 }; 3307 }; 3308 3309 port@1 { 3310 reg = <1>; 3311 mdss_dsi0_out: endpoint { 3312 }; 3313 }; 3314 }; 3315 3316 dsi_opp_table: opp-table { 3317 compatible = "operating-points-v2"; 3318 3319 opp-187500000 { 3320 opp-hz = /bits/ 64 <187500000>; 3321 required-opps = <&rpmhpd_opp_low_svs>; 3322 }; 3323 3324 opp-300000000 { 3325 opp-hz = /bits/ 64 <300000000>; 3326 required-opps = <&rpmhpd_opp_svs>; 3327 }; 3328 3329 opp-358000000 { 3330 opp-hz = /bits/ 64 <358000000>; 3331 required-opps = <&rpmhpd_opp_svs_l1>; 3332 }; 3333 }; 3334 }; 3335 3336 mdss_dsi0_phy: phy@ae94400 { 3337 compatible = "qcom,dsi-phy-10nm"; 3338 reg = <0 0x0ae94400 0 0x200>, 3339 <0 0x0ae94600 0 0x280>, 3340 <0 0x0ae94a00 0 0x1e0>; 3341 reg-names = "dsi_phy", 3342 "dsi_phy_lane", 3343 "dsi_pll"; 3344 3345 #clock-cells = <1>; 3346 #phy-cells = <0>; 3347 3348 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3349 <&rpmhcc RPMH_CXO_CLK>; 3350 clock-names = "iface", "ref"; 3351 3352 status = "disabled"; 3353 }; 3354 3355 mdss_dp: displayport-controller@ae90000 { 3356 compatible = "qcom,sc7180-dp"; 3357 status = "disabled"; 3358 3359 reg = <0 0x0ae90000 0 0x200>, 3360 <0 0x0ae90200 0 0x200>, 3361 <0 0x0ae90400 0 0xc00>, 3362 <0 0x0ae91000 0 0x400>, 3363 <0 0x0ae91400 0 0x400>; 3364 3365 interrupt-parent = <&mdss>; 3366 interrupts = <12>; 3367 3368 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3369 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3370 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3371 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3372 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3373 clock-names = "core_iface", "core_aux", "ctrl_link", 3374 "ctrl_link_iface", "stream_pixel"; 3375 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3376 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3377 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3378 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3379 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3380 phy-names = "dp"; 3381 3382 operating-points-v2 = <&dp_opp_table>; 3383 power-domains = <&rpmhpd SC7180_CX>; 3384 3385 #sound-dai-cells = <0>; 3386 3387 ports { 3388 #address-cells = <1>; 3389 #size-cells = <0>; 3390 port@0 { 3391 reg = <0>; 3392 dp_in: endpoint { 3393 remote-endpoint = <&dpu_intf0_out>; 3394 }; 3395 }; 3396 3397 port@1 { 3398 reg = <1>; 3399 mdss_dp_out: endpoint { }; 3400 }; 3401 }; 3402 3403 dp_opp_table: opp-table { 3404 compatible = "operating-points-v2"; 3405 3406 opp-160000000 { 3407 opp-hz = /bits/ 64 <160000000>; 3408 required-opps = <&rpmhpd_opp_low_svs>; 3409 }; 3410 3411 opp-270000000 { 3412 opp-hz = /bits/ 64 <270000000>; 3413 required-opps = <&rpmhpd_opp_svs>; 3414 }; 3415 3416 opp-540000000 { 3417 opp-hz = /bits/ 64 <540000000>; 3418 required-opps = <&rpmhpd_opp_svs_l1>; 3419 }; 3420 3421 opp-810000000 { 3422 opp-hz = /bits/ 64 <810000000>; 3423 required-opps = <&rpmhpd_opp_nom>; 3424 }; 3425 }; 3426 }; 3427 }; 3428 3429 dispcc: clock-controller@af00000 { 3430 compatible = "qcom,sc7180-dispcc"; 3431 reg = <0 0x0af00000 0 0x200000>; 3432 clocks = <&rpmhcc RPMH_CXO_CLK>, 3433 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3434 <&mdss_dsi0_phy 0>, 3435 <&mdss_dsi0_phy 1>, 3436 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3437 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3438 clock-names = "bi_tcxo", 3439 "gcc_disp_gpll0_clk_src", 3440 "dsi0_phy_pll_out_byteclk", 3441 "dsi0_phy_pll_out_dsiclk", 3442 "dp_phy_pll_link_clk", 3443 "dp_phy_pll_vco_div_clk"; 3444 #clock-cells = <1>; 3445 #reset-cells = <1>; 3446 #power-domain-cells = <1>; 3447 }; 3448 3449 pdc: interrupt-controller@b220000 { 3450 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3451 reg = <0 0x0b220000 0 0x30000>; 3452 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3453 #interrupt-cells = <2>; 3454 interrupt-parent = <&intc>; 3455 interrupt-controller; 3456 }; 3457 3458 pdc_reset: reset-controller@b2e0000 { 3459 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3460 reg = <0 0x0b2e0000 0 0x20000>; 3461 #reset-cells = <1>; 3462 }; 3463 3464 tsens0: thermal-sensor@c263000 { 3465 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3466 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3467 <0 0x0c222000 0 0x1ff>; /* SROT */ 3468 #qcom,sensors = <15>; 3469 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3471 interrupt-names = "uplow","critical"; 3472 #thermal-sensor-cells = <1>; 3473 }; 3474 3475 tsens1: thermal-sensor@c265000 { 3476 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3477 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3478 <0 0x0c223000 0 0x1ff>; /* SROT */ 3479 #qcom,sensors = <10>; 3480 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3482 interrupt-names = "uplow","critical"; 3483 #thermal-sensor-cells = <1>; 3484 }; 3485 3486 aoss_reset: reset-controller@c2a0000 { 3487 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3488 reg = <0 0x0c2a0000 0 0x31000>; 3489 #reset-cells = <1>; 3490 }; 3491 3492 aoss_qmp: power-management@c300000 { 3493 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; 3494 reg = <0 0x0c300000 0 0x400>; 3495 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3496 mboxes = <&apss_shared 0>; 3497 3498 #clock-cells = <0>; 3499 }; 3500 3501 sram@c3f0000 { 3502 compatible = "qcom,rpmh-stats"; 3503 reg = <0 0x0c3f0000 0 0x400>; 3504 }; 3505 3506 spmi_bus: spmi@c440000 { 3507 compatible = "qcom,spmi-pmic-arb"; 3508 reg = <0 0x0c440000 0 0x1100>, 3509 <0 0x0c600000 0 0x2000000>, 3510 <0 0x0e600000 0 0x100000>, 3511 <0 0x0e700000 0 0xa0000>, 3512 <0 0x0c40a000 0 0x26000>; 3513 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3514 interrupt-names = "periph_irq"; 3515 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3516 qcom,ee = <0>; 3517 qcom,channel = <0>; 3518 #address-cells = <2>; 3519 #size-cells = <0>; 3520 interrupt-controller; 3521 #interrupt-cells = <4>; 3522 }; 3523 3524 sram@146aa000 { 3525 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; 3526 reg = <0 0x146aa000 0 0x2000>; 3527 3528 #address-cells = <1>; 3529 #size-cells = <1>; 3530 3531 ranges = <0 0 0x146aa000 0x2000>; 3532 3533 pil-reloc@94c { 3534 compatible = "qcom,pil-reloc-info"; 3535 reg = <0x94c 0xc8>; 3536 }; 3537 }; 3538 3539 apps_smmu: iommu@15000000 { 3540 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3541 reg = <0 0x15000000 0 0x100000>; 3542 #iommu-cells = <2>; 3543 #global-interrupts = <1>; 3544 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3545 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3546 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3547 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3548 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3549 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3550 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3551 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3552 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3553 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3554 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3555 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3556 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3557 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3558 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3559 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3560 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3561 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3562 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3563 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3564 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3565 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3566 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3567 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3568 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3569 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3570 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3571 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3572 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3573 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3574 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3575 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3576 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3577 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3578 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3579 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3580 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3581 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3582 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3583 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3584 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3585 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3586 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3587 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3588 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3589 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3590 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3591 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3592 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3593 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3594 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3595 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3596 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3597 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3598 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3599 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3600 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3601 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3602 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3603 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3604 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3605 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3625 dma-coherent; 3626 }; 3627 3628 intc: interrupt-controller@17a00000 { 3629 compatible = "arm,gic-v3"; 3630 #address-cells = <2>; 3631 #size-cells = <2>; 3632 ranges; 3633 #interrupt-cells = <3>; 3634 interrupt-controller; 3635 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3636 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3637 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3638 3639 msi-controller@17a40000 { 3640 compatible = "arm,gic-v3-its"; 3641 msi-controller; 3642 #msi-cells = <1>; 3643 reg = <0 0x17a40000 0 0x20000>; 3644 status = "disabled"; 3645 }; 3646 }; 3647 3648 apss_shared: mailbox@17c00000 { 3649 compatible = "qcom,sc7180-apss-shared", 3650 "qcom,sdm845-apss-shared"; 3651 reg = <0 0x17c00000 0 0x10000>; 3652 #mbox-cells = <1>; 3653 }; 3654 3655 watchdog@17c10000 { 3656 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3657 reg = <0 0x17c10000 0 0x1000>; 3658 clocks = <&sleep_clk>; 3659 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 3660 }; 3661 3662 timer@17c20000 { 3663 #address-cells = <1>; 3664 #size-cells = <1>; 3665 ranges = <0 0 0 0x20000000>; 3666 compatible = "arm,armv7-timer-mem"; 3667 reg = <0 0x17c20000 0 0x1000>; 3668 3669 frame@17c21000 { 3670 frame-number = <0>; 3671 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3672 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3673 reg = <0x17c21000 0x1000>, 3674 <0x17c22000 0x1000>; 3675 }; 3676 3677 frame@17c23000 { 3678 frame-number = <1>; 3679 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3680 reg = <0x17c23000 0x1000>; 3681 status = "disabled"; 3682 }; 3683 3684 frame@17c25000 { 3685 frame-number = <2>; 3686 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3687 reg = <0x17c25000 0x1000>; 3688 status = "disabled"; 3689 }; 3690 3691 frame@17c27000 { 3692 frame-number = <3>; 3693 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3694 reg = <0x17c27000 0x1000>; 3695 status = "disabled"; 3696 }; 3697 3698 frame@17c29000 { 3699 frame-number = <4>; 3700 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3701 reg = <0x17c29000 0x1000>; 3702 status = "disabled"; 3703 }; 3704 3705 frame@17c2b000 { 3706 frame-number = <5>; 3707 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3708 reg = <0x17c2b000 0x1000>; 3709 status = "disabled"; 3710 }; 3711 3712 frame@17c2d000 { 3713 frame-number = <6>; 3714 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3715 reg = <0x17c2d000 0x1000>; 3716 status = "disabled"; 3717 }; 3718 }; 3719 3720 apps_rsc: rsc@18200000 { 3721 compatible = "qcom,rpmh-rsc"; 3722 reg = <0 0x18200000 0 0x10000>, 3723 <0 0x18210000 0 0x10000>, 3724 <0 0x18220000 0 0x10000>; 3725 reg-names = "drv-0", "drv-1", "drv-2"; 3726 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3729 qcom,tcs-offset = <0xd00>; 3730 qcom,drv-id = <2>; 3731 qcom,tcs-config = <ACTIVE_TCS 2>, 3732 <SLEEP_TCS 3>, 3733 <WAKE_TCS 3>, 3734 <CONTROL_TCS 1>; 3735 power-domains = <&cluster_pd>; 3736 3737 rpmhcc: clock-controller { 3738 compatible = "qcom,sc7180-rpmh-clk"; 3739 clocks = <&xo_board>; 3740 clock-names = "xo"; 3741 #clock-cells = <1>; 3742 }; 3743 3744 rpmhpd: power-controller { 3745 compatible = "qcom,sc7180-rpmhpd"; 3746 #power-domain-cells = <1>; 3747 operating-points-v2 = <&rpmhpd_opp_table>; 3748 3749 rpmhpd_opp_table: opp-table { 3750 compatible = "operating-points-v2"; 3751 3752 rpmhpd_opp_ret: opp1 { 3753 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3754 }; 3755 3756 rpmhpd_opp_min_svs: opp2 { 3757 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3758 }; 3759 3760 rpmhpd_opp_low_svs: opp3 { 3761 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3762 }; 3763 3764 rpmhpd_opp_svs: opp4 { 3765 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3766 }; 3767 3768 rpmhpd_opp_svs_l1: opp5 { 3769 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3770 }; 3771 3772 rpmhpd_opp_svs_l2: opp6 { 3773 opp-level = <224>; 3774 }; 3775 3776 rpmhpd_opp_nom: opp7 { 3777 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3778 }; 3779 3780 rpmhpd_opp_nom_l1: opp8 { 3781 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3782 }; 3783 3784 rpmhpd_opp_nom_l2: opp9 { 3785 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3786 }; 3787 3788 rpmhpd_opp_turbo: opp10 { 3789 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3790 }; 3791 3792 rpmhpd_opp_turbo_l1: opp11 { 3793 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3794 }; 3795 }; 3796 }; 3797 3798 apps_bcm_voter: bcm-voter { 3799 compatible = "qcom,bcm-voter"; 3800 }; 3801 }; 3802 3803 osm_l3: interconnect@18321000 { 3804 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3"; 3805 reg = <0 0x18321000 0 0x1400>; 3806 3807 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3808 clock-names = "xo", "alternate"; 3809 3810 #interconnect-cells = <1>; 3811 }; 3812 3813 cpufreq_hw: cpufreq@18323000 { 3814 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw"; 3815 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3816 reg-names = "freq-domain0", "freq-domain1"; 3817 3818 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3819 clock-names = "xo", "alternate"; 3820 3821 #freq-domain-cells = <1>; 3822 #clock-cells = <1>; 3823 }; 3824 3825 wifi: wifi@18800000 { 3826 compatible = "qcom,wcn3990-wifi"; 3827 reg = <0 0x18800000 0 0x800000>; 3828 reg-names = "membase"; 3829 iommus = <&apps_smmu 0xc0 0x1>; 3830 interrupts = 3831 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3832 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3833 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3834 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3835 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3836 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3837 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3838 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3839 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3840 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3841 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3842 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3843 memory-region = <&wlan_mem>; 3844 qcom,msa-fixed-perm; 3845 status = "disabled"; 3846 }; 3847 3848 remoteproc_adsp: remoteproc@62400000 { 3849 compatible = "qcom,sc7180-adsp-pas"; 3850 reg = <0 0x62400000 0 0x100>; 3851 3852 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3853 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3854 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3855 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3856 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3857 interrupt-names = "wdog", 3858 "fatal", 3859 "ready", 3860 "handover", 3861 "stop-ack"; 3862 3863 clocks = <&rpmhcc RPMH_CXO_CLK>; 3864 clock-names = "xo"; 3865 3866 power-domains = <&rpmhpd SC7180_LCX>, 3867 <&rpmhpd SC7180_LMX>; 3868 power-domain-names = "lcx", "lmx"; 3869 3870 qcom,qmp = <&aoss_qmp>; 3871 qcom,smem-states = <&adsp_smp2p_out 0>; 3872 qcom,smem-state-names = "stop"; 3873 3874 status = "disabled"; 3875 3876 glink-edge { 3877 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3878 label = "lpass"; 3879 qcom,remote-pid = <2>; 3880 mboxes = <&apss_shared 8>; 3881 3882 apr { 3883 compatible = "qcom,apr-v2"; 3884 qcom,glink-channels = "apr_audio_svc"; 3885 qcom,domain = <APR_DOMAIN_ADSP>; 3886 #address-cells = <1>; 3887 #size-cells = <0>; 3888 3889 service@3 { 3890 compatible = "qcom,q6core"; 3891 reg = <APR_SVC_ADSP_CORE>; 3892 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3893 }; 3894 3895 q6afe: service@4 { 3896 compatible = "qcom,q6afe"; 3897 reg = <APR_SVC_AFE>; 3898 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3899 3900 q6afedai: dais { 3901 compatible = "qcom,q6afe-dais"; 3902 #address-cells = <1>; 3903 #size-cells = <0>; 3904 #sound-dai-cells = <1>; 3905 }; 3906 3907 q6afecc: clock-controller { 3908 compatible = "qcom,q6afe-clocks"; 3909 #clock-cells = <2>; 3910 }; 3911 }; 3912 3913 q6asm: service@7 { 3914 compatible = "qcom,q6asm"; 3915 reg = <APR_SVC_ASM>; 3916 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3917 3918 q6asmdai: dais { 3919 compatible = "qcom,q6asm-dais"; 3920 #address-cells = <1>; 3921 #size-cells = <0>; 3922 #sound-dai-cells = <1>; 3923 iommus = <&apps_smmu 0x1001 0x0>; 3924 }; 3925 }; 3926 3927 q6adm: service@8 { 3928 compatible = "qcom,q6adm"; 3929 reg = <APR_SVC_ADM>; 3930 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3931 3932 q6routing: routing { 3933 compatible = "qcom,q6adm-routing"; 3934 #sound-dai-cells = <0>; 3935 }; 3936 }; 3937 }; 3938 3939 fastrpc { 3940 compatible = "qcom,fastrpc"; 3941 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3942 label = "adsp"; 3943 #address-cells = <1>; 3944 #size-cells = <0>; 3945 3946 compute-cb@3 { 3947 compatible = "qcom,fastrpc-compute-cb"; 3948 reg = <3>; 3949 iommus = <&apps_smmu 0x1003 0x0>; 3950 }; 3951 3952 compute-cb@4 { 3953 compatible = "qcom,fastrpc-compute-cb"; 3954 reg = <4>; 3955 iommus = <&apps_smmu 0x1004 0x0>; 3956 }; 3957 3958 compute-cb@5 { 3959 compatible = "qcom,fastrpc-compute-cb"; 3960 reg = <5>; 3961 iommus = <&apps_smmu 0x1005 0x0>; 3962 qcom,nsessions = <5>; 3963 }; 3964 }; 3965 }; 3966 }; 3967 3968 lpasscc: clock-controller@62d00000 { 3969 compatible = "qcom,sc7180-lpasscorecc"; 3970 reg = <0 0x62d00000 0 0x50000>, 3971 <0 0x62780000 0 0x30000>; 3972 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3973 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3974 <&rpmhcc RPMH_CXO_CLK>; 3975 clock-names = "iface", "bi_tcxo"; 3976 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3977 #clock-cells = <1>; 3978 #power-domain-cells = <1>; 3979 3980 status = "reserved"; /* Controlled by ADSP */ 3981 }; 3982 3983 lpass_cpu: lpass@62d87000 { 3984 compatible = "qcom,sc7180-lpass-cpu"; 3985 3986 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 3987 reg-names = "lpass-hdmiif", "lpass-lpaif"; 3988 3989 iommus = <&apps_smmu 0x1020 0>, 3990 <&apps_smmu 0x1021 0>, 3991 <&apps_smmu 0x1032 0>; 3992 3993 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3994 required-opps = <&rpmhpd_opp_nom>; 3995 3996 status = "disabled"; 3997 3998 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3999 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 4000 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 4001 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 4002 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 4003 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 4004 4005 clock-names = "pcnoc-sway-clk", "audio-core", 4006 "mclk0", "pcnoc-mport-clk", 4007 "mi2s-bit-clk0", "mi2s-bit-clk1"; 4008 4009 4010 #sound-dai-cells = <1>; 4011 #address-cells = <1>; 4012 #size-cells = <0>; 4013 4014 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 4016 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 4017 }; 4018 4019 lpass_hm: clock-controller@63000000 { 4020 compatible = "qcom,sc7180-lpasshm"; 4021 reg = <0 0x63000000 0 0x28>; 4022 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 4023 <&rpmhcc RPMH_CXO_CLK>; 4024 clock-names = "iface", "bi_tcxo"; 4025 power-domains = <&rpmhpd SC7180_CX>; 4026 4027 #clock-cells = <1>; 4028 #power-domain-cells = <1>; 4029 4030 status = "reserved"; /* Controlled by ADSP */ 4031 }; 4032 }; 4033 4034 thermal-zones { 4035 cpu0_thermal: cpu0-thermal { 4036 polling-delay-passive = <250>; 4037 4038 thermal-sensors = <&tsens0 1>; 4039 sustainable-power = <1052>; 4040 4041 trips { 4042 cpu0_alert0: trip-point0 { 4043 temperature = <90000>; 4044 hysteresis = <2000>; 4045 type = "passive"; 4046 }; 4047 4048 cpu0_alert1: trip-point1 { 4049 temperature = <95000>; 4050 hysteresis = <2000>; 4051 type = "passive"; 4052 }; 4053 4054 cpu0_crit: cpu-crit { 4055 temperature = <110000>; 4056 hysteresis = <1000>; 4057 type = "critical"; 4058 }; 4059 }; 4060 4061 cooling-maps { 4062 map0 { 4063 trip = <&cpu0_alert0>; 4064 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4065 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4066 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4067 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4068 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4069 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4070 }; 4071 map1 { 4072 trip = <&cpu0_alert1>; 4073 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4074 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4075 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4076 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4077 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4078 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4079 }; 4080 }; 4081 }; 4082 4083 cpu1_thermal: cpu1-thermal { 4084 polling-delay-passive = <250>; 4085 4086 thermal-sensors = <&tsens0 2>; 4087 sustainable-power = <1052>; 4088 4089 trips { 4090 cpu1_alert0: trip-point0 { 4091 temperature = <90000>; 4092 hysteresis = <2000>; 4093 type = "passive"; 4094 }; 4095 4096 cpu1_alert1: trip-point1 { 4097 temperature = <95000>; 4098 hysteresis = <2000>; 4099 type = "passive"; 4100 }; 4101 4102 cpu1_crit: cpu-crit { 4103 temperature = <110000>; 4104 hysteresis = <1000>; 4105 type = "critical"; 4106 }; 4107 }; 4108 4109 cooling-maps { 4110 map0 { 4111 trip = <&cpu1_alert0>; 4112 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4113 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4114 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4115 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4116 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4117 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4118 }; 4119 map1 { 4120 trip = <&cpu1_alert1>; 4121 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4122 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4123 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4124 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4125 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4126 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4127 }; 4128 }; 4129 }; 4130 4131 cpu2_thermal: cpu2-thermal { 4132 polling-delay-passive = <250>; 4133 4134 thermal-sensors = <&tsens0 3>; 4135 sustainable-power = <1052>; 4136 4137 trips { 4138 cpu2_alert0: trip-point0 { 4139 temperature = <90000>; 4140 hysteresis = <2000>; 4141 type = "passive"; 4142 }; 4143 4144 cpu2_alert1: trip-point1 { 4145 temperature = <95000>; 4146 hysteresis = <2000>; 4147 type = "passive"; 4148 }; 4149 4150 cpu2_crit: cpu-crit { 4151 temperature = <110000>; 4152 hysteresis = <1000>; 4153 type = "critical"; 4154 }; 4155 }; 4156 4157 cooling-maps { 4158 map0 { 4159 trip = <&cpu2_alert0>; 4160 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4161 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4162 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4163 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4164 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4165 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4166 }; 4167 map1 { 4168 trip = <&cpu2_alert1>; 4169 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4170 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4171 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4172 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4173 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4174 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4175 }; 4176 }; 4177 }; 4178 4179 cpu3_thermal: cpu3-thermal { 4180 polling-delay-passive = <250>; 4181 4182 thermal-sensors = <&tsens0 4>; 4183 sustainable-power = <1052>; 4184 4185 trips { 4186 cpu3_alert0: trip-point0 { 4187 temperature = <90000>; 4188 hysteresis = <2000>; 4189 type = "passive"; 4190 }; 4191 4192 cpu3_alert1: trip-point1 { 4193 temperature = <95000>; 4194 hysteresis = <2000>; 4195 type = "passive"; 4196 }; 4197 4198 cpu3_crit: cpu-crit { 4199 temperature = <110000>; 4200 hysteresis = <1000>; 4201 type = "critical"; 4202 }; 4203 }; 4204 4205 cooling-maps { 4206 map0 { 4207 trip = <&cpu3_alert0>; 4208 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4209 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4210 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4211 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4212 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4213 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4214 }; 4215 map1 { 4216 trip = <&cpu3_alert1>; 4217 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4218 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4219 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4220 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4221 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4222 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4223 }; 4224 }; 4225 }; 4226 4227 cpu4_thermal: cpu4-thermal { 4228 polling-delay-passive = <250>; 4229 4230 thermal-sensors = <&tsens0 5>; 4231 sustainable-power = <1052>; 4232 4233 trips { 4234 cpu4_alert0: trip-point0 { 4235 temperature = <90000>; 4236 hysteresis = <2000>; 4237 type = "passive"; 4238 }; 4239 4240 cpu4_alert1: trip-point1 { 4241 temperature = <95000>; 4242 hysteresis = <2000>; 4243 type = "passive"; 4244 }; 4245 4246 cpu4_crit: cpu-crit { 4247 temperature = <110000>; 4248 hysteresis = <1000>; 4249 type = "critical"; 4250 }; 4251 }; 4252 4253 cooling-maps { 4254 map0 { 4255 trip = <&cpu4_alert0>; 4256 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4257 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4258 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4259 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4260 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4261 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4262 }; 4263 map1 { 4264 trip = <&cpu4_alert1>; 4265 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4266 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4267 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4268 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4269 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4270 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4271 }; 4272 }; 4273 }; 4274 4275 cpu5_thermal: cpu5-thermal { 4276 polling-delay-passive = <250>; 4277 4278 thermal-sensors = <&tsens0 6>; 4279 sustainable-power = <1052>; 4280 4281 trips { 4282 cpu5_alert0: trip-point0 { 4283 temperature = <90000>; 4284 hysteresis = <2000>; 4285 type = "passive"; 4286 }; 4287 4288 cpu5_alert1: trip-point1 { 4289 temperature = <95000>; 4290 hysteresis = <2000>; 4291 type = "passive"; 4292 }; 4293 4294 cpu5_crit: cpu-crit { 4295 temperature = <110000>; 4296 hysteresis = <1000>; 4297 type = "critical"; 4298 }; 4299 }; 4300 4301 cooling-maps { 4302 map0 { 4303 trip = <&cpu5_alert0>; 4304 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4305 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4306 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4307 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4308 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4309 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4310 }; 4311 map1 { 4312 trip = <&cpu5_alert1>; 4313 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4314 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4315 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4316 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4317 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4318 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4319 }; 4320 }; 4321 }; 4322 4323 cpu6_thermal: cpu6-thermal { 4324 polling-delay-passive = <250>; 4325 4326 thermal-sensors = <&tsens0 9>; 4327 sustainable-power = <1425>; 4328 4329 trips { 4330 cpu6_alert0: trip-point0 { 4331 temperature = <90000>; 4332 hysteresis = <2000>; 4333 type = "passive"; 4334 }; 4335 4336 cpu6_alert1: trip-point1 { 4337 temperature = <95000>; 4338 hysteresis = <2000>; 4339 type = "passive"; 4340 }; 4341 4342 cpu6_crit: cpu-crit { 4343 temperature = <110000>; 4344 hysteresis = <1000>; 4345 type = "critical"; 4346 }; 4347 }; 4348 4349 cooling-maps { 4350 map0 { 4351 trip = <&cpu6_alert0>; 4352 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4353 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4354 }; 4355 map1 { 4356 trip = <&cpu6_alert1>; 4357 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4358 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4359 }; 4360 }; 4361 }; 4362 4363 cpu7_thermal: cpu7-thermal { 4364 polling-delay-passive = <250>; 4365 4366 thermal-sensors = <&tsens0 10>; 4367 sustainable-power = <1425>; 4368 4369 trips { 4370 cpu7_alert0: trip-point0 { 4371 temperature = <90000>; 4372 hysteresis = <2000>; 4373 type = "passive"; 4374 }; 4375 4376 cpu7_alert1: trip-point1 { 4377 temperature = <95000>; 4378 hysteresis = <2000>; 4379 type = "passive"; 4380 }; 4381 4382 cpu7_crit: cpu-crit { 4383 temperature = <110000>; 4384 hysteresis = <1000>; 4385 type = "critical"; 4386 }; 4387 }; 4388 4389 cooling-maps { 4390 map0 { 4391 trip = <&cpu7_alert0>; 4392 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4393 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4394 }; 4395 map1 { 4396 trip = <&cpu7_alert1>; 4397 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4398 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4399 }; 4400 }; 4401 }; 4402 4403 cpu8_thermal: cpu8-thermal { 4404 polling-delay-passive = <250>; 4405 4406 thermal-sensors = <&tsens0 11>; 4407 sustainable-power = <1425>; 4408 4409 trips { 4410 cpu8_alert0: trip-point0 { 4411 temperature = <90000>; 4412 hysteresis = <2000>; 4413 type = "passive"; 4414 }; 4415 4416 cpu8_alert1: trip-point1 { 4417 temperature = <95000>; 4418 hysteresis = <2000>; 4419 type = "passive"; 4420 }; 4421 4422 cpu8_crit: cpu-crit { 4423 temperature = <110000>; 4424 hysteresis = <1000>; 4425 type = "critical"; 4426 }; 4427 }; 4428 4429 cooling-maps { 4430 map0 { 4431 trip = <&cpu8_alert0>; 4432 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4433 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4434 }; 4435 map1 { 4436 trip = <&cpu8_alert1>; 4437 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4438 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4439 }; 4440 }; 4441 }; 4442 4443 cpu9_thermal: cpu9-thermal { 4444 polling-delay-passive = <250>; 4445 4446 thermal-sensors = <&tsens0 12>; 4447 sustainable-power = <1425>; 4448 4449 trips { 4450 cpu9_alert0: trip-point0 { 4451 temperature = <90000>; 4452 hysteresis = <2000>; 4453 type = "passive"; 4454 }; 4455 4456 cpu9_alert1: trip-point1 { 4457 temperature = <95000>; 4458 hysteresis = <2000>; 4459 type = "passive"; 4460 }; 4461 4462 cpu9_crit: cpu-crit { 4463 temperature = <110000>; 4464 hysteresis = <1000>; 4465 type = "critical"; 4466 }; 4467 }; 4468 4469 cooling-maps { 4470 map0 { 4471 trip = <&cpu9_alert0>; 4472 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4473 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4474 }; 4475 map1 { 4476 trip = <&cpu9_alert1>; 4477 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4478 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4479 }; 4480 }; 4481 }; 4482 4483 aoss0-thermal { 4484 polling-delay-passive = <250>; 4485 4486 thermal-sensors = <&tsens0 0>; 4487 4488 trips { 4489 aoss0_alert0: trip-point0 { 4490 temperature = <90000>; 4491 hysteresis = <2000>; 4492 type = "hot"; 4493 }; 4494 4495 aoss0_crit: aoss0-crit { 4496 temperature = <110000>; 4497 hysteresis = <2000>; 4498 type = "critical"; 4499 }; 4500 }; 4501 }; 4502 4503 cpuss0-thermal { 4504 polling-delay-passive = <250>; 4505 4506 thermal-sensors = <&tsens0 7>; 4507 4508 trips { 4509 cpuss0_alert0: trip-point0 { 4510 temperature = <90000>; 4511 hysteresis = <2000>; 4512 type = "hot"; 4513 }; 4514 cpuss0_crit: cluster0-crit { 4515 temperature = <110000>; 4516 hysteresis = <2000>; 4517 type = "critical"; 4518 }; 4519 }; 4520 }; 4521 4522 cpuss1-thermal { 4523 polling-delay-passive = <250>; 4524 4525 thermal-sensors = <&tsens0 8>; 4526 4527 trips { 4528 cpuss1_alert0: trip-point0 { 4529 temperature = <90000>; 4530 hysteresis = <2000>; 4531 type = "hot"; 4532 }; 4533 cpuss1_crit: cluster0-crit { 4534 temperature = <110000>; 4535 hysteresis = <2000>; 4536 type = "critical"; 4537 }; 4538 }; 4539 }; 4540 4541 gpuss0-thermal { 4542 polling-delay-passive = <250>; 4543 4544 thermal-sensors = <&tsens0 13>; 4545 4546 trips { 4547 gpuss0_alert0: trip-point0 { 4548 temperature = <95000>; 4549 hysteresis = <2000>; 4550 type = "passive"; 4551 }; 4552 4553 gpuss0_crit: gpuss0-crit { 4554 temperature = <110000>; 4555 hysteresis = <2000>; 4556 type = "critical"; 4557 }; 4558 }; 4559 4560 cooling-maps { 4561 map0 { 4562 trip = <&gpuss0_alert0>; 4563 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4564 }; 4565 }; 4566 }; 4567 4568 gpuss1-thermal { 4569 polling-delay-passive = <250>; 4570 4571 thermal-sensors = <&tsens0 14>; 4572 4573 trips { 4574 gpuss1_alert0: trip-point0 { 4575 temperature = <95000>; 4576 hysteresis = <2000>; 4577 type = "passive"; 4578 }; 4579 4580 gpuss1_crit: gpuss1-crit { 4581 temperature = <110000>; 4582 hysteresis = <2000>; 4583 type = "critical"; 4584 }; 4585 }; 4586 4587 cooling-maps { 4588 map0 { 4589 trip = <&gpuss1_alert0>; 4590 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4591 }; 4592 }; 4593 }; 4594 4595 aoss1-thermal { 4596 polling-delay-passive = <250>; 4597 4598 thermal-sensors = <&tsens1 0>; 4599 4600 trips { 4601 aoss1_alert0: trip-point0 { 4602 temperature = <90000>; 4603 hysteresis = <2000>; 4604 type = "hot"; 4605 }; 4606 4607 aoss1_crit: aoss1-crit { 4608 temperature = <110000>; 4609 hysteresis = <2000>; 4610 type = "critical"; 4611 }; 4612 }; 4613 }; 4614 4615 cwlan-thermal { 4616 polling-delay-passive = <250>; 4617 4618 thermal-sensors = <&tsens1 1>; 4619 4620 trips { 4621 cwlan_alert0: trip-point0 { 4622 temperature = <90000>; 4623 hysteresis = <2000>; 4624 type = "hot"; 4625 }; 4626 4627 cwlan_crit: cwlan-crit { 4628 temperature = <110000>; 4629 hysteresis = <2000>; 4630 type = "critical"; 4631 }; 4632 }; 4633 }; 4634 4635 audio-thermal { 4636 polling-delay-passive = <250>; 4637 4638 thermal-sensors = <&tsens1 2>; 4639 4640 trips { 4641 audio_alert0: trip-point0 { 4642 temperature = <90000>; 4643 hysteresis = <2000>; 4644 type = "hot"; 4645 }; 4646 4647 audio_crit: audio-crit { 4648 temperature = <110000>; 4649 hysteresis = <2000>; 4650 type = "critical"; 4651 }; 4652 }; 4653 }; 4654 4655 ddr-thermal { 4656 polling-delay-passive = <250>; 4657 4658 thermal-sensors = <&tsens1 3>; 4659 4660 trips { 4661 ddr_alert0: trip-point0 { 4662 temperature = <90000>; 4663 hysteresis = <2000>; 4664 type = "hot"; 4665 }; 4666 4667 ddr_crit: ddr-crit { 4668 temperature = <110000>; 4669 hysteresis = <2000>; 4670 type = "critical"; 4671 }; 4672 }; 4673 }; 4674 4675 q6-hvx-thermal { 4676 polling-delay-passive = <250>; 4677 4678 thermal-sensors = <&tsens1 4>; 4679 4680 trips { 4681 q6_hvx_alert0: trip-point0 { 4682 temperature = <90000>; 4683 hysteresis = <2000>; 4684 type = "hot"; 4685 }; 4686 4687 q6_hvx_crit: q6-hvx-crit { 4688 temperature = <110000>; 4689 hysteresis = <2000>; 4690 type = "critical"; 4691 }; 4692 }; 4693 }; 4694 4695 camera-thermal { 4696 polling-delay-passive = <250>; 4697 4698 thermal-sensors = <&tsens1 5>; 4699 4700 trips { 4701 camera_alert0: trip-point0 { 4702 temperature = <90000>; 4703 hysteresis = <2000>; 4704 type = "hot"; 4705 }; 4706 4707 camera_crit: camera-crit { 4708 temperature = <110000>; 4709 hysteresis = <2000>; 4710 type = "critical"; 4711 }; 4712 }; 4713 }; 4714 4715 mdm-core-thermal { 4716 polling-delay-passive = <250>; 4717 4718 thermal-sensors = <&tsens1 6>; 4719 4720 trips { 4721 mdm_alert0: trip-point0 { 4722 temperature = <90000>; 4723 hysteresis = <2000>; 4724 type = "hot"; 4725 }; 4726 4727 mdm_crit: mdm-crit { 4728 temperature = <110000>; 4729 hysteresis = <2000>; 4730 type = "critical"; 4731 }; 4732 }; 4733 }; 4734 4735 mdm-dsp-thermal { 4736 polling-delay-passive = <250>; 4737 4738 thermal-sensors = <&tsens1 7>; 4739 4740 trips { 4741 mdm_dsp_alert0: trip-point0 { 4742 temperature = <90000>; 4743 hysteresis = <2000>; 4744 type = "hot"; 4745 }; 4746 4747 mdm_dsp_crit: mdm-dsp-crit { 4748 temperature = <110000>; 4749 hysteresis = <2000>; 4750 type = "critical"; 4751 }; 4752 }; 4753 }; 4754 4755 npu-thermal { 4756 polling-delay-passive = <250>; 4757 4758 thermal-sensors = <&tsens1 8>; 4759 4760 trips { 4761 npu_alert0: trip-point0 { 4762 temperature = <90000>; 4763 hysteresis = <2000>; 4764 type = "hot"; 4765 }; 4766 4767 npu_crit: npu-crit { 4768 temperature = <110000>; 4769 hysteresis = <2000>; 4770 type = "critical"; 4771 }; 4772 }; 4773 }; 4774 4775 video-thermal { 4776 polling-delay-passive = <250>; 4777 4778 thermal-sensors = <&tsens1 9>; 4779 4780 trips { 4781 video_alert0: trip-point0 { 4782 temperature = <90000>; 4783 hysteresis = <2000>; 4784 type = "hot"; 4785 }; 4786 4787 video_crit: video-crit { 4788 temperature = <110000>; 4789 hysteresis = <2000>; 4790 type = "critical"; 4791 }; 4792 }; 4793 }; 4794 }; 4795 4796 timer { 4797 compatible = "arm,armv8-timer"; 4798 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4799 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4800 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4801 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4802 }; 4803}; 4804