1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-sc7180.h> 11#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7180.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/interconnect/qcom,icc.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7180.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/phy/phy-qcom-qmp.h> 21#include <dt-bindings/phy/phy-qcom-qusb2.h> 22#include <dt-bindings/power/qcom-rpmpd.h> 23#include <dt-bindings/reset/qcom,sdm845-aoss.h> 24#include <dt-bindings/reset/qcom,sdm845-pdc.h> 25#include <dt-bindings/soc/qcom,rpmh-rsc.h> 26#include <dt-bindings/soc/qcom,apr.h> 27#include <dt-bindings/sound/qcom,q6afe.h> 28#include <dt-bindings/thermal/thermal.h> 29 30/ { 31 interrupt-parent = <&intc>; 32 33 #address-cells = <2>; 34 #size-cells = <2>; 35 36 aliases { 37 mmc1 = &sdhc_1; 38 mmc2 = &sdhc_2; 39 i2c0 = &i2c0; 40 i2c1 = &i2c1; 41 i2c2 = &i2c2; 42 i2c3 = &i2c3; 43 i2c4 = &i2c4; 44 i2c5 = &i2c5; 45 i2c6 = &i2c6; 46 i2c7 = &i2c7; 47 i2c8 = &i2c8; 48 i2c9 = &i2c9; 49 i2c10 = &i2c10; 50 i2c11 = &i2c11; 51 spi0 = &spi0; 52 spi1 = &spi1; 53 spi3 = &spi3; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi8 = &spi8; 57 spi10 = &spi10; 58 spi11 = &spi11; 59 }; 60 61 chosen { }; 62 63 clocks { 64 xo_board: xo-board { 65 compatible = "fixed-clock"; 66 clock-frequency = <38400000>; 67 #clock-cells = <0>; 68 }; 69 70 sleep_clk: sleep-clk { 71 compatible = "fixed-clock"; 72 clock-frequency = <32764>; 73 #clock-cells = <0>; 74 }; 75 }; 76 77 cpus { 78 #address-cells = <2>; 79 #size-cells = <0>; 80 81 cpu0: cpu@0 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo468"; 84 reg = <0x0 0x0>; 85 clocks = <&cpufreq_hw 0>; 86 enable-method = "psci"; 87 power-domains = <&cpu_pd0>; 88 power-domain-names = "psci"; 89 capacity-dmips-mhz = <415>; 90 dynamic-power-coefficient = <137>; 91 operating-points-v2 = <&cpu0_opp_table>; 92 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 93 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 94 next-level-cache = <&l2_0>; 95 #cooling-cells = <2>; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 l2_0: l2-cache { 98 compatible = "cache"; 99 cache-level = <2>; 100 cache-unified; 101 next-level-cache = <&l3_0>; 102 l3_0: l3-cache { 103 compatible = "cache"; 104 cache-level = <3>; 105 cache-unified; 106 }; 107 }; 108 }; 109 110 cpu1: cpu@100 { 111 device_type = "cpu"; 112 compatible = "qcom,kryo468"; 113 reg = <0x0 0x100>; 114 clocks = <&cpufreq_hw 0>; 115 enable-method = "psci"; 116 power-domains = <&cpu_pd1>; 117 power-domain-names = "psci"; 118 capacity-dmips-mhz = <415>; 119 dynamic-power-coefficient = <137>; 120 next-level-cache = <&l2_100>; 121 operating-points-v2 = <&cpu0_opp_table>; 122 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 123 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 124 #cooling-cells = <2>; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 l2_100: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 cache-unified; 130 next-level-cache = <&l3_0>; 131 }; 132 }; 133 134 cpu2: cpu@200 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo468"; 137 reg = <0x0 0x200>; 138 clocks = <&cpufreq_hw 0>; 139 enable-method = "psci"; 140 power-domains = <&cpu_pd2>; 141 power-domain-names = "psci"; 142 capacity-dmips-mhz = <415>; 143 dynamic-power-coefficient = <137>; 144 next-level-cache = <&l2_200>; 145 operating-points-v2 = <&cpu0_opp_table>; 146 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 147 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 148 #cooling-cells = <2>; 149 qcom,freq-domain = <&cpufreq_hw 0>; 150 l2_200: l2-cache { 151 compatible = "cache"; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_0>; 155 }; 156 }; 157 158 cpu3: cpu@300 { 159 device_type = "cpu"; 160 compatible = "qcom,kryo468"; 161 reg = <0x0 0x300>; 162 clocks = <&cpufreq_hw 0>; 163 enable-method = "psci"; 164 power-domains = <&cpu_pd3>; 165 power-domain-names = "psci"; 166 capacity-dmips-mhz = <415>; 167 dynamic-power-coefficient = <137>; 168 next-level-cache = <&l2_300>; 169 operating-points-v2 = <&cpu0_opp_table>; 170 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 171 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 172 #cooling-cells = <2>; 173 qcom,freq-domain = <&cpufreq_hw 0>; 174 l2_300: l2-cache { 175 compatible = "cache"; 176 cache-level = <2>; 177 cache-unified; 178 next-level-cache = <&l3_0>; 179 }; 180 }; 181 182 cpu4: cpu@400 { 183 device_type = "cpu"; 184 compatible = "qcom,kryo468"; 185 reg = <0x0 0x400>; 186 clocks = <&cpufreq_hw 0>; 187 enable-method = "psci"; 188 power-domains = <&cpu_pd4>; 189 power-domain-names = "psci"; 190 capacity-dmips-mhz = <415>; 191 dynamic-power-coefficient = <137>; 192 next-level-cache = <&l2_400>; 193 operating-points-v2 = <&cpu0_opp_table>; 194 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 195 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 196 #cooling-cells = <2>; 197 qcom,freq-domain = <&cpufreq_hw 0>; 198 l2_400: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&l3_0>; 203 }; 204 }; 205 206 cpu5: cpu@500 { 207 device_type = "cpu"; 208 compatible = "qcom,kryo468"; 209 reg = <0x0 0x500>; 210 clocks = <&cpufreq_hw 0>; 211 enable-method = "psci"; 212 power-domains = <&cpu_pd5>; 213 power-domain-names = "psci"; 214 capacity-dmips-mhz = <415>; 215 dynamic-power-coefficient = <137>; 216 next-level-cache = <&l2_500>; 217 operating-points-v2 = <&cpu0_opp_table>; 218 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 219 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 220 #cooling-cells = <2>; 221 qcom,freq-domain = <&cpufreq_hw 0>; 222 l2_500: l2-cache { 223 compatible = "cache"; 224 cache-level = <2>; 225 cache-unified; 226 next-level-cache = <&l3_0>; 227 }; 228 }; 229 230 cpu6: cpu@600 { 231 device_type = "cpu"; 232 compatible = "qcom,kryo468"; 233 reg = <0x0 0x600>; 234 clocks = <&cpufreq_hw 1>; 235 enable-method = "psci"; 236 power-domains = <&cpu_pd6>; 237 power-domain-names = "psci"; 238 capacity-dmips-mhz = <1024>; 239 dynamic-power-coefficient = <480>; 240 next-level-cache = <&l2_600>; 241 operating-points-v2 = <&cpu6_opp_table>; 242 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 243 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 244 #cooling-cells = <2>; 245 qcom,freq-domain = <&cpufreq_hw 1>; 246 l2_600: l2-cache { 247 compatible = "cache"; 248 cache-level = <2>; 249 cache-unified; 250 next-level-cache = <&l3_0>; 251 }; 252 }; 253 254 cpu7: cpu@700 { 255 device_type = "cpu"; 256 compatible = "qcom,kryo468"; 257 reg = <0x0 0x700>; 258 clocks = <&cpufreq_hw 1>; 259 enable-method = "psci"; 260 power-domains = <&cpu_pd7>; 261 power-domain-names = "psci"; 262 capacity-dmips-mhz = <1024>; 263 dynamic-power-coefficient = <480>; 264 next-level-cache = <&l2_700>; 265 operating-points-v2 = <&cpu6_opp_table>; 266 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 267 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 268 #cooling-cells = <2>; 269 qcom,freq-domain = <&cpufreq_hw 1>; 270 l2_700: l2-cache { 271 compatible = "cache"; 272 cache-level = <2>; 273 cache-unified; 274 next-level-cache = <&l3_0>; 275 }; 276 }; 277 278 cpu-map { 279 cluster0 { 280 core0 { 281 cpu = <&cpu0>; 282 }; 283 284 core1 { 285 cpu = <&cpu1>; 286 }; 287 288 core2 { 289 cpu = <&cpu2>; 290 }; 291 292 core3 { 293 cpu = <&cpu3>; 294 }; 295 296 core4 { 297 cpu = <&cpu4>; 298 }; 299 300 core5 { 301 cpu = <&cpu5>; 302 }; 303 304 core6 { 305 cpu = <&cpu6>; 306 }; 307 308 core7 { 309 cpu = <&cpu7>; 310 }; 311 }; 312 }; 313 314 idle_states: idle-states { 315 entry-method = "psci"; 316 317 little_cpu_sleep_0: cpu-sleep-0-0 { 318 compatible = "arm,idle-state"; 319 idle-state-name = "little-power-down"; 320 arm,psci-suspend-param = <0x40000003>; 321 entry-latency-us = <549>; 322 exit-latency-us = <901>; 323 min-residency-us = <1774>; 324 local-timer-stop; 325 }; 326 327 little_cpu_sleep_1: cpu-sleep-0-1 { 328 compatible = "arm,idle-state"; 329 idle-state-name = "little-rail-power-down"; 330 arm,psci-suspend-param = <0x40000004>; 331 entry-latency-us = <702>; 332 exit-latency-us = <915>; 333 min-residency-us = <4001>; 334 local-timer-stop; 335 }; 336 337 big_cpu_sleep_0: cpu-sleep-1-0 { 338 compatible = "arm,idle-state"; 339 idle-state-name = "big-power-down"; 340 arm,psci-suspend-param = <0x40000003>; 341 entry-latency-us = <523>; 342 exit-latency-us = <1244>; 343 min-residency-us = <2207>; 344 local-timer-stop; 345 }; 346 347 big_cpu_sleep_1: cpu-sleep-1-1 { 348 compatible = "arm,idle-state"; 349 idle-state-name = "big-rail-power-down"; 350 arm,psci-suspend-param = <0x40000004>; 351 entry-latency-us = <526>; 352 exit-latency-us = <1854>; 353 min-residency-us = <5555>; 354 local-timer-stop; 355 }; 356 }; 357 358 domain_idle_states: domain-idle-states { 359 cluster_sleep_pc: cluster-sleep-0 { 360 compatible = "domain-idle-state"; 361 arm,psci-suspend-param = <0x41000044>; 362 entry-latency-us = <2752>; 363 exit-latency-us = <3048>; 364 min-residency-us = <6118>; 365 }; 366 367 cluster_sleep_cx_ret: cluster-sleep-1 { 368 compatible = "domain-idle-state"; 369 arm,psci-suspend-param = <0x41001244>; 370 entry-latency-us = <3638>; 371 exit-latency-us = <4562>; 372 min-residency-us = <8467>; 373 }; 374 375 cluster_aoss_sleep: cluster-sleep-2 { 376 compatible = "domain-idle-state"; 377 arm,psci-suspend-param = <0x4100b244>; 378 entry-latency-us = <3263>; 379 exit-latency-us = <6562>; 380 min-residency-us = <9826>; 381 }; 382 }; 383 }; 384 385 firmware { 386 scm: scm { 387 compatible = "qcom,scm-sc7180", "qcom,scm"; 388 }; 389 }; 390 391 memory@80000000 { 392 device_type = "memory"; 393 /* We expect the bootloader to fill in the size */ 394 reg = <0 0x80000000 0 0>; 395 }; 396 397 cpu0_opp_table: opp-table-cpu0 { 398 compatible = "operating-points-v2"; 399 opp-shared; 400 401 cpu0_opp1: opp-300000000 { 402 opp-hz = /bits/ 64 <300000000>; 403 opp-peak-kBps = <1200000 4800000>; 404 }; 405 406 cpu0_opp2: opp-576000000 { 407 opp-hz = /bits/ 64 <576000000>; 408 opp-peak-kBps = <1200000 4800000>; 409 }; 410 411 cpu0_opp3: opp-768000000 { 412 opp-hz = /bits/ 64 <768000000>; 413 opp-peak-kBps = <1200000 4800000>; 414 }; 415 416 cpu0_opp4: opp-1017600000 { 417 opp-hz = /bits/ 64 <1017600000>; 418 opp-peak-kBps = <1804000 8908800>; 419 }; 420 421 cpu0_opp5: opp-1248000000 { 422 opp-hz = /bits/ 64 <1248000000>; 423 opp-peak-kBps = <2188000 12902400>; 424 }; 425 426 cpu0_opp6: opp-1324800000 { 427 opp-hz = /bits/ 64 <1324800000>; 428 opp-peak-kBps = <2188000 12902400>; 429 }; 430 431 cpu0_opp7: opp-1516800000 { 432 opp-hz = /bits/ 64 <1516800000>; 433 opp-peak-kBps = <3072000 15052800>; 434 }; 435 436 cpu0_opp8: opp-1612800000 { 437 opp-hz = /bits/ 64 <1612800000>; 438 opp-peak-kBps = <3072000 15052800>; 439 }; 440 441 cpu0_opp9: opp-1708800000 { 442 opp-hz = /bits/ 64 <1708800000>; 443 opp-peak-kBps = <3072000 15052800>; 444 }; 445 446 cpu0_opp10: opp-1804800000 { 447 opp-hz = /bits/ 64 <1804800000>; 448 opp-peak-kBps = <4068000 22425600>; 449 }; 450 }; 451 452 cpu6_opp_table: opp-table-cpu6 { 453 compatible = "operating-points-v2"; 454 opp-shared; 455 456 cpu6_opp1: opp-300000000 { 457 opp-hz = /bits/ 64 <300000000>; 458 opp-peak-kBps = <2188000 8908800>; 459 }; 460 461 cpu6_opp2: opp-652800000 { 462 opp-hz = /bits/ 64 <652800000>; 463 opp-peak-kBps = <2188000 8908800>; 464 }; 465 466 cpu6_opp3: opp-825600000 { 467 opp-hz = /bits/ 64 <825600000>; 468 opp-peak-kBps = <2188000 8908800>; 469 }; 470 471 cpu6_opp4: opp-979200000 { 472 opp-hz = /bits/ 64 <979200000>; 473 opp-peak-kBps = <2188000 8908800>; 474 }; 475 476 cpu6_opp5: opp-1113600000 { 477 opp-hz = /bits/ 64 <1113600000>; 478 opp-peak-kBps = <2188000 8908800>; 479 }; 480 481 cpu6_opp6: opp-1267200000 { 482 opp-hz = /bits/ 64 <1267200000>; 483 opp-peak-kBps = <4068000 12902400>; 484 }; 485 486 cpu6_opp7: opp-1555200000 { 487 opp-hz = /bits/ 64 <1555200000>; 488 opp-peak-kBps = <4068000 15052800>; 489 }; 490 491 cpu6_opp8: opp-1708800000 { 492 opp-hz = /bits/ 64 <1708800000>; 493 opp-peak-kBps = <6220000 19353600>; 494 }; 495 496 cpu6_opp9: opp-1843200000 { 497 opp-hz = /bits/ 64 <1843200000>; 498 opp-peak-kBps = <6220000 19353600>; 499 }; 500 501 cpu6_opp10: opp-1900800000 { 502 opp-hz = /bits/ 64 <1900800000>; 503 opp-peak-kBps = <6220000 22425600>; 504 }; 505 506 cpu6_opp11: opp-1996800000 { 507 opp-hz = /bits/ 64 <1996800000>; 508 opp-peak-kBps = <6220000 22425600>; 509 }; 510 511 cpu6_opp12: opp-2112000000 { 512 opp-hz = /bits/ 64 <2112000000>; 513 opp-peak-kBps = <6220000 22425600>; 514 }; 515 516 cpu6_opp13: opp-2208000000 { 517 opp-hz = /bits/ 64 <2208000000>; 518 opp-peak-kBps = <7216000 22425600>; 519 }; 520 521 cpu6_opp14: opp-2323200000 { 522 opp-hz = /bits/ 64 <2323200000>; 523 opp-peak-kBps = <7216000 22425600>; 524 }; 525 526 cpu6_opp15: opp-2400000000 { 527 opp-hz = /bits/ 64 <2400000000>; 528 opp-peak-kBps = <8532000 23347200>; 529 }; 530 531 cpu6_opp16: opp-2553600000 { 532 opp-hz = /bits/ 64 <2553600000>; 533 opp-peak-kBps = <8532000 23347200>; 534 }; 535 }; 536 537 qspi_opp_table: opp-table-qspi { 538 compatible = "operating-points-v2"; 539 540 opp-75000000 { 541 opp-hz = /bits/ 64 <75000000>; 542 required-opps = <&rpmhpd_opp_low_svs>; 543 }; 544 545 opp-150000000 { 546 opp-hz = /bits/ 64 <150000000>; 547 required-opps = <&rpmhpd_opp_svs>; 548 }; 549 550 opp-300000000 { 551 opp-hz = /bits/ 64 <300000000>; 552 required-opps = <&rpmhpd_opp_nom>; 553 }; 554 }; 555 556 qup_opp_table: opp-table-qup { 557 compatible = "operating-points-v2"; 558 559 opp-75000000 { 560 opp-hz = /bits/ 64 <75000000>; 561 required-opps = <&rpmhpd_opp_low_svs>; 562 }; 563 564 opp-100000000 { 565 opp-hz = /bits/ 64 <100000000>; 566 required-opps = <&rpmhpd_opp_svs>; 567 }; 568 569 opp-128000000 { 570 opp-hz = /bits/ 64 <128000000>; 571 required-opps = <&rpmhpd_opp_nom>; 572 }; 573 }; 574 575 pmu { 576 compatible = "arm,armv8-pmuv3"; 577 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 578 }; 579 580 psci { 581 compatible = "arm,psci-1.0"; 582 method = "smc"; 583 584 cpu_pd0: power-domain-cpu0 { 585 #power-domain-cells = <0>; 586 power-domains = <&cluster_pd>; 587 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 588 }; 589 590 cpu_pd1: power-domain-cpu1 { 591 #power-domain-cells = <0>; 592 power-domains = <&cluster_pd>; 593 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 594 }; 595 596 cpu_pd2: power-domain-cpu2 { 597 #power-domain-cells = <0>; 598 power-domains = <&cluster_pd>; 599 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 600 }; 601 602 cpu_pd3: power-domain-cpu3 { 603 #power-domain-cells = <0>; 604 power-domains = <&cluster_pd>; 605 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 606 }; 607 608 cpu_pd4: power-domain-cpu4 { 609 #power-domain-cells = <0>; 610 power-domains = <&cluster_pd>; 611 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 612 }; 613 614 cpu_pd5: power-domain-cpu5 { 615 #power-domain-cells = <0>; 616 power-domains = <&cluster_pd>; 617 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 618 }; 619 620 cpu_pd6: power-domain-cpu6 { 621 #power-domain-cells = <0>; 622 power-domains = <&cluster_pd>; 623 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 624 }; 625 626 cpu_pd7: power-domain-cpu7 { 627 #power-domain-cells = <0>; 628 power-domains = <&cluster_pd>; 629 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 630 }; 631 632 cluster_pd: power-domain-cluster { 633 #power-domain-cells = <0>; 634 domain-idle-states = <&cluster_sleep_pc 635 &cluster_sleep_cx_ret 636 &cluster_aoss_sleep>; 637 }; 638 }; 639 640 reserved_memory: reserved-memory { 641 #address-cells = <2>; 642 #size-cells = <2>; 643 ranges; 644 645 hyp_mem: memory@80000000 { 646 reg = <0x0 0x80000000 0x0 0x600000>; 647 no-map; 648 }; 649 650 xbl_mem: memory@80600000 { 651 reg = <0x0 0x80600000 0x0 0x200000>; 652 no-map; 653 }; 654 655 aop_mem: memory@80800000 { 656 reg = <0x0 0x80800000 0x0 0x20000>; 657 no-map; 658 }; 659 660 aop_cmd_db_mem: memory@80820000 { 661 reg = <0x0 0x80820000 0x0 0x20000>; 662 compatible = "qcom,cmd-db"; 663 no-map; 664 }; 665 666 sec_apps_mem: memory@808ff000 { 667 reg = <0x0 0x808ff000 0x0 0x1000>; 668 no-map; 669 }; 670 671 smem_mem: memory@80900000 { 672 reg = <0x0 0x80900000 0x0 0x200000>; 673 no-map; 674 }; 675 676 tz_mem: memory@80b00000 { 677 reg = <0x0 0x80b00000 0x0 0x3900000>; 678 no-map; 679 }; 680 681 ipa_fw_mem: memory@8b700000 { 682 reg = <0 0x8b700000 0 0x10000>; 683 no-map; 684 }; 685 686 rmtfs_mem: memory@94600000 { 687 compatible = "qcom,rmtfs-mem"; 688 reg = <0x0 0x94600000 0x0 0x200000>; 689 no-map; 690 691 qcom,client-id = <1>; 692 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 693 }; 694 }; 695 696 smem { 697 compatible = "qcom,smem"; 698 memory-region = <&smem_mem>; 699 hwlocks = <&tcsr_mutex 3>; 700 }; 701 702 smp2p-cdsp { 703 compatible = "qcom,smp2p"; 704 qcom,smem = <94>, <432>; 705 706 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 707 708 mboxes = <&apss_shared 6>; 709 710 qcom,local-pid = <0>; 711 qcom,remote-pid = <5>; 712 713 cdsp_smp2p_out: master-kernel { 714 qcom,entry-name = "master-kernel"; 715 #qcom,smem-state-cells = <1>; 716 }; 717 718 cdsp_smp2p_in: slave-kernel { 719 qcom,entry-name = "slave-kernel"; 720 721 interrupt-controller; 722 #interrupt-cells = <2>; 723 }; 724 }; 725 726 smp2p-lpass { 727 compatible = "qcom,smp2p"; 728 qcom,smem = <443>, <429>; 729 730 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 731 732 mboxes = <&apss_shared 10>; 733 734 qcom,local-pid = <0>; 735 qcom,remote-pid = <2>; 736 737 adsp_smp2p_out: master-kernel { 738 qcom,entry-name = "master-kernel"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 adsp_smp2p_in: slave-kernel { 743 qcom,entry-name = "slave-kernel"; 744 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 smp2p-mpss { 751 compatible = "qcom,smp2p"; 752 qcom,smem = <435>, <428>; 753 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 754 mboxes = <&apss_shared 14>; 755 qcom,local-pid = <0>; 756 qcom,remote-pid = <1>; 757 758 modem_smp2p_out: master-kernel { 759 qcom,entry-name = "master-kernel"; 760 #qcom,smem-state-cells = <1>; 761 }; 762 763 modem_smp2p_in: slave-kernel { 764 qcom,entry-name = "slave-kernel"; 765 interrupt-controller; 766 #interrupt-cells = <2>; 767 }; 768 769 ipa_smp2p_out: ipa-ap-to-modem { 770 qcom,entry-name = "ipa"; 771 #qcom,smem-state-cells = <1>; 772 }; 773 774 ipa_smp2p_in: ipa-modem-to-ap { 775 qcom,entry-name = "ipa"; 776 interrupt-controller; 777 #interrupt-cells = <2>; 778 }; 779 }; 780 781 soc: soc@0 { 782 #address-cells = <2>; 783 #size-cells = <2>; 784 ranges = <0 0 0 0 0x10 0>; 785 dma-ranges = <0 0 0 0 0x10 0>; 786 compatible = "simple-bus"; 787 788 gcc: clock-controller@100000 { 789 compatible = "qcom,gcc-sc7180"; 790 reg = <0 0x00100000 0 0x1f0000>; 791 clocks = <&rpmhcc RPMH_CXO_CLK>, 792 <&rpmhcc RPMH_CXO_CLK_A>, 793 <&sleep_clk>; 794 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 795 #clock-cells = <1>; 796 #reset-cells = <1>; 797 #power-domain-cells = <1>; 798 power-domains = <&rpmhpd SC7180_CX>; 799 }; 800 801 qfprom: efuse@784000 { 802 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 803 reg = <0 0x00784000 0 0x7a0>, 804 <0 0x00780000 0 0x7a0>, 805 <0 0x00782000 0 0x100>, 806 <0 0x00786000 0 0x1fff>; 807 808 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 809 clock-names = "core"; 810 #address-cells = <1>; 811 #size-cells = <1>; 812 813 qusb2p_hstx_trim: hstx-trim-primary@25b { 814 reg = <0x25b 0x1>; 815 bits = <1 3>; 816 }; 817 818 gpu_speed_bin: gpu-speed-bin@1d2 { 819 reg = <0x1d2 0x2>; 820 bits = <5 8>; 821 }; 822 }; 823 824 sdhc_1: mmc@7c4000 { 825 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 826 reg = <0 0x007c4000 0 0x1000>, 827 <0 0x007c5000 0 0x1000>; 828 reg-names = "hc", "cqhci"; 829 830 iommus = <&apps_smmu 0x60 0x0>; 831 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 833 interrupt-names = "hc_irq", "pwr_irq"; 834 835 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 836 <&gcc GCC_SDCC1_APPS_CLK>, 837 <&rpmhcc RPMH_CXO_CLK>; 838 clock-names = "iface", "core", "xo"; 839 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 840 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 841 interconnect-names = "sdhc-ddr","cpu-sdhc"; 842 power-domains = <&rpmhpd SC7180_CX>; 843 operating-points-v2 = <&sdhc1_opp_table>; 844 845 bus-width = <8>; 846 non-removable; 847 supports-cqe; 848 849 mmc-ddr-1_8v; 850 mmc-hs200-1_8v; 851 mmc-hs400-1_8v; 852 mmc-hs400-enhanced-strobe; 853 854 status = "disabled"; 855 856 sdhc1_opp_table: opp-table { 857 compatible = "operating-points-v2"; 858 859 opp-100000000 { 860 opp-hz = /bits/ 64 <100000000>; 861 required-opps = <&rpmhpd_opp_low_svs>; 862 opp-peak-kBps = <1800000 600000>; 863 opp-avg-kBps = <100000 0>; 864 }; 865 866 opp-384000000 { 867 opp-hz = /bits/ 64 <384000000>; 868 required-opps = <&rpmhpd_opp_nom>; 869 opp-peak-kBps = <5400000 1600000>; 870 opp-avg-kBps = <390000 0>; 871 }; 872 }; 873 }; 874 875 qupv3_id_0: geniqup@8c0000 { 876 compatible = "qcom,geni-se-qup"; 877 reg = <0 0x008c0000 0 0x6000>; 878 clock-names = "m-ahb", "s-ahb"; 879 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 880 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 881 #address-cells = <2>; 882 #size-cells = <2>; 883 ranges; 884 iommus = <&apps_smmu 0x43 0x0>; 885 status = "disabled"; 886 887 i2c0: i2c@880000 { 888 compatible = "qcom,geni-i2c"; 889 reg = <0 0x00880000 0 0x4000>; 890 clock-names = "se"; 891 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&qup_i2c0_default>; 894 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 898 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 899 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 900 interconnect-names = "qup-core", "qup-config", 901 "qup-memory"; 902 power-domains = <&rpmhpd SC7180_CX>; 903 required-opps = <&rpmhpd_opp_low_svs>; 904 status = "disabled"; 905 }; 906 907 spi0: spi@880000 { 908 compatible = "qcom,geni-spi"; 909 reg = <0 0x00880000 0 0x4000>; 910 clock-names = "se"; 911 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>; 914 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 power-domains = <&rpmhpd SC7180_CX>; 918 operating-points-v2 = <&qup_opp_table>; 919 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 920 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 921 interconnect-names = "qup-core", "qup-config"; 922 status = "disabled"; 923 }; 924 925 uart0: serial@880000 { 926 compatible = "qcom,geni-uart"; 927 reg = <0 0x00880000 0 0x4000>; 928 clock-names = "se"; 929 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 930 pinctrl-names = "default"; 931 pinctrl-0 = <&qup_uart0_default>; 932 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 933 power-domains = <&rpmhpd SC7180_CX>; 934 operating-points-v2 = <&qup_opp_table>; 935 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 937 interconnect-names = "qup-core", "qup-config"; 938 status = "disabled"; 939 }; 940 941 i2c1: i2c@884000 { 942 compatible = "qcom,geni-i2c"; 943 reg = <0 0x00884000 0 0x4000>; 944 clock-names = "se"; 945 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&qup_i2c1_default>; 948 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 952 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 953 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 954 interconnect-names = "qup-core", "qup-config", 955 "qup-memory"; 956 power-domains = <&rpmhpd SC7180_CX>; 957 required-opps = <&rpmhpd_opp_low_svs>; 958 status = "disabled"; 959 }; 960 961 spi1: spi@884000 { 962 compatible = "qcom,geni-spi"; 963 reg = <0 0x00884000 0 0x4000>; 964 clock-names = "se"; 965 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>; 968 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 power-domains = <&rpmhpd SC7180_CX>; 972 operating-points-v2 = <&qup_opp_table>; 973 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 974 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 975 interconnect-names = "qup-core", "qup-config"; 976 status = "disabled"; 977 }; 978 979 uart1: serial@884000 { 980 compatible = "qcom,geni-uart"; 981 reg = <0 0x00884000 0 0x4000>; 982 clock-names = "se"; 983 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_uart1_default>; 986 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 987 power-domains = <&rpmhpd SC7180_CX>; 988 operating-points-v2 = <&qup_opp_table>; 989 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 990 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 991 interconnect-names = "qup-core", "qup-config"; 992 status = "disabled"; 993 }; 994 995 i2c2: i2c@888000 { 996 compatible = "qcom,geni-i2c"; 997 reg = <0 0x00888000 0 0x4000>; 998 clock-names = "se"; 999 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_i2c2_default>; 1002 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1006 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1007 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1008 interconnect-names = "qup-core", "qup-config", 1009 "qup-memory"; 1010 power-domains = <&rpmhpd SC7180_CX>; 1011 required-opps = <&rpmhpd_opp_low_svs>; 1012 status = "disabled"; 1013 }; 1014 1015 uart2: serial@888000 { 1016 compatible = "qcom,geni-uart"; 1017 reg = <0 0x00888000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_uart2_default>; 1022 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1023 power-domains = <&rpmhpd SC7180_CX>; 1024 operating-points-v2 = <&qup_opp_table>; 1025 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1026 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1027 interconnect-names = "qup-core", "qup-config"; 1028 status = "disabled"; 1029 }; 1030 1031 i2c3: i2c@88c000 { 1032 compatible = "qcom,geni-i2c"; 1033 reg = <0 0x0088c000 0 0x4000>; 1034 clock-names = "se"; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1036 pinctrl-names = "default"; 1037 pinctrl-0 = <&qup_i2c3_default>; 1038 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1042 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1043 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1044 interconnect-names = "qup-core", "qup-config", 1045 "qup-memory"; 1046 power-domains = <&rpmhpd SC7180_CX>; 1047 required-opps = <&rpmhpd_opp_low_svs>; 1048 status = "disabled"; 1049 }; 1050 1051 spi3: spi@88c000 { 1052 compatible = "qcom,geni-spi"; 1053 reg = <0 0x0088c000 0 0x4000>; 1054 clock-names = "se"; 1055 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1056 pinctrl-names = "default"; 1057 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>; 1058 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 power-domains = <&rpmhpd SC7180_CX>; 1062 operating-points-v2 = <&qup_opp_table>; 1063 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1064 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1065 interconnect-names = "qup-core", "qup-config"; 1066 status = "disabled"; 1067 }; 1068 1069 uart3: serial@88c000 { 1070 compatible = "qcom,geni-uart"; 1071 reg = <0 0x0088c000 0 0x4000>; 1072 clock-names = "se"; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&qup_uart3_default>; 1076 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1077 power-domains = <&rpmhpd SC7180_CX>; 1078 operating-points-v2 = <&qup_opp_table>; 1079 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1080 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1081 interconnect-names = "qup-core", "qup-config"; 1082 status = "disabled"; 1083 }; 1084 1085 i2c4: i2c@890000 { 1086 compatible = "qcom,geni-i2c"; 1087 reg = <0 0x00890000 0 0x4000>; 1088 clock-names = "se"; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1090 pinctrl-names = "default"; 1091 pinctrl-0 = <&qup_i2c4_default>; 1092 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1096 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1097 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1098 interconnect-names = "qup-core", "qup-config", 1099 "qup-memory"; 1100 power-domains = <&rpmhpd SC7180_CX>; 1101 required-opps = <&rpmhpd_opp_low_svs>; 1102 status = "disabled"; 1103 }; 1104 1105 uart4: serial@890000 { 1106 compatible = "qcom,geni-uart"; 1107 reg = <0 0x00890000 0 0x4000>; 1108 clock-names = "se"; 1109 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&qup_uart4_default>; 1112 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1113 power-domains = <&rpmhpd SC7180_CX>; 1114 operating-points-v2 = <&qup_opp_table>; 1115 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1116 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1117 interconnect-names = "qup-core", "qup-config"; 1118 status = "disabled"; 1119 }; 1120 1121 i2c5: i2c@894000 { 1122 compatible = "qcom,geni-i2c"; 1123 reg = <0 0x00894000 0 0x4000>; 1124 clock-names = "se"; 1125 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1126 pinctrl-names = "default"; 1127 pinctrl-0 = <&qup_i2c5_default>; 1128 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1132 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1133 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1134 interconnect-names = "qup-core", "qup-config", 1135 "qup-memory"; 1136 power-domains = <&rpmhpd SC7180_CX>; 1137 required-opps = <&rpmhpd_opp_low_svs>; 1138 status = "disabled"; 1139 }; 1140 1141 spi5: spi@894000 { 1142 compatible = "qcom,geni-spi"; 1143 reg = <0 0x00894000 0 0x4000>; 1144 clock-names = "se"; 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>; 1148 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 power-domains = <&rpmhpd SC7180_CX>; 1152 operating-points-v2 = <&qup_opp_table>; 1153 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1154 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1155 interconnect-names = "qup-core", "qup-config"; 1156 status = "disabled"; 1157 }; 1158 1159 uart5: serial@894000 { 1160 compatible = "qcom,geni-uart"; 1161 reg = <0 0x00894000 0 0x4000>; 1162 clock-names = "se"; 1163 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&qup_uart5_default>; 1166 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1167 power-domains = <&rpmhpd SC7180_CX>; 1168 operating-points-v2 = <&qup_opp_table>; 1169 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1170 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1171 interconnect-names = "qup-core", "qup-config"; 1172 status = "disabled"; 1173 }; 1174 }; 1175 1176 qupv3_id_1: geniqup@ac0000 { 1177 compatible = "qcom,geni-se-qup"; 1178 reg = <0 0x00ac0000 0 0x6000>; 1179 clock-names = "m-ahb", "s-ahb"; 1180 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1181 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1182 #address-cells = <2>; 1183 #size-cells = <2>; 1184 ranges; 1185 iommus = <&apps_smmu 0x4c3 0x0>; 1186 status = "disabled"; 1187 1188 i2c6: i2c@a80000 { 1189 compatible = "qcom,geni-i2c"; 1190 reg = <0 0x00a80000 0 0x4000>; 1191 clock-names = "se"; 1192 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_i2c6_default>; 1195 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1199 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1200 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1201 interconnect-names = "qup-core", "qup-config", 1202 "qup-memory"; 1203 power-domains = <&rpmhpd SC7180_CX>; 1204 required-opps = <&rpmhpd_opp_low_svs>; 1205 status = "disabled"; 1206 }; 1207 1208 spi6: spi@a80000 { 1209 compatible = "qcom,geni-spi"; 1210 reg = <0 0x00a80000 0 0x4000>; 1211 clock-names = "se"; 1212 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1213 pinctrl-names = "default"; 1214 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>; 1215 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 power-domains = <&rpmhpd SC7180_CX>; 1219 operating-points-v2 = <&qup_opp_table>; 1220 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1222 interconnect-names = "qup-core", "qup-config"; 1223 status = "disabled"; 1224 }; 1225 1226 uart6: serial@a80000 { 1227 compatible = "qcom,geni-uart"; 1228 reg = <0 0x00a80000 0 0x4000>; 1229 clock-names = "se"; 1230 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&qup_uart6_default>; 1233 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1234 power-domains = <&rpmhpd SC7180_CX>; 1235 operating-points-v2 = <&qup_opp_table>; 1236 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1238 interconnect-names = "qup-core", "qup-config"; 1239 status = "disabled"; 1240 }; 1241 1242 i2c7: i2c@a84000 { 1243 compatible = "qcom,geni-i2c"; 1244 reg = <0 0x00a84000 0 0x4000>; 1245 clock-names = "se"; 1246 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1247 pinctrl-names = "default"; 1248 pinctrl-0 = <&qup_i2c7_default>; 1249 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1253 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1254 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1255 interconnect-names = "qup-core", "qup-config", 1256 "qup-memory"; 1257 power-domains = <&rpmhpd SC7180_CX>; 1258 required-opps = <&rpmhpd_opp_low_svs>; 1259 status = "disabled"; 1260 }; 1261 1262 uart7: serial@a84000 { 1263 compatible = "qcom,geni-uart"; 1264 reg = <0 0x00a84000 0 0x4000>; 1265 clock-names = "se"; 1266 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&qup_uart7_default>; 1269 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1270 power-domains = <&rpmhpd SC7180_CX>; 1271 operating-points-v2 = <&qup_opp_table>; 1272 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1273 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1274 interconnect-names = "qup-core", "qup-config"; 1275 status = "disabled"; 1276 }; 1277 1278 i2c8: i2c@a88000 { 1279 compatible = "qcom,geni-i2c"; 1280 reg = <0 0x00a88000 0 0x4000>; 1281 clock-names = "se"; 1282 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_i2c8_default>; 1285 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1290 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1291 interconnect-names = "qup-core", "qup-config", 1292 "qup-memory"; 1293 power-domains = <&rpmhpd SC7180_CX>; 1294 required-opps = <&rpmhpd_opp_low_svs>; 1295 status = "disabled"; 1296 }; 1297 1298 spi8: spi@a88000 { 1299 compatible = "qcom,geni-spi"; 1300 reg = <0 0x00a88000 0 0x4000>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>; 1305 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 power-domains = <&rpmhpd SC7180_CX>; 1309 operating-points-v2 = <&qup_opp_table>; 1310 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1311 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1312 interconnect-names = "qup-core", "qup-config"; 1313 status = "disabled"; 1314 }; 1315 1316 uart8: serial@a88000 { 1317 compatible = "qcom,geni-debug-uart"; 1318 reg = <0 0x00a88000 0 0x4000>; 1319 clock-names = "se"; 1320 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_uart8_default>; 1323 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1324 power-domains = <&rpmhpd SC7180_CX>; 1325 operating-points-v2 = <&qup_opp_table>; 1326 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1327 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1328 interconnect-names = "qup-core", "qup-config"; 1329 status = "disabled"; 1330 }; 1331 1332 i2c9: i2c@a8c000 { 1333 compatible = "qcom,geni-i2c"; 1334 reg = <0 0x00a8c000 0 0x4000>; 1335 clock-names = "se"; 1336 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1337 pinctrl-names = "default"; 1338 pinctrl-0 = <&qup_i2c9_default>; 1339 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1343 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1344 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1345 interconnect-names = "qup-core", "qup-config", 1346 "qup-memory"; 1347 power-domains = <&rpmhpd SC7180_CX>; 1348 required-opps = <&rpmhpd_opp_low_svs>; 1349 status = "disabled"; 1350 }; 1351 1352 uart9: serial@a8c000 { 1353 compatible = "qcom,geni-uart"; 1354 reg = <0 0x00a8c000 0 0x4000>; 1355 clock-names = "se"; 1356 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1357 pinctrl-names = "default"; 1358 pinctrl-0 = <&qup_uart9_default>; 1359 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1360 power-domains = <&rpmhpd SC7180_CX>; 1361 operating-points-v2 = <&qup_opp_table>; 1362 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1364 interconnect-names = "qup-core", "qup-config"; 1365 status = "disabled"; 1366 }; 1367 1368 i2c10: i2c@a90000 { 1369 compatible = "qcom,geni-i2c"; 1370 reg = <0 0x00a90000 0 0x4000>; 1371 clock-names = "se"; 1372 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1373 pinctrl-names = "default"; 1374 pinctrl-0 = <&qup_i2c10_default>; 1375 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1376 #address-cells = <1>; 1377 #size-cells = <0>; 1378 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1379 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1380 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1381 interconnect-names = "qup-core", "qup-config", 1382 "qup-memory"; 1383 power-domains = <&rpmhpd SC7180_CX>; 1384 required-opps = <&rpmhpd_opp_low_svs>; 1385 status = "disabled"; 1386 }; 1387 1388 spi10: spi@a90000 { 1389 compatible = "qcom,geni-spi"; 1390 reg = <0 0x00a90000 0 0x4000>; 1391 clock-names = "se"; 1392 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1393 pinctrl-names = "default"; 1394 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>; 1395 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 power-domains = <&rpmhpd SC7180_CX>; 1399 operating-points-v2 = <&qup_opp_table>; 1400 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1401 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1402 interconnect-names = "qup-core", "qup-config"; 1403 status = "disabled"; 1404 }; 1405 1406 uart10: serial@a90000 { 1407 compatible = "qcom,geni-uart"; 1408 reg = <0 0x00a90000 0 0x4000>; 1409 clock-names = "se"; 1410 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1411 pinctrl-names = "default"; 1412 pinctrl-0 = <&qup_uart10_default>; 1413 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1414 power-domains = <&rpmhpd SC7180_CX>; 1415 operating-points-v2 = <&qup_opp_table>; 1416 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1417 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1418 interconnect-names = "qup-core", "qup-config"; 1419 status = "disabled"; 1420 }; 1421 1422 i2c11: i2c@a94000 { 1423 compatible = "qcom,geni-i2c"; 1424 reg = <0 0x00a94000 0 0x4000>; 1425 clock-names = "se"; 1426 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1427 pinctrl-names = "default"; 1428 pinctrl-0 = <&qup_i2c11_default>; 1429 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1433 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1434 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1435 interconnect-names = "qup-core", "qup-config", 1436 "qup-memory"; 1437 power-domains = <&rpmhpd SC7180_CX>; 1438 required-opps = <&rpmhpd_opp_low_svs>; 1439 status = "disabled"; 1440 }; 1441 1442 spi11: spi@a94000 { 1443 compatible = "qcom,geni-spi"; 1444 reg = <0 0x00a94000 0 0x4000>; 1445 clock-names = "se"; 1446 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>; 1449 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 power-domains = <&rpmhpd SC7180_CX>; 1453 operating-points-v2 = <&qup_opp_table>; 1454 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1455 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1456 interconnect-names = "qup-core", "qup-config"; 1457 status = "disabled"; 1458 }; 1459 1460 uart11: serial@a94000 { 1461 compatible = "qcom,geni-uart"; 1462 reg = <0 0x00a94000 0 0x4000>; 1463 clock-names = "se"; 1464 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1465 pinctrl-names = "default"; 1466 pinctrl-0 = <&qup_uart11_default>; 1467 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1468 power-domains = <&rpmhpd SC7180_CX>; 1469 operating-points-v2 = <&qup_opp_table>; 1470 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1471 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1472 interconnect-names = "qup-core", "qup-config"; 1473 status = "disabled"; 1474 }; 1475 }; 1476 1477 refgen: regulator@ff1000 { 1478 compatible = "qcom,sc7180-refgen-regulator", 1479 "qcom,sdm845-refgen-regulator"; 1480 reg = <0x0 0x00ff1000 0x0 0x60>; 1481 }; 1482 1483 config_noc: interconnect@1500000 { 1484 compatible = "qcom,sc7180-config-noc"; 1485 reg = <0 0x01500000 0 0x28000>; 1486 #interconnect-cells = <2>; 1487 qcom,bcm-voters = <&apps_bcm_voter>; 1488 }; 1489 1490 system_noc: interconnect@1620000 { 1491 compatible = "qcom,sc7180-system-noc"; 1492 reg = <0 0x01620000 0 0x17080>; 1493 #interconnect-cells = <2>; 1494 qcom,bcm-voters = <&apps_bcm_voter>; 1495 }; 1496 1497 mc_virt: interconnect@1638000 { 1498 compatible = "qcom,sc7180-mc-virt"; 1499 reg = <0 0x01638000 0 0x1000>; 1500 #interconnect-cells = <2>; 1501 qcom,bcm-voters = <&apps_bcm_voter>; 1502 }; 1503 1504 qup_virt: interconnect@1650000 { 1505 compatible = "qcom,sc7180-qup-virt"; 1506 reg = <0 0x01650000 0 0x1000>; 1507 #interconnect-cells = <2>; 1508 qcom,bcm-voters = <&apps_bcm_voter>; 1509 }; 1510 1511 aggre1_noc: interconnect@16e0000 { 1512 compatible = "qcom,sc7180-aggre1-noc"; 1513 reg = <0 0x016e0000 0 0x15080>; 1514 #interconnect-cells = <2>; 1515 qcom,bcm-voters = <&apps_bcm_voter>; 1516 }; 1517 1518 aggre2_noc: interconnect@1705000 { 1519 compatible = "qcom,sc7180-aggre2-noc"; 1520 reg = <0 0x01705000 0 0x9000>; 1521 #interconnect-cells = <2>; 1522 qcom,bcm-voters = <&apps_bcm_voter>; 1523 }; 1524 1525 compute_noc: interconnect@170e000 { 1526 compatible = "qcom,sc7180-compute-noc"; 1527 reg = <0 0x0170e000 0 0x6000>; 1528 #interconnect-cells = <2>; 1529 qcom,bcm-voters = <&apps_bcm_voter>; 1530 }; 1531 1532 mmss_noc: interconnect@1740000 { 1533 compatible = "qcom,sc7180-mmss-noc"; 1534 reg = <0 0x01740000 0 0x1c100>; 1535 #interconnect-cells = <2>; 1536 qcom,bcm-voters = <&apps_bcm_voter>; 1537 }; 1538 1539 ufs_mem_hc: ufshc@1d84000 { 1540 compatible = "qcom,sc7180-ufshc", "qcom,ufshc", 1541 "jedec,ufs-2.0"; 1542 reg = <0 0x01d84000 0 0x3000>; 1543 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1544 phys = <&ufs_mem_phy>; 1545 phy-names = "ufsphy"; 1546 lanes-per-direction = <1>; 1547 #reset-cells = <1>; 1548 resets = <&gcc GCC_UFS_PHY_BCR>; 1549 reset-names = "rst"; 1550 1551 power-domains = <&gcc UFS_PHY_GDSC>; 1552 1553 iommus = <&apps_smmu 0xa0 0x0>; 1554 1555 clock-names = "core_clk", 1556 "bus_aggr_clk", 1557 "iface_clk", 1558 "core_clk_unipro", 1559 "ref_clk", 1560 "tx_lane0_sync_clk", 1561 "rx_lane0_sync_clk"; 1562 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1563 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1564 <&gcc GCC_UFS_PHY_AHB_CLK>, 1565 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1566 <&rpmhcc RPMH_CXO_CLK>, 1567 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1568 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; 1569 freq-table-hz = <50000000 200000000>, 1570 <0 0>, 1571 <0 0>, 1572 <37500000 150000000>, 1573 <0 0>, 1574 <0 0>, 1575 <0 0>; 1576 1577 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1578 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1579 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1580 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 1581 interconnect-names = "ufs-ddr", "cpu-ufs"; 1582 1583 qcom,ice = <&ice>; 1584 1585 status = "disabled"; 1586 }; 1587 1588 ufs_mem_phy: phy@1d87000 { 1589 compatible = "qcom,sc7180-qmp-ufs-phy"; 1590 reg = <0 0x01d87000 0 0x1000>; 1591 clocks = <&rpmhcc RPMH_CXO_CLK>, 1592 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1593 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1594 clock-names = "ref", 1595 "ref_aux", 1596 "qref"; 1597 power-domains = <&gcc UFS_PHY_GDSC>; 1598 resets = <&ufs_mem_hc 0>; 1599 reset-names = "ufsphy"; 1600 #phy-cells = <0>; 1601 status = "disabled"; 1602 }; 1603 1604 ice: crypto@1d90000 { 1605 compatible = "qcom,sc7180-inline-crypto-engine", 1606 "qcom,inline-crypto-engine"; 1607 reg = <0 0x01d90000 0 0x8000>; 1608 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1609 }; 1610 1611 ipa: ipa@1e40000 { 1612 compatible = "qcom,sc7180-ipa"; 1613 1614 iommus = <&apps_smmu 0x440 0x0>, 1615 <&apps_smmu 0x442 0x0>; 1616 reg = <0 0x01e40000 0 0x7000>, 1617 <0 0x01e47000 0 0x2000>, 1618 <0 0x01e04000 0 0x2c000>; 1619 reg-names = "ipa-reg", 1620 "ipa-shared", 1621 "gsi"; 1622 1623 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1624 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1625 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1626 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1627 interrupt-names = "ipa", 1628 "gsi", 1629 "ipa-clock-query", 1630 "ipa-setup-ready"; 1631 1632 clocks = <&rpmhcc RPMH_IPA_CLK>; 1633 clock-names = "core"; 1634 1635 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1636 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1637 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1638 interconnect-names = "memory", 1639 "imem", 1640 "config"; 1641 1642 qcom,qmp = <&aoss_qmp>; 1643 1644 qcom,smem-states = <&ipa_smp2p_out 0>, 1645 <&ipa_smp2p_out 1>; 1646 qcom,smem-state-names = "ipa-clock-enabled-valid", 1647 "ipa-clock-enabled"; 1648 1649 sram = <&ipa_modem_tables>; 1650 1651 status = "disabled"; 1652 }; 1653 1654 tcsr_mutex: hwlock@1f40000 { 1655 compatible = "qcom,tcsr-mutex"; 1656 reg = <0 0x01f40000 0 0x20000>; 1657 #hwlock-cells = <1>; 1658 }; 1659 1660 tcsr_regs_1: syscon@1f60000 { 1661 compatible = "qcom,sc7180-tcsr", "syscon"; 1662 reg = <0 0x01f60000 0 0x20000>; 1663 }; 1664 1665 tcsr_regs_2: syscon@1fc0000 { 1666 compatible = "qcom,sc7180-tcsr", "syscon"; 1667 reg = <0 0x01fc0000 0 0x40000>; 1668 }; 1669 1670 tlmm: pinctrl@3500000 { 1671 compatible = "qcom,sc7180-pinctrl"; 1672 reg = <0 0x03500000 0 0x300000>, 1673 <0 0x03900000 0 0x300000>, 1674 <0 0x03d00000 0 0x300000>; 1675 reg-names = "west", "north", "south"; 1676 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1677 gpio-controller; 1678 #gpio-cells = <2>; 1679 interrupt-controller; 1680 #interrupt-cells = <2>; 1681 gpio-ranges = <&tlmm 0 0 120>; 1682 wakeup-parent = <&pdc>; 1683 1684 dp_hot_plug_det: dp-hot-plug-det-state { 1685 pins = "gpio117"; 1686 function = "dp_hot"; 1687 }; 1688 1689 qspi_clk: qspi-clk-state { 1690 pins = "gpio63"; 1691 function = "qspi_clk"; 1692 }; 1693 1694 qspi_cs0: qspi-cs0-state { 1695 pins = "gpio68"; 1696 function = "qspi_cs"; 1697 }; 1698 1699 qspi_cs1: qspi-cs1-state { 1700 pins = "gpio72"; 1701 function = "qspi_cs"; 1702 }; 1703 1704 qspi_data0: qspi-data0-state { 1705 pins = "gpio64"; 1706 function = "qspi_data"; 1707 }; 1708 1709 qspi_data1: qspi-data1-state { 1710 pins = "gpio65"; 1711 function = "qspi_data"; 1712 }; 1713 1714 qspi_data23: qspi-data23-state { 1715 pins = "gpio66", "gpio67"; 1716 function = "qspi_data"; 1717 }; 1718 1719 qup_i2c0_default: qup-i2c0-default-state { 1720 pins = "gpio34", "gpio35"; 1721 function = "qup00"; 1722 }; 1723 1724 qup_i2c1_default: qup-i2c1-default-state { 1725 pins = "gpio0", "gpio1"; 1726 function = "qup01"; 1727 }; 1728 1729 qup_i2c2_default: qup-i2c2-default-state { 1730 pins = "gpio15", "gpio16"; 1731 function = "qup02_i2c"; 1732 }; 1733 1734 qup_i2c3_default: qup-i2c3-default-state { 1735 pins = "gpio38", "gpio39"; 1736 function = "qup03"; 1737 }; 1738 1739 qup_i2c4_default: qup-i2c4-default-state { 1740 pins = "gpio115", "gpio116"; 1741 function = "qup04_i2c"; 1742 }; 1743 1744 qup_i2c5_default: qup-i2c5-default-state { 1745 pins = "gpio25", "gpio26"; 1746 function = "qup05"; 1747 }; 1748 1749 qup_i2c6_default: qup-i2c6-default-state { 1750 pins = "gpio59", "gpio60"; 1751 function = "qup10"; 1752 }; 1753 1754 qup_i2c7_default: qup-i2c7-default-state { 1755 pins = "gpio6", "gpio7"; 1756 function = "qup11_i2c"; 1757 }; 1758 1759 qup_i2c8_default: qup-i2c8-default-state { 1760 pins = "gpio42", "gpio43"; 1761 function = "qup12"; 1762 }; 1763 1764 qup_i2c9_default: qup-i2c9-default-state { 1765 pins = "gpio46", "gpio47"; 1766 function = "qup13_i2c"; 1767 }; 1768 1769 qup_i2c10_default: qup-i2c10-default-state { 1770 pins = "gpio86", "gpio87"; 1771 function = "qup14"; 1772 }; 1773 1774 qup_i2c11_default: qup-i2c11-default-state { 1775 pins = "gpio53", "gpio54"; 1776 function = "qup15"; 1777 }; 1778 1779 qup_spi0_spi: qup-spi0-spi-state { 1780 pins = "gpio34", "gpio35", "gpio36"; 1781 function = "qup00"; 1782 }; 1783 1784 qup_spi0_cs: qup-spi0-cs-state { 1785 pins = "gpio37"; 1786 function = "qup00"; 1787 }; 1788 1789 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 1790 pins = "gpio37"; 1791 function = "gpio"; 1792 }; 1793 1794 qup_spi1_spi: qup-spi1-spi-state { 1795 pins = "gpio0", "gpio1", "gpio2"; 1796 function = "qup01"; 1797 }; 1798 1799 qup_spi1_cs: qup-spi1-cs-state { 1800 pins = "gpio3"; 1801 function = "qup01"; 1802 }; 1803 1804 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 1805 pins = "gpio3"; 1806 function = "gpio"; 1807 }; 1808 1809 qup_spi3_spi: qup-spi3-spi-state { 1810 pins = "gpio38", "gpio39", "gpio40"; 1811 function = "qup03"; 1812 }; 1813 1814 qup_spi3_cs: qup-spi3-cs-state { 1815 pins = "gpio41"; 1816 function = "qup03"; 1817 }; 1818 1819 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 1820 pins = "gpio41"; 1821 function = "gpio"; 1822 }; 1823 1824 qup_spi5_spi: qup-spi5-spi-state { 1825 pins = "gpio25", "gpio26", "gpio27"; 1826 function = "qup05"; 1827 }; 1828 1829 qup_spi5_cs: qup-spi5-cs-state { 1830 pins = "gpio28"; 1831 function = "qup05"; 1832 }; 1833 1834 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 1835 pins = "gpio28"; 1836 function = "gpio"; 1837 }; 1838 1839 qup_spi6_spi: qup-spi6-spi-state { 1840 pins = "gpio59", "gpio60", "gpio61"; 1841 function = "qup10"; 1842 }; 1843 1844 qup_spi6_cs: qup-spi6-cs-state { 1845 pins = "gpio62"; 1846 function = "qup10"; 1847 }; 1848 1849 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1850 pins = "gpio62"; 1851 function = "gpio"; 1852 }; 1853 1854 qup_spi8_spi: qup-spi8-spi-state { 1855 pins = "gpio42", "gpio43", "gpio44"; 1856 function = "qup12"; 1857 }; 1858 1859 qup_spi8_cs: qup-spi8-cs-state { 1860 pins = "gpio45"; 1861 function = "qup12"; 1862 }; 1863 1864 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 1865 pins = "gpio45"; 1866 function = "gpio"; 1867 }; 1868 1869 qup_spi10_spi: qup-spi10-spi-state { 1870 pins = "gpio86", "gpio87", "gpio88"; 1871 function = "qup14"; 1872 }; 1873 1874 qup_spi10_cs: qup-spi10-cs-state { 1875 pins = "gpio89"; 1876 function = "qup14"; 1877 }; 1878 1879 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 1880 pins = "gpio89"; 1881 function = "gpio"; 1882 }; 1883 1884 qup_spi11_spi: qup-spi11-spi-state { 1885 pins = "gpio53", "gpio54", "gpio55"; 1886 function = "qup15"; 1887 }; 1888 1889 qup_spi11_cs: qup-spi11-cs-state { 1890 pins = "gpio56"; 1891 function = "qup15"; 1892 }; 1893 1894 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 1895 pins = "gpio56"; 1896 function = "gpio"; 1897 }; 1898 1899 qup_uart0_default: qup-uart0-default-state { 1900 qup_uart0_cts: cts-pins { 1901 pins = "gpio34"; 1902 function = "qup00"; 1903 }; 1904 1905 qup_uart0_rts: rts-pins { 1906 pins = "gpio35"; 1907 function = "qup00"; 1908 }; 1909 1910 qup_uart0_tx: tx-pins { 1911 pins = "gpio36"; 1912 function = "qup00"; 1913 }; 1914 1915 qup_uart0_rx: rx-pins { 1916 pins = "gpio37"; 1917 function = "qup00"; 1918 }; 1919 }; 1920 1921 qup_uart1_default: qup-uart1-default-state { 1922 qup_uart1_cts: cts-pins { 1923 pins = "gpio0"; 1924 function = "qup01"; 1925 }; 1926 1927 qup_uart1_rts: rts-pins { 1928 pins = "gpio1"; 1929 function = "qup01"; 1930 }; 1931 1932 qup_uart1_tx: tx-pins { 1933 pins = "gpio2"; 1934 function = "qup01"; 1935 }; 1936 1937 qup_uart1_rx: rx-pins { 1938 pins = "gpio3"; 1939 function = "qup01"; 1940 }; 1941 }; 1942 1943 qup_uart2_default: qup-uart2-default-state { 1944 qup_uart2_tx: tx-pins { 1945 pins = "gpio15"; 1946 function = "qup02_uart"; 1947 }; 1948 1949 qup_uart2_rx: rx-pins { 1950 pins = "gpio16"; 1951 function = "qup02_uart"; 1952 }; 1953 }; 1954 1955 qup_uart3_default: qup-uart3-default-state { 1956 qup_uart3_cts: cts-pins { 1957 pins = "gpio38"; 1958 function = "qup03"; 1959 }; 1960 1961 qup_uart3_rts: rts-pins { 1962 pins = "gpio39"; 1963 function = "qup03"; 1964 }; 1965 1966 qup_uart3_tx: tx-pins { 1967 pins = "gpio40"; 1968 function = "qup03"; 1969 }; 1970 1971 qup_uart3_rx: rx-pins { 1972 pins = "gpio41"; 1973 function = "qup03"; 1974 }; 1975 }; 1976 1977 qup_uart4_default: qup-uart4-default-state { 1978 qup_uart4_tx: tx-pins { 1979 pins = "gpio115"; 1980 function = "qup04_uart"; 1981 }; 1982 1983 qup_uart4_rx: rx-pins { 1984 pins = "gpio116"; 1985 function = "qup04_uart"; 1986 }; 1987 }; 1988 1989 qup_uart5_default: qup-uart5-default-state { 1990 qup_uart5_cts: cts-pins { 1991 pins = "gpio25"; 1992 function = "qup05"; 1993 }; 1994 1995 qup_uart5_rts: rts-pins { 1996 pins = "gpio26"; 1997 function = "qup05"; 1998 }; 1999 2000 qup_uart5_tx: tx-pins { 2001 pins = "gpio27"; 2002 function = "qup05"; 2003 }; 2004 2005 qup_uart5_rx: rx-pins { 2006 pins = "gpio28"; 2007 function = "qup05"; 2008 }; 2009 }; 2010 2011 qup_uart6_default: qup-uart6-default-state { 2012 qup_uart6_cts: cts-pins { 2013 pins = "gpio59"; 2014 function = "qup10"; 2015 }; 2016 2017 qup_uart6_rts: rts-pins { 2018 pins = "gpio60"; 2019 function = "qup10"; 2020 }; 2021 2022 qup_uart6_tx: tx-pins { 2023 pins = "gpio61"; 2024 function = "qup10"; 2025 }; 2026 2027 qup_uart6_rx: rx-pins { 2028 pins = "gpio62"; 2029 function = "qup10"; 2030 }; 2031 }; 2032 2033 qup_uart7_default: qup-uart7-default-state { 2034 qup_uart7_tx: tx-pins { 2035 pins = "gpio6"; 2036 function = "qup11_uart"; 2037 }; 2038 2039 qup_uart7_rx: rx-pins { 2040 pins = "gpio7"; 2041 function = "qup11_uart"; 2042 }; 2043 }; 2044 2045 qup_uart8_default: qup-uart8-default-state { 2046 qup_uart8_tx: tx-pins { 2047 pins = "gpio44"; 2048 function = "qup12"; 2049 }; 2050 2051 qup_uart8_rx: rx-pins { 2052 pins = "gpio45"; 2053 function = "qup12"; 2054 }; 2055 }; 2056 2057 qup_uart9_default: qup-uart9-default-state { 2058 qup_uart9_tx: tx-pins { 2059 pins = "gpio46"; 2060 function = "qup13_uart"; 2061 }; 2062 2063 qup_uart9_rx: rx-pins { 2064 pins = "gpio47"; 2065 function = "qup13_uart"; 2066 }; 2067 }; 2068 2069 qup_uart10_default: qup-uart10-default-state { 2070 qup_uart10_cts: cts-pins { 2071 pins = "gpio86"; 2072 function = "qup14"; 2073 }; 2074 2075 qup_uart10_rts: rts-pins { 2076 pins = "gpio87"; 2077 function = "qup14"; 2078 }; 2079 2080 qup_uart10_tx: tx-pins { 2081 pins = "gpio88"; 2082 function = "qup14"; 2083 }; 2084 2085 qup_uart10_rx: rx-pins { 2086 pins = "gpio89"; 2087 function = "qup14"; 2088 }; 2089 }; 2090 2091 qup_uart11_default: qup-uart11-default-state { 2092 qup_uart11_cts: cts-pins { 2093 pins = "gpio53"; 2094 function = "qup15"; 2095 }; 2096 2097 qup_uart11_rts: rts-pins { 2098 pins = "gpio54"; 2099 function = "qup15"; 2100 }; 2101 2102 qup_uart11_tx: tx-pins { 2103 pins = "gpio55"; 2104 function = "qup15"; 2105 }; 2106 2107 qup_uart11_rx: rx-pins { 2108 pins = "gpio56"; 2109 function = "qup15"; 2110 }; 2111 }; 2112 2113 sec_mi2s_active: sec-mi2s-active-state { 2114 pins = "gpio49", "gpio50", "gpio51"; 2115 function = "mi2s_1"; 2116 }; 2117 2118 pri_mi2s_active: pri-mi2s-active-state { 2119 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 2120 function = "mi2s_0"; 2121 }; 2122 2123 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state { 2124 pins = "gpio57"; 2125 function = "lpass_ext"; 2126 }; 2127 2128 ter_mi2s_active: ter-mi2s-active-state { 2129 pins = "gpio63", "gpio64", "gpio65", "gpio66"; 2130 function = "mi2s_2"; 2131 }; 2132 }; 2133 2134 remoteproc_mpss: remoteproc@4080000 { 2135 compatible = "qcom,sc7180-mpss-pas"; 2136 reg = <0 0x04080000 0 0x4040>; 2137 2138 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2139 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2140 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2141 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2142 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2143 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2144 interrupt-names = "wdog", "fatal", "ready", "handover", 2145 "stop-ack", "shutdown-ack"; 2146 2147 clocks = <&rpmhcc RPMH_CXO_CLK>; 2148 clock-names = "xo"; 2149 2150 power-domains = <&rpmhpd SC7180_CX>, 2151 <&rpmhpd SC7180_MX>, 2152 <&rpmhpd SC7180_MSS>; 2153 power-domain-names = "cx", "mx", "mss"; 2154 2155 memory-region = <&mpss_mem>; 2156 2157 qcom,qmp = <&aoss_qmp>; 2158 2159 qcom,smem-states = <&modem_smp2p_out 0>; 2160 qcom,smem-state-names = "stop"; 2161 2162 status = "disabled"; 2163 2164 glink-edge { 2165 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2166 label = "modem"; 2167 qcom,remote-pid = <1>; 2168 mboxes = <&apss_shared 12>; 2169 }; 2170 }; 2171 2172 gpu: gpu@5000000 { 2173 compatible = "qcom,adreno-618.0", "qcom,adreno"; 2174 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 2175 <0 0x05061000 0 0x800>; 2176 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 2177 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2178 iommus = <&adreno_smmu 0>; 2179 operating-points-v2 = <&gpu_opp_table>; 2180 qcom,gmu = <&gmu>; 2181 2182 #cooling-cells = <2>; 2183 2184 nvmem-cells = <&gpu_speed_bin>; 2185 nvmem-cell-names = "speed_bin"; 2186 2187 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2188 interconnect-names = "gfx-mem"; 2189 2190 gpu_zap_shader: zap-shader { 2191 memory-region = <&gpu_mem>; 2192 }; 2193 2194 gpu_opp_table: opp-table { 2195 compatible = "operating-points-v2"; 2196 2197 opp-825000000 { 2198 opp-hz = /bits/ 64 <825000000>; 2199 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2200 opp-peak-kBps = <8532000>; 2201 opp-supported-hw = <0x04>; 2202 }; 2203 2204 opp-800000000 { 2205 opp-hz = /bits/ 64 <800000000>; 2206 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2207 opp-peak-kBps = <8532000>; 2208 opp-supported-hw = <0x07>; 2209 }; 2210 2211 opp-650000000 { 2212 opp-hz = /bits/ 64 <650000000>; 2213 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2214 opp-peak-kBps = <7216000>; 2215 opp-supported-hw = <0x07>; 2216 }; 2217 2218 opp-565000000 { 2219 opp-hz = /bits/ 64 <565000000>; 2220 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2221 opp-peak-kBps = <5412000>; 2222 opp-supported-hw = <0x07>; 2223 }; 2224 2225 opp-430000000 { 2226 opp-hz = /bits/ 64 <430000000>; 2227 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2228 opp-peak-kBps = <5412000>; 2229 opp-supported-hw = <0x07>; 2230 }; 2231 2232 opp-355000000 { 2233 opp-hz = /bits/ 64 <355000000>; 2234 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2235 opp-peak-kBps = <3072000>; 2236 opp-supported-hw = <0x07>; 2237 }; 2238 2239 opp-267000000 { 2240 opp-hz = /bits/ 64 <267000000>; 2241 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2242 opp-peak-kBps = <3072000>; 2243 opp-supported-hw = <0x07>; 2244 }; 2245 2246 opp-180000000 { 2247 opp-hz = /bits/ 64 <180000000>; 2248 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2249 opp-peak-kBps = <1804000>; 2250 opp-supported-hw = <0x07>; 2251 }; 2252 }; 2253 }; 2254 2255 adreno_smmu: iommu@5040000 { 2256 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2257 reg = <0 0x05040000 0 0x10000>; 2258 #iommu-cells = <1>; 2259 #global-interrupts = <2>; 2260 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2261 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2262 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2263 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2264 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2265 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2266 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2267 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2268 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2269 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2270 2271 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2272 <&gcc GCC_GPU_CFG_AHB_CLK>; 2273 clock-names = "bus", "iface"; 2274 2275 power-domains = <&gpucc CX_GDSC>; 2276 }; 2277 2278 gmu: gmu@506a000 { 2279 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2280 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2281 <0 0x0b490000 0 0x10000>; 2282 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2283 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2284 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2285 interrupt-names = "hfi", "gmu"; 2286 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2287 <&gpucc GPU_CC_CXO_CLK>, 2288 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2289 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2290 clock-names = "gmu", "cxo", "axi", "memnoc"; 2291 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2292 power-domain-names = "cx", "gx"; 2293 iommus = <&adreno_smmu 5>; 2294 operating-points-v2 = <&gmu_opp_table>; 2295 2296 gmu_opp_table: opp-table { 2297 compatible = "operating-points-v2"; 2298 2299 opp-200000000 { 2300 opp-hz = /bits/ 64 <200000000>; 2301 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2302 }; 2303 }; 2304 }; 2305 2306 gpucc: clock-controller@5090000 { 2307 compatible = "qcom,sc7180-gpucc"; 2308 reg = <0 0x05090000 0 0x9000>; 2309 clocks = <&rpmhcc RPMH_CXO_CLK>, 2310 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2311 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2312 clock-names = "bi_tcxo", 2313 "gcc_gpu_gpll0_clk_src", 2314 "gcc_gpu_gpll0_div_clk_src"; 2315 #clock-cells = <1>; 2316 #reset-cells = <1>; 2317 #power-domain-cells = <1>; 2318 }; 2319 2320 dma@10a2000 { 2321 compatible = "qcom,sc7180-dcc", "qcom,dcc"; 2322 reg = <0x0 0x010a2000 0x0 0x1000>, 2323 <0x0 0x010ae000 0x0 0x2000>; 2324 status = "disabled"; 2325 }; 2326 2327 stm@6002000 { 2328 compatible = "arm,coresight-stm", "arm,primecell"; 2329 reg = <0 0x06002000 0 0x1000>, 2330 <0 0x16280000 0 0x180000>; 2331 reg-names = "stm-base", "stm-stimulus-base"; 2332 2333 clocks = <&aoss_qmp>; 2334 clock-names = "apb_pclk"; 2335 2336 out-ports { 2337 port { 2338 stm_out: endpoint { 2339 remote-endpoint = <&funnel0_in7>; 2340 }; 2341 }; 2342 }; 2343 }; 2344 2345 funnel@6041000 { 2346 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2347 reg = <0 0x06041000 0 0x1000>; 2348 2349 clocks = <&aoss_qmp>; 2350 clock-names = "apb_pclk"; 2351 2352 out-ports { 2353 port { 2354 funnel0_out: endpoint { 2355 remote-endpoint = <&merge_funnel_in0>; 2356 }; 2357 }; 2358 }; 2359 2360 in-ports { 2361 #address-cells = <1>; 2362 #size-cells = <0>; 2363 2364 port@7 { 2365 reg = <7>; 2366 funnel0_in7: endpoint { 2367 remote-endpoint = <&stm_out>; 2368 }; 2369 }; 2370 }; 2371 }; 2372 2373 funnel@6042000 { 2374 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2375 reg = <0 0x06042000 0 0x1000>; 2376 2377 clocks = <&aoss_qmp>; 2378 clock-names = "apb_pclk"; 2379 2380 out-ports { 2381 port { 2382 funnel1_out: endpoint { 2383 remote-endpoint = <&merge_funnel_in1>; 2384 }; 2385 }; 2386 }; 2387 2388 in-ports { 2389 #address-cells = <1>; 2390 #size-cells = <0>; 2391 2392 port@4 { 2393 reg = <4>; 2394 funnel1_in4: endpoint { 2395 remote-endpoint = <&apss_merge_funnel_out>; 2396 }; 2397 }; 2398 }; 2399 }; 2400 2401 funnel@6045000 { 2402 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2403 reg = <0 0x06045000 0 0x1000>; 2404 2405 clocks = <&aoss_qmp>; 2406 clock-names = "apb_pclk"; 2407 2408 out-ports { 2409 port { 2410 merge_funnel_out: endpoint { 2411 remote-endpoint = <&swao_funnel_in>; 2412 }; 2413 }; 2414 }; 2415 2416 in-ports { 2417 #address-cells = <1>; 2418 #size-cells = <0>; 2419 2420 port@0 { 2421 reg = <0>; 2422 merge_funnel_in0: endpoint { 2423 remote-endpoint = <&funnel0_out>; 2424 }; 2425 }; 2426 2427 port@1 { 2428 reg = <1>; 2429 merge_funnel_in1: endpoint { 2430 remote-endpoint = <&funnel1_out>; 2431 }; 2432 }; 2433 }; 2434 }; 2435 2436 replicator@6046000 { 2437 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2438 reg = <0 0x06046000 0 0x1000>; 2439 2440 clocks = <&aoss_qmp>; 2441 clock-names = "apb_pclk"; 2442 2443 out-ports { 2444 port { 2445 replicator_out: endpoint { 2446 remote-endpoint = <&etr_in>; 2447 }; 2448 }; 2449 }; 2450 2451 in-ports { 2452 port { 2453 replicator_in: endpoint { 2454 remote-endpoint = <&swao_replicator_out>; 2455 }; 2456 }; 2457 }; 2458 }; 2459 2460 etr@6048000 { 2461 compatible = "arm,coresight-tmc", "arm,primecell"; 2462 reg = <0 0x06048000 0 0x1000>; 2463 iommus = <&apps_smmu 0x04a0 0x20>; 2464 2465 clocks = <&aoss_qmp>; 2466 clock-names = "apb_pclk"; 2467 arm,scatter-gather; 2468 2469 in-ports { 2470 port { 2471 etr_in: endpoint { 2472 remote-endpoint = <&replicator_out>; 2473 }; 2474 }; 2475 }; 2476 }; 2477 2478 funnel@6b04000 { 2479 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2480 reg = <0 0x06b04000 0 0x1000>; 2481 2482 clocks = <&aoss_qmp>; 2483 clock-names = "apb_pclk"; 2484 2485 out-ports { 2486 port { 2487 swao_funnel_out: endpoint { 2488 remote-endpoint = <&etf_in>; 2489 }; 2490 }; 2491 }; 2492 2493 in-ports { 2494 #address-cells = <1>; 2495 #size-cells = <0>; 2496 2497 port@7 { 2498 reg = <7>; 2499 swao_funnel_in: endpoint { 2500 remote-endpoint = <&merge_funnel_out>; 2501 }; 2502 }; 2503 }; 2504 }; 2505 2506 etf@6b05000 { 2507 compatible = "arm,coresight-tmc", "arm,primecell"; 2508 reg = <0 0x06b05000 0 0x1000>; 2509 2510 clocks = <&aoss_qmp>; 2511 clock-names = "apb_pclk"; 2512 2513 out-ports { 2514 port { 2515 etf_out: endpoint { 2516 remote-endpoint = <&swao_replicator_in>; 2517 }; 2518 }; 2519 }; 2520 2521 in-ports { 2522 port { 2523 etf_in: endpoint { 2524 remote-endpoint = <&swao_funnel_out>; 2525 }; 2526 }; 2527 }; 2528 }; 2529 2530 replicator@6b06000 { 2531 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2532 reg = <0 0x06b06000 0 0x1000>; 2533 2534 clocks = <&aoss_qmp>; 2535 clock-names = "apb_pclk"; 2536 qcom,replicator-loses-context; 2537 2538 out-ports { 2539 port { 2540 swao_replicator_out: endpoint { 2541 remote-endpoint = <&replicator_in>; 2542 }; 2543 }; 2544 }; 2545 2546 in-ports { 2547 port { 2548 swao_replicator_in: endpoint { 2549 remote-endpoint = <&etf_out>; 2550 }; 2551 }; 2552 }; 2553 }; 2554 2555 etm@7040000 { 2556 compatible = "arm,coresight-etm4x", "arm,primecell"; 2557 reg = <0 0x07040000 0 0x1000>; 2558 2559 cpu = <&cpu0>; 2560 2561 clocks = <&aoss_qmp>; 2562 clock-names = "apb_pclk"; 2563 arm,coresight-loses-context-with-cpu; 2564 qcom,skip-power-up; 2565 2566 out-ports { 2567 port { 2568 etm0_out: endpoint { 2569 remote-endpoint = <&apss_funnel_in0>; 2570 }; 2571 }; 2572 }; 2573 }; 2574 2575 etm@7140000 { 2576 compatible = "arm,coresight-etm4x", "arm,primecell"; 2577 reg = <0 0x07140000 0 0x1000>; 2578 2579 cpu = <&cpu1>; 2580 2581 clocks = <&aoss_qmp>; 2582 clock-names = "apb_pclk"; 2583 arm,coresight-loses-context-with-cpu; 2584 qcom,skip-power-up; 2585 2586 out-ports { 2587 port { 2588 etm1_out: endpoint { 2589 remote-endpoint = <&apss_funnel_in1>; 2590 }; 2591 }; 2592 }; 2593 }; 2594 2595 etm@7240000 { 2596 compatible = "arm,coresight-etm4x", "arm,primecell"; 2597 reg = <0 0x07240000 0 0x1000>; 2598 2599 cpu = <&cpu2>; 2600 2601 clocks = <&aoss_qmp>; 2602 clock-names = "apb_pclk"; 2603 arm,coresight-loses-context-with-cpu; 2604 qcom,skip-power-up; 2605 2606 out-ports { 2607 port { 2608 etm2_out: endpoint { 2609 remote-endpoint = <&apss_funnel_in2>; 2610 }; 2611 }; 2612 }; 2613 }; 2614 2615 etm@7340000 { 2616 compatible = "arm,coresight-etm4x", "arm,primecell"; 2617 reg = <0 0x07340000 0 0x1000>; 2618 2619 cpu = <&cpu3>; 2620 2621 clocks = <&aoss_qmp>; 2622 clock-names = "apb_pclk"; 2623 arm,coresight-loses-context-with-cpu; 2624 qcom,skip-power-up; 2625 2626 out-ports { 2627 port { 2628 etm3_out: endpoint { 2629 remote-endpoint = <&apss_funnel_in3>; 2630 }; 2631 }; 2632 }; 2633 }; 2634 2635 etm@7440000 { 2636 compatible = "arm,coresight-etm4x", "arm,primecell"; 2637 reg = <0 0x07440000 0 0x1000>; 2638 2639 cpu = <&cpu4>; 2640 2641 clocks = <&aoss_qmp>; 2642 clock-names = "apb_pclk"; 2643 arm,coresight-loses-context-with-cpu; 2644 qcom,skip-power-up; 2645 2646 out-ports { 2647 port { 2648 etm4_out: endpoint { 2649 remote-endpoint = <&apss_funnel_in4>; 2650 }; 2651 }; 2652 }; 2653 }; 2654 2655 etm@7540000 { 2656 compatible = "arm,coresight-etm4x", "arm,primecell"; 2657 reg = <0 0x07540000 0 0x1000>; 2658 2659 cpu = <&cpu5>; 2660 2661 clocks = <&aoss_qmp>; 2662 clock-names = "apb_pclk"; 2663 arm,coresight-loses-context-with-cpu; 2664 qcom,skip-power-up; 2665 2666 out-ports { 2667 port { 2668 etm5_out: endpoint { 2669 remote-endpoint = <&apss_funnel_in5>; 2670 }; 2671 }; 2672 }; 2673 }; 2674 2675 etm@7640000 { 2676 compatible = "arm,coresight-etm4x", "arm,primecell"; 2677 reg = <0 0x07640000 0 0x1000>; 2678 2679 cpu = <&cpu6>; 2680 2681 clocks = <&aoss_qmp>; 2682 clock-names = "apb_pclk"; 2683 arm,coresight-loses-context-with-cpu; 2684 qcom,skip-power-up; 2685 2686 out-ports { 2687 port { 2688 etm6_out: endpoint { 2689 remote-endpoint = <&apss_funnel_in6>; 2690 }; 2691 }; 2692 }; 2693 }; 2694 2695 etm@7740000 { 2696 compatible = "arm,coresight-etm4x", "arm,primecell"; 2697 reg = <0 0x07740000 0 0x1000>; 2698 2699 cpu = <&cpu7>; 2700 2701 clocks = <&aoss_qmp>; 2702 clock-names = "apb_pclk"; 2703 arm,coresight-loses-context-with-cpu; 2704 qcom,skip-power-up; 2705 2706 out-ports { 2707 port { 2708 etm7_out: endpoint { 2709 remote-endpoint = <&apss_funnel_in7>; 2710 }; 2711 }; 2712 }; 2713 }; 2714 2715 funnel@7800000 { /* APSS Funnel */ 2716 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2717 reg = <0 0x07800000 0 0x1000>; 2718 2719 clocks = <&aoss_qmp>; 2720 clock-names = "apb_pclk"; 2721 2722 out-ports { 2723 port { 2724 apss_funnel_out: endpoint { 2725 remote-endpoint = <&apss_merge_funnel_in>; 2726 }; 2727 }; 2728 }; 2729 2730 in-ports { 2731 #address-cells = <1>; 2732 #size-cells = <0>; 2733 2734 port@0 { 2735 reg = <0>; 2736 apss_funnel_in0: endpoint { 2737 remote-endpoint = <&etm0_out>; 2738 }; 2739 }; 2740 2741 port@1 { 2742 reg = <1>; 2743 apss_funnel_in1: endpoint { 2744 remote-endpoint = <&etm1_out>; 2745 }; 2746 }; 2747 2748 port@2 { 2749 reg = <2>; 2750 apss_funnel_in2: endpoint { 2751 remote-endpoint = <&etm2_out>; 2752 }; 2753 }; 2754 2755 port@3 { 2756 reg = <3>; 2757 apss_funnel_in3: endpoint { 2758 remote-endpoint = <&etm3_out>; 2759 }; 2760 }; 2761 2762 port@4 { 2763 reg = <4>; 2764 apss_funnel_in4: endpoint { 2765 remote-endpoint = <&etm4_out>; 2766 }; 2767 }; 2768 2769 port@5 { 2770 reg = <5>; 2771 apss_funnel_in5: endpoint { 2772 remote-endpoint = <&etm5_out>; 2773 }; 2774 }; 2775 2776 port@6 { 2777 reg = <6>; 2778 apss_funnel_in6: endpoint { 2779 remote-endpoint = <&etm6_out>; 2780 }; 2781 }; 2782 2783 port@7 { 2784 reg = <7>; 2785 apss_funnel_in7: endpoint { 2786 remote-endpoint = <&etm7_out>; 2787 }; 2788 }; 2789 }; 2790 }; 2791 2792 funnel@7810000 { 2793 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2794 reg = <0 0x07810000 0 0x1000>; 2795 2796 clocks = <&aoss_qmp>; 2797 clock-names = "apb_pclk"; 2798 2799 out-ports { 2800 port { 2801 apss_merge_funnel_out: endpoint { 2802 remote-endpoint = <&funnel1_in4>; 2803 }; 2804 }; 2805 }; 2806 2807 in-ports { 2808 port { 2809 apss_merge_funnel_in: endpoint { 2810 remote-endpoint = <&apss_funnel_out>; 2811 }; 2812 }; 2813 }; 2814 }; 2815 2816 sdhc_2: mmc@8804000 { 2817 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2818 reg = <0 0x08804000 0 0x1000>; 2819 2820 iommus = <&apps_smmu 0x80 0>; 2821 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2822 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2823 interrupt-names = "hc_irq", "pwr_irq"; 2824 2825 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2826 <&gcc GCC_SDCC2_APPS_CLK>, 2827 <&rpmhcc RPMH_CXO_CLK>; 2828 clock-names = "iface", "core", "xo"; 2829 2830 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2831 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2832 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2833 power-domains = <&rpmhpd SC7180_CX>; 2834 operating-points-v2 = <&sdhc2_opp_table>; 2835 2836 bus-width = <4>; 2837 2838 status = "disabled"; 2839 2840 sdhc2_opp_table: opp-table { 2841 compatible = "operating-points-v2"; 2842 2843 opp-100000000 { 2844 opp-hz = /bits/ 64 <100000000>; 2845 required-opps = <&rpmhpd_opp_low_svs>; 2846 opp-peak-kBps = <1800000 600000>; 2847 opp-avg-kBps = <100000 0>; 2848 }; 2849 2850 opp-202000000 { 2851 opp-hz = /bits/ 64 <202000000>; 2852 required-opps = <&rpmhpd_opp_nom>; 2853 opp-peak-kBps = <5400000 1600000>; 2854 opp-avg-kBps = <200000 0>; 2855 }; 2856 }; 2857 }; 2858 2859 qspi: spi@88dc000 { 2860 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; 2861 reg = <0 0x088dc000 0 0x600>; 2862 iommus = <&apps_smmu 0x20 0x0>; 2863 #address-cells = <1>; 2864 #size-cells = <0>; 2865 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2866 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2867 <&gcc GCC_QSPI_CORE_CLK>; 2868 clock-names = "iface", "core"; 2869 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2870 &config_noc SLAVE_QSPI_0 0>; 2871 interconnect-names = "qspi-config"; 2872 power-domains = <&rpmhpd SC7180_CX>; 2873 operating-points-v2 = <&qspi_opp_table>; 2874 status = "disabled"; 2875 }; 2876 2877 usb_1_hsphy: phy@88e3000 { 2878 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2879 reg = <0 0x088e3000 0 0x400>; 2880 status = "disabled"; 2881 #phy-cells = <0>; 2882 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2883 <&rpmhcc RPMH_CXO_CLK>; 2884 clock-names = "cfg_ahb", "ref"; 2885 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2886 2887 nvmem-cells = <&qusb2p_hstx_trim>; 2888 }; 2889 2890 usb_1_qmpphy: phy@88e8000 { 2891 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2892 reg = <0 0x088e8000 0 0x3000>; 2893 status = "disabled"; 2894 2895 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2896 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2897 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2898 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, 2899 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 2900 clock-names = "aux", 2901 "ref", 2902 "com_aux", 2903 "usb3_pipe", 2904 "cfg_ahb"; 2905 2906 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2907 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2908 reset-names = "phy", "common"; 2909 2910 #clock-cells = <1>; 2911 #phy-cells = <1>; 2912 2913 ports { 2914 #address-cells = <1>; 2915 #size-cells = <0>; 2916 2917 port@0 { 2918 reg = <0>; 2919 2920 usb_1_qmpphy_out: endpoint { }; 2921 }; 2922 2923 port@1 { 2924 reg = <1>; 2925 2926 usb_1_qmpphy_usb_ss_in: endpoint { 2927 remote-endpoint = <&usb_1_dwc3_ss>; 2928 }; 2929 }; 2930 2931 port@2 { 2932 reg = <2>; 2933 2934 usb_1_qmpphy_dp_in: endpoint { }; 2935 }; 2936 }; 2937 }; 2938 2939 pmu@90b6300 { 2940 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon"; 2941 reg = <0 0x090b6300 0 0x600>; 2942 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2943 2944 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2945 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 2946 operating-points-v2 = <&cpu_bwmon_opp_table>; 2947 2948 cpu_bwmon_opp_table: opp-table { 2949 compatible = "operating-points-v2"; 2950 2951 opp-0 { 2952 opp-peak-kBps = <2288000>; 2953 }; 2954 2955 opp-1 { 2956 opp-peak-kBps = <4577000>; 2957 }; 2958 2959 opp-2 { 2960 opp-peak-kBps = <7110000>; 2961 }; 2962 2963 opp-3 { 2964 opp-peak-kBps = <9155000>; 2965 }; 2966 2967 opp-4 { 2968 opp-peak-kBps = <12298000>; 2969 }; 2970 2971 opp-5 { 2972 opp-peak-kBps = <14236000>; 2973 }; 2974 }; 2975 }; 2976 2977 pmu@90cd000 { 2978 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 2979 reg = <0 0x090cd000 0 0x1000>; 2980 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 2981 2982 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 2983 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2984 operating-points-v2 = <&llcc_bwmon_opp_table>; 2985 2986 llcc_bwmon_opp_table: opp-table { 2987 compatible = "operating-points-v2"; 2988 2989 opp-0 { 2990 opp-peak-kBps = <1144000>; 2991 }; 2992 2993 opp-1 { 2994 opp-peak-kBps = <1720000>; 2995 }; 2996 2997 opp-2 { 2998 opp-peak-kBps = <2086000>; 2999 }; 3000 3001 opp-3 { 3002 opp-peak-kBps = <2929000>; 3003 }; 3004 3005 opp-4 { 3006 opp-peak-kBps = <3879000>; 3007 }; 3008 3009 opp-5 { 3010 opp-peak-kBps = <5931000>; 3011 }; 3012 3013 opp-6 { 3014 opp-peak-kBps = <6881000>; 3015 }; 3016 3017 opp-7 { 3018 opp-peak-kBps = <8137000>; 3019 }; 3020 }; 3021 }; 3022 3023 dc_noc: interconnect@9160000 { 3024 compatible = "qcom,sc7180-dc-noc"; 3025 reg = <0 0x09160000 0 0x03200>; 3026 #interconnect-cells = <2>; 3027 qcom,bcm-voters = <&apps_bcm_voter>; 3028 }; 3029 3030 system-cache-controller@9200000 { 3031 compatible = "qcom,sc7180-llcc"; 3032 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 3033 reg-names = "llcc0_base", "llcc_broadcast_base"; 3034 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3035 }; 3036 3037 gem_noc: interconnect@9680000 { 3038 compatible = "qcom,sc7180-gem-noc"; 3039 reg = <0 0x09680000 0 0x3e200>; 3040 #interconnect-cells = <2>; 3041 qcom,bcm-voters = <&apps_bcm_voter>; 3042 }; 3043 3044 npu_noc: interconnect@9990000 { 3045 compatible = "qcom,sc7180-npu-noc"; 3046 reg = <0 0x09990000 0 0x1600>; 3047 #interconnect-cells = <2>; 3048 qcom,bcm-voters = <&apps_bcm_voter>; 3049 }; 3050 3051 usb_1: usb@a6f8800 { 3052 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 3053 reg = <0 0x0a6f8800 0 0x400>; 3054 status = "disabled"; 3055 #address-cells = <2>; 3056 #size-cells = <2>; 3057 ranges; 3058 dma-ranges; 3059 3060 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3061 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3062 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3063 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3064 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3065 clock-names = "cfg_noc", 3066 "core", 3067 "iface", 3068 "sleep", 3069 "mock_utmi"; 3070 3071 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3072 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3073 assigned-clock-rates = <19200000>, <150000000>; 3074 3075 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3076 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3077 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 3078 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3079 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 3080 interrupt-names = "pwr_event", 3081 "hs_phy_irq", 3082 "dp_hs_phy_irq", 3083 "dm_hs_phy_irq", 3084 "ss_phy_irq"; 3085 3086 power-domains = <&gcc USB30_PRIM_GDSC>; 3087 required-opps = <&rpmhpd_opp_nom>; 3088 3089 resets = <&gcc GCC_USB30_PRIM_BCR>; 3090 3091 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 3092 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 3093 interconnect-names = "usb-ddr", "apps-usb"; 3094 3095 wakeup-source; 3096 3097 usb_1_dwc3: usb@a600000 { 3098 compatible = "snps,dwc3"; 3099 reg = <0 0x0a600000 0 0xe000>; 3100 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3101 iommus = <&apps_smmu 0x540 0>; 3102 snps,dis_u2_susphy_quirk; 3103 snps,dis_enblslpm_quirk; 3104 snps,parkmode-disable-ss-quirk; 3105 snps,dis-u1-entry-quirk; 3106 snps,dis-u2-entry-quirk; 3107 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3108 phy-names = "usb2-phy", "usb3-phy"; 3109 maximum-speed = "super-speed"; 3110 3111 ports { 3112 #address-cells = <1>; 3113 #size-cells = <0>; 3114 3115 port@0 { 3116 reg = <0>; 3117 3118 usb_1_dwc3_hs: endpoint { 3119 }; 3120 }; 3121 3122 port@1 { 3123 reg = <1>; 3124 3125 usb_1_dwc3_ss: endpoint { 3126 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 3127 }; 3128 }; 3129 }; 3130 }; 3131 }; 3132 3133 venus: video-codec@aa00000 { 3134 compatible = "qcom,sc7180-venus"; 3135 reg = <0 0x0aa00000 0 0xff000>; 3136 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3137 power-domains = <&videocc VENUS_GDSC>, 3138 <&videocc VCODEC0_GDSC>, 3139 <&rpmhpd SC7180_CX>; 3140 power-domain-names = "venus", "vcodec0", "cx"; 3141 operating-points-v2 = <&venus_opp_table>; 3142 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3143 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3144 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3145 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3146 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 3147 clock-names = "core", "iface", "bus", 3148 "vcodec0_core", "vcodec0_bus"; 3149 iommus = <&apps_smmu 0x0c00 0x60>; 3150 memory-region = <&venus_mem>; 3151 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 3152 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 3153 interconnect-names = "video-mem", "cpu-cfg"; 3154 3155 venus_opp_table: opp-table { 3156 compatible = "operating-points-v2"; 3157 3158 opp-150000000 { 3159 opp-hz = /bits/ 64 <150000000>; 3160 required-opps = <&rpmhpd_opp_low_svs>; 3161 }; 3162 3163 opp-270000000 { 3164 opp-hz = /bits/ 64 <270000000>; 3165 required-opps = <&rpmhpd_opp_svs>; 3166 }; 3167 3168 opp-340000000 { 3169 opp-hz = /bits/ 64 <340000000>; 3170 required-opps = <&rpmhpd_opp_svs_l1>; 3171 }; 3172 3173 opp-434000000 { 3174 opp-hz = /bits/ 64 <434000000>; 3175 required-opps = <&rpmhpd_opp_nom>; 3176 }; 3177 3178 opp-500000097 { 3179 opp-hz = /bits/ 64 <500000097>; 3180 required-opps = <&rpmhpd_opp_turbo>; 3181 }; 3182 }; 3183 }; 3184 3185 videocc: clock-controller@ab00000 { 3186 compatible = "qcom,sc7180-videocc"; 3187 reg = <0 0x0ab00000 0 0x10000>; 3188 clocks = <&rpmhcc RPMH_CXO_CLK>; 3189 clock-names = "bi_tcxo"; 3190 #clock-cells = <1>; 3191 #reset-cells = <1>; 3192 #power-domain-cells = <1>; 3193 }; 3194 3195 camnoc_virt: interconnect@ac00000 { 3196 compatible = "qcom,sc7180-camnoc-virt"; 3197 reg = <0 0x0ac00000 0 0x1000>; 3198 #interconnect-cells = <2>; 3199 qcom,bcm-voters = <&apps_bcm_voter>; 3200 }; 3201 3202 camcc: clock-controller@ad00000 { 3203 compatible = "qcom,sc7180-camcc"; 3204 reg = <0 0x0ad00000 0 0x10000>; 3205 clocks = <&rpmhcc RPMH_CXO_CLK>, 3206 <&gcc GCC_CAMERA_AHB_CLK>, 3207 <&gcc GCC_CAMERA_XO_CLK>; 3208 clock-names = "bi_tcxo", "iface", "xo"; 3209 #clock-cells = <1>; 3210 #reset-cells = <1>; 3211 #power-domain-cells = <1>; 3212 }; 3213 3214 mdss: display-subsystem@ae00000 { 3215 compatible = "qcom,sc7180-mdss"; 3216 reg = <0 0x0ae00000 0 0x1000>; 3217 reg-names = "mdss"; 3218 3219 power-domains = <&dispcc MDSS_GDSC>; 3220 3221 clocks = <&gcc GCC_DISP_AHB_CLK>, 3222 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3223 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3224 clock-names = "iface", "ahb", "core"; 3225 3226 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3227 interrupt-controller; 3228 #interrupt-cells = <1>; 3229 3230 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 3231 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3232 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3233 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 3234 interconnect-names = "mdp0-mem", 3235 "cpu-cfg"; 3236 3237 iommus = <&apps_smmu 0x800 0x2>; 3238 3239 #address-cells = <2>; 3240 #size-cells = <2>; 3241 ranges; 3242 3243 status = "disabled"; 3244 3245 mdp: display-controller@ae01000 { 3246 compatible = "qcom,sc7180-dpu"; 3247 reg = <0 0x0ae01000 0 0x8f000>, 3248 <0 0x0aeb0000 0 0x3000>; 3249 reg-names = "mdp", "vbif"; 3250 3251 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3252 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3253 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3254 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3255 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3256 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3257 clock-names = "bus", "iface", "rot", "lut", "core", 3258 "vsync"; 3259 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3260 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3261 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3262 assigned-clock-rates = <19200000>, 3263 <19200000>, 3264 <19200000>; 3265 operating-points-v2 = <&mdp_opp_table>; 3266 power-domains = <&rpmhpd SC7180_CX>; 3267 3268 interrupt-parent = <&mdss>; 3269 interrupts = <0>; 3270 3271 ports { 3272 #address-cells = <1>; 3273 #size-cells = <0>; 3274 3275 port@0 { 3276 reg = <0>; 3277 dpu_intf1_out: endpoint { 3278 remote-endpoint = <&mdss_dsi0_in>; 3279 }; 3280 }; 3281 3282 port@2 { 3283 reg = <2>; 3284 dpu_intf0_out: endpoint { 3285 remote-endpoint = <&dp_in>; 3286 }; 3287 }; 3288 }; 3289 3290 mdp_opp_table: opp-table { 3291 compatible = "operating-points-v2"; 3292 3293 opp-200000000 { 3294 opp-hz = /bits/ 64 <200000000>; 3295 required-opps = <&rpmhpd_opp_low_svs>; 3296 }; 3297 3298 opp-300000000 { 3299 opp-hz = /bits/ 64 <300000000>; 3300 required-opps = <&rpmhpd_opp_svs>; 3301 }; 3302 3303 opp-345000000 { 3304 opp-hz = /bits/ 64 <345000000>; 3305 required-opps = <&rpmhpd_opp_svs_l1>; 3306 }; 3307 3308 opp-460000000 { 3309 opp-hz = /bits/ 64 <460000000>; 3310 required-opps = <&rpmhpd_opp_nom>; 3311 }; 3312 }; 3313 }; 3314 3315 mdss_dsi0: dsi@ae94000 { 3316 compatible = "qcom,sc7180-dsi-ctrl", 3317 "qcom,mdss-dsi-ctrl"; 3318 reg = <0 0x0ae94000 0 0x400>; 3319 reg-names = "dsi_ctrl"; 3320 3321 interrupt-parent = <&mdss>; 3322 interrupts = <4>; 3323 3324 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3325 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3326 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3327 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3328 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3329 <&gcc GCC_DISP_HF_AXI_CLK>; 3330 clock-names = "byte", 3331 "byte_intf", 3332 "pixel", 3333 "core", 3334 "iface", 3335 "bus"; 3336 3337 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3338 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3339 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3340 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3341 3342 operating-points-v2 = <&dsi_opp_table>; 3343 power-domains = <&rpmhpd SC7180_CX>; 3344 3345 phys = <&mdss_dsi0_phy>; 3346 3347 refgen-supply = <&refgen>; 3348 3349 #address-cells = <1>; 3350 #size-cells = <0>; 3351 3352 status = "disabled"; 3353 3354 ports { 3355 #address-cells = <1>; 3356 #size-cells = <0>; 3357 3358 port@0 { 3359 reg = <0>; 3360 mdss_dsi0_in: endpoint { 3361 remote-endpoint = <&dpu_intf1_out>; 3362 }; 3363 }; 3364 3365 port@1 { 3366 reg = <1>; 3367 mdss_dsi0_out: endpoint { 3368 }; 3369 }; 3370 }; 3371 3372 dsi_opp_table: opp-table { 3373 compatible = "operating-points-v2"; 3374 3375 opp-187500000 { 3376 opp-hz = /bits/ 64 <187500000>; 3377 required-opps = <&rpmhpd_opp_low_svs>; 3378 }; 3379 3380 opp-300000000 { 3381 opp-hz = /bits/ 64 <300000000>; 3382 required-opps = <&rpmhpd_opp_svs>; 3383 }; 3384 3385 opp-358000000 { 3386 opp-hz = /bits/ 64 <358000000>; 3387 required-opps = <&rpmhpd_opp_svs_l1>; 3388 }; 3389 }; 3390 }; 3391 3392 mdss_dsi0_phy: phy@ae94400 { 3393 compatible = "qcom,dsi-phy-10nm"; 3394 reg = <0 0x0ae94400 0 0x200>, 3395 <0 0x0ae94600 0 0x280>, 3396 <0 0x0ae94a00 0 0x1e0>; 3397 reg-names = "dsi_phy", 3398 "dsi_phy_lane", 3399 "dsi_pll"; 3400 3401 #clock-cells = <1>; 3402 #phy-cells = <0>; 3403 3404 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3405 <&rpmhcc RPMH_CXO_CLK>; 3406 clock-names = "iface", "ref"; 3407 3408 status = "disabled"; 3409 }; 3410 3411 mdss_dp: displayport-controller@ae90000 { 3412 compatible = "qcom,sc7180-dp"; 3413 status = "disabled"; 3414 3415 reg = <0 0x0ae90000 0 0x200>, 3416 <0 0x0ae90200 0 0x200>, 3417 <0 0x0ae90400 0 0xc00>, 3418 <0 0x0ae91000 0 0x400>, 3419 <0 0x0ae91400 0 0x400>; 3420 3421 interrupt-parent = <&mdss>; 3422 interrupts = <12>; 3423 3424 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3425 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3426 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3427 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3428 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3429 clock-names = "core_iface", "core_aux", "ctrl_link", 3430 "ctrl_link_iface", "stream_pixel"; 3431 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3432 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3433 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3434 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3435 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3436 phy-names = "dp"; 3437 3438 operating-points-v2 = <&dp_opp_table>; 3439 power-domains = <&rpmhpd SC7180_CX>; 3440 3441 #sound-dai-cells = <0>; 3442 3443 ports { 3444 #address-cells = <1>; 3445 #size-cells = <0>; 3446 3447 port@0 { 3448 reg = <0>; 3449 3450 dp_in: endpoint { 3451 remote-endpoint = <&dpu_intf0_out>; 3452 }; 3453 }; 3454 3455 port@1 { 3456 reg = <1>; 3457 3458 mdss_dp_out: endpoint { }; 3459 }; 3460 }; 3461 3462 dp_opp_table: opp-table { 3463 compatible = "operating-points-v2"; 3464 3465 opp-162000000 { 3466 opp-hz = /bits/ 64 <162000000>; 3467 required-opps = <&rpmhpd_opp_low_svs>; 3468 }; 3469 3470 opp-270000000 { 3471 opp-hz = /bits/ 64 <270000000>; 3472 required-opps = <&rpmhpd_opp_svs>; 3473 }; 3474 3475 opp-540000000 { 3476 opp-hz = /bits/ 64 <540000000>; 3477 required-opps = <&rpmhpd_opp_svs_l1>; 3478 }; 3479 3480 opp-810000000 { 3481 opp-hz = /bits/ 64 <810000000>; 3482 required-opps = <&rpmhpd_opp_nom>; 3483 }; 3484 }; 3485 }; 3486 }; 3487 3488 dispcc: clock-controller@af00000 { 3489 compatible = "qcom,sc7180-dispcc"; 3490 reg = <0 0x0af00000 0 0x200000>; 3491 clocks = <&rpmhcc RPMH_CXO_CLK>, 3492 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3493 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3494 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3495 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3496 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3497 clock-names = "bi_tcxo", 3498 "gcc_disp_gpll0_clk_src", 3499 "dsi0_phy_pll_out_byteclk", 3500 "dsi0_phy_pll_out_dsiclk", 3501 "dp_phy_pll_link_clk", 3502 "dp_phy_pll_vco_div_clk"; 3503 #clock-cells = <1>; 3504 #reset-cells = <1>; 3505 #power-domain-cells = <1>; 3506 }; 3507 3508 pdc: interrupt-controller@b220000 { 3509 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3510 reg = <0 0x0b220000 0 0x30000>; 3511 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3512 #interrupt-cells = <2>; 3513 interrupt-parent = <&intc>; 3514 interrupt-controller; 3515 }; 3516 3517 pdc_reset: reset-controller@b2e0000 { 3518 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3519 reg = <0 0x0b2e0000 0 0x20000>; 3520 #reset-cells = <1>; 3521 }; 3522 3523 tsens0: thermal-sensor@c263000 { 3524 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3525 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3526 <0 0x0c222000 0 0x1ff>; /* SROT */ 3527 #qcom,sensors = <15>; 3528 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3529 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3530 interrupt-names = "uplow","critical"; 3531 #thermal-sensor-cells = <1>; 3532 }; 3533 3534 tsens1: thermal-sensor@c265000 { 3535 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3536 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3537 <0 0x0c223000 0 0x1ff>; /* SROT */ 3538 #qcom,sensors = <10>; 3539 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3540 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3541 interrupt-names = "uplow","critical"; 3542 #thermal-sensor-cells = <1>; 3543 }; 3544 3545 aoss_reset: reset-controller@c2a0000 { 3546 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3547 reg = <0 0x0c2a0000 0 0x31000>; 3548 #reset-cells = <1>; 3549 }; 3550 3551 aoss_qmp: power-management@c300000 { 3552 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; 3553 reg = <0 0x0c300000 0 0x400>; 3554 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3555 mboxes = <&apss_shared 0>; 3556 3557 #clock-cells = <0>; 3558 }; 3559 3560 sram@c3f0000 { 3561 compatible = "qcom,rpmh-stats"; 3562 reg = <0 0x0c3f0000 0 0x400>; 3563 }; 3564 3565 spmi_bus: spmi@c440000 { 3566 compatible = "qcom,spmi-pmic-arb"; 3567 reg = <0 0x0c440000 0 0x1100>, 3568 <0 0x0c600000 0 0x2000000>, 3569 <0 0x0e600000 0 0x100000>, 3570 <0 0x0e700000 0 0xa0000>, 3571 <0 0x0c40a000 0 0x26000>; 3572 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3573 interrupt-names = "periph_irq"; 3574 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3575 qcom,ee = <0>; 3576 qcom,channel = <0>; 3577 #address-cells = <2>; 3578 #size-cells = <0>; 3579 interrupt-controller; 3580 #interrupt-cells = <4>; 3581 }; 3582 3583 sram@14680000 { 3584 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; 3585 reg = <0 0x14680000 0 0x2e000>; 3586 3587 #address-cells = <1>; 3588 #size-cells = <1>; 3589 3590 ranges = <0 0 0x14680000 0x2e000>; 3591 3592 ipa_modem_tables: modem-tables@28000 { 3593 reg = <0x28000 0x2000>; 3594 }; 3595 3596 pil-reloc@2a94c { 3597 compatible = "qcom,pil-reloc-info"; 3598 reg = <0x2a94c 0xc8>; 3599 }; 3600 }; 3601 3602 apps_smmu: iommu@15000000 { 3603 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3604 reg = <0 0x15000000 0 0x100000>; 3605 #iommu-cells = <2>; 3606 #global-interrupts = <1>; 3607 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3631 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3632 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3654 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3660 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3670 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3671 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3672 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3673 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3674 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3675 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3676 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3677 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3678 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3680 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3681 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3682 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3683 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3684 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3685 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3686 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3687 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3688 dma-coherent; 3689 }; 3690 3691 intc: interrupt-controller@17a00000 { 3692 compatible = "arm,gic-v3"; 3693 #address-cells = <2>; 3694 #size-cells = <2>; 3695 ranges; 3696 #interrupt-cells = <3>; 3697 interrupt-controller; 3698 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3699 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3700 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3701 3702 msi-controller@17a40000 { 3703 compatible = "arm,gic-v3-its"; 3704 msi-controller; 3705 #msi-cells = <1>; 3706 reg = <0 0x17a40000 0 0x20000>; 3707 status = "disabled"; 3708 }; 3709 }; 3710 3711 apss_shared: mailbox@17c00000 { 3712 compatible = "qcom,sc7180-apss-shared", 3713 "qcom,sdm845-apss-shared"; 3714 reg = <0 0x17c00000 0 0x10000>; 3715 #mbox-cells = <1>; 3716 }; 3717 3718 watchdog@17c10000 { 3719 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3720 reg = <0 0x17c10000 0 0x1000>; 3721 clocks = <&sleep_clk>; 3722 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 3723 }; 3724 3725 timer@17c20000 { 3726 #address-cells = <1>; 3727 #size-cells = <1>; 3728 ranges = <0 0 0 0x20000000>; 3729 compatible = "arm,armv7-timer-mem"; 3730 reg = <0 0x17c20000 0 0x1000>; 3731 3732 frame@17c21000 { 3733 frame-number = <0>; 3734 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3736 reg = <0x17c21000 0x1000>, 3737 <0x17c22000 0x1000>; 3738 }; 3739 3740 frame@17c23000 { 3741 frame-number = <1>; 3742 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3743 reg = <0x17c23000 0x1000>; 3744 status = "disabled"; 3745 }; 3746 3747 frame@17c25000 { 3748 frame-number = <2>; 3749 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3750 reg = <0x17c25000 0x1000>; 3751 status = "disabled"; 3752 }; 3753 3754 frame@17c27000 { 3755 frame-number = <3>; 3756 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3757 reg = <0x17c27000 0x1000>; 3758 status = "disabled"; 3759 }; 3760 3761 frame@17c29000 { 3762 frame-number = <4>; 3763 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3764 reg = <0x17c29000 0x1000>; 3765 status = "disabled"; 3766 }; 3767 3768 frame@17c2b000 { 3769 frame-number = <5>; 3770 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3771 reg = <0x17c2b000 0x1000>; 3772 status = "disabled"; 3773 }; 3774 3775 frame@17c2d000 { 3776 frame-number = <6>; 3777 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3778 reg = <0x17c2d000 0x1000>; 3779 status = "disabled"; 3780 }; 3781 }; 3782 3783 apps_rsc: rsc@18200000 { 3784 compatible = "qcom,sc7180-rpmh-apps-rsc", "qcom,rpmh-rsc"; 3785 reg = <0 0x18200000 0 0x10000>, 3786 <0 0x18210000 0 0x10000>, 3787 <0 0x18220000 0 0x10000>; 3788 reg-names = "drv-0", "drv-1", "drv-2"; 3789 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3792 qcom,tcs-offset = <0xd00>; 3793 qcom,drv-id = <2>; 3794 qcom,tcs-config = <ACTIVE_TCS 2>, 3795 <SLEEP_TCS 3>, 3796 <WAKE_TCS 3>, 3797 <CONTROL_TCS 1>; 3798 power-domains = <&cluster_pd>; 3799 3800 rpmhcc: clock-controller { 3801 compatible = "qcom,sc7180-rpmh-clk"; 3802 clocks = <&xo_board>; 3803 clock-names = "xo"; 3804 #clock-cells = <1>; 3805 }; 3806 3807 rpmhpd: power-controller { 3808 compatible = "qcom,sc7180-rpmhpd"; 3809 #power-domain-cells = <1>; 3810 operating-points-v2 = <&rpmhpd_opp_table>; 3811 3812 rpmhpd_opp_table: opp-table { 3813 compatible = "operating-points-v2"; 3814 3815 rpmhpd_opp_ret: opp1 { 3816 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3817 }; 3818 3819 rpmhpd_opp_min_svs: opp2 { 3820 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3821 }; 3822 3823 rpmhpd_opp_low_svs: opp3 { 3824 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3825 }; 3826 3827 rpmhpd_opp_svs: opp4 { 3828 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3829 }; 3830 3831 rpmhpd_opp_svs_l1: opp5 { 3832 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3833 }; 3834 3835 rpmhpd_opp_svs_l2: opp6 { 3836 opp-level = <224>; 3837 }; 3838 3839 rpmhpd_opp_nom: opp7 { 3840 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3841 }; 3842 3843 rpmhpd_opp_nom_l1: opp8 { 3844 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3845 }; 3846 3847 rpmhpd_opp_nom_l2: opp9 { 3848 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3849 }; 3850 3851 rpmhpd_opp_turbo: opp10 { 3852 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3853 }; 3854 3855 rpmhpd_opp_turbo_l1: opp11 { 3856 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3857 }; 3858 }; 3859 }; 3860 3861 apps_bcm_voter: bcm-voter { 3862 compatible = "qcom,bcm-voter"; 3863 }; 3864 }; 3865 3866 osm_l3: interconnect@18321000 { 3867 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3"; 3868 reg = <0 0x18321000 0 0x1400>; 3869 3870 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3871 clock-names = "xo", "alternate"; 3872 3873 #interconnect-cells = <1>; 3874 }; 3875 3876 cpufreq_hw: cpufreq@18323000 { 3877 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw"; 3878 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3879 reg-names = "freq-domain0", "freq-domain1"; 3880 3881 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3882 clock-names = "xo", "alternate"; 3883 3884 #freq-domain-cells = <1>; 3885 #clock-cells = <1>; 3886 }; 3887 3888 wifi: wifi@18800000 { 3889 compatible = "qcom,wcn3990-wifi"; 3890 reg = <0 0x18800000 0 0x800000>; 3891 reg-names = "membase"; 3892 iommus = <&apps_smmu 0xc0 0x1>; 3893 interrupts = 3894 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3895 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3896 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3897 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3898 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3899 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3900 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3901 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3902 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3903 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3904 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3905 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3906 memory-region = <&wlan_mem>; 3907 qcom,msa-fixed-perm; 3908 status = "disabled"; 3909 }; 3910 3911 remoteproc_adsp: remoteproc@62400000 { 3912 compatible = "qcom,sc7180-adsp-pas"; 3913 reg = <0 0x62400000 0 0x100>; 3914 3915 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3916 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3917 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3918 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3919 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3920 interrupt-names = "wdog", 3921 "fatal", 3922 "ready", 3923 "handover", 3924 "stop-ack"; 3925 3926 clocks = <&rpmhcc RPMH_CXO_CLK>; 3927 clock-names = "xo"; 3928 3929 power-domains = <&rpmhpd SC7180_LCX>, 3930 <&rpmhpd SC7180_LMX>; 3931 power-domain-names = "lcx", "lmx"; 3932 3933 qcom,qmp = <&aoss_qmp>; 3934 qcom,smem-states = <&adsp_smp2p_out 0>; 3935 qcom,smem-state-names = "stop"; 3936 3937 status = "disabled"; 3938 3939 glink-edge { 3940 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3941 label = "lpass"; 3942 qcom,remote-pid = <2>; 3943 mboxes = <&apss_shared 8>; 3944 3945 apr { 3946 compatible = "qcom,apr-v2"; 3947 qcom,glink-channels = "apr_audio_svc"; 3948 qcom,domain = <APR_DOMAIN_ADSP>; 3949 #address-cells = <1>; 3950 #size-cells = <0>; 3951 3952 service@3 { 3953 compatible = "qcom,q6core"; 3954 reg = <APR_SVC_ADSP_CORE>; 3955 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3956 }; 3957 3958 q6afe: service@4 { 3959 compatible = "qcom,q6afe"; 3960 reg = <APR_SVC_AFE>; 3961 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3962 3963 q6afedai: dais { 3964 compatible = "qcom,q6afe-dais"; 3965 #address-cells = <1>; 3966 #size-cells = <0>; 3967 #sound-dai-cells = <1>; 3968 }; 3969 3970 q6afecc: clock-controller { 3971 compatible = "qcom,q6afe-clocks"; 3972 #clock-cells = <2>; 3973 }; 3974 }; 3975 3976 q6asm: service@7 { 3977 compatible = "qcom,q6asm"; 3978 reg = <APR_SVC_ASM>; 3979 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3980 3981 q6asmdai: dais { 3982 compatible = "qcom,q6asm-dais"; 3983 #address-cells = <1>; 3984 #size-cells = <0>; 3985 #sound-dai-cells = <1>; 3986 iommus = <&apps_smmu 0x1001 0x0>; 3987 }; 3988 }; 3989 3990 q6adm: service@8 { 3991 compatible = "qcom,q6adm"; 3992 reg = <APR_SVC_ADM>; 3993 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3994 3995 q6routing: routing { 3996 compatible = "qcom,q6adm-routing"; 3997 #sound-dai-cells = <0>; 3998 }; 3999 }; 4000 }; 4001 4002 fastrpc { 4003 compatible = "qcom,fastrpc"; 4004 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4005 label = "adsp"; 4006 #address-cells = <1>; 4007 #size-cells = <0>; 4008 4009 compute-cb@3 { 4010 compatible = "qcom,fastrpc-compute-cb"; 4011 reg = <3>; 4012 iommus = <&apps_smmu 0x1003 0x0>; 4013 }; 4014 4015 compute-cb@4 { 4016 compatible = "qcom,fastrpc-compute-cb"; 4017 reg = <4>; 4018 iommus = <&apps_smmu 0x1004 0x0>; 4019 }; 4020 4021 compute-cb@5 { 4022 compatible = "qcom,fastrpc-compute-cb"; 4023 reg = <5>; 4024 iommus = <&apps_smmu 0x1005 0x0>; 4025 qcom,nsessions = <5>; 4026 }; 4027 }; 4028 }; 4029 }; 4030 4031 lpasscc: clock-controller@62d00000 { 4032 compatible = "qcom,sc7180-lpasscorecc"; 4033 reg = <0 0x62d00000 0 0x50000>, 4034 <0 0x62780000 0 0x30000>; 4035 reg-names = "lpass_core_cc", "lpass_audio_cc"; 4036 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 4037 <&rpmhcc RPMH_CXO_CLK>; 4038 clock-names = "iface", "bi_tcxo"; 4039 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 4040 #clock-cells = <1>; 4041 #power-domain-cells = <1>; 4042 4043 status = "reserved"; /* Controlled by ADSP */ 4044 }; 4045 4046 lpass_cpu: lpass@62d87000 { 4047 compatible = "qcom,sc7180-lpass-cpu"; 4048 4049 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 4050 reg-names = "lpass-hdmiif", "lpass-lpaif"; 4051 4052 iommus = <&apps_smmu 0x1020 0>, 4053 <&apps_smmu 0x1021 0>, 4054 <&apps_smmu 0x1032 0>; 4055 4056 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 4057 required-opps = <&rpmhpd_opp_nom>; 4058 4059 status = "disabled"; 4060 4061 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 4062 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 4063 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 4064 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 4065 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 4066 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 4067 4068 clock-names = "pcnoc-sway-clk", "audio-core", 4069 "mclk0", "pcnoc-mport-clk", 4070 "mi2s-bit-clk0", "mi2s-bit-clk1"; 4071 4072 4073 #sound-dai-cells = <1>; 4074 #address-cells = <1>; 4075 #size-cells = <0>; 4076 4077 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 4079 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 4080 }; 4081 4082 lpass_hm: clock-controller@63000000 { 4083 compatible = "qcom,sc7180-lpasshm"; 4084 reg = <0 0x63000000 0 0x28>; 4085 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 4086 <&rpmhcc RPMH_CXO_CLK>; 4087 clock-names = "iface", "bi_tcxo"; 4088 power-domains = <&rpmhpd SC7180_CX>; 4089 4090 #clock-cells = <1>; 4091 #power-domain-cells = <1>; 4092 4093 status = "reserved"; /* Controlled by ADSP */ 4094 }; 4095 }; 4096 4097 thermal-zones { 4098 cpu0_thermal: cpu0-thermal { 4099 polling-delay-passive = <250>; 4100 4101 thermal-sensors = <&tsens0 1>; 4102 sustainable-power = <1052>; 4103 4104 trips { 4105 cpu0_alert0: trip-point0 { 4106 temperature = <90000>; 4107 hysteresis = <2000>; 4108 type = "passive"; 4109 }; 4110 4111 cpu0_alert1: trip-point1 { 4112 temperature = <95000>; 4113 hysteresis = <2000>; 4114 type = "passive"; 4115 }; 4116 4117 cpu0_crit: cpu-crit { 4118 temperature = <110000>; 4119 hysteresis = <1000>; 4120 type = "critical"; 4121 }; 4122 }; 4123 4124 cooling-maps { 4125 map0 { 4126 trip = <&cpu0_alert0>; 4127 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4128 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4129 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4130 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4131 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4132 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4133 }; 4134 map1 { 4135 trip = <&cpu0_alert1>; 4136 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4137 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4138 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4139 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4140 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4141 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4142 }; 4143 }; 4144 }; 4145 4146 cpu1_thermal: cpu1-thermal { 4147 polling-delay-passive = <250>; 4148 4149 thermal-sensors = <&tsens0 2>; 4150 sustainable-power = <1052>; 4151 4152 trips { 4153 cpu1_alert0: trip-point0 { 4154 temperature = <90000>; 4155 hysteresis = <2000>; 4156 type = "passive"; 4157 }; 4158 4159 cpu1_alert1: trip-point1 { 4160 temperature = <95000>; 4161 hysteresis = <2000>; 4162 type = "passive"; 4163 }; 4164 4165 cpu1_crit: cpu-crit { 4166 temperature = <110000>; 4167 hysteresis = <1000>; 4168 type = "critical"; 4169 }; 4170 }; 4171 4172 cooling-maps { 4173 map0 { 4174 trip = <&cpu1_alert0>; 4175 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4176 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4177 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4178 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4179 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4180 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4181 }; 4182 map1 { 4183 trip = <&cpu1_alert1>; 4184 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4185 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4186 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4187 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4188 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4189 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4190 }; 4191 }; 4192 }; 4193 4194 cpu2_thermal: cpu2-thermal { 4195 polling-delay-passive = <250>; 4196 4197 thermal-sensors = <&tsens0 3>; 4198 sustainable-power = <1052>; 4199 4200 trips { 4201 cpu2_alert0: trip-point0 { 4202 temperature = <90000>; 4203 hysteresis = <2000>; 4204 type = "passive"; 4205 }; 4206 4207 cpu2_alert1: trip-point1 { 4208 temperature = <95000>; 4209 hysteresis = <2000>; 4210 type = "passive"; 4211 }; 4212 4213 cpu2_crit: cpu-crit { 4214 temperature = <110000>; 4215 hysteresis = <1000>; 4216 type = "critical"; 4217 }; 4218 }; 4219 4220 cooling-maps { 4221 map0 { 4222 trip = <&cpu2_alert0>; 4223 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4224 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4225 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4226 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4227 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4228 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4229 }; 4230 map1 { 4231 trip = <&cpu2_alert1>; 4232 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4233 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4234 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4235 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4236 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4237 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4238 }; 4239 }; 4240 }; 4241 4242 cpu3_thermal: cpu3-thermal { 4243 polling-delay-passive = <250>; 4244 4245 thermal-sensors = <&tsens0 4>; 4246 sustainable-power = <1052>; 4247 4248 trips { 4249 cpu3_alert0: trip-point0 { 4250 temperature = <90000>; 4251 hysteresis = <2000>; 4252 type = "passive"; 4253 }; 4254 4255 cpu3_alert1: trip-point1 { 4256 temperature = <95000>; 4257 hysteresis = <2000>; 4258 type = "passive"; 4259 }; 4260 4261 cpu3_crit: cpu-crit { 4262 temperature = <110000>; 4263 hysteresis = <1000>; 4264 type = "critical"; 4265 }; 4266 }; 4267 4268 cooling-maps { 4269 map0 { 4270 trip = <&cpu3_alert0>; 4271 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4272 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4273 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4274 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4275 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4276 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4277 }; 4278 map1 { 4279 trip = <&cpu3_alert1>; 4280 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4281 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4282 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4283 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4284 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4285 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4286 }; 4287 }; 4288 }; 4289 4290 cpu4_thermal: cpu4-thermal { 4291 polling-delay-passive = <250>; 4292 4293 thermal-sensors = <&tsens0 5>; 4294 sustainable-power = <1052>; 4295 4296 trips { 4297 cpu4_alert0: trip-point0 { 4298 temperature = <90000>; 4299 hysteresis = <2000>; 4300 type = "passive"; 4301 }; 4302 4303 cpu4_alert1: trip-point1 { 4304 temperature = <95000>; 4305 hysteresis = <2000>; 4306 type = "passive"; 4307 }; 4308 4309 cpu4_crit: cpu-crit { 4310 temperature = <110000>; 4311 hysteresis = <1000>; 4312 type = "critical"; 4313 }; 4314 }; 4315 4316 cooling-maps { 4317 map0 { 4318 trip = <&cpu4_alert0>; 4319 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4320 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4321 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4322 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4323 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4324 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4325 }; 4326 map1 { 4327 trip = <&cpu4_alert1>; 4328 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4329 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4330 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4331 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4332 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4333 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4334 }; 4335 }; 4336 }; 4337 4338 cpu5_thermal: cpu5-thermal { 4339 polling-delay-passive = <250>; 4340 4341 thermal-sensors = <&tsens0 6>; 4342 sustainable-power = <1052>; 4343 4344 trips { 4345 cpu5_alert0: trip-point0 { 4346 temperature = <90000>; 4347 hysteresis = <2000>; 4348 type = "passive"; 4349 }; 4350 4351 cpu5_alert1: trip-point1 { 4352 temperature = <95000>; 4353 hysteresis = <2000>; 4354 type = "passive"; 4355 }; 4356 4357 cpu5_crit: cpu-crit { 4358 temperature = <110000>; 4359 hysteresis = <1000>; 4360 type = "critical"; 4361 }; 4362 }; 4363 4364 cooling-maps { 4365 map0 { 4366 trip = <&cpu5_alert0>; 4367 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4368 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4369 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4370 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4371 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4372 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4373 }; 4374 map1 { 4375 trip = <&cpu5_alert1>; 4376 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4377 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4378 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4379 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4380 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4381 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4382 }; 4383 }; 4384 }; 4385 4386 cpu6_thermal: cpu6-thermal { 4387 polling-delay-passive = <250>; 4388 4389 thermal-sensors = <&tsens0 9>; 4390 sustainable-power = <1425>; 4391 4392 trips { 4393 cpu6_alert0: trip-point0 { 4394 temperature = <90000>; 4395 hysteresis = <2000>; 4396 type = "passive"; 4397 }; 4398 4399 cpu6_alert1: trip-point1 { 4400 temperature = <95000>; 4401 hysteresis = <2000>; 4402 type = "passive"; 4403 }; 4404 4405 cpu6_crit: cpu-crit { 4406 temperature = <110000>; 4407 hysteresis = <1000>; 4408 type = "critical"; 4409 }; 4410 }; 4411 4412 cooling-maps { 4413 map0 { 4414 trip = <&cpu6_alert0>; 4415 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4416 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4417 }; 4418 map1 { 4419 trip = <&cpu6_alert1>; 4420 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4421 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4422 }; 4423 }; 4424 }; 4425 4426 cpu7_thermal: cpu7-thermal { 4427 polling-delay-passive = <250>; 4428 4429 thermal-sensors = <&tsens0 10>; 4430 sustainable-power = <1425>; 4431 4432 trips { 4433 cpu7_alert0: trip-point0 { 4434 temperature = <90000>; 4435 hysteresis = <2000>; 4436 type = "passive"; 4437 }; 4438 4439 cpu7_alert1: trip-point1 { 4440 temperature = <95000>; 4441 hysteresis = <2000>; 4442 type = "passive"; 4443 }; 4444 4445 cpu7_crit: cpu-crit { 4446 temperature = <110000>; 4447 hysteresis = <1000>; 4448 type = "critical"; 4449 }; 4450 }; 4451 4452 cooling-maps { 4453 map0 { 4454 trip = <&cpu7_alert0>; 4455 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4456 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4457 }; 4458 map1 { 4459 trip = <&cpu7_alert1>; 4460 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4461 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4462 }; 4463 }; 4464 }; 4465 4466 cpu8_thermal: cpu8-thermal { 4467 polling-delay-passive = <250>; 4468 4469 thermal-sensors = <&tsens0 11>; 4470 sustainable-power = <1425>; 4471 4472 trips { 4473 cpu8_alert0: trip-point0 { 4474 temperature = <90000>; 4475 hysteresis = <2000>; 4476 type = "passive"; 4477 }; 4478 4479 cpu8_alert1: trip-point1 { 4480 temperature = <95000>; 4481 hysteresis = <2000>; 4482 type = "passive"; 4483 }; 4484 4485 cpu8_crit: cpu-crit { 4486 temperature = <110000>; 4487 hysteresis = <1000>; 4488 type = "critical"; 4489 }; 4490 }; 4491 4492 cooling-maps { 4493 map0 { 4494 trip = <&cpu8_alert0>; 4495 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4496 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4497 }; 4498 map1 { 4499 trip = <&cpu8_alert1>; 4500 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4501 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4502 }; 4503 }; 4504 }; 4505 4506 cpu9_thermal: cpu9-thermal { 4507 polling-delay-passive = <250>; 4508 4509 thermal-sensors = <&tsens0 12>; 4510 sustainable-power = <1425>; 4511 4512 trips { 4513 cpu9_alert0: trip-point0 { 4514 temperature = <90000>; 4515 hysteresis = <2000>; 4516 type = "passive"; 4517 }; 4518 4519 cpu9_alert1: trip-point1 { 4520 temperature = <95000>; 4521 hysteresis = <2000>; 4522 type = "passive"; 4523 }; 4524 4525 cpu9_crit: cpu-crit { 4526 temperature = <110000>; 4527 hysteresis = <1000>; 4528 type = "critical"; 4529 }; 4530 }; 4531 4532 cooling-maps { 4533 map0 { 4534 trip = <&cpu9_alert0>; 4535 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4536 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4537 }; 4538 map1 { 4539 trip = <&cpu9_alert1>; 4540 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4541 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4542 }; 4543 }; 4544 }; 4545 4546 aoss0-thermal { 4547 polling-delay-passive = <250>; 4548 4549 thermal-sensors = <&tsens0 0>; 4550 4551 trips { 4552 aoss0_alert0: trip-point0 { 4553 temperature = <90000>; 4554 hysteresis = <2000>; 4555 type = "hot"; 4556 }; 4557 4558 aoss0_crit: aoss0-crit { 4559 temperature = <110000>; 4560 hysteresis = <2000>; 4561 type = "critical"; 4562 }; 4563 }; 4564 }; 4565 4566 cpuss0-thermal { 4567 polling-delay-passive = <250>; 4568 4569 thermal-sensors = <&tsens0 7>; 4570 4571 trips { 4572 cpuss0_alert0: trip-point0 { 4573 temperature = <90000>; 4574 hysteresis = <2000>; 4575 type = "hot"; 4576 }; 4577 cpuss0_crit: cluster0-crit { 4578 temperature = <110000>; 4579 hysteresis = <2000>; 4580 type = "critical"; 4581 }; 4582 }; 4583 }; 4584 4585 cpuss1-thermal { 4586 polling-delay-passive = <250>; 4587 4588 thermal-sensors = <&tsens0 8>; 4589 4590 trips { 4591 cpuss1_alert0: trip-point0 { 4592 temperature = <90000>; 4593 hysteresis = <2000>; 4594 type = "hot"; 4595 }; 4596 cpuss1_crit: cluster0-crit { 4597 temperature = <110000>; 4598 hysteresis = <2000>; 4599 type = "critical"; 4600 }; 4601 }; 4602 }; 4603 4604 gpuss0-thermal { 4605 polling-delay-passive = <250>; 4606 4607 thermal-sensors = <&tsens0 13>; 4608 4609 trips { 4610 gpuss0_alert0: trip-point0 { 4611 temperature = <95000>; 4612 hysteresis = <2000>; 4613 type = "passive"; 4614 }; 4615 4616 gpuss0_crit: gpuss0-crit { 4617 temperature = <110000>; 4618 hysteresis = <2000>; 4619 type = "critical"; 4620 }; 4621 }; 4622 4623 cooling-maps { 4624 map0 { 4625 trip = <&gpuss0_alert0>; 4626 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4627 }; 4628 }; 4629 }; 4630 4631 gpuss1-thermal { 4632 polling-delay-passive = <250>; 4633 4634 thermal-sensors = <&tsens0 14>; 4635 4636 trips { 4637 gpuss1_alert0: trip-point0 { 4638 temperature = <95000>; 4639 hysteresis = <2000>; 4640 type = "passive"; 4641 }; 4642 4643 gpuss1_crit: gpuss1-crit { 4644 temperature = <110000>; 4645 hysteresis = <2000>; 4646 type = "critical"; 4647 }; 4648 }; 4649 4650 cooling-maps { 4651 map0 { 4652 trip = <&gpuss1_alert0>; 4653 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4654 }; 4655 }; 4656 }; 4657 4658 aoss1-thermal { 4659 polling-delay-passive = <250>; 4660 4661 thermal-sensors = <&tsens1 0>; 4662 4663 trips { 4664 aoss1_alert0: trip-point0 { 4665 temperature = <90000>; 4666 hysteresis = <2000>; 4667 type = "hot"; 4668 }; 4669 4670 aoss1_crit: aoss1-crit { 4671 temperature = <110000>; 4672 hysteresis = <2000>; 4673 type = "critical"; 4674 }; 4675 }; 4676 }; 4677 4678 cwlan-thermal { 4679 polling-delay-passive = <250>; 4680 4681 thermal-sensors = <&tsens1 1>; 4682 4683 trips { 4684 cwlan_alert0: trip-point0 { 4685 temperature = <90000>; 4686 hysteresis = <2000>; 4687 type = "hot"; 4688 }; 4689 4690 cwlan_crit: cwlan-crit { 4691 temperature = <110000>; 4692 hysteresis = <2000>; 4693 type = "critical"; 4694 }; 4695 }; 4696 }; 4697 4698 audio-thermal { 4699 polling-delay-passive = <250>; 4700 4701 thermal-sensors = <&tsens1 2>; 4702 4703 trips { 4704 audio_alert0: trip-point0 { 4705 temperature = <90000>; 4706 hysteresis = <2000>; 4707 type = "hot"; 4708 }; 4709 4710 audio_crit: audio-crit { 4711 temperature = <110000>; 4712 hysteresis = <2000>; 4713 type = "critical"; 4714 }; 4715 }; 4716 }; 4717 4718 ddr-thermal { 4719 polling-delay-passive = <250>; 4720 4721 thermal-sensors = <&tsens1 3>; 4722 4723 trips { 4724 ddr_alert0: trip-point0 { 4725 temperature = <90000>; 4726 hysteresis = <2000>; 4727 type = "hot"; 4728 }; 4729 4730 ddr_crit: ddr-crit { 4731 temperature = <110000>; 4732 hysteresis = <2000>; 4733 type = "critical"; 4734 }; 4735 }; 4736 }; 4737 4738 q6-hvx-thermal { 4739 polling-delay-passive = <250>; 4740 4741 thermal-sensors = <&tsens1 4>; 4742 4743 trips { 4744 q6_hvx_alert0: trip-point0 { 4745 temperature = <90000>; 4746 hysteresis = <2000>; 4747 type = "hot"; 4748 }; 4749 4750 q6_hvx_crit: q6-hvx-crit { 4751 temperature = <110000>; 4752 hysteresis = <2000>; 4753 type = "critical"; 4754 }; 4755 }; 4756 }; 4757 4758 camera-thermal { 4759 polling-delay-passive = <250>; 4760 4761 thermal-sensors = <&tsens1 5>; 4762 4763 trips { 4764 camera_alert0: trip-point0 { 4765 temperature = <90000>; 4766 hysteresis = <2000>; 4767 type = "hot"; 4768 }; 4769 4770 camera_crit: camera-crit { 4771 temperature = <110000>; 4772 hysteresis = <2000>; 4773 type = "critical"; 4774 }; 4775 }; 4776 }; 4777 4778 mdm-core-thermal { 4779 polling-delay-passive = <250>; 4780 4781 thermal-sensors = <&tsens1 6>; 4782 4783 trips { 4784 mdm_alert0: trip-point0 { 4785 temperature = <90000>; 4786 hysteresis = <2000>; 4787 type = "hot"; 4788 }; 4789 4790 mdm_crit: mdm-crit { 4791 temperature = <110000>; 4792 hysteresis = <2000>; 4793 type = "critical"; 4794 }; 4795 }; 4796 }; 4797 4798 mdm-dsp-thermal { 4799 polling-delay-passive = <250>; 4800 4801 thermal-sensors = <&tsens1 7>; 4802 4803 trips { 4804 mdm_dsp_alert0: trip-point0 { 4805 temperature = <90000>; 4806 hysteresis = <2000>; 4807 type = "hot"; 4808 }; 4809 4810 mdm_dsp_crit: mdm-dsp-crit { 4811 temperature = <110000>; 4812 hysteresis = <2000>; 4813 type = "critical"; 4814 }; 4815 }; 4816 }; 4817 4818 npu-thermal { 4819 polling-delay-passive = <250>; 4820 4821 thermal-sensors = <&tsens1 8>; 4822 4823 trips { 4824 npu_alert0: trip-point0 { 4825 temperature = <90000>; 4826 hysteresis = <2000>; 4827 type = "hot"; 4828 }; 4829 4830 npu_crit: npu-crit { 4831 temperature = <110000>; 4832 hysteresis = <2000>; 4833 type = "critical"; 4834 }; 4835 }; 4836 }; 4837 4838 video-thermal { 4839 polling-delay-passive = <250>; 4840 4841 thermal-sensors = <&tsens1 9>; 4842 4843 trips { 4844 video_alert0: trip-point0 { 4845 temperature = <90000>; 4846 hysteresis = <2000>; 4847 type = "hot"; 4848 }; 4849 4850 video_crit: video-crit { 4851 temperature = <110000>; 4852 hysteresis = <2000>; 4853 type = "critical"; 4854 }; 4855 }; 4856 }; 4857 }; 4858 4859 timer { 4860 compatible = "arm,armv8-timer"; 4861 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4862 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4863 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4864 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4865 }; 4866}; 4867