1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sc7180.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 clock-frequency = <38400000>; 23 #clock-cells = <0>; 24 }; 25 26 sleep_clk: sleep-clk { 27 compatible = "fixed-clock"; 28 clock-frequency = <32764>; 29 #clock-cells = <0>; 30 }; 31 }; 32 33 reserved_memory: reserved-memory { 34 #address-cells = <2>; 35 #size-cells = <2>; 36 ranges; 37 38 aop_cmd_db_mem: memory@80820000 { 39 reg = <0x0 0x80820000 0x0 0x20000>; 40 compatible = "qcom,cmd-db"; 41 no-map; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 CPU0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,armv8"; 52 reg = <0x0 0x0>; 53 enable-method = "psci"; 54 next-level-cache = <&L2_0>; 55 L2_0: l2-cache { 56 compatible = "cache"; 57 next-level-cache = <&L3_0>; 58 L3_0: l3-cache { 59 compatible = "cache"; 60 }; 61 }; 62 }; 63 64 CPU1: cpu@100 { 65 device_type = "cpu"; 66 compatible = "arm,armv8"; 67 reg = <0x0 0x100>; 68 enable-method = "psci"; 69 next-level-cache = <&L2_100>; 70 L2_100: l2-cache { 71 compatible = "cache"; 72 next-level-cache = <&L3_0>; 73 }; 74 }; 75 76 CPU2: cpu@200 { 77 device_type = "cpu"; 78 compatible = "arm,armv8"; 79 reg = <0x0 0x200>; 80 enable-method = "psci"; 81 next-level-cache = <&L2_200>; 82 L2_200: l2-cache { 83 compatible = "cache"; 84 next-level-cache = <&L3_0>; 85 }; 86 }; 87 88 CPU3: cpu@300 { 89 device_type = "cpu"; 90 compatible = "arm,armv8"; 91 reg = <0x0 0x300>; 92 enable-method = "psci"; 93 next-level-cache = <&L2_300>; 94 L2_300: l2-cache { 95 compatible = "cache"; 96 next-level-cache = <&L3_0>; 97 }; 98 }; 99 100 CPU4: cpu@400 { 101 device_type = "cpu"; 102 compatible = "arm,armv8"; 103 reg = <0x0 0x400>; 104 enable-method = "psci"; 105 next-level-cache = <&L2_400>; 106 L2_400: l2-cache { 107 compatible = "cache"; 108 next-level-cache = <&L3_0>; 109 }; 110 }; 111 112 CPU5: cpu@500 { 113 device_type = "cpu"; 114 compatible = "arm,armv8"; 115 reg = <0x0 0x500>; 116 enable-method = "psci"; 117 next-level-cache = <&L2_500>; 118 L2_500: l2-cache { 119 compatible = "cache"; 120 next-level-cache = <&L3_0>; 121 }; 122 }; 123 124 CPU6: cpu@600 { 125 device_type = "cpu"; 126 compatible = "arm,armv8"; 127 reg = <0x0 0x600>; 128 enable-method = "psci"; 129 next-level-cache = <&L2_600>; 130 L2_600: l2-cache { 131 compatible = "cache"; 132 next-level-cache = <&L3_0>; 133 }; 134 }; 135 136 CPU7: cpu@700 { 137 device_type = "cpu"; 138 compatible = "arm,armv8"; 139 reg = <0x0 0x700>; 140 enable-method = "psci"; 141 next-level-cache = <&L2_700>; 142 L2_700: l2-cache { 143 compatible = "cache"; 144 next-level-cache = <&L3_0>; 145 }; 146 }; 147 }; 148 149 memory@80000000 { 150 device_type = "memory"; 151 /* We expect the bootloader to fill in the size */ 152 reg = <0 0x80000000 0 0>; 153 }; 154 155 pmu { 156 compatible = "arm,armv8-pmuv3"; 157 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 158 }; 159 160 psci { 161 compatible = "arm,psci-1.0"; 162 method = "smc"; 163 }; 164 165 soc: soc { 166 #address-cells = <2>; 167 #size-cells = <2>; 168 ranges = <0 0 0 0 0x10 0>; 169 dma-ranges = <0 0 0 0 0x10 0>; 170 compatible = "simple-bus"; 171 172 gcc: clock-controller@100000 { 173 compatible = "qcom,gcc-sc7180"; 174 reg = <0 0x00100000 0 0x1f0000>; 175 #clock-cells = <1>; 176 #reset-cells = <1>; 177 #power-domain-cells = <1>; 178 }; 179 180 qupv3_id_1: geniqup@ac0000 { 181 compatible = "qcom,geni-se-qup"; 182 reg = <0 0x00ac0000 0 0x6000>; 183 clock-names = "m-ahb", "s-ahb"; 184 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 185 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 186 #address-cells = <2>; 187 #size-cells = <2>; 188 ranges; 189 status = "disabled"; 190 191 uart8: serial@a88000 { 192 compatible = "qcom,geni-debug-uart"; 193 reg = <0 0x00a88000 0 0x4000>; 194 clock-names = "se"; 195 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&qup_uart8_default>; 198 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 199 status = "disabled"; 200 }; 201 }; 202 203 tlmm: pinctrl@3500000 { 204 compatible = "qcom,sc7180-pinctrl"; 205 reg = <0 0x03500000 0 0x300000>, 206 <0 0x03900000 0 0x300000>, 207 <0 0x03d00000 0 0x300000>; 208 reg-names = "west", "north", "south"; 209 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 210 gpio-controller; 211 #gpio-cells = <2>; 212 interrupt-controller; 213 #interrupt-cells = <2>; 214 gpio-ranges = <&tlmm 0 0 120>; 215 216 qup_uart8_default: qup-uart8-default { 217 pinmux { 218 pins = "gpio44", "gpio45"; 219 function = "qup12"; 220 }; 221 }; 222 }; 223 224 apps_smmu: iommu@15000000 { 225 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 226 reg = <0 0x15000000 0 0x100000>; 227 #iommu-cells = <2>; 228 #global-interrupts = <1>; 229 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 310 }; 311 312 intc: interrupt-controller@17a00000 { 313 compatible = "arm,gic-v3"; 314 #address-cells = <2>; 315 #size-cells = <2>; 316 ranges; 317 #interrupt-cells = <3>; 318 interrupt-controller; 319 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 320 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 321 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 322 323 gic-its@17a40000 { 324 compatible = "arm,gic-v3-its"; 325 msi-controller; 326 #msi-cells = <1>; 327 reg = <0 0x17a40000 0 0x20000>; 328 status = "disabled"; 329 }; 330 }; 331 332 timer@17c20000{ 333 #address-cells = <2>; 334 #size-cells = <2>; 335 ranges; 336 compatible = "arm,armv7-timer-mem"; 337 reg = <0 0x17c20000 0 0x1000>; 338 339 frame@17c21000 { 340 frame-number = <0>; 341 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 343 reg = <0 0x17c21000 0 0x1000>, 344 <0 0x17c22000 0 0x1000>; 345 }; 346 347 frame@17c23000 { 348 frame-number = <1>; 349 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 350 reg = <0 0x17c23000 0 0x1000>; 351 status = "disabled"; 352 }; 353 354 frame@17c25000 { 355 frame-number = <2>; 356 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 357 reg = <0 0x17c25000 0 0x1000>; 358 status = "disabled"; 359 }; 360 361 frame@17c27000 { 362 frame-number = <3>; 363 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 364 reg = <0 0x17c27000 0 0x1000>; 365 status = "disabled"; 366 }; 367 368 frame@17c29000 { 369 frame-number = <4>; 370 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 371 reg = <0 0x17c29000 0 0x1000>; 372 status = "disabled"; 373 }; 374 375 frame@17c2b000 { 376 frame-number = <5>; 377 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 378 reg = <0 0x17c2b000 0 0x1000>; 379 status = "disabled"; 380 }; 381 382 frame@17c2d000 { 383 frame-number = <6>; 384 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 385 reg = <0 0x17c2d000 0 0x1000>; 386 status = "disabled"; 387 }; 388 }; 389 }; 390 391 timer { 392 compatible = "arm,armv8-timer"; 393 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 394 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 395 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 396 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 397 }; 398}; 399