1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,gcc-sc7180.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 11#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sc7180.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc7180.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/phy/phy-qcom-qusb2.h> 18#include <dt-bindings/power/qcom-aoss-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/reset/qcom,sdm845-aoss.h> 21#include <dt-bindings/reset/qcom,sdm845-pdc.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 aliases { 34 mmc1 = &sdhc_1; 35 mmc2 = &sdhc_2; 36 i2c0 = &i2c0; 37 i2c1 = &i2c1; 38 i2c2 = &i2c2; 39 i2c3 = &i2c3; 40 i2c4 = &i2c4; 41 i2c5 = &i2c5; 42 i2c6 = &i2c6; 43 i2c7 = &i2c7; 44 i2c8 = &i2c8; 45 i2c9 = &i2c9; 46 i2c10 = &i2c10; 47 i2c11 = &i2c11; 48 spi0 = &spi0; 49 spi1 = &spi1; 50 spi3 = &spi3; 51 spi5 = &spi5; 52 spi6 = &spi6; 53 spi8 = &spi8; 54 spi10 = &spi10; 55 spi11 = &spi11; 56 }; 57 58 clocks { 59 xo_board: xo-board { 60 compatible = "fixed-clock"; 61 clock-frequency = <38400000>; 62 #clock-cells = <0>; 63 }; 64 65 sleep_clk: sleep-clk { 66 compatible = "fixed-clock"; 67 clock-frequency = <32764>; 68 #clock-cells = <0>; 69 }; 70 }; 71 72 reserved_memory: reserved-memory { 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges; 76 77 hyp_mem: memory@80000000 { 78 reg = <0x0 0x80000000 0x0 0x600000>; 79 no-map; 80 }; 81 82 xbl_mem: memory@80600000 { 83 reg = <0x0 0x80600000 0x0 0x200000>; 84 no-map; 85 }; 86 87 aop_mem: memory@80800000 { 88 reg = <0x0 0x80800000 0x0 0x20000>; 89 no-map; 90 }; 91 92 aop_cmd_db_mem: memory@80820000 { 93 reg = <0x0 0x80820000 0x0 0x20000>; 94 compatible = "qcom,cmd-db"; 95 no-map; 96 }; 97 98 sec_apps_mem: memory@808ff000 { 99 reg = <0x0 0x808ff000 0x0 0x1000>; 100 no-map; 101 }; 102 103 smem_mem: memory@80900000 { 104 reg = <0x0 0x80900000 0x0 0x200000>; 105 no-map; 106 }; 107 108 tz_mem: memory@80b00000 { 109 reg = <0x0 0x80b00000 0x0 0x3900000>; 110 no-map; 111 }; 112 113 rmtfs_mem: memory@84400000 { 114 compatible = "qcom,rmtfs-mem"; 115 reg = <0x0 0x84400000 0x0 0x200000>; 116 no-map; 117 118 qcom,client-id = <1>; 119 qcom,vmid = <15>; 120 }; 121 }; 122 123 cpus { 124 #address-cells = <2>; 125 #size-cells = <0>; 126 127 CPU0: cpu@0 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo468"; 130 reg = <0x0 0x0>; 131 enable-method = "psci"; 132 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 133 &LITTLE_CPU_SLEEP_1 134 &CLUSTER_SLEEP_0>; 135 capacity-dmips-mhz = <1024>; 136 dynamic-power-coefficient = <100>; 137 operating-points-v2 = <&cpu0_opp_table>; 138 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 139 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 140 next-level-cache = <&L2_0>; 141 #cooling-cells = <2>; 142 qcom,freq-domain = <&cpufreq_hw 0>; 143 L2_0: l2-cache { 144 compatible = "cache"; 145 next-level-cache = <&L3_0>; 146 L3_0: l3-cache { 147 compatible = "cache"; 148 }; 149 }; 150 }; 151 152 CPU1: cpu@100 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo468"; 155 reg = <0x0 0x100>; 156 enable-method = "psci"; 157 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 158 &LITTLE_CPU_SLEEP_1 159 &CLUSTER_SLEEP_0>; 160 capacity-dmips-mhz = <1024>; 161 dynamic-power-coefficient = <100>; 162 next-level-cache = <&L2_100>; 163 operating-points-v2 = <&cpu0_opp_table>; 164 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 165 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 166 #cooling-cells = <2>; 167 qcom,freq-domain = <&cpufreq_hw 0>; 168 L2_100: l2-cache { 169 compatible = "cache"; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU2: cpu@200 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo468"; 177 reg = <0x0 0x200>; 178 enable-method = "psci"; 179 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 180 &LITTLE_CPU_SLEEP_1 181 &CLUSTER_SLEEP_0>; 182 capacity-dmips-mhz = <1024>; 183 dynamic-power-coefficient = <100>; 184 next-level-cache = <&L2_200>; 185 operating-points-v2 = <&cpu0_opp_table>; 186 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 187 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 188 #cooling-cells = <2>; 189 qcom,freq-domain = <&cpufreq_hw 0>; 190 L2_200: l2-cache { 191 compatible = "cache"; 192 next-level-cache = <&L3_0>; 193 }; 194 }; 195 196 CPU3: cpu@300 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo468"; 199 reg = <0x0 0x300>; 200 enable-method = "psci"; 201 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 202 &LITTLE_CPU_SLEEP_1 203 &CLUSTER_SLEEP_0>; 204 capacity-dmips-mhz = <1024>; 205 dynamic-power-coefficient = <100>; 206 next-level-cache = <&L2_300>; 207 operating-points-v2 = <&cpu0_opp_table>; 208 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 209 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 210 #cooling-cells = <2>; 211 qcom,freq-domain = <&cpufreq_hw 0>; 212 L2_300: l2-cache { 213 compatible = "cache"; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU4: cpu@400 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo468"; 221 reg = <0x0 0x400>; 222 enable-method = "psci"; 223 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 224 &LITTLE_CPU_SLEEP_1 225 &CLUSTER_SLEEP_0>; 226 capacity-dmips-mhz = <1024>; 227 dynamic-power-coefficient = <100>; 228 next-level-cache = <&L2_400>; 229 operating-points-v2 = <&cpu0_opp_table>; 230 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 231 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 232 #cooling-cells = <2>; 233 qcom,freq-domain = <&cpufreq_hw 0>; 234 L2_400: l2-cache { 235 compatible = "cache"; 236 next-level-cache = <&L3_0>; 237 }; 238 }; 239 240 CPU5: cpu@500 { 241 device_type = "cpu"; 242 compatible = "qcom,kryo468"; 243 reg = <0x0 0x500>; 244 enable-method = "psci"; 245 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 246 &LITTLE_CPU_SLEEP_1 247 &CLUSTER_SLEEP_0>; 248 capacity-dmips-mhz = <1024>; 249 dynamic-power-coefficient = <100>; 250 next-level-cache = <&L2_500>; 251 operating-points-v2 = <&cpu0_opp_table>; 252 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 253 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 254 #cooling-cells = <2>; 255 qcom,freq-domain = <&cpufreq_hw 0>; 256 L2_500: l2-cache { 257 compatible = "cache"; 258 next-level-cache = <&L3_0>; 259 }; 260 }; 261 262 CPU6: cpu@600 { 263 device_type = "cpu"; 264 compatible = "qcom,kryo468"; 265 reg = <0x0 0x600>; 266 enable-method = "psci"; 267 cpu-idle-states = <&BIG_CPU_SLEEP_0 268 &BIG_CPU_SLEEP_1 269 &CLUSTER_SLEEP_0>; 270 capacity-dmips-mhz = <1740>; 271 dynamic-power-coefficient = <405>; 272 next-level-cache = <&L2_600>; 273 operating-points-v2 = <&cpu6_opp_table>; 274 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 275 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 276 #cooling-cells = <2>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 L2_600: l2-cache { 279 compatible = "cache"; 280 next-level-cache = <&L3_0>; 281 }; 282 }; 283 284 CPU7: cpu@700 { 285 device_type = "cpu"; 286 compatible = "qcom,kryo468"; 287 reg = <0x0 0x700>; 288 enable-method = "psci"; 289 cpu-idle-states = <&BIG_CPU_SLEEP_0 290 &BIG_CPU_SLEEP_1 291 &CLUSTER_SLEEP_0>; 292 capacity-dmips-mhz = <1740>; 293 dynamic-power-coefficient = <405>; 294 next-level-cache = <&L2_700>; 295 operating-points-v2 = <&cpu6_opp_table>; 296 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 297 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 298 #cooling-cells = <2>; 299 qcom,freq-domain = <&cpufreq_hw 1>; 300 L2_700: l2-cache { 301 compatible = "cache"; 302 next-level-cache = <&L3_0>; 303 }; 304 }; 305 306 cpu-map { 307 cluster0 { 308 core0 { 309 cpu = <&CPU0>; 310 }; 311 312 core1 { 313 cpu = <&CPU1>; 314 }; 315 316 core2 { 317 cpu = <&CPU2>; 318 }; 319 320 core3 { 321 cpu = <&CPU3>; 322 }; 323 324 core4 { 325 cpu = <&CPU4>; 326 }; 327 328 core5 { 329 cpu = <&CPU5>; 330 }; 331 332 core6 { 333 cpu = <&CPU6>; 334 }; 335 336 core7 { 337 cpu = <&CPU7>; 338 }; 339 }; 340 }; 341 342 idle-states { 343 entry-method = "psci"; 344 345 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 346 compatible = "arm,idle-state"; 347 idle-state-name = "little-power-down"; 348 arm,psci-suspend-param = <0x40000003>; 349 entry-latency-us = <549>; 350 exit-latency-us = <901>; 351 min-residency-us = <1774>; 352 local-timer-stop; 353 }; 354 355 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 356 compatible = "arm,idle-state"; 357 idle-state-name = "little-rail-power-down"; 358 arm,psci-suspend-param = <0x40000004>; 359 entry-latency-us = <702>; 360 exit-latency-us = <915>; 361 min-residency-us = <4001>; 362 local-timer-stop; 363 }; 364 365 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 366 compatible = "arm,idle-state"; 367 idle-state-name = "big-power-down"; 368 arm,psci-suspend-param = <0x40000003>; 369 entry-latency-us = <523>; 370 exit-latency-us = <1244>; 371 min-residency-us = <2207>; 372 local-timer-stop; 373 }; 374 375 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 376 compatible = "arm,idle-state"; 377 idle-state-name = "big-rail-power-down"; 378 arm,psci-suspend-param = <0x40000004>; 379 entry-latency-us = <526>; 380 exit-latency-us = <1854>; 381 min-residency-us = <5555>; 382 local-timer-stop; 383 }; 384 385 CLUSTER_SLEEP_0: cluster-sleep-0 { 386 compatible = "arm,idle-state"; 387 idle-state-name = "cluster-power-down"; 388 arm,psci-suspend-param = <0x40003444>; 389 entry-latency-us = <3263>; 390 exit-latency-us = <6562>; 391 min-residency-us = <9926>; 392 local-timer-stop; 393 }; 394 }; 395 }; 396 397 cpu0_opp_table: cpu0_opp_table { 398 compatible = "operating-points-v2"; 399 opp-shared; 400 401 cpu0_opp1: opp-300000000 { 402 opp-hz = /bits/ 64 <300000000>; 403 opp-peak-kBps = <1200000 4800000>; 404 }; 405 406 cpu0_opp2: opp-576000000 { 407 opp-hz = /bits/ 64 <576000000>; 408 opp-peak-kBps = <1200000 4800000>; 409 }; 410 411 cpu0_opp3: opp-768000000 { 412 opp-hz = /bits/ 64 <768000000>; 413 opp-peak-kBps = <1200000 4800000>; 414 }; 415 416 cpu0_opp4: opp-1017600000 { 417 opp-hz = /bits/ 64 <1017600000>; 418 opp-peak-kBps = <1804000 8908800>; 419 }; 420 421 cpu0_opp5: opp-1248000000 { 422 opp-hz = /bits/ 64 <1248000000>; 423 opp-peak-kBps = <2188000 12902400>; 424 }; 425 426 cpu0_opp6: opp-1324800000 { 427 opp-hz = /bits/ 64 <1324800000>; 428 opp-peak-kBps = <2188000 12902400>; 429 }; 430 431 cpu0_opp7: opp-1516800000 { 432 opp-hz = /bits/ 64 <1516800000>; 433 opp-peak-kBps = <3072000 15052800>; 434 }; 435 436 cpu0_opp8: opp-1612800000 { 437 opp-hz = /bits/ 64 <1612800000>; 438 opp-peak-kBps = <3072000 15052800>; 439 }; 440 441 cpu0_opp9: opp-1708800000 { 442 opp-hz = /bits/ 64 <1708800000>; 443 opp-peak-kBps = <3072000 15052800>; 444 }; 445 446 cpu0_opp10: opp-1804800000 { 447 opp-hz = /bits/ 64 <1804800000>; 448 opp-peak-kBps = <4068000 22425600>; 449 }; 450 }; 451 452 cpu6_opp_table: cpu6_opp_table { 453 compatible = "operating-points-v2"; 454 opp-shared; 455 456 cpu6_opp1: opp-300000000 { 457 opp-hz = /bits/ 64 <300000000>; 458 opp-peak-kBps = <2188000 8908800>; 459 }; 460 461 cpu6_opp2: opp-652800000 { 462 opp-hz = /bits/ 64 <652800000>; 463 opp-peak-kBps = <2188000 8908800>; 464 }; 465 466 cpu6_opp3: opp-825600000 { 467 opp-hz = /bits/ 64 <825600000>; 468 opp-peak-kBps = <2188000 8908800>; 469 }; 470 471 cpu6_opp4: opp-979200000 { 472 opp-hz = /bits/ 64 <979200000>; 473 opp-peak-kBps = <2188000 8908800>; 474 }; 475 476 cpu6_opp5: opp-1113600000 { 477 opp-hz = /bits/ 64 <1113600000>; 478 opp-peak-kBps = <2188000 8908800>; 479 }; 480 481 cpu6_opp6: opp-1267200000 { 482 opp-hz = /bits/ 64 <1267200000>; 483 opp-peak-kBps = <4068000 12902400>; 484 }; 485 486 cpu6_opp7: opp-1555200000 { 487 opp-hz = /bits/ 64 <1555200000>; 488 opp-peak-kBps = <4068000 15052800>; 489 }; 490 491 cpu6_opp8: opp-1708800000 { 492 opp-hz = /bits/ 64 <1708800000>; 493 opp-peak-kBps = <6220000 19353600>; 494 }; 495 496 cpu6_opp9: opp-1843200000 { 497 opp-hz = /bits/ 64 <1843200000>; 498 opp-peak-kBps = <6220000 19353600>; 499 }; 500 501 cpu6_opp10: opp-1900800000 { 502 opp-hz = /bits/ 64 <1900800000>; 503 opp-peak-kBps = <6220000 22425600>; 504 }; 505 506 cpu6_opp11: opp-1996800000 { 507 opp-hz = /bits/ 64 <1996800000>; 508 opp-peak-kBps = <6220000 22425600>; 509 }; 510 511 cpu6_opp12: opp-2112000000 { 512 opp-hz = /bits/ 64 <2112000000>; 513 opp-peak-kBps = <6220000 22425600>; 514 }; 515 516 cpu6_opp13: opp-2208000000 { 517 opp-hz = /bits/ 64 <2208000000>; 518 opp-peak-kBps = <7216000 22425600>; 519 }; 520 521 cpu6_opp14: opp-2323200000 { 522 opp-hz = /bits/ 64 <2323200000>; 523 opp-peak-kBps = <7216000 22425600>; 524 }; 525 526 cpu6_opp15: opp-2400000000 { 527 opp-hz = /bits/ 64 <2400000000>; 528 opp-peak-kBps = <8532000 23347200>; 529 }; 530 531 cpu6_opp16: opp-2553600000 { 532 opp-hz = /bits/ 64 <2553600000>; 533 opp-peak-kBps = <8532000 23347200>; 534 }; 535 }; 536 537 memory@80000000 { 538 device_type = "memory"; 539 /* We expect the bootloader to fill in the size */ 540 reg = <0 0x80000000 0 0>; 541 }; 542 543 pmu { 544 compatible = "arm,armv8-pmuv3"; 545 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 546 }; 547 548 firmware { 549 scm { 550 compatible = "qcom,scm-sc7180", "qcom,scm"; 551 }; 552 }; 553 554 tcsr_mutex: hwlock { 555 compatible = "qcom,tcsr-mutex"; 556 syscon = <&tcsr_mutex_regs 0 0x1000>; 557 #hwlock-cells = <1>; 558 }; 559 560 smem { 561 compatible = "qcom,smem"; 562 memory-region = <&smem_mem>; 563 hwlocks = <&tcsr_mutex 3>; 564 }; 565 566 smp2p-cdsp { 567 compatible = "qcom,smp2p"; 568 qcom,smem = <94>, <432>; 569 570 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 571 572 mboxes = <&apss_shared 6>; 573 574 qcom,local-pid = <0>; 575 qcom,remote-pid = <5>; 576 577 cdsp_smp2p_out: master-kernel { 578 qcom,entry-name = "master-kernel"; 579 #qcom,smem-state-cells = <1>; 580 }; 581 582 cdsp_smp2p_in: slave-kernel { 583 qcom,entry-name = "slave-kernel"; 584 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 }; 588 }; 589 590 smp2p-lpass { 591 compatible = "qcom,smp2p"; 592 qcom,smem = <443>, <429>; 593 594 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 595 596 mboxes = <&apss_shared 10>; 597 598 qcom,local-pid = <0>; 599 qcom,remote-pid = <2>; 600 601 adsp_smp2p_out: master-kernel { 602 qcom,entry-name = "master-kernel"; 603 #qcom,smem-state-cells = <1>; 604 }; 605 606 adsp_smp2p_in: slave-kernel { 607 qcom,entry-name = "slave-kernel"; 608 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 }; 612 }; 613 614 smp2p-mpss { 615 compatible = "qcom,smp2p"; 616 qcom,smem = <435>, <428>; 617 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 618 mboxes = <&apss_shared 14>; 619 qcom,local-pid = <0>; 620 qcom,remote-pid = <1>; 621 622 modem_smp2p_out: master-kernel { 623 qcom,entry-name = "master-kernel"; 624 #qcom,smem-state-cells = <1>; 625 }; 626 627 modem_smp2p_in: slave-kernel { 628 qcom,entry-name = "slave-kernel"; 629 interrupt-controller; 630 #interrupt-cells = <2>; 631 }; 632 633 ipa_smp2p_out: ipa-ap-to-modem { 634 qcom,entry-name = "ipa"; 635 #qcom,smem-state-cells = <1>; 636 }; 637 638 ipa_smp2p_in: ipa-modem-to-ap { 639 qcom,entry-name = "ipa"; 640 interrupt-controller; 641 #interrupt-cells = <2>; 642 }; 643 }; 644 645 psci { 646 compatible = "arm,psci-1.0"; 647 method = "smc"; 648 }; 649 650 soc: soc@0 { 651 #address-cells = <2>; 652 #size-cells = <2>; 653 ranges = <0 0 0 0 0x10 0>; 654 dma-ranges = <0 0 0 0 0x10 0>; 655 compatible = "simple-bus"; 656 657 gcc: clock-controller@100000 { 658 compatible = "qcom,gcc-sc7180"; 659 reg = <0 0x00100000 0 0x1f0000>; 660 clocks = <&rpmhcc RPMH_CXO_CLK>, 661 <&rpmhcc RPMH_CXO_CLK_A>, 662 <&sleep_clk>; 663 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 664 #clock-cells = <1>; 665 #reset-cells = <1>; 666 #power-domain-cells = <1>; 667 }; 668 669 qfprom: efuse@784000 { 670 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 671 reg = <0 0x00784000 0 0x8ff>, 672 <0 0x00780000 0 0x7a0>, 673 <0 0x00782000 0 0x100>, 674 <0 0x00786000 0 0x1fff>; 675 676 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 677 clock-names = "core"; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 681 qusb2p_hstx_trim: hstx-trim-primary@25b { 682 reg = <0x25b 0x1>; 683 bits = <1 3>; 684 }; 685 }; 686 687 sdhc_1: sdhci@7c4000 { 688 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 689 reg = <0 0x7c4000 0 0x1000>, 690 <0 0x07c5000 0 0x1000>; 691 reg-names = "hc", "cqhci"; 692 693 iommus = <&apps_smmu 0x60 0x0>; 694 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 696 interrupt-names = "hc_irq", "pwr_irq"; 697 698 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 699 <&gcc GCC_SDCC1_AHB_CLK>; 700 clock-names = "core", "iface"; 701 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 702 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 703 interconnect-names = "sdhc-ddr","cpu-sdhc"; 704 power-domains = <&rpmhpd SC7180_CX>; 705 operating-points-v2 = <&sdhc1_opp_table>; 706 707 bus-width = <8>; 708 non-removable; 709 supports-cqe; 710 711 mmc-ddr-1_8v; 712 mmc-hs200-1_8v; 713 mmc-hs400-1_8v; 714 mmc-hs400-enhanced-strobe; 715 716 status = "disabled"; 717 718 sdhc1_opp_table: sdhc1-opp-table { 719 compatible = "operating-points-v2"; 720 721 opp-100000000 { 722 opp-hz = /bits/ 64 <100000000>; 723 required-opps = <&rpmhpd_opp_low_svs>; 724 opp-peak-kBps = <100000 100000>; 725 opp-avg-kBps = <100000 50000>; 726 }; 727 728 opp-384000000 { 729 opp-hz = /bits/ 64 <384000000>; 730 required-opps = <&rpmhpd_opp_svs_l1>; 731 opp-peak-kBps = <600000 900000>; 732 opp-avg-kBps = <261438 300000>; 733 }; 734 }; 735 }; 736 737 qup_opp_table: qup-opp-table { 738 compatible = "operating-points-v2"; 739 740 opp-75000000 { 741 opp-hz = /bits/ 64 <75000000>; 742 required-opps = <&rpmhpd_opp_low_svs>; 743 }; 744 745 opp-100000000 { 746 opp-hz = /bits/ 64 <100000000>; 747 required-opps = <&rpmhpd_opp_svs>; 748 }; 749 750 opp-128000000 { 751 opp-hz = /bits/ 64 <128000000>; 752 required-opps = <&rpmhpd_opp_nom>; 753 }; 754 }; 755 756 qupv3_id_0: geniqup@8c0000 { 757 compatible = "qcom,geni-se-qup"; 758 reg = <0 0x008c0000 0 0x6000>; 759 clock-names = "m-ahb", "s-ahb"; 760 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 761 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 762 #address-cells = <2>; 763 #size-cells = <2>; 764 ranges; 765 iommus = <&apps_smmu 0x43 0x0>; 766 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>; 767 interconnect-names = "qup-core"; 768 status = "disabled"; 769 770 i2c0: i2c@880000 { 771 compatible = "qcom,geni-i2c"; 772 reg = <0 0x00880000 0 0x4000>; 773 clock-names = "se"; 774 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 775 pinctrl-names = "default"; 776 pinctrl-0 = <&qup_i2c0_default>; 777 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 781 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 782 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 783 interconnect-names = "qup-core", "qup-config", 784 "qup-memory"; 785 status = "disabled"; 786 }; 787 788 spi0: spi@880000 { 789 compatible = "qcom,geni-spi"; 790 reg = <0 0x00880000 0 0x4000>; 791 clock-names = "se"; 792 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 793 pinctrl-names = "default"; 794 pinctrl-0 = <&qup_spi0_default>; 795 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 796 #address-cells = <1>; 797 #size-cells = <0>; 798 power-domains = <&rpmhpd SC7180_CX>; 799 operating-points-v2 = <&qup_opp_table>; 800 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 801 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 802 interconnect-names = "qup-core", "qup-config"; 803 status = "disabled"; 804 }; 805 806 uart0: serial@880000 { 807 compatible = "qcom,geni-uart"; 808 reg = <0 0x00880000 0 0x4000>; 809 clock-names = "se"; 810 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&qup_uart0_default>; 813 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 814 power-domains = <&rpmhpd SC7180_CX>; 815 operating-points-v2 = <&qup_opp_table>; 816 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 817 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 818 interconnect-names = "qup-core", "qup-config"; 819 status = "disabled"; 820 }; 821 822 i2c1: i2c@884000 { 823 compatible = "qcom,geni-i2c"; 824 reg = <0 0x00884000 0 0x4000>; 825 clock-names = "se"; 826 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 827 pinctrl-names = "default"; 828 pinctrl-0 = <&qup_i2c1_default>; 829 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 833 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 834 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 835 interconnect-names = "qup-core", "qup-config", 836 "qup-memory"; 837 status = "disabled"; 838 }; 839 840 spi1: spi@884000 { 841 compatible = "qcom,geni-spi"; 842 reg = <0 0x00884000 0 0x4000>; 843 clock-names = "se"; 844 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 845 pinctrl-names = "default"; 846 pinctrl-0 = <&qup_spi1_default>; 847 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 848 #address-cells = <1>; 849 #size-cells = <0>; 850 power-domains = <&rpmhpd SC7180_CX>; 851 operating-points-v2 = <&qup_opp_table>; 852 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 853 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 854 interconnect-names = "qup-core", "qup-config"; 855 status = "disabled"; 856 }; 857 858 uart1: serial@884000 { 859 compatible = "qcom,geni-uart"; 860 reg = <0 0x00884000 0 0x4000>; 861 clock-names = "se"; 862 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 863 pinctrl-names = "default"; 864 pinctrl-0 = <&qup_uart1_default>; 865 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 866 power-domains = <&rpmhpd SC7180_CX>; 867 operating-points-v2 = <&qup_opp_table>; 868 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 869 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 870 interconnect-names = "qup-core", "qup-config"; 871 status = "disabled"; 872 }; 873 874 i2c2: i2c@888000 { 875 compatible = "qcom,geni-i2c"; 876 reg = <0 0x00888000 0 0x4000>; 877 clock-names = "se"; 878 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 879 pinctrl-names = "default"; 880 pinctrl-0 = <&qup_i2c2_default>; 881 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 885 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 886 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 887 interconnect-names = "qup-core", "qup-config", 888 "qup-memory"; 889 status = "disabled"; 890 }; 891 892 uart2: serial@888000 { 893 compatible = "qcom,geni-uart"; 894 reg = <0 0x00888000 0 0x4000>; 895 clock-names = "se"; 896 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 897 pinctrl-names = "default"; 898 pinctrl-0 = <&qup_uart2_default>; 899 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 900 power-domains = <&rpmhpd SC7180_CX>; 901 operating-points-v2 = <&qup_opp_table>; 902 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 903 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 904 interconnect-names = "qup-core", "qup-config"; 905 status = "disabled"; 906 }; 907 908 i2c3: i2c@88c000 { 909 compatible = "qcom,geni-i2c"; 910 reg = <0 0x0088c000 0 0x4000>; 911 clock-names = "se"; 912 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 913 pinctrl-names = "default"; 914 pinctrl-0 = <&qup_i2c3_default>; 915 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 919 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 920 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 921 interconnect-names = "qup-core", "qup-config", 922 "qup-memory"; 923 status = "disabled"; 924 }; 925 926 spi3: spi@88c000 { 927 compatible = "qcom,geni-spi"; 928 reg = <0 0x0088c000 0 0x4000>; 929 clock-names = "se"; 930 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 931 pinctrl-names = "default"; 932 pinctrl-0 = <&qup_spi3_default>; 933 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 934 #address-cells = <1>; 935 #size-cells = <0>; 936 power-domains = <&rpmhpd SC7180_CX>; 937 operating-points-v2 = <&qup_opp_table>; 938 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 939 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 940 interconnect-names = "qup-core", "qup-config"; 941 status = "disabled"; 942 }; 943 944 uart3: serial@88c000 { 945 compatible = "qcom,geni-uart"; 946 reg = <0 0x0088c000 0 0x4000>; 947 clock-names = "se"; 948 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 949 pinctrl-names = "default"; 950 pinctrl-0 = <&qup_uart3_default>; 951 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 952 power-domains = <&rpmhpd SC7180_CX>; 953 operating-points-v2 = <&qup_opp_table>; 954 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 955 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 956 interconnect-names = "qup-core", "qup-config"; 957 status = "disabled"; 958 }; 959 960 i2c4: i2c@890000 { 961 compatible = "qcom,geni-i2c"; 962 reg = <0 0x00890000 0 0x4000>; 963 clock-names = "se"; 964 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 965 pinctrl-names = "default"; 966 pinctrl-0 = <&qup_i2c4_default>; 967 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 971 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 972 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 973 interconnect-names = "qup-core", "qup-config", 974 "qup-memory"; 975 status = "disabled"; 976 }; 977 978 uart4: serial@890000 { 979 compatible = "qcom,geni-uart"; 980 reg = <0 0x00890000 0 0x4000>; 981 clock-names = "se"; 982 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 983 pinctrl-names = "default"; 984 pinctrl-0 = <&qup_uart4_default>; 985 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 986 power-domains = <&rpmhpd SC7180_CX>; 987 operating-points-v2 = <&qup_opp_table>; 988 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 989 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 990 interconnect-names = "qup-core", "qup-config"; 991 status = "disabled"; 992 }; 993 994 i2c5: i2c@894000 { 995 compatible = "qcom,geni-i2c"; 996 reg = <0 0x00894000 0 0x4000>; 997 clock-names = "se"; 998 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_i2c5_default>; 1001 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1005 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1006 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1007 interconnect-names = "qup-core", "qup-config", 1008 "qup-memory"; 1009 status = "disabled"; 1010 }; 1011 1012 spi5: spi@894000 { 1013 compatible = "qcom,geni-spi"; 1014 reg = <0 0x00894000 0 0x4000>; 1015 clock-names = "se"; 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1017 pinctrl-names = "default"; 1018 pinctrl-0 = <&qup_spi5_default>; 1019 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 power-domains = <&rpmhpd SC7180_CX>; 1023 operating-points-v2 = <&qup_opp_table>; 1024 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1025 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1026 interconnect-names = "qup-core", "qup-config"; 1027 status = "disabled"; 1028 }; 1029 1030 uart5: serial@894000 { 1031 compatible = "qcom,geni-uart"; 1032 reg = <0 0x00894000 0 0x4000>; 1033 clock-names = "se"; 1034 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1035 pinctrl-names = "default"; 1036 pinctrl-0 = <&qup_uart5_default>; 1037 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1038 power-domains = <&rpmhpd SC7180_CX>; 1039 operating-points-v2 = <&qup_opp_table>; 1040 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1041 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1042 interconnect-names = "qup-core", "qup-config"; 1043 status = "disabled"; 1044 }; 1045 }; 1046 1047 qupv3_id_1: geniqup@ac0000 { 1048 compatible = "qcom,geni-se-qup"; 1049 reg = <0 0x00ac0000 0 0x6000>; 1050 clock-names = "m-ahb", "s-ahb"; 1051 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1052 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1053 #address-cells = <2>; 1054 #size-cells = <2>; 1055 ranges; 1056 iommus = <&apps_smmu 0x4c3 0x0>; 1057 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>; 1058 interconnect-names = "qup-core"; 1059 status = "disabled"; 1060 1061 i2c6: i2c@a80000 { 1062 compatible = "qcom,geni-i2c"; 1063 reg = <0 0x00a80000 0 0x4000>; 1064 clock-names = "se"; 1065 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1066 pinctrl-names = "default"; 1067 pinctrl-0 = <&qup_i2c6_default>; 1068 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1072 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1073 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1074 interconnect-names = "qup-core", "qup-config", 1075 "qup-memory"; 1076 status = "disabled"; 1077 }; 1078 1079 spi6: spi@a80000 { 1080 compatible = "qcom,geni-spi"; 1081 reg = <0 0x00a80000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&qup_spi6_default>; 1086 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 power-domains = <&rpmhpd SC7180_CX>; 1090 operating-points-v2 = <&qup_opp_table>; 1091 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1092 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1093 interconnect-names = "qup-core", "qup-config"; 1094 status = "disabled"; 1095 }; 1096 1097 uart6: serial@a80000 { 1098 compatible = "qcom,geni-uart"; 1099 reg = <0 0x00a80000 0 0x4000>; 1100 clock-names = "se"; 1101 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1102 pinctrl-names = "default"; 1103 pinctrl-0 = <&qup_uart6_default>; 1104 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1105 power-domains = <&rpmhpd SC7180_CX>; 1106 operating-points-v2 = <&qup_opp_table>; 1107 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1108 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1109 interconnect-names = "qup-core", "qup-config"; 1110 status = "disabled"; 1111 }; 1112 1113 i2c7: i2c@a84000 { 1114 compatible = "qcom,geni-i2c"; 1115 reg = <0 0x00a84000 0 0x4000>; 1116 clock-names = "se"; 1117 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_i2c7_default>; 1120 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1124 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1125 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1126 interconnect-names = "qup-core", "qup-config", 1127 "qup-memory"; 1128 status = "disabled"; 1129 }; 1130 1131 uart7: serial@a84000 { 1132 compatible = "qcom,geni-uart"; 1133 reg = <0 0x00a84000 0 0x4000>; 1134 clock-names = "se"; 1135 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1136 pinctrl-names = "default"; 1137 pinctrl-0 = <&qup_uart7_default>; 1138 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1139 power-domains = <&rpmhpd SC7180_CX>; 1140 operating-points-v2 = <&qup_opp_table>; 1141 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1142 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1143 interconnect-names = "qup-core", "qup-config"; 1144 status = "disabled"; 1145 }; 1146 1147 i2c8: i2c@a88000 { 1148 compatible = "qcom,geni-i2c"; 1149 reg = <0 0x00a88000 0 0x4000>; 1150 clock-names = "se"; 1151 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&qup_i2c8_default>; 1154 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1155 #address-cells = <1>; 1156 #size-cells = <0>; 1157 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1158 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1159 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1160 interconnect-names = "qup-core", "qup-config", 1161 "qup-memory"; 1162 status = "disabled"; 1163 }; 1164 1165 spi8: spi@a88000 { 1166 compatible = "qcom,geni-spi"; 1167 reg = <0 0x00a88000 0 0x4000>; 1168 clock-names = "se"; 1169 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1170 pinctrl-names = "default"; 1171 pinctrl-0 = <&qup_spi8_default>; 1172 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 power-domains = <&rpmhpd SC7180_CX>; 1176 operating-points-v2 = <&qup_opp_table>; 1177 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1178 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1179 interconnect-names = "qup-core", "qup-config"; 1180 status = "disabled"; 1181 }; 1182 1183 uart8: serial@a88000 { 1184 compatible = "qcom,geni-debug-uart"; 1185 reg = <0 0x00a88000 0 0x4000>; 1186 clock-names = "se"; 1187 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1188 pinctrl-names = "default"; 1189 pinctrl-0 = <&qup_uart8_default>; 1190 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1191 power-domains = <&rpmhpd SC7180_CX>; 1192 operating-points-v2 = <&qup_opp_table>; 1193 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1194 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1195 interconnect-names = "qup-core", "qup-config"; 1196 status = "disabled"; 1197 }; 1198 1199 i2c9: i2c@a8c000 { 1200 compatible = "qcom,geni-i2c"; 1201 reg = <0 0x00a8c000 0 0x4000>; 1202 clock-names = "se"; 1203 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1204 pinctrl-names = "default"; 1205 pinctrl-0 = <&qup_i2c9_default>; 1206 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1210 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1211 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1212 interconnect-names = "qup-core", "qup-config", 1213 "qup-memory"; 1214 status = "disabled"; 1215 }; 1216 1217 uart9: serial@a8c000 { 1218 compatible = "qcom,geni-uart"; 1219 reg = <0 0x00a8c000 0 0x4000>; 1220 clock-names = "se"; 1221 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&qup_uart9_default>; 1224 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1225 power-domains = <&rpmhpd SC7180_CX>; 1226 operating-points-v2 = <&qup_opp_table>; 1227 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1228 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1229 interconnect-names = "qup-core", "qup-config"; 1230 status = "disabled"; 1231 }; 1232 1233 i2c10: i2c@a90000 { 1234 compatible = "qcom,geni-i2c"; 1235 reg = <0 0x00a90000 0 0x4000>; 1236 clock-names = "se"; 1237 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&qup_i2c10_default>; 1240 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1244 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1245 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1246 interconnect-names = "qup-core", "qup-config", 1247 "qup-memory"; 1248 status = "disabled"; 1249 }; 1250 1251 spi10: spi@a90000 { 1252 compatible = "qcom,geni-spi"; 1253 reg = <0 0x00a90000 0 0x4000>; 1254 clock-names = "se"; 1255 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&qup_spi10_default>; 1258 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 power-domains = <&rpmhpd SC7180_CX>; 1262 operating-points-v2 = <&qup_opp_table>; 1263 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1264 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1265 interconnect-names = "qup-core", "qup-config"; 1266 status = "disabled"; 1267 }; 1268 1269 uart10: serial@a90000 { 1270 compatible = "qcom,geni-uart"; 1271 reg = <0 0x00a90000 0 0x4000>; 1272 clock-names = "se"; 1273 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1274 pinctrl-names = "default"; 1275 pinctrl-0 = <&qup_uart10_default>; 1276 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1277 power-domains = <&rpmhpd SC7180_CX>; 1278 operating-points-v2 = <&qup_opp_table>; 1279 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1280 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1281 interconnect-names = "qup-core", "qup-config"; 1282 status = "disabled"; 1283 }; 1284 1285 i2c11: i2c@a94000 { 1286 compatible = "qcom,geni-i2c"; 1287 reg = <0 0x00a94000 0 0x4000>; 1288 clock-names = "se"; 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_i2c11_default>; 1292 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1296 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1297 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1298 interconnect-names = "qup-core", "qup-config", 1299 "qup-memory"; 1300 status = "disabled"; 1301 }; 1302 1303 spi11: spi@a94000 { 1304 compatible = "qcom,geni-spi"; 1305 reg = <0 0x00a94000 0 0x4000>; 1306 clock-names = "se"; 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_spi11_default>; 1310 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 power-domains = <&rpmhpd SC7180_CX>; 1314 operating-points-v2 = <&qup_opp_table>; 1315 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1316 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1317 interconnect-names = "qup-core", "qup-config"; 1318 status = "disabled"; 1319 }; 1320 1321 uart11: serial@a94000 { 1322 compatible = "qcom,geni-uart"; 1323 reg = <0 0x00a94000 0 0x4000>; 1324 clock-names = "se"; 1325 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1326 pinctrl-names = "default"; 1327 pinctrl-0 = <&qup_uart11_default>; 1328 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1329 power-domains = <&rpmhpd SC7180_CX>; 1330 operating-points-v2 = <&qup_opp_table>; 1331 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1332 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1333 interconnect-names = "qup-core", "qup-config"; 1334 status = "disabled"; 1335 }; 1336 }; 1337 1338 config_noc: interconnect@1500000 { 1339 compatible = "qcom,sc7180-config-noc"; 1340 reg = <0 0x01500000 0 0x28000>; 1341 #interconnect-cells = <2>; 1342 qcom,bcm-voters = <&apps_bcm_voter>; 1343 }; 1344 1345 system_noc: interconnect@1620000 { 1346 compatible = "qcom,sc7180-system-noc"; 1347 reg = <0 0x01620000 0 0x17080>; 1348 #interconnect-cells = <2>; 1349 qcom,bcm-voters = <&apps_bcm_voter>; 1350 }; 1351 1352 mc_virt: interconnect@1638000 { 1353 compatible = "qcom,sc7180-mc-virt"; 1354 reg = <0 0x01638000 0 0x1000>; 1355 #interconnect-cells = <2>; 1356 qcom,bcm-voters = <&apps_bcm_voter>; 1357 }; 1358 1359 qup_virt: interconnect@1650000 { 1360 compatible = "qcom,sc7180-qup-virt"; 1361 reg = <0 0x01650000 0 0x1000>; 1362 #interconnect-cells = <2>; 1363 qcom,bcm-voters = <&apps_bcm_voter>; 1364 }; 1365 1366 aggre1_noc: interconnect@16e0000 { 1367 compatible = "qcom,sc7180-aggre1-noc"; 1368 reg = <0 0x016e0000 0 0x15080>; 1369 #interconnect-cells = <2>; 1370 qcom,bcm-voters = <&apps_bcm_voter>; 1371 }; 1372 1373 aggre2_noc: interconnect@1705000 { 1374 compatible = "qcom,sc7180-aggre2-noc"; 1375 reg = <0 0x01705000 0 0x9000>; 1376 #interconnect-cells = <2>; 1377 qcom,bcm-voters = <&apps_bcm_voter>; 1378 }; 1379 1380 compute_noc: interconnect@170e000 { 1381 compatible = "qcom,sc7180-compute-noc"; 1382 reg = <0 0x0170e000 0 0x6000>; 1383 #interconnect-cells = <2>; 1384 qcom,bcm-voters = <&apps_bcm_voter>; 1385 }; 1386 1387 mmss_noc: interconnect@1740000 { 1388 compatible = "qcom,sc7180-mmss-noc"; 1389 reg = <0 0x01740000 0 0x1c100>; 1390 #interconnect-cells = <2>; 1391 qcom,bcm-voters = <&apps_bcm_voter>; 1392 }; 1393 1394 ipa_virt: interconnect@1e00000 { 1395 compatible = "qcom,sc7180-ipa-virt"; 1396 reg = <0 0x01e00000 0 0x1000>; 1397 #interconnect-cells = <2>; 1398 qcom,bcm-voters = <&apps_bcm_voter>; 1399 }; 1400 1401 ipa: ipa@1e40000 { 1402 compatible = "qcom,sc7180-ipa"; 1403 1404 iommus = <&apps_smmu 0x440 0x0>, 1405 <&apps_smmu 0x442 0x0>; 1406 reg = <0 0x1e40000 0 0x7000>, 1407 <0 0x1e47000 0 0x2000>, 1408 <0 0x1e04000 0 0x2c000>; 1409 reg-names = "ipa-reg", 1410 "ipa-shared", 1411 "gsi"; 1412 1413 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1414 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1415 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1416 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1417 interrupt-names = "ipa", 1418 "gsi", 1419 "ipa-clock-query", 1420 "ipa-setup-ready"; 1421 1422 clocks = <&rpmhcc RPMH_IPA_CLK>; 1423 clock-names = "core"; 1424 1425 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1426 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1427 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1428 interconnect-names = "memory", 1429 "imem", 1430 "config"; 1431 1432 qcom,smem-states = <&ipa_smp2p_out 0>, 1433 <&ipa_smp2p_out 1>; 1434 qcom,smem-state-names = "ipa-clock-enabled-valid", 1435 "ipa-clock-enabled"; 1436 1437 modem-remoteproc = <&remoteproc_mpss>; 1438 1439 status = "disabled"; 1440 }; 1441 1442 tcsr_mutex_regs: syscon@1f40000 { 1443 compatible = "syscon"; 1444 reg = <0 0x01f40000 0 0x40000>; 1445 }; 1446 1447 tcsr_regs: syscon@1fc0000 { 1448 compatible = "syscon"; 1449 reg = <0 0x01fc0000 0 0x40000>; 1450 }; 1451 1452 tlmm: pinctrl@3500000 { 1453 compatible = "qcom,sc7180-pinctrl"; 1454 reg = <0 0x03500000 0 0x300000>, 1455 <0 0x03900000 0 0x300000>, 1456 <0 0x03d00000 0 0x300000>; 1457 reg-names = "west", "north", "south"; 1458 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1459 gpio-controller; 1460 #gpio-cells = <2>; 1461 interrupt-controller; 1462 #interrupt-cells = <2>; 1463 gpio-ranges = <&tlmm 0 0 120>; 1464 wakeup-parent = <&pdc>; 1465 1466 dp_hot_plug_det: dp-hot-plug-det { 1467 pinmux { 1468 pins = "gpio117"; 1469 function = "dp_hot"; 1470 }; 1471 1472 pinconf { 1473 pins = "gpio117"; 1474 bias-disable; 1475 input-enable; 1476 }; 1477 }; 1478 1479 qspi_clk: qspi-clk { 1480 pinmux { 1481 pins = "gpio63"; 1482 function = "qspi_clk"; 1483 }; 1484 }; 1485 1486 qspi_cs0: qspi-cs0 { 1487 pinmux { 1488 pins = "gpio68"; 1489 function = "qspi_cs"; 1490 }; 1491 }; 1492 1493 qspi_cs1: qspi-cs1 { 1494 pinmux { 1495 pins = "gpio72"; 1496 function = "qspi_cs"; 1497 }; 1498 }; 1499 1500 qspi_data01: qspi-data01 { 1501 pinmux-data { 1502 pins = "gpio64", "gpio65"; 1503 function = "qspi_data"; 1504 }; 1505 }; 1506 1507 qspi_data12: qspi-data12 { 1508 pinmux-data { 1509 pins = "gpio66", "gpio67"; 1510 function = "qspi_data"; 1511 }; 1512 }; 1513 1514 qup_i2c0_default: qup-i2c0-default { 1515 pinmux { 1516 pins = "gpio34", "gpio35"; 1517 function = "qup00"; 1518 }; 1519 }; 1520 1521 qup_i2c1_default: qup-i2c1-default { 1522 pinmux { 1523 pins = "gpio0", "gpio1"; 1524 function = "qup01"; 1525 }; 1526 }; 1527 1528 qup_i2c2_default: qup-i2c2-default { 1529 pinmux { 1530 pins = "gpio15", "gpio16"; 1531 function = "qup02_i2c"; 1532 }; 1533 }; 1534 1535 qup_i2c3_default: qup-i2c3-default { 1536 pinmux { 1537 pins = "gpio38", "gpio39"; 1538 function = "qup03"; 1539 }; 1540 }; 1541 1542 qup_i2c4_default: qup-i2c4-default { 1543 pinmux { 1544 pins = "gpio115", "gpio116"; 1545 function = "qup04_i2c"; 1546 }; 1547 }; 1548 1549 qup_i2c5_default: qup-i2c5-default { 1550 pinmux { 1551 pins = "gpio25", "gpio26"; 1552 function = "qup05"; 1553 }; 1554 }; 1555 1556 qup_i2c6_default: qup-i2c6-default { 1557 pinmux { 1558 pins = "gpio59", "gpio60"; 1559 function = "qup10"; 1560 }; 1561 }; 1562 1563 qup_i2c7_default: qup-i2c7-default { 1564 pinmux { 1565 pins = "gpio6", "gpio7"; 1566 function = "qup11_i2c"; 1567 }; 1568 }; 1569 1570 qup_i2c8_default: qup-i2c8-default { 1571 pinmux { 1572 pins = "gpio42", "gpio43"; 1573 function = "qup12"; 1574 }; 1575 }; 1576 1577 qup_i2c9_default: qup-i2c9-default { 1578 pinmux { 1579 pins = "gpio46", "gpio47"; 1580 function = "qup13_i2c"; 1581 }; 1582 }; 1583 1584 qup_i2c10_default: qup-i2c10-default { 1585 pinmux { 1586 pins = "gpio86", "gpio87"; 1587 function = "qup14"; 1588 }; 1589 }; 1590 1591 qup_i2c11_default: qup-i2c11-default { 1592 pinmux { 1593 pins = "gpio53", "gpio54"; 1594 function = "qup15"; 1595 }; 1596 }; 1597 1598 qup_spi0_default: qup-spi0-default { 1599 pinmux { 1600 pins = "gpio34", "gpio35", 1601 "gpio36", "gpio37"; 1602 function = "qup00"; 1603 }; 1604 }; 1605 1606 qup_spi0_cs_gpio: qup-spi0-cs-gpio { 1607 pinmux { 1608 pins = "gpio34", "gpio35", 1609 "gpio36"; 1610 function = "qup00"; 1611 }; 1612 1613 pinmux-cs { 1614 pins = "gpio37"; 1615 function = "gpio"; 1616 }; 1617 }; 1618 1619 qup_spi1_default: qup-spi1-default { 1620 pinmux { 1621 pins = "gpio0", "gpio1", 1622 "gpio2", "gpio3"; 1623 function = "qup01"; 1624 }; 1625 }; 1626 1627 qup_spi1_cs_gpio: qup-spi1-cs-gpio { 1628 pinmux { 1629 pins = "gpio0", "gpio1", 1630 "gpio2"; 1631 function = "qup01"; 1632 }; 1633 1634 pinmux-cs { 1635 pins = "gpio3"; 1636 function = "gpio"; 1637 }; 1638 }; 1639 1640 qup_spi3_default: qup-spi3-default { 1641 pinmux { 1642 pins = "gpio38", "gpio39", 1643 "gpio40", "gpio41"; 1644 function = "qup03"; 1645 }; 1646 }; 1647 1648 qup_spi3_cs_gpio: qup-spi3-cs-gpio { 1649 pinmux { 1650 pins = "gpio38", "gpio39", 1651 "gpio40"; 1652 function = "qup03"; 1653 }; 1654 1655 pinmux-cs { 1656 pins = "gpio41"; 1657 function = "gpio"; 1658 }; 1659 }; 1660 1661 qup_spi5_default: qup-spi5-default { 1662 pinmux { 1663 pins = "gpio25", "gpio26", 1664 "gpio27", "gpio28"; 1665 function = "qup05"; 1666 }; 1667 }; 1668 1669 qup_spi5_cs_gpio: qup-spi5-cs-gpio { 1670 pinmux { 1671 pins = "gpio25", "gpio26", 1672 "gpio27"; 1673 function = "qup05"; 1674 }; 1675 1676 pinmux-cs { 1677 pins = "gpio28"; 1678 function = "gpio"; 1679 }; 1680 }; 1681 1682 qup_spi6_default: qup-spi6-default { 1683 pinmux { 1684 pins = "gpio59", "gpio60", 1685 "gpio61", "gpio62"; 1686 function = "qup10"; 1687 }; 1688 }; 1689 1690 qup_spi6_cs_gpio: qup-spi6-cs-gpio { 1691 pinmux { 1692 pins = "gpio59", "gpio60", 1693 "gpio61"; 1694 function = "qup10"; 1695 }; 1696 1697 pinmux-cs { 1698 pins = "gpio62"; 1699 function = "gpio"; 1700 }; 1701 }; 1702 1703 qup_spi8_default: qup-spi8-default { 1704 pinmux { 1705 pins = "gpio42", "gpio43", 1706 "gpio44", "gpio45"; 1707 function = "qup12"; 1708 }; 1709 }; 1710 1711 qup_spi8_cs_gpio: qup-spi8-cs-gpio { 1712 pinmux { 1713 pins = "gpio42", "gpio43", 1714 "gpio44"; 1715 function = "qup12"; 1716 }; 1717 1718 pinmux-cs { 1719 pins = "gpio45"; 1720 function = "gpio"; 1721 }; 1722 }; 1723 1724 qup_spi10_default: qup-spi10-default { 1725 pinmux { 1726 pins = "gpio86", "gpio87", 1727 "gpio88", "gpio89"; 1728 function = "qup14"; 1729 }; 1730 }; 1731 1732 qup_spi10_cs_gpio: qup-spi10-cs-gpio { 1733 pinmux { 1734 pins = "gpio86", "gpio87", 1735 "gpio88"; 1736 function = "qup14"; 1737 }; 1738 1739 pinmux-cs { 1740 pins = "gpio89"; 1741 function = "gpio"; 1742 }; 1743 }; 1744 1745 qup_spi11_default: qup-spi11-default { 1746 pinmux { 1747 pins = "gpio53", "gpio54", 1748 "gpio55", "gpio56"; 1749 function = "qup15"; 1750 }; 1751 }; 1752 1753 qup_spi11_cs_gpio: qup-spi11-cs-gpio { 1754 pinmux { 1755 pins = "gpio53", "gpio54", 1756 "gpio55"; 1757 function = "qup15"; 1758 }; 1759 1760 pinmux-cs { 1761 pins = "gpio56"; 1762 function = "gpio"; 1763 }; 1764 }; 1765 1766 qup_uart0_default: qup-uart0-default { 1767 pinmux { 1768 pins = "gpio34", "gpio35", 1769 "gpio36", "gpio37"; 1770 function = "qup00"; 1771 }; 1772 }; 1773 1774 qup_uart1_default: qup-uart1-default { 1775 pinmux { 1776 pins = "gpio0", "gpio1", 1777 "gpio2", "gpio3"; 1778 function = "qup01"; 1779 }; 1780 }; 1781 1782 qup_uart2_default: qup-uart2-default { 1783 pinmux { 1784 pins = "gpio15", "gpio16"; 1785 function = "qup02_uart"; 1786 }; 1787 }; 1788 1789 qup_uart3_default: qup-uart3-default { 1790 pinmux { 1791 pins = "gpio38", "gpio39", 1792 "gpio40", "gpio41"; 1793 function = "qup03"; 1794 }; 1795 }; 1796 1797 qup_uart4_default: qup-uart4-default { 1798 pinmux { 1799 pins = "gpio115", "gpio116"; 1800 function = "qup04_uart"; 1801 }; 1802 }; 1803 1804 qup_uart5_default: qup-uart5-default { 1805 pinmux { 1806 pins = "gpio25", "gpio26", 1807 "gpio27", "gpio28"; 1808 function = "qup05"; 1809 }; 1810 }; 1811 1812 qup_uart6_default: qup-uart6-default { 1813 pinmux { 1814 pins = "gpio59", "gpio60", 1815 "gpio61", "gpio62"; 1816 function = "qup10"; 1817 }; 1818 }; 1819 1820 qup_uart7_default: qup-uart7-default { 1821 pinmux { 1822 pins = "gpio6", "gpio7"; 1823 function = "qup11_uart"; 1824 }; 1825 }; 1826 1827 qup_uart8_default: qup-uart8-default { 1828 pinmux { 1829 pins = "gpio44", "gpio45"; 1830 function = "qup12"; 1831 }; 1832 }; 1833 1834 qup_uart9_default: qup-uart9-default { 1835 pinmux { 1836 pins = "gpio46", "gpio47"; 1837 function = "qup13_uart"; 1838 }; 1839 }; 1840 1841 qup_uart10_default: qup-uart10-default { 1842 pinmux { 1843 pins = "gpio86", "gpio87", 1844 "gpio88", "gpio89"; 1845 function = "qup14"; 1846 }; 1847 }; 1848 1849 qup_uart11_default: qup-uart11-default { 1850 pinmux { 1851 pins = "gpio53", "gpio54", 1852 "gpio55", "gpio56"; 1853 function = "qup15"; 1854 }; 1855 }; 1856 1857 sec_mi2s_active: sec-mi2s-active { 1858 pinmux { 1859 pins = "gpio49", "gpio50", "gpio51"; 1860 function = "mi2s_1"; 1861 }; 1862 1863 pinconf { 1864 pins = "gpio49", "gpio50", "gpio51"; 1865 drive-strength = <8>; 1866 bias-pull-up; 1867 }; 1868 }; 1869 1870 pri_mi2s_active: pri-mi2s-active { 1871 pinmux { 1872 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1873 function = "mi2s_0"; 1874 }; 1875 1876 pinconf { 1877 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1878 drive-strength = <8>; 1879 bias-pull-up; 1880 }; 1881 }; 1882 1883 pri_mi2s_mclk_active: pri-mi2s-mclk-active { 1884 pinmux { 1885 pins = "gpio57"; 1886 function = "lpass_ext"; 1887 }; 1888 1889 pinconf { 1890 pins = "gpio57"; 1891 drive-strength = <8>; 1892 bias-pull-up; 1893 }; 1894 }; 1895 1896 sdc1_on: sdc1-on { 1897 pinconf-clk { 1898 pins = "sdc1_clk"; 1899 bias-disable; 1900 drive-strength = <16>; 1901 }; 1902 1903 pinconf-cmd { 1904 pins = "sdc1_cmd"; 1905 bias-pull-up; 1906 drive-strength = <10>; 1907 }; 1908 1909 pinconf-data { 1910 pins = "sdc1_data"; 1911 bias-pull-up; 1912 drive-strength = <10>; 1913 }; 1914 1915 pinconf-rclk { 1916 pins = "sdc1_rclk"; 1917 bias-pull-down; 1918 }; 1919 }; 1920 1921 sdc1_off: sdc1-off { 1922 pinconf-clk { 1923 pins = "sdc1_clk"; 1924 bias-disable; 1925 drive-strength = <2>; 1926 }; 1927 1928 pinconf-cmd { 1929 pins = "sdc1_cmd"; 1930 bias-pull-up; 1931 drive-strength = <2>; 1932 }; 1933 1934 pinconf-data { 1935 pins = "sdc1_data"; 1936 bias-pull-up; 1937 drive-strength = <2>; 1938 }; 1939 1940 pinconf-rclk { 1941 pins = "sdc1_rclk"; 1942 bias-pull-down; 1943 }; 1944 }; 1945 1946 sdc2_on: sdc2-on { 1947 pinconf-clk { 1948 pins = "sdc2_clk"; 1949 bias-disable; 1950 drive-strength = <16>; 1951 }; 1952 1953 pinconf-cmd { 1954 pins = "sdc2_cmd"; 1955 bias-pull-up; 1956 drive-strength = <10>; 1957 }; 1958 1959 pinconf-data { 1960 pins = "sdc2_data"; 1961 bias-pull-up; 1962 drive-strength = <10>; 1963 }; 1964 1965 pinconf-sd-cd { 1966 pins = "gpio69"; 1967 bias-pull-up; 1968 drive-strength = <2>; 1969 }; 1970 }; 1971 1972 sdc2_off: sdc2-off { 1973 pinconf-clk { 1974 pins = "sdc2_clk"; 1975 bias-disable; 1976 drive-strength = <2>; 1977 }; 1978 1979 pinconf-cmd { 1980 pins = "sdc2_cmd"; 1981 bias-pull-up; 1982 drive-strength = <2>; 1983 }; 1984 1985 pinconf-data { 1986 pins = "sdc2_data"; 1987 bias-pull-up; 1988 drive-strength = <2>; 1989 }; 1990 1991 pinconf-sd-cd { 1992 pins = "gpio69"; 1993 bias-disable; 1994 drive-strength = <2>; 1995 }; 1996 }; 1997 }; 1998 1999 remoteproc_mpss: remoteproc@4080000 { 2000 compatible = "qcom,sc7180-mpss-pas"; 2001 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>; 2002 reg-names = "qdsp6", "rmb"; 2003 2004 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2005 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2006 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2007 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2008 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2009 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2010 interrupt-names = "wdog", "fatal", "ready", "handover", 2011 "stop-ack", "shutdown-ack"; 2012 2013 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2014 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 2015 <&gcc GCC_MSS_NAV_AXI_CLK>, 2016 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2017 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 2018 <&rpmhcc RPMH_CXO_CLK>; 2019 clock-names = "iface", "bus", "nav", "snoc_axi", 2020 "mnoc_axi", "xo"; 2021 2022 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, 2023 <&rpmhpd SC7180_CX>, 2024 <&rpmhpd SC7180_MX>, 2025 <&rpmhpd SC7180_MSS>; 2026 power-domain-names = "load_state", "cx", "mx", "mss"; 2027 2028 memory-region = <&mpss_mem>; 2029 2030 qcom,smem-states = <&modem_smp2p_out 0>; 2031 qcom,smem-state-names = "stop"; 2032 2033 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2034 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2035 reset-names = "mss_restart", "pdc_reset"; 2036 2037 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2038 qcom,spare-regs = <&tcsr_regs 0xb3e4>; 2039 2040 status = "disabled"; 2041 2042 glink-edge { 2043 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2044 label = "modem"; 2045 qcom,remote-pid = <1>; 2046 mboxes = <&apss_shared 12>; 2047 }; 2048 }; 2049 2050 gpu: gpu@5000000 { 2051 compatible = "qcom,adreno-618.0", "qcom,adreno"; 2052 #stream-id-cells = <16>; 2053 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 2054 <0 0x05061000 0 0x800>; 2055 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 2056 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2057 iommus = <&adreno_smmu 0>; 2058 operating-points-v2 = <&gpu_opp_table>; 2059 qcom,gmu = <&gmu>; 2060 2061 #cooling-cells = <2>; 2062 2063 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2064 interconnect-names = "gfx-mem"; 2065 2066 gpu_opp_table: opp-table { 2067 compatible = "operating-points-v2"; 2068 2069 opp-800000000 { 2070 opp-hz = /bits/ 64 <800000000>; 2071 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2072 opp-peak-kBps = <8532000>; 2073 }; 2074 2075 opp-650000000 { 2076 opp-hz = /bits/ 64 <650000000>; 2077 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2078 opp-peak-kBps = <7216000>; 2079 }; 2080 2081 opp-565000000 { 2082 opp-hz = /bits/ 64 <565000000>; 2083 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2084 opp-peak-kBps = <5412000>; 2085 }; 2086 2087 opp-430000000 { 2088 opp-hz = /bits/ 64 <430000000>; 2089 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2090 opp-peak-kBps = <5412000>; 2091 }; 2092 2093 opp-355000000 { 2094 opp-hz = /bits/ 64 <355000000>; 2095 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2096 opp-peak-kBps = <3072000>; 2097 }; 2098 2099 opp-267000000 { 2100 opp-hz = /bits/ 64 <267000000>; 2101 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2102 opp-peak-kBps = <3072000>; 2103 }; 2104 2105 opp-180000000 { 2106 opp-hz = /bits/ 64 <180000000>; 2107 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2108 opp-peak-kBps = <1804000>; 2109 }; 2110 }; 2111 }; 2112 2113 adreno_smmu: iommu@5040000 { 2114 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2115 reg = <0 0x05040000 0 0x10000>; 2116 #iommu-cells = <1>; 2117 #global-interrupts = <2>; 2118 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2121 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2122 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2123 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2124 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2125 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2126 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2127 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2128 2129 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2130 <&gcc GCC_GPU_CFG_AHB_CLK>; 2131 clock-names = "bus", "iface"; 2132 2133 power-domains = <&gpucc CX_GDSC>; 2134 }; 2135 2136 gmu: gmu@506a000 { 2137 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2138 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2139 <0 0x0b490000 0 0x10000>; 2140 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2141 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2143 interrupt-names = "hfi", "gmu"; 2144 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2145 <&gpucc GPU_CC_CXO_CLK>, 2146 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2147 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2148 clock-names = "gmu", "cxo", "axi", "memnoc"; 2149 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2150 power-domain-names = "cx", "gx"; 2151 iommus = <&adreno_smmu 5>; 2152 operating-points-v2 = <&gmu_opp_table>; 2153 2154 gmu_opp_table: opp-table { 2155 compatible = "operating-points-v2"; 2156 2157 opp-200000000 { 2158 opp-hz = /bits/ 64 <200000000>; 2159 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2160 }; 2161 }; 2162 }; 2163 2164 gpucc: clock-controller@5090000 { 2165 compatible = "qcom,sc7180-gpucc"; 2166 reg = <0 0x05090000 0 0x9000>; 2167 clocks = <&rpmhcc RPMH_CXO_CLK>, 2168 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2169 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2170 clock-names = "bi_tcxo", 2171 "gcc_gpu_gpll0_clk_src", 2172 "gcc_gpu_gpll0_div_clk_src"; 2173 #clock-cells = <1>; 2174 #reset-cells = <1>; 2175 #power-domain-cells = <1>; 2176 }; 2177 2178 stm@6002000 { 2179 compatible = "arm,coresight-stm", "arm,primecell"; 2180 reg = <0 0x06002000 0 0x1000>, 2181 <0 0x16280000 0 0x180000>; 2182 reg-names = "stm-base", "stm-stimulus-base"; 2183 2184 clocks = <&aoss_qmp>; 2185 clock-names = "apb_pclk"; 2186 2187 out-ports { 2188 port { 2189 stm_out: endpoint { 2190 remote-endpoint = <&funnel0_in7>; 2191 }; 2192 }; 2193 }; 2194 }; 2195 2196 funnel@6041000 { 2197 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2198 reg = <0 0x06041000 0 0x1000>; 2199 2200 clocks = <&aoss_qmp>; 2201 clock-names = "apb_pclk"; 2202 2203 out-ports { 2204 port { 2205 funnel0_out: endpoint { 2206 remote-endpoint = <&merge_funnel_in0>; 2207 }; 2208 }; 2209 }; 2210 2211 in-ports { 2212 #address-cells = <1>; 2213 #size-cells = <0>; 2214 2215 port@7 { 2216 reg = <7>; 2217 funnel0_in7: endpoint { 2218 remote-endpoint = <&stm_out>; 2219 }; 2220 }; 2221 }; 2222 }; 2223 2224 funnel@6042000 { 2225 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2226 reg = <0 0x06042000 0 0x1000>; 2227 2228 clocks = <&aoss_qmp>; 2229 clock-names = "apb_pclk"; 2230 2231 out-ports { 2232 port { 2233 funnel1_out: endpoint { 2234 remote-endpoint = <&merge_funnel_in1>; 2235 }; 2236 }; 2237 }; 2238 2239 in-ports { 2240 #address-cells = <1>; 2241 #size-cells = <0>; 2242 2243 port@4 { 2244 reg = <4>; 2245 funnel1_in4: endpoint { 2246 remote-endpoint = <&apss_merge_funnel_out>; 2247 }; 2248 }; 2249 }; 2250 }; 2251 2252 funnel@6045000 { 2253 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2254 reg = <0 0x06045000 0 0x1000>; 2255 2256 clocks = <&aoss_qmp>; 2257 clock-names = "apb_pclk"; 2258 2259 out-ports { 2260 port { 2261 merge_funnel_out: endpoint { 2262 remote-endpoint = <&swao_funnel_in>; 2263 }; 2264 }; 2265 }; 2266 2267 in-ports { 2268 #address-cells = <1>; 2269 #size-cells = <0>; 2270 2271 port@0 { 2272 reg = <0>; 2273 merge_funnel_in0: endpoint { 2274 remote-endpoint = <&funnel0_out>; 2275 }; 2276 }; 2277 2278 port@1 { 2279 reg = <1>; 2280 merge_funnel_in1: endpoint { 2281 remote-endpoint = <&funnel1_out>; 2282 }; 2283 }; 2284 }; 2285 }; 2286 2287 replicator@6046000 { 2288 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2289 reg = <0 0x06046000 0 0x1000>; 2290 2291 clocks = <&aoss_qmp>; 2292 clock-names = "apb_pclk"; 2293 2294 out-ports { 2295 port { 2296 replicator_out: endpoint { 2297 remote-endpoint = <&etr_in>; 2298 }; 2299 }; 2300 }; 2301 2302 in-ports { 2303 port { 2304 replicator_in: endpoint { 2305 remote-endpoint = <&swao_replicator_out>; 2306 }; 2307 }; 2308 }; 2309 }; 2310 2311 etr@6048000 { 2312 compatible = "arm,coresight-tmc", "arm,primecell"; 2313 reg = <0 0x06048000 0 0x1000>; 2314 iommus = <&apps_smmu 0x04a0 0x20>; 2315 2316 clocks = <&aoss_qmp>; 2317 clock-names = "apb_pclk"; 2318 arm,scatter-gather; 2319 2320 in-ports { 2321 port { 2322 etr_in: endpoint { 2323 remote-endpoint = <&replicator_out>; 2324 }; 2325 }; 2326 }; 2327 }; 2328 2329 funnel@6b04000 { 2330 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2331 reg = <0 0x06b04000 0 0x1000>; 2332 2333 clocks = <&aoss_qmp>; 2334 clock-names = "apb_pclk"; 2335 2336 out-ports { 2337 port { 2338 swao_funnel_out: endpoint { 2339 remote-endpoint = <&etf_in>; 2340 }; 2341 }; 2342 }; 2343 2344 in-ports { 2345 #address-cells = <1>; 2346 #size-cells = <0>; 2347 2348 port@7 { 2349 reg = <7>; 2350 swao_funnel_in: endpoint { 2351 remote-endpoint = <&merge_funnel_out>; 2352 }; 2353 }; 2354 }; 2355 }; 2356 2357 etf@6b05000 { 2358 compatible = "arm,coresight-tmc", "arm,primecell"; 2359 reg = <0 0x06b05000 0 0x1000>; 2360 2361 clocks = <&aoss_qmp>; 2362 clock-names = "apb_pclk"; 2363 2364 out-ports { 2365 port { 2366 etf_out: endpoint { 2367 remote-endpoint = <&swao_replicator_in>; 2368 }; 2369 }; 2370 }; 2371 2372 in-ports { 2373 port { 2374 etf_in: endpoint { 2375 remote-endpoint = <&swao_funnel_out>; 2376 }; 2377 }; 2378 }; 2379 }; 2380 2381 replicator@6b06000 { 2382 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2383 reg = <0 0x06b06000 0 0x1000>; 2384 2385 clocks = <&aoss_qmp>; 2386 clock-names = "apb_pclk"; 2387 qcom,replicator-loses-context; 2388 2389 out-ports { 2390 port { 2391 swao_replicator_out: endpoint { 2392 remote-endpoint = <&replicator_in>; 2393 }; 2394 }; 2395 }; 2396 2397 in-ports { 2398 port { 2399 swao_replicator_in: endpoint { 2400 remote-endpoint = <&etf_out>; 2401 }; 2402 }; 2403 }; 2404 }; 2405 2406 etm@7040000 { 2407 compatible = "arm,coresight-etm4x", "arm,primecell"; 2408 reg = <0 0x07040000 0 0x1000>; 2409 2410 cpu = <&CPU0>; 2411 2412 clocks = <&aoss_qmp>; 2413 clock-names = "apb_pclk"; 2414 arm,coresight-loses-context-with-cpu; 2415 qcom,skip-power-up; 2416 2417 out-ports { 2418 port { 2419 etm0_out: endpoint { 2420 remote-endpoint = <&apss_funnel_in0>; 2421 }; 2422 }; 2423 }; 2424 }; 2425 2426 etm@7140000 { 2427 compatible = "arm,coresight-etm4x", "arm,primecell"; 2428 reg = <0 0x07140000 0 0x1000>; 2429 2430 cpu = <&CPU1>; 2431 2432 clocks = <&aoss_qmp>; 2433 clock-names = "apb_pclk"; 2434 arm,coresight-loses-context-with-cpu; 2435 qcom,skip-power-up; 2436 2437 out-ports { 2438 port { 2439 etm1_out: endpoint { 2440 remote-endpoint = <&apss_funnel_in1>; 2441 }; 2442 }; 2443 }; 2444 }; 2445 2446 etm@7240000 { 2447 compatible = "arm,coresight-etm4x", "arm,primecell"; 2448 reg = <0 0x07240000 0 0x1000>; 2449 2450 cpu = <&CPU2>; 2451 2452 clocks = <&aoss_qmp>; 2453 clock-names = "apb_pclk"; 2454 arm,coresight-loses-context-with-cpu; 2455 qcom,skip-power-up; 2456 2457 out-ports { 2458 port { 2459 etm2_out: endpoint { 2460 remote-endpoint = <&apss_funnel_in2>; 2461 }; 2462 }; 2463 }; 2464 }; 2465 2466 etm@7340000 { 2467 compatible = "arm,coresight-etm4x", "arm,primecell"; 2468 reg = <0 0x07340000 0 0x1000>; 2469 2470 cpu = <&CPU3>; 2471 2472 clocks = <&aoss_qmp>; 2473 clock-names = "apb_pclk"; 2474 arm,coresight-loses-context-with-cpu; 2475 qcom,skip-power-up; 2476 2477 out-ports { 2478 port { 2479 etm3_out: endpoint { 2480 remote-endpoint = <&apss_funnel_in3>; 2481 }; 2482 }; 2483 }; 2484 }; 2485 2486 etm@7440000 { 2487 compatible = "arm,coresight-etm4x", "arm,primecell"; 2488 reg = <0 0x07440000 0 0x1000>; 2489 2490 cpu = <&CPU4>; 2491 2492 clocks = <&aoss_qmp>; 2493 clock-names = "apb_pclk"; 2494 arm,coresight-loses-context-with-cpu; 2495 qcom,skip-power-up; 2496 2497 out-ports { 2498 port { 2499 etm4_out: endpoint { 2500 remote-endpoint = <&apss_funnel_in4>; 2501 }; 2502 }; 2503 }; 2504 }; 2505 2506 etm@7540000 { 2507 compatible = "arm,coresight-etm4x", "arm,primecell"; 2508 reg = <0 0x07540000 0 0x1000>; 2509 2510 cpu = <&CPU5>; 2511 2512 clocks = <&aoss_qmp>; 2513 clock-names = "apb_pclk"; 2514 arm,coresight-loses-context-with-cpu; 2515 qcom,skip-power-up; 2516 2517 out-ports { 2518 port { 2519 etm5_out: endpoint { 2520 remote-endpoint = <&apss_funnel_in5>; 2521 }; 2522 }; 2523 }; 2524 }; 2525 2526 etm@7640000 { 2527 compatible = "arm,coresight-etm4x", "arm,primecell"; 2528 reg = <0 0x07640000 0 0x1000>; 2529 2530 cpu = <&CPU6>; 2531 2532 clocks = <&aoss_qmp>; 2533 clock-names = "apb_pclk"; 2534 arm,coresight-loses-context-with-cpu; 2535 qcom,skip-power-up; 2536 2537 out-ports { 2538 port { 2539 etm6_out: endpoint { 2540 remote-endpoint = <&apss_funnel_in6>; 2541 }; 2542 }; 2543 }; 2544 }; 2545 2546 etm@7740000 { 2547 compatible = "arm,coresight-etm4x", "arm,primecell"; 2548 reg = <0 0x07740000 0 0x1000>; 2549 2550 cpu = <&CPU7>; 2551 2552 clocks = <&aoss_qmp>; 2553 clock-names = "apb_pclk"; 2554 arm,coresight-loses-context-with-cpu; 2555 qcom,skip-power-up; 2556 2557 out-ports { 2558 port { 2559 etm7_out: endpoint { 2560 remote-endpoint = <&apss_funnel_in7>; 2561 }; 2562 }; 2563 }; 2564 }; 2565 2566 funnel@7800000 { /* APSS Funnel */ 2567 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2568 reg = <0 0x07800000 0 0x1000>; 2569 2570 clocks = <&aoss_qmp>; 2571 clock-names = "apb_pclk"; 2572 2573 out-ports { 2574 port { 2575 apss_funnel_out: endpoint { 2576 remote-endpoint = <&apss_merge_funnel_in>; 2577 }; 2578 }; 2579 }; 2580 2581 in-ports { 2582 #address-cells = <1>; 2583 #size-cells = <0>; 2584 2585 port@0 { 2586 reg = <0>; 2587 apss_funnel_in0: endpoint { 2588 remote-endpoint = <&etm0_out>; 2589 }; 2590 }; 2591 2592 port@1 { 2593 reg = <1>; 2594 apss_funnel_in1: endpoint { 2595 remote-endpoint = <&etm1_out>; 2596 }; 2597 }; 2598 2599 port@2 { 2600 reg = <2>; 2601 apss_funnel_in2: endpoint { 2602 remote-endpoint = <&etm2_out>; 2603 }; 2604 }; 2605 2606 port@3 { 2607 reg = <3>; 2608 apss_funnel_in3: endpoint { 2609 remote-endpoint = <&etm3_out>; 2610 }; 2611 }; 2612 2613 port@4 { 2614 reg = <4>; 2615 apss_funnel_in4: endpoint { 2616 remote-endpoint = <&etm4_out>; 2617 }; 2618 }; 2619 2620 port@5 { 2621 reg = <5>; 2622 apss_funnel_in5: endpoint { 2623 remote-endpoint = <&etm5_out>; 2624 }; 2625 }; 2626 2627 port@6 { 2628 reg = <6>; 2629 apss_funnel_in6: endpoint { 2630 remote-endpoint = <&etm6_out>; 2631 }; 2632 }; 2633 2634 port@7 { 2635 reg = <7>; 2636 apss_funnel_in7: endpoint { 2637 remote-endpoint = <&etm7_out>; 2638 }; 2639 }; 2640 }; 2641 }; 2642 2643 funnel@7810000 { 2644 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2645 reg = <0 0x07810000 0 0x1000>; 2646 2647 clocks = <&aoss_qmp>; 2648 clock-names = "apb_pclk"; 2649 2650 out-ports { 2651 port { 2652 apss_merge_funnel_out: endpoint { 2653 remote-endpoint = <&funnel1_in4>; 2654 }; 2655 }; 2656 }; 2657 2658 in-ports { 2659 port { 2660 apss_merge_funnel_in: endpoint { 2661 remote-endpoint = <&apss_funnel_out>; 2662 }; 2663 }; 2664 }; 2665 }; 2666 2667 sdhc_2: sdhci@8804000 { 2668 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2669 reg = <0 0x08804000 0 0x1000>; 2670 2671 iommus = <&apps_smmu 0x80 0>; 2672 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2673 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2674 interrupt-names = "hc_irq", "pwr_irq"; 2675 2676 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 2677 <&gcc GCC_SDCC2_AHB_CLK>; 2678 clock-names = "core", "iface"; 2679 2680 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2681 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2682 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2683 power-domains = <&rpmhpd SC7180_CX>; 2684 operating-points-v2 = <&sdhc2_opp_table>; 2685 2686 bus-width = <4>; 2687 2688 status = "disabled"; 2689 2690 sdhc2_opp_table: sdhc2-opp-table { 2691 compatible = "operating-points-v2"; 2692 2693 opp-100000000 { 2694 opp-hz = /bits/ 64 <100000000>; 2695 required-opps = <&rpmhpd_opp_low_svs>; 2696 opp-peak-kBps = <160000 100000>; 2697 opp-avg-kBps = <80000 50000>; 2698 }; 2699 2700 opp-202000000 { 2701 opp-hz = /bits/ 64 <202000000>; 2702 required-opps = <&rpmhpd_opp_svs_l1>; 2703 opp-peak-kBps = <200000 120000>; 2704 opp-avg-kBps = <100000 60000>; 2705 }; 2706 }; 2707 }; 2708 2709 qspi_opp_table: qspi-opp-table { 2710 compatible = "operating-points-v2"; 2711 2712 opp-75000000 { 2713 opp-hz = /bits/ 64 <75000000>; 2714 required-opps = <&rpmhpd_opp_low_svs>; 2715 }; 2716 2717 opp-150000000 { 2718 opp-hz = /bits/ 64 <150000000>; 2719 required-opps = <&rpmhpd_opp_svs>; 2720 }; 2721 2722 opp-300000000 { 2723 opp-hz = /bits/ 64 <300000000>; 2724 required-opps = <&rpmhpd_opp_nom>; 2725 }; 2726 }; 2727 2728 qspi: spi@88dc000 { 2729 compatible = "qcom,qspi-v1"; 2730 reg = <0 0x088dc000 0 0x600>; 2731 #address-cells = <1>; 2732 #size-cells = <0>; 2733 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2734 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2735 <&gcc GCC_QSPI_CORE_CLK>; 2736 clock-names = "iface", "core"; 2737 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2738 &config_noc SLAVE_QSPI_0 0>; 2739 interconnect-names = "qspi-config"; 2740 power-domains = <&rpmhpd SC7180_CX>; 2741 operating-points-v2 = <&qspi_opp_table>; 2742 status = "disabled"; 2743 }; 2744 2745 usb_1_hsphy: phy@88e3000 { 2746 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2747 reg = <0 0x088e3000 0 0x400>; 2748 status = "disabled"; 2749 #phy-cells = <0>; 2750 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2751 <&rpmhcc RPMH_CXO_CLK>; 2752 clock-names = "cfg_ahb", "ref"; 2753 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2754 2755 nvmem-cells = <&qusb2p_hstx_trim>; 2756 }; 2757 2758 usb_1_qmpphy: phy-wrapper@88e9000 { 2759 compatible = "qcom,sc7180-qmp-usb3-phy"; 2760 reg = <0 0x088e9000 0 0x18c>, 2761 <0 0x088e8000 0 0x38>; 2762 reg-names = "reg-base", "dp_com"; 2763 status = "disabled"; 2764 #clock-cells = <1>; 2765 #address-cells = <2>; 2766 #size-cells = <2>; 2767 ranges; 2768 2769 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2770 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2771 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2772 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2773 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2774 2775 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2776 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2777 reset-names = "phy", "common"; 2778 2779 usb_1_ssphy: phy@88e9200 { 2780 reg = <0 0x088e9200 0 0x128>, 2781 <0 0x088e9400 0 0x200>, 2782 <0 0x088e9c00 0 0x218>, 2783 <0 0x088e9600 0 0x128>, 2784 <0 0x088e9800 0 0x200>, 2785 <0 0x088e9a00 0 0x18>; 2786 #clock-cells = <0>; 2787 #phy-cells = <0>; 2788 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2789 clock-names = "pipe0"; 2790 clock-output-names = "usb3_phy_pipe_clk_src"; 2791 }; 2792 }; 2793 2794 dc_noc: interconnect@9160000 { 2795 compatible = "qcom,sc7180-dc-noc"; 2796 reg = <0 0x09160000 0 0x03200>; 2797 #interconnect-cells = <2>; 2798 qcom,bcm-voters = <&apps_bcm_voter>; 2799 }; 2800 2801 system-cache-controller@9200000 { 2802 compatible = "qcom,sc7180-llcc"; 2803 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 2804 reg-names = "llcc_base", "llcc_broadcast_base"; 2805 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2806 }; 2807 2808 gem_noc: interconnect@9680000 { 2809 compatible = "qcom,sc7180-gem-noc"; 2810 reg = <0 0x09680000 0 0x3e200>; 2811 #interconnect-cells = <2>; 2812 qcom,bcm-voters = <&apps_bcm_voter>; 2813 }; 2814 2815 npu_noc: interconnect@9990000 { 2816 compatible = "qcom,sc7180-npu-noc"; 2817 reg = <0 0x09990000 0 0x1600>; 2818 #interconnect-cells = <2>; 2819 qcom,bcm-voters = <&apps_bcm_voter>; 2820 }; 2821 2822 usb_1: usb@a6f8800 { 2823 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 2824 reg = <0 0x0a6f8800 0 0x400>; 2825 status = "disabled"; 2826 #address-cells = <2>; 2827 #size-cells = <2>; 2828 ranges; 2829 dma-ranges; 2830 2831 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2832 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2833 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2834 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2835 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2836 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2837 "sleep"; 2838 2839 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2840 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2841 assigned-clock-rates = <19200000>, <150000000>; 2842 2843 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2844 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2845 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2846 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 2847 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2848 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2849 2850 power-domains = <&gcc USB30_PRIM_GDSC>; 2851 2852 resets = <&gcc GCC_USB30_PRIM_BCR>; 2853 2854 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 2855 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 2856 interconnect-names = "usb-ddr", "apps-usb"; 2857 2858 usb_1_dwc3: dwc3@a600000 { 2859 compatible = "snps,dwc3"; 2860 reg = <0 0x0a600000 0 0xe000>; 2861 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2862 iommus = <&apps_smmu 0x540 0>; 2863 snps,dis_u2_susphy_quirk; 2864 snps,dis_enblslpm_quirk; 2865 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2866 phy-names = "usb2-phy", "usb3-phy"; 2867 maximum-speed = "super-speed"; 2868 }; 2869 }; 2870 2871 venus: video-codec@aa00000 { 2872 compatible = "qcom,sc7180-venus"; 2873 reg = <0 0x0aa00000 0 0xff000>; 2874 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2875 power-domains = <&videocc VENUS_GDSC>, 2876 <&videocc VCODEC0_GDSC>, 2877 <&rpmhpd SC7180_CX>; 2878 power-domain-names = "venus", "vcodec0", "cx"; 2879 operating-points-v2 = <&venus_opp_table>; 2880 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2881 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2882 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 2883 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2884 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2885 clock-names = "core", "iface", "bus", 2886 "vcodec0_core", "vcodec0_bus"; 2887 iommus = <&apps_smmu 0x0c00 0x60>; 2888 memory-region = <&venus_mem>; 2889 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 2890 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 2891 interconnect-names = "video-mem", "cpu-cfg"; 2892 2893 video-decoder { 2894 compatible = "venus-decoder"; 2895 }; 2896 2897 video-encoder { 2898 compatible = "venus-encoder"; 2899 }; 2900 2901 venus_opp_table: venus-opp-table { 2902 compatible = "operating-points-v2"; 2903 2904 opp-150000000 { 2905 opp-hz = /bits/ 64 <150000000>; 2906 required-opps = <&rpmhpd_opp_low_svs>; 2907 }; 2908 2909 opp-270000000 { 2910 opp-hz = /bits/ 64 <270000000>; 2911 required-opps = <&rpmhpd_opp_svs>; 2912 }; 2913 2914 opp-340000000 { 2915 opp-hz = /bits/ 64 <340000000>; 2916 required-opps = <&rpmhpd_opp_svs_l1>; 2917 }; 2918 2919 opp-434000000 { 2920 opp-hz = /bits/ 64 <434000000>; 2921 required-opps = <&rpmhpd_opp_nom>; 2922 }; 2923 2924 opp-500000097 { 2925 opp-hz = /bits/ 64 <500000097>; 2926 required-opps = <&rpmhpd_opp_turbo>; 2927 }; 2928 }; 2929 }; 2930 2931 videocc: clock-controller@ab00000 { 2932 compatible = "qcom,sc7180-videocc"; 2933 reg = <0 0x0ab00000 0 0x10000>; 2934 clocks = <&rpmhcc RPMH_CXO_CLK>; 2935 clock-names = "bi_tcxo"; 2936 #clock-cells = <1>; 2937 #reset-cells = <1>; 2938 #power-domain-cells = <1>; 2939 }; 2940 2941 camnoc_virt: interconnect@ac00000 { 2942 compatible = "qcom,sc7180-camnoc-virt"; 2943 reg = <0 0x0ac00000 0 0x1000>; 2944 #interconnect-cells = <2>; 2945 qcom,bcm-voters = <&apps_bcm_voter>; 2946 }; 2947 2948 camcc: clock-controller@ad00000 { 2949 compatible = "qcom,sc7180-camcc"; 2950 reg = <0 0x0ad00000 0 0x10000>; 2951 clocks = <&rpmhcc RPMH_CXO_CLK>, 2952 <&gcc GCC_CAMERA_AHB_CLK>, 2953 <&gcc GCC_CAMERA_XO_CLK>; 2954 clock-names = "bi_tcxo", "iface", "xo"; 2955 #clock-cells = <1>; 2956 #reset-cells = <1>; 2957 #power-domain-cells = <1>; 2958 }; 2959 2960 mdss: mdss@ae00000 { 2961 compatible = "qcom,sc7180-mdss"; 2962 reg = <0 0x0ae00000 0 0x1000>; 2963 reg-names = "mdss"; 2964 2965 power-domains = <&dispcc MDSS_GDSC>; 2966 2967 clocks = <&gcc GCC_DISP_AHB_CLK>, 2968 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2969 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2970 clock-names = "iface", "ahb", "core"; 2971 2972 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2973 assigned-clock-rates = <300000000>; 2974 2975 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2976 interrupt-controller; 2977 #interrupt-cells = <1>; 2978 2979 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 2980 interconnect-names = "mdp0-mem"; 2981 2982 iommus = <&apps_smmu 0x800 0x2>; 2983 2984 #address-cells = <2>; 2985 #size-cells = <2>; 2986 ranges; 2987 2988 status = "disabled"; 2989 2990 mdp: mdp@ae01000 { 2991 compatible = "qcom,sc7180-dpu"; 2992 reg = <0 0x0ae01000 0 0x8f000>, 2993 <0 0x0aeb0000 0 0x2008>; 2994 reg-names = "mdp", "vbif"; 2995 2996 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2997 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2998 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2999 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3000 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3001 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3002 clock-names = "bus", "iface", "rot", "lut", "core", 3003 "vsync"; 3004 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 3005 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3006 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3007 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3008 assigned-clock-rates = <300000000>, 3009 <19200000>, 3010 <19200000>, 3011 <19200000>; 3012 operating-points-v2 = <&mdp_opp_table>; 3013 power-domains = <&rpmhpd SC7180_CX>; 3014 3015 interrupt-parent = <&mdss>; 3016 interrupts = <0>; 3017 3018 status = "disabled"; 3019 3020 ports { 3021 #address-cells = <1>; 3022 #size-cells = <0>; 3023 3024 port@0 { 3025 reg = <0>; 3026 dpu_intf1_out: endpoint { 3027 remote-endpoint = <&dsi0_in>; 3028 }; 3029 }; 3030 }; 3031 3032 mdp_opp_table: mdp-opp-table { 3033 compatible = "operating-points-v2"; 3034 3035 opp-200000000 { 3036 opp-hz = /bits/ 64 <200000000>; 3037 required-opps = <&rpmhpd_opp_low_svs>; 3038 }; 3039 3040 opp-300000000 { 3041 opp-hz = /bits/ 64 <300000000>; 3042 required-opps = <&rpmhpd_opp_svs>; 3043 }; 3044 3045 opp-345000000 { 3046 opp-hz = /bits/ 64 <345000000>; 3047 required-opps = <&rpmhpd_opp_svs_l1>; 3048 }; 3049 3050 opp-460000000 { 3051 opp-hz = /bits/ 64 <460000000>; 3052 required-opps = <&rpmhpd_opp_nom>; 3053 }; 3054 }; 3055 3056 }; 3057 3058 dsi0: dsi@ae94000 { 3059 compatible = "qcom,mdss-dsi-ctrl"; 3060 reg = <0 0x0ae94000 0 0x400>; 3061 reg-names = "dsi_ctrl"; 3062 3063 interrupt-parent = <&mdss>; 3064 interrupts = <4>; 3065 3066 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3067 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3068 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3069 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3070 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3071 <&gcc GCC_DISP_HF_AXI_CLK>; 3072 clock-names = "byte", 3073 "byte_intf", 3074 "pixel", 3075 "core", 3076 "iface", 3077 "bus"; 3078 3079 operating-points-v2 = <&dsi_opp_table>; 3080 power-domains = <&rpmhpd SC7180_CX>; 3081 3082 phys = <&dsi_phy>; 3083 phy-names = "dsi"; 3084 3085 #address-cells = <1>; 3086 #size-cells = <0>; 3087 3088 status = "disabled"; 3089 3090 ports { 3091 #address-cells = <1>; 3092 #size-cells = <0>; 3093 3094 port@0 { 3095 reg = <0>; 3096 dsi0_in: endpoint { 3097 remote-endpoint = <&dpu_intf1_out>; 3098 }; 3099 }; 3100 3101 port@1 { 3102 reg = <1>; 3103 dsi0_out: endpoint { 3104 }; 3105 }; 3106 }; 3107 3108 dsi_opp_table: dsi-opp-table { 3109 compatible = "operating-points-v2"; 3110 3111 opp-187500000 { 3112 opp-hz = /bits/ 64 <187500000>; 3113 required-opps = <&rpmhpd_opp_low_svs>; 3114 }; 3115 3116 opp-300000000 { 3117 opp-hz = /bits/ 64 <300000000>; 3118 required-opps = <&rpmhpd_opp_svs>; 3119 }; 3120 3121 opp-358000000 { 3122 opp-hz = /bits/ 64 <358000000>; 3123 required-opps = <&rpmhpd_opp_svs_l1>; 3124 }; 3125 }; 3126 }; 3127 3128 dsi_phy: dsi-phy@ae94400 { 3129 compatible = "qcom,dsi-phy-10nm"; 3130 reg = <0 0x0ae94400 0 0x200>, 3131 <0 0x0ae94600 0 0x280>, 3132 <0 0x0ae94a00 0 0x1e0>; 3133 reg-names = "dsi_phy", 3134 "dsi_phy_lane", 3135 "dsi_pll"; 3136 3137 #clock-cells = <1>; 3138 #phy-cells = <0>; 3139 3140 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3141 <&rpmhcc RPMH_CXO_CLK>; 3142 clock-names = "iface", "ref"; 3143 3144 status = "disabled"; 3145 }; 3146 }; 3147 3148 dispcc: clock-controller@af00000 { 3149 compatible = "qcom,sc7180-dispcc"; 3150 reg = <0 0x0af00000 0 0x200000>; 3151 clocks = <&rpmhcc RPMH_CXO_CLK>, 3152 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3153 <&dsi_phy 0>, 3154 <&dsi_phy 1>, 3155 <0>, 3156 <0>; 3157 clock-names = "bi_tcxo", 3158 "gcc_disp_gpll0_clk_src", 3159 "dsi0_phy_pll_out_byteclk", 3160 "dsi0_phy_pll_out_dsiclk", 3161 "dp_phy_pll_link_clk", 3162 "dp_phy_pll_vco_div_clk"; 3163 #clock-cells = <1>; 3164 #reset-cells = <1>; 3165 #power-domain-cells = <1>; 3166 }; 3167 3168 pdc: interrupt-controller@b220000 { 3169 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3170 reg = <0 0x0b220000 0 0x30000>; 3171 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3172 #interrupt-cells = <2>; 3173 interrupt-parent = <&intc>; 3174 interrupt-controller; 3175 }; 3176 3177 pdc_reset: reset-controller@b2e0000 { 3178 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3179 reg = <0 0x0b2e0000 0 0x20000>; 3180 #reset-cells = <1>; 3181 }; 3182 3183 tsens0: thermal-sensor@c263000 { 3184 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3185 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3186 <0 0x0c222000 0 0x1ff>; /* SROT */ 3187 #qcom,sensors = <15>; 3188 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3190 interrupt-names = "uplow","critical"; 3191 #thermal-sensor-cells = <1>; 3192 }; 3193 3194 tsens1: thermal-sensor@c265000 { 3195 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3196 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3197 <0 0x0c223000 0 0x1ff>; /* SROT */ 3198 #qcom,sensors = <10>; 3199 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3201 interrupt-names = "uplow","critical"; 3202 #thermal-sensor-cells = <1>; 3203 }; 3204 3205 aoss_reset: reset-controller@c2a0000 { 3206 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3207 reg = <0 0x0c2a0000 0 0x31000>; 3208 #reset-cells = <1>; 3209 }; 3210 3211 aoss_qmp: qmp@c300000 { 3212 compatible = "qcom,sc7180-aoss-qmp"; 3213 reg = <0 0x0c300000 0 0x100000>; 3214 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3215 mboxes = <&apss_shared 0>; 3216 3217 #clock-cells = <0>; 3218 #power-domain-cells = <1>; 3219 }; 3220 3221 spmi_bus: spmi@c440000 { 3222 compatible = "qcom,spmi-pmic-arb"; 3223 reg = <0 0x0c440000 0 0x1100>, 3224 <0 0x0c600000 0 0x2000000>, 3225 <0 0x0e600000 0 0x100000>, 3226 <0 0x0e700000 0 0xa0000>, 3227 <0 0x0c40a000 0 0x26000>; 3228 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3229 interrupt-names = "periph_irq"; 3230 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3231 qcom,ee = <0>; 3232 qcom,channel = <0>; 3233 #address-cells = <1>; 3234 #size-cells = <1>; 3235 interrupt-controller; 3236 #interrupt-cells = <4>; 3237 cell-index = <0>; 3238 }; 3239 3240 apps_smmu: iommu@15000000 { 3241 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3242 reg = <0 0x15000000 0 0x100000>; 3243 #iommu-cells = <2>; 3244 #global-interrupts = <1>; 3245 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3326 }; 3327 3328 intc: interrupt-controller@17a00000 { 3329 compatible = "arm,gic-v3"; 3330 #address-cells = <2>; 3331 #size-cells = <2>; 3332 ranges; 3333 #interrupt-cells = <3>; 3334 interrupt-controller; 3335 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3336 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3337 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3338 3339 msi-controller@17a40000 { 3340 compatible = "arm,gic-v3-its"; 3341 msi-controller; 3342 #msi-cells = <1>; 3343 reg = <0 0x17a40000 0 0x20000>; 3344 status = "disabled"; 3345 }; 3346 }; 3347 3348 apss_shared: mailbox@17c00000 { 3349 compatible = "qcom,sc7180-apss-shared"; 3350 reg = <0 0x17c00000 0 0x10000>; 3351 #mbox-cells = <1>; 3352 }; 3353 3354 watchdog@17c10000 { 3355 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3356 reg = <0 0x17c10000 0 0x1000>; 3357 clocks = <&sleep_clk>; 3358 }; 3359 3360 timer@17c20000{ 3361 #address-cells = <2>; 3362 #size-cells = <2>; 3363 ranges; 3364 compatible = "arm,armv7-timer-mem"; 3365 reg = <0 0x17c20000 0 0x1000>; 3366 3367 frame@17c21000 { 3368 frame-number = <0>; 3369 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3371 reg = <0 0x17c21000 0 0x1000>, 3372 <0 0x17c22000 0 0x1000>; 3373 }; 3374 3375 frame@17c23000 { 3376 frame-number = <1>; 3377 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3378 reg = <0 0x17c23000 0 0x1000>; 3379 status = "disabled"; 3380 }; 3381 3382 frame@17c25000 { 3383 frame-number = <2>; 3384 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3385 reg = <0 0x17c25000 0 0x1000>; 3386 status = "disabled"; 3387 }; 3388 3389 frame@17c27000 { 3390 frame-number = <3>; 3391 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3392 reg = <0 0x17c27000 0 0x1000>; 3393 status = "disabled"; 3394 }; 3395 3396 frame@17c29000 { 3397 frame-number = <4>; 3398 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3399 reg = <0 0x17c29000 0 0x1000>; 3400 status = "disabled"; 3401 }; 3402 3403 frame@17c2b000 { 3404 frame-number = <5>; 3405 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3406 reg = <0 0x17c2b000 0 0x1000>; 3407 status = "disabled"; 3408 }; 3409 3410 frame@17c2d000 { 3411 frame-number = <6>; 3412 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3413 reg = <0 0x17c2d000 0 0x1000>; 3414 status = "disabled"; 3415 }; 3416 }; 3417 3418 apps_rsc: rsc@18200000 { 3419 compatible = "qcom,rpmh-rsc"; 3420 reg = <0 0x18200000 0 0x10000>, 3421 <0 0x18210000 0 0x10000>, 3422 <0 0x18220000 0 0x10000>; 3423 reg-names = "drv-0", "drv-1", "drv-2"; 3424 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3425 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3426 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3427 qcom,tcs-offset = <0xd00>; 3428 qcom,drv-id = <2>; 3429 qcom,tcs-config = <ACTIVE_TCS 2>, 3430 <SLEEP_TCS 3>, 3431 <WAKE_TCS 3>, 3432 <CONTROL_TCS 1>; 3433 3434 rpmhcc: clock-controller { 3435 compatible = "qcom,sc7180-rpmh-clk"; 3436 clocks = <&xo_board>; 3437 clock-names = "xo"; 3438 #clock-cells = <1>; 3439 }; 3440 3441 rpmhpd: power-controller { 3442 compatible = "qcom,sc7180-rpmhpd"; 3443 #power-domain-cells = <1>; 3444 operating-points-v2 = <&rpmhpd_opp_table>; 3445 3446 rpmhpd_opp_table: opp-table { 3447 compatible = "operating-points-v2"; 3448 3449 rpmhpd_opp_ret: opp1 { 3450 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3451 }; 3452 3453 rpmhpd_opp_min_svs: opp2 { 3454 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3455 }; 3456 3457 rpmhpd_opp_low_svs: opp3 { 3458 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3459 }; 3460 3461 rpmhpd_opp_svs: opp4 { 3462 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3463 }; 3464 3465 rpmhpd_opp_svs_l1: opp5 { 3466 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3467 }; 3468 3469 rpmhpd_opp_svs_l2: opp6 { 3470 opp-level = <224>; 3471 }; 3472 3473 rpmhpd_opp_nom: opp7 { 3474 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3475 }; 3476 3477 rpmhpd_opp_nom_l1: opp8 { 3478 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3479 }; 3480 3481 rpmhpd_opp_nom_l2: opp9 { 3482 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3483 }; 3484 3485 rpmhpd_opp_turbo: opp10 { 3486 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3487 }; 3488 3489 rpmhpd_opp_turbo_l1: opp11 { 3490 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3491 }; 3492 }; 3493 }; 3494 3495 apps_bcm_voter: bcm_voter { 3496 compatible = "qcom,bcm-voter"; 3497 }; 3498 }; 3499 3500 osm_l3: interconnect@18321000 { 3501 compatible = "qcom,sc7180-osm-l3"; 3502 reg = <0 0x18321000 0 0x1400>; 3503 3504 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3505 clock-names = "xo", "alternate"; 3506 3507 #interconnect-cells = <1>; 3508 }; 3509 3510 cpufreq_hw: cpufreq@18323000 { 3511 compatible = "qcom,cpufreq-hw"; 3512 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3513 reg-names = "freq-domain0", "freq-domain1"; 3514 3515 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3516 clock-names = "xo", "alternate"; 3517 3518 #freq-domain-cells = <1>; 3519 }; 3520 3521 wifi: wifi@18800000 { 3522 compatible = "qcom,wcn3990-wifi"; 3523 reg = <0 0x18800000 0 0x800000>; 3524 reg-names = "membase"; 3525 iommus = <&apps_smmu 0xc0 0x1>; 3526 interrupts = 3527 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3528 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3529 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3530 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3531 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3532 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3533 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3534 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3535 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3536 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3537 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3538 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3539 memory-region = <&wlan_mem>; 3540 qcom,msa-fixed-perm; 3541 status = "disabled"; 3542 }; 3543 3544 lpasscc: clock-controller@62d00000 { 3545 compatible = "qcom,sc7180-lpasscorecc"; 3546 reg = <0 0x62d00000 0 0x50000>, 3547 <0 0x62780000 0 0x30000>; 3548 reg-names = "lpass_core_cc", "lpass_audio_cc"; 3549 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3550 <&rpmhcc RPMH_CXO_CLK>; 3551 clock-names = "iface", "bi_tcxo"; 3552 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3553 #clock-cells = <1>; 3554 #power-domain-cells = <1>; 3555 }; 3556 3557 lpass_cpu: lpass@62f00000 { 3558 compatible = "qcom,sc7180-lpass-cpu"; 3559 3560 reg = <0 0x62f00000 0 0x29000>; 3561 reg-names = "lpass-lpaif"; 3562 3563 iommus = <&apps_smmu 0x1020 0>; 3564 3565 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 3566 3567 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3568 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 3569 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 3570 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 3571 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 3572 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 3573 3574 clock-names = "pcnoc-sway-clk", "audio-core", 3575 "mclk0", "pcnoc-mport-clk", 3576 "mi2s-bit-clk0", "mi2s-bit-clk1"; 3577 3578 3579 #sound-dai-cells = <1>; 3580 #address-cells = <1>; 3581 #size-cells = <0>; 3582 3583 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 3584 interrupt-names = "lpass-irq-lpaif"; 3585 }; 3586 3587 lpass_hm: clock-controller@63000000 { 3588 compatible = "qcom,sc7180-lpasshm"; 3589 reg = <0 0x63000000 0 0x28>; 3590 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 3591 <&rpmhcc RPMH_CXO_CLK>; 3592 clock-names = "iface", "bi_tcxo"; 3593 #clock-cells = <1>; 3594 #power-domain-cells = <1>; 3595 }; 3596 }; 3597 3598 thermal-zones { 3599 cpu0-thermal { 3600 polling-delay-passive = <250>; 3601 polling-delay = <0>; 3602 3603 thermal-sensors = <&tsens0 1>; 3604 sustainable-power = <768>; 3605 3606 trips { 3607 cpu0_alert0: trip-point0 { 3608 temperature = <90000>; 3609 hysteresis = <2000>; 3610 type = "passive"; 3611 }; 3612 3613 cpu0_alert1: trip-point1 { 3614 temperature = <95000>; 3615 hysteresis = <2000>; 3616 type = "passive"; 3617 }; 3618 3619 cpu0_crit: cpu_crit { 3620 temperature = <110000>; 3621 hysteresis = <1000>; 3622 type = "critical"; 3623 }; 3624 }; 3625 3626 cooling-maps { 3627 map0 { 3628 trip = <&cpu0_alert0>; 3629 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3630 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3631 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3632 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3633 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3634 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3635 }; 3636 map1 { 3637 trip = <&cpu0_alert1>; 3638 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3639 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3640 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3641 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3642 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3643 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3644 }; 3645 }; 3646 }; 3647 3648 cpu1-thermal { 3649 polling-delay-passive = <250>; 3650 polling-delay = <0>; 3651 3652 thermal-sensors = <&tsens0 2>; 3653 sustainable-power = <768>; 3654 3655 trips { 3656 cpu1_alert0: trip-point0 { 3657 temperature = <90000>; 3658 hysteresis = <2000>; 3659 type = "passive"; 3660 }; 3661 3662 cpu1_alert1: trip-point1 { 3663 temperature = <95000>; 3664 hysteresis = <2000>; 3665 type = "passive"; 3666 }; 3667 3668 cpu1_crit: cpu_crit { 3669 temperature = <110000>; 3670 hysteresis = <1000>; 3671 type = "critical"; 3672 }; 3673 }; 3674 3675 cooling-maps { 3676 map0 { 3677 trip = <&cpu1_alert0>; 3678 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3679 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3680 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3681 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3682 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3683 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3684 }; 3685 map1 { 3686 trip = <&cpu1_alert1>; 3687 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3688 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3689 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3690 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3691 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3692 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3693 }; 3694 }; 3695 }; 3696 3697 cpu2-thermal { 3698 polling-delay-passive = <250>; 3699 polling-delay = <0>; 3700 3701 thermal-sensors = <&tsens0 3>; 3702 sustainable-power = <768>; 3703 3704 trips { 3705 cpu2_alert0: trip-point0 { 3706 temperature = <90000>; 3707 hysteresis = <2000>; 3708 type = "passive"; 3709 }; 3710 3711 cpu2_alert1: trip-point1 { 3712 temperature = <95000>; 3713 hysteresis = <2000>; 3714 type = "passive"; 3715 }; 3716 3717 cpu2_crit: cpu_crit { 3718 temperature = <110000>; 3719 hysteresis = <1000>; 3720 type = "critical"; 3721 }; 3722 }; 3723 3724 cooling-maps { 3725 map0 { 3726 trip = <&cpu2_alert0>; 3727 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3728 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3729 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3730 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3731 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3732 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3733 }; 3734 map1 { 3735 trip = <&cpu2_alert1>; 3736 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3737 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3738 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3739 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3740 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3741 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3742 }; 3743 }; 3744 }; 3745 3746 cpu3-thermal { 3747 polling-delay-passive = <250>; 3748 polling-delay = <0>; 3749 3750 thermal-sensors = <&tsens0 4>; 3751 sustainable-power = <768>; 3752 3753 trips { 3754 cpu3_alert0: trip-point0 { 3755 temperature = <90000>; 3756 hysteresis = <2000>; 3757 type = "passive"; 3758 }; 3759 3760 cpu3_alert1: trip-point1 { 3761 temperature = <95000>; 3762 hysteresis = <2000>; 3763 type = "passive"; 3764 }; 3765 3766 cpu3_crit: cpu_crit { 3767 temperature = <110000>; 3768 hysteresis = <1000>; 3769 type = "critical"; 3770 }; 3771 }; 3772 3773 cooling-maps { 3774 map0 { 3775 trip = <&cpu3_alert0>; 3776 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3777 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3778 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3779 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3780 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3781 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3782 }; 3783 map1 { 3784 trip = <&cpu3_alert1>; 3785 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3786 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3787 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3788 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3789 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3790 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3791 }; 3792 }; 3793 }; 3794 3795 cpu4-thermal { 3796 polling-delay-passive = <250>; 3797 polling-delay = <0>; 3798 3799 thermal-sensors = <&tsens0 5>; 3800 sustainable-power = <768>; 3801 3802 trips { 3803 cpu4_alert0: trip-point0 { 3804 temperature = <90000>; 3805 hysteresis = <2000>; 3806 type = "passive"; 3807 }; 3808 3809 cpu4_alert1: trip-point1 { 3810 temperature = <95000>; 3811 hysteresis = <2000>; 3812 type = "passive"; 3813 }; 3814 3815 cpu4_crit: cpu_crit { 3816 temperature = <110000>; 3817 hysteresis = <1000>; 3818 type = "critical"; 3819 }; 3820 }; 3821 3822 cooling-maps { 3823 map0 { 3824 trip = <&cpu4_alert0>; 3825 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3826 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3827 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3828 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3829 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3830 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3831 }; 3832 map1 { 3833 trip = <&cpu4_alert1>; 3834 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3835 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3836 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3837 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3838 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3839 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3840 }; 3841 }; 3842 }; 3843 3844 cpu5-thermal { 3845 polling-delay-passive = <250>; 3846 polling-delay = <0>; 3847 3848 thermal-sensors = <&tsens0 6>; 3849 sustainable-power = <768>; 3850 3851 trips { 3852 cpu5_alert0: trip-point0 { 3853 temperature = <90000>; 3854 hysteresis = <2000>; 3855 type = "passive"; 3856 }; 3857 3858 cpu5_alert1: trip-point1 { 3859 temperature = <95000>; 3860 hysteresis = <2000>; 3861 type = "passive"; 3862 }; 3863 3864 cpu5_crit: cpu_crit { 3865 temperature = <110000>; 3866 hysteresis = <1000>; 3867 type = "critical"; 3868 }; 3869 }; 3870 3871 cooling-maps { 3872 map0 { 3873 trip = <&cpu5_alert0>; 3874 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3875 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3876 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3877 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3878 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3879 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3880 }; 3881 map1 { 3882 trip = <&cpu5_alert1>; 3883 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3884 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3885 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3886 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3887 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3888 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3889 }; 3890 }; 3891 }; 3892 3893 cpu6-thermal { 3894 polling-delay-passive = <250>; 3895 polling-delay = <0>; 3896 3897 thermal-sensors = <&tsens0 9>; 3898 sustainable-power = <1202>; 3899 3900 trips { 3901 cpu6_alert0: trip-point0 { 3902 temperature = <90000>; 3903 hysteresis = <2000>; 3904 type = "passive"; 3905 }; 3906 3907 cpu6_alert1: trip-point1 { 3908 temperature = <95000>; 3909 hysteresis = <2000>; 3910 type = "passive"; 3911 }; 3912 3913 cpu6_crit: cpu_crit { 3914 temperature = <110000>; 3915 hysteresis = <1000>; 3916 type = "critical"; 3917 }; 3918 }; 3919 3920 cooling-maps { 3921 map0 { 3922 trip = <&cpu6_alert0>; 3923 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3924 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3925 }; 3926 map1 { 3927 trip = <&cpu6_alert1>; 3928 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3929 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3930 }; 3931 }; 3932 }; 3933 3934 cpu7-thermal { 3935 polling-delay-passive = <250>; 3936 polling-delay = <0>; 3937 3938 thermal-sensors = <&tsens0 10>; 3939 sustainable-power = <1202>; 3940 3941 trips { 3942 cpu7_alert0: trip-point0 { 3943 temperature = <90000>; 3944 hysteresis = <2000>; 3945 type = "passive"; 3946 }; 3947 3948 cpu7_alert1: trip-point1 { 3949 temperature = <95000>; 3950 hysteresis = <2000>; 3951 type = "passive"; 3952 }; 3953 3954 cpu7_crit: cpu_crit { 3955 temperature = <110000>; 3956 hysteresis = <1000>; 3957 type = "critical"; 3958 }; 3959 }; 3960 3961 cooling-maps { 3962 map0 { 3963 trip = <&cpu7_alert0>; 3964 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3965 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3966 }; 3967 map1 { 3968 trip = <&cpu7_alert1>; 3969 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3970 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3971 }; 3972 }; 3973 }; 3974 3975 cpu8-thermal { 3976 polling-delay-passive = <250>; 3977 polling-delay = <0>; 3978 3979 thermal-sensors = <&tsens0 11>; 3980 sustainable-power = <1202>; 3981 3982 trips { 3983 cpu8_alert0: trip-point0 { 3984 temperature = <90000>; 3985 hysteresis = <2000>; 3986 type = "passive"; 3987 }; 3988 3989 cpu8_alert1: trip-point1 { 3990 temperature = <95000>; 3991 hysteresis = <2000>; 3992 type = "passive"; 3993 }; 3994 3995 cpu8_crit: cpu_crit { 3996 temperature = <110000>; 3997 hysteresis = <1000>; 3998 type = "critical"; 3999 }; 4000 }; 4001 4002 cooling-maps { 4003 map0 { 4004 trip = <&cpu8_alert0>; 4005 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4006 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4007 }; 4008 map1 { 4009 trip = <&cpu8_alert1>; 4010 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4011 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4012 }; 4013 }; 4014 }; 4015 4016 cpu9-thermal { 4017 polling-delay-passive = <250>; 4018 polling-delay = <0>; 4019 4020 thermal-sensors = <&tsens0 12>; 4021 sustainable-power = <1202>; 4022 4023 trips { 4024 cpu9_alert0: trip-point0 { 4025 temperature = <90000>; 4026 hysteresis = <2000>; 4027 type = "passive"; 4028 }; 4029 4030 cpu9_alert1: trip-point1 { 4031 temperature = <95000>; 4032 hysteresis = <2000>; 4033 type = "passive"; 4034 }; 4035 4036 cpu9_crit: cpu_crit { 4037 temperature = <110000>; 4038 hysteresis = <1000>; 4039 type = "critical"; 4040 }; 4041 }; 4042 4043 cooling-maps { 4044 map0 { 4045 trip = <&cpu9_alert0>; 4046 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4047 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4048 }; 4049 map1 { 4050 trip = <&cpu9_alert1>; 4051 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4052 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4053 }; 4054 }; 4055 }; 4056 4057 aoss0-thermal { 4058 polling-delay-passive = <250>; 4059 polling-delay = <0>; 4060 4061 thermal-sensors = <&tsens0 0>; 4062 4063 trips { 4064 aoss0_alert0: trip-point0 { 4065 temperature = <90000>; 4066 hysteresis = <2000>; 4067 type = "hot"; 4068 }; 4069 4070 aoss0_crit: aoss0_crit { 4071 temperature = <110000>; 4072 hysteresis = <2000>; 4073 type = "critical"; 4074 }; 4075 }; 4076 }; 4077 4078 cpuss0-thermal { 4079 polling-delay-passive = <250>; 4080 polling-delay = <0>; 4081 4082 thermal-sensors = <&tsens0 7>; 4083 4084 trips { 4085 cpuss0_alert0: trip-point0 { 4086 temperature = <90000>; 4087 hysteresis = <2000>; 4088 type = "hot"; 4089 }; 4090 cpuss0_crit: cluster0_crit { 4091 temperature = <110000>; 4092 hysteresis = <2000>; 4093 type = "critical"; 4094 }; 4095 }; 4096 }; 4097 4098 cpuss1-thermal { 4099 polling-delay-passive = <250>; 4100 polling-delay = <0>; 4101 4102 thermal-sensors = <&tsens0 8>; 4103 4104 trips { 4105 cpuss1_alert0: trip-point0 { 4106 temperature = <90000>; 4107 hysteresis = <2000>; 4108 type = "hot"; 4109 }; 4110 cpuss1_crit: cluster0_crit { 4111 temperature = <110000>; 4112 hysteresis = <2000>; 4113 type = "critical"; 4114 }; 4115 }; 4116 }; 4117 4118 gpuss0-thermal { 4119 polling-delay-passive = <250>; 4120 polling-delay = <0>; 4121 4122 thermal-sensors = <&tsens0 13>; 4123 4124 trips { 4125 gpuss0_alert0: trip-point0 { 4126 temperature = <95000>; 4127 hysteresis = <2000>; 4128 type = "passive"; 4129 }; 4130 4131 gpuss0_crit: gpuss0_crit { 4132 temperature = <110000>; 4133 hysteresis = <2000>; 4134 type = "critical"; 4135 }; 4136 }; 4137 4138 cooling-maps { 4139 map0 { 4140 trip = <&gpuss0_alert0>; 4141 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4142 }; 4143 }; 4144 }; 4145 4146 gpuss1-thermal { 4147 polling-delay-passive = <250>; 4148 polling-delay = <0>; 4149 4150 thermal-sensors = <&tsens0 14>; 4151 4152 trips { 4153 gpuss1_alert0: trip-point0 { 4154 temperature = <95000>; 4155 hysteresis = <2000>; 4156 type = "passive"; 4157 }; 4158 4159 gpuss1_crit: gpuss1_crit { 4160 temperature = <110000>; 4161 hysteresis = <2000>; 4162 type = "critical"; 4163 }; 4164 }; 4165 4166 cooling-maps { 4167 map0 { 4168 trip = <&gpuss1_alert0>; 4169 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4170 }; 4171 }; 4172 }; 4173 4174 aoss1-thermal { 4175 polling-delay-passive = <250>; 4176 polling-delay = <0>; 4177 4178 thermal-sensors = <&tsens1 0>; 4179 4180 trips { 4181 aoss1_alert0: trip-point0 { 4182 temperature = <90000>; 4183 hysteresis = <2000>; 4184 type = "hot"; 4185 }; 4186 4187 aoss1_crit: aoss1_crit { 4188 temperature = <110000>; 4189 hysteresis = <2000>; 4190 type = "critical"; 4191 }; 4192 }; 4193 }; 4194 4195 cwlan-thermal { 4196 polling-delay-passive = <250>; 4197 polling-delay = <0>; 4198 4199 thermal-sensors = <&tsens1 1>; 4200 4201 trips { 4202 cwlan_alert0: trip-point0 { 4203 temperature = <90000>; 4204 hysteresis = <2000>; 4205 type = "hot"; 4206 }; 4207 4208 cwlan_crit: cwlan_crit { 4209 temperature = <110000>; 4210 hysteresis = <2000>; 4211 type = "critical"; 4212 }; 4213 }; 4214 }; 4215 4216 audio-thermal { 4217 polling-delay-passive = <250>; 4218 polling-delay = <0>; 4219 4220 thermal-sensors = <&tsens1 2>; 4221 4222 trips { 4223 audio_alert0: trip-point0 { 4224 temperature = <90000>; 4225 hysteresis = <2000>; 4226 type = "hot"; 4227 }; 4228 4229 audio_crit: audio_crit { 4230 temperature = <110000>; 4231 hysteresis = <2000>; 4232 type = "critical"; 4233 }; 4234 }; 4235 }; 4236 4237 ddr-thermal { 4238 polling-delay-passive = <250>; 4239 polling-delay = <0>; 4240 4241 thermal-sensors = <&tsens1 3>; 4242 4243 trips { 4244 ddr_alert0: trip-point0 { 4245 temperature = <90000>; 4246 hysteresis = <2000>; 4247 type = "hot"; 4248 }; 4249 4250 ddr_crit: ddr_crit { 4251 temperature = <110000>; 4252 hysteresis = <2000>; 4253 type = "critical"; 4254 }; 4255 }; 4256 }; 4257 4258 q6-hvx-thermal { 4259 polling-delay-passive = <250>; 4260 polling-delay = <0>; 4261 4262 thermal-sensors = <&tsens1 4>; 4263 4264 trips { 4265 q6_hvx_alert0: trip-point0 { 4266 temperature = <90000>; 4267 hysteresis = <2000>; 4268 type = "hot"; 4269 }; 4270 4271 q6_hvx_crit: q6_hvx_crit { 4272 temperature = <110000>; 4273 hysteresis = <2000>; 4274 type = "critical"; 4275 }; 4276 }; 4277 }; 4278 4279 camera-thermal { 4280 polling-delay-passive = <250>; 4281 polling-delay = <0>; 4282 4283 thermal-sensors = <&tsens1 5>; 4284 4285 trips { 4286 camera_alert0: trip-point0 { 4287 temperature = <90000>; 4288 hysteresis = <2000>; 4289 type = "hot"; 4290 }; 4291 4292 camera_crit: camera_crit { 4293 temperature = <110000>; 4294 hysteresis = <2000>; 4295 type = "critical"; 4296 }; 4297 }; 4298 }; 4299 4300 mdm-core-thermal { 4301 polling-delay-passive = <250>; 4302 polling-delay = <0>; 4303 4304 thermal-sensors = <&tsens1 6>; 4305 4306 trips { 4307 mdm_alert0: trip-point0 { 4308 temperature = <90000>; 4309 hysteresis = <2000>; 4310 type = "hot"; 4311 }; 4312 4313 mdm_crit: mdm_crit { 4314 temperature = <110000>; 4315 hysteresis = <2000>; 4316 type = "critical"; 4317 }; 4318 }; 4319 }; 4320 4321 mdm-dsp-thermal { 4322 polling-delay-passive = <250>; 4323 polling-delay = <0>; 4324 4325 thermal-sensors = <&tsens1 7>; 4326 4327 trips { 4328 mdm_dsp_alert0: trip-point0 { 4329 temperature = <90000>; 4330 hysteresis = <2000>; 4331 type = "hot"; 4332 }; 4333 4334 mdm_dsp_crit: mdm_dsp_crit { 4335 temperature = <110000>; 4336 hysteresis = <2000>; 4337 type = "critical"; 4338 }; 4339 }; 4340 }; 4341 4342 npu-thermal { 4343 polling-delay-passive = <250>; 4344 polling-delay = <0>; 4345 4346 thermal-sensors = <&tsens1 8>; 4347 4348 trips { 4349 npu_alert0: trip-point0 { 4350 temperature = <90000>; 4351 hysteresis = <2000>; 4352 type = "hot"; 4353 }; 4354 4355 npu_crit: npu_crit { 4356 temperature = <110000>; 4357 hysteresis = <2000>; 4358 type = "critical"; 4359 }; 4360 }; 4361 }; 4362 4363 video-thermal { 4364 polling-delay-passive = <250>; 4365 polling-delay = <0>; 4366 4367 thermal-sensors = <&tsens1 9>; 4368 4369 trips { 4370 video_alert0: trip-point0 { 4371 temperature = <90000>; 4372 hysteresis = <2000>; 4373 type = "hot"; 4374 }; 4375 4376 video_crit: video_crit { 4377 temperature = <110000>; 4378 hysteresis = <2000>; 4379 type = "critical"; 4380 }; 4381 }; 4382 }; 4383 }; 4384 4385 timer { 4386 compatible = "arm,armv8-timer"; 4387 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4388 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4389 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4390 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4391 }; 4392}; 4393