1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-sc7180.h> 11#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7180.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/interconnect/qcom,icc.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7180.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/phy/phy-qcom-qmp.h> 21#include <dt-bindings/phy/phy-qcom-qusb2.h> 22#include <dt-bindings/power/qcom-rpmpd.h> 23#include <dt-bindings/reset/qcom,sdm845-aoss.h> 24#include <dt-bindings/reset/qcom,sdm845-pdc.h> 25#include <dt-bindings/soc/qcom,rpmh-rsc.h> 26#include <dt-bindings/soc/qcom,apr.h> 27#include <dt-bindings/sound/qcom,q6afe.h> 28#include <dt-bindings/thermal/thermal.h> 29 30/ { 31 interrupt-parent = <&intc>; 32 33 #address-cells = <2>; 34 #size-cells = <2>; 35 36 aliases { 37 mmc1 = &sdhc_1; 38 mmc2 = &sdhc_2; 39 i2c0 = &i2c0; 40 i2c1 = &i2c1; 41 i2c2 = &i2c2; 42 i2c3 = &i2c3; 43 i2c4 = &i2c4; 44 i2c5 = &i2c5; 45 i2c6 = &i2c6; 46 i2c7 = &i2c7; 47 i2c8 = &i2c8; 48 i2c9 = &i2c9; 49 i2c10 = &i2c10; 50 i2c11 = &i2c11; 51 spi0 = &spi0; 52 spi1 = &spi1; 53 spi3 = &spi3; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi8 = &spi8; 57 spi10 = &spi10; 58 spi11 = &spi11; 59 }; 60 61 chosen { }; 62 63 clocks { 64 xo_board: xo-board { 65 compatible = "fixed-clock"; 66 clock-frequency = <38400000>; 67 #clock-cells = <0>; 68 }; 69 70 sleep_clk: sleep-clk { 71 compatible = "fixed-clock"; 72 clock-frequency = <32764>; 73 #clock-cells = <0>; 74 }; 75 }; 76 77 cpus { 78 #address-cells = <2>; 79 #size-cells = <0>; 80 81 cpu0: cpu@0 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo468"; 84 reg = <0x0 0x0>; 85 clocks = <&cpufreq_hw 0>; 86 enable-method = "psci"; 87 power-domains = <&cpu_pd0>; 88 power-domain-names = "psci"; 89 capacity-dmips-mhz = <415>; 90 dynamic-power-coefficient = <137>; 91 operating-points-v2 = <&cpu0_opp_table>; 92 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 93 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 94 next-level-cache = <&l2_0>; 95 #cooling-cells = <2>; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 l2_0: l2-cache { 98 compatible = "cache"; 99 cache-level = <2>; 100 cache-unified; 101 next-level-cache = <&l3_0>; 102 l3_0: l3-cache { 103 compatible = "cache"; 104 cache-level = <3>; 105 cache-unified; 106 }; 107 }; 108 }; 109 110 cpu1: cpu@100 { 111 device_type = "cpu"; 112 compatible = "qcom,kryo468"; 113 reg = <0x0 0x100>; 114 clocks = <&cpufreq_hw 0>; 115 enable-method = "psci"; 116 power-domains = <&cpu_pd1>; 117 power-domain-names = "psci"; 118 capacity-dmips-mhz = <415>; 119 dynamic-power-coefficient = <137>; 120 next-level-cache = <&l2_100>; 121 operating-points-v2 = <&cpu0_opp_table>; 122 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 123 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 124 #cooling-cells = <2>; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 l2_100: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 cache-unified; 130 next-level-cache = <&l3_0>; 131 }; 132 }; 133 134 cpu2: cpu@200 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo468"; 137 reg = <0x0 0x200>; 138 clocks = <&cpufreq_hw 0>; 139 enable-method = "psci"; 140 power-domains = <&cpu_pd2>; 141 power-domain-names = "psci"; 142 capacity-dmips-mhz = <415>; 143 dynamic-power-coefficient = <137>; 144 next-level-cache = <&l2_200>; 145 operating-points-v2 = <&cpu0_opp_table>; 146 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 147 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 148 #cooling-cells = <2>; 149 qcom,freq-domain = <&cpufreq_hw 0>; 150 l2_200: l2-cache { 151 compatible = "cache"; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_0>; 155 }; 156 }; 157 158 cpu3: cpu@300 { 159 device_type = "cpu"; 160 compatible = "qcom,kryo468"; 161 reg = <0x0 0x300>; 162 clocks = <&cpufreq_hw 0>; 163 enable-method = "psci"; 164 power-domains = <&cpu_pd3>; 165 power-domain-names = "psci"; 166 capacity-dmips-mhz = <415>; 167 dynamic-power-coefficient = <137>; 168 next-level-cache = <&l2_300>; 169 operating-points-v2 = <&cpu0_opp_table>; 170 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 171 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 172 #cooling-cells = <2>; 173 qcom,freq-domain = <&cpufreq_hw 0>; 174 l2_300: l2-cache { 175 compatible = "cache"; 176 cache-level = <2>; 177 cache-unified; 178 next-level-cache = <&l3_0>; 179 }; 180 }; 181 182 cpu4: cpu@400 { 183 device_type = "cpu"; 184 compatible = "qcom,kryo468"; 185 reg = <0x0 0x400>; 186 clocks = <&cpufreq_hw 0>; 187 enable-method = "psci"; 188 power-domains = <&cpu_pd4>; 189 power-domain-names = "psci"; 190 capacity-dmips-mhz = <415>; 191 dynamic-power-coefficient = <137>; 192 next-level-cache = <&l2_400>; 193 operating-points-v2 = <&cpu0_opp_table>; 194 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 195 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 196 #cooling-cells = <2>; 197 qcom,freq-domain = <&cpufreq_hw 0>; 198 l2_400: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&l3_0>; 203 }; 204 }; 205 206 cpu5: cpu@500 { 207 device_type = "cpu"; 208 compatible = "qcom,kryo468"; 209 reg = <0x0 0x500>; 210 clocks = <&cpufreq_hw 0>; 211 enable-method = "psci"; 212 power-domains = <&cpu_pd5>; 213 power-domain-names = "psci"; 214 capacity-dmips-mhz = <415>; 215 dynamic-power-coefficient = <137>; 216 next-level-cache = <&l2_500>; 217 operating-points-v2 = <&cpu0_opp_table>; 218 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 219 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 220 #cooling-cells = <2>; 221 qcom,freq-domain = <&cpufreq_hw 0>; 222 l2_500: l2-cache { 223 compatible = "cache"; 224 cache-level = <2>; 225 cache-unified; 226 next-level-cache = <&l3_0>; 227 }; 228 }; 229 230 cpu6: cpu@600 { 231 device_type = "cpu"; 232 compatible = "qcom,kryo468"; 233 reg = <0x0 0x600>; 234 clocks = <&cpufreq_hw 1>; 235 enable-method = "psci"; 236 power-domains = <&cpu_pd6>; 237 power-domain-names = "psci"; 238 capacity-dmips-mhz = <1024>; 239 dynamic-power-coefficient = <480>; 240 next-level-cache = <&l2_600>; 241 operating-points-v2 = <&cpu6_opp_table>; 242 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 243 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 244 #cooling-cells = <2>; 245 qcom,freq-domain = <&cpufreq_hw 1>; 246 l2_600: l2-cache { 247 compatible = "cache"; 248 cache-level = <2>; 249 cache-unified; 250 next-level-cache = <&l3_0>; 251 }; 252 }; 253 254 cpu7: cpu@700 { 255 device_type = "cpu"; 256 compatible = "qcom,kryo468"; 257 reg = <0x0 0x700>; 258 clocks = <&cpufreq_hw 1>; 259 enable-method = "psci"; 260 power-domains = <&cpu_pd7>; 261 power-domain-names = "psci"; 262 capacity-dmips-mhz = <1024>; 263 dynamic-power-coefficient = <480>; 264 next-level-cache = <&l2_700>; 265 operating-points-v2 = <&cpu6_opp_table>; 266 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 267 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 268 #cooling-cells = <2>; 269 qcom,freq-domain = <&cpufreq_hw 1>; 270 l2_700: l2-cache { 271 compatible = "cache"; 272 cache-level = <2>; 273 cache-unified; 274 next-level-cache = <&l3_0>; 275 }; 276 }; 277 278 cpu-map { 279 cluster0 { 280 core0 { 281 cpu = <&cpu0>; 282 }; 283 284 core1 { 285 cpu = <&cpu1>; 286 }; 287 288 core2 { 289 cpu = <&cpu2>; 290 }; 291 292 core3 { 293 cpu = <&cpu3>; 294 }; 295 296 core4 { 297 cpu = <&cpu4>; 298 }; 299 300 core5 { 301 cpu = <&cpu5>; 302 }; 303 304 core6 { 305 cpu = <&cpu6>; 306 }; 307 308 core7 { 309 cpu = <&cpu7>; 310 }; 311 }; 312 }; 313 314 idle_states: idle-states { 315 entry-method = "psci"; 316 317 little_cpu_sleep_0: cpu-sleep-0-0 { 318 compatible = "arm,idle-state"; 319 idle-state-name = "little-power-down"; 320 arm,psci-suspend-param = <0x40000003>; 321 entry-latency-us = <549>; 322 exit-latency-us = <901>; 323 min-residency-us = <1774>; 324 local-timer-stop; 325 }; 326 327 little_cpu_sleep_1: cpu-sleep-0-1 { 328 compatible = "arm,idle-state"; 329 idle-state-name = "little-rail-power-down"; 330 arm,psci-suspend-param = <0x40000004>; 331 entry-latency-us = <702>; 332 exit-latency-us = <915>; 333 min-residency-us = <4001>; 334 local-timer-stop; 335 }; 336 337 big_cpu_sleep_0: cpu-sleep-1-0 { 338 compatible = "arm,idle-state"; 339 idle-state-name = "big-power-down"; 340 arm,psci-suspend-param = <0x40000003>; 341 entry-latency-us = <523>; 342 exit-latency-us = <1244>; 343 min-residency-us = <2207>; 344 local-timer-stop; 345 }; 346 347 big_cpu_sleep_1: cpu-sleep-1-1 { 348 compatible = "arm,idle-state"; 349 idle-state-name = "big-rail-power-down"; 350 arm,psci-suspend-param = <0x40000004>; 351 entry-latency-us = <526>; 352 exit-latency-us = <1854>; 353 min-residency-us = <5555>; 354 local-timer-stop; 355 }; 356 }; 357 358 domain_idle_states: domain-idle-states { 359 cluster_sleep_pc: cluster-sleep-0 { 360 compatible = "domain-idle-state"; 361 arm,psci-suspend-param = <0x41000044>; 362 entry-latency-us = <2752>; 363 exit-latency-us = <3048>; 364 min-residency-us = <6118>; 365 }; 366 367 cluster_sleep_cx_ret: cluster-sleep-1 { 368 compatible = "domain-idle-state"; 369 arm,psci-suspend-param = <0x41001244>; 370 entry-latency-us = <3638>; 371 exit-latency-us = <4562>; 372 min-residency-us = <8467>; 373 }; 374 375 cluster_aoss_sleep: cluster-sleep-2 { 376 compatible = "domain-idle-state"; 377 arm,psci-suspend-param = <0x4100b244>; 378 entry-latency-us = <3263>; 379 exit-latency-us = <6562>; 380 min-residency-us = <9826>; 381 }; 382 }; 383 }; 384 385 firmware { 386 scm: scm { 387 compatible = "qcom,scm-sc7180", "qcom,scm"; 388 }; 389 }; 390 391 memory@80000000 { 392 device_type = "memory"; 393 /* We expect the bootloader to fill in the size */ 394 reg = <0 0x80000000 0 0>; 395 }; 396 397 cpu0_opp_table: opp-table-cpu0 { 398 compatible = "operating-points-v2"; 399 opp-shared; 400 401 cpu0_opp1: opp-300000000 { 402 opp-hz = /bits/ 64 <300000000>; 403 opp-peak-kBps = <1200000 4800000>; 404 }; 405 406 cpu0_opp2: opp-576000000 { 407 opp-hz = /bits/ 64 <576000000>; 408 opp-peak-kBps = <1200000 4800000>; 409 }; 410 411 cpu0_opp3: opp-768000000 { 412 opp-hz = /bits/ 64 <768000000>; 413 opp-peak-kBps = <1200000 4800000>; 414 }; 415 416 cpu0_opp4: opp-1017600000 { 417 opp-hz = /bits/ 64 <1017600000>; 418 opp-peak-kBps = <1804000 8908800>; 419 }; 420 421 cpu0_opp5: opp-1248000000 { 422 opp-hz = /bits/ 64 <1248000000>; 423 opp-peak-kBps = <2188000 12902400>; 424 }; 425 426 cpu0_opp6: opp-1324800000 { 427 opp-hz = /bits/ 64 <1324800000>; 428 opp-peak-kBps = <2188000 12902400>; 429 }; 430 431 cpu0_opp7: opp-1516800000 { 432 opp-hz = /bits/ 64 <1516800000>; 433 opp-peak-kBps = <3072000 15052800>; 434 }; 435 436 cpu0_opp8: opp-1612800000 { 437 opp-hz = /bits/ 64 <1612800000>; 438 opp-peak-kBps = <3072000 15052800>; 439 }; 440 441 cpu0_opp9: opp-1708800000 { 442 opp-hz = /bits/ 64 <1708800000>; 443 opp-peak-kBps = <3072000 15052800>; 444 }; 445 446 cpu0_opp10: opp-1804800000 { 447 opp-hz = /bits/ 64 <1804800000>; 448 opp-peak-kBps = <4068000 22425600>; 449 }; 450 }; 451 452 cpu6_opp_table: opp-table-cpu6 { 453 compatible = "operating-points-v2"; 454 opp-shared; 455 456 cpu6_opp1: opp-300000000 { 457 opp-hz = /bits/ 64 <300000000>; 458 opp-peak-kBps = <2188000 8908800>; 459 }; 460 461 cpu6_opp2: opp-652800000 { 462 opp-hz = /bits/ 64 <652800000>; 463 opp-peak-kBps = <2188000 8908800>; 464 }; 465 466 cpu6_opp3: opp-825600000 { 467 opp-hz = /bits/ 64 <825600000>; 468 opp-peak-kBps = <2188000 8908800>; 469 }; 470 471 cpu6_opp4: opp-979200000 { 472 opp-hz = /bits/ 64 <979200000>; 473 opp-peak-kBps = <2188000 8908800>; 474 }; 475 476 cpu6_opp5: opp-1113600000 { 477 opp-hz = /bits/ 64 <1113600000>; 478 opp-peak-kBps = <2188000 8908800>; 479 }; 480 481 cpu6_opp6: opp-1267200000 { 482 opp-hz = /bits/ 64 <1267200000>; 483 opp-peak-kBps = <4068000 12902400>; 484 }; 485 486 cpu6_opp7: opp-1555200000 { 487 opp-hz = /bits/ 64 <1555200000>; 488 opp-peak-kBps = <4068000 15052800>; 489 }; 490 491 cpu6_opp8: opp-1708800000 { 492 opp-hz = /bits/ 64 <1708800000>; 493 opp-peak-kBps = <6220000 19353600>; 494 }; 495 496 cpu6_opp9: opp-1843200000 { 497 opp-hz = /bits/ 64 <1843200000>; 498 opp-peak-kBps = <6220000 19353600>; 499 }; 500 501 cpu6_opp10: opp-1900800000 { 502 opp-hz = /bits/ 64 <1900800000>; 503 opp-peak-kBps = <6220000 22425600>; 504 }; 505 506 cpu6_opp11: opp-1996800000 { 507 opp-hz = /bits/ 64 <1996800000>; 508 opp-peak-kBps = <6220000 22425600>; 509 }; 510 511 cpu6_opp12: opp-2112000000 { 512 opp-hz = /bits/ 64 <2112000000>; 513 opp-peak-kBps = <6220000 22425600>; 514 }; 515 516 cpu6_opp13: opp-2208000000 { 517 opp-hz = /bits/ 64 <2208000000>; 518 opp-peak-kBps = <7216000 22425600>; 519 }; 520 521 cpu6_opp14: opp-2323200000 { 522 opp-hz = /bits/ 64 <2323200000>; 523 opp-peak-kBps = <7216000 22425600>; 524 }; 525 526 cpu6_opp15: opp-2400000000 { 527 opp-hz = /bits/ 64 <2400000000>; 528 opp-peak-kBps = <8532000 23347200>; 529 }; 530 531 cpu6_opp16: opp-2553600000 { 532 opp-hz = /bits/ 64 <2553600000>; 533 opp-peak-kBps = <8532000 23347200>; 534 }; 535 }; 536 537 qspi_opp_table: opp-table-qspi { 538 compatible = "operating-points-v2"; 539 540 opp-75000000 { 541 opp-hz = /bits/ 64 <75000000>; 542 required-opps = <&rpmhpd_opp_low_svs>; 543 }; 544 545 opp-150000000 { 546 opp-hz = /bits/ 64 <150000000>; 547 required-opps = <&rpmhpd_opp_svs>; 548 }; 549 550 opp-300000000 { 551 opp-hz = /bits/ 64 <300000000>; 552 required-opps = <&rpmhpd_opp_nom>; 553 }; 554 }; 555 556 qup_opp_table: opp-table-qup { 557 compatible = "operating-points-v2"; 558 559 opp-75000000 { 560 opp-hz = /bits/ 64 <75000000>; 561 required-opps = <&rpmhpd_opp_low_svs>; 562 }; 563 564 opp-100000000 { 565 opp-hz = /bits/ 64 <100000000>; 566 required-opps = <&rpmhpd_opp_svs>; 567 }; 568 569 opp-128000000 { 570 opp-hz = /bits/ 64 <128000000>; 571 required-opps = <&rpmhpd_opp_nom>; 572 }; 573 }; 574 575 pmu { 576 compatible = "arm,armv8-pmuv3"; 577 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 578 }; 579 580 psci { 581 compatible = "arm,psci-1.0"; 582 method = "smc"; 583 584 cpu_pd0: power-domain-cpu0 { 585 #power-domain-cells = <0>; 586 power-domains = <&cluster_pd>; 587 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 588 }; 589 590 cpu_pd1: power-domain-cpu1 { 591 #power-domain-cells = <0>; 592 power-domains = <&cluster_pd>; 593 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 594 }; 595 596 cpu_pd2: power-domain-cpu2 { 597 #power-domain-cells = <0>; 598 power-domains = <&cluster_pd>; 599 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 600 }; 601 602 cpu_pd3: power-domain-cpu3 { 603 #power-domain-cells = <0>; 604 power-domains = <&cluster_pd>; 605 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 606 }; 607 608 cpu_pd4: power-domain-cpu4 { 609 #power-domain-cells = <0>; 610 power-domains = <&cluster_pd>; 611 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 612 }; 613 614 cpu_pd5: power-domain-cpu5 { 615 #power-domain-cells = <0>; 616 power-domains = <&cluster_pd>; 617 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 618 }; 619 620 cpu_pd6: power-domain-cpu6 { 621 #power-domain-cells = <0>; 622 power-domains = <&cluster_pd>; 623 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 624 }; 625 626 cpu_pd7: power-domain-cpu7 { 627 #power-domain-cells = <0>; 628 power-domains = <&cluster_pd>; 629 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 630 }; 631 632 cluster_pd: power-domain-cluster { 633 #power-domain-cells = <0>; 634 domain-idle-states = <&cluster_sleep_pc 635 &cluster_sleep_cx_ret 636 &cluster_aoss_sleep>; 637 }; 638 }; 639 640 reserved_memory: reserved-memory { 641 #address-cells = <2>; 642 #size-cells = <2>; 643 ranges; 644 645 hyp_mem: memory@80000000 { 646 reg = <0x0 0x80000000 0x0 0x600000>; 647 no-map; 648 }; 649 650 xbl_mem: memory@80600000 { 651 reg = <0x0 0x80600000 0x0 0x200000>; 652 no-map; 653 }; 654 655 aop_mem: memory@80800000 { 656 reg = <0x0 0x80800000 0x0 0x20000>; 657 no-map; 658 }; 659 660 aop_cmd_db_mem: memory@80820000 { 661 reg = <0x0 0x80820000 0x0 0x20000>; 662 compatible = "qcom,cmd-db"; 663 no-map; 664 }; 665 666 sec_apps_mem: memory@808ff000 { 667 reg = <0x0 0x808ff000 0x0 0x1000>; 668 no-map; 669 }; 670 671 smem_mem: memory@80900000 { 672 reg = <0x0 0x80900000 0x0 0x200000>; 673 no-map; 674 }; 675 676 tz_mem: memory@80b00000 { 677 reg = <0x0 0x80b00000 0x0 0x3900000>; 678 no-map; 679 }; 680 681 ipa_fw_mem: memory@8b700000 { 682 reg = <0 0x8b700000 0 0x10000>; 683 no-map; 684 }; 685 686 rmtfs_mem: memory@94600000 { 687 compatible = "qcom,rmtfs-mem"; 688 reg = <0x0 0x94600000 0x0 0x200000>; 689 no-map; 690 691 qcom,client-id = <1>; 692 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 693 }; 694 }; 695 696 smem { 697 compatible = "qcom,smem"; 698 memory-region = <&smem_mem>; 699 hwlocks = <&tcsr_mutex 3>; 700 }; 701 702 smp2p-cdsp { 703 compatible = "qcom,smp2p"; 704 qcom,smem = <94>, <432>; 705 706 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 707 708 mboxes = <&apss_shared 6>; 709 710 qcom,local-pid = <0>; 711 qcom,remote-pid = <5>; 712 713 cdsp_smp2p_out: master-kernel { 714 qcom,entry-name = "master-kernel"; 715 #qcom,smem-state-cells = <1>; 716 }; 717 718 cdsp_smp2p_in: slave-kernel { 719 qcom,entry-name = "slave-kernel"; 720 721 interrupt-controller; 722 #interrupt-cells = <2>; 723 }; 724 }; 725 726 smp2p-lpass { 727 compatible = "qcom,smp2p"; 728 qcom,smem = <443>, <429>; 729 730 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 731 732 mboxes = <&apss_shared 10>; 733 734 qcom,local-pid = <0>; 735 qcom,remote-pid = <2>; 736 737 adsp_smp2p_out: master-kernel { 738 qcom,entry-name = "master-kernel"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 adsp_smp2p_in: slave-kernel { 743 qcom,entry-name = "slave-kernel"; 744 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 smp2p-mpss { 751 compatible = "qcom,smp2p"; 752 qcom,smem = <435>, <428>; 753 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 754 mboxes = <&apss_shared 14>; 755 qcom,local-pid = <0>; 756 qcom,remote-pid = <1>; 757 758 modem_smp2p_out: master-kernel { 759 qcom,entry-name = "master-kernel"; 760 #qcom,smem-state-cells = <1>; 761 }; 762 763 modem_smp2p_in: slave-kernel { 764 qcom,entry-name = "slave-kernel"; 765 interrupt-controller; 766 #interrupt-cells = <2>; 767 }; 768 769 ipa_smp2p_out: ipa-ap-to-modem { 770 qcom,entry-name = "ipa"; 771 #qcom,smem-state-cells = <1>; 772 }; 773 774 ipa_smp2p_in: ipa-modem-to-ap { 775 qcom,entry-name = "ipa"; 776 interrupt-controller; 777 #interrupt-cells = <2>; 778 }; 779 }; 780 781 soc: soc@0 { 782 #address-cells = <2>; 783 #size-cells = <2>; 784 ranges = <0 0 0 0 0x10 0>; 785 dma-ranges = <0 0 0 0 0x10 0>; 786 compatible = "simple-bus"; 787 788 gcc: clock-controller@100000 { 789 compatible = "qcom,gcc-sc7180"; 790 reg = <0 0x00100000 0 0x1f0000>; 791 clocks = <&rpmhcc RPMH_CXO_CLK>, 792 <&rpmhcc RPMH_CXO_CLK_A>, 793 <&sleep_clk>; 794 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 795 #clock-cells = <1>; 796 #reset-cells = <1>; 797 #power-domain-cells = <1>; 798 power-domains = <&rpmhpd SC7180_CX>; 799 }; 800 801 qfprom: efuse@784000 { 802 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 803 reg = <0 0x00784000 0 0x7a0>, 804 <0 0x00780000 0 0x7a0>, 805 <0 0x00782000 0 0x100>, 806 <0 0x00786000 0 0x1fff>; 807 808 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 809 clock-names = "core"; 810 #address-cells = <1>; 811 #size-cells = <1>; 812 813 qusb2p_hstx_trim: hstx-trim-primary@25b { 814 reg = <0x25b 0x1>; 815 bits = <1 3>; 816 }; 817 818 gpu_speed_bin: gpu-speed-bin@1d2 { 819 reg = <0x1d2 0x2>; 820 bits = <5 8>; 821 }; 822 }; 823 824 sdhc_1: mmc@7c4000 { 825 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 826 reg = <0 0x007c4000 0 0x1000>, 827 <0 0x007c5000 0 0x1000>; 828 reg-names = "hc", "cqhci"; 829 830 iommus = <&apps_smmu 0x60 0x0>; 831 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 833 interrupt-names = "hc_irq", "pwr_irq"; 834 835 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 836 <&gcc GCC_SDCC1_APPS_CLK>, 837 <&rpmhcc RPMH_CXO_CLK>; 838 clock-names = "iface", "core", "xo"; 839 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 840 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 841 interconnect-names = "sdhc-ddr","cpu-sdhc"; 842 power-domains = <&rpmhpd SC7180_CX>; 843 operating-points-v2 = <&sdhc1_opp_table>; 844 845 bus-width = <8>; 846 non-removable; 847 supports-cqe; 848 849 mmc-ddr-1_8v; 850 mmc-hs200-1_8v; 851 mmc-hs400-1_8v; 852 mmc-hs400-enhanced-strobe; 853 854 status = "disabled"; 855 856 sdhc1_opp_table: opp-table { 857 compatible = "operating-points-v2"; 858 859 opp-100000000 { 860 opp-hz = /bits/ 64 <100000000>; 861 required-opps = <&rpmhpd_opp_low_svs>; 862 opp-peak-kBps = <1800000 600000>; 863 opp-avg-kBps = <100000 0>; 864 }; 865 866 opp-384000000 { 867 opp-hz = /bits/ 64 <384000000>; 868 required-opps = <&rpmhpd_opp_nom>; 869 opp-peak-kBps = <5400000 1600000>; 870 opp-avg-kBps = <390000 0>; 871 }; 872 }; 873 }; 874 875 qupv3_id_0: geniqup@8c0000 { 876 compatible = "qcom,geni-se-qup"; 877 reg = <0 0x008c0000 0 0x6000>; 878 clock-names = "m-ahb", "s-ahb"; 879 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 880 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 881 #address-cells = <2>; 882 #size-cells = <2>; 883 ranges; 884 iommus = <&apps_smmu 0x43 0x0>; 885 status = "disabled"; 886 887 i2c0: i2c@880000 { 888 compatible = "qcom,geni-i2c"; 889 reg = <0 0x00880000 0 0x4000>; 890 clock-names = "se"; 891 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&qup_i2c0_default>; 894 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 898 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 899 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 900 interconnect-names = "qup-core", "qup-config", 901 "qup-memory"; 902 power-domains = <&rpmhpd SC7180_CX>; 903 required-opps = <&rpmhpd_opp_low_svs>; 904 status = "disabled"; 905 }; 906 907 spi0: spi@880000 { 908 compatible = "qcom,geni-spi"; 909 reg = <0 0x00880000 0 0x4000>; 910 clock-names = "se"; 911 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>; 914 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 power-domains = <&rpmhpd SC7180_CX>; 918 operating-points-v2 = <&qup_opp_table>; 919 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 920 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 921 interconnect-names = "qup-core", "qup-config"; 922 status = "disabled"; 923 }; 924 925 uart0: serial@880000 { 926 compatible = "qcom,geni-uart"; 927 reg = <0 0x00880000 0 0x4000>; 928 clock-names = "se"; 929 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 930 pinctrl-names = "default"; 931 pinctrl-0 = <&qup_uart0_default>; 932 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 933 power-domains = <&rpmhpd SC7180_CX>; 934 operating-points-v2 = <&qup_opp_table>; 935 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 937 interconnect-names = "qup-core", "qup-config"; 938 status = "disabled"; 939 }; 940 941 i2c1: i2c@884000 { 942 compatible = "qcom,geni-i2c"; 943 reg = <0 0x00884000 0 0x4000>; 944 clock-names = "se"; 945 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&qup_i2c1_default>; 948 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 952 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 953 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 954 interconnect-names = "qup-core", "qup-config", 955 "qup-memory"; 956 power-domains = <&rpmhpd SC7180_CX>; 957 required-opps = <&rpmhpd_opp_low_svs>; 958 status = "disabled"; 959 }; 960 961 spi1: spi@884000 { 962 compatible = "qcom,geni-spi"; 963 reg = <0 0x00884000 0 0x4000>; 964 clock-names = "se"; 965 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>; 968 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 power-domains = <&rpmhpd SC7180_CX>; 972 operating-points-v2 = <&qup_opp_table>; 973 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 974 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 975 interconnect-names = "qup-core", "qup-config"; 976 status = "disabled"; 977 }; 978 979 uart1: serial@884000 { 980 compatible = "qcom,geni-uart"; 981 reg = <0 0x00884000 0 0x4000>; 982 clock-names = "se"; 983 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_uart1_default>; 986 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 987 power-domains = <&rpmhpd SC7180_CX>; 988 operating-points-v2 = <&qup_opp_table>; 989 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 990 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 991 interconnect-names = "qup-core", "qup-config"; 992 status = "disabled"; 993 }; 994 995 i2c2: i2c@888000 { 996 compatible = "qcom,geni-i2c"; 997 reg = <0 0x00888000 0 0x4000>; 998 clock-names = "se"; 999 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_i2c2_default>; 1002 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1006 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1007 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1008 interconnect-names = "qup-core", "qup-config", 1009 "qup-memory"; 1010 power-domains = <&rpmhpd SC7180_CX>; 1011 required-opps = <&rpmhpd_opp_low_svs>; 1012 status = "disabled"; 1013 }; 1014 1015 uart2: serial@888000 { 1016 compatible = "qcom,geni-uart"; 1017 reg = <0 0x00888000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_uart2_default>; 1022 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1023 power-domains = <&rpmhpd SC7180_CX>; 1024 operating-points-v2 = <&qup_opp_table>; 1025 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1026 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1027 interconnect-names = "qup-core", "qup-config"; 1028 status = "disabled"; 1029 }; 1030 1031 i2c3: i2c@88c000 { 1032 compatible = "qcom,geni-i2c"; 1033 reg = <0 0x0088c000 0 0x4000>; 1034 clock-names = "se"; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1036 pinctrl-names = "default"; 1037 pinctrl-0 = <&qup_i2c3_default>; 1038 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1042 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1043 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1044 interconnect-names = "qup-core", "qup-config", 1045 "qup-memory"; 1046 power-domains = <&rpmhpd SC7180_CX>; 1047 required-opps = <&rpmhpd_opp_low_svs>; 1048 status = "disabled"; 1049 }; 1050 1051 spi3: spi@88c000 { 1052 compatible = "qcom,geni-spi"; 1053 reg = <0 0x0088c000 0 0x4000>; 1054 clock-names = "se"; 1055 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1056 pinctrl-names = "default"; 1057 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>; 1058 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 power-domains = <&rpmhpd SC7180_CX>; 1062 operating-points-v2 = <&qup_opp_table>; 1063 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1064 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1065 interconnect-names = "qup-core", "qup-config"; 1066 status = "disabled"; 1067 }; 1068 1069 uart3: serial@88c000 { 1070 compatible = "qcom,geni-uart"; 1071 reg = <0 0x0088c000 0 0x4000>; 1072 clock-names = "se"; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&qup_uart3_default>; 1076 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1077 power-domains = <&rpmhpd SC7180_CX>; 1078 operating-points-v2 = <&qup_opp_table>; 1079 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1080 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1081 interconnect-names = "qup-core", "qup-config"; 1082 status = "disabled"; 1083 }; 1084 1085 i2c4: i2c@890000 { 1086 compatible = "qcom,geni-i2c"; 1087 reg = <0 0x00890000 0 0x4000>; 1088 clock-names = "se"; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1090 pinctrl-names = "default"; 1091 pinctrl-0 = <&qup_i2c4_default>; 1092 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1096 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1097 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1098 interconnect-names = "qup-core", "qup-config", 1099 "qup-memory"; 1100 power-domains = <&rpmhpd SC7180_CX>; 1101 required-opps = <&rpmhpd_opp_low_svs>; 1102 status = "disabled"; 1103 }; 1104 1105 uart4: serial@890000 { 1106 compatible = "qcom,geni-uart"; 1107 reg = <0 0x00890000 0 0x4000>; 1108 clock-names = "se"; 1109 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&qup_uart4_default>; 1112 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1113 power-domains = <&rpmhpd SC7180_CX>; 1114 operating-points-v2 = <&qup_opp_table>; 1115 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1116 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1117 interconnect-names = "qup-core", "qup-config"; 1118 status = "disabled"; 1119 }; 1120 1121 i2c5: i2c@894000 { 1122 compatible = "qcom,geni-i2c"; 1123 reg = <0 0x00894000 0 0x4000>; 1124 clock-names = "se"; 1125 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1126 pinctrl-names = "default"; 1127 pinctrl-0 = <&qup_i2c5_default>; 1128 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1132 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1133 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1134 interconnect-names = "qup-core", "qup-config", 1135 "qup-memory"; 1136 power-domains = <&rpmhpd SC7180_CX>; 1137 required-opps = <&rpmhpd_opp_low_svs>; 1138 status = "disabled"; 1139 }; 1140 1141 spi5: spi@894000 { 1142 compatible = "qcom,geni-spi"; 1143 reg = <0 0x00894000 0 0x4000>; 1144 clock-names = "se"; 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>; 1148 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 power-domains = <&rpmhpd SC7180_CX>; 1152 operating-points-v2 = <&qup_opp_table>; 1153 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1154 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1155 interconnect-names = "qup-core", "qup-config"; 1156 status = "disabled"; 1157 }; 1158 1159 uart5: serial@894000 { 1160 compatible = "qcom,geni-uart"; 1161 reg = <0 0x00894000 0 0x4000>; 1162 clock-names = "se"; 1163 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&qup_uart5_default>; 1166 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1167 power-domains = <&rpmhpd SC7180_CX>; 1168 operating-points-v2 = <&qup_opp_table>; 1169 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1170 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1171 interconnect-names = "qup-core", "qup-config"; 1172 status = "disabled"; 1173 }; 1174 }; 1175 1176 qupv3_id_1: geniqup@ac0000 { 1177 compatible = "qcom,geni-se-qup"; 1178 reg = <0 0x00ac0000 0 0x6000>; 1179 clock-names = "m-ahb", "s-ahb"; 1180 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1181 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1182 #address-cells = <2>; 1183 #size-cells = <2>; 1184 ranges; 1185 iommus = <&apps_smmu 0x4c3 0x0>; 1186 status = "disabled"; 1187 1188 i2c6: i2c@a80000 { 1189 compatible = "qcom,geni-i2c"; 1190 reg = <0 0x00a80000 0 0x4000>; 1191 clock-names = "se"; 1192 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_i2c6_default>; 1195 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1199 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1200 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1201 interconnect-names = "qup-core", "qup-config", 1202 "qup-memory"; 1203 power-domains = <&rpmhpd SC7180_CX>; 1204 required-opps = <&rpmhpd_opp_low_svs>; 1205 status = "disabled"; 1206 }; 1207 1208 spi6: spi@a80000 { 1209 compatible = "qcom,geni-spi"; 1210 reg = <0 0x00a80000 0 0x4000>; 1211 clock-names = "se"; 1212 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1213 pinctrl-names = "default"; 1214 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>; 1215 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 power-domains = <&rpmhpd SC7180_CX>; 1219 operating-points-v2 = <&qup_opp_table>; 1220 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1222 interconnect-names = "qup-core", "qup-config"; 1223 status = "disabled"; 1224 }; 1225 1226 uart6: serial@a80000 { 1227 compatible = "qcom,geni-uart"; 1228 reg = <0 0x00a80000 0 0x4000>; 1229 clock-names = "se"; 1230 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&qup_uart6_default>; 1233 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1234 power-domains = <&rpmhpd SC7180_CX>; 1235 operating-points-v2 = <&qup_opp_table>; 1236 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1238 interconnect-names = "qup-core", "qup-config"; 1239 status = "disabled"; 1240 }; 1241 1242 i2c7: i2c@a84000 { 1243 compatible = "qcom,geni-i2c"; 1244 reg = <0 0x00a84000 0 0x4000>; 1245 clock-names = "se"; 1246 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1247 pinctrl-names = "default"; 1248 pinctrl-0 = <&qup_i2c7_default>; 1249 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1253 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1254 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1255 interconnect-names = "qup-core", "qup-config", 1256 "qup-memory"; 1257 power-domains = <&rpmhpd SC7180_CX>; 1258 required-opps = <&rpmhpd_opp_low_svs>; 1259 status = "disabled"; 1260 }; 1261 1262 uart7: serial@a84000 { 1263 compatible = "qcom,geni-uart"; 1264 reg = <0 0x00a84000 0 0x4000>; 1265 clock-names = "se"; 1266 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&qup_uart7_default>; 1269 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1270 power-domains = <&rpmhpd SC7180_CX>; 1271 operating-points-v2 = <&qup_opp_table>; 1272 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1273 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1274 interconnect-names = "qup-core", "qup-config"; 1275 status = "disabled"; 1276 }; 1277 1278 i2c8: i2c@a88000 { 1279 compatible = "qcom,geni-i2c"; 1280 reg = <0 0x00a88000 0 0x4000>; 1281 clock-names = "se"; 1282 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_i2c8_default>; 1285 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1290 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1291 interconnect-names = "qup-core", "qup-config", 1292 "qup-memory"; 1293 power-domains = <&rpmhpd SC7180_CX>; 1294 required-opps = <&rpmhpd_opp_low_svs>; 1295 status = "disabled"; 1296 }; 1297 1298 spi8: spi@a88000 { 1299 compatible = "qcom,geni-spi"; 1300 reg = <0 0x00a88000 0 0x4000>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>; 1305 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 power-domains = <&rpmhpd SC7180_CX>; 1309 operating-points-v2 = <&qup_opp_table>; 1310 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1311 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1312 interconnect-names = "qup-core", "qup-config"; 1313 status = "disabled"; 1314 }; 1315 1316 uart8: serial@a88000 { 1317 compatible = "qcom,geni-debug-uart"; 1318 reg = <0 0x00a88000 0 0x4000>; 1319 clock-names = "se"; 1320 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_uart8_default>; 1323 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1324 power-domains = <&rpmhpd SC7180_CX>; 1325 operating-points-v2 = <&qup_opp_table>; 1326 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1327 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1328 interconnect-names = "qup-core", "qup-config"; 1329 status = "disabled"; 1330 }; 1331 1332 i2c9: i2c@a8c000 { 1333 compatible = "qcom,geni-i2c"; 1334 reg = <0 0x00a8c000 0 0x4000>; 1335 clock-names = "se"; 1336 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1337 pinctrl-names = "default"; 1338 pinctrl-0 = <&qup_i2c9_default>; 1339 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1343 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1344 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1345 interconnect-names = "qup-core", "qup-config", 1346 "qup-memory"; 1347 power-domains = <&rpmhpd SC7180_CX>; 1348 required-opps = <&rpmhpd_opp_low_svs>; 1349 status = "disabled"; 1350 }; 1351 1352 uart9: serial@a8c000 { 1353 compatible = "qcom,geni-uart"; 1354 reg = <0 0x00a8c000 0 0x4000>; 1355 clock-names = "se"; 1356 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1357 pinctrl-names = "default"; 1358 pinctrl-0 = <&qup_uart9_default>; 1359 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1360 power-domains = <&rpmhpd SC7180_CX>; 1361 operating-points-v2 = <&qup_opp_table>; 1362 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1364 interconnect-names = "qup-core", "qup-config"; 1365 status = "disabled"; 1366 }; 1367 1368 i2c10: i2c@a90000 { 1369 compatible = "qcom,geni-i2c"; 1370 reg = <0 0x00a90000 0 0x4000>; 1371 clock-names = "se"; 1372 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1373 pinctrl-names = "default"; 1374 pinctrl-0 = <&qup_i2c10_default>; 1375 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1376 #address-cells = <1>; 1377 #size-cells = <0>; 1378 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1379 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1380 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1381 interconnect-names = "qup-core", "qup-config", 1382 "qup-memory"; 1383 power-domains = <&rpmhpd SC7180_CX>; 1384 required-opps = <&rpmhpd_opp_low_svs>; 1385 status = "disabled"; 1386 }; 1387 1388 spi10: spi@a90000 { 1389 compatible = "qcom,geni-spi"; 1390 reg = <0 0x00a90000 0 0x4000>; 1391 clock-names = "se"; 1392 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1393 pinctrl-names = "default"; 1394 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>; 1395 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 power-domains = <&rpmhpd SC7180_CX>; 1399 operating-points-v2 = <&qup_opp_table>; 1400 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1401 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1402 interconnect-names = "qup-core", "qup-config"; 1403 status = "disabled"; 1404 }; 1405 1406 uart10: serial@a90000 { 1407 compatible = "qcom,geni-uart"; 1408 reg = <0 0x00a90000 0 0x4000>; 1409 clock-names = "se"; 1410 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1411 pinctrl-names = "default"; 1412 pinctrl-0 = <&qup_uart10_default>; 1413 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1414 power-domains = <&rpmhpd SC7180_CX>; 1415 operating-points-v2 = <&qup_opp_table>; 1416 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1417 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1418 interconnect-names = "qup-core", "qup-config"; 1419 status = "disabled"; 1420 }; 1421 1422 i2c11: i2c@a94000 { 1423 compatible = "qcom,geni-i2c"; 1424 reg = <0 0x00a94000 0 0x4000>; 1425 clock-names = "se"; 1426 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1427 pinctrl-names = "default"; 1428 pinctrl-0 = <&qup_i2c11_default>; 1429 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1433 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1434 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1435 interconnect-names = "qup-core", "qup-config", 1436 "qup-memory"; 1437 power-domains = <&rpmhpd SC7180_CX>; 1438 required-opps = <&rpmhpd_opp_low_svs>; 1439 status = "disabled"; 1440 }; 1441 1442 spi11: spi@a94000 { 1443 compatible = "qcom,geni-spi"; 1444 reg = <0 0x00a94000 0 0x4000>; 1445 clock-names = "se"; 1446 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>; 1449 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 power-domains = <&rpmhpd SC7180_CX>; 1453 operating-points-v2 = <&qup_opp_table>; 1454 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1455 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1456 interconnect-names = "qup-core", "qup-config"; 1457 status = "disabled"; 1458 }; 1459 1460 uart11: serial@a94000 { 1461 compatible = "qcom,geni-uart"; 1462 reg = <0 0x00a94000 0 0x4000>; 1463 clock-names = "se"; 1464 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1465 pinctrl-names = "default"; 1466 pinctrl-0 = <&qup_uart11_default>; 1467 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1468 power-domains = <&rpmhpd SC7180_CX>; 1469 operating-points-v2 = <&qup_opp_table>; 1470 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1471 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1472 interconnect-names = "qup-core", "qup-config"; 1473 status = "disabled"; 1474 }; 1475 }; 1476 1477 config_noc: interconnect@1500000 { 1478 compatible = "qcom,sc7180-config-noc"; 1479 reg = <0 0x01500000 0 0x28000>; 1480 #interconnect-cells = <2>; 1481 qcom,bcm-voters = <&apps_bcm_voter>; 1482 }; 1483 1484 system_noc: interconnect@1620000 { 1485 compatible = "qcom,sc7180-system-noc"; 1486 reg = <0 0x01620000 0 0x17080>; 1487 #interconnect-cells = <2>; 1488 qcom,bcm-voters = <&apps_bcm_voter>; 1489 }; 1490 1491 mc_virt: interconnect@1638000 { 1492 compatible = "qcom,sc7180-mc-virt"; 1493 reg = <0 0x01638000 0 0x1000>; 1494 #interconnect-cells = <2>; 1495 qcom,bcm-voters = <&apps_bcm_voter>; 1496 }; 1497 1498 qup_virt: interconnect@1650000 { 1499 compatible = "qcom,sc7180-qup-virt"; 1500 reg = <0 0x01650000 0 0x1000>; 1501 #interconnect-cells = <2>; 1502 qcom,bcm-voters = <&apps_bcm_voter>; 1503 }; 1504 1505 aggre1_noc: interconnect@16e0000 { 1506 compatible = "qcom,sc7180-aggre1-noc"; 1507 reg = <0 0x016e0000 0 0x15080>; 1508 #interconnect-cells = <2>; 1509 qcom,bcm-voters = <&apps_bcm_voter>; 1510 }; 1511 1512 aggre2_noc: interconnect@1705000 { 1513 compatible = "qcom,sc7180-aggre2-noc"; 1514 reg = <0 0x01705000 0 0x9000>; 1515 #interconnect-cells = <2>; 1516 qcom,bcm-voters = <&apps_bcm_voter>; 1517 }; 1518 1519 compute_noc: interconnect@170e000 { 1520 compatible = "qcom,sc7180-compute-noc"; 1521 reg = <0 0x0170e000 0 0x6000>; 1522 #interconnect-cells = <2>; 1523 qcom,bcm-voters = <&apps_bcm_voter>; 1524 }; 1525 1526 mmss_noc: interconnect@1740000 { 1527 compatible = "qcom,sc7180-mmss-noc"; 1528 reg = <0 0x01740000 0 0x1c100>; 1529 #interconnect-cells = <2>; 1530 qcom,bcm-voters = <&apps_bcm_voter>; 1531 }; 1532 1533 ufs_mem_hc: ufshc@1d84000 { 1534 compatible = "qcom,sc7180-ufshc", "qcom,ufshc", 1535 "jedec,ufs-2.0"; 1536 reg = <0 0x01d84000 0 0x3000>; 1537 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1538 phys = <&ufs_mem_phy>; 1539 phy-names = "ufsphy"; 1540 lanes-per-direction = <1>; 1541 #reset-cells = <1>; 1542 resets = <&gcc GCC_UFS_PHY_BCR>; 1543 reset-names = "rst"; 1544 1545 power-domains = <&gcc UFS_PHY_GDSC>; 1546 1547 iommus = <&apps_smmu 0xa0 0x0>; 1548 1549 clock-names = "core_clk", 1550 "bus_aggr_clk", 1551 "iface_clk", 1552 "core_clk_unipro", 1553 "ref_clk", 1554 "tx_lane0_sync_clk", 1555 "rx_lane0_sync_clk"; 1556 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1557 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1558 <&gcc GCC_UFS_PHY_AHB_CLK>, 1559 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1560 <&rpmhcc RPMH_CXO_CLK>, 1561 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1562 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; 1563 freq-table-hz = <50000000 200000000>, 1564 <0 0>, 1565 <0 0>, 1566 <37500000 150000000>, 1567 <0 0>, 1568 <0 0>, 1569 <0 0>; 1570 1571 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1572 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1573 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1574 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 1575 interconnect-names = "ufs-ddr", "cpu-ufs"; 1576 1577 qcom,ice = <&ice>; 1578 1579 status = "disabled"; 1580 }; 1581 1582 ufs_mem_phy: phy@1d87000 { 1583 compatible = "qcom,sc7180-qmp-ufs-phy"; 1584 reg = <0 0x01d87000 0 0x1000>; 1585 clocks = <&rpmhcc RPMH_CXO_CLK>, 1586 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1587 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1588 clock-names = "ref", 1589 "ref_aux", 1590 "qref"; 1591 power-domains = <&gcc UFS_PHY_GDSC>; 1592 resets = <&ufs_mem_hc 0>; 1593 reset-names = "ufsphy"; 1594 #phy-cells = <0>; 1595 status = "disabled"; 1596 }; 1597 1598 ice: crypto@1d90000 { 1599 compatible = "qcom,sc7180-inline-crypto-engine", 1600 "qcom,inline-crypto-engine"; 1601 reg = <0 0x01d90000 0 0x8000>; 1602 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1603 }; 1604 1605 ipa: ipa@1e40000 { 1606 compatible = "qcom,sc7180-ipa"; 1607 1608 iommus = <&apps_smmu 0x440 0x0>, 1609 <&apps_smmu 0x442 0x0>; 1610 reg = <0 0x01e40000 0 0x7000>, 1611 <0 0x01e47000 0 0x2000>, 1612 <0 0x01e04000 0 0x2c000>; 1613 reg-names = "ipa-reg", 1614 "ipa-shared", 1615 "gsi"; 1616 1617 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1618 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1619 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1620 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1621 interrupt-names = "ipa", 1622 "gsi", 1623 "ipa-clock-query", 1624 "ipa-setup-ready"; 1625 1626 clocks = <&rpmhcc RPMH_IPA_CLK>; 1627 clock-names = "core"; 1628 1629 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1630 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1631 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1632 interconnect-names = "memory", 1633 "imem", 1634 "config"; 1635 1636 qcom,qmp = <&aoss_qmp>; 1637 1638 qcom,smem-states = <&ipa_smp2p_out 0>, 1639 <&ipa_smp2p_out 1>; 1640 qcom,smem-state-names = "ipa-clock-enabled-valid", 1641 "ipa-clock-enabled"; 1642 1643 status = "disabled"; 1644 }; 1645 1646 tcsr_mutex: hwlock@1f40000 { 1647 compatible = "qcom,tcsr-mutex"; 1648 reg = <0 0x01f40000 0 0x20000>; 1649 #hwlock-cells = <1>; 1650 }; 1651 1652 tcsr_regs_1: syscon@1f60000 { 1653 compatible = "qcom,sc7180-tcsr", "syscon"; 1654 reg = <0 0x01f60000 0 0x20000>; 1655 }; 1656 1657 tcsr_regs_2: syscon@1fc0000 { 1658 compatible = "qcom,sc7180-tcsr", "syscon"; 1659 reg = <0 0x01fc0000 0 0x40000>; 1660 }; 1661 1662 tlmm: pinctrl@3500000 { 1663 compatible = "qcom,sc7180-pinctrl"; 1664 reg = <0 0x03500000 0 0x300000>, 1665 <0 0x03900000 0 0x300000>, 1666 <0 0x03d00000 0 0x300000>; 1667 reg-names = "west", "north", "south"; 1668 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1669 gpio-controller; 1670 #gpio-cells = <2>; 1671 interrupt-controller; 1672 #interrupt-cells = <2>; 1673 gpio-ranges = <&tlmm 0 0 120>; 1674 wakeup-parent = <&pdc>; 1675 1676 dp_hot_plug_det: dp-hot-plug-det-state { 1677 pins = "gpio117"; 1678 function = "dp_hot"; 1679 }; 1680 1681 qspi_clk: qspi-clk-state { 1682 pins = "gpio63"; 1683 function = "qspi_clk"; 1684 }; 1685 1686 qspi_cs0: qspi-cs0-state { 1687 pins = "gpio68"; 1688 function = "qspi_cs"; 1689 }; 1690 1691 qspi_cs1: qspi-cs1-state { 1692 pins = "gpio72"; 1693 function = "qspi_cs"; 1694 }; 1695 1696 qspi_data0: qspi-data0-state { 1697 pins = "gpio64"; 1698 function = "qspi_data"; 1699 }; 1700 1701 qspi_data1: qspi-data1-state { 1702 pins = "gpio65"; 1703 function = "qspi_data"; 1704 }; 1705 1706 qspi_data23: qspi-data23-state { 1707 pins = "gpio66", "gpio67"; 1708 function = "qspi_data"; 1709 }; 1710 1711 qup_i2c0_default: qup-i2c0-default-state { 1712 pins = "gpio34", "gpio35"; 1713 function = "qup00"; 1714 }; 1715 1716 qup_i2c1_default: qup-i2c1-default-state { 1717 pins = "gpio0", "gpio1"; 1718 function = "qup01"; 1719 }; 1720 1721 qup_i2c2_default: qup-i2c2-default-state { 1722 pins = "gpio15", "gpio16"; 1723 function = "qup02_i2c"; 1724 }; 1725 1726 qup_i2c3_default: qup-i2c3-default-state { 1727 pins = "gpio38", "gpio39"; 1728 function = "qup03"; 1729 }; 1730 1731 qup_i2c4_default: qup-i2c4-default-state { 1732 pins = "gpio115", "gpio116"; 1733 function = "qup04_i2c"; 1734 }; 1735 1736 qup_i2c5_default: qup-i2c5-default-state { 1737 pins = "gpio25", "gpio26"; 1738 function = "qup05"; 1739 }; 1740 1741 qup_i2c6_default: qup-i2c6-default-state { 1742 pins = "gpio59", "gpio60"; 1743 function = "qup10"; 1744 }; 1745 1746 qup_i2c7_default: qup-i2c7-default-state { 1747 pins = "gpio6", "gpio7"; 1748 function = "qup11_i2c"; 1749 }; 1750 1751 qup_i2c8_default: qup-i2c8-default-state { 1752 pins = "gpio42", "gpio43"; 1753 function = "qup12"; 1754 }; 1755 1756 qup_i2c9_default: qup-i2c9-default-state { 1757 pins = "gpio46", "gpio47"; 1758 function = "qup13_i2c"; 1759 }; 1760 1761 qup_i2c10_default: qup-i2c10-default-state { 1762 pins = "gpio86", "gpio87"; 1763 function = "qup14"; 1764 }; 1765 1766 qup_i2c11_default: qup-i2c11-default-state { 1767 pins = "gpio53", "gpio54"; 1768 function = "qup15"; 1769 }; 1770 1771 qup_spi0_spi: qup-spi0-spi-state { 1772 pins = "gpio34", "gpio35", "gpio36"; 1773 function = "qup00"; 1774 }; 1775 1776 qup_spi0_cs: qup-spi0-cs-state { 1777 pins = "gpio37"; 1778 function = "qup00"; 1779 }; 1780 1781 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 1782 pins = "gpio37"; 1783 function = "gpio"; 1784 }; 1785 1786 qup_spi1_spi: qup-spi1-spi-state { 1787 pins = "gpio0", "gpio1", "gpio2"; 1788 function = "qup01"; 1789 }; 1790 1791 qup_spi1_cs: qup-spi1-cs-state { 1792 pins = "gpio3"; 1793 function = "qup01"; 1794 }; 1795 1796 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 1797 pins = "gpio3"; 1798 function = "gpio"; 1799 }; 1800 1801 qup_spi3_spi: qup-spi3-spi-state { 1802 pins = "gpio38", "gpio39", "gpio40"; 1803 function = "qup03"; 1804 }; 1805 1806 qup_spi3_cs: qup-spi3-cs-state { 1807 pins = "gpio41"; 1808 function = "qup03"; 1809 }; 1810 1811 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 1812 pins = "gpio41"; 1813 function = "gpio"; 1814 }; 1815 1816 qup_spi5_spi: qup-spi5-spi-state { 1817 pins = "gpio25", "gpio26", "gpio27"; 1818 function = "qup05"; 1819 }; 1820 1821 qup_spi5_cs: qup-spi5-cs-state { 1822 pins = "gpio28"; 1823 function = "qup05"; 1824 }; 1825 1826 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 1827 pins = "gpio28"; 1828 function = "gpio"; 1829 }; 1830 1831 qup_spi6_spi: qup-spi6-spi-state { 1832 pins = "gpio59", "gpio60", "gpio61"; 1833 function = "qup10"; 1834 }; 1835 1836 qup_spi6_cs: qup-spi6-cs-state { 1837 pins = "gpio62"; 1838 function = "qup10"; 1839 }; 1840 1841 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1842 pins = "gpio62"; 1843 function = "gpio"; 1844 }; 1845 1846 qup_spi8_spi: qup-spi8-spi-state { 1847 pins = "gpio42", "gpio43", "gpio44"; 1848 function = "qup12"; 1849 }; 1850 1851 qup_spi8_cs: qup-spi8-cs-state { 1852 pins = "gpio45"; 1853 function = "qup12"; 1854 }; 1855 1856 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 1857 pins = "gpio45"; 1858 function = "gpio"; 1859 }; 1860 1861 qup_spi10_spi: qup-spi10-spi-state { 1862 pins = "gpio86", "gpio87", "gpio88"; 1863 function = "qup14"; 1864 }; 1865 1866 qup_spi10_cs: qup-spi10-cs-state { 1867 pins = "gpio89"; 1868 function = "qup14"; 1869 }; 1870 1871 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 1872 pins = "gpio89"; 1873 function = "gpio"; 1874 }; 1875 1876 qup_spi11_spi: qup-spi11-spi-state { 1877 pins = "gpio53", "gpio54", "gpio55"; 1878 function = "qup15"; 1879 }; 1880 1881 qup_spi11_cs: qup-spi11-cs-state { 1882 pins = "gpio56"; 1883 function = "qup15"; 1884 }; 1885 1886 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 1887 pins = "gpio56"; 1888 function = "gpio"; 1889 }; 1890 1891 qup_uart0_default: qup-uart0-default-state { 1892 qup_uart0_cts: cts-pins { 1893 pins = "gpio34"; 1894 function = "qup00"; 1895 }; 1896 1897 qup_uart0_rts: rts-pins { 1898 pins = "gpio35"; 1899 function = "qup00"; 1900 }; 1901 1902 qup_uart0_tx: tx-pins { 1903 pins = "gpio36"; 1904 function = "qup00"; 1905 }; 1906 1907 qup_uart0_rx: rx-pins { 1908 pins = "gpio37"; 1909 function = "qup00"; 1910 }; 1911 }; 1912 1913 qup_uart1_default: qup-uart1-default-state { 1914 qup_uart1_cts: cts-pins { 1915 pins = "gpio0"; 1916 function = "qup01"; 1917 }; 1918 1919 qup_uart1_rts: rts-pins { 1920 pins = "gpio1"; 1921 function = "qup01"; 1922 }; 1923 1924 qup_uart1_tx: tx-pins { 1925 pins = "gpio2"; 1926 function = "qup01"; 1927 }; 1928 1929 qup_uart1_rx: rx-pins { 1930 pins = "gpio3"; 1931 function = "qup01"; 1932 }; 1933 }; 1934 1935 qup_uart2_default: qup-uart2-default-state { 1936 qup_uart2_tx: tx-pins { 1937 pins = "gpio15"; 1938 function = "qup02_uart"; 1939 }; 1940 1941 qup_uart2_rx: rx-pins { 1942 pins = "gpio16"; 1943 function = "qup02_uart"; 1944 }; 1945 }; 1946 1947 qup_uart3_default: qup-uart3-default-state { 1948 qup_uart3_cts: cts-pins { 1949 pins = "gpio38"; 1950 function = "qup03"; 1951 }; 1952 1953 qup_uart3_rts: rts-pins { 1954 pins = "gpio39"; 1955 function = "qup03"; 1956 }; 1957 1958 qup_uart3_tx: tx-pins { 1959 pins = "gpio40"; 1960 function = "qup03"; 1961 }; 1962 1963 qup_uart3_rx: rx-pins { 1964 pins = "gpio41"; 1965 function = "qup03"; 1966 }; 1967 }; 1968 1969 qup_uart4_default: qup-uart4-default-state { 1970 qup_uart4_tx: tx-pins { 1971 pins = "gpio115"; 1972 function = "qup04_uart"; 1973 }; 1974 1975 qup_uart4_rx: rx-pins { 1976 pins = "gpio116"; 1977 function = "qup04_uart"; 1978 }; 1979 }; 1980 1981 qup_uart5_default: qup-uart5-default-state { 1982 qup_uart5_cts: cts-pins { 1983 pins = "gpio25"; 1984 function = "qup05"; 1985 }; 1986 1987 qup_uart5_rts: rts-pins { 1988 pins = "gpio26"; 1989 function = "qup05"; 1990 }; 1991 1992 qup_uart5_tx: tx-pins { 1993 pins = "gpio27"; 1994 function = "qup05"; 1995 }; 1996 1997 qup_uart5_rx: rx-pins { 1998 pins = "gpio28"; 1999 function = "qup05"; 2000 }; 2001 }; 2002 2003 qup_uart6_default: qup-uart6-default-state { 2004 qup_uart6_cts: cts-pins { 2005 pins = "gpio59"; 2006 function = "qup10"; 2007 }; 2008 2009 qup_uart6_rts: rts-pins { 2010 pins = "gpio60"; 2011 function = "qup10"; 2012 }; 2013 2014 qup_uart6_tx: tx-pins { 2015 pins = "gpio61"; 2016 function = "qup10"; 2017 }; 2018 2019 qup_uart6_rx: rx-pins { 2020 pins = "gpio62"; 2021 function = "qup10"; 2022 }; 2023 }; 2024 2025 qup_uart7_default: qup-uart7-default-state { 2026 qup_uart7_tx: tx-pins { 2027 pins = "gpio6"; 2028 function = "qup11_uart"; 2029 }; 2030 2031 qup_uart7_rx: rx-pins { 2032 pins = "gpio7"; 2033 function = "qup11_uart"; 2034 }; 2035 }; 2036 2037 qup_uart8_default: qup-uart8-default-state { 2038 qup_uart8_tx: tx-pins { 2039 pins = "gpio44"; 2040 function = "qup12"; 2041 }; 2042 2043 qup_uart8_rx: rx-pins { 2044 pins = "gpio45"; 2045 function = "qup12"; 2046 }; 2047 }; 2048 2049 qup_uart9_default: qup-uart9-default-state { 2050 qup_uart9_tx: tx-pins { 2051 pins = "gpio46"; 2052 function = "qup13_uart"; 2053 }; 2054 2055 qup_uart9_rx: rx-pins { 2056 pins = "gpio47"; 2057 function = "qup13_uart"; 2058 }; 2059 }; 2060 2061 qup_uart10_default: qup-uart10-default-state { 2062 qup_uart10_cts: cts-pins { 2063 pins = "gpio86"; 2064 function = "qup14"; 2065 }; 2066 2067 qup_uart10_rts: rts-pins { 2068 pins = "gpio87"; 2069 function = "qup14"; 2070 }; 2071 2072 qup_uart10_tx: tx-pins { 2073 pins = "gpio88"; 2074 function = "qup14"; 2075 }; 2076 2077 qup_uart10_rx: rx-pins { 2078 pins = "gpio89"; 2079 function = "qup14"; 2080 }; 2081 }; 2082 2083 qup_uart11_default: qup-uart11-default-state { 2084 qup_uart11_cts: cts-pins { 2085 pins = "gpio53"; 2086 function = "qup15"; 2087 }; 2088 2089 qup_uart11_rts: rts-pins { 2090 pins = "gpio54"; 2091 function = "qup15"; 2092 }; 2093 2094 qup_uart11_tx: tx-pins { 2095 pins = "gpio55"; 2096 function = "qup15"; 2097 }; 2098 2099 qup_uart11_rx: rx-pins { 2100 pins = "gpio56"; 2101 function = "qup15"; 2102 }; 2103 }; 2104 2105 sec_mi2s_active: sec-mi2s-active-state { 2106 pins = "gpio49", "gpio50", "gpio51"; 2107 function = "mi2s_1"; 2108 }; 2109 2110 pri_mi2s_active: pri-mi2s-active-state { 2111 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 2112 function = "mi2s_0"; 2113 }; 2114 2115 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state { 2116 pins = "gpio57"; 2117 function = "lpass_ext"; 2118 }; 2119 2120 ter_mi2s_active: ter-mi2s-active-state { 2121 pins = "gpio63", "gpio64", "gpio65", "gpio66"; 2122 function = "mi2s_2"; 2123 }; 2124 }; 2125 2126 remoteproc_mpss: remoteproc@4080000 { 2127 compatible = "qcom,sc7180-mpss-pas"; 2128 reg = <0 0x04080000 0 0x4040>; 2129 2130 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2131 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2132 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2133 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2134 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2135 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2136 interrupt-names = "wdog", "fatal", "ready", "handover", 2137 "stop-ack", "shutdown-ack"; 2138 2139 clocks = <&rpmhcc RPMH_CXO_CLK>; 2140 clock-names = "xo"; 2141 2142 power-domains = <&rpmhpd SC7180_CX>, 2143 <&rpmhpd SC7180_MX>, 2144 <&rpmhpd SC7180_MSS>; 2145 power-domain-names = "cx", "mx", "mss"; 2146 2147 memory-region = <&mpss_mem>; 2148 2149 qcom,qmp = <&aoss_qmp>; 2150 2151 qcom,smem-states = <&modem_smp2p_out 0>; 2152 qcom,smem-state-names = "stop"; 2153 2154 status = "disabled"; 2155 2156 glink-edge { 2157 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2158 label = "modem"; 2159 qcom,remote-pid = <1>; 2160 mboxes = <&apss_shared 12>; 2161 }; 2162 }; 2163 2164 gpu: gpu@5000000 { 2165 compatible = "qcom,adreno-618.0", "qcom,adreno"; 2166 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 2167 <0 0x05061000 0 0x800>; 2168 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 2169 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2170 iommus = <&adreno_smmu 0>; 2171 operating-points-v2 = <&gpu_opp_table>; 2172 qcom,gmu = <&gmu>; 2173 2174 #cooling-cells = <2>; 2175 2176 nvmem-cells = <&gpu_speed_bin>; 2177 nvmem-cell-names = "speed_bin"; 2178 2179 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2180 interconnect-names = "gfx-mem"; 2181 2182 gpu_opp_table: opp-table { 2183 compatible = "operating-points-v2"; 2184 2185 opp-825000000 { 2186 opp-hz = /bits/ 64 <825000000>; 2187 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2188 opp-peak-kBps = <8532000>; 2189 opp-supported-hw = <0x04>; 2190 }; 2191 2192 opp-800000000 { 2193 opp-hz = /bits/ 64 <800000000>; 2194 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2195 opp-peak-kBps = <8532000>; 2196 opp-supported-hw = <0x07>; 2197 }; 2198 2199 opp-650000000 { 2200 opp-hz = /bits/ 64 <650000000>; 2201 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2202 opp-peak-kBps = <7216000>; 2203 opp-supported-hw = <0x07>; 2204 }; 2205 2206 opp-565000000 { 2207 opp-hz = /bits/ 64 <565000000>; 2208 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2209 opp-peak-kBps = <5412000>; 2210 opp-supported-hw = <0x07>; 2211 }; 2212 2213 opp-430000000 { 2214 opp-hz = /bits/ 64 <430000000>; 2215 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2216 opp-peak-kBps = <5412000>; 2217 opp-supported-hw = <0x07>; 2218 }; 2219 2220 opp-355000000 { 2221 opp-hz = /bits/ 64 <355000000>; 2222 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2223 opp-peak-kBps = <3072000>; 2224 opp-supported-hw = <0x07>; 2225 }; 2226 2227 opp-267000000 { 2228 opp-hz = /bits/ 64 <267000000>; 2229 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2230 opp-peak-kBps = <3072000>; 2231 opp-supported-hw = <0x07>; 2232 }; 2233 2234 opp-180000000 { 2235 opp-hz = /bits/ 64 <180000000>; 2236 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2237 opp-peak-kBps = <1804000>; 2238 opp-supported-hw = <0x07>; 2239 }; 2240 }; 2241 }; 2242 2243 adreno_smmu: iommu@5040000 { 2244 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2245 reg = <0 0x05040000 0 0x10000>; 2246 #iommu-cells = <1>; 2247 #global-interrupts = <2>; 2248 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2249 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2251 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2252 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2253 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2254 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2255 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2256 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2257 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2258 2259 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2260 <&gcc GCC_GPU_CFG_AHB_CLK>; 2261 clock-names = "bus", "iface"; 2262 2263 power-domains = <&gpucc CX_GDSC>; 2264 }; 2265 2266 gmu: gmu@506a000 { 2267 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2268 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2269 <0 0x0b490000 0 0x10000>; 2270 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2271 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2272 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2273 interrupt-names = "hfi", "gmu"; 2274 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2275 <&gpucc GPU_CC_CXO_CLK>, 2276 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2277 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2278 clock-names = "gmu", "cxo", "axi", "memnoc"; 2279 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2280 power-domain-names = "cx", "gx"; 2281 iommus = <&adreno_smmu 5>; 2282 operating-points-v2 = <&gmu_opp_table>; 2283 2284 gmu_opp_table: opp-table { 2285 compatible = "operating-points-v2"; 2286 2287 opp-200000000 { 2288 opp-hz = /bits/ 64 <200000000>; 2289 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2290 }; 2291 }; 2292 }; 2293 2294 gpucc: clock-controller@5090000 { 2295 compatible = "qcom,sc7180-gpucc"; 2296 reg = <0 0x05090000 0 0x9000>; 2297 clocks = <&rpmhcc RPMH_CXO_CLK>, 2298 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2299 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2300 clock-names = "bi_tcxo", 2301 "gcc_gpu_gpll0_clk_src", 2302 "gcc_gpu_gpll0_div_clk_src"; 2303 #clock-cells = <1>; 2304 #reset-cells = <1>; 2305 #power-domain-cells = <1>; 2306 }; 2307 2308 dma@10a2000 { 2309 compatible = "qcom,sc7180-dcc", "qcom,dcc"; 2310 reg = <0x0 0x010a2000 0x0 0x1000>, 2311 <0x0 0x010ae000 0x0 0x2000>; 2312 status = "disabled"; 2313 }; 2314 2315 stm@6002000 { 2316 compatible = "arm,coresight-stm", "arm,primecell"; 2317 reg = <0 0x06002000 0 0x1000>, 2318 <0 0x16280000 0 0x180000>; 2319 reg-names = "stm-base", "stm-stimulus-base"; 2320 2321 clocks = <&aoss_qmp>; 2322 clock-names = "apb_pclk"; 2323 2324 out-ports { 2325 port { 2326 stm_out: endpoint { 2327 remote-endpoint = <&funnel0_in7>; 2328 }; 2329 }; 2330 }; 2331 }; 2332 2333 funnel@6041000 { 2334 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2335 reg = <0 0x06041000 0 0x1000>; 2336 2337 clocks = <&aoss_qmp>; 2338 clock-names = "apb_pclk"; 2339 2340 out-ports { 2341 port { 2342 funnel0_out: endpoint { 2343 remote-endpoint = <&merge_funnel_in0>; 2344 }; 2345 }; 2346 }; 2347 2348 in-ports { 2349 #address-cells = <1>; 2350 #size-cells = <0>; 2351 2352 port@7 { 2353 reg = <7>; 2354 funnel0_in7: endpoint { 2355 remote-endpoint = <&stm_out>; 2356 }; 2357 }; 2358 }; 2359 }; 2360 2361 funnel@6042000 { 2362 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2363 reg = <0 0x06042000 0 0x1000>; 2364 2365 clocks = <&aoss_qmp>; 2366 clock-names = "apb_pclk"; 2367 2368 out-ports { 2369 port { 2370 funnel1_out: endpoint { 2371 remote-endpoint = <&merge_funnel_in1>; 2372 }; 2373 }; 2374 }; 2375 2376 in-ports { 2377 #address-cells = <1>; 2378 #size-cells = <0>; 2379 2380 port@4 { 2381 reg = <4>; 2382 funnel1_in4: endpoint { 2383 remote-endpoint = <&apss_merge_funnel_out>; 2384 }; 2385 }; 2386 }; 2387 }; 2388 2389 funnel@6045000 { 2390 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2391 reg = <0 0x06045000 0 0x1000>; 2392 2393 clocks = <&aoss_qmp>; 2394 clock-names = "apb_pclk"; 2395 2396 out-ports { 2397 port { 2398 merge_funnel_out: endpoint { 2399 remote-endpoint = <&swao_funnel_in>; 2400 }; 2401 }; 2402 }; 2403 2404 in-ports { 2405 #address-cells = <1>; 2406 #size-cells = <0>; 2407 2408 port@0 { 2409 reg = <0>; 2410 merge_funnel_in0: endpoint { 2411 remote-endpoint = <&funnel0_out>; 2412 }; 2413 }; 2414 2415 port@1 { 2416 reg = <1>; 2417 merge_funnel_in1: endpoint { 2418 remote-endpoint = <&funnel1_out>; 2419 }; 2420 }; 2421 }; 2422 }; 2423 2424 replicator@6046000 { 2425 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2426 reg = <0 0x06046000 0 0x1000>; 2427 2428 clocks = <&aoss_qmp>; 2429 clock-names = "apb_pclk"; 2430 2431 out-ports { 2432 port { 2433 replicator_out: endpoint { 2434 remote-endpoint = <&etr_in>; 2435 }; 2436 }; 2437 }; 2438 2439 in-ports { 2440 port { 2441 replicator_in: endpoint { 2442 remote-endpoint = <&swao_replicator_out>; 2443 }; 2444 }; 2445 }; 2446 }; 2447 2448 etr@6048000 { 2449 compatible = "arm,coresight-tmc", "arm,primecell"; 2450 reg = <0 0x06048000 0 0x1000>; 2451 iommus = <&apps_smmu 0x04a0 0x20>; 2452 2453 clocks = <&aoss_qmp>; 2454 clock-names = "apb_pclk"; 2455 arm,scatter-gather; 2456 2457 in-ports { 2458 port { 2459 etr_in: endpoint { 2460 remote-endpoint = <&replicator_out>; 2461 }; 2462 }; 2463 }; 2464 }; 2465 2466 funnel@6b04000 { 2467 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2468 reg = <0 0x06b04000 0 0x1000>; 2469 2470 clocks = <&aoss_qmp>; 2471 clock-names = "apb_pclk"; 2472 2473 out-ports { 2474 port { 2475 swao_funnel_out: endpoint { 2476 remote-endpoint = <&etf_in>; 2477 }; 2478 }; 2479 }; 2480 2481 in-ports { 2482 #address-cells = <1>; 2483 #size-cells = <0>; 2484 2485 port@7 { 2486 reg = <7>; 2487 swao_funnel_in: endpoint { 2488 remote-endpoint = <&merge_funnel_out>; 2489 }; 2490 }; 2491 }; 2492 }; 2493 2494 etf@6b05000 { 2495 compatible = "arm,coresight-tmc", "arm,primecell"; 2496 reg = <0 0x06b05000 0 0x1000>; 2497 2498 clocks = <&aoss_qmp>; 2499 clock-names = "apb_pclk"; 2500 2501 out-ports { 2502 port { 2503 etf_out: endpoint { 2504 remote-endpoint = <&swao_replicator_in>; 2505 }; 2506 }; 2507 }; 2508 2509 in-ports { 2510 port { 2511 etf_in: endpoint { 2512 remote-endpoint = <&swao_funnel_out>; 2513 }; 2514 }; 2515 }; 2516 }; 2517 2518 replicator@6b06000 { 2519 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2520 reg = <0 0x06b06000 0 0x1000>; 2521 2522 clocks = <&aoss_qmp>; 2523 clock-names = "apb_pclk"; 2524 qcom,replicator-loses-context; 2525 2526 out-ports { 2527 port { 2528 swao_replicator_out: endpoint { 2529 remote-endpoint = <&replicator_in>; 2530 }; 2531 }; 2532 }; 2533 2534 in-ports { 2535 port { 2536 swao_replicator_in: endpoint { 2537 remote-endpoint = <&etf_out>; 2538 }; 2539 }; 2540 }; 2541 }; 2542 2543 etm@7040000 { 2544 compatible = "arm,coresight-etm4x", "arm,primecell"; 2545 reg = <0 0x07040000 0 0x1000>; 2546 2547 cpu = <&cpu0>; 2548 2549 clocks = <&aoss_qmp>; 2550 clock-names = "apb_pclk"; 2551 arm,coresight-loses-context-with-cpu; 2552 qcom,skip-power-up; 2553 2554 out-ports { 2555 port { 2556 etm0_out: endpoint { 2557 remote-endpoint = <&apss_funnel_in0>; 2558 }; 2559 }; 2560 }; 2561 }; 2562 2563 etm@7140000 { 2564 compatible = "arm,coresight-etm4x", "arm,primecell"; 2565 reg = <0 0x07140000 0 0x1000>; 2566 2567 cpu = <&cpu1>; 2568 2569 clocks = <&aoss_qmp>; 2570 clock-names = "apb_pclk"; 2571 arm,coresight-loses-context-with-cpu; 2572 qcom,skip-power-up; 2573 2574 out-ports { 2575 port { 2576 etm1_out: endpoint { 2577 remote-endpoint = <&apss_funnel_in1>; 2578 }; 2579 }; 2580 }; 2581 }; 2582 2583 etm@7240000 { 2584 compatible = "arm,coresight-etm4x", "arm,primecell"; 2585 reg = <0 0x07240000 0 0x1000>; 2586 2587 cpu = <&cpu2>; 2588 2589 clocks = <&aoss_qmp>; 2590 clock-names = "apb_pclk"; 2591 arm,coresight-loses-context-with-cpu; 2592 qcom,skip-power-up; 2593 2594 out-ports { 2595 port { 2596 etm2_out: endpoint { 2597 remote-endpoint = <&apss_funnel_in2>; 2598 }; 2599 }; 2600 }; 2601 }; 2602 2603 etm@7340000 { 2604 compatible = "arm,coresight-etm4x", "arm,primecell"; 2605 reg = <0 0x07340000 0 0x1000>; 2606 2607 cpu = <&cpu3>; 2608 2609 clocks = <&aoss_qmp>; 2610 clock-names = "apb_pclk"; 2611 arm,coresight-loses-context-with-cpu; 2612 qcom,skip-power-up; 2613 2614 out-ports { 2615 port { 2616 etm3_out: endpoint { 2617 remote-endpoint = <&apss_funnel_in3>; 2618 }; 2619 }; 2620 }; 2621 }; 2622 2623 etm@7440000 { 2624 compatible = "arm,coresight-etm4x", "arm,primecell"; 2625 reg = <0 0x07440000 0 0x1000>; 2626 2627 cpu = <&cpu4>; 2628 2629 clocks = <&aoss_qmp>; 2630 clock-names = "apb_pclk"; 2631 arm,coresight-loses-context-with-cpu; 2632 qcom,skip-power-up; 2633 2634 out-ports { 2635 port { 2636 etm4_out: endpoint { 2637 remote-endpoint = <&apss_funnel_in4>; 2638 }; 2639 }; 2640 }; 2641 }; 2642 2643 etm@7540000 { 2644 compatible = "arm,coresight-etm4x", "arm,primecell"; 2645 reg = <0 0x07540000 0 0x1000>; 2646 2647 cpu = <&cpu5>; 2648 2649 clocks = <&aoss_qmp>; 2650 clock-names = "apb_pclk"; 2651 arm,coresight-loses-context-with-cpu; 2652 qcom,skip-power-up; 2653 2654 out-ports { 2655 port { 2656 etm5_out: endpoint { 2657 remote-endpoint = <&apss_funnel_in5>; 2658 }; 2659 }; 2660 }; 2661 }; 2662 2663 etm@7640000 { 2664 compatible = "arm,coresight-etm4x", "arm,primecell"; 2665 reg = <0 0x07640000 0 0x1000>; 2666 2667 cpu = <&cpu6>; 2668 2669 clocks = <&aoss_qmp>; 2670 clock-names = "apb_pclk"; 2671 arm,coresight-loses-context-with-cpu; 2672 qcom,skip-power-up; 2673 2674 out-ports { 2675 port { 2676 etm6_out: endpoint { 2677 remote-endpoint = <&apss_funnel_in6>; 2678 }; 2679 }; 2680 }; 2681 }; 2682 2683 etm@7740000 { 2684 compatible = "arm,coresight-etm4x", "arm,primecell"; 2685 reg = <0 0x07740000 0 0x1000>; 2686 2687 cpu = <&cpu7>; 2688 2689 clocks = <&aoss_qmp>; 2690 clock-names = "apb_pclk"; 2691 arm,coresight-loses-context-with-cpu; 2692 qcom,skip-power-up; 2693 2694 out-ports { 2695 port { 2696 etm7_out: endpoint { 2697 remote-endpoint = <&apss_funnel_in7>; 2698 }; 2699 }; 2700 }; 2701 }; 2702 2703 funnel@7800000 { /* APSS Funnel */ 2704 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2705 reg = <0 0x07800000 0 0x1000>; 2706 2707 clocks = <&aoss_qmp>; 2708 clock-names = "apb_pclk"; 2709 2710 out-ports { 2711 port { 2712 apss_funnel_out: endpoint { 2713 remote-endpoint = <&apss_merge_funnel_in>; 2714 }; 2715 }; 2716 }; 2717 2718 in-ports { 2719 #address-cells = <1>; 2720 #size-cells = <0>; 2721 2722 port@0 { 2723 reg = <0>; 2724 apss_funnel_in0: endpoint { 2725 remote-endpoint = <&etm0_out>; 2726 }; 2727 }; 2728 2729 port@1 { 2730 reg = <1>; 2731 apss_funnel_in1: endpoint { 2732 remote-endpoint = <&etm1_out>; 2733 }; 2734 }; 2735 2736 port@2 { 2737 reg = <2>; 2738 apss_funnel_in2: endpoint { 2739 remote-endpoint = <&etm2_out>; 2740 }; 2741 }; 2742 2743 port@3 { 2744 reg = <3>; 2745 apss_funnel_in3: endpoint { 2746 remote-endpoint = <&etm3_out>; 2747 }; 2748 }; 2749 2750 port@4 { 2751 reg = <4>; 2752 apss_funnel_in4: endpoint { 2753 remote-endpoint = <&etm4_out>; 2754 }; 2755 }; 2756 2757 port@5 { 2758 reg = <5>; 2759 apss_funnel_in5: endpoint { 2760 remote-endpoint = <&etm5_out>; 2761 }; 2762 }; 2763 2764 port@6 { 2765 reg = <6>; 2766 apss_funnel_in6: endpoint { 2767 remote-endpoint = <&etm6_out>; 2768 }; 2769 }; 2770 2771 port@7 { 2772 reg = <7>; 2773 apss_funnel_in7: endpoint { 2774 remote-endpoint = <&etm7_out>; 2775 }; 2776 }; 2777 }; 2778 }; 2779 2780 funnel@7810000 { 2781 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2782 reg = <0 0x07810000 0 0x1000>; 2783 2784 clocks = <&aoss_qmp>; 2785 clock-names = "apb_pclk"; 2786 2787 out-ports { 2788 port { 2789 apss_merge_funnel_out: endpoint { 2790 remote-endpoint = <&funnel1_in4>; 2791 }; 2792 }; 2793 }; 2794 2795 in-ports { 2796 port { 2797 apss_merge_funnel_in: endpoint { 2798 remote-endpoint = <&apss_funnel_out>; 2799 }; 2800 }; 2801 }; 2802 }; 2803 2804 sdhc_2: mmc@8804000 { 2805 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2806 reg = <0 0x08804000 0 0x1000>; 2807 2808 iommus = <&apps_smmu 0x80 0>; 2809 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2810 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2811 interrupt-names = "hc_irq", "pwr_irq"; 2812 2813 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2814 <&gcc GCC_SDCC2_APPS_CLK>, 2815 <&rpmhcc RPMH_CXO_CLK>; 2816 clock-names = "iface", "core", "xo"; 2817 2818 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2819 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2820 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2821 power-domains = <&rpmhpd SC7180_CX>; 2822 operating-points-v2 = <&sdhc2_opp_table>; 2823 2824 bus-width = <4>; 2825 2826 status = "disabled"; 2827 2828 sdhc2_opp_table: opp-table { 2829 compatible = "operating-points-v2"; 2830 2831 opp-100000000 { 2832 opp-hz = /bits/ 64 <100000000>; 2833 required-opps = <&rpmhpd_opp_low_svs>; 2834 opp-peak-kBps = <1800000 600000>; 2835 opp-avg-kBps = <100000 0>; 2836 }; 2837 2838 opp-202000000 { 2839 opp-hz = /bits/ 64 <202000000>; 2840 required-opps = <&rpmhpd_opp_nom>; 2841 opp-peak-kBps = <5400000 1600000>; 2842 opp-avg-kBps = <200000 0>; 2843 }; 2844 }; 2845 }; 2846 2847 qspi: spi@88dc000 { 2848 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; 2849 reg = <0 0x088dc000 0 0x600>; 2850 iommus = <&apps_smmu 0x20 0x0>; 2851 #address-cells = <1>; 2852 #size-cells = <0>; 2853 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2854 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2855 <&gcc GCC_QSPI_CORE_CLK>; 2856 clock-names = "iface", "core"; 2857 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2858 &config_noc SLAVE_QSPI_0 0>; 2859 interconnect-names = "qspi-config"; 2860 power-domains = <&rpmhpd SC7180_CX>; 2861 operating-points-v2 = <&qspi_opp_table>; 2862 status = "disabled"; 2863 }; 2864 2865 usb_1_hsphy: phy@88e3000 { 2866 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2867 reg = <0 0x088e3000 0 0x400>; 2868 status = "disabled"; 2869 #phy-cells = <0>; 2870 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2871 <&rpmhcc RPMH_CXO_CLK>; 2872 clock-names = "cfg_ahb", "ref"; 2873 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2874 2875 nvmem-cells = <&qusb2p_hstx_trim>; 2876 }; 2877 2878 usb_1_qmpphy: phy@88e8000 { 2879 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2880 reg = <0 0x088e8000 0 0x3000>; 2881 status = "disabled"; 2882 2883 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2884 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2885 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2886 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, 2887 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 2888 clock-names = "aux", 2889 "ref", 2890 "com_aux", 2891 "usb3_pipe", 2892 "cfg_ahb"; 2893 2894 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2895 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2896 reset-names = "phy", "common"; 2897 2898 #clock-cells = <1>; 2899 #phy-cells = <1>; 2900 2901 ports { 2902 #address-cells = <1>; 2903 #size-cells = <0>; 2904 2905 port@0 { 2906 reg = <0>; 2907 2908 usb_1_qmpphy_out: endpoint { }; 2909 }; 2910 2911 port@1 { 2912 reg = <1>; 2913 2914 usb_1_qmpphy_usb_ss_in: endpoint { 2915 remote-endpoint = <&usb_1_dwc3_ss>; 2916 }; 2917 }; 2918 2919 port@2 { 2920 reg = <2>; 2921 2922 usb_1_qmpphy_dp_in: endpoint { }; 2923 }; 2924 }; 2925 }; 2926 2927 pmu@90b6300 { 2928 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon"; 2929 reg = <0 0x090b6300 0 0x600>; 2930 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2931 2932 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2933 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 2934 operating-points-v2 = <&cpu_bwmon_opp_table>; 2935 2936 cpu_bwmon_opp_table: opp-table { 2937 compatible = "operating-points-v2"; 2938 2939 opp-0 { 2940 opp-peak-kBps = <2288000>; 2941 }; 2942 2943 opp-1 { 2944 opp-peak-kBps = <4577000>; 2945 }; 2946 2947 opp-2 { 2948 opp-peak-kBps = <7110000>; 2949 }; 2950 2951 opp-3 { 2952 opp-peak-kBps = <9155000>; 2953 }; 2954 2955 opp-4 { 2956 opp-peak-kBps = <12298000>; 2957 }; 2958 2959 opp-5 { 2960 opp-peak-kBps = <14236000>; 2961 }; 2962 }; 2963 }; 2964 2965 pmu@90cd000 { 2966 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 2967 reg = <0 0x090cd000 0 0x1000>; 2968 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 2969 2970 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 2971 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2972 operating-points-v2 = <&llcc_bwmon_opp_table>; 2973 2974 llcc_bwmon_opp_table: opp-table { 2975 compatible = "operating-points-v2"; 2976 2977 opp-0 { 2978 opp-peak-kBps = <1144000>; 2979 }; 2980 2981 opp-1 { 2982 opp-peak-kBps = <1720000>; 2983 }; 2984 2985 opp-2 { 2986 opp-peak-kBps = <2086000>; 2987 }; 2988 2989 opp-3 { 2990 opp-peak-kBps = <2929000>; 2991 }; 2992 2993 opp-4 { 2994 opp-peak-kBps = <3879000>; 2995 }; 2996 2997 opp-5 { 2998 opp-peak-kBps = <5931000>; 2999 }; 3000 3001 opp-6 { 3002 opp-peak-kBps = <6881000>; 3003 }; 3004 3005 opp-7 { 3006 opp-peak-kBps = <8137000>; 3007 }; 3008 }; 3009 }; 3010 3011 dc_noc: interconnect@9160000 { 3012 compatible = "qcom,sc7180-dc-noc"; 3013 reg = <0 0x09160000 0 0x03200>; 3014 #interconnect-cells = <2>; 3015 qcom,bcm-voters = <&apps_bcm_voter>; 3016 }; 3017 3018 system-cache-controller@9200000 { 3019 compatible = "qcom,sc7180-llcc"; 3020 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 3021 reg-names = "llcc0_base", "llcc_broadcast_base"; 3022 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3023 }; 3024 3025 gem_noc: interconnect@9680000 { 3026 compatible = "qcom,sc7180-gem-noc"; 3027 reg = <0 0x09680000 0 0x3e200>; 3028 #interconnect-cells = <2>; 3029 qcom,bcm-voters = <&apps_bcm_voter>; 3030 }; 3031 3032 npu_noc: interconnect@9990000 { 3033 compatible = "qcom,sc7180-npu-noc"; 3034 reg = <0 0x09990000 0 0x1600>; 3035 #interconnect-cells = <2>; 3036 qcom,bcm-voters = <&apps_bcm_voter>; 3037 }; 3038 3039 usb_1: usb@a6f8800 { 3040 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 3041 reg = <0 0x0a6f8800 0 0x400>; 3042 status = "disabled"; 3043 #address-cells = <2>; 3044 #size-cells = <2>; 3045 ranges; 3046 dma-ranges; 3047 3048 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3049 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3050 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3051 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3052 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3053 clock-names = "cfg_noc", 3054 "core", 3055 "iface", 3056 "sleep", 3057 "mock_utmi"; 3058 3059 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3060 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3061 assigned-clock-rates = <19200000>, <150000000>; 3062 3063 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3064 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3065 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 3066 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3067 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 3068 interrupt-names = "pwr_event", 3069 "hs_phy_irq", 3070 "dp_hs_phy_irq", 3071 "dm_hs_phy_irq", 3072 "ss_phy_irq"; 3073 3074 power-domains = <&gcc USB30_PRIM_GDSC>; 3075 required-opps = <&rpmhpd_opp_nom>; 3076 3077 resets = <&gcc GCC_USB30_PRIM_BCR>; 3078 3079 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 3080 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 3081 interconnect-names = "usb-ddr", "apps-usb"; 3082 3083 wakeup-source; 3084 3085 usb_1_dwc3: usb@a600000 { 3086 compatible = "snps,dwc3"; 3087 reg = <0 0x0a600000 0 0xe000>; 3088 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3089 iommus = <&apps_smmu 0x540 0>; 3090 snps,dis_u2_susphy_quirk; 3091 snps,dis_enblslpm_quirk; 3092 snps,parkmode-disable-ss-quirk; 3093 snps,dis-u1-entry-quirk; 3094 snps,dis-u2-entry-quirk; 3095 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3096 phy-names = "usb2-phy", "usb3-phy"; 3097 maximum-speed = "super-speed"; 3098 3099 ports { 3100 #address-cells = <1>; 3101 #size-cells = <0>; 3102 3103 port@0 { 3104 reg = <0>; 3105 3106 usb_1_dwc3_hs: endpoint { 3107 }; 3108 }; 3109 3110 port@1 { 3111 reg = <1>; 3112 3113 usb_1_dwc3_ss: endpoint { 3114 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 3115 }; 3116 }; 3117 }; 3118 }; 3119 }; 3120 3121 venus: video-codec@aa00000 { 3122 compatible = "qcom,sc7180-venus"; 3123 reg = <0 0x0aa00000 0 0xff000>; 3124 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3125 power-domains = <&videocc VENUS_GDSC>, 3126 <&videocc VCODEC0_GDSC>, 3127 <&rpmhpd SC7180_CX>; 3128 power-domain-names = "venus", "vcodec0", "cx"; 3129 operating-points-v2 = <&venus_opp_table>; 3130 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3131 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3132 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3133 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3134 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 3135 clock-names = "core", "iface", "bus", 3136 "vcodec0_core", "vcodec0_bus"; 3137 iommus = <&apps_smmu 0x0c00 0x60>; 3138 memory-region = <&venus_mem>; 3139 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 3140 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 3141 interconnect-names = "video-mem", "cpu-cfg"; 3142 3143 venus_opp_table: opp-table { 3144 compatible = "operating-points-v2"; 3145 3146 opp-150000000 { 3147 opp-hz = /bits/ 64 <150000000>; 3148 required-opps = <&rpmhpd_opp_low_svs>; 3149 }; 3150 3151 opp-270000000 { 3152 opp-hz = /bits/ 64 <270000000>; 3153 required-opps = <&rpmhpd_opp_svs>; 3154 }; 3155 3156 opp-340000000 { 3157 opp-hz = /bits/ 64 <340000000>; 3158 required-opps = <&rpmhpd_opp_svs_l1>; 3159 }; 3160 3161 opp-434000000 { 3162 opp-hz = /bits/ 64 <434000000>; 3163 required-opps = <&rpmhpd_opp_nom>; 3164 }; 3165 3166 opp-500000097 { 3167 opp-hz = /bits/ 64 <500000097>; 3168 required-opps = <&rpmhpd_opp_turbo>; 3169 }; 3170 }; 3171 }; 3172 3173 videocc: clock-controller@ab00000 { 3174 compatible = "qcom,sc7180-videocc"; 3175 reg = <0 0x0ab00000 0 0x10000>; 3176 clocks = <&rpmhcc RPMH_CXO_CLK>; 3177 clock-names = "bi_tcxo"; 3178 #clock-cells = <1>; 3179 #reset-cells = <1>; 3180 #power-domain-cells = <1>; 3181 }; 3182 3183 camnoc_virt: interconnect@ac00000 { 3184 compatible = "qcom,sc7180-camnoc-virt"; 3185 reg = <0 0x0ac00000 0 0x1000>; 3186 #interconnect-cells = <2>; 3187 qcom,bcm-voters = <&apps_bcm_voter>; 3188 }; 3189 3190 camcc: clock-controller@ad00000 { 3191 compatible = "qcom,sc7180-camcc"; 3192 reg = <0 0x0ad00000 0 0x10000>; 3193 clocks = <&rpmhcc RPMH_CXO_CLK>, 3194 <&gcc GCC_CAMERA_AHB_CLK>, 3195 <&gcc GCC_CAMERA_XO_CLK>; 3196 clock-names = "bi_tcxo", "iface", "xo"; 3197 #clock-cells = <1>; 3198 #reset-cells = <1>; 3199 #power-domain-cells = <1>; 3200 }; 3201 3202 mdss: display-subsystem@ae00000 { 3203 compatible = "qcom,sc7180-mdss"; 3204 reg = <0 0x0ae00000 0 0x1000>; 3205 reg-names = "mdss"; 3206 3207 power-domains = <&dispcc MDSS_GDSC>; 3208 3209 clocks = <&gcc GCC_DISP_AHB_CLK>, 3210 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3211 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3212 clock-names = "iface", "ahb", "core"; 3213 3214 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3215 interrupt-controller; 3216 #interrupt-cells = <1>; 3217 3218 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 3219 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3220 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3221 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 3222 interconnect-names = "mdp0-mem", 3223 "cpu-cfg"; 3224 3225 iommus = <&apps_smmu 0x800 0x2>; 3226 3227 #address-cells = <2>; 3228 #size-cells = <2>; 3229 ranges; 3230 3231 status = "disabled"; 3232 3233 mdp: display-controller@ae01000 { 3234 compatible = "qcom,sc7180-dpu"; 3235 reg = <0 0x0ae01000 0 0x8f000>, 3236 <0 0x0aeb0000 0 0x3000>; 3237 reg-names = "mdp", "vbif"; 3238 3239 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3240 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3241 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3242 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3243 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3244 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3245 clock-names = "bus", "iface", "rot", "lut", "core", 3246 "vsync"; 3247 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3248 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3249 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3250 assigned-clock-rates = <19200000>, 3251 <19200000>, 3252 <19200000>; 3253 operating-points-v2 = <&mdp_opp_table>; 3254 power-domains = <&rpmhpd SC7180_CX>; 3255 3256 interrupt-parent = <&mdss>; 3257 interrupts = <0>; 3258 3259 ports { 3260 #address-cells = <1>; 3261 #size-cells = <0>; 3262 3263 port@0 { 3264 reg = <0>; 3265 dpu_intf1_out: endpoint { 3266 remote-endpoint = <&mdss_dsi0_in>; 3267 }; 3268 }; 3269 3270 port@2 { 3271 reg = <2>; 3272 dpu_intf0_out: endpoint { 3273 remote-endpoint = <&dp_in>; 3274 }; 3275 }; 3276 }; 3277 3278 mdp_opp_table: opp-table { 3279 compatible = "operating-points-v2"; 3280 3281 opp-200000000 { 3282 opp-hz = /bits/ 64 <200000000>; 3283 required-opps = <&rpmhpd_opp_low_svs>; 3284 }; 3285 3286 opp-300000000 { 3287 opp-hz = /bits/ 64 <300000000>; 3288 required-opps = <&rpmhpd_opp_svs>; 3289 }; 3290 3291 opp-345000000 { 3292 opp-hz = /bits/ 64 <345000000>; 3293 required-opps = <&rpmhpd_opp_svs_l1>; 3294 }; 3295 3296 opp-460000000 { 3297 opp-hz = /bits/ 64 <460000000>; 3298 required-opps = <&rpmhpd_opp_nom>; 3299 }; 3300 }; 3301 }; 3302 3303 mdss_dsi0: dsi@ae94000 { 3304 compatible = "qcom,sc7180-dsi-ctrl", 3305 "qcom,mdss-dsi-ctrl"; 3306 reg = <0 0x0ae94000 0 0x400>; 3307 reg-names = "dsi_ctrl"; 3308 3309 interrupt-parent = <&mdss>; 3310 interrupts = <4>; 3311 3312 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3313 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3314 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3315 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3316 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3317 <&gcc GCC_DISP_HF_AXI_CLK>; 3318 clock-names = "byte", 3319 "byte_intf", 3320 "pixel", 3321 "core", 3322 "iface", 3323 "bus"; 3324 3325 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3326 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3327 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3328 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3329 3330 operating-points-v2 = <&dsi_opp_table>; 3331 power-domains = <&rpmhpd SC7180_CX>; 3332 3333 phys = <&mdss_dsi0_phy>; 3334 3335 #address-cells = <1>; 3336 #size-cells = <0>; 3337 3338 status = "disabled"; 3339 3340 ports { 3341 #address-cells = <1>; 3342 #size-cells = <0>; 3343 3344 port@0 { 3345 reg = <0>; 3346 mdss_dsi0_in: endpoint { 3347 remote-endpoint = <&dpu_intf1_out>; 3348 }; 3349 }; 3350 3351 port@1 { 3352 reg = <1>; 3353 mdss_dsi0_out: endpoint { 3354 }; 3355 }; 3356 }; 3357 3358 dsi_opp_table: opp-table { 3359 compatible = "operating-points-v2"; 3360 3361 opp-187500000 { 3362 opp-hz = /bits/ 64 <187500000>; 3363 required-opps = <&rpmhpd_opp_low_svs>; 3364 }; 3365 3366 opp-300000000 { 3367 opp-hz = /bits/ 64 <300000000>; 3368 required-opps = <&rpmhpd_opp_svs>; 3369 }; 3370 3371 opp-358000000 { 3372 opp-hz = /bits/ 64 <358000000>; 3373 required-opps = <&rpmhpd_opp_svs_l1>; 3374 }; 3375 }; 3376 }; 3377 3378 mdss_dsi0_phy: phy@ae94400 { 3379 compatible = "qcom,dsi-phy-10nm"; 3380 reg = <0 0x0ae94400 0 0x200>, 3381 <0 0x0ae94600 0 0x280>, 3382 <0 0x0ae94a00 0 0x1e0>; 3383 reg-names = "dsi_phy", 3384 "dsi_phy_lane", 3385 "dsi_pll"; 3386 3387 #clock-cells = <1>; 3388 #phy-cells = <0>; 3389 3390 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3391 <&rpmhcc RPMH_CXO_CLK>; 3392 clock-names = "iface", "ref"; 3393 3394 status = "disabled"; 3395 }; 3396 3397 mdss_dp: displayport-controller@ae90000 { 3398 compatible = "qcom,sc7180-dp"; 3399 status = "disabled"; 3400 3401 reg = <0 0x0ae90000 0 0x200>, 3402 <0 0x0ae90200 0 0x200>, 3403 <0 0x0ae90400 0 0xc00>, 3404 <0 0x0ae91000 0 0x400>, 3405 <0 0x0ae91400 0 0x400>; 3406 3407 interrupt-parent = <&mdss>; 3408 interrupts = <12>; 3409 3410 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3411 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3412 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3413 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3414 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3415 clock-names = "core_iface", "core_aux", "ctrl_link", 3416 "ctrl_link_iface", "stream_pixel"; 3417 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3418 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3419 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3420 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3421 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3422 phy-names = "dp"; 3423 3424 operating-points-v2 = <&dp_opp_table>; 3425 power-domains = <&rpmhpd SC7180_CX>; 3426 3427 #sound-dai-cells = <0>; 3428 3429 ports { 3430 #address-cells = <1>; 3431 #size-cells = <0>; 3432 3433 port@0 { 3434 reg = <0>; 3435 3436 dp_in: endpoint { 3437 remote-endpoint = <&dpu_intf0_out>; 3438 }; 3439 }; 3440 3441 port@1 { 3442 reg = <1>; 3443 3444 mdss_dp_out: endpoint { }; 3445 }; 3446 }; 3447 3448 dp_opp_table: opp-table { 3449 compatible = "operating-points-v2"; 3450 3451 opp-160000000 { 3452 opp-hz = /bits/ 64 <160000000>; 3453 required-opps = <&rpmhpd_opp_low_svs>; 3454 }; 3455 3456 opp-270000000 { 3457 opp-hz = /bits/ 64 <270000000>; 3458 required-opps = <&rpmhpd_opp_svs>; 3459 }; 3460 3461 opp-540000000 { 3462 opp-hz = /bits/ 64 <540000000>; 3463 required-opps = <&rpmhpd_opp_svs_l1>; 3464 }; 3465 3466 opp-810000000 { 3467 opp-hz = /bits/ 64 <810000000>; 3468 required-opps = <&rpmhpd_opp_nom>; 3469 }; 3470 }; 3471 }; 3472 }; 3473 3474 dispcc: clock-controller@af00000 { 3475 compatible = "qcom,sc7180-dispcc"; 3476 reg = <0 0x0af00000 0 0x200000>; 3477 clocks = <&rpmhcc RPMH_CXO_CLK>, 3478 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3479 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3480 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3481 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3482 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3483 clock-names = "bi_tcxo", 3484 "gcc_disp_gpll0_clk_src", 3485 "dsi0_phy_pll_out_byteclk", 3486 "dsi0_phy_pll_out_dsiclk", 3487 "dp_phy_pll_link_clk", 3488 "dp_phy_pll_vco_div_clk"; 3489 #clock-cells = <1>; 3490 #reset-cells = <1>; 3491 #power-domain-cells = <1>; 3492 }; 3493 3494 pdc: interrupt-controller@b220000 { 3495 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3496 reg = <0 0x0b220000 0 0x30000>; 3497 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3498 #interrupt-cells = <2>; 3499 interrupt-parent = <&intc>; 3500 interrupt-controller; 3501 }; 3502 3503 pdc_reset: reset-controller@b2e0000 { 3504 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3505 reg = <0 0x0b2e0000 0 0x20000>; 3506 #reset-cells = <1>; 3507 }; 3508 3509 tsens0: thermal-sensor@c263000 { 3510 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3511 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3512 <0 0x0c222000 0 0x1ff>; /* SROT */ 3513 #qcom,sensors = <15>; 3514 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3516 interrupt-names = "uplow","critical"; 3517 #thermal-sensor-cells = <1>; 3518 }; 3519 3520 tsens1: thermal-sensor@c265000 { 3521 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3522 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3523 <0 0x0c223000 0 0x1ff>; /* SROT */ 3524 #qcom,sensors = <10>; 3525 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3527 interrupt-names = "uplow","critical"; 3528 #thermal-sensor-cells = <1>; 3529 }; 3530 3531 aoss_reset: reset-controller@c2a0000 { 3532 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3533 reg = <0 0x0c2a0000 0 0x31000>; 3534 #reset-cells = <1>; 3535 }; 3536 3537 aoss_qmp: power-management@c300000 { 3538 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; 3539 reg = <0 0x0c300000 0 0x400>; 3540 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3541 mboxes = <&apss_shared 0>; 3542 3543 #clock-cells = <0>; 3544 }; 3545 3546 sram@c3f0000 { 3547 compatible = "qcom,rpmh-stats"; 3548 reg = <0 0x0c3f0000 0 0x400>; 3549 }; 3550 3551 spmi_bus: spmi@c440000 { 3552 compatible = "qcom,spmi-pmic-arb"; 3553 reg = <0 0x0c440000 0 0x1100>, 3554 <0 0x0c600000 0 0x2000000>, 3555 <0 0x0e600000 0 0x100000>, 3556 <0 0x0e700000 0 0xa0000>, 3557 <0 0x0c40a000 0 0x26000>; 3558 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3559 interrupt-names = "periph_irq"; 3560 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3561 qcom,ee = <0>; 3562 qcom,channel = <0>; 3563 #address-cells = <2>; 3564 #size-cells = <0>; 3565 interrupt-controller; 3566 #interrupt-cells = <4>; 3567 }; 3568 3569 sram@14680000 { 3570 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; 3571 reg = <0 0x14680000 0 0x2e000>; 3572 3573 #address-cells = <1>; 3574 #size-cells = <1>; 3575 3576 ranges = <0 0 0x14680000 0x2e000>; 3577 3578 pil-reloc@2a94c { 3579 compatible = "qcom,pil-reloc-info"; 3580 reg = <0x2a94c 0xc8>; 3581 }; 3582 }; 3583 3584 apps_smmu: iommu@15000000 { 3585 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3586 reg = <0 0x15000000 0 0x100000>; 3587 #iommu-cells = <2>; 3588 #global-interrupts = <1>; 3589 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3590 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3591 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3592 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3593 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3594 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3595 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3596 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3597 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3598 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3599 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3600 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3601 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3602 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3603 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3604 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3605 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3631 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3632 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3654 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3660 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3670 dma-coherent; 3671 }; 3672 3673 intc: interrupt-controller@17a00000 { 3674 compatible = "arm,gic-v3"; 3675 #address-cells = <2>; 3676 #size-cells = <2>; 3677 ranges; 3678 #interrupt-cells = <3>; 3679 interrupt-controller; 3680 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3681 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3682 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3683 3684 msi-controller@17a40000 { 3685 compatible = "arm,gic-v3-its"; 3686 msi-controller; 3687 #msi-cells = <1>; 3688 reg = <0 0x17a40000 0 0x20000>; 3689 status = "disabled"; 3690 }; 3691 }; 3692 3693 apss_shared: mailbox@17c00000 { 3694 compatible = "qcom,sc7180-apss-shared", 3695 "qcom,sdm845-apss-shared"; 3696 reg = <0 0x17c00000 0 0x10000>; 3697 #mbox-cells = <1>; 3698 }; 3699 3700 watchdog@17c10000 { 3701 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3702 reg = <0 0x17c10000 0 0x1000>; 3703 clocks = <&sleep_clk>; 3704 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 3705 }; 3706 3707 timer@17c20000 { 3708 #address-cells = <1>; 3709 #size-cells = <1>; 3710 ranges = <0 0 0 0x20000000>; 3711 compatible = "arm,armv7-timer-mem"; 3712 reg = <0 0x17c20000 0 0x1000>; 3713 3714 frame@17c21000 { 3715 frame-number = <0>; 3716 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3718 reg = <0x17c21000 0x1000>, 3719 <0x17c22000 0x1000>; 3720 }; 3721 3722 frame@17c23000 { 3723 frame-number = <1>; 3724 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3725 reg = <0x17c23000 0x1000>; 3726 status = "disabled"; 3727 }; 3728 3729 frame@17c25000 { 3730 frame-number = <2>; 3731 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3732 reg = <0x17c25000 0x1000>; 3733 status = "disabled"; 3734 }; 3735 3736 frame@17c27000 { 3737 frame-number = <3>; 3738 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3739 reg = <0x17c27000 0x1000>; 3740 status = "disabled"; 3741 }; 3742 3743 frame@17c29000 { 3744 frame-number = <4>; 3745 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3746 reg = <0x17c29000 0x1000>; 3747 status = "disabled"; 3748 }; 3749 3750 frame@17c2b000 { 3751 frame-number = <5>; 3752 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3753 reg = <0x17c2b000 0x1000>; 3754 status = "disabled"; 3755 }; 3756 3757 frame@17c2d000 { 3758 frame-number = <6>; 3759 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3760 reg = <0x17c2d000 0x1000>; 3761 status = "disabled"; 3762 }; 3763 }; 3764 3765 apps_rsc: rsc@18200000 { 3766 compatible = "qcom,sc7180-rpmh-apps-rsc", "qcom,rpmh-rsc"; 3767 reg = <0 0x18200000 0 0x10000>, 3768 <0 0x18210000 0 0x10000>, 3769 <0 0x18220000 0 0x10000>; 3770 reg-names = "drv-0", "drv-1", "drv-2"; 3771 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3774 qcom,tcs-offset = <0xd00>; 3775 qcom,drv-id = <2>; 3776 qcom,tcs-config = <ACTIVE_TCS 2>, 3777 <SLEEP_TCS 3>, 3778 <WAKE_TCS 3>, 3779 <CONTROL_TCS 1>; 3780 power-domains = <&cluster_pd>; 3781 3782 rpmhcc: clock-controller { 3783 compatible = "qcom,sc7180-rpmh-clk"; 3784 clocks = <&xo_board>; 3785 clock-names = "xo"; 3786 #clock-cells = <1>; 3787 }; 3788 3789 rpmhpd: power-controller { 3790 compatible = "qcom,sc7180-rpmhpd"; 3791 #power-domain-cells = <1>; 3792 operating-points-v2 = <&rpmhpd_opp_table>; 3793 3794 rpmhpd_opp_table: opp-table { 3795 compatible = "operating-points-v2"; 3796 3797 rpmhpd_opp_ret: opp1 { 3798 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3799 }; 3800 3801 rpmhpd_opp_min_svs: opp2 { 3802 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3803 }; 3804 3805 rpmhpd_opp_low_svs: opp3 { 3806 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3807 }; 3808 3809 rpmhpd_opp_svs: opp4 { 3810 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3811 }; 3812 3813 rpmhpd_opp_svs_l1: opp5 { 3814 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3815 }; 3816 3817 rpmhpd_opp_svs_l2: opp6 { 3818 opp-level = <224>; 3819 }; 3820 3821 rpmhpd_opp_nom: opp7 { 3822 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3823 }; 3824 3825 rpmhpd_opp_nom_l1: opp8 { 3826 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3827 }; 3828 3829 rpmhpd_opp_nom_l2: opp9 { 3830 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3831 }; 3832 3833 rpmhpd_opp_turbo: opp10 { 3834 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3835 }; 3836 3837 rpmhpd_opp_turbo_l1: opp11 { 3838 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3839 }; 3840 }; 3841 }; 3842 3843 apps_bcm_voter: bcm-voter { 3844 compatible = "qcom,bcm-voter"; 3845 }; 3846 }; 3847 3848 osm_l3: interconnect@18321000 { 3849 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3"; 3850 reg = <0 0x18321000 0 0x1400>; 3851 3852 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3853 clock-names = "xo", "alternate"; 3854 3855 #interconnect-cells = <1>; 3856 }; 3857 3858 cpufreq_hw: cpufreq@18323000 { 3859 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw"; 3860 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3861 reg-names = "freq-domain0", "freq-domain1"; 3862 3863 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3864 clock-names = "xo", "alternate"; 3865 3866 #freq-domain-cells = <1>; 3867 #clock-cells = <1>; 3868 }; 3869 3870 wifi: wifi@18800000 { 3871 compatible = "qcom,wcn3990-wifi"; 3872 reg = <0 0x18800000 0 0x800000>; 3873 reg-names = "membase"; 3874 iommus = <&apps_smmu 0xc0 0x1>; 3875 interrupts = 3876 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3877 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3878 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3879 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3880 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3881 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3882 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3883 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3884 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3885 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3886 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3887 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3888 memory-region = <&wlan_mem>; 3889 qcom,msa-fixed-perm; 3890 status = "disabled"; 3891 }; 3892 3893 remoteproc_adsp: remoteproc@62400000 { 3894 compatible = "qcom,sc7180-adsp-pas"; 3895 reg = <0 0x62400000 0 0x100>; 3896 3897 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3898 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3899 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3900 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3901 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3902 interrupt-names = "wdog", 3903 "fatal", 3904 "ready", 3905 "handover", 3906 "stop-ack"; 3907 3908 clocks = <&rpmhcc RPMH_CXO_CLK>; 3909 clock-names = "xo"; 3910 3911 power-domains = <&rpmhpd SC7180_LCX>, 3912 <&rpmhpd SC7180_LMX>; 3913 power-domain-names = "lcx", "lmx"; 3914 3915 qcom,qmp = <&aoss_qmp>; 3916 qcom,smem-states = <&adsp_smp2p_out 0>; 3917 qcom,smem-state-names = "stop"; 3918 3919 status = "disabled"; 3920 3921 glink-edge { 3922 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3923 label = "lpass"; 3924 qcom,remote-pid = <2>; 3925 mboxes = <&apss_shared 8>; 3926 3927 apr { 3928 compatible = "qcom,apr-v2"; 3929 qcom,glink-channels = "apr_audio_svc"; 3930 qcom,domain = <APR_DOMAIN_ADSP>; 3931 #address-cells = <1>; 3932 #size-cells = <0>; 3933 3934 service@3 { 3935 compatible = "qcom,q6core"; 3936 reg = <APR_SVC_ADSP_CORE>; 3937 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3938 }; 3939 3940 q6afe: service@4 { 3941 compatible = "qcom,q6afe"; 3942 reg = <APR_SVC_AFE>; 3943 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3944 3945 q6afedai: dais { 3946 compatible = "qcom,q6afe-dais"; 3947 #address-cells = <1>; 3948 #size-cells = <0>; 3949 #sound-dai-cells = <1>; 3950 }; 3951 3952 q6afecc: clock-controller { 3953 compatible = "qcom,q6afe-clocks"; 3954 #clock-cells = <2>; 3955 }; 3956 }; 3957 3958 q6asm: service@7 { 3959 compatible = "qcom,q6asm"; 3960 reg = <APR_SVC_ASM>; 3961 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3962 3963 q6asmdai: dais { 3964 compatible = "qcom,q6asm-dais"; 3965 #address-cells = <1>; 3966 #size-cells = <0>; 3967 #sound-dai-cells = <1>; 3968 iommus = <&apps_smmu 0x1001 0x0>; 3969 }; 3970 }; 3971 3972 q6adm: service@8 { 3973 compatible = "qcom,q6adm"; 3974 reg = <APR_SVC_ADM>; 3975 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3976 3977 q6routing: routing { 3978 compatible = "qcom,q6adm-routing"; 3979 #sound-dai-cells = <0>; 3980 }; 3981 }; 3982 }; 3983 3984 fastrpc { 3985 compatible = "qcom,fastrpc"; 3986 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3987 label = "adsp"; 3988 #address-cells = <1>; 3989 #size-cells = <0>; 3990 3991 compute-cb@3 { 3992 compatible = "qcom,fastrpc-compute-cb"; 3993 reg = <3>; 3994 iommus = <&apps_smmu 0x1003 0x0>; 3995 }; 3996 3997 compute-cb@4 { 3998 compatible = "qcom,fastrpc-compute-cb"; 3999 reg = <4>; 4000 iommus = <&apps_smmu 0x1004 0x0>; 4001 }; 4002 4003 compute-cb@5 { 4004 compatible = "qcom,fastrpc-compute-cb"; 4005 reg = <5>; 4006 iommus = <&apps_smmu 0x1005 0x0>; 4007 qcom,nsessions = <5>; 4008 }; 4009 }; 4010 }; 4011 }; 4012 4013 lpasscc: clock-controller@62d00000 { 4014 compatible = "qcom,sc7180-lpasscorecc"; 4015 reg = <0 0x62d00000 0 0x50000>, 4016 <0 0x62780000 0 0x30000>; 4017 reg-names = "lpass_core_cc", "lpass_audio_cc"; 4018 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 4019 <&rpmhcc RPMH_CXO_CLK>; 4020 clock-names = "iface", "bi_tcxo"; 4021 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 4022 #clock-cells = <1>; 4023 #power-domain-cells = <1>; 4024 4025 status = "reserved"; /* Controlled by ADSP */ 4026 }; 4027 4028 lpass_cpu: lpass@62d87000 { 4029 compatible = "qcom,sc7180-lpass-cpu"; 4030 4031 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 4032 reg-names = "lpass-hdmiif", "lpass-lpaif"; 4033 4034 iommus = <&apps_smmu 0x1020 0>, 4035 <&apps_smmu 0x1021 0>, 4036 <&apps_smmu 0x1032 0>; 4037 4038 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 4039 required-opps = <&rpmhpd_opp_nom>; 4040 4041 status = "disabled"; 4042 4043 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 4044 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 4045 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 4046 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 4047 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 4048 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 4049 4050 clock-names = "pcnoc-sway-clk", "audio-core", 4051 "mclk0", "pcnoc-mport-clk", 4052 "mi2s-bit-clk0", "mi2s-bit-clk1"; 4053 4054 4055 #sound-dai-cells = <1>; 4056 #address-cells = <1>; 4057 #size-cells = <0>; 4058 4059 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 4061 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 4062 }; 4063 4064 lpass_hm: clock-controller@63000000 { 4065 compatible = "qcom,sc7180-lpasshm"; 4066 reg = <0 0x63000000 0 0x28>; 4067 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 4068 <&rpmhcc RPMH_CXO_CLK>; 4069 clock-names = "iface", "bi_tcxo"; 4070 power-domains = <&rpmhpd SC7180_CX>; 4071 4072 #clock-cells = <1>; 4073 #power-domain-cells = <1>; 4074 4075 status = "reserved"; /* Controlled by ADSP */ 4076 }; 4077 }; 4078 4079 thermal-zones { 4080 cpu0_thermal: cpu0-thermal { 4081 polling-delay-passive = <250>; 4082 4083 thermal-sensors = <&tsens0 1>; 4084 sustainable-power = <1052>; 4085 4086 trips { 4087 cpu0_alert0: trip-point0 { 4088 temperature = <90000>; 4089 hysteresis = <2000>; 4090 type = "passive"; 4091 }; 4092 4093 cpu0_alert1: trip-point1 { 4094 temperature = <95000>; 4095 hysteresis = <2000>; 4096 type = "passive"; 4097 }; 4098 4099 cpu0_crit: cpu-crit { 4100 temperature = <110000>; 4101 hysteresis = <1000>; 4102 type = "critical"; 4103 }; 4104 }; 4105 4106 cooling-maps { 4107 map0 { 4108 trip = <&cpu0_alert0>; 4109 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4110 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4111 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4112 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4113 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4114 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4115 }; 4116 map1 { 4117 trip = <&cpu0_alert1>; 4118 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4119 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4120 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4121 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4122 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4123 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4124 }; 4125 }; 4126 }; 4127 4128 cpu1_thermal: cpu1-thermal { 4129 polling-delay-passive = <250>; 4130 4131 thermal-sensors = <&tsens0 2>; 4132 sustainable-power = <1052>; 4133 4134 trips { 4135 cpu1_alert0: trip-point0 { 4136 temperature = <90000>; 4137 hysteresis = <2000>; 4138 type = "passive"; 4139 }; 4140 4141 cpu1_alert1: trip-point1 { 4142 temperature = <95000>; 4143 hysteresis = <2000>; 4144 type = "passive"; 4145 }; 4146 4147 cpu1_crit: cpu-crit { 4148 temperature = <110000>; 4149 hysteresis = <1000>; 4150 type = "critical"; 4151 }; 4152 }; 4153 4154 cooling-maps { 4155 map0 { 4156 trip = <&cpu1_alert0>; 4157 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4158 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4160 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4161 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4162 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4163 }; 4164 map1 { 4165 trip = <&cpu1_alert1>; 4166 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4167 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4168 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4169 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4170 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4171 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4172 }; 4173 }; 4174 }; 4175 4176 cpu2_thermal: cpu2-thermal { 4177 polling-delay-passive = <250>; 4178 4179 thermal-sensors = <&tsens0 3>; 4180 sustainable-power = <1052>; 4181 4182 trips { 4183 cpu2_alert0: trip-point0 { 4184 temperature = <90000>; 4185 hysteresis = <2000>; 4186 type = "passive"; 4187 }; 4188 4189 cpu2_alert1: trip-point1 { 4190 temperature = <95000>; 4191 hysteresis = <2000>; 4192 type = "passive"; 4193 }; 4194 4195 cpu2_crit: cpu-crit { 4196 temperature = <110000>; 4197 hysteresis = <1000>; 4198 type = "critical"; 4199 }; 4200 }; 4201 4202 cooling-maps { 4203 map0 { 4204 trip = <&cpu2_alert0>; 4205 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4206 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4207 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4208 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4209 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4210 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4211 }; 4212 map1 { 4213 trip = <&cpu2_alert1>; 4214 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4215 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4216 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4217 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4218 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4219 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4220 }; 4221 }; 4222 }; 4223 4224 cpu3_thermal: cpu3-thermal { 4225 polling-delay-passive = <250>; 4226 4227 thermal-sensors = <&tsens0 4>; 4228 sustainable-power = <1052>; 4229 4230 trips { 4231 cpu3_alert0: trip-point0 { 4232 temperature = <90000>; 4233 hysteresis = <2000>; 4234 type = "passive"; 4235 }; 4236 4237 cpu3_alert1: trip-point1 { 4238 temperature = <95000>; 4239 hysteresis = <2000>; 4240 type = "passive"; 4241 }; 4242 4243 cpu3_crit: cpu-crit { 4244 temperature = <110000>; 4245 hysteresis = <1000>; 4246 type = "critical"; 4247 }; 4248 }; 4249 4250 cooling-maps { 4251 map0 { 4252 trip = <&cpu3_alert0>; 4253 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4254 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4255 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4256 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4257 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4258 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4259 }; 4260 map1 { 4261 trip = <&cpu3_alert1>; 4262 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4263 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4264 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4265 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4266 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4267 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4268 }; 4269 }; 4270 }; 4271 4272 cpu4_thermal: cpu4-thermal { 4273 polling-delay-passive = <250>; 4274 4275 thermal-sensors = <&tsens0 5>; 4276 sustainable-power = <1052>; 4277 4278 trips { 4279 cpu4_alert0: trip-point0 { 4280 temperature = <90000>; 4281 hysteresis = <2000>; 4282 type = "passive"; 4283 }; 4284 4285 cpu4_alert1: trip-point1 { 4286 temperature = <95000>; 4287 hysteresis = <2000>; 4288 type = "passive"; 4289 }; 4290 4291 cpu4_crit: cpu-crit { 4292 temperature = <110000>; 4293 hysteresis = <1000>; 4294 type = "critical"; 4295 }; 4296 }; 4297 4298 cooling-maps { 4299 map0 { 4300 trip = <&cpu4_alert0>; 4301 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4302 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4303 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4304 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4305 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4306 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4307 }; 4308 map1 { 4309 trip = <&cpu4_alert1>; 4310 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4311 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4312 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4313 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4314 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4315 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4316 }; 4317 }; 4318 }; 4319 4320 cpu5_thermal: cpu5-thermal { 4321 polling-delay-passive = <250>; 4322 4323 thermal-sensors = <&tsens0 6>; 4324 sustainable-power = <1052>; 4325 4326 trips { 4327 cpu5_alert0: trip-point0 { 4328 temperature = <90000>; 4329 hysteresis = <2000>; 4330 type = "passive"; 4331 }; 4332 4333 cpu5_alert1: trip-point1 { 4334 temperature = <95000>; 4335 hysteresis = <2000>; 4336 type = "passive"; 4337 }; 4338 4339 cpu5_crit: cpu-crit { 4340 temperature = <110000>; 4341 hysteresis = <1000>; 4342 type = "critical"; 4343 }; 4344 }; 4345 4346 cooling-maps { 4347 map0 { 4348 trip = <&cpu5_alert0>; 4349 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4350 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4351 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4352 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4353 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4354 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4355 }; 4356 map1 { 4357 trip = <&cpu5_alert1>; 4358 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4359 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4360 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4361 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4362 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4363 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4364 }; 4365 }; 4366 }; 4367 4368 cpu6_thermal: cpu6-thermal { 4369 polling-delay-passive = <250>; 4370 4371 thermal-sensors = <&tsens0 9>; 4372 sustainable-power = <1425>; 4373 4374 trips { 4375 cpu6_alert0: trip-point0 { 4376 temperature = <90000>; 4377 hysteresis = <2000>; 4378 type = "passive"; 4379 }; 4380 4381 cpu6_alert1: trip-point1 { 4382 temperature = <95000>; 4383 hysteresis = <2000>; 4384 type = "passive"; 4385 }; 4386 4387 cpu6_crit: cpu-crit { 4388 temperature = <110000>; 4389 hysteresis = <1000>; 4390 type = "critical"; 4391 }; 4392 }; 4393 4394 cooling-maps { 4395 map0 { 4396 trip = <&cpu6_alert0>; 4397 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4398 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4399 }; 4400 map1 { 4401 trip = <&cpu6_alert1>; 4402 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4403 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4404 }; 4405 }; 4406 }; 4407 4408 cpu7_thermal: cpu7-thermal { 4409 polling-delay-passive = <250>; 4410 4411 thermal-sensors = <&tsens0 10>; 4412 sustainable-power = <1425>; 4413 4414 trips { 4415 cpu7_alert0: trip-point0 { 4416 temperature = <90000>; 4417 hysteresis = <2000>; 4418 type = "passive"; 4419 }; 4420 4421 cpu7_alert1: trip-point1 { 4422 temperature = <95000>; 4423 hysteresis = <2000>; 4424 type = "passive"; 4425 }; 4426 4427 cpu7_crit: cpu-crit { 4428 temperature = <110000>; 4429 hysteresis = <1000>; 4430 type = "critical"; 4431 }; 4432 }; 4433 4434 cooling-maps { 4435 map0 { 4436 trip = <&cpu7_alert0>; 4437 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4438 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4439 }; 4440 map1 { 4441 trip = <&cpu7_alert1>; 4442 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4443 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4444 }; 4445 }; 4446 }; 4447 4448 cpu8_thermal: cpu8-thermal { 4449 polling-delay-passive = <250>; 4450 4451 thermal-sensors = <&tsens0 11>; 4452 sustainable-power = <1425>; 4453 4454 trips { 4455 cpu8_alert0: trip-point0 { 4456 temperature = <90000>; 4457 hysteresis = <2000>; 4458 type = "passive"; 4459 }; 4460 4461 cpu8_alert1: trip-point1 { 4462 temperature = <95000>; 4463 hysteresis = <2000>; 4464 type = "passive"; 4465 }; 4466 4467 cpu8_crit: cpu-crit { 4468 temperature = <110000>; 4469 hysteresis = <1000>; 4470 type = "critical"; 4471 }; 4472 }; 4473 4474 cooling-maps { 4475 map0 { 4476 trip = <&cpu8_alert0>; 4477 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4478 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4479 }; 4480 map1 { 4481 trip = <&cpu8_alert1>; 4482 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4483 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4484 }; 4485 }; 4486 }; 4487 4488 cpu9_thermal: cpu9-thermal { 4489 polling-delay-passive = <250>; 4490 4491 thermal-sensors = <&tsens0 12>; 4492 sustainable-power = <1425>; 4493 4494 trips { 4495 cpu9_alert0: trip-point0 { 4496 temperature = <90000>; 4497 hysteresis = <2000>; 4498 type = "passive"; 4499 }; 4500 4501 cpu9_alert1: trip-point1 { 4502 temperature = <95000>; 4503 hysteresis = <2000>; 4504 type = "passive"; 4505 }; 4506 4507 cpu9_crit: cpu-crit { 4508 temperature = <110000>; 4509 hysteresis = <1000>; 4510 type = "critical"; 4511 }; 4512 }; 4513 4514 cooling-maps { 4515 map0 { 4516 trip = <&cpu9_alert0>; 4517 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4518 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4519 }; 4520 map1 { 4521 trip = <&cpu9_alert1>; 4522 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4523 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4524 }; 4525 }; 4526 }; 4527 4528 aoss0-thermal { 4529 polling-delay-passive = <250>; 4530 4531 thermal-sensors = <&tsens0 0>; 4532 4533 trips { 4534 aoss0_alert0: trip-point0 { 4535 temperature = <90000>; 4536 hysteresis = <2000>; 4537 type = "hot"; 4538 }; 4539 4540 aoss0_crit: aoss0-crit { 4541 temperature = <110000>; 4542 hysteresis = <2000>; 4543 type = "critical"; 4544 }; 4545 }; 4546 }; 4547 4548 cpuss0-thermal { 4549 polling-delay-passive = <250>; 4550 4551 thermal-sensors = <&tsens0 7>; 4552 4553 trips { 4554 cpuss0_alert0: trip-point0 { 4555 temperature = <90000>; 4556 hysteresis = <2000>; 4557 type = "hot"; 4558 }; 4559 cpuss0_crit: cluster0-crit { 4560 temperature = <110000>; 4561 hysteresis = <2000>; 4562 type = "critical"; 4563 }; 4564 }; 4565 }; 4566 4567 cpuss1-thermal { 4568 polling-delay-passive = <250>; 4569 4570 thermal-sensors = <&tsens0 8>; 4571 4572 trips { 4573 cpuss1_alert0: trip-point0 { 4574 temperature = <90000>; 4575 hysteresis = <2000>; 4576 type = "hot"; 4577 }; 4578 cpuss1_crit: cluster0-crit { 4579 temperature = <110000>; 4580 hysteresis = <2000>; 4581 type = "critical"; 4582 }; 4583 }; 4584 }; 4585 4586 gpuss0-thermal { 4587 polling-delay-passive = <250>; 4588 4589 thermal-sensors = <&tsens0 13>; 4590 4591 trips { 4592 gpuss0_alert0: trip-point0 { 4593 temperature = <95000>; 4594 hysteresis = <2000>; 4595 type = "passive"; 4596 }; 4597 4598 gpuss0_crit: gpuss0-crit { 4599 temperature = <110000>; 4600 hysteresis = <2000>; 4601 type = "critical"; 4602 }; 4603 }; 4604 4605 cooling-maps { 4606 map0 { 4607 trip = <&gpuss0_alert0>; 4608 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4609 }; 4610 }; 4611 }; 4612 4613 gpuss1-thermal { 4614 polling-delay-passive = <250>; 4615 4616 thermal-sensors = <&tsens0 14>; 4617 4618 trips { 4619 gpuss1_alert0: trip-point0 { 4620 temperature = <95000>; 4621 hysteresis = <2000>; 4622 type = "passive"; 4623 }; 4624 4625 gpuss1_crit: gpuss1-crit { 4626 temperature = <110000>; 4627 hysteresis = <2000>; 4628 type = "critical"; 4629 }; 4630 }; 4631 4632 cooling-maps { 4633 map0 { 4634 trip = <&gpuss1_alert0>; 4635 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4636 }; 4637 }; 4638 }; 4639 4640 aoss1-thermal { 4641 polling-delay-passive = <250>; 4642 4643 thermal-sensors = <&tsens1 0>; 4644 4645 trips { 4646 aoss1_alert0: trip-point0 { 4647 temperature = <90000>; 4648 hysteresis = <2000>; 4649 type = "hot"; 4650 }; 4651 4652 aoss1_crit: aoss1-crit { 4653 temperature = <110000>; 4654 hysteresis = <2000>; 4655 type = "critical"; 4656 }; 4657 }; 4658 }; 4659 4660 cwlan-thermal { 4661 polling-delay-passive = <250>; 4662 4663 thermal-sensors = <&tsens1 1>; 4664 4665 trips { 4666 cwlan_alert0: trip-point0 { 4667 temperature = <90000>; 4668 hysteresis = <2000>; 4669 type = "hot"; 4670 }; 4671 4672 cwlan_crit: cwlan-crit { 4673 temperature = <110000>; 4674 hysteresis = <2000>; 4675 type = "critical"; 4676 }; 4677 }; 4678 }; 4679 4680 audio-thermal { 4681 polling-delay-passive = <250>; 4682 4683 thermal-sensors = <&tsens1 2>; 4684 4685 trips { 4686 audio_alert0: trip-point0 { 4687 temperature = <90000>; 4688 hysteresis = <2000>; 4689 type = "hot"; 4690 }; 4691 4692 audio_crit: audio-crit { 4693 temperature = <110000>; 4694 hysteresis = <2000>; 4695 type = "critical"; 4696 }; 4697 }; 4698 }; 4699 4700 ddr-thermal { 4701 polling-delay-passive = <250>; 4702 4703 thermal-sensors = <&tsens1 3>; 4704 4705 trips { 4706 ddr_alert0: trip-point0 { 4707 temperature = <90000>; 4708 hysteresis = <2000>; 4709 type = "hot"; 4710 }; 4711 4712 ddr_crit: ddr-crit { 4713 temperature = <110000>; 4714 hysteresis = <2000>; 4715 type = "critical"; 4716 }; 4717 }; 4718 }; 4719 4720 q6-hvx-thermal { 4721 polling-delay-passive = <250>; 4722 4723 thermal-sensors = <&tsens1 4>; 4724 4725 trips { 4726 q6_hvx_alert0: trip-point0 { 4727 temperature = <90000>; 4728 hysteresis = <2000>; 4729 type = "hot"; 4730 }; 4731 4732 q6_hvx_crit: q6-hvx-crit { 4733 temperature = <110000>; 4734 hysteresis = <2000>; 4735 type = "critical"; 4736 }; 4737 }; 4738 }; 4739 4740 camera-thermal { 4741 polling-delay-passive = <250>; 4742 4743 thermal-sensors = <&tsens1 5>; 4744 4745 trips { 4746 camera_alert0: trip-point0 { 4747 temperature = <90000>; 4748 hysteresis = <2000>; 4749 type = "hot"; 4750 }; 4751 4752 camera_crit: camera-crit { 4753 temperature = <110000>; 4754 hysteresis = <2000>; 4755 type = "critical"; 4756 }; 4757 }; 4758 }; 4759 4760 mdm-core-thermal { 4761 polling-delay-passive = <250>; 4762 4763 thermal-sensors = <&tsens1 6>; 4764 4765 trips { 4766 mdm_alert0: trip-point0 { 4767 temperature = <90000>; 4768 hysteresis = <2000>; 4769 type = "hot"; 4770 }; 4771 4772 mdm_crit: mdm-crit { 4773 temperature = <110000>; 4774 hysteresis = <2000>; 4775 type = "critical"; 4776 }; 4777 }; 4778 }; 4779 4780 mdm-dsp-thermal { 4781 polling-delay-passive = <250>; 4782 4783 thermal-sensors = <&tsens1 7>; 4784 4785 trips { 4786 mdm_dsp_alert0: trip-point0 { 4787 temperature = <90000>; 4788 hysteresis = <2000>; 4789 type = "hot"; 4790 }; 4791 4792 mdm_dsp_crit: mdm-dsp-crit { 4793 temperature = <110000>; 4794 hysteresis = <2000>; 4795 type = "critical"; 4796 }; 4797 }; 4798 }; 4799 4800 npu-thermal { 4801 polling-delay-passive = <250>; 4802 4803 thermal-sensors = <&tsens1 8>; 4804 4805 trips { 4806 npu_alert0: trip-point0 { 4807 temperature = <90000>; 4808 hysteresis = <2000>; 4809 type = "hot"; 4810 }; 4811 4812 npu_crit: npu-crit { 4813 temperature = <110000>; 4814 hysteresis = <2000>; 4815 type = "critical"; 4816 }; 4817 }; 4818 }; 4819 4820 video-thermal { 4821 polling-delay-passive = <250>; 4822 4823 thermal-sensors = <&tsens1 9>; 4824 4825 trips { 4826 video_alert0: trip-point0 { 4827 temperature = <90000>; 4828 hysteresis = <2000>; 4829 type = "hot"; 4830 }; 4831 4832 video_crit: video-crit { 4833 temperature = <110000>; 4834 hysteresis = <2000>; 4835 type = "critical"; 4836 }; 4837 }; 4838 }; 4839 }; 4840 4841 timer { 4842 compatible = "arm,armv8-timer"; 4843 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4844 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4845 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4846 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4847 }; 4848}; 4849