1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sar2130p-gcc.h> 8#include <dt-bindings/clock/qcom,sar2130p-gpucc.h> 9#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 10#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/interconnect/qcom,icc.h> 13#include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/soc/qcom,gpr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 clocks { 32 xo_board: xo-board { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <19200000>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32764>; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a55"; 52 reg = <0x0 0x0>; 53 clocks = <&cpufreq_hw 0>; 54 enable-method = "psci"; 55 next-level-cache = <&l2_0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 power-domains = <&cpu_pd0>; 58 power-domain-names = "psci"; 59 #cooling-cells = <2>; 60 61 l2_0: l2-cache { 62 compatible = "cache"; 63 cache-level = <2>; 64 cache-unified; 65 next-level-cache = <&l3_0>; 66 67 l3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 cache-unified; 71 }; 72 }; 73 }; 74 75 cpu1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a55"; 78 reg = <0x0 0x100>; 79 clocks = <&cpufreq_hw 0>; 80 enable-method = "psci"; 81 next-level-cache = <&l2_100>; 82 qcom,freq-domain = <&cpufreq_hw 0>; 83 power-domains = <&cpu_pd1>; 84 power-domain-names = "psci"; 85 #cooling-cells = <2>; 86 87 l2_100: l2-cache { 88 compatible = "cache"; 89 cache-level = <2>; 90 cache-unified; 91 next-level-cache = <&l3_0>; 92 }; 93 }; 94 95 cpu2: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a55"; 98 reg = <0x0 0x200>; 99 clocks = <&cpufreq_hw 0>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_200>; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 power-domains = <&cpu_pd2>; 104 power-domain-names = "psci"; 105 #cooling-cells = <2>; 106 107 l2_200: l2-cache { 108 compatible = "cache"; 109 cache-level = <2>; 110 cache-unified; 111 next-level-cache = <&l3_0>; 112 }; 113 }; 114 115 cpu3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x0 0x300>; 119 clocks = <&cpufreq_hw 0>; 120 enable-method = "psci"; 121 next-level-cache = <&l2_300>; 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 power-domains = <&cpu_pd3>; 124 power-domain-names = "psci"; 125 #cooling-cells = <2>; 126 127 l2_300: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&l3_0>; 132 }; 133 }; 134 135 cpu-map { 136 cluster0 { 137 core0 { 138 cpu = <&cpu0>; 139 }; 140 141 core1 { 142 cpu = <&cpu1>; 143 }; 144 145 core2 { 146 cpu = <&cpu2>; 147 }; 148 149 core3 { 150 cpu = <&cpu3>; 151 }; 152 }; 153 }; 154 155 idle-states { 156 entry-method = "psci"; 157 158 cpu_sleep_0: cpu-sleep-0-0 { 159 compatible = "arm,idle-state"; 160 idle-state-name = "silver-power-collapse"; 161 arm,psci-suspend-param = <0x40000003>; 162 entry-latency-us = <549>; 163 exit-latency-us = <901>; 164 min-residency-us = <1774>; 165 local-timer-stop; 166 }; 167 168 cpu_sleep_1: cpu-sleep-0-1 { 169 compatible = "arm,idle-state"; 170 idle-state-name = "silver-rail-power-collapse"; 171 arm,psci-suspend-param = <0x40000004>; 172 entry-latency-us = <702>; 173 exit-latency-us = <915>; 174 min-residency-us = <4001>; 175 local-timer-stop; 176 }; 177 }; 178 179 domain-idle-states { 180 cluster_sleep_0: cluster-sleep-0 { 181 compatible = "domain-idle-state"; 182 arm,psci-suspend-param = <0x41000044>; 183 entry-latency-us = <2752>; 184 exit-latency-us = <3048>; 185 min-residency-us = <6118>; 186 }; 187 188 cluster_sleep_1: cluster-sleep-1 { 189 compatible = "domain-idle-state"; 190 arm,psci-suspend-param = <0x41002344>; 191 entry-latency-us = <3263>; 192 exit-latency-us = <4562>; 193 min-residency-us = <8467>; 194 }; 195 196 cluster_sleep_2: cluster-sleep-2 { 197 compatible = "domain-idle-state"; 198 arm,psci-suspend-param = <0x4100c344>; 199 entry-latency-us = <3638>; 200 exit-latency-us = <6562>; 201 min-residency-us = <9862>; 202 }; 203 }; 204 }; 205 206 firmware { 207 scm: scm { 208 compatible = "qcom,scm-sar2130p", "qcom,scm"; 209 qcom,dload-mode = <&tcsr_mutex 0x13000>; 210 interconnects = <&system_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 211 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 212 }; 213 }; 214 215 clk_virt: interconnect-0 { 216 compatible = "qcom,sar2130p-clk-virt"; 217 #interconnect-cells = <2>; 218 qcom,bcm-voters = <&apps_bcm_voter>; 219 }; 220 221 mc_virt: interconnect-1 { 222 compatible = "qcom,sar2130p-mc-virt"; 223 #interconnect-cells = <2>; 224 qcom,bcm-voters = <&apps_bcm_voter>; 225 }; 226 227 memory@80000000 { 228 device_type = "memory"; 229 /* We expect the bootloader to fill in the size */ 230 reg = <0x0 0x80000000 0x0 0x0>; 231 }; 232 233 pmu { 234 compatible = "arm,armv8-pmuv3"; 235 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 236 }; 237 238 psci { 239 compatible = "arm,psci-1.0"; 240 method = "smc"; 241 242 cpu_pd0: power-domain-cpu0 { 243 #power-domain-cells = <0>; 244 power-domains = <&cluster_pd>; 245 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 246 }; 247 248 cpu_pd1: power-domain-cpu1 { 249 #power-domain-cells = <0>; 250 power-domains = <&cluster_pd>; 251 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 252 }; 253 254 cpu_pd2: power-domain-cpu2 { 255 #power-domain-cells = <0>; 256 power-domains = <&cluster_pd>; 257 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 258 }; 259 260 cpu_pd3: power-domain-cpu3 { 261 #power-domain-cells = <0>; 262 power-domains = <&cluster_pd>; 263 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 264 }; 265 266 cluster_pd: power-domain-cpu-cluster0 { 267 #power-domain-cells = <0>; 268 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>, <&cluster_sleep_2>; 269 }; 270 }; 271 272 reserved_memory: reserved-memory { 273 #address-cells = <2>; 274 #size-cells = <2>; 275 ranges; 276 277 hyp_mem: hyp@80000000 { 278 reg = <0x0 0x80000000 0x0 0x600000>; 279 no-map; 280 }; 281 282 xbl_dt_log_mem: xbl-dt-log@80600000 { 283 reg = <0x0 0x80600000 0x0 0x40000>; 284 no-map; 285 }; 286 287 xbl_ramdump_mem: xbl-ramdump@80640000 { 288 reg = <0x0 0x80640000 0x0 0x1c0000>; 289 no-map; 290 }; 291 292 aop_image_mem: aop-image@80800000 { 293 reg = <0x0 0x80800000 0x0 0x60000>; 294 no-map; 295 }; 296 297 aop_cmd_db_mem: aop-cmd-db@80860000 { 298 compatible = "qcom,cmd-db"; 299 reg = <0x0 0x80860000 0x0 0x20000>; 300 no-map; 301 }; 302 303 aop_config_mem: aop-config@80880000 { 304 reg = <0x0 0x80880000 0x0 0x20000>; 305 no-map; 306 }; 307 308 tme_crash_dump_mem: tme-crash-dump@808a0000 { 309 reg = <0x0 0x808a0000 0x0 0x40000>; 310 no-map; 311 }; 312 313 tme_log_mem: tme-log@808e0000 { 314 reg = <0x0 0x808e0000 0x0 0x4000>; 315 no-map; 316 }; 317 318 uefi_log_mem: uefi-log@808e4000 { 319 reg = <0x0 0x808e4000 0x0 0x10000>; 320 no-map; 321 }; 322 323 secdata_apss_mem: secdata-apss@808ff000 { 324 reg = <0x0 0x808ff000 0x0 0x1000>; 325 no-map; 326 }; 327 328 smem: smem@80900000 { 329 compatible = "qcom,smem"; 330 reg = <0x0 0x80900000 0x0 0x200000>; 331 hwlocks = <&tcsr_mutex 3>; 332 no-map; 333 }; 334 335 cpucp_fw_mem: cpucp-fw@80b00000 { 336 reg = <0x0 0x80b00000 0x0 0x100000>; 337 no-map; 338 }; 339 340 helios_ram_dump_mem: helios-ram-dump@80c00000 { 341 reg = <0x0 0x80c00000 0x0 0xe00000>; 342 no-map; 343 }; 344 345 camera_mem: camera@84e00000 { 346 reg = <0x0 0x84e00000 0x0 0x800000>; 347 no-map; 348 }; 349 350 video_mem: video@86f00000 { 351 reg = <0x0 0x86f00000 0x0 0x500000>; 352 no-map; 353 }; 354 355 adsp_mem: adsp@87600000 { 356 reg = <0x0 0x87600000 0x0 0x1e00000>; 357 no-map; 358 }; 359 360 cdsp_mem: cdsp@89400000 { 361 reg = <0x0 0x89400000 0x0 0xf00000>; 362 no-map; 363 }; 364 365 ipa_fw_mem: ipa-fw@8a300000 { 366 reg = <0x0 0x8a300000 0x0 0x10000>; 367 no-map; 368 }; 369 370 ipa_gsi_mem: ipa-gsi@8a3a0000 { 371 reg = <0x0 0x8a310000 0x0 0xa000>; 372 no-map; 373 }; 374 375 gpu_micro_code_mem: gpu-micro-code@8a31a000 { 376 reg = <0x0 0x8a31a000 0x0 0x2000>; 377 no-map; 378 }; 379 380 cvp_mem: cvp@8a400000 { 381 reg = <0x0 0x8a400000 0x0 0x700000>; 382 no-map; 383 }; 384 385 xbl_sc_mem: xbl-sc@a6e00000 { 386 no-map; 387 reg = <0x0 0xa6e00000 0x0 0x40000>; 388 }; 389 390 global_sync_mem: global-sync@a6f00000 { 391 no-map; 392 reg = <0x0 0xa6f00000 0x0 0x100000>; 393 }; 394 395 tz_stat_mem: tz-stat@e8800000 { 396 no-map; 397 reg = <0x0 0xe8800000 0x0 0x100000>; 398 }; 399 400 tags_mem: tags@e8900000 { 401 no-map; 402 reg = <0x0 0xe8900000 0x0 0x500000>; 403 }; 404 405 qtee_mem: qtee@e8e00000 { 406 no-map; 407 reg = <0x0 0xe8e00000 0x0 0x500000>; 408 }; 409 410 trusted_apps_mem: trusted-apps@e9300000 { 411 no-map; 412 reg = <0x0 0xe9300000 0x0 0xc00000>; 413 }; 414 }; 415 416 smp2p-adsp { 417 compatible = "qcom,smp2p"; 418 qcom,smem = <443>, <429>; 419 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 420 IPCC_MPROC_SIGNAL_SMP2P 421 IRQ_TYPE_EDGE_RISING>; 422 mboxes = <&ipcc IPCC_CLIENT_LPASS 423 IPCC_MPROC_SIGNAL_SMP2P>; 424 425 qcom,local-pid = <0>; 426 qcom,remote-pid = <2>; 427 428 smp2p_adsp_out: master-kernel { 429 qcom,entry-name = "master-kernel"; 430 #qcom,smem-state-cells = <1>; 431 }; 432 433 smp2p_adsp_in: slave-kernel { 434 qcom,entry-name = "slave-kernel"; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 }; 438 }; 439 440 smp2p-cdsp { 441 compatible = "qcom,smp2p"; 442 qcom,smem = <94>, <432>; 443 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 444 IPCC_MPROC_SIGNAL_SMP2P 445 IRQ_TYPE_EDGE_RISING>; 446 mboxes = <&ipcc IPCC_CLIENT_CDSP 447 IPCC_MPROC_SIGNAL_SMP2P>; 448 449 qcom,local-pid = <0>; 450 qcom,remote-pid = <5>; 451 452 smp2p_cdsp_out: master-kernel { 453 qcom,entry-name = "master-kernel"; 454 #qcom,smem-state-cells = <1>; 455 }; 456 457 smp2p_cdsp_in: slave-kernel { 458 qcom,entry-name = "slave-kernel"; 459 interrupt-controller; 460 #interrupt-cells = <2>; 461 }; 462 }; 463 464 soc: soc@0 { 465 compatible = "simple-bus"; 466 #address-cells = <2>; 467 #size-cells = <2>; 468 ranges = <0 0 0 0 0x10 0>; 469 dma-ranges = <0 0 0 0 0x10 0>; 470 471 gcc: clock-controller@100000 { 472 compatible = "qcom,sar2130p-gcc"; 473 reg = <0x0 0x00100000 0x0 0x1f4200>; 474 #clock-cells = <1>; 475 #reset-cells = <1>; 476 #power-domain-cells = <1>; 477 clocks = <&rpmhcc RPMH_CXO_CLK>, 478 <&sleep_clk>, 479 <&pcie0_phy>, 480 <&pcie1_phy>, 481 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 482 }; 483 484 sdhc_1: mmc@7c4000 { 485 compatible = "qcom,sar2130p-sdhci", "qcom,sdhci-msm-v5"; 486 reg = <0x0 0x007c4000 0x0 0x1000>, 487 <0x0 0x007c5000 0x0 0x1000>; 488 reg-names = "hc", "cqhci"; 489 490 iommus = <&apps_smmu 0x160 0x0>; 491 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 493 interrupt-names = "hc_irq", "pwr_irq"; 494 495 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 496 <&gcc GCC_SDCC1_APPS_CLK>, 497 <&rpmhcc RPMH_CXO_CLK>; 498 clock-names = "iface", "core", "xo"; 499 interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 500 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 501 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 502 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; 503 interconnect-names = "sdhc-ddr","cpu-sdhc"; 504 power-domains = <&rpmhpd RPMHPD_CX>; 505 operating-points-v2 = <&sdhc1_opp_table>; 506 507 pinctrl-0 = <&sdc1_default>; 508 pinctrl-1 = <&sdc1_sleep>; 509 pinctrl-names = "default", "sleep"; 510 511 bus-width = <8>; 512 non-removable; 513 supports-cqe; 514 515 mmc-ddr-1_8v; 516 mmc-hs200-1_8v; 517 mmc-hs400-1_8v; 518 mmc-hs400-enhanced-strobe; 519 520 status = "disabled"; 521 522 sdhc1_opp_table: opp-table { 523 compatible = "operating-points-v2"; 524 525 opp-100000000 { 526 opp-hz = /bits/ 64 <100000000>; 527 required-opps = <&rpmhpd_opp_low_svs>; 528 opp-peak-kBps = <500000 200000>; 529 opp-avg-kBps = <104000 0>; 530 }; 531 532 opp-384000000 { 533 opp-hz = /bits/ 64 <384000000>; 534 required-opps = <&rpmhpd_opp_nom>; 535 opp-peak-kBps = <2500000 1000000>; 536 opp-avg-kBps = <400000 0>; 537 }; 538 }; 539 }; 540 541 gpi_dma0: dma-controller@900000 { 542 compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma"; 543 reg = <0x0 0x00900000 0x0 0x60000>; 544 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 556 #dma-cells = <3>; 557 dma-channels = <12>; 558 dma-channel-mask = <0x7e>; 559 iommus = <&apps_smmu 0x76 0x0>; 560 561 status = "disabled"; 562 }; 563 564 qupv3_id_0: geniqup@9c0000 { 565 compatible = "qcom,geni-se-qup"; 566 reg = <0x0 0x009c0000 0x0 0x2000>; 567 clock-names = "m-ahb", "s-ahb"; 568 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 569 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 570 iommus = <&apps_smmu 0x63 0x0>; 571 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 572 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; 573 interconnect-names = "qup-core"; 574 #address-cells = <2>; 575 #size-cells = <2>; 576 ranges; 577 578 status = "disabled"; 579 580 i2c0: i2c@980000 { 581 compatible = "qcom,geni-i2c"; 582 reg = <0x0 0x00980000 0x0 0x4000>; 583 clock-names = "se"; 584 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 585 pinctrl-0 = <&qup_i2c0_data_clk>; 586 pinctrl-names = "default"; 587 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 591 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 592 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 593 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 594 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 595 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 596 interconnect-names = "qup-core", "qup-config", "qup-memory"; 597 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 598 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 599 dma-names = "tx", "rx"; 600 601 status = "disabled"; 602 }; 603 604 spi0: spi@980000 { 605 compatible = "qcom,geni-spi"; 606 reg = <0x0 0x00980000 0x0 0x4000>; 607 clock-names = "se"; 608 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 609 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 610 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs0>; 611 pinctrl-names = "default"; 612 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 613 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 614 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 615 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 616 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 617 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 618 interconnect-names = "qup-core", "qup-config", "qup-memory"; 619 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 620 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 621 dma-names = "tx", "rx"; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 625 status = "disabled"; 626 }; 627 628 i2c1: i2c@984000 { 629 compatible = "qcom,geni-i2c"; 630 reg = <0x0 0x00984000 0x0 0x4000>; 631 clock-names = "se"; 632 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 633 pinctrl-0 = <&qup_i2c1_data_clk>; 634 pinctrl-names = "default"; 635 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 639 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 640 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 641 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 642 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 643 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 644 interconnect-names = "qup-core", "qup-config", "qup-memory"; 645 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 646 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 647 dma-names = "tx", "rx"; 648 649 status = "disabled"; 650 }; 651 652 spi1: spi@984000 { 653 compatible = "qcom,geni-spi"; 654 reg = <0x0 0x00984000 0x0 0x4000>; 655 clock-names = "se"; 656 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 657 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 658 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 659 pinctrl-names = "default"; 660 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 661 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 662 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 663 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 664 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 665 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 666 interconnect-names = "qup-core", "qup-config", "qup-memory"; 667 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 668 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 669 dma-names = "tx", "rx"; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 673 status = "disabled"; 674 }; 675 676 i2c2: i2c@988000 { 677 compatible = "qcom,geni-i2c"; 678 reg = <0x0 0x00988000 0x0 0x4000>; 679 clock-names = "se"; 680 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 681 pinctrl-0 = <&qup_i2c2_data_clk>; 682 pinctrl-names = "default"; 683 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 687 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 688 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 689 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 690 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 691 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 692 interconnect-names = "qup-core", "qup-config", "qup-memory"; 693 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 694 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 695 dma-names = "tx", "rx"; 696 697 status = "disabled"; 698 }; 699 700 spi2: spi@988000 { 701 compatible = "qcom,geni-spi"; 702 reg = <0x0 0x00988000 0x0 0x4000>; 703 clock-names = "se"; 704 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 705 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 706 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 707 pinctrl-names = "default"; 708 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 709 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 710 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 711 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 712 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 713 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 714 interconnect-names = "qup-core", "qup-config", "qup-memory"; 715 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 716 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 717 dma-names = "tx", "rx"; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 721 status = "disabled"; 722 }; 723 724 725 i2c3: i2c@98c000 { 726 compatible = "qcom,geni-i2c"; 727 reg = <0x0 0x0098c000 0x0 0x4000>; 728 clock-names = "se"; 729 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 730 pinctrl-0 = <&qup_i2c3_data_clk>; 731 pinctrl-names = "default"; 732 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 736 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 737 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 738 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 739 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 740 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 741 interconnect-names = "qup-core", "qup-config", "qup-memory"; 742 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 743 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 744 dma-names = "tx", "rx"; 745 746 status = "disabled"; 747 }; 748 749 spi3: spi@98c000 { 750 compatible = "qcom,geni-spi"; 751 reg = <0x0 0x0098c000 0x0 0x4000>; 752 clock-names = "se"; 753 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 754 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 755 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs0>; 756 pinctrl-names = "default"; 757 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 758 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 759 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 760 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 761 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 762 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 763 interconnect-names = "qup-core", "qup-config", "qup-memory"; 764 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 765 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 766 dma-names = "tx", "rx"; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 770 status = "disabled"; 771 }; 772 773 i2c4: i2c@990000 { 774 compatible = "qcom,geni-i2c"; 775 reg = <0x0 0x00990000 0x0 0x4000>; 776 clock-names = "se"; 777 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 778 pinctrl-0 = <&qup_i2c4_data_clk>; 779 pinctrl-names = "default"; 780 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 784 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 785 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 786 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 787 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 788 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 789 interconnect-names = "qup-core", "qup-config", "qup-memory"; 790 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 791 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 792 dma-names = "tx", "rx"; 793 794 status = "disabled"; 795 }; 796 797 spi4: spi@990000 { 798 compatible = "qcom,geni-spi"; 799 reg = <0x0 0x00990000 0x0 0x4000>; 800 clock-names = "se"; 801 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 802 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 803 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs0>; 804 pinctrl-names = "default"; 805 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 806 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 807 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 808 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 809 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 810 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 811 interconnect-names = "qup-core", "qup-config", "qup-memory"; 812 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 813 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 814 dma-names = "tx", "rx"; 815 #address-cells = <1>; 816 #size-cells = <0>; 817 818 status = "disabled"; 819 }; 820 821 i2c5: i2c@994000 { 822 compatible = "qcom,geni-i2c"; 823 reg = <0x0 0x00994000 0x0 0x4000>; 824 clock-names = "se"; 825 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 826 pinctrl-0 = <&qup_i2c5_data_clk>; 827 pinctrl-names = "default"; 828 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 832 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 833 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 834 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 835 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 836 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 837 interconnect-names = "qup-core", "qup-config", "qup-memory"; 838 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 839 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 840 dma-names = "tx", "rx"; 841 842 status = "disabled"; 843 }; 844 845 spi5: spi@994000 { 846 compatible = "qcom,geni-spi"; 847 reg = <0x0 0x00994000 0x0 0x4000>; 848 clock-names = "se"; 849 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 850 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 851 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 852 pinctrl-names = "default"; 853 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 854 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 855 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 856 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 857 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 858 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 859 interconnect-names = "qup-core", "qup-config", "qup-memory"; 860 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 861 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 862 dma-names = "tx", "rx"; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 866 status = "disabled"; 867 }; 868 }; 869 870 gpi_dma1: dma-controller@a00000 { 871 compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma"; 872 #dma-cells = <3>; 873 reg = <0x0 0x00a00000 0x0 0x60000>; 874 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 886 dma-channels = <12>; 887 dma-channel-mask = <0x7e>; 888 iommus = <&apps_smmu 0x16 0x0>; 889 890 status = "disabled"; 891 }; 892 893 qupv3_id_1: geniqup@ac0000 { 894 compatible = "qcom,geni-se-qup"; 895 reg = <0x0 0x00ac0000 0x0 0x6000>; 896 clock-names = "m-ahb", "s-ahb"; 897 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 898 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 899 iommus = <&apps_smmu 0x3 0x0>; 900 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 901 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 902 interconnect-names = "qup-core"; 903 #address-cells = <2>; 904 #size-cells = <2>; 905 ranges; 906 907 status = "disabled"; 908 909 i2c6: i2c@a80000 { 910 compatible = "qcom,geni-i2c"; 911 reg = <0x0 0x00a80000 0x0 0x4000>; 912 clock-names = "se"; 913 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 914 pinctrl-0 = <&qup_i2c6_data_clk>; 915 pinctrl-names = "default"; 916 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 920 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 921 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 922 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 923 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 924 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 925 interconnect-names = "qup-core", "qup-config", "qup-memory"; 926 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 927 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 928 dma-names = "tx", "rx"; 929 930 status = "disabled"; 931 }; 932 933 spi6: spi@a80000 { 934 compatible = "qcom,geni-spi"; 935 reg = <0x0 0x00a80000 0x0 0x4000>; 936 clock-names = "se"; 937 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 938 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 939 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 940 pinctrl-names = "default"; 941 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 942 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 943 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 944 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 945 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 946 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 947 interconnect-names = "qup-core", "qup-config", "qup-memory"; 948 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 949 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 950 dma-names = "tx", "rx"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 954 status = "disabled"; 955 }; 956 957 i2c7: i2c@a84000 { 958 compatible = "qcom,geni-i2c"; 959 reg = <0x0 0x00a84000 0x0 0x4000>; 960 clock-names = "se"; 961 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 962 pinctrl-0 = <&qup_i2c7_data_clk>; 963 pinctrl-names = "default"; 964 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 968 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 969 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 970 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 971 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 972 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 973 interconnect-names = "qup-core", "qup-config", "qup-memory"; 974 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 975 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 976 dma-names = "tx", "rx"; 977 978 status = "disabled"; 979 }; 980 981 spi7: spi@a84000 { 982 compatible = "qcom,geni-spi"; 983 reg = <0x0 0x00a84000 0x0 0x4000>; 984 clock-names = "se"; 985 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 986 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 987 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 988 pinctrl-names = "default"; 989 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 990 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 991 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 992 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 993 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 995 interconnect-names = "qup-core", "qup-config", "qup-memory"; 996 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 997 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 998 dma-names = "tx", "rx"; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 1002 status = "disabled"; 1003 }; 1004 1005 uart7: serial@a84000 { 1006 compatible = "qcom,geni-uart"; 1007 reg = <0x0 0x00a84000 0x0 0x4000>; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1010 pinctrl-0 = <&qup_uart7_default>; 1011 pinctrl-names = "default"; 1012 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1014 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1015 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1016 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; 1017 interconnect-names = "qup-core", "qup-config"; 1018 1019 status = "disabled"; 1020 }; 1021 1022 i2c8: i2c@a88000 { 1023 compatible = "qcom,geni-i2c"; 1024 reg = <0x0 0x00a88000 0x0 0x4000>; 1025 clock-names = "se"; 1026 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1027 pinctrl-0 = <&qup_i2c8_data_clk>; 1028 pinctrl-names = "default"; 1029 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1030 #address-cells = <1>; 1031 #size-cells = <0>; 1032 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1033 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1034 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1035 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1036 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1037 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1038 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1039 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1040 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1041 dma-names = "tx", "rx"; 1042 1043 status = "disabled"; 1044 }; 1045 1046 spi8: spi@a88000 { 1047 compatible = "qcom,geni-spi"; 1048 reg = <0x0 0x00a88000 0x0 0x4000>; 1049 clock-names = "se"; 1050 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1051 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1052 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1053 pinctrl-names = "default"; 1054 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1055 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1056 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1057 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1058 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1059 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1060 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1061 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1062 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1063 dma-names = "tx", "rx"; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 1067 status = "disabled"; 1068 }; 1069 1070 i2c9: i2c@a8c000 { 1071 compatible = "qcom,geni-i2c"; 1072 reg = <0x0 0x00a8c000 0x0 0x4000>; 1073 clock-names = "se"; 1074 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1075 pinctrl-0 = <&qup_i2c9_data_clk>; 1076 pinctrl-names = "default"; 1077 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1081 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1082 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1083 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1084 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1085 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1086 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1087 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1088 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1089 dma-names = "tx", "rx"; 1090 1091 status = "disabled"; 1092 }; 1093 1094 spi9: spi@a8c000 { 1095 compatible = "qcom,geni-spi"; 1096 reg = <0x0 0x00a8c000 0x0 0x4000>; 1097 clock-names = "se"; 1098 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1099 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1100 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1101 pinctrl-names = "default"; 1102 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1103 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1104 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1105 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1106 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1107 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1108 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1109 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1110 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1111 dma-names = "tx", "rx"; 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 1115 status = "disabled"; 1116 }; 1117 1118 i2c10: i2c@a90000 { 1119 compatible = "qcom,geni-i2c"; 1120 reg = <0x0 0x00a90000 0x0 0x4000>; 1121 clock-names = "se"; 1122 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1123 pinctrl-0 = <&qup_i2c10_data_clk>; 1124 pinctrl-names = "default"; 1125 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1129 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1130 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1131 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1132 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1133 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1134 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1135 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1136 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1137 dma-names = "tx", "rx"; 1138 1139 status = "disabled"; 1140 }; 1141 1142 spi10: spi@a90000 { 1143 compatible = "qcom,geni-spi"; 1144 reg = <0x0 0x00a90000 0x0 0x4000>; 1145 clock-names = "se"; 1146 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1147 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1148 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1149 pinctrl-names = "default"; 1150 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1151 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1152 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1153 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1154 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1155 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1156 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1157 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1158 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1159 dma-names = "tx", "rx"; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 1163 status = "disabled"; 1164 }; 1165 1166 i2c11: i2c@a94000 { 1167 compatible = "qcom,geni-i2c"; 1168 reg = <0x0 0x00a94000 0x0 0x4000>; 1169 clock-names = "se"; 1170 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1171 pinctrl-0 = <&qup_i2c11_data_clk>; 1172 pinctrl-names = "default"; 1173 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1177 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1178 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1179 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1180 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1181 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1182 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1183 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1184 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1185 dma-names = "tx", "rx"; 1186 1187 status = "disabled"; 1188 }; 1189 1190 spi11: spi@a94000 { 1191 compatible = "qcom,geni-spi"; 1192 reg = <0x0 0x00a94000 0x0 0x4000>; 1193 clock-names = "se"; 1194 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1195 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1196 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1197 pinctrl-names = "default"; 1198 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1199 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1200 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1201 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1202 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1203 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1204 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1205 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1206 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1207 dma-names = "tx", "rx"; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 1211 status = "disabled"; 1212 }; 1213 1214 uart11: serial@a94000 { 1215 compatible = "qcom,geni-debug-uart"; 1216 reg = <0x0 0x00a94000 0x0 0x4000>; 1217 clock-names = "se"; 1218 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1219 pinctrl-0 = <&qup_uart11_default>; 1220 pinctrl-names = "default"; 1221 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1222 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1223 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1224 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1225 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1226 interconnect-names = "qup-core", 1227 "qup-config"; 1228 1229 status = "disabled"; 1230 }; 1231 }; 1232 1233 config_noc: interconnect@1500000 { 1234 compatible = "qcom,sar2130p-config-noc"; 1235 reg = <0x0 0x01500000 0x0 0x10>; 1236 #interconnect-cells = <2>; 1237 qcom,bcm-voters = <&apps_bcm_voter>; 1238 }; 1239 1240 system_noc: interconnect@1680000 { 1241 compatible = "qcom,sar2130p-system-noc"; 1242 reg = <0x0 0x01680000 0x0 0x29080>; 1243 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1244 #interconnect-cells = <2>; 1245 qcom,bcm-voters = <&apps_bcm_voter>; 1246 }; 1247 1248 pcie_noc: interconnect@16c0000 { 1249 compatible = "qcom,sar2130p-pcie-anoc"; 1250 reg = <0x0 0x016c0000 0x0 0xa080>; 1251 clocks = <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1252 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1253 #interconnect-cells = <2>; 1254 qcom,bcm-voters = <&apps_bcm_voter>; 1255 }; 1256 1257 mmss_noc: interconnect@1740000 { 1258 compatible = "qcom,sar2130p-mmss-noc"; 1259 reg = <0x0 0x01740000 0x0 0x1f100>; 1260 #interconnect-cells = <2>; 1261 qcom,bcm-voters = <&apps_bcm_voter>; 1262 }; 1263 1264 pcie0: pcie@1c00000 { 1265 device_type = "pci"; 1266 compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550"; 1267 reg = <0x0 0x01c00000 0x0 0x3000>, 1268 <0x0 0x60000000 0x0 0xf1d>, 1269 <0x0 0x60000f20 0x0 0xa8>, 1270 <0x0 0x60001000 0x0 0x1000>, 1271 <0x0 0x60100000 0x0 0x100000>, 1272 <0x0 0x01c0c000 0x0 0x1000>; 1273 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1274 #address-cells = <3>; 1275 #size-cells = <2>; 1276 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1277 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1278 bus-range = <0x00 0xff>; 1279 1280 dma-coherent; 1281 1282 linux,pci-domain = <0>; 1283 num-lanes = <2>; 1284 1285 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1293 interrupt-names = "msi0", 1294 "msi1", 1295 "msi2", 1296 "msi3", 1297 "msi4", 1298 "msi5", 1299 "msi6", 1300 "msi7"; 1301 #interrupt-cells = <1>; 1302 interrupt-map-mask = <0 0 0 0x7>; 1303 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1304 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1305 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1306 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1307 1308 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1309 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1310 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1311 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1312 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1313 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 1314 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1315 clock-names = "aux", 1316 "cfg", 1317 "bus_master", 1318 "bus_slave", 1319 "slave_q2a", 1320 "ddrss_sf_tbu", 1321 "noc_aggr"; 1322 1323 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 1324 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1325 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1326 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 1327 interconnect-names = "pcie-mem", "cpu-pcie"; 1328 1329 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1330 <0x100 &apps_smmu 0x1c01 0x1>; 1331 1332 resets = <&gcc GCC_PCIE_0_BCR>; 1333 reset-names = "pci"; 1334 1335 power-domains = <&gcc PCIE_0_GDSC>; 1336 1337 phys = <&pcie0_phy>; 1338 phy-names = "pciephy"; 1339 1340 status = "disabled"; 1341 1342 pcieport0: pcie@0 { 1343 device_type = "pci"; 1344 reg = <0x0 0x0 0x0 0x0 0x0>; 1345 bus-range = <0x01 0xff>; 1346 1347 #address-cells = <3>; 1348 #size-cells = <2>; 1349 ranges; 1350 }; 1351 }; 1352 1353 pcie0_phy: phy@1c06000 { 1354 compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy"; 1355 reg = <0x0 0x01c06000 0x0 0x2000>; 1356 1357 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1358 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1359 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1360 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1361 <&gcc GCC_PCIE_0_PIPE_CLK>; 1362 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1363 "pipe"; 1364 1365 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1366 reset-names = "phy"; 1367 1368 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1369 assigned-clock-rates = <100000000>; 1370 1371 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1372 1373 #clock-cells = <0>; 1374 clock-output-names = "pcie0_pipe_clk"; 1375 1376 #phy-cells = <0>; 1377 1378 status = "disabled"; 1379 }; 1380 1381 pcie1: pcie@1c08000 { 1382 device_type = "pci"; 1383 compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550"; 1384 reg = <0x0 0x01c08000 0x0 0x3000>, 1385 <0x0 0x40000000 0x0 0xf1d>, 1386 <0x0 0x40000f20 0x0 0xa8>, 1387 <0x0 0x40001000 0x0 0x1000>, 1388 <0x0 0x40100000 0x0 0x100000>, 1389 <0x0 0x01c0b000 0x0 0x1000>; 1390 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1391 #address-cells = <3>; 1392 #size-cells = <2>; 1393 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1394 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1395 bus-range = <0x00 0xff>; 1396 1397 dma-coherent; 1398 1399 linux,pci-domain = <1>; 1400 num-lanes = <2>; 1401 1402 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1410 interrupt-names = "msi0", 1411 "msi1", 1412 "msi2", 1413 "msi3", 1414 "msi4", 1415 "msi5", 1416 "msi6", 1417 "msi7"; 1418 #interrupt-cells = <1>; 1419 interrupt-map-mask = <0 0 0 0x7>; 1420 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1421 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1422 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1423 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1424 1425 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1426 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1427 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1428 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1429 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1430 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 1431 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1432 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, 1433 <&gcc GCC_QMIP_PCIE_AHB_CLK>; 1434 clock-names = "aux", 1435 "cfg", 1436 "bus_master", 1437 "bus_slave", 1438 "slave_q2a", 1439 "ddrss_sf_tbu", 1440 "noc_aggr", 1441 "cnoc_sf_axi", 1442 "qmip_pcie_ahb"; 1443 1444 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1445 assigned-clock-rates = <19200000>; 1446 1447 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 1448 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1449 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1450 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 1451 interconnect-names = "pcie-mem", "cpu-pcie"; 1452 1453 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1454 <0x100 &apps_smmu 0x1e01 0x1>; 1455 1456 resets = <&gcc GCC_PCIE_1_BCR>, 1457 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1458 reset-names = "pci", "link_down"; 1459 1460 power-domains = <&gcc PCIE_1_GDSC>; 1461 1462 phys = <&pcie1_phy>; 1463 phy-names = "pciephy"; 1464 1465 status = "disabled"; 1466 1467 pcie@0 { 1468 device_type = "pci"; 1469 reg = <0x0 0x0 0x0 0x0 0x0>; 1470 bus-range = <0x01 0xff>; 1471 1472 #address-cells = <3>; 1473 #size-cells = <2>; 1474 ranges; 1475 }; 1476 }; 1477 1478 pcie1_ep: pcie-ep@1c08000 { 1479 compatible = "qcom,sar2130p-pcie-ep"; 1480 reg = <0x0 0x01c08000 0x0 0x3000>, 1481 <0x0 0x40000000 0x0 0xf1d>, 1482 <0x0 0x40000f20 0x0 0xa8>, 1483 <0x0 0x40001000 0x0 0x1000>, 1484 <0x0 0x40200000 0x0 0x1000000>, 1485 <0x0 0x01c0b000 0x0 0x1000>, 1486 <0x0 0x40002000 0x0 0x2000>; 1487 reg-names = "parf", 1488 "dbi", 1489 "elbi", 1490 "atu", 1491 "addr_space", 1492 "mmio", 1493 "dma"; 1494 1495 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1496 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1497 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1498 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1499 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1500 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 1501 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1502 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, 1503 <&gcc GCC_QMIP_PCIE_AHB_CLK>; 1504 clock-names = "aux", 1505 "cfg", 1506 "bus_master", 1507 "bus_slave", 1508 "slave_q2a", 1509 "ddrss_sf_tbu", 1510 "aggre_noc_axi", 1511 "cnoc_sf_axi", 1512 "qmip_pcie_ahb"; 1513 1514 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1517 interrupt-names = "global", 1518 "doorbell", 1519 "dma"; 1520 1521 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 1522 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1523 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1524 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1525 interconnect-names = "pcie-mem", 1526 "cpu-pcie"; 1527 iommus = <&apps_smmu 0x1e00 0x1>; 1528 resets = <&gcc GCC_PCIE_1_BCR>; 1529 reset-names = "core"; 1530 power-domains = <&gcc PCIE_1_GDSC>; 1531 phys = <&pcie1_phy>; 1532 phy-names = "pciephy"; 1533 1534 num-lanes = <2>; 1535 1536 status = "disabled"; 1537 }; 1538 1539 pcie1_phy: phy@1c0e000 { 1540 compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy"; 1541 reg = <0x0 0x01c0e000 0x0 0x2000>; 1542 1543 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1544 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1545 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1546 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1547 <&gcc GCC_PCIE_1_PIPE_CLK>; 1548 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1549 "pipe"; 1550 1551 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1552 reset-names = "phy"; 1553 1554 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1555 assigned-clock-rates = <100000000>; 1556 1557 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1558 1559 #clock-cells = <0>; 1560 clock-output-names = "pcie1_pipe_clk"; 1561 1562 #phy-cells = <0>; 1563 1564 status = "disabled"; 1565 }; 1566 1567 tcsr_mutex: hwlock@1f40000 { 1568 compatible = "qcom,tcsr-mutex"; 1569 reg = <0x0 0x01f40000 0x0 0x20000>; 1570 1571 #hwlock-cells = <1>; 1572 }; 1573 1574 tcsr: clock-controller@1fc0000 { 1575 compatible = "qcom,sar2130p-tcsr", "syscon"; 1576 reg = <0x0 0x01fc0000 0x0 0x30000>; 1577 clocks = <&rpmhcc RPMH_CXO_CLK>; 1578 #clock-cells = <1>; 1579 #reset-cells = <1>; 1580 }; 1581 1582 remoteproc_adsp: remoteproc@3000000 { 1583 compatible = "qcom,sar2130p-adsp-pas"; 1584 reg = <0x0 0x03000000 0x0 0x10000>; 1585 1586 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1587 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1588 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1589 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1590 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1591 interrupt-names = "wdog", "fatal", "ready", 1592 "handover", "stop-ack"; 1593 1594 clocks = <&rpmhcc RPMH_CXO_CLK>; 1595 clock-names = "xo"; 1596 1597 power-domains = <&rpmhpd RPMHPD_LCX>, 1598 <&rpmhpd RPMHPD_LMX>; 1599 power-domain-names = "lcx", "lmx"; 1600 1601 memory-region = <&adsp_mem>; 1602 1603 qcom,qmp = <&aoss_qmp>; 1604 1605 qcom,smem-states = <&smp2p_adsp_out 0>; 1606 qcom,smem-state-names = "stop"; 1607 1608 status = "disabled"; 1609 1610 remoteproc_adsp_glink: glink-edge { 1611 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1612 IPCC_MPROC_SIGNAL_GLINK_QMP 1613 IRQ_TYPE_EDGE_RISING>; 1614 mboxes = <&ipcc IPCC_CLIENT_LPASS 1615 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1616 1617 label = "lpass"; 1618 qcom,remote-pid = <2>; 1619 1620 gpr { 1621 compatible = "qcom,gpr"; 1622 qcom,glink-channels = "adsp_apps"; 1623 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 1624 qcom,intents = <512 20>; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 1628 q6apm: service@1 { 1629 compatible = "qcom,q6apm"; 1630 reg = <GPR_APM_MODULE_IID>; 1631 #sound-dai-cells = <0>; 1632 qcom,protection-domain = "avs/audio", 1633 "msm/adsp/audio_pd"; 1634 1635 q6apmdai: dais { 1636 compatible = "qcom,q6apm-dais"; 1637 iommus = <&apps_smmu 0x1801 0x0>; 1638 }; 1639 1640 q6apmbedai: bedais { 1641 compatible = "qcom,q6apm-lpass-dais"; 1642 #sound-dai-cells = <1>; 1643 }; 1644 }; 1645 1646 q6prm: service@2 { 1647 compatible = "qcom,q6prm"; 1648 reg = <GPR_PRM_MODULE_IID>; 1649 qcom,protection-domain = "avs/audio", 1650 "msm/adsp/audio_pd"; 1651 1652 q6prmcc: clock-controller { 1653 compatible = "qcom,q6prm-lpass-clocks"; 1654 #clock-cells = <2>; 1655 }; 1656 }; 1657 }; 1658 1659 fastrpc { 1660 compatible = "qcom,fastrpc"; 1661 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1662 label = "adsp"; 1663 qcom,non-secure-domain; 1664 #address-cells = <1>; 1665 #size-cells = <0>; 1666 1667 compute-cb@3 { 1668 compatible = "qcom,fastrpc-compute-cb"; 1669 reg = <3>; 1670 iommus = <&apps_smmu 0x1803 0x0>; 1671 }; 1672 1673 compute-cb@4 { 1674 compatible = "qcom,fastrpc-compute-cb"; 1675 reg = <4>; 1676 iommus = <&apps_smmu 0x1804 0x0>; 1677 }; 1678 1679 compute-cb@5 { 1680 compatible = "qcom,fastrpc-compute-cb"; 1681 reg = <5>; 1682 iommus = <&apps_smmu 0x1805 0x0>; 1683 }; 1684 1685 compute-cb@6 { 1686 compatible = "qcom,fastrpc-compute-cb"; 1687 reg = <6>; 1688 iommus = <&apps_smmu 0x1806 0x0>; 1689 }; 1690 }; 1691 }; 1692 }; 1693 1694 gpu: gpu@3d00000 { 1695 compatible = "qcom,adreno-621.0", "qcom,adreno"; 1696 reg = <0x0 0x03d00000 0x0 0x40000>, 1697 <0x0 0x03d9e000 0x0 0x2000>, 1698 <0x0 0x03d61000 0x0 0x800>; 1699 reg-names = "kgsl_3d0_reg_memory", 1700 "cx_mem", 1701 "cx_dbgc"; 1702 1703 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1704 1705 iommus = <&adreno_smmu 0 0x401>; 1706 1707 operating-points-v2 = <&gpu_opp_table>; 1708 1709 qcom,gmu = <&gmu>; 1710 1711 nvmem-cells = <&gpu_speed_bin>; 1712 nvmem-cell-names = "speed_bin"; 1713 #cooling-cells = <2>; 1714 1715 status = "disabled"; 1716 1717 gpu_zap_shader: zap-shader { 1718 memory-region = <&gpu_micro_code_mem>; 1719 }; 1720 1721 gpu_opp_table: opp-table { 1722 compatible = "operating-points-v2"; 1723 1724 opp-843000000 { 1725 opp-hz = /bits/ 64 <843000000>; 1726 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1727 opp-supported-hw = <0x1>; 1728 }; 1729 1730 opp-780000000 { 1731 opp-hz = /bits/ 64 <780000000>; 1732 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1733 opp-supported-hw = <0x1>; 1734 }; 1735 1736 opp-644000000 { 1737 opp-hz = /bits/ 64 <644000000>; 1738 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1739 opp-supported-hw = <0x3>; 1740 }; 1741 1742 opp-570000000 { 1743 opp-hz = /bits/ 64 <570000000>; 1744 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1745 opp-supported-hw = <0x3>; 1746 }; 1747 1748 opp-450000000 { 1749 opp-hz = /bits/ 64 <450000000>; 1750 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1751 opp-supported-hw = <0x3>; 1752 }; 1753 1754 opp-320000000 { 1755 opp-hz = /bits/ 64 <320000000>; 1756 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1757 opp-supported-hw = <0x3>; 1758 }; 1759 1760 opp-235000000 { 1761 opp-hz = /bits/ 64 <235000000>; 1762 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 1763 opp-supported-hw = <0x3>; 1764 }; 1765 }; 1766 }; 1767 1768 gmu: gmu@3d6a000 { 1769 compatible = "qcom,adreno-gmu-621.0", "qcom,adreno-gmu"; 1770 reg = <0x0 0x03d6a000 0x0 0x35000>, 1771 <0x0 0x03de0000 0x0 0x10000>, 1772 <0x0 0x0b290000 0x0 0x10000>; 1773 reg-names = "gmu", "rscc", "gmu_pdc"; 1774 1775 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1777 interrupt-names = "hfi", "gmu"; 1778 1779 clocks = <&gpucc GPU_CC_AHB_CLK>, 1780 <&gpucc GPU_CC_CX_GMU_CLK>, 1781 <&gpucc GPU_CC_CXO_CLK>, 1782 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1783 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1784 <&gpucc GPU_CC_HUB_CX_INT_CLK>; 1785 clock-names = "ahb", 1786 "gmu", 1787 "cxo", 1788 "axi", 1789 "memnoc", 1790 "hub"; 1791 1792 power-domains = <&gpucc GPU_CX_GDSC>, 1793 <&gpucc GPU_GX_GDSC>; 1794 power-domain-names = "cx", 1795 "gx"; 1796 1797 iommus = <&adreno_smmu 5 0x400>; 1798 1799 qcom,qmp = <&aoss_qmp>; 1800 1801 operating-points-v2 = <&gmu_opp_table>; 1802 1803 gmu_opp_table: opp-table { 1804 compatible = "operating-points-v2"; 1805 1806 opp-220000000 { 1807 opp-hz = /bits/ 64 <220000000>; 1808 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1809 }; 1810 1811 opp-550000000 { 1812 opp-hz = /bits/ 64 <550000000>; 1813 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1814 }; 1815 }; 1816 }; 1817 1818 gpucc: clock-controller@3d90000 { 1819 compatible = "qcom,sar2130p-gpucc"; 1820 reg = <0x0 0x03d90000 0x0 0xa000>; 1821 1822 clocks = <&rpmhcc RPMH_CXO_CLK>, 1823 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1824 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1825 1826 #clock-cells = <1>; 1827 #reset-cells = <1>; 1828 #power-domain-cells = <1>; 1829 }; 1830 1831 adreno_smmu: iommu@3da0000 { 1832 compatible = "qcom,sar2130p-smmu-500", "qcom,adreno-smmu", 1833 "qcom,smmu-500", "arm,mmu-500"; 1834 reg = <0x0 0x03da0000 0x0 0x10000>; 1835 #iommu-cells = <2>; 1836 #global-interrupts = <1>; 1837 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 1846 1847 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1848 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1849 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1850 <&gpucc GPU_CC_AHB_CLK>; 1851 clock-names = "hlos", 1852 "bus", 1853 "iface", 1854 "ahb"; 1855 power-domains = <&gpucc GPU_CX_GDSC>; 1856 dma-coherent; 1857 }; 1858 1859 usb_1_hsphy: phy@88e3000 { 1860 compatible = "qcom,sar2130p-snps-eusb2-phy", 1861 "qcom,sm8550-snps-eusb2-phy"; 1862 reg = <0x0 0x088e3000 0x0 0x154>; 1863 #phy-cells = <0>; 1864 1865 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 1866 clock-names = "ref"; 1867 1868 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1869 1870 status = "disabled"; 1871 }; 1872 1873 usb_dp_qmpphy: phy@88e8000 { 1874 compatible = "qcom,sar2130p-qmp-usb3-dp-phy"; 1875 reg = <0x0 0x088e8000 0x0 0x3000>; 1876 1877 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1878 <&rpmhcc RPMH_CXO_CLK>, 1879 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1880 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1881 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1882 1883 power-domains = <&gcc USB3_PHY_GDSC>; 1884 1885 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1886 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1887 reset-names = "phy", "common"; 1888 1889 #clock-cells = <1>; 1890 #phy-cells = <1>; 1891 1892 orientation-switch; 1893 1894 status = "disabled"; 1895 1896 ports { 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 1900 port@0 { 1901 reg = <0>; 1902 1903 usb_dp_qmpphy_out: endpoint { 1904 }; 1905 }; 1906 1907 port@1 { 1908 reg = <1>; 1909 1910 usb_dp_qmpphy_usb_ss_in: endpoint { 1911 remote-endpoint = <&usb_1_dwc3_ss>; 1912 }; 1913 }; 1914 1915 port@2 { 1916 reg = <2>; 1917 1918 usb_dp_qmpphy_dp_in: endpoint { 1919 remote-endpoint = <&mdss_dp0_out>; 1920 }; 1921 }; 1922 }; 1923 }; 1924 1925 usb_1: usb@a6f8800 { 1926 compatible = "qcom,sar2130p-dwc3", "qcom,dwc3"; 1927 reg = <0x0 0x0a6f8800 0x0 0x400>; 1928 #address-cells = <2>; 1929 #size-cells = <2>; 1930 ranges; 1931 1932 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1933 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1934 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1935 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1936 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1937 <&tcsr TCSR_USB3_CLKREF_EN>; 1938 clock-names = "cfg_noc", 1939 "core", 1940 "iface", 1941 "sleep", 1942 "mock_utmi", 1943 "xo"; 1944 1945 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1946 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1947 assigned-clock-rates = <19200000>, <200000000>; 1948 1949 interrupts-extended = <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1950 <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1951 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1952 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1953 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1954 interrupt-names = "pwr_event", 1955 "hs_phy_irq", 1956 "dp_hs_phy_irq", 1957 "dm_hs_phy_irq", 1958 "ss_phy_irq"; 1959 1960 power-domains = <&gcc USB30_PRIM_GDSC>; 1961 required-opps = <&rpmhpd_opp_nom>; 1962 1963 resets = <&gcc GCC_USB30_PRIM_BCR>; 1964 1965 interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 1966 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1967 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1968 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 1969 interconnect-names = "usb-ddr", "apps-usb"; 1970 1971 status = "disabled"; 1972 1973 usb_1_dwc3: usb@a600000 { 1974 compatible = "snps,dwc3"; 1975 reg = <0x0 0x0a600000 0x0 0xcd00>; 1976 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 1977 iommus = <&apps_smmu 0x20 0x0>; 1978 phys = <&usb_1_hsphy>, 1979 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 1980 phy-names = "usb2-phy", "usb3-phy"; 1981 1982 snps,has-lpm-erratum; 1983 snps,hird-threshold = /bits/ 8 <0x0>; 1984 snps,is-utmi-l1-suspend; 1985 snps,dis-u1-entry-quirk; 1986 snps,dis-u2-entry-quirk; 1987 snps,dis_u2_susphy_quirk; 1988 snps,dis_u3_susphy_quirk; 1989 snps,parkmode-disable-ss-quirk; 1990 1991 tx-fifo-resize; 1992 dma-coherent; 1993 usb-role-switch; 1994 1995 ports { 1996 #address-cells = <1>; 1997 #size-cells = <0>; 1998 1999 port@0 { 2000 reg = <0>; 2001 2002 usb_1_dwc3_hs: endpoint { 2003 }; 2004 }; 2005 2006 port@1 { 2007 reg = <1>; 2008 2009 usb_1_dwc3_ss: endpoint { 2010 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 2011 }; 2012 }; 2013 }; 2014 }; 2015 }; 2016 2017 mdss: display-subsystem@ae00000 { 2018 compatible = "qcom,sar2130p-mdss"; 2019 reg = <0x0 0x0ae00000 0x0 0x1000>; 2020 reg-names = "mdss"; 2021 2022 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2023 interrupt-controller; 2024 #interrupt-cells = <1>; 2025 2026 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2027 <&gcc GCC_DISP_AHB_CLK>, 2028 <&gcc GCC_DISP_HF_AXI_CLK>, 2029 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2030 2031 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2032 2033 power-domains = <&dispcc MDSS_GDSC>; 2034 2035 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ACTIVE_ONLY 2036 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 2037 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2038 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2039 interconnect-names = "mdp0-mem", "cpu-cfg"; 2040 2041 iommus = <&apps_smmu 0x2000 0x402>; 2042 2043 #address-cells = <2>; 2044 #size-cells = <2>; 2045 ranges; 2046 2047 status = "disabled"; 2048 2049 mdss_mdp: display-controller@ae01000 { 2050 compatible = "qcom,sar2130p-dpu"; 2051 reg = <0x0 0x0ae01000 0x0 0x8f000>, 2052 <0x0 0x0aeb0000 0x0 0x2008>; 2053 reg-names = "mdp", 2054 "vbif"; 2055 2056 interrupt-parent = <&mdss>; 2057 interrupts = <0>; 2058 2059 clocks = <&gcc GCC_DISP_AHB_CLK>, 2060 <&gcc GCC_DISP_HF_AXI_CLK>, 2061 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2062 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2063 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2064 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2065 clock-names = "bus", 2066 "nrt_bus", 2067 "iface", 2068 "lut", 2069 "core", 2070 "vsync"; 2071 2072 power-domains = <&rpmhpd RPMHPD_MMCX>; 2073 2074 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2075 assigned-clock-rates = <19200000>; 2076 2077 operating-points-v2 = <&mdp_opp_table>; 2078 2079 ports { 2080 #address-cells = <1>; 2081 #size-cells = <0>; 2082 2083 port@0 { 2084 reg = <0>; 2085 2086 dpu_intf1_out: endpoint { 2087 remote-endpoint = <&mdss_dsi0_in>; 2088 }; 2089 }; 2090 2091 port@1 { 2092 reg = <1>; 2093 2094 dpu_intf2_out: endpoint { 2095 remote-endpoint = <&mdss_dsi1_in>; 2096 }; 2097 }; 2098 2099 port@2 { 2100 reg = <2>; 2101 2102 dpu_intf0_out: endpoint { 2103 remote-endpoint = <&mdss_dp0_in>; 2104 }; 2105 }; 2106 }; 2107 2108 mdp_opp_table: opp-table { 2109 compatible = "operating-points-v2"; 2110 2111 opp-200000000 { 2112 opp-hz = /bits/ 64 <200000000>; 2113 required-opps = <&rpmhpd_opp_low_svs>; 2114 }; 2115 2116 opp-325000000 { 2117 opp-hz = /bits/ 64 <325000000>; 2118 required-opps = <&rpmhpd_opp_svs>; 2119 }; 2120 2121 opp-514000000 { 2122 opp-hz = /bits/ 64 <514000000>; 2123 required-opps = <&rpmhpd_opp_turbo>; 2124 }; 2125 }; 2126 }; 2127 2128 mdss_dp0: displayport-controller@ae90000 { 2129 compatible = "qcom,sar2130p-dp", 2130 "qcom,sm8350-dp"; 2131 reg = <0x0 0xae90000 0x0 0x200>, 2132 <0x0 0xae90200 0x0 0x200>, 2133 <0x0 0xae90400 0x0 0xc00>, 2134 <0x0 0xae91000 0x0 0x400>, 2135 <0x0 0xae91400 0x0 0x400>; 2136 interrupt-parent = <&mdss>; 2137 interrupts = <12>; 2138 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2139 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2140 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2141 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2142 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 2143 clock-names = "core_iface", 2144 "core_aux", 2145 "ctrl_link", 2146 "ctrl_link_iface", 2147 "stream_pixel"; 2148 2149 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2150 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 2151 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2152 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2153 2154 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 2155 phy-names = "dp"; 2156 2157 #sound-dai-cells = <0>; 2158 2159 operating-points-v2 = <&dp_opp_table>; 2160 power-domains = <&rpmhpd RPMHPD_MMCX>; 2161 2162 status = "disabled"; 2163 2164 ports { 2165 #address-cells = <1>; 2166 #size-cells = <0>; 2167 2168 port@0 { 2169 reg = <0>; 2170 2171 mdss_dp0_in: endpoint { 2172 remote-endpoint = <&dpu_intf0_out>; 2173 }; 2174 }; 2175 2176 port@1 { 2177 reg = <1>; 2178 2179 mdss_dp0_out: endpoint { 2180 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 2181 }; 2182 }; 2183 }; 2184 2185 dp_opp_table: opp-table { 2186 compatible = "operating-points-v2"; 2187 2188 opp-162000000 { 2189 opp-hz = /bits/ 64 <162000000>; 2190 required-opps = <&rpmhpd_opp_low_svs_d1>; 2191 }; 2192 2193 opp-270000000 { 2194 opp-hz = /bits/ 64 <270000000>; 2195 required-opps = <&rpmhpd_opp_low_svs>; 2196 }; 2197 2198 opp-540000000 { 2199 opp-hz = /bits/ 64 <540000000>; 2200 required-opps = <&rpmhpd_opp_svs_l1>; 2201 }; 2202 2203 opp-810000000 { 2204 opp-hz = /bits/ 64 <810000000>; 2205 required-opps = <&rpmhpd_opp_nom>; 2206 }; 2207 }; 2208 }; 2209 2210 mdss_dsi0: dsi@ae94000 { 2211 compatible = "qcom,sar2130p-dsi-ctrl", 2212 "qcom,mdss-dsi-ctrl"; 2213 reg = <0x0 0x0ae94000 0x0 0x400>; 2214 reg-names = "dsi_ctrl"; 2215 2216 interrupt-parent = <&mdss>; 2217 interrupts = <4>; 2218 2219 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2220 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2221 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2222 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2223 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2224 <&gcc GCC_DISP_HF_AXI_CLK>; 2225 clock-names = "byte", 2226 "byte_intf", 2227 "pixel", 2228 "core", 2229 "iface", 2230 "bus"; 2231 2232 power-domains = <&rpmhpd RPMHPD_MMCX>; 2233 2234 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2235 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2236 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2237 <&mdss_dsi0_phy 1>; 2238 2239 operating-points-v2 = <&mdss_dsi_opp_table>; 2240 2241 phys = <&mdss_dsi0_phy>; 2242 phy-names = "dsi"; 2243 2244 #address-cells = <1>; 2245 #size-cells = <0>; 2246 2247 status = "disabled"; 2248 2249 ports { 2250 #address-cells = <1>; 2251 #size-cells = <0>; 2252 2253 port@0 { 2254 reg = <0>; 2255 mdss_dsi0_in: endpoint { 2256 remote-endpoint = <&dpu_intf1_out>; 2257 }; 2258 }; 2259 2260 port@1 { 2261 reg = <1>; 2262 mdss_dsi0_out: endpoint { 2263 }; 2264 }; 2265 }; 2266 2267 mdss_dsi_opp_table: opp-table { 2268 compatible = "operating-points-v2"; 2269 2270 opp-187500000 { 2271 opp-hz = /bits/ 64 <187500000>; 2272 required-opps = <&rpmhpd_opp_low_svs>; 2273 }; 2274 2275 opp-300000000 { 2276 opp-hz = /bits/ 64 <300000000>; 2277 required-opps = <&rpmhpd_opp_svs>; 2278 }; 2279 2280 opp-358000000 { 2281 opp-hz = /bits/ 64 <358000000>; 2282 required-opps = <&rpmhpd_opp_nom>; 2283 }; 2284 }; 2285 }; 2286 2287 mdss_dsi0_phy: phy@ae95000 { 2288 compatible = "qcom,sar2130p-dsi-phy-5nm"; 2289 reg = <0x0 0x0ae95000 0x0 0x200>, 2290 <0x0 0x0ae95200 0x0 0x280>, 2291 <0x0 0x0ae95500 0x0 0x400>; 2292 reg-names = "dsi_phy", 2293 "dsi_phy_lane", 2294 "dsi_pll"; 2295 2296 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2297 <&rpmhcc RPMH_CXO_CLK>; 2298 clock-names = "iface", "ref"; 2299 2300 #clock-cells = <1>; 2301 #phy-cells = <0>; 2302 2303 status = "disabled"; 2304 }; 2305 2306 mdss_dsi1: dsi@ae96000 { 2307 compatible = "qcom,sar2130p-dsi-ctrl", 2308 "qcom,mdss-dsi-ctrl"; 2309 reg = <0x0 0x0ae96000 0x0 0x400>; 2310 reg-names = "dsi_ctrl"; 2311 2312 interrupt-parent = <&mdss>; 2313 interrupts = <5>; 2314 2315 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2316 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2317 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2318 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2319 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2320 <&gcc GCC_DISP_HF_AXI_CLK>; 2321 clock-names = "byte", 2322 "byte_intf", 2323 "pixel", 2324 "core", 2325 "iface", 2326 "bus"; 2327 2328 power-domains = <&rpmhpd RPMHPD_MMCX>; 2329 2330 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2331 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2332 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2333 <&mdss_dsi1_phy 1>; 2334 2335 operating-points-v2 = <&mdss_dsi_opp_table>; 2336 2337 phys = <&mdss_dsi1_phy>; 2338 phy-names = "dsi"; 2339 2340 #address-cells = <1>; 2341 #size-cells = <0>; 2342 2343 status = "disabled"; 2344 2345 ports { 2346 #address-cells = <1>; 2347 #size-cells = <0>; 2348 2349 port@0 { 2350 reg = <0>; 2351 mdss_dsi1_in: endpoint { 2352 remote-endpoint = <&dpu_intf2_out>; 2353 }; 2354 }; 2355 2356 port@1 { 2357 reg = <1>; 2358 mdss_dsi1_out: endpoint { 2359 }; 2360 }; 2361 }; 2362 }; 2363 2364 mdss_dsi1_phy: phy@ae97000 { 2365 compatible = "qcom,sar2130p-dsi-phy-5nm"; 2366 reg = <0x0 0x0ae97000 0x0 0x200>, 2367 <0x0 0x0ae97200 0x0 0x280>, 2368 <0x0 0x0ae97500 0x0 0x400>; 2369 reg-names = "dsi_phy", 2370 "dsi_phy_lane", 2371 "dsi_pll"; 2372 2373 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2374 <&rpmhcc RPMH_CXO_CLK>; 2375 clock-names = "iface", "ref"; 2376 2377 #clock-cells = <1>; 2378 #phy-cells = <0>; 2379 2380 status = "disabled"; 2381 }; 2382 }; 2383 2384 dispcc: clock-controller@af00000 { 2385 compatible = "qcom,sar2130p-dispcc"; 2386 reg = <0x0 0x0af00000 0x0 0x20000>; 2387 clocks = <&rpmhcc RPMH_CXO_CLK>, 2388 <&rpmhcc RPMH_CXO_CLK_A>, 2389 <&gcc GCC_DISP_AHB_CLK>, 2390 <&sleep_clk>, 2391 <&mdss_dsi0_phy 0>, 2392 <&mdss_dsi0_phy 1>, 2393 <&mdss_dsi1_phy 0>, 2394 <&mdss_dsi1_phy 1>, 2395 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2396 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2397 <0>, /* dp1 */ 2398 <0>, 2399 <0>, /* dp2 */ 2400 <0>, 2401 <0>, /* dp3 */ 2402 <0>; 2403 power-domains = <&rpmhpd RPMHPD_MMCX>; 2404 #clock-cells = <1>; 2405 #reset-cells = <1>; 2406 #power-domain-cells = <1>; 2407 }; 2408 2409 pdc: interrupt-controller@b220000 { 2410 compatible = "qcom,sar2130p-pdc", "qcom,pdc"; 2411 reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; 2412 qcom,pdc-ranges = <0 480 94>, 2413 <94 609 31>, 2414 <125 63 1>, 2415 <126 716 12>; 2416 #interrupt-cells = <2>; 2417 interrupt-parent = <&intc>; 2418 interrupt-controller; 2419 }; 2420 2421 aoss_qmp: power-management@c300000 { 2422 compatible = "qcom,sar2130p-aoss-qmp", "qcom,aoss-qmp"; 2423 reg = <0x0 0x0c300000 0x0 0x400>; 2424 interrupt-parent = <&ipcc>; 2425 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2426 IRQ_TYPE_EDGE_RISING>; 2427 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2428 2429 #clock-cells = <0>; 2430 }; 2431 2432 tsens0: thermal-sensor@c263000 { 2433 compatible = "qcom,sar2130p-tsens", "qcom,tsens-v2"; 2434 reg = <0x0 0x0c263000 0x0 0x1000>, /* TM */ 2435 <0x0 0x0c222000 0x0 0x1000>; /* SROT */ 2436 #qcom,sensors = <16>; 2437 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2439 interrupt-names = "uplow", "critical"; 2440 #thermal-sensor-cells = <1>; 2441 }; 2442 2443 sram@c3f0000 { 2444 compatible = "qcom,rpmh-stats"; 2445 reg = <0x0 0x0c3f0000 0x0 0x400>; 2446 }; 2447 2448 arbiter@c400000 { 2449 compatible = "qcom,sar2130p-spmi-pmic-arb", 2450 "qcom,x1e80100-spmi-pmic-arb"; 2451 reg = <0x0 0x0c400000 0x0 0x3000>, 2452 <0x0 0x0c500000 0x0 0x400000>, 2453 <0x0 0x0c440000 0x0 0x80000>; 2454 reg-names = "core", "chnls", "obsrvr"; 2455 2456 qcom,ee = <0>; 2457 qcom,channel = <0>; 2458 2459 #address-cells = <2>; 2460 #size-cells = <2>; 2461 ranges; 2462 2463 spmi_bus: spmi@c42d000 { 2464 reg = <0x0 0x0c42d000 0x0 0x4000>, 2465 <0x0 0x0c4c0000 0x0 0x10000>; 2466 reg-names = "cnfg", "intr"; 2467 2468 interrupt-names = "periph_irq"; 2469 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2470 interrupt-controller; 2471 #interrupt-cells = <4>; 2472 2473 #address-cells = <2>; 2474 #size-cells = <0>; 2475 }; 2476 }; 2477 2478 ipcc: mailbox@ed18000 { 2479 compatible = "qcom,sar2130p-ipcc", "qcom,ipcc"; 2480 reg = <0x0 0x0ed18000 0x0 0x1000>; 2481 2482 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 2483 interrupt-controller; 2484 #interrupt-cells = <3>; 2485 2486 #mbox-cells = <2>; 2487 }; 2488 2489 tlmm: pinctrl@f100000 { 2490 compatible = "qcom,sar2130p-tlmm"; 2491 reg = <0x0 0x0f100000 0x0 0x300000>; 2492 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2493 gpio-controller; 2494 #gpio-cells = <2>; 2495 interrupt-controller; 2496 #interrupt-cells = <2>; 2497 gpio-ranges = <&tlmm 0 0 156>; 2498 wakeup-parent = <&pdc>; 2499 2500 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2501 /* SDA, SCL */ 2502 pins = "gpio0", "gpio1"; 2503 function = "qup0"; 2504 drive-strength = <2>; 2505 bias-pull-up; 2506 }; 2507 2508 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2509 /* SDA, SCL */ 2510 pins = "gpio2", "gpio3"; 2511 function = "qup1"; 2512 drive-strength = <2>; 2513 bias-pull-up; 2514 }; 2515 2516 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2517 /* SDA, SCL */ 2518 pins = "gpio22", "gpio23"; 2519 function = "qup2"; 2520 drive-strength = <2>; 2521 bias-pull-up; 2522 }; 2523 2524 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2525 /* SDA, SCL */ 2526 pins = "gpio16", "gpio17"; 2527 function = "qup3"; 2528 drive-strength = <2>; 2529 bias-pull-up; 2530 }; 2531 2532 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2533 /* SDA, SCL */ 2534 pins = "gpio20", "gpio21"; 2535 function = "qup4"; 2536 drive-strength = <2>; 2537 bias-pull-up; 2538 }; 2539 2540 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 2541 /* SDA, SCL */ 2542 pins = "gpio95", "gpio96"; 2543 function = "qup5"; 2544 drive-strength = <2>; 2545 bias-pull-up; 2546 }; 2547 2548 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 2549 /* SDA, SCL */ 2550 pins = "gpio91", "gpio92"; 2551 function = "qup6"; 2552 drive-strength = <2>; 2553 bias-pull-up; 2554 }; 2555 2556 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 2557 /* SDA, SCL */ 2558 pins = "gpio8", "gpio9"; 2559 function = "qup7"; 2560 drive-strength = <2>; 2561 bias-pull-up; 2562 }; 2563 2564 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 2565 /* SDA, SCL */ 2566 pins = "gpio8", "gpio9"; 2567 function = "qup8"; 2568 drive-strength = <2>; 2569 bias-pull-up; 2570 }; 2571 2572 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 2573 /* SDA, SCL */ 2574 pins = "gpio109", "gpio110"; 2575 function = "qup9"; 2576 drive-strength = <2>; 2577 bias-pull-up; 2578 }; 2579 2580 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 2581 /* SDA, SCL */ 2582 pins = "gpio4", "gpio5"; 2583 function = "qup10"; 2584 drive-strength = <2>; 2585 bias-pull-up; 2586 }; 2587 2588 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 2589 /* SDA, SCL */ 2590 pins = "gpio28", "gpio30"; 2591 function = "qup11"; 2592 drive-strength = <2>; 2593 bias-pull-up; 2594 }; 2595 2596 qup_spi0_cs0: qup-spi0-cs0-state { 2597 pins = "gpio3"; 2598 function = "qup0"; 2599 drive-strength = <2>; 2600 bias-disable; 2601 }; 2602 2603 qup_spi0_cs1: qup-spi0-cs1-state { 2604 pins = "gpio93"; 2605 function = "qup0"; 2606 drive-strength = <2>; 2607 bias-disable; 2608 }; 2609 2610 qup_spi0_data_clk: qup-spi0-data-clk-state { 2611 /* MISO, MOSI, CLK */ 2612 pins = "gpio0", "gpio1", "gpio2"; 2613 function = "qup0"; 2614 drive-strength = <2>; 2615 bias-disable; 2616 }; 2617 2618 qup_spi1_cs: qup-spi1-cs-state { 2619 pins = "gpio62"; 2620 function = "qup1"; 2621 drive-strength = <2>; 2622 bias-disable; 2623 }; 2624 2625 qup_spi1_data_clk: qup-spi1-data-clk-state { 2626 /* MISO, MOSI, CLK */ 2627 pins = "gpio2", "gpio3", "gpio61"; 2628 function = "qup1"; 2629 drive-strength = <2>; 2630 bias-disable; 2631 }; 2632 2633 qup_spi2_cs: qup-spi2-cs-state { 2634 pins = "gpio13"; 2635 function = "qup2"; 2636 drive-strength = <2>; 2637 bias-disable; 2638 }; 2639 2640 qup_spi2_data_clk: qup-spi2-data-clk-state { 2641 /* MISO, MOSI, CLK */ 2642 pins = "gpio22", "gpio23", "gpio12"; 2643 function = "qup2"; 2644 drive-strength = <2>; 2645 bias-disable; 2646 }; 2647 2648 qup_spi3_cs0: qup-spi3-cs0-state { 2649 pins = "gpio19"; 2650 function = "qup3"; 2651 drive-strength = <2>; 2652 bias-disable; 2653 }; 2654 2655 qup_spi3_cs1: qup-spi3-cs1-state { 2656 pins = "gpio41"; 2657 function = "qup3"; 2658 drive-strength = <2>; 2659 bias-disable; 2660 }; 2661 2662 qup_spi3_data_clk: qup-spi3-data-clk-state { 2663 /* MISO, MOSI, CLK */ 2664 pins = "gpio16", "gpio17", "gpio18"; 2665 function = "qup3"; 2666 drive-strength = <2>; 2667 bias-disable; 2668 }; 2669 2670 qup_spi4_cs0: qup-spi4-cs0-state { 2671 pins = "gpio23"; 2672 function = "qup4"; 2673 drive-strength = <2>; 2674 bias-disable; 2675 }; 2676 2677 qup_spi4_cs1: qup-spi4-cs1-state { 2678 pins = "gpio94"; 2679 function = "qup4"; 2680 drive-strength = <2>; 2681 bias-disable; 2682 }; 2683 2684 qup_spi4_data_clk: qup-spi4-data-clk-state { 2685 /* MISO, MOSI, CLK */ 2686 pins = "gpio20", "gpio21", "gpio22"; 2687 function = "qup4"; 2688 drive-strength = <2>; 2689 bias-disable; 2690 }; 2691 2692 qup_spi5_cs: qup-spi5-cs-state { 2693 pins = "gpio98"; 2694 function = "qup5"; 2695 drive-strength = <2>; 2696 bias-disable; 2697 }; 2698 2699 qup_spi5_data_clk: qup-spi5-data-clk-state { 2700 /* MISO, MOSI, CLK */ 2701 pins = "gpio95", "gpio96", "gpio97"; 2702 function = "qup5"; 2703 drive-strength = <2>; 2704 bias-disable; 2705 }; 2706 2707 qup_spi6_cs: qup-spi6-cs-state { 2708 pins = "gpio63"; 2709 function = "qup6"; 2710 drive-strength = <2>; 2711 bias-disable; 2712 }; 2713 2714 qup_spi6_data_clk: qup-spi6-data-clk-state { 2715 /* MISO, MOSI, CLK */ 2716 pins = "gpio91", "gpio92", "gpio64"; 2717 function = "qup6"; 2718 drive-strength = <2>; 2719 bias-disable; 2720 }; 2721 2722 qup_spi7_cs: qup-spi7-cs-state { 2723 pins = "gpio27"; 2724 function = "qup7"; 2725 drive-strength = <2>; 2726 bias-disable; 2727 }; 2728 2729 qup_spi7_data_clk: qup-spi7-data-clk-state { 2730 /* MISO, MOSI, CLK */ 2731 pins = "gpio24", "gpio25", "gpio26"; 2732 function = "qup7"; 2733 drive-strength = <2>; 2734 bias-disable; 2735 }; 2736 2737 qup_spi8_cs: qup-spi8-cs-state { 2738 pins = "gpio11"; 2739 function = "qup8"; 2740 drive-strength = <2>; 2741 bias-disable; 2742 }; 2743 2744 qup_spi8_data_clk: qup-spi8-data-clk-state { 2745 /* MISO, MOSI, CLK */ 2746 pins = "gpio8", "gpio9", "gpio10"; 2747 function = "qup8"; 2748 drive-strength = <2>; 2749 bias-disable; 2750 }; 2751 2752 qup_spi9_cs: qup-spi9-cs-state { 2753 pins = "gpio35"; 2754 function = "qup9"; 2755 drive-strength = <2>; 2756 bias-disable; 2757 }; 2758 2759 qup_spi9_data_clk: qup-spi9-data-clk-state { 2760 /* MISO, MOSI, CLK */ 2761 pins = "gpio109", "gpio110", "gpio34"; 2762 function = "qup9"; 2763 drive-strength = <2>; 2764 bias-disable; 2765 }; 2766 2767 qup_spi10_cs: qup-spi10-cs-state { 2768 pins = "gpio7"; 2769 function = "qup10"; 2770 drive-strength = <2>; 2771 bias-disable; 2772 }; 2773 2774 qup_spi10_data_clk: qup-spi10-data-clk-state { 2775 /* MISO, MOSI, CLK */ 2776 pins = "gpio4", "gpio5", "gpio6"; 2777 function = "qup10"; 2778 drive-strength = <2>; 2779 bias-disable; 2780 }; 2781 2782 qup_spi11_cs: qup-spi11-cs-state { 2783 pins = "gpio15"; 2784 function = "qup11"; 2785 drive-strength = <2>; 2786 bias-disable; 2787 }; 2788 2789 qup_spi11_data_clk: qup-spi11-data-clk-state { 2790 /* MISO, MOSI, CLK */ 2791 pins = "gpio28", "gpio30", "gpio14"; 2792 function = "qup11"; 2793 drive-strength = <2>; 2794 bias-disable; 2795 }; 2796 2797 qup_uart7_default: qup-uart7-default-state { 2798 cts-pins { 2799 pins = "gpio24"; 2800 function = "qup7"; 2801 drive-strength = <2>; 2802 bias-disable; 2803 }; 2804 2805 rts-pins { 2806 pins = "gpio25"; 2807 function = "qup7"; 2808 drive-strength = <2>; 2809 bias-pull-down; 2810 }; 2811 2812 rx-pins { 2813 pins = "gpio27"; 2814 function = "qup7"; 2815 drive-strength = <2>; 2816 bias-pull-down; 2817 }; 2818 2819 tx-pins { 2820 pins = "gpio26"; 2821 function = "qup7"; 2822 drive-strength = <2>; 2823 bias-pull-up; 2824 }; 2825 }; 2826 2827 qup_uart11_default: qup-uart11-default-state { 2828 pins = "gpio14", "gpio15"; 2829 function = "qup11"; 2830 drive-strength = <2>; 2831 bias-disable; 2832 }; 2833 2834 sdc1_default: sdc1-default-state { 2835 clk-pins { 2836 pins = "sdc1_clk"; 2837 drive-strength = <16>; 2838 bias-disable; 2839 }; 2840 2841 cmd-pins { 2842 pins = "sdc1_cmd"; 2843 drive-strength = <10>; 2844 bias-pull-up; 2845 }; 2846 2847 data-pins { 2848 pins = "sdc1_data"; 2849 drive-strength = <10>; 2850 bias-pull-up; 2851 }; 2852 2853 rclk-pins { 2854 pins = "sdc1_rclk"; 2855 bias-pull-down; 2856 }; 2857 }; 2858 2859 sdc1_sleep: sdc1-sleep-state { 2860 clk-pins { 2861 pins = "sdc1_clk"; 2862 drive-strength = <2>; 2863 bias-disable; 2864 }; 2865 2866 cmd-pins { 2867 pins = "sdc1_cmd"; 2868 drive-strength = <2>; 2869 bias-pull-up; 2870 }; 2871 2872 data-pins { 2873 pins = "sdc1_data"; 2874 drive-strength = <2>; 2875 bias-pull-up; 2876 }; 2877 2878 rclk-pins { 2879 pins = "sdc1_rclk"; 2880 bias-pull-down; 2881 }; 2882 }; 2883 }; 2884 2885 apps_smmu: iommu@15000000 { 2886 compatible = "qcom,sar2130p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2887 reg = <0x0 0x15000000 0x0 0x100000>; 2888 #iommu-cells = <2>; 2889 #global-interrupts = <1>; 2890 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2891 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2892 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2893 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2894 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2895 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2896 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2897 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2898 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2899 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2900 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2901 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2902 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2903 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2904 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2905 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2906 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2907 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2908 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2909 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2910 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2911 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2912 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2913 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2914 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2915 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2916 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2917 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2918 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2919 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2920 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2921 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2922 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2923 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2924 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2925 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2926 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2927 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2928 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2929 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2930 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2931 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2932 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2933 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2934 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2935 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2936 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2937 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2938 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2939 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2940 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2941 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2942 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2943 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2944 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2945 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2946 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2947 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2948 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2949 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2950 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2951 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2952 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2953 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2954 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2955 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2956 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2957 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2958 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2959 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2960 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2961 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2962 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2963 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2964 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2965 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2966 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2967 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2968 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2969 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2970 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2971 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2972 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2973 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2974 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2975 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 2976 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2977 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2978 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 2979 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 2980 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 2981 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 2982 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 2983 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 2984 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 2985 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 2986 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 2987 dma-coherent; 2988 }; 2989 2990 intc: interrupt-controller@17200000 { 2991 compatible = "arm,gic-v3"; 2992 #interrupt-cells = <3>; 2993 interrupt-controller; 2994 #redistributor-regions = <1>; 2995 redistributor-stride = <0x0 0x20000>; 2996 reg = <0x0 0x17200000 0x0 0x10000>, 2997 <0x0 0x17260000 0x0 0x100000>; 2998 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2999 #address-cells = <2>; 3000 #size-cells = <2>; 3001 ranges; 3002 3003 gic_its: msi-controller@17240000 { 3004 compatible = "arm,gic-v3-its"; 3005 reg = <0x0 0x17240000 0x0 0x20000>; 3006 msi-controller; 3007 #msi-cells = <1>; 3008 }; 3009 }; 3010 3011 apps_rsc: rsc@17a00000 { 3012 label = "apps_rsc"; 3013 compatible = "qcom,rpmh-rsc"; 3014 reg = <0x0 0x17a00000 0x0 0x10000>, 3015 <0x0 0x17a10000 0x0 0x10000>, 3016 <0x0 0x17a20000 0x0 0x10000>; 3017 reg-names = "drv-0", "drv-1", "drv-2"; 3018 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3019 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3020 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3021 qcom,tcs-offset = <0xd00>; 3022 qcom,drv-id = <2>; 3023 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3024 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3025 power-domains = <&cluster_pd>; 3026 3027 apps_bcm_voter: bcm-voter { 3028 compatible = "qcom,bcm-voter"; 3029 }; 3030 3031 rpmhcc: clock-controller { 3032 compatible = "qcom,sar2130p-rpmh-clk"; 3033 #clock-cells = <1>; 3034 clock-names = "xo"; 3035 clocks = <&xo_board>; 3036 }; 3037 3038 rpmhpd: power-controller { 3039 compatible = "qcom,sar2130p-rpmhpd"; 3040 #power-domain-cells = <1>; 3041 operating-points-v2 = <&rpmhpd_opp_table>; 3042 3043 rpmhpd_opp_table: opp-table { 3044 compatible = "operating-points-v2"; 3045 3046 rpmhpd_opp_ret: opp1 { 3047 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3048 }; 3049 3050 rpmhpd_opp_min_svs: opp2 { 3051 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3052 }; 3053 3054 rpmhpd_opp_low_svs_d1: opp3 { 3055 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3056 }; 3057 3058 rpmhpd_opp_low_svs: opp4 { 3059 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3060 }; 3061 3062 rpmhpd_opp_svs: opp5 { 3063 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3064 }; 3065 3066 rpmhpd_opp_svs_l1: opp6 { 3067 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3068 }; 3069 3070 rpmhpd_opp_nom: opp7 { 3071 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3072 }; 3073 3074 rpmhpd_opp_turbo: opp8 { 3075 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3076 }; 3077 3078 rpmhpd_opp_turbo_l1: opp9 { 3079 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3080 }; 3081 }; 3082 }; 3083 }; 3084 3085 cpufreq_hw: cpufreq@17d91000 { 3086 compatible = "qcom,sar2130p-cpufreq-epss", "qcom,cpufreq-epss"; 3087 reg = <0x0 0x17d91000 0x0 0x1000>; 3088 reg-names = "freq-domain0"; 3089 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3090 clock-names = "xo", "alternate"; 3091 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3092 interrupt-names = "dcvsh-irq-0"; 3093 #freq-domain-cells = <1>; 3094 #clock-cells = <1>; 3095 }; 3096 3097 gem_noc: interconnect@19100000 { 3098 compatible = "qcom,sar2130p-gem-noc"; 3099 reg = <0x0 0x19100000 0x0 0xa2080>; 3100 #interconnect-cells = <2>; 3101 qcom,bcm-voters = <&apps_bcm_voter>; 3102 }; 3103 3104 /* 3105 * Bootloader expects just cache-controller node instead of 3106 * the typical system-cache-controller 3107 */ 3108 llcc: cache-controller@19200000 { 3109 compatible = "qcom,sar2130p-llcc"; 3110 reg = <0x0 0x19200000 0x0 0x80000>, 3111 <0x0 0x19300000 0x0 0x80000>, 3112 <0x0 0x19a00000 0x0 0x80000>, 3113 <0x0 0x19c00000 0x0 0x80000>, 3114 <0x0 0x19af0000 0x0 0x80000>, 3115 <0x0 0x19cf0000 0x0 0x80000>; 3116 reg-names = "llcc0_base", 3117 "llcc1_base", 3118 "llcc_broadcast_base", 3119 "llcc_broadcast_and_base", 3120 "llcc_scratchpad_broadcast_base", 3121 "llcc_scratchpad_broadcast_and_base"; 3122 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3123 }; 3124 3125 qfprom: qfprom@221c8000 { 3126 compatible = "qcom,sar2130p-qfprom", "qcom,qfprom"; 3127 reg = <0x0 0x221c8000 0x0 0x1000>; 3128 #address-cells = <1>; 3129 #size-cells = <1>; 3130 read-only; 3131 3132 gpu_speed_bin: gpu-speed-bin@119 { 3133 reg = <0x119 0x2>; 3134 bits = <5 8>; 3135 }; 3136 }; 3137 3138 nsp_noc: interconnect@320c0000 { 3139 compatible = "qcom,sar2130p-nsp-noc"; 3140 reg = <0x0 0x320c0000 0x0 0x10>; 3141 #interconnect-cells = <2>; 3142 qcom,bcm-voters = <&apps_bcm_voter>; 3143 }; 3144 3145 lpass_ag_noc: interconnect@3c40000 { 3146 compatible = "qcom,sar2130p-lpass-ag-noc"; 3147 reg = <0x0 0x3c40000 0x0 0x10>; 3148 #interconnect-cells = <1>; 3149 qcom,bcm-voters = <&apps_bcm_voter>; 3150 }; 3151 }; 3152 3153 timer { 3154 compatible = "arm,armv8-timer"; 3155 3156 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3157 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3158 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3159 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3160 }; 3161 3162 thermal-zones { 3163 aoss0-thermal { 3164 thermal-sensors = <&tsens0 0>; 3165 3166 trips { 3167 trip-point0 { 3168 temperature = <115000>; 3169 hysteresis = <5000>; 3170 type = "hot"; 3171 }; 3172 3173 aoss0-critical { 3174 temperature = <125000>; 3175 hysteresis = <0>; 3176 type = "critical"; 3177 }; 3178 3179 }; 3180 }; 3181 3182 cpu0-thermal { 3183 thermal-sensors = <&tsens0 1>; 3184 3185 trips { 3186 cpu0_alert0: trip-point0 { 3187 temperature = <110000>; 3188 hysteresis = <10000>; 3189 type = "passive"; 3190 }; 3191 3192 cpu0_alert1: trip-point1 { 3193 temperature = <115000>; 3194 hysteresis = <5000>; 3195 type = "passive"; 3196 }; 3197 3198 cpu0-critical { 3199 temperature = <125000>; 3200 hysteresis = <1000>; 3201 type = "critical"; 3202 }; 3203 }; 3204 3205 cooling-maps { 3206 map0 { 3207 trip = <&cpu0_alert0>; 3208 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3209 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3210 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3211 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3212 }; 3213 3214 map1 { 3215 trip = <&cpu0_alert1>; 3216 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3217 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3218 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3219 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3220 }; 3221 }; 3222 }; 3223 3224 cpu1-thermal { 3225 thermal-sensors = <&tsens0 2>; 3226 3227 trips { 3228 cpu1_alert0: trip-point0 { 3229 temperature = <110000>; 3230 hysteresis = <10000>; 3231 type = "passive"; 3232 }; 3233 3234 cpu1_alert1: trip-point1 { 3235 temperature = <115000>; 3236 hysteresis = <5000>; 3237 type = "passive"; 3238 }; 3239 3240 cpu1-critical { 3241 temperature = <125000>; 3242 hysteresis = <1000>; 3243 type = "critical"; 3244 }; 3245 }; 3246 3247 cooling-maps { 3248 map0 { 3249 trip = <&cpu1_alert0>; 3250 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3251 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3252 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3253 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3254 }; 3255 3256 map1 { 3257 trip = <&cpu1_alert1>; 3258 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3259 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3260 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3261 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3262 }; 3263 }; 3264 }; 3265 3266 cpu2-thermal { 3267 thermal-sensors = <&tsens0 3>; 3268 3269 trips { 3270 cpu2_alert0: trip-point0 { 3271 temperature = <110000>; 3272 hysteresis = <10000>; 3273 type = "passive"; 3274 }; 3275 3276 cpu2_alert1: trip-point1 { 3277 temperature = <115000>; 3278 hysteresis = <5000>; 3279 type = "passive"; 3280 }; 3281 3282 cpu2-critical { 3283 temperature = <125000>; 3284 hysteresis = <1000>; 3285 type = "critical"; 3286 }; 3287 }; 3288 3289 cooling-maps { 3290 map0 { 3291 trip = <&cpu2_alert0>; 3292 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3293 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3294 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3295 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3296 }; 3297 3298 map1 { 3299 trip = <&cpu2_alert1>; 3300 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3301 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3302 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3303 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3304 }; 3305 }; 3306 }; 3307 3308 cpu3-thermal { 3309 thermal-sensors = <&tsens0 4>; 3310 3311 trips { 3312 cpu3_alert0: trip-point0 { 3313 temperature = <110000>; 3314 hysteresis = <10000>; 3315 type = "passive"; 3316 }; 3317 3318 cpu3_alert1: rip-point1 { 3319 temperature = <115000>; 3320 hysteresis = <5000>; 3321 type = "passive"; 3322 }; 3323 3324 cpu3-critical { 3325 temperature = <125000>; 3326 hysteresis = <1000>; 3327 type = "critical"; 3328 }; 3329 }; 3330 3331 cooling-maps { 3332 map0 { 3333 trip = <&cpu3_alert0>; 3334 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3335 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3336 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3337 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3338 }; 3339 3340 map1 { 3341 trip = <&cpu3_alert1>; 3342 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3343 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3344 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3345 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3346 }; 3347 }; 3348 }; 3349 3350 gpuss0-thermal { 3351 polling-delay-passive = <250>; 3352 3353 thermal-sensors = <&tsens0 5>; 3354 3355 cooling-maps { 3356 map0 { 3357 trip = <&gpu0_alert0>; 3358 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3359 }; 3360 }; 3361 3362 trips { 3363 gpu0_alert0: trip-point0 { 3364 temperature = <85000>; 3365 hysteresis = <1000>; 3366 type = "passive"; 3367 }; 3368 3369 trip-point1 { 3370 temperature = <90000>; 3371 hysteresis = <1000>; 3372 type = "hot"; 3373 }; 3374 3375 trip-point2 { 3376 temperature = <115000>; 3377 hysteresis = <1000>; 3378 type = "critical"; 3379 }; 3380 }; 3381 }; 3382 3383 gpuss1-thermal { 3384 polling-delay-passive = <250>; 3385 3386 thermal-sensors = <&tsens0 6>; 3387 3388 cooling-maps { 3389 map0 { 3390 trip = <&gpu1_alert0>; 3391 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3392 }; 3393 }; 3394 3395 trips { 3396 gpu1_alert0: trip-point0 { 3397 temperature = <85000>; 3398 hysteresis = <1000>; 3399 type = "passive"; 3400 }; 3401 3402 trip-point1 { 3403 temperature = <90000>; 3404 hysteresis = <1000>; 3405 type = "hot"; 3406 }; 3407 3408 trip-point2 { 3409 temperature = <115000>; 3410 hysteresis = <1000>; 3411 type = "critical"; 3412 }; 3413 }; 3414 }; 3415 3416 nspss0-thermal { 3417 thermal-sensors = <&tsens0 7>; 3418 3419 trips { 3420 trip-point0 { 3421 temperature = <95000>; 3422 hysteresis = <5000>; 3423 type = "hot"; 3424 }; 3425 3426 trip-point1 { 3427 temperature = <115000>; 3428 hysteresis = <5000>; 3429 type = "hot"; 3430 }; 3431 3432 nspss1-critical { 3433 temperature = <125000>; 3434 hysteresis = <1000>; 3435 type = "critical"; 3436 }; 3437 }; 3438 }; 3439 3440 nspss1-thermal { 3441 thermal-sensors = <&tsens0 8>; 3442 3443 trips { 3444 trip-point0 { 3445 temperature = <95000>; 3446 hysteresis = <5000>; 3447 type = "hot"; 3448 }; 3449 3450 trip-point1 { 3451 temperature = <115000>; 3452 hysteresis = <5000>; 3453 type = "hot"; 3454 }; 3455 3456 nspss2-critical { 3457 temperature = <125000>; 3458 hysteresis = <1000>; 3459 type = "critical"; 3460 }; 3461 }; 3462 }; 3463 3464 nspss2-thermal { 3465 thermal-sensors = <&tsens0 9>; 3466 3467 trips { 3468 trip-point0 { 3469 temperature = <95000>; 3470 hysteresis = <5000>; 3471 type = "hot"; 3472 }; 3473 3474 trip-point1 { 3475 temperature = <115000>; 3476 hysteresis = <5000>; 3477 type = "hot"; 3478 }; 3479 3480 nspss2-critical { 3481 temperature = <125000>; 3482 hysteresis = <1000>; 3483 type = "critical"; 3484 }; 3485 }; 3486 }; 3487 3488 video-thermal { 3489 thermal-sensors = <&tsens0 10>; 3490 3491 trips { 3492 trip-point0 { 3493 temperature = <115000>; 3494 hysteresis = <5000>; 3495 type = "hot"; 3496 }; 3497 3498 video-critical { 3499 temperature = <125000>; 3500 hysteresis = <0>; 3501 type = "critical"; 3502 }; 3503 }; 3504 }; 3505 3506 ddr-thermal { 3507 thermal-sensors = <&tsens0 11>; 3508 3509 trips { 3510 trip-point0 { 3511 temperature = <115000>; 3512 hysteresis = <5000>; 3513 type = "hot"; 3514 }; 3515 3516 ddr-critical { 3517 temperature = <125000>; 3518 hysteresis = <0>; 3519 type = "critical"; 3520 }; 3521 }; 3522 }; 3523 3524 camera0-thermal { 3525 thermal-sensors = <&tsens0 12>; 3526 3527 trips { 3528 trip-point0 { 3529 temperature = <115000>; 3530 hysteresis = <5000>; 3531 type = "hot"; 3532 }; 3533 3534 camera0-critical { 3535 temperature = <125000>; 3536 hysteresis = <0>; 3537 type = "critical"; 3538 }; 3539 }; 3540 }; 3541 3542 camera1-thermal { 3543 thermal-sensors = <&tsens0 13>; 3544 3545 trips { 3546 trip-point0 { 3547 temperature = <115000>; 3548 hysteresis = <5000>; 3549 type = "hot"; 3550 }; 3551 3552 camera1-critical { 3553 temperature = <125000>; 3554 hysteresis = <0>; 3555 type = "critical"; 3556 }; 3557 }; 3558 }; 3559 3560 mdmss-thermal { 3561 thermal-sensors = <&tsens0 14>; 3562 3563 trips { 3564 trip-point0 { 3565 temperature = <115000>; 3566 hysteresis = <5000>; 3567 type = "hot"; 3568 }; 3569 3570 mdmss-critical { 3571 temperature = <125000>; 3572 hysteresis = <0>; 3573 type = "critical"; 3574 }; 3575 }; 3576 }; 3577 }; 3578}; 3579