1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024, Linaro Limited 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sar2130p-gcc.h> 9#include <dt-bindings/clock/qcom,sar2130p-gpucc.h> 10#include <dt-bindings/clock/qcom,sm8550-dispcc.h> 11#include <dt-bindings/clock/qcom,sm8550-tcsr.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/interconnect/qcom,icc.h> 14#include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/soc/qcom,gpr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <19200000>; 37 }; 38 39 sleep_clk: sleep-clk { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <32764>; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a55"; 53 reg = <0x0 0x0>; 54 clocks = <&cpufreq_hw 0>; 55 enable-method = "psci"; 56 next-level-cache = <&l2_0>; 57 qcom,freq-domain = <&cpufreq_hw 0>; 58 power-domains = <&cpu_pd0>; 59 power-domain-names = "psci"; 60 #cooling-cells = <2>; 61 62 l2_0: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 cache-unified; 66 next-level-cache = <&l3_0>; 67 68 l3_0: l3-cache { 69 compatible = "cache"; 70 cache-level = <3>; 71 cache-unified; 72 }; 73 }; 74 }; 75 76 cpu1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x0 0x100>; 80 clocks = <&cpufreq_hw 0>; 81 enable-method = "psci"; 82 next-level-cache = <&l2_100>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 power-domains = <&cpu_pd1>; 85 power-domain-names = "psci"; 86 #cooling-cells = <2>; 87 88 l2_100: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 next-level-cache = <&l3_0>; 93 }; 94 }; 95 96 cpu2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a55"; 99 reg = <0x0 0x200>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 next-level-cache = <&l2_200>; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 power-domains = <&cpu_pd2>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 108 l2_200: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&l3_0>; 113 }; 114 }; 115 116 cpu3: cpu@300 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a55"; 119 reg = <0x0 0x300>; 120 clocks = <&cpufreq_hw 0>; 121 enable-method = "psci"; 122 next-level-cache = <&l2_300>; 123 qcom,freq-domain = <&cpufreq_hw 0>; 124 power-domains = <&cpu_pd3>; 125 power-domain-names = "psci"; 126 #cooling-cells = <2>; 127 128 l2_300: l2-cache { 129 compatible = "cache"; 130 cache-level = <2>; 131 cache-unified; 132 next-level-cache = <&l3_0>; 133 }; 134 }; 135 136 cpu-map { 137 cluster0 { 138 core0 { 139 cpu = <&cpu0>; 140 }; 141 142 core1 { 143 cpu = <&cpu1>; 144 }; 145 146 core2 { 147 cpu = <&cpu2>; 148 }; 149 150 core3 { 151 cpu = <&cpu3>; 152 }; 153 }; 154 }; 155 156 idle-states { 157 entry-method = "psci"; 158 159 cpu_sleep_0: cpu-sleep-0-0 { 160 compatible = "arm,idle-state"; 161 idle-state-name = "silver-power-collapse"; 162 arm,psci-suspend-param = <0x40000003>; 163 entry-latency-us = <549>; 164 exit-latency-us = <901>; 165 min-residency-us = <1774>; 166 local-timer-stop; 167 }; 168 169 cpu_sleep_1: cpu-sleep-0-1 { 170 compatible = "arm,idle-state"; 171 idle-state-name = "silver-rail-power-collapse"; 172 arm,psci-suspend-param = <0x40000004>; 173 entry-latency-us = <702>; 174 exit-latency-us = <915>; 175 min-residency-us = <4001>; 176 local-timer-stop; 177 }; 178 }; 179 180 domain-idle-states { 181 cluster_sleep_0: cluster-sleep-0 { 182 compatible = "domain-idle-state"; 183 arm,psci-suspend-param = <0x41000044>; 184 entry-latency-us = <2752>; 185 exit-latency-us = <3048>; 186 min-residency-us = <6118>; 187 }; 188 189 cluster_sleep_1: cluster-sleep-1 { 190 compatible = "domain-idle-state"; 191 arm,psci-suspend-param = <0x41002344>; 192 entry-latency-us = <3263>; 193 exit-latency-us = <4562>; 194 min-residency-us = <8467>; 195 }; 196 197 cluster_sleep_2: cluster-sleep-2 { 198 compatible = "domain-idle-state"; 199 arm,psci-suspend-param = <0x4100c344>; 200 entry-latency-us = <3638>; 201 exit-latency-us = <6562>; 202 min-residency-us = <9862>; 203 }; 204 }; 205 }; 206 207 firmware { 208 scm: scm { 209 compatible = "qcom,scm-sar2130p", "qcom,scm"; 210 qcom,dload-mode = <&tcsr_mutex 0x13000>; 211 interconnects = <&system_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 212 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 213 }; 214 }; 215 216 clk_virt: interconnect-0 { 217 compatible = "qcom,sar2130p-clk-virt"; 218 #interconnect-cells = <2>; 219 qcom,bcm-voters = <&apps_bcm_voter>; 220 }; 221 222 mc_virt: interconnect-1 { 223 compatible = "qcom,sar2130p-mc-virt"; 224 #interconnect-cells = <2>; 225 qcom,bcm-voters = <&apps_bcm_voter>; 226 }; 227 228 memory@80000000 { 229 device_type = "memory"; 230 /* We expect the bootloader to fill in the size */ 231 reg = <0x0 0x80000000 0x0 0x0>; 232 }; 233 234 pmu { 235 compatible = "arm,armv8-pmuv3"; 236 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 237 }; 238 239 psci { 240 compatible = "arm,psci-1.0"; 241 method = "smc"; 242 243 cpu_pd0: power-domain-cpu0 { 244 #power-domain-cells = <0>; 245 power-domains = <&cluster_pd>; 246 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 247 }; 248 249 cpu_pd1: power-domain-cpu1 { 250 #power-domain-cells = <0>; 251 power-domains = <&cluster_pd>; 252 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 253 }; 254 255 cpu_pd2: power-domain-cpu2 { 256 #power-domain-cells = <0>; 257 power-domains = <&cluster_pd>; 258 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 259 }; 260 261 cpu_pd3: power-domain-cpu3 { 262 #power-domain-cells = <0>; 263 power-domains = <&cluster_pd>; 264 domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>; 265 }; 266 267 cluster_pd: power-domain-cpu-cluster0 { 268 #power-domain-cells = <0>; 269 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>, <&cluster_sleep_2>; 270 }; 271 }; 272 273 reserved_memory: reserved-memory { 274 #address-cells = <2>; 275 #size-cells = <2>; 276 ranges; 277 278 hyp_mem: hyp@80000000 { 279 reg = <0x0 0x80000000 0x0 0x600000>; 280 no-map; 281 }; 282 283 xbl_dt_log_mem: xbl-dt-log@80600000 { 284 reg = <0x0 0x80600000 0x0 0x40000>; 285 no-map; 286 }; 287 288 xbl_ramdump_mem: xbl-ramdump@80640000 { 289 reg = <0x0 0x80640000 0x0 0x1c0000>; 290 no-map; 291 }; 292 293 aop_image_mem: aop-image@80800000 { 294 reg = <0x0 0x80800000 0x0 0x60000>; 295 no-map; 296 }; 297 298 aop_cmd_db_mem: aop-cmd-db@80860000 { 299 compatible = "qcom,cmd-db"; 300 reg = <0x0 0x80860000 0x0 0x20000>; 301 no-map; 302 }; 303 304 aop_config_mem: aop-config@80880000 { 305 reg = <0x0 0x80880000 0x0 0x20000>; 306 no-map; 307 }; 308 309 tme_crash_dump_mem: tme-crash-dump@808a0000 { 310 reg = <0x0 0x808a0000 0x0 0x40000>; 311 no-map; 312 }; 313 314 tme_log_mem: tme-log@808e0000 { 315 reg = <0x0 0x808e0000 0x0 0x4000>; 316 no-map; 317 }; 318 319 uefi_log_mem: uefi-log@808e4000 { 320 reg = <0x0 0x808e4000 0x0 0x10000>; 321 no-map; 322 }; 323 324 secdata_apss_mem: secdata-apss@808ff000 { 325 reg = <0x0 0x808ff000 0x0 0x1000>; 326 no-map; 327 }; 328 329 smem: smem@80900000 { 330 compatible = "qcom,smem"; 331 reg = <0x0 0x80900000 0x0 0x200000>; 332 hwlocks = <&tcsr_mutex 3>; 333 no-map; 334 }; 335 336 cpucp_fw_mem: cpucp-fw@80b00000 { 337 reg = <0x0 0x80b00000 0x0 0x100000>; 338 no-map; 339 }; 340 341 helios_ram_dump_mem: helios-ram-dump@80c00000 { 342 reg = <0x0 0x80c00000 0x0 0xe00000>; 343 no-map; 344 }; 345 346 camera_mem: camera@84e00000 { 347 reg = <0x0 0x84e00000 0x0 0x800000>; 348 no-map; 349 }; 350 351 video_mem: video@86f00000 { 352 reg = <0x0 0x86f00000 0x0 0x500000>; 353 no-map; 354 }; 355 356 adsp_mem: adsp@87600000 { 357 reg = <0x0 0x87600000 0x0 0x1e00000>; 358 no-map; 359 }; 360 361 cdsp_mem: cdsp@89400000 { 362 reg = <0x0 0x89400000 0x0 0xf00000>; 363 no-map; 364 }; 365 366 ipa_fw_mem: ipa-fw@8a300000 { 367 reg = <0x0 0x8a300000 0x0 0x10000>; 368 no-map; 369 }; 370 371 ipa_gsi_mem: ipa-gsi@8a3a0000 { 372 reg = <0x0 0x8a310000 0x0 0xa000>; 373 no-map; 374 }; 375 376 gpu_micro_code_mem: gpu-micro-code@8a31a000 { 377 reg = <0x0 0x8a31a000 0x0 0x2000>; 378 no-map; 379 }; 380 381 cvp_mem: cvp@8a400000 { 382 reg = <0x0 0x8a400000 0x0 0x700000>; 383 no-map; 384 }; 385 386 xbl_sc_mem: xbl-sc@a6e00000 { 387 no-map; 388 reg = <0x0 0xa6e00000 0x0 0x40000>; 389 }; 390 391 global_sync_mem: global-sync@a6f00000 { 392 no-map; 393 reg = <0x0 0xa6f00000 0x0 0x100000>; 394 }; 395 396 tz_stat_mem: tz-stat@e8800000 { 397 no-map; 398 reg = <0x0 0xe8800000 0x0 0x100000>; 399 }; 400 401 tags_mem: tags@e8900000 { 402 no-map; 403 reg = <0x0 0xe8900000 0x0 0x500000>; 404 }; 405 406 qtee_mem: qtee@e8e00000 { 407 no-map; 408 reg = <0x0 0xe8e00000 0x0 0x500000>; 409 }; 410 411 trusted_apps_mem: trusted-apps@e9300000 { 412 no-map; 413 reg = <0x0 0xe9300000 0x0 0xc00000>; 414 }; 415 }; 416 417 smp2p-adsp { 418 compatible = "qcom,smp2p"; 419 qcom,smem = <443>, <429>; 420 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 421 IPCC_MPROC_SIGNAL_SMP2P 422 IRQ_TYPE_EDGE_RISING>; 423 mboxes = <&ipcc IPCC_CLIENT_LPASS 424 IPCC_MPROC_SIGNAL_SMP2P>; 425 426 qcom,local-pid = <0>; 427 qcom,remote-pid = <2>; 428 429 smp2p_adsp_out: master-kernel { 430 qcom,entry-name = "master-kernel"; 431 #qcom,smem-state-cells = <1>; 432 }; 433 434 smp2p_adsp_in: slave-kernel { 435 qcom,entry-name = "slave-kernel"; 436 interrupt-controller; 437 #interrupt-cells = <2>; 438 }; 439 }; 440 441 smp2p-cdsp { 442 compatible = "qcom,smp2p"; 443 qcom,smem = <94>, <432>; 444 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 445 IPCC_MPROC_SIGNAL_SMP2P 446 IRQ_TYPE_EDGE_RISING>; 447 mboxes = <&ipcc IPCC_CLIENT_CDSP 448 IPCC_MPROC_SIGNAL_SMP2P>; 449 450 qcom,local-pid = <0>; 451 qcom,remote-pid = <5>; 452 453 smp2p_cdsp_out: master-kernel { 454 qcom,entry-name = "master-kernel"; 455 #qcom,smem-state-cells = <1>; 456 }; 457 458 smp2p_cdsp_in: slave-kernel { 459 qcom,entry-name = "slave-kernel"; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 }; 463 }; 464 465 soc: soc@0 { 466 compatible = "simple-bus"; 467 #address-cells = <2>; 468 #size-cells = <2>; 469 ranges = <0 0 0 0 0x10 0>; 470 dma-ranges = <0 0 0 0 0x10 0>; 471 472 gcc: clock-controller@100000 { 473 compatible = "qcom,sar2130p-gcc"; 474 reg = <0x0 0x00100000 0x0 0x1f4200>; 475 #clock-cells = <1>; 476 #reset-cells = <1>; 477 #power-domain-cells = <1>; 478 clocks = <&rpmhcc RPMH_CXO_CLK>, 479 <&sleep_clk>, 480 <&pcie0_phy>, 481 <&pcie1_phy>, 482 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 483 }; 484 485 sdhc_1: mmc@7c4000 { 486 compatible = "qcom,sar2130p-sdhci", "qcom,sdhci-msm-v5"; 487 reg = <0x0 0x007c4000 0x0 0x1000>, 488 <0x0 0x007c5000 0x0 0x1000>; 489 reg-names = "hc", "cqhci"; 490 491 iommus = <&apps_smmu 0x160 0x0>; 492 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 494 interrupt-names = "hc_irq", "pwr_irq"; 495 496 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 497 <&gcc GCC_SDCC1_APPS_CLK>, 498 <&rpmhcc RPMH_CXO_CLK>; 499 clock-names = "iface", "core", "xo"; 500 interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 501 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 502 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 503 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; 504 interconnect-names = "sdhc-ddr","cpu-sdhc"; 505 power-domains = <&rpmhpd RPMHPD_CX>; 506 operating-points-v2 = <&sdhc1_opp_table>; 507 508 pinctrl-0 = <&sdc1_default>; 509 pinctrl-1 = <&sdc1_sleep>; 510 pinctrl-names = "default", "sleep"; 511 512 bus-width = <8>; 513 non-removable; 514 supports-cqe; 515 516 mmc-ddr-1_8v; 517 mmc-hs200-1_8v; 518 mmc-hs400-1_8v; 519 mmc-hs400-enhanced-strobe; 520 521 status = "disabled"; 522 523 sdhc1_opp_table: opp-table { 524 compatible = "operating-points-v2"; 525 526 opp-100000000 { 527 opp-hz = /bits/ 64 <100000000>; 528 required-opps = <&rpmhpd_opp_low_svs>; 529 opp-peak-kBps = <500000 200000>; 530 opp-avg-kBps = <104000 0>; 531 }; 532 533 opp-384000000 { 534 opp-hz = /bits/ 64 <384000000>; 535 required-opps = <&rpmhpd_opp_nom>; 536 opp-peak-kBps = <2500000 1000000>; 537 opp-avg-kBps = <400000 0>; 538 }; 539 }; 540 }; 541 542 gpi_dma0: dma-controller@900000 { 543 compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma"; 544 reg = <0x0 0x00900000 0x0 0x60000>; 545 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 557 #dma-cells = <3>; 558 dma-channels = <12>; 559 dma-channel-mask = <0x7e>; 560 iommus = <&apps_smmu 0x76 0x0>; 561 562 status = "disabled"; 563 }; 564 565 qupv3_id_0: geniqup@9c0000 { 566 compatible = "qcom,geni-se-qup"; 567 reg = <0x0 0x009c0000 0x0 0x2000>; 568 clock-names = "m-ahb", "s-ahb"; 569 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 570 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 571 iommus = <&apps_smmu 0x63 0x0>; 572 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 573 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; 574 interconnect-names = "qup-core"; 575 #address-cells = <2>; 576 #size-cells = <2>; 577 ranges; 578 579 status = "disabled"; 580 581 i2c0: i2c@980000 { 582 compatible = "qcom,geni-i2c"; 583 reg = <0x0 0x00980000 0x0 0x4000>; 584 clock-names = "se"; 585 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 586 pinctrl-0 = <&qup_i2c0_data_clk>; 587 pinctrl-names = "default"; 588 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 592 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 593 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 594 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 595 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 596 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 597 interconnect-names = "qup-core", "qup-config", "qup-memory"; 598 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 599 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 600 dma-names = "tx", "rx"; 601 602 status = "disabled"; 603 }; 604 605 spi0: spi@980000 { 606 compatible = "qcom,geni-spi"; 607 reg = <0x0 0x00980000 0x0 0x4000>; 608 clock-names = "se"; 609 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 610 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 611 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs0>; 612 pinctrl-names = "default"; 613 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 614 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 615 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 616 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 617 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 618 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 619 interconnect-names = "qup-core", "qup-config", "qup-memory"; 620 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 621 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 622 dma-names = "tx", "rx"; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 626 status = "disabled"; 627 }; 628 629 i2c1: i2c@984000 { 630 compatible = "qcom,geni-i2c"; 631 reg = <0x0 0x00984000 0x0 0x4000>; 632 clock-names = "se"; 633 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 634 pinctrl-0 = <&qup_i2c1_data_clk>; 635 pinctrl-names = "default"; 636 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 640 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 641 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 642 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 643 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 644 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 645 interconnect-names = "qup-core", "qup-config", "qup-memory"; 646 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 647 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 648 dma-names = "tx", "rx"; 649 650 status = "disabled"; 651 }; 652 653 spi1: spi@984000 { 654 compatible = "qcom,geni-spi"; 655 reg = <0x0 0x00984000 0x0 0x4000>; 656 clock-names = "se"; 657 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 658 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 659 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 660 pinctrl-names = "default"; 661 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 662 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 663 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 664 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 665 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 666 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 667 interconnect-names = "qup-core", "qup-config", "qup-memory"; 668 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 669 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 670 dma-names = "tx", "rx"; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 674 status = "disabled"; 675 }; 676 677 i2c2: i2c@988000 { 678 compatible = "qcom,geni-i2c"; 679 reg = <0x0 0x00988000 0x0 0x4000>; 680 clock-names = "se"; 681 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 682 pinctrl-0 = <&qup_i2c2_data_clk>; 683 pinctrl-names = "default"; 684 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 688 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 689 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 690 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 691 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 692 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 693 interconnect-names = "qup-core", "qup-config", "qup-memory"; 694 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 695 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 696 dma-names = "tx", "rx"; 697 698 status = "disabled"; 699 }; 700 701 spi2: spi@988000 { 702 compatible = "qcom,geni-spi"; 703 reg = <0x0 0x00988000 0x0 0x4000>; 704 clock-names = "se"; 705 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 706 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 707 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 708 pinctrl-names = "default"; 709 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 710 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 711 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 712 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 713 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 714 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 715 interconnect-names = "qup-core", "qup-config", "qup-memory"; 716 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 717 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 718 dma-names = "tx", "rx"; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 722 status = "disabled"; 723 }; 724 725 726 i2c3: i2c@98c000 { 727 compatible = "qcom,geni-i2c"; 728 reg = <0x0 0x0098c000 0x0 0x4000>; 729 clock-names = "se"; 730 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 731 pinctrl-0 = <&qup_i2c3_data_clk>; 732 pinctrl-names = "default"; 733 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 737 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 738 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 739 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 740 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 741 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 742 interconnect-names = "qup-core", "qup-config", "qup-memory"; 743 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 744 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 745 dma-names = "tx", "rx"; 746 747 status = "disabled"; 748 }; 749 750 spi3: spi@98c000 { 751 compatible = "qcom,geni-spi"; 752 reg = <0x0 0x0098c000 0x0 0x4000>; 753 clock-names = "se"; 754 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 755 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 756 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs0>; 757 pinctrl-names = "default"; 758 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 759 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 760 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 761 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 762 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 763 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 764 interconnect-names = "qup-core", "qup-config", "qup-memory"; 765 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 766 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 767 dma-names = "tx", "rx"; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 771 status = "disabled"; 772 }; 773 774 i2c4: i2c@990000 { 775 compatible = "qcom,geni-i2c"; 776 reg = <0x0 0x00990000 0x0 0x4000>; 777 clock-names = "se"; 778 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 779 pinctrl-0 = <&qup_i2c4_data_clk>; 780 pinctrl-names = "default"; 781 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 785 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 786 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 787 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 788 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 789 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 790 interconnect-names = "qup-core", "qup-config", "qup-memory"; 791 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 792 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 793 dma-names = "tx", "rx"; 794 795 status = "disabled"; 796 }; 797 798 spi4: spi@990000 { 799 compatible = "qcom,geni-spi"; 800 reg = <0x0 0x00990000 0x0 0x4000>; 801 clock-names = "se"; 802 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 803 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 804 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs0>; 805 pinctrl-names = "default"; 806 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 807 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 808 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 809 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 810 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 811 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 812 interconnect-names = "qup-core", "qup-config", "qup-memory"; 813 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 814 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 815 dma-names = "tx", "rx"; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 819 status = "disabled"; 820 }; 821 822 i2c5: i2c@994000 { 823 compatible = "qcom,geni-i2c"; 824 reg = <0x0 0x00994000 0x0 0x4000>; 825 clock-names = "se"; 826 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 827 pinctrl-0 = <&qup_i2c5_data_clk>; 828 pinctrl-names = "default"; 829 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 833 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 834 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 835 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 836 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 837 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 838 interconnect-names = "qup-core", "qup-config", "qup-memory"; 839 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 840 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 841 dma-names = "tx", "rx"; 842 843 status = "disabled"; 844 }; 845 846 spi5: spi@994000 { 847 compatible = "qcom,geni-spi"; 848 reg = <0x0 0x00994000 0x0 0x4000>; 849 clock-names = "se"; 850 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 851 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 852 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 853 pinctrl-names = "default"; 854 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 855 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 856 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 857 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 858 <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 859 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 860 interconnect-names = "qup-core", "qup-config", "qup-memory"; 861 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 862 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 863 dma-names = "tx", "rx"; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 867 status = "disabled"; 868 }; 869 }; 870 871 gpi_dma1: dma-controller@a00000 { 872 compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma"; 873 #dma-cells = <3>; 874 reg = <0x0 0x00a00000 0x0 0x60000>; 875 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 887 dma-channels = <12>; 888 dma-channel-mask = <0x7e>; 889 iommus = <&apps_smmu 0x16 0x0>; 890 891 status = "disabled"; 892 }; 893 894 qupv3_id_1: geniqup@ac0000 { 895 compatible = "qcom,geni-se-qup"; 896 reg = <0x0 0x00ac0000 0x0 0x6000>; 897 clock-names = "m-ahb", "s-ahb"; 898 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 899 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 900 iommus = <&apps_smmu 0x3 0x0>; 901 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 902 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 903 interconnect-names = "qup-core"; 904 #address-cells = <2>; 905 #size-cells = <2>; 906 ranges; 907 908 status = "disabled"; 909 910 i2c6: i2c@a80000 { 911 compatible = "qcom,geni-i2c"; 912 reg = <0x0 0x00a80000 0x0 0x4000>; 913 clock-names = "se"; 914 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 915 pinctrl-0 = <&qup_i2c6_data_clk>; 916 pinctrl-names = "default"; 917 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 921 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 922 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 923 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 924 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 926 interconnect-names = "qup-core", "qup-config", "qup-memory"; 927 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 928 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 929 dma-names = "tx", "rx"; 930 931 status = "disabled"; 932 }; 933 934 spi6: spi@a80000 { 935 compatible = "qcom,geni-spi"; 936 reg = <0x0 0x00a80000 0x0 0x4000>; 937 clock-names = "se"; 938 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 939 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 940 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 941 pinctrl-names = "default"; 942 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 943 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 944 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 945 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 946 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 947 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 948 interconnect-names = "qup-core", "qup-config", "qup-memory"; 949 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 950 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 951 dma-names = "tx", "rx"; 952 #address-cells = <1>; 953 #size-cells = <0>; 954 955 status = "disabled"; 956 }; 957 958 i2c7: i2c@a84000 { 959 compatible = "qcom,geni-i2c"; 960 reg = <0x0 0x00a84000 0x0 0x4000>; 961 clock-names = "se"; 962 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 963 pinctrl-0 = <&qup_i2c7_data_clk>; 964 pinctrl-names = "default"; 965 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 969 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 970 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 971 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 972 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 973 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 974 interconnect-names = "qup-core", "qup-config", "qup-memory"; 975 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 976 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 977 dma-names = "tx", "rx"; 978 979 status = "disabled"; 980 }; 981 982 spi7: spi@a84000 { 983 compatible = "qcom,geni-spi"; 984 reg = <0x0 0x00a84000 0x0 0x4000>; 985 clock-names = "se"; 986 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 987 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 988 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 989 pinctrl-names = "default"; 990 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 991 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 992 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 993 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 994 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 996 interconnect-names = "qup-core", "qup-config", "qup-memory"; 997 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 998 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 999 dma-names = "tx", "rx"; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 1003 status = "disabled"; 1004 }; 1005 1006 uart7: serial@a84000 { 1007 compatible = "qcom,geni-uart"; 1008 reg = <0x0 0x00a84000 0x0 0x4000>; 1009 clock-names = "se"; 1010 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1011 pinctrl-0 = <&qup_uart7_default>; 1012 pinctrl-names = "default"; 1013 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1014 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1015 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1016 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1017 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>; 1018 interconnect-names = "qup-core", "qup-config"; 1019 1020 status = "disabled"; 1021 }; 1022 1023 i2c8: i2c@a88000 { 1024 compatible = "qcom,geni-i2c"; 1025 reg = <0x0 0x00a88000 0x0 0x4000>; 1026 clock-names = "se"; 1027 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1028 pinctrl-0 = <&qup_i2c8_data_clk>; 1029 pinctrl-names = "default"; 1030 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1034 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1035 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1036 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1037 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1038 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1039 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1040 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1041 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1042 dma-names = "tx", "rx"; 1043 1044 status = "disabled"; 1045 }; 1046 1047 spi8: spi@a88000 { 1048 compatible = "qcom,geni-spi"; 1049 reg = <0x0 0x00a88000 0x0 0x4000>; 1050 clock-names = "se"; 1051 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1052 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1053 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1054 pinctrl-names = "default"; 1055 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1056 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1057 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1058 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1059 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1060 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1061 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1062 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1063 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1064 dma-names = "tx", "rx"; 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 1068 status = "disabled"; 1069 }; 1070 1071 i2c9: i2c@a8c000 { 1072 compatible = "qcom,geni-i2c"; 1073 reg = <0x0 0x00a8c000 0x0 0x4000>; 1074 clock-names = "se"; 1075 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1076 pinctrl-0 = <&qup_i2c9_data_clk>; 1077 pinctrl-names = "default"; 1078 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1082 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1083 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1084 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1085 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1086 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1087 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1088 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1089 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1090 dma-names = "tx", "rx"; 1091 1092 status = "disabled"; 1093 }; 1094 1095 spi9: spi@a8c000 { 1096 compatible = "qcom,geni-spi"; 1097 reg = <0x0 0x00a8c000 0x0 0x4000>; 1098 clock-names = "se"; 1099 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1100 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1101 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1102 pinctrl-names = "default"; 1103 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1104 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1105 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1106 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1107 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1108 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1109 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1110 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1111 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1112 dma-names = "tx", "rx"; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 1116 status = "disabled"; 1117 }; 1118 1119 i2c10: i2c@a90000 { 1120 compatible = "qcom,geni-i2c"; 1121 reg = <0x0 0x00a90000 0x0 0x4000>; 1122 clock-names = "se"; 1123 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1124 pinctrl-0 = <&qup_i2c10_data_clk>; 1125 pinctrl-names = "default"; 1126 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1130 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1131 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1132 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1133 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1134 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1135 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1136 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1137 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1138 dma-names = "tx", "rx"; 1139 1140 status = "disabled"; 1141 }; 1142 1143 spi10: spi@a90000 { 1144 compatible = "qcom,geni-spi"; 1145 reg = <0x0 0x00a90000 0x0 0x4000>; 1146 clock-names = "se"; 1147 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1148 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1149 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1150 pinctrl-names = "default"; 1151 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1152 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1153 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1154 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1155 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1156 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1157 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1158 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1159 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1160 dma-names = "tx", "rx"; 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 1164 status = "disabled"; 1165 }; 1166 1167 i2c11: i2c@a94000 { 1168 compatible = "qcom,geni-i2c"; 1169 reg = <0x0 0x00a94000 0x0 0x4000>; 1170 clock-names = "se"; 1171 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1172 pinctrl-0 = <&qup_i2c11_data_clk>; 1173 pinctrl-names = "default"; 1174 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1178 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1179 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1180 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1181 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1182 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1183 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1184 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1185 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1186 dma-names = "tx", "rx"; 1187 1188 status = "disabled"; 1189 }; 1190 1191 spi11: spi@a94000 { 1192 compatible = "qcom,geni-spi"; 1193 reg = <0x0 0x00a94000 0x0 0x4000>; 1194 clock-names = "se"; 1195 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1196 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1197 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1198 pinctrl-names = "default"; 1199 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1200 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1201 <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS 1202 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 1203 <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1204 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1205 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1206 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1207 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1208 dma-names = "tx", "rx"; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 1212 status = "disabled"; 1213 }; 1214 1215 uart11: serial@a94000 { 1216 compatible = "qcom,geni-debug-uart"; 1217 reg = <0x0 0x00a94000 0x0 0x4000>; 1218 clock-names = "se"; 1219 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1220 pinctrl-0 = <&qup_uart11_default>; 1221 pinctrl-names = "default"; 1222 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1223 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1224 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1225 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1226 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1227 interconnect-names = "qup-core", 1228 "qup-config"; 1229 1230 status = "disabled"; 1231 }; 1232 }; 1233 1234 config_noc: interconnect@1500000 { 1235 compatible = "qcom,sar2130p-config-noc"; 1236 reg = <0x0 0x01500000 0x0 0x10>; 1237 #interconnect-cells = <2>; 1238 qcom,bcm-voters = <&apps_bcm_voter>; 1239 }; 1240 1241 system_noc: interconnect@1680000 { 1242 compatible = "qcom,sar2130p-system-noc"; 1243 reg = <0x0 0x01680000 0x0 0x29080>; 1244 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1245 #interconnect-cells = <2>; 1246 qcom,bcm-voters = <&apps_bcm_voter>; 1247 }; 1248 1249 pcie_noc: interconnect@16c0000 { 1250 compatible = "qcom,sar2130p-pcie-anoc"; 1251 reg = <0x0 0x016c0000 0x0 0xa080>; 1252 clocks = <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1253 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1254 #interconnect-cells = <2>; 1255 qcom,bcm-voters = <&apps_bcm_voter>; 1256 }; 1257 1258 mmss_noc: interconnect@1740000 { 1259 compatible = "qcom,sar2130p-mmss-noc"; 1260 reg = <0x0 0x01740000 0x0 0x1f100>; 1261 #interconnect-cells = <2>; 1262 qcom,bcm-voters = <&apps_bcm_voter>; 1263 }; 1264 1265 pcie0: pcie@1c00000 { 1266 device_type = "pci"; 1267 compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550"; 1268 reg = <0x0 0x01c00000 0x0 0x3000>, 1269 <0x0 0x60000000 0x0 0xf1d>, 1270 <0x0 0x60000f20 0x0 0xa8>, 1271 <0x0 0x60001000 0x0 0x1000>, 1272 <0x0 0x60100000 0x0 0x100000>, 1273 <0x0 0x01c0c000 0x0 0x1000>; 1274 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1275 #address-cells = <3>; 1276 #size-cells = <2>; 1277 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1278 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1279 bus-range = <0x00 0xff>; 1280 1281 dma-coherent; 1282 1283 linux,pci-domain = <0>; 1284 num-lanes = <2>; 1285 1286 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1295 interrupt-names = "msi0", 1296 "msi1", 1297 "msi2", 1298 "msi3", 1299 "msi4", 1300 "msi5", 1301 "msi6", 1302 "msi7", 1303 "global"; 1304 #interrupt-cells = <1>; 1305 interrupt-map-mask = <0 0 0 0x7>; 1306 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1307 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1308 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1309 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1310 1311 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1312 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1313 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1314 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1315 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1316 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 1317 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1318 clock-names = "aux", 1319 "cfg", 1320 "bus_master", 1321 "bus_slave", 1322 "slave_q2a", 1323 "ddrss_sf_tbu", 1324 "noc_aggr"; 1325 1326 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 1327 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1328 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1329 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 1330 interconnect-names = "pcie-mem", "cpu-pcie"; 1331 1332 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1333 <0x100 &apps_smmu 0x1c01 0x1>; 1334 1335 resets = <&gcc GCC_PCIE_0_BCR>; 1336 reset-names = "pci"; 1337 1338 power-domains = <&gcc PCIE_0_GDSC>; 1339 1340 phys = <&pcie0_phy>; 1341 phy-names = "pciephy"; 1342 1343 status = "disabled"; 1344 1345 pcieport0: pcie@0 { 1346 device_type = "pci"; 1347 reg = <0x0 0x0 0x0 0x0 0x0>; 1348 bus-range = <0x01 0xff>; 1349 1350 #address-cells = <3>; 1351 #size-cells = <2>; 1352 ranges; 1353 }; 1354 }; 1355 1356 pcie0_phy: phy@1c06000 { 1357 compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy"; 1358 reg = <0x0 0x01c06000 0x0 0x2000>; 1359 1360 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1361 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1362 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 1363 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1364 <&gcc GCC_PCIE_0_PIPE_CLK>; 1365 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1366 "pipe"; 1367 1368 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1369 reset-names = "phy"; 1370 1371 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1372 assigned-clock-rates = <100000000>; 1373 1374 power-domains = <&gcc PCIE_0_PHY_GDSC>; 1375 1376 #clock-cells = <0>; 1377 clock-output-names = "pcie0_pipe_clk"; 1378 1379 #phy-cells = <0>; 1380 1381 status = "disabled"; 1382 }; 1383 1384 pcie1: pcie@1c08000 { 1385 device_type = "pci"; 1386 compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550"; 1387 reg = <0x0 0x01c08000 0x0 0x3000>, 1388 <0x0 0x40000000 0x0 0xf1d>, 1389 <0x0 0x40000f20 0x0 0xa8>, 1390 <0x0 0x40001000 0x0 0x1000>, 1391 <0x0 0x40100000 0x0 0x100000>, 1392 <0x0 0x01c0b000 0x0 0x1000>; 1393 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1394 #address-cells = <3>; 1395 #size-cells = <2>; 1396 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1397 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1398 bus-range = <0x00 0xff>; 1399 1400 dma-coherent; 1401 1402 linux,pci-domain = <1>; 1403 num-lanes = <2>; 1404 1405 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1414 interrupt-names = "msi0", 1415 "msi1", 1416 "msi2", 1417 "msi3", 1418 "msi4", 1419 "msi5", 1420 "msi6", 1421 "msi7", 1422 "global"; 1423 #interrupt-cells = <1>; 1424 interrupt-map-mask = <0 0 0 0x7>; 1425 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1426 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1427 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1428 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1429 1430 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1431 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1432 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1433 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1434 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1435 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 1436 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1437 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, 1438 <&gcc GCC_QMIP_PCIE_AHB_CLK>; 1439 clock-names = "aux", 1440 "cfg", 1441 "bus_master", 1442 "bus_slave", 1443 "slave_q2a", 1444 "ddrss_sf_tbu", 1445 "noc_aggr", 1446 "cnoc_sf_axi", 1447 "qmip_pcie_ahb"; 1448 1449 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1450 assigned-clock-rates = <19200000>; 1451 1452 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 1453 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1454 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1455 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 1456 interconnect-names = "pcie-mem", "cpu-pcie"; 1457 1458 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1459 <0x100 &apps_smmu 0x1e01 0x1>; 1460 1461 resets = <&gcc GCC_PCIE_1_BCR>, 1462 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 1463 reset-names = "pci", "link_down"; 1464 1465 power-domains = <&gcc PCIE_1_GDSC>; 1466 1467 phys = <&pcie1_phy>; 1468 phy-names = "pciephy"; 1469 1470 status = "disabled"; 1471 1472 pcie@0 { 1473 device_type = "pci"; 1474 reg = <0x0 0x0 0x0 0x0 0x0>; 1475 bus-range = <0x01 0xff>; 1476 1477 #address-cells = <3>; 1478 #size-cells = <2>; 1479 ranges; 1480 }; 1481 }; 1482 1483 pcie1_ep: pcie-ep@1c08000 { 1484 compatible = "qcom,sar2130p-pcie-ep"; 1485 reg = <0x0 0x01c08000 0x0 0x3000>, 1486 <0x0 0x40000000 0x0 0xf1d>, 1487 <0x0 0x40000f20 0x0 0xa8>, 1488 <0x0 0x40001000 0x0 0x1000>, 1489 <0x0 0x40200000 0x0 0x1000000>, 1490 <0x0 0x01c0b000 0x0 0x1000>, 1491 <0x0 0x40002000 0x0 0x2000>; 1492 reg-names = "parf", 1493 "dbi", 1494 "elbi", 1495 "atu", 1496 "addr_space", 1497 "mmio", 1498 "dma"; 1499 1500 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1501 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1502 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1503 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1504 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1505 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 1506 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1507 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, 1508 <&gcc GCC_QMIP_PCIE_AHB_CLK>; 1509 clock-names = "aux", 1510 "cfg", 1511 "bus_master", 1512 "bus_slave", 1513 "slave_q2a", 1514 "ddrss_sf_tbu", 1515 "aggre_noc_axi", 1516 "cnoc_sf_axi", 1517 "qmip_pcie_ahb"; 1518 1519 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1522 interrupt-names = "global", 1523 "doorbell", 1524 "dma"; 1525 1526 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 1527 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1528 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1529 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1530 interconnect-names = "pcie-mem", 1531 "cpu-pcie"; 1532 iommus = <&apps_smmu 0x1e00 0x1>; 1533 resets = <&gcc GCC_PCIE_1_BCR>; 1534 reset-names = "core"; 1535 power-domains = <&gcc PCIE_1_GDSC>; 1536 phys = <&pcie1_phy>; 1537 phy-names = "pciephy"; 1538 1539 num-lanes = <2>; 1540 1541 status = "disabled"; 1542 }; 1543 1544 pcie1_phy: phy@1c0e000 { 1545 compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy"; 1546 reg = <0x0 0x01c0e000 0x0 0x2000>; 1547 1548 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1549 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1550 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 1551 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1552 <&gcc GCC_PCIE_1_PIPE_CLK>; 1553 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1554 "pipe"; 1555 1556 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1557 reset-names = "phy"; 1558 1559 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1560 assigned-clock-rates = <100000000>; 1561 1562 power-domains = <&gcc PCIE_1_PHY_GDSC>; 1563 1564 #clock-cells = <0>; 1565 clock-output-names = "pcie1_pipe_clk"; 1566 1567 #phy-cells = <0>; 1568 1569 status = "disabled"; 1570 }; 1571 1572 tcsr_mutex: hwlock@1f40000 { 1573 compatible = "qcom,tcsr-mutex"; 1574 reg = <0x0 0x01f40000 0x0 0x20000>; 1575 1576 #hwlock-cells = <1>; 1577 }; 1578 1579 tcsr: clock-controller@1fc0000 { 1580 compatible = "qcom,sar2130p-tcsr", "syscon"; 1581 reg = <0x0 0x01fc0000 0x0 0x30000>; 1582 clocks = <&rpmhcc RPMH_CXO_CLK>; 1583 #clock-cells = <1>; 1584 #reset-cells = <1>; 1585 }; 1586 1587 remoteproc_adsp: remoteproc@3000000 { 1588 compatible = "qcom,sar2130p-adsp-pas"; 1589 reg = <0x0 0x03000000 0x0 0x10000>; 1590 1591 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1592 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1593 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1594 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1595 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1596 interrupt-names = "wdog", "fatal", "ready", 1597 "handover", "stop-ack"; 1598 1599 clocks = <&rpmhcc RPMH_CXO_CLK>; 1600 clock-names = "xo"; 1601 1602 power-domains = <&rpmhpd RPMHPD_LCX>, 1603 <&rpmhpd RPMHPD_LMX>; 1604 power-domain-names = "lcx", "lmx"; 1605 1606 memory-region = <&adsp_mem>; 1607 1608 qcom,qmp = <&aoss_qmp>; 1609 1610 qcom,smem-states = <&smp2p_adsp_out 0>; 1611 qcom,smem-state-names = "stop"; 1612 1613 status = "disabled"; 1614 1615 remoteproc_adsp_glink: glink-edge { 1616 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1617 IPCC_MPROC_SIGNAL_GLINK_QMP 1618 IRQ_TYPE_EDGE_RISING>; 1619 mboxes = <&ipcc IPCC_CLIENT_LPASS 1620 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1621 1622 label = "lpass"; 1623 qcom,remote-pid = <2>; 1624 1625 gpr { 1626 compatible = "qcom,gpr"; 1627 qcom,glink-channels = "adsp_apps"; 1628 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 1629 qcom,intents = <512 20>; 1630 #address-cells = <1>; 1631 #size-cells = <0>; 1632 1633 q6apm: service@1 { 1634 compatible = "qcom,q6apm"; 1635 reg = <GPR_APM_MODULE_IID>; 1636 #sound-dai-cells = <0>; 1637 qcom,protection-domain = "avs/audio", 1638 "msm/adsp/audio_pd"; 1639 1640 q6apmdai: dais { 1641 compatible = "qcom,q6apm-dais"; 1642 iommus = <&apps_smmu 0x1801 0x0>; 1643 }; 1644 1645 q6apmbedai: bedais { 1646 compatible = "qcom,q6apm-lpass-dais"; 1647 #sound-dai-cells = <1>; 1648 }; 1649 }; 1650 1651 q6prm: service@2 { 1652 compatible = "qcom,q6prm"; 1653 reg = <GPR_PRM_MODULE_IID>; 1654 qcom,protection-domain = "avs/audio", 1655 "msm/adsp/audio_pd"; 1656 1657 q6prmcc: clock-controller { 1658 compatible = "qcom,q6prm-lpass-clocks"; 1659 #clock-cells = <2>; 1660 }; 1661 }; 1662 }; 1663 1664 fastrpc { 1665 compatible = "qcom,fastrpc"; 1666 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1667 label = "adsp"; 1668 qcom,non-secure-domain; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 1672 compute-cb@3 { 1673 compatible = "qcom,fastrpc-compute-cb"; 1674 reg = <3>; 1675 iommus = <&apps_smmu 0x1803 0x0>; 1676 }; 1677 1678 compute-cb@4 { 1679 compatible = "qcom,fastrpc-compute-cb"; 1680 reg = <4>; 1681 iommus = <&apps_smmu 0x1804 0x0>; 1682 }; 1683 1684 compute-cb@5 { 1685 compatible = "qcom,fastrpc-compute-cb"; 1686 reg = <5>; 1687 iommus = <&apps_smmu 0x1805 0x0>; 1688 }; 1689 1690 compute-cb@6 { 1691 compatible = "qcom,fastrpc-compute-cb"; 1692 reg = <6>; 1693 iommus = <&apps_smmu 0x1806 0x0>; 1694 }; 1695 }; 1696 }; 1697 }; 1698 1699 gpu: gpu@3d00000 { 1700 compatible = "qcom,adreno-621.0", "qcom,adreno"; 1701 reg = <0x0 0x03d00000 0x0 0x40000>, 1702 <0x0 0x03d9e000 0x0 0x2000>, 1703 <0x0 0x03d61000 0x0 0x800>; 1704 reg-names = "kgsl_3d0_reg_memory", 1705 "cx_mem", 1706 "cx_dbgc"; 1707 1708 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1709 1710 iommus = <&adreno_smmu 0 0x401>; 1711 1712 operating-points-v2 = <&gpu_opp_table>; 1713 1714 qcom,gmu = <&gmu>; 1715 1716 nvmem-cells = <&gpu_speed_bin>; 1717 nvmem-cell-names = "speed_bin"; 1718 #cooling-cells = <2>; 1719 1720 status = "disabled"; 1721 1722 gpu_zap_shader: zap-shader { 1723 memory-region = <&gpu_micro_code_mem>; 1724 }; 1725 1726 gpu_opp_table: opp-table { 1727 compatible = "operating-points-v2"; 1728 1729 opp-843000000 { 1730 opp-hz = /bits/ 64 <843000000>; 1731 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1732 opp-supported-hw = <0x1>; 1733 }; 1734 1735 opp-780000000 { 1736 opp-hz = /bits/ 64 <780000000>; 1737 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1738 opp-supported-hw = <0x1>; 1739 }; 1740 1741 opp-644000000 { 1742 opp-hz = /bits/ 64 <644000000>; 1743 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1744 opp-supported-hw = <0x3>; 1745 }; 1746 1747 opp-570000000 { 1748 opp-hz = /bits/ 64 <570000000>; 1749 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1750 opp-supported-hw = <0x3>; 1751 }; 1752 1753 opp-450000000 { 1754 opp-hz = /bits/ 64 <450000000>; 1755 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1756 opp-supported-hw = <0x3>; 1757 }; 1758 1759 opp-320000000 { 1760 opp-hz = /bits/ 64 <320000000>; 1761 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1762 opp-supported-hw = <0x3>; 1763 }; 1764 1765 opp-235000000 { 1766 opp-hz = /bits/ 64 <235000000>; 1767 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 1768 opp-supported-hw = <0x3>; 1769 }; 1770 }; 1771 }; 1772 1773 gmu: gmu@3d6a000 { 1774 compatible = "qcom,adreno-gmu-621.0", "qcom,adreno-gmu"; 1775 reg = <0x0 0x03d6a000 0x0 0x35000>, 1776 <0x0 0x03de0000 0x0 0x10000>, 1777 <0x0 0x0b290000 0x0 0x10000>; 1778 reg-names = "gmu", "rscc", "gmu_pdc"; 1779 1780 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1782 interrupt-names = "hfi", "gmu"; 1783 1784 clocks = <&gpucc GPU_CC_AHB_CLK>, 1785 <&gpucc GPU_CC_CX_GMU_CLK>, 1786 <&gpucc GPU_CC_CXO_CLK>, 1787 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1788 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1789 <&gpucc GPU_CC_HUB_CX_INT_CLK>; 1790 clock-names = "ahb", 1791 "gmu", 1792 "cxo", 1793 "axi", 1794 "memnoc", 1795 "hub"; 1796 1797 power-domains = <&gpucc GPU_CX_GDSC>, 1798 <&gpucc GPU_GX_GDSC>; 1799 power-domain-names = "cx", 1800 "gx"; 1801 1802 iommus = <&adreno_smmu 5 0x400>; 1803 1804 qcom,qmp = <&aoss_qmp>; 1805 1806 operating-points-v2 = <&gmu_opp_table>; 1807 1808 gmu_opp_table: opp-table { 1809 compatible = "operating-points-v2"; 1810 1811 opp-220000000 { 1812 opp-hz = /bits/ 64 <220000000>; 1813 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1814 }; 1815 1816 opp-550000000 { 1817 opp-hz = /bits/ 64 <550000000>; 1818 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1819 }; 1820 }; 1821 }; 1822 1823 gpucc: clock-controller@3d90000 { 1824 compatible = "qcom,sar2130p-gpucc"; 1825 reg = <0x0 0x03d90000 0x0 0xa000>; 1826 1827 clocks = <&rpmhcc RPMH_CXO_CLK>, 1828 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1829 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1830 1831 #clock-cells = <1>; 1832 #reset-cells = <1>; 1833 #power-domain-cells = <1>; 1834 }; 1835 1836 adreno_smmu: iommu@3da0000 { 1837 compatible = "qcom,sar2130p-smmu-500", "qcom,adreno-smmu", 1838 "qcom,smmu-500", "arm,mmu-500"; 1839 reg = <0x0 0x03da0000 0x0 0x10000>; 1840 #iommu-cells = <2>; 1841 #global-interrupts = <1>; 1842 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 1851 1852 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1853 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1854 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1855 <&gpucc GPU_CC_AHB_CLK>; 1856 clock-names = "hlos", 1857 "bus", 1858 "iface", 1859 "ahb"; 1860 power-domains = <&gpucc GPU_CX_GDSC>; 1861 dma-coherent; 1862 }; 1863 1864 usb_1_hsphy: phy@88e3000 { 1865 compatible = "qcom,sar2130p-snps-eusb2-phy", 1866 "qcom,sm8550-snps-eusb2-phy"; 1867 reg = <0x0 0x088e3000 0x0 0x154>; 1868 #phy-cells = <0>; 1869 1870 clocks = <&tcsr TCSR_USB2_CLKREF_EN>; 1871 clock-names = "ref"; 1872 1873 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1874 1875 status = "disabled"; 1876 }; 1877 1878 usb_dp_qmpphy: phy@88e8000 { 1879 compatible = "qcom,sar2130p-qmp-usb3-dp-phy"; 1880 reg = <0x0 0x088e8000 0x0 0x3000>; 1881 1882 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1883 <&rpmhcc RPMH_CXO_CLK>, 1884 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1885 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1886 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1887 1888 power-domains = <&gcc USB3_PHY_GDSC>; 1889 1890 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1891 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1892 reset-names = "phy", "common"; 1893 1894 #clock-cells = <1>; 1895 #phy-cells = <1>; 1896 1897 orientation-switch; 1898 1899 status = "disabled"; 1900 1901 ports { 1902 #address-cells = <1>; 1903 #size-cells = <0>; 1904 1905 port@0 { 1906 reg = <0>; 1907 1908 usb_dp_qmpphy_out: endpoint { 1909 }; 1910 }; 1911 1912 port@1 { 1913 reg = <1>; 1914 1915 usb_dp_qmpphy_usb_ss_in: endpoint { 1916 remote-endpoint = <&usb_1_dwc3_ss>; 1917 }; 1918 }; 1919 1920 port@2 { 1921 reg = <2>; 1922 1923 usb_dp_qmpphy_dp_in: endpoint { 1924 remote-endpoint = <&mdss_dp0_out>; 1925 }; 1926 }; 1927 }; 1928 }; 1929 1930 usb_1: usb@a6f8800 { 1931 compatible = "qcom,sar2130p-dwc3", "qcom,dwc3"; 1932 reg = <0x0 0x0a6f8800 0x0 0x400>; 1933 #address-cells = <2>; 1934 #size-cells = <2>; 1935 ranges; 1936 1937 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1938 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1939 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1940 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1941 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1942 <&tcsr TCSR_USB3_CLKREF_EN>; 1943 clock-names = "cfg_noc", 1944 "core", 1945 "iface", 1946 "sleep", 1947 "mock_utmi", 1948 "xo"; 1949 1950 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1951 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1952 assigned-clock-rates = <19200000>, <200000000>; 1953 1954 interrupts-extended = <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1955 <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1956 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1957 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1958 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1959 interrupt-names = "pwr_event", 1960 "hs_phy_irq", 1961 "dp_hs_phy_irq", 1962 "dm_hs_phy_irq", 1963 "ss_phy_irq"; 1964 1965 power-domains = <&gcc USB30_PRIM_GDSC>; 1966 required-opps = <&rpmhpd_opp_nom>; 1967 1968 resets = <&gcc GCC_USB30_PRIM_BCR>; 1969 1970 interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 1971 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1972 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1973 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 1974 interconnect-names = "usb-ddr", "apps-usb"; 1975 1976 status = "disabled"; 1977 1978 usb_1_dwc3: usb@a600000 { 1979 compatible = "snps,dwc3"; 1980 reg = <0x0 0x0a600000 0x0 0xcd00>; 1981 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 1982 iommus = <&apps_smmu 0x20 0x0>; 1983 phys = <&usb_1_hsphy>, 1984 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 1985 phy-names = "usb2-phy", "usb3-phy"; 1986 1987 snps,has-lpm-erratum; 1988 snps,hird-threshold = /bits/ 8 <0x0>; 1989 snps,is-utmi-l1-suspend; 1990 snps,dis-u1-entry-quirk; 1991 snps,dis-u2-entry-quirk; 1992 snps,dis_u2_susphy_quirk; 1993 snps,dis_u3_susphy_quirk; 1994 snps,parkmode-disable-ss-quirk; 1995 1996 tx-fifo-resize; 1997 dma-coherent; 1998 usb-role-switch; 1999 2000 ports { 2001 #address-cells = <1>; 2002 #size-cells = <0>; 2003 2004 port@0 { 2005 reg = <0>; 2006 2007 usb_1_dwc3_hs: endpoint { 2008 }; 2009 }; 2010 2011 port@1 { 2012 reg = <1>; 2013 2014 usb_1_dwc3_ss: endpoint { 2015 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 2016 }; 2017 }; 2018 }; 2019 }; 2020 }; 2021 2022 mdss: display-subsystem@ae00000 { 2023 compatible = "qcom,sar2130p-mdss"; 2024 reg = <0x0 0x0ae00000 0x0 0x1000>; 2025 reg-names = "mdss"; 2026 2027 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2028 interrupt-controller; 2029 #interrupt-cells = <1>; 2030 2031 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2032 <&gcc GCC_DISP_AHB_CLK>, 2033 <&gcc GCC_DISP_HF_AXI_CLK>, 2034 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2035 2036 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2037 2038 power-domains = <&dispcc MDSS_GDSC>; 2039 2040 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 2041 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2042 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2043 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2044 interconnect-names = "mdp0-mem", "cpu-cfg"; 2045 2046 iommus = <&apps_smmu 0x2000 0x402>; 2047 2048 #address-cells = <2>; 2049 #size-cells = <2>; 2050 ranges; 2051 2052 status = "disabled"; 2053 2054 mdss_mdp: display-controller@ae01000 { 2055 compatible = "qcom,sar2130p-dpu"; 2056 reg = <0x0 0x0ae01000 0x0 0x8f000>, 2057 <0x0 0x0aeb0000 0x0 0x3000>; 2058 reg-names = "mdp", 2059 "vbif"; 2060 2061 interrupt-parent = <&mdss>; 2062 interrupts = <0>; 2063 2064 clocks = <&gcc GCC_DISP_AHB_CLK>, 2065 <&gcc GCC_DISP_HF_AXI_CLK>, 2066 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2067 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2068 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2069 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2070 clock-names = "bus", 2071 "nrt_bus", 2072 "iface", 2073 "lut", 2074 "core", 2075 "vsync"; 2076 2077 power-domains = <&rpmhpd RPMHPD_MMCX>; 2078 2079 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2080 assigned-clock-rates = <19200000>; 2081 2082 operating-points-v2 = <&mdp_opp_table>; 2083 2084 ports { 2085 #address-cells = <1>; 2086 #size-cells = <0>; 2087 2088 port@0 { 2089 reg = <0>; 2090 2091 dpu_intf1_out: endpoint { 2092 remote-endpoint = <&mdss_dsi0_in>; 2093 }; 2094 }; 2095 2096 port@1 { 2097 reg = <1>; 2098 2099 dpu_intf2_out: endpoint { 2100 remote-endpoint = <&mdss_dsi1_in>; 2101 }; 2102 }; 2103 2104 port@2 { 2105 reg = <2>; 2106 2107 dpu_intf0_out: endpoint { 2108 remote-endpoint = <&mdss_dp0_in>; 2109 }; 2110 }; 2111 }; 2112 2113 mdp_opp_table: opp-table { 2114 compatible = "operating-points-v2"; 2115 2116 opp-200000000 { 2117 opp-hz = /bits/ 64 <200000000>; 2118 required-opps = <&rpmhpd_opp_low_svs>; 2119 }; 2120 2121 opp-325000000 { 2122 opp-hz = /bits/ 64 <325000000>; 2123 required-opps = <&rpmhpd_opp_svs>; 2124 }; 2125 2126 opp-514000000 { 2127 opp-hz = /bits/ 64 <514000000>; 2128 required-opps = <&rpmhpd_opp_turbo>; 2129 }; 2130 }; 2131 }; 2132 2133 mdss_dp0: displayport-controller@ae90000 { 2134 compatible = "qcom,sar2130p-dp", 2135 "qcom,sm8350-dp"; 2136 reg = <0x0 0xae90000 0x0 0x200>, 2137 <0x0 0xae90200 0x0 0x200>, 2138 <0x0 0xae90400 0x0 0xc00>, 2139 <0x0 0xae91000 0x0 0x400>, 2140 <0x0 0xae91400 0x0 0x400>; 2141 interrupt-parent = <&mdss>; 2142 interrupts = <12>; 2143 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2144 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 2145 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 2146 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 2147 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 2148 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 2149 clock-names = "core_iface", 2150 "core_aux", 2151 "ctrl_link", 2152 "ctrl_link_iface", 2153 "stream_pixel", 2154 "stream_1_pixel"; 2155 2156 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 2157 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 2158 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 2159 assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2160 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2161 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2162 2163 phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; 2164 phy-names = "dp"; 2165 2166 #sound-dai-cells = <0>; 2167 2168 operating-points-v2 = <&dp_opp_table>; 2169 power-domains = <&rpmhpd RPMHPD_MMCX>; 2170 2171 status = "disabled"; 2172 2173 ports { 2174 #address-cells = <1>; 2175 #size-cells = <0>; 2176 2177 port@0 { 2178 reg = <0>; 2179 2180 mdss_dp0_in: endpoint { 2181 remote-endpoint = <&dpu_intf0_out>; 2182 }; 2183 }; 2184 2185 port@1 { 2186 reg = <1>; 2187 2188 mdss_dp0_out: endpoint { 2189 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 2190 }; 2191 }; 2192 }; 2193 2194 dp_opp_table: opp-table { 2195 compatible = "operating-points-v2"; 2196 2197 opp-162000000 { 2198 opp-hz = /bits/ 64 <162000000>; 2199 required-opps = <&rpmhpd_opp_low_svs_d1>; 2200 }; 2201 2202 opp-270000000 { 2203 opp-hz = /bits/ 64 <270000000>; 2204 required-opps = <&rpmhpd_opp_low_svs>; 2205 }; 2206 2207 opp-540000000 { 2208 opp-hz = /bits/ 64 <540000000>; 2209 required-opps = <&rpmhpd_opp_svs_l1>; 2210 }; 2211 2212 opp-810000000 { 2213 opp-hz = /bits/ 64 <810000000>; 2214 required-opps = <&rpmhpd_opp_nom>; 2215 }; 2216 }; 2217 }; 2218 2219 mdss_dsi0: dsi@ae94000 { 2220 compatible = "qcom,sar2130p-dsi-ctrl", 2221 "qcom,mdss-dsi-ctrl"; 2222 reg = <0x0 0x0ae94000 0x0 0x400>; 2223 reg-names = "dsi_ctrl"; 2224 2225 interrupt-parent = <&mdss>; 2226 interrupts = <4>; 2227 2228 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2229 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2230 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2231 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2232 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2233 <&gcc GCC_DISP_HF_AXI_CLK>; 2234 clock-names = "byte", 2235 "byte_intf", 2236 "pixel", 2237 "core", 2238 "iface", 2239 "bus"; 2240 2241 power-domains = <&rpmhpd RPMHPD_MMCX>; 2242 2243 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2244 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2245 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2246 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2247 2248 operating-points-v2 = <&mdss_dsi_opp_table>; 2249 2250 phys = <&mdss_dsi0_phy>; 2251 phy-names = "dsi"; 2252 2253 #address-cells = <1>; 2254 #size-cells = <0>; 2255 2256 status = "disabled"; 2257 2258 ports { 2259 #address-cells = <1>; 2260 #size-cells = <0>; 2261 2262 port@0 { 2263 reg = <0>; 2264 mdss_dsi0_in: endpoint { 2265 remote-endpoint = <&dpu_intf1_out>; 2266 }; 2267 }; 2268 2269 port@1 { 2270 reg = <1>; 2271 mdss_dsi0_out: endpoint { 2272 }; 2273 }; 2274 }; 2275 2276 mdss_dsi_opp_table: opp-table { 2277 compatible = "operating-points-v2"; 2278 2279 opp-187500000 { 2280 opp-hz = /bits/ 64 <187500000>; 2281 required-opps = <&rpmhpd_opp_low_svs>; 2282 }; 2283 2284 opp-300000000 { 2285 opp-hz = /bits/ 64 <300000000>; 2286 required-opps = <&rpmhpd_opp_svs>; 2287 }; 2288 2289 opp-358000000 { 2290 opp-hz = /bits/ 64 <358000000>; 2291 required-opps = <&rpmhpd_opp_nom>; 2292 }; 2293 }; 2294 }; 2295 2296 mdss_dsi0_phy: phy@ae95000 { 2297 compatible = "qcom,sar2130p-dsi-phy-5nm"; 2298 reg = <0x0 0x0ae95000 0x0 0x200>, 2299 <0x0 0x0ae95200 0x0 0x280>, 2300 <0x0 0x0ae95500 0x0 0x400>; 2301 reg-names = "dsi_phy", 2302 "dsi_phy_lane", 2303 "dsi_pll"; 2304 2305 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2306 <&rpmhcc RPMH_CXO_CLK>; 2307 clock-names = "iface", "ref"; 2308 2309 #clock-cells = <1>; 2310 #phy-cells = <0>; 2311 2312 status = "disabled"; 2313 }; 2314 2315 mdss_dsi1: dsi@ae96000 { 2316 compatible = "qcom,sar2130p-dsi-ctrl", 2317 "qcom,mdss-dsi-ctrl"; 2318 reg = <0x0 0x0ae96000 0x0 0x400>; 2319 reg-names = "dsi_ctrl"; 2320 2321 interrupt-parent = <&mdss>; 2322 interrupts = <5>; 2323 2324 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2325 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2326 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2327 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2328 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2329 <&gcc GCC_DISP_HF_AXI_CLK>; 2330 clock-names = "byte", 2331 "byte_intf", 2332 "pixel", 2333 "core", 2334 "iface", 2335 "bus"; 2336 2337 power-domains = <&rpmhpd RPMHPD_MMCX>; 2338 2339 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2340 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2341 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 2342 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 2343 2344 operating-points-v2 = <&mdss_dsi_opp_table>; 2345 2346 phys = <&mdss_dsi1_phy>; 2347 phy-names = "dsi"; 2348 2349 #address-cells = <1>; 2350 #size-cells = <0>; 2351 2352 status = "disabled"; 2353 2354 ports { 2355 #address-cells = <1>; 2356 #size-cells = <0>; 2357 2358 port@0 { 2359 reg = <0>; 2360 mdss_dsi1_in: endpoint { 2361 remote-endpoint = <&dpu_intf2_out>; 2362 }; 2363 }; 2364 2365 port@1 { 2366 reg = <1>; 2367 mdss_dsi1_out: endpoint { 2368 }; 2369 }; 2370 }; 2371 }; 2372 2373 mdss_dsi1_phy: phy@ae97000 { 2374 compatible = "qcom,sar2130p-dsi-phy-5nm"; 2375 reg = <0x0 0x0ae97000 0x0 0x200>, 2376 <0x0 0x0ae97200 0x0 0x280>, 2377 <0x0 0x0ae97500 0x0 0x400>; 2378 reg-names = "dsi_phy", 2379 "dsi_phy_lane", 2380 "dsi_pll"; 2381 2382 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2383 <&rpmhcc RPMH_CXO_CLK>; 2384 clock-names = "iface", "ref"; 2385 2386 #clock-cells = <1>; 2387 #phy-cells = <0>; 2388 2389 status = "disabled"; 2390 }; 2391 }; 2392 2393 dispcc: clock-controller@af00000 { 2394 compatible = "qcom,sar2130p-dispcc"; 2395 reg = <0x0 0x0af00000 0x0 0x20000>; 2396 clocks = <&rpmhcc RPMH_CXO_CLK>, 2397 <&rpmhcc RPMH_CXO_CLK_A>, 2398 <&gcc GCC_DISP_AHB_CLK>, 2399 <&sleep_clk>, 2400 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2401 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2402 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 2403 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 2404 <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2405 <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2406 <0>, /* dp1 */ 2407 <0>, 2408 <0>, /* dp2 */ 2409 <0>, 2410 <0>, /* dp3 */ 2411 <0>; 2412 power-domains = <&rpmhpd RPMHPD_MMCX>; 2413 #clock-cells = <1>; 2414 #reset-cells = <1>; 2415 #power-domain-cells = <1>; 2416 }; 2417 2418 pdc: interrupt-controller@b220000 { 2419 compatible = "qcom,sar2130p-pdc", "qcom,pdc"; 2420 reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; 2421 qcom,pdc-ranges = <0 480 94>, 2422 <94 609 31>, 2423 <125 63 1>, 2424 <126 716 12>; 2425 #interrupt-cells = <2>; 2426 interrupt-parent = <&intc>; 2427 interrupt-controller; 2428 }; 2429 2430 aoss_qmp: power-management@c300000 { 2431 compatible = "qcom,sar2130p-aoss-qmp", "qcom,aoss-qmp"; 2432 reg = <0x0 0x0c300000 0x0 0x400>; 2433 interrupt-parent = <&ipcc>; 2434 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2435 IRQ_TYPE_EDGE_RISING>; 2436 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2437 2438 #clock-cells = <0>; 2439 }; 2440 2441 tsens0: thermal-sensor@c263000 { 2442 compatible = "qcom,sar2130p-tsens", "qcom,tsens-v2"; 2443 reg = <0x0 0x0c263000 0x0 0x1000>, /* TM */ 2444 <0x0 0x0c222000 0x0 0x1000>; /* SROT */ 2445 #qcom,sensors = <16>; 2446 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2448 interrupt-names = "uplow", "critical"; 2449 #thermal-sensor-cells = <1>; 2450 }; 2451 2452 sram@c3f0000 { 2453 compatible = "qcom,rpmh-stats"; 2454 reg = <0x0 0x0c3f0000 0x0 0x400>; 2455 }; 2456 2457 arbiter@c400000 { 2458 compatible = "qcom,sar2130p-spmi-pmic-arb", 2459 "qcom,x1e80100-spmi-pmic-arb"; 2460 reg = <0x0 0x0c400000 0x0 0x3000>, 2461 <0x0 0x0c500000 0x0 0x400000>, 2462 <0x0 0x0c440000 0x0 0x80000>; 2463 reg-names = "core", "chnls", "obsrvr"; 2464 2465 qcom,ee = <0>; 2466 qcom,channel = <0>; 2467 2468 #address-cells = <2>; 2469 #size-cells = <2>; 2470 ranges; 2471 2472 spmi_bus: spmi@c42d000 { 2473 reg = <0x0 0x0c42d000 0x0 0x4000>, 2474 <0x0 0x0c4c0000 0x0 0x10000>; 2475 reg-names = "cnfg", "intr"; 2476 2477 interrupt-names = "periph_irq"; 2478 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2479 interrupt-controller; 2480 #interrupt-cells = <4>; 2481 2482 #address-cells = <2>; 2483 #size-cells = <0>; 2484 }; 2485 }; 2486 2487 ipcc: mailbox@ed18000 { 2488 compatible = "qcom,sar2130p-ipcc", "qcom,ipcc"; 2489 reg = <0x0 0x0ed18000 0x0 0x1000>; 2490 2491 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 2492 interrupt-controller; 2493 #interrupt-cells = <3>; 2494 2495 #mbox-cells = <2>; 2496 }; 2497 2498 tlmm: pinctrl@f100000 { 2499 compatible = "qcom,sar2130p-tlmm"; 2500 reg = <0x0 0x0f100000 0x0 0x300000>; 2501 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2502 gpio-controller; 2503 #gpio-cells = <2>; 2504 interrupt-controller; 2505 #interrupt-cells = <2>; 2506 gpio-ranges = <&tlmm 0 0 156>; 2507 wakeup-parent = <&pdc>; 2508 2509 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2510 /* SDA, SCL */ 2511 pins = "gpio0", "gpio1"; 2512 function = "qup0"; 2513 drive-strength = <2>; 2514 bias-pull-up; 2515 }; 2516 2517 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2518 /* SDA, SCL */ 2519 pins = "gpio2", "gpio3"; 2520 function = "qup1"; 2521 drive-strength = <2>; 2522 bias-pull-up; 2523 }; 2524 2525 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2526 /* SDA, SCL */ 2527 pins = "gpio22", "gpio23"; 2528 function = "qup2"; 2529 drive-strength = <2>; 2530 bias-pull-up; 2531 }; 2532 2533 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2534 /* SDA, SCL */ 2535 pins = "gpio16", "gpio17"; 2536 function = "qup3"; 2537 drive-strength = <2>; 2538 bias-pull-up; 2539 }; 2540 2541 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2542 /* SDA, SCL */ 2543 pins = "gpio20", "gpio21"; 2544 function = "qup4"; 2545 drive-strength = <2>; 2546 bias-pull-up; 2547 }; 2548 2549 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 2550 /* SDA, SCL */ 2551 pins = "gpio95", "gpio96"; 2552 function = "qup5"; 2553 drive-strength = <2>; 2554 bias-pull-up; 2555 }; 2556 2557 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 2558 /* SDA, SCL */ 2559 pins = "gpio91", "gpio92"; 2560 function = "qup6"; 2561 drive-strength = <2>; 2562 bias-pull-up; 2563 }; 2564 2565 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 2566 /* SDA, SCL */ 2567 pins = "gpio8", "gpio9"; 2568 function = "qup7"; 2569 drive-strength = <2>; 2570 bias-pull-up; 2571 }; 2572 2573 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 2574 /* SDA, SCL */ 2575 pins = "gpio8", "gpio9"; 2576 function = "qup8"; 2577 drive-strength = <2>; 2578 bias-pull-up; 2579 }; 2580 2581 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 2582 /* SDA, SCL */ 2583 pins = "gpio109", "gpio110"; 2584 function = "qup9"; 2585 drive-strength = <2>; 2586 bias-pull-up; 2587 }; 2588 2589 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 2590 /* SDA, SCL */ 2591 pins = "gpio4", "gpio5"; 2592 function = "qup10"; 2593 drive-strength = <2>; 2594 bias-pull-up; 2595 }; 2596 2597 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 2598 /* SDA, SCL */ 2599 pins = "gpio28", "gpio30"; 2600 function = "qup11"; 2601 drive-strength = <2>; 2602 bias-pull-up; 2603 }; 2604 2605 qup_spi0_cs0: qup-spi0-cs0-state { 2606 pins = "gpio3"; 2607 function = "qup0"; 2608 drive-strength = <2>; 2609 bias-disable; 2610 }; 2611 2612 qup_spi0_cs1: qup-spi0-cs1-state { 2613 pins = "gpio93"; 2614 function = "qup0"; 2615 drive-strength = <2>; 2616 bias-disable; 2617 }; 2618 2619 qup_spi0_data_clk: qup-spi0-data-clk-state { 2620 /* MISO, MOSI, CLK */ 2621 pins = "gpio0", "gpio1", "gpio2"; 2622 function = "qup0"; 2623 drive-strength = <2>; 2624 bias-disable; 2625 }; 2626 2627 qup_spi1_cs: qup-spi1-cs-state { 2628 pins = "gpio62"; 2629 function = "qup1"; 2630 drive-strength = <2>; 2631 bias-disable; 2632 }; 2633 2634 qup_spi1_data_clk: qup-spi1-data-clk-state { 2635 /* MISO, MOSI, CLK */ 2636 pins = "gpio2", "gpio3", "gpio61"; 2637 function = "qup1"; 2638 drive-strength = <2>; 2639 bias-disable; 2640 }; 2641 2642 qup_spi2_cs: qup-spi2-cs-state { 2643 pins = "gpio13"; 2644 function = "qup2"; 2645 drive-strength = <2>; 2646 bias-disable; 2647 }; 2648 2649 qup_spi2_data_clk: qup-spi2-data-clk-state { 2650 /* MISO, MOSI, CLK */ 2651 pins = "gpio22", "gpio23", "gpio12"; 2652 function = "qup2"; 2653 drive-strength = <2>; 2654 bias-disable; 2655 }; 2656 2657 qup_spi3_cs0: qup-spi3-cs0-state { 2658 pins = "gpio19"; 2659 function = "qup3"; 2660 drive-strength = <2>; 2661 bias-disable; 2662 }; 2663 2664 qup_spi3_cs1: qup-spi3-cs1-state { 2665 pins = "gpio41"; 2666 function = "qup3"; 2667 drive-strength = <2>; 2668 bias-disable; 2669 }; 2670 2671 qup_spi3_data_clk: qup-spi3-data-clk-state { 2672 /* MISO, MOSI, CLK */ 2673 pins = "gpio16", "gpio17", "gpio18"; 2674 function = "qup3"; 2675 drive-strength = <2>; 2676 bias-disable; 2677 }; 2678 2679 qup_spi4_cs0: qup-spi4-cs0-state { 2680 pins = "gpio23"; 2681 function = "qup4"; 2682 drive-strength = <2>; 2683 bias-disable; 2684 }; 2685 2686 qup_spi4_cs1: qup-spi4-cs1-state { 2687 pins = "gpio94"; 2688 function = "qup4"; 2689 drive-strength = <2>; 2690 bias-disable; 2691 }; 2692 2693 qup_spi4_data_clk: qup-spi4-data-clk-state { 2694 /* MISO, MOSI, CLK */ 2695 pins = "gpio20", "gpio21", "gpio22"; 2696 function = "qup4"; 2697 drive-strength = <2>; 2698 bias-disable; 2699 }; 2700 2701 qup_spi5_cs: qup-spi5-cs-state { 2702 pins = "gpio98"; 2703 function = "qup5"; 2704 drive-strength = <2>; 2705 bias-disable; 2706 }; 2707 2708 qup_spi5_data_clk: qup-spi5-data-clk-state { 2709 /* MISO, MOSI, CLK */ 2710 pins = "gpio95", "gpio96", "gpio97"; 2711 function = "qup5"; 2712 drive-strength = <2>; 2713 bias-disable; 2714 }; 2715 2716 qup_spi6_cs: qup-spi6-cs-state { 2717 pins = "gpio63"; 2718 function = "qup6"; 2719 drive-strength = <2>; 2720 bias-disable; 2721 }; 2722 2723 qup_spi6_data_clk: qup-spi6-data-clk-state { 2724 /* MISO, MOSI, CLK */ 2725 pins = "gpio91", "gpio92", "gpio64"; 2726 function = "qup6"; 2727 drive-strength = <2>; 2728 bias-disable; 2729 }; 2730 2731 qup_spi7_cs: qup-spi7-cs-state { 2732 pins = "gpio27"; 2733 function = "qup7"; 2734 drive-strength = <2>; 2735 bias-disable; 2736 }; 2737 2738 qup_spi7_data_clk: qup-spi7-data-clk-state { 2739 /* MISO, MOSI, CLK */ 2740 pins = "gpio24", "gpio25", "gpio26"; 2741 function = "qup7"; 2742 drive-strength = <2>; 2743 bias-disable; 2744 }; 2745 2746 qup_spi8_cs: qup-spi8-cs-state { 2747 pins = "gpio11"; 2748 function = "qup8"; 2749 drive-strength = <2>; 2750 bias-disable; 2751 }; 2752 2753 qup_spi8_data_clk: qup-spi8-data-clk-state { 2754 /* MISO, MOSI, CLK */ 2755 pins = "gpio8", "gpio9", "gpio10"; 2756 function = "qup8"; 2757 drive-strength = <2>; 2758 bias-disable; 2759 }; 2760 2761 qup_spi9_cs: qup-spi9-cs-state { 2762 pins = "gpio35"; 2763 function = "qup9"; 2764 drive-strength = <2>; 2765 bias-disable; 2766 }; 2767 2768 qup_spi9_data_clk: qup-spi9-data-clk-state { 2769 /* MISO, MOSI, CLK */ 2770 pins = "gpio109", "gpio110", "gpio34"; 2771 function = "qup9"; 2772 drive-strength = <2>; 2773 bias-disable; 2774 }; 2775 2776 qup_spi10_cs: qup-spi10-cs-state { 2777 pins = "gpio7"; 2778 function = "qup10"; 2779 drive-strength = <2>; 2780 bias-disable; 2781 }; 2782 2783 qup_spi10_data_clk: qup-spi10-data-clk-state { 2784 /* MISO, MOSI, CLK */ 2785 pins = "gpio4", "gpio5", "gpio6"; 2786 function = "qup10"; 2787 drive-strength = <2>; 2788 bias-disable; 2789 }; 2790 2791 qup_spi11_cs: qup-spi11-cs-state { 2792 pins = "gpio15"; 2793 function = "qup11"; 2794 drive-strength = <2>; 2795 bias-disable; 2796 }; 2797 2798 qup_spi11_data_clk: qup-spi11-data-clk-state { 2799 /* MISO, MOSI, CLK */ 2800 pins = "gpio28", "gpio30", "gpio14"; 2801 function = "qup11"; 2802 drive-strength = <2>; 2803 bias-disable; 2804 }; 2805 2806 qup_uart7_default: qup-uart7-default-state { 2807 cts-pins { 2808 pins = "gpio24"; 2809 function = "qup7"; 2810 drive-strength = <2>; 2811 bias-disable; 2812 }; 2813 2814 rts-pins { 2815 pins = "gpio25"; 2816 function = "qup7"; 2817 drive-strength = <2>; 2818 bias-pull-down; 2819 }; 2820 2821 rx-pins { 2822 pins = "gpio27"; 2823 function = "qup7"; 2824 drive-strength = <2>; 2825 bias-pull-down; 2826 }; 2827 2828 tx-pins { 2829 pins = "gpio26"; 2830 function = "qup7"; 2831 drive-strength = <2>; 2832 bias-pull-up; 2833 }; 2834 }; 2835 2836 qup_uart11_default: qup-uart11-default-state { 2837 pins = "gpio14", "gpio15"; 2838 function = "qup11"; 2839 drive-strength = <2>; 2840 bias-disable; 2841 }; 2842 2843 sdc1_default: sdc1-default-state { 2844 clk-pins { 2845 pins = "sdc1_clk"; 2846 drive-strength = <16>; 2847 bias-disable; 2848 }; 2849 2850 cmd-pins { 2851 pins = "sdc1_cmd"; 2852 drive-strength = <10>; 2853 bias-pull-up; 2854 }; 2855 2856 data-pins { 2857 pins = "sdc1_data"; 2858 drive-strength = <10>; 2859 bias-pull-up; 2860 }; 2861 2862 rclk-pins { 2863 pins = "sdc1_rclk"; 2864 bias-pull-down; 2865 }; 2866 }; 2867 2868 sdc1_sleep: sdc1-sleep-state { 2869 clk-pins { 2870 pins = "sdc1_clk"; 2871 drive-strength = <2>; 2872 bias-disable; 2873 }; 2874 2875 cmd-pins { 2876 pins = "sdc1_cmd"; 2877 drive-strength = <2>; 2878 bias-pull-up; 2879 }; 2880 2881 data-pins { 2882 pins = "sdc1_data"; 2883 drive-strength = <2>; 2884 bias-pull-up; 2885 }; 2886 2887 rclk-pins { 2888 pins = "sdc1_rclk"; 2889 bias-pull-down; 2890 }; 2891 }; 2892 }; 2893 2894 apps_smmu: iommu@15000000 { 2895 compatible = "qcom,sar2130p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2896 reg = <0x0 0x15000000 0x0 0x100000>; 2897 #iommu-cells = <2>; 2898 #global-interrupts = <1>; 2899 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2900 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2901 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2902 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2903 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2904 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2905 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2906 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2907 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2908 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2909 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2910 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2911 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2912 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2913 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2914 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2915 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2916 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2917 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2918 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2919 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2920 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2921 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2922 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2923 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2924 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2925 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2926 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2927 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2928 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2929 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2930 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2931 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2932 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2933 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2934 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2935 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2936 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2937 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2938 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2939 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2940 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2941 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2942 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2943 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2944 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2945 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2946 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2947 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2948 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2949 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2950 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2951 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2952 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2953 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2954 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2955 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2956 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2957 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2958 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2959 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2960 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2961 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2962 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2963 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2964 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2965 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2966 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2967 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2968 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2969 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2970 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2971 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2972 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2973 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2974 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2975 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2976 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2977 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2978 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2979 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2980 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2981 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2982 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2983 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2984 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 2985 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2986 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2987 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 2988 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 2989 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 2990 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 2991 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 2992 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 2993 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 2994 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 2995 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 2996 dma-coherent; 2997 }; 2998 2999 intc: interrupt-controller@17200000 { 3000 compatible = "arm,gic-v3"; 3001 #interrupt-cells = <3>; 3002 interrupt-controller; 3003 #redistributor-regions = <1>; 3004 redistributor-stride = <0x0 0x20000>; 3005 reg = <0x0 0x17200000 0x0 0x10000>, 3006 <0x0 0x17260000 0x0 0x100000>; 3007 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3008 #address-cells = <2>; 3009 #size-cells = <2>; 3010 ranges; 3011 3012 gic_its: msi-controller@17240000 { 3013 compatible = "arm,gic-v3-its"; 3014 reg = <0x0 0x17240000 0x0 0x20000>; 3015 msi-controller; 3016 #msi-cells = <1>; 3017 }; 3018 }; 3019 3020 apps_rsc: rsc@17a00000 { 3021 label = "apps_rsc"; 3022 compatible = "qcom,rpmh-rsc"; 3023 reg = <0x0 0x17a00000 0x0 0x10000>, 3024 <0x0 0x17a10000 0x0 0x10000>, 3025 <0x0 0x17a20000 0x0 0x10000>; 3026 reg-names = "drv-0", "drv-1", "drv-2"; 3027 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3028 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3029 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3030 qcom,tcs-offset = <0xd00>; 3031 qcom,drv-id = <2>; 3032 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3033 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3034 power-domains = <&cluster_pd>; 3035 3036 apps_bcm_voter: bcm-voter { 3037 compatible = "qcom,bcm-voter"; 3038 }; 3039 3040 rpmhcc: clock-controller { 3041 compatible = "qcom,sar2130p-rpmh-clk"; 3042 #clock-cells = <1>; 3043 clock-names = "xo"; 3044 clocks = <&xo_board>; 3045 }; 3046 3047 rpmhpd: power-controller { 3048 compatible = "qcom,sar2130p-rpmhpd"; 3049 #power-domain-cells = <1>; 3050 operating-points-v2 = <&rpmhpd_opp_table>; 3051 3052 rpmhpd_opp_table: opp-table { 3053 compatible = "operating-points-v2"; 3054 3055 rpmhpd_opp_ret: opp1 { 3056 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3057 }; 3058 3059 rpmhpd_opp_min_svs: opp2 { 3060 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3061 }; 3062 3063 rpmhpd_opp_low_svs_d1: opp3 { 3064 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3065 }; 3066 3067 rpmhpd_opp_low_svs: opp4 { 3068 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3069 }; 3070 3071 rpmhpd_opp_svs: opp5 { 3072 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3073 }; 3074 3075 rpmhpd_opp_svs_l1: opp6 { 3076 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3077 }; 3078 3079 rpmhpd_opp_nom: opp7 { 3080 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3081 }; 3082 3083 rpmhpd_opp_turbo: opp8 { 3084 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3085 }; 3086 3087 rpmhpd_opp_turbo_l1: opp9 { 3088 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3089 }; 3090 }; 3091 }; 3092 }; 3093 3094 cpufreq_hw: cpufreq@17d91000 { 3095 compatible = "qcom,sar2130p-cpufreq-epss", "qcom,cpufreq-epss"; 3096 reg = <0x0 0x17d91000 0x0 0x1000>; 3097 reg-names = "freq-domain0"; 3098 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3099 clock-names = "xo", "alternate"; 3100 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3101 interrupt-names = "dcvsh-irq-0"; 3102 #freq-domain-cells = <1>; 3103 #clock-cells = <1>; 3104 }; 3105 3106 gem_noc: interconnect@19100000 { 3107 compatible = "qcom,sar2130p-gem-noc"; 3108 reg = <0x0 0x19100000 0x0 0xa2080>; 3109 #interconnect-cells = <2>; 3110 qcom,bcm-voters = <&apps_bcm_voter>; 3111 }; 3112 3113 /* 3114 * Bootloader expects just cache-controller node instead of 3115 * the typical system-cache-controller 3116 */ 3117 llcc: cache-controller@19200000 { 3118 compatible = "qcom,sar2130p-llcc"; 3119 reg = <0x0 0x19200000 0x0 0x80000>, 3120 <0x0 0x19300000 0x0 0x80000>, 3121 <0x0 0x19a00000 0x0 0x80000>, 3122 <0x0 0x19c00000 0x0 0x80000>, 3123 <0x0 0x19af0000 0x0 0x80000>, 3124 <0x0 0x19cf0000 0x0 0x80000>; 3125 reg-names = "llcc0_base", 3126 "llcc1_base", 3127 "llcc_broadcast_base", 3128 "llcc_broadcast_and_base", 3129 "llcc_scratchpad_broadcast_base", 3130 "llcc_scratchpad_broadcast_and_base"; 3131 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 3132 }; 3133 3134 qfprom: qfprom@221c8000 { 3135 compatible = "qcom,sar2130p-qfprom", "qcom,qfprom"; 3136 reg = <0x0 0x221c8000 0x0 0x1000>; 3137 #address-cells = <1>; 3138 #size-cells = <1>; 3139 read-only; 3140 3141 gpu_speed_bin: gpu-speed-bin@119 { 3142 reg = <0x119 0x2>; 3143 bits = <5 8>; 3144 }; 3145 }; 3146 3147 nsp_noc: interconnect@320c0000 { 3148 compatible = "qcom,sar2130p-nsp-noc"; 3149 reg = <0x0 0x320c0000 0x0 0x10>; 3150 #interconnect-cells = <2>; 3151 qcom,bcm-voters = <&apps_bcm_voter>; 3152 }; 3153 3154 lpass_ag_noc: interconnect@3c40000 { 3155 compatible = "qcom,sar2130p-lpass-ag-noc"; 3156 reg = <0x0 0x3c40000 0x0 0x10>; 3157 #interconnect-cells = <1>; 3158 qcom,bcm-voters = <&apps_bcm_voter>; 3159 }; 3160 }; 3161 3162 timer { 3163 compatible = "arm,armv8-timer"; 3164 3165 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3166 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3167 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3168 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3169 }; 3170 3171 thermal-zones { 3172 aoss0-thermal { 3173 thermal-sensors = <&tsens0 0>; 3174 3175 trips { 3176 trip-point0 { 3177 temperature = <115000>; 3178 hysteresis = <5000>; 3179 type = "hot"; 3180 }; 3181 3182 aoss0-critical { 3183 temperature = <125000>; 3184 hysteresis = <0>; 3185 type = "critical"; 3186 }; 3187 3188 }; 3189 }; 3190 3191 cpu0-thermal { 3192 thermal-sensors = <&tsens0 1>; 3193 3194 trips { 3195 cpu0_alert0: trip-point0 { 3196 temperature = <110000>; 3197 hysteresis = <10000>; 3198 type = "passive"; 3199 }; 3200 3201 cpu0_alert1: trip-point1 { 3202 temperature = <115000>; 3203 hysteresis = <5000>; 3204 type = "passive"; 3205 }; 3206 3207 cpu0-critical { 3208 temperature = <125000>; 3209 hysteresis = <1000>; 3210 type = "critical"; 3211 }; 3212 }; 3213 3214 cooling-maps { 3215 map0 { 3216 trip = <&cpu0_alert0>; 3217 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3218 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3219 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3220 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3221 }; 3222 3223 map1 { 3224 trip = <&cpu0_alert1>; 3225 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3226 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3227 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3228 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3229 }; 3230 }; 3231 }; 3232 3233 cpu1-thermal { 3234 thermal-sensors = <&tsens0 2>; 3235 3236 trips { 3237 cpu1_alert0: trip-point0 { 3238 temperature = <110000>; 3239 hysteresis = <10000>; 3240 type = "passive"; 3241 }; 3242 3243 cpu1_alert1: trip-point1 { 3244 temperature = <115000>; 3245 hysteresis = <5000>; 3246 type = "passive"; 3247 }; 3248 3249 cpu1-critical { 3250 temperature = <125000>; 3251 hysteresis = <1000>; 3252 type = "critical"; 3253 }; 3254 }; 3255 3256 cooling-maps { 3257 map0 { 3258 trip = <&cpu1_alert0>; 3259 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3260 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3261 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3262 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3263 }; 3264 3265 map1 { 3266 trip = <&cpu1_alert1>; 3267 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3268 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3269 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3270 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3271 }; 3272 }; 3273 }; 3274 3275 cpu2-thermal { 3276 thermal-sensors = <&tsens0 3>; 3277 3278 trips { 3279 cpu2_alert0: trip-point0 { 3280 temperature = <110000>; 3281 hysteresis = <10000>; 3282 type = "passive"; 3283 }; 3284 3285 cpu2_alert1: trip-point1 { 3286 temperature = <115000>; 3287 hysteresis = <5000>; 3288 type = "passive"; 3289 }; 3290 3291 cpu2-critical { 3292 temperature = <125000>; 3293 hysteresis = <1000>; 3294 type = "critical"; 3295 }; 3296 }; 3297 3298 cooling-maps { 3299 map0 { 3300 trip = <&cpu2_alert0>; 3301 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3302 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3303 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3304 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3305 }; 3306 3307 map1 { 3308 trip = <&cpu2_alert1>; 3309 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3310 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3311 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3312 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3313 }; 3314 }; 3315 }; 3316 3317 cpu3-thermal { 3318 thermal-sensors = <&tsens0 4>; 3319 3320 trips { 3321 cpu3_alert0: trip-point0 { 3322 temperature = <110000>; 3323 hysteresis = <10000>; 3324 type = "passive"; 3325 }; 3326 3327 cpu3_alert1: rip-point1 { 3328 temperature = <115000>; 3329 hysteresis = <5000>; 3330 type = "passive"; 3331 }; 3332 3333 cpu3-critical { 3334 temperature = <125000>; 3335 hysteresis = <1000>; 3336 type = "critical"; 3337 }; 3338 }; 3339 3340 cooling-maps { 3341 map0 { 3342 trip = <&cpu3_alert0>; 3343 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3344 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3345 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3346 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3347 }; 3348 3349 map1 { 3350 trip = <&cpu3_alert1>; 3351 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3352 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3353 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3354 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3355 }; 3356 }; 3357 }; 3358 3359 gpuss0-thermal { 3360 polling-delay-passive = <250>; 3361 3362 thermal-sensors = <&tsens0 5>; 3363 3364 cooling-maps { 3365 map0 { 3366 trip = <&gpu0_alert0>; 3367 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3368 }; 3369 }; 3370 3371 trips { 3372 gpu0_alert0: trip-point0 { 3373 temperature = <85000>; 3374 hysteresis = <1000>; 3375 type = "passive"; 3376 }; 3377 3378 trip-point1 { 3379 temperature = <90000>; 3380 hysteresis = <1000>; 3381 type = "hot"; 3382 }; 3383 3384 trip-point2 { 3385 temperature = <115000>; 3386 hysteresis = <1000>; 3387 type = "critical"; 3388 }; 3389 }; 3390 }; 3391 3392 gpuss1-thermal { 3393 polling-delay-passive = <250>; 3394 3395 thermal-sensors = <&tsens0 6>; 3396 3397 cooling-maps { 3398 map0 { 3399 trip = <&gpu1_alert0>; 3400 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3401 }; 3402 }; 3403 3404 trips { 3405 gpu1_alert0: trip-point0 { 3406 temperature = <85000>; 3407 hysteresis = <1000>; 3408 type = "passive"; 3409 }; 3410 3411 trip-point1 { 3412 temperature = <90000>; 3413 hysteresis = <1000>; 3414 type = "hot"; 3415 }; 3416 3417 trip-point2 { 3418 temperature = <115000>; 3419 hysteresis = <1000>; 3420 type = "critical"; 3421 }; 3422 }; 3423 }; 3424 3425 nspss0-thermal { 3426 thermal-sensors = <&tsens0 7>; 3427 3428 trips { 3429 trip-point0 { 3430 temperature = <95000>; 3431 hysteresis = <5000>; 3432 type = "hot"; 3433 }; 3434 3435 trip-point1 { 3436 temperature = <115000>; 3437 hysteresis = <5000>; 3438 type = "hot"; 3439 }; 3440 3441 nspss1-critical { 3442 temperature = <125000>; 3443 hysteresis = <1000>; 3444 type = "critical"; 3445 }; 3446 }; 3447 }; 3448 3449 nspss1-thermal { 3450 thermal-sensors = <&tsens0 8>; 3451 3452 trips { 3453 trip-point0 { 3454 temperature = <95000>; 3455 hysteresis = <5000>; 3456 type = "hot"; 3457 }; 3458 3459 trip-point1 { 3460 temperature = <115000>; 3461 hysteresis = <5000>; 3462 type = "hot"; 3463 }; 3464 3465 nspss2-critical { 3466 temperature = <125000>; 3467 hysteresis = <1000>; 3468 type = "critical"; 3469 }; 3470 }; 3471 }; 3472 3473 nspss2-thermal { 3474 thermal-sensors = <&tsens0 9>; 3475 3476 trips { 3477 trip-point0 { 3478 temperature = <95000>; 3479 hysteresis = <5000>; 3480 type = "hot"; 3481 }; 3482 3483 trip-point1 { 3484 temperature = <115000>; 3485 hysteresis = <5000>; 3486 type = "hot"; 3487 }; 3488 3489 nspss2-critical { 3490 temperature = <125000>; 3491 hysteresis = <1000>; 3492 type = "critical"; 3493 }; 3494 }; 3495 }; 3496 3497 video-thermal { 3498 thermal-sensors = <&tsens0 10>; 3499 3500 trips { 3501 trip-point0 { 3502 temperature = <115000>; 3503 hysteresis = <5000>; 3504 type = "hot"; 3505 }; 3506 3507 video-critical { 3508 temperature = <125000>; 3509 hysteresis = <0>; 3510 type = "critical"; 3511 }; 3512 }; 3513 }; 3514 3515 ddr-thermal { 3516 thermal-sensors = <&tsens0 11>; 3517 3518 trips { 3519 trip-point0 { 3520 temperature = <115000>; 3521 hysteresis = <5000>; 3522 type = "hot"; 3523 }; 3524 3525 ddr-critical { 3526 temperature = <125000>; 3527 hysteresis = <0>; 3528 type = "critical"; 3529 }; 3530 }; 3531 }; 3532 3533 camera0-thermal { 3534 thermal-sensors = <&tsens0 12>; 3535 3536 trips { 3537 trip-point0 { 3538 temperature = <115000>; 3539 hysteresis = <5000>; 3540 type = "hot"; 3541 }; 3542 3543 camera0-critical { 3544 temperature = <125000>; 3545 hysteresis = <0>; 3546 type = "critical"; 3547 }; 3548 }; 3549 }; 3550 3551 camera1-thermal { 3552 thermal-sensors = <&tsens0 13>; 3553 3554 trips { 3555 trip-point0 { 3556 temperature = <115000>; 3557 hysteresis = <5000>; 3558 type = "hot"; 3559 }; 3560 3561 camera1-critical { 3562 temperature = <125000>; 3563 hysteresis = <0>; 3564 type = "critical"; 3565 }; 3566 }; 3567 }; 3568 3569 mdmss-thermal { 3570 thermal-sensors = <&tsens0 14>; 3571 3572 trips { 3573 trip-point0 { 3574 temperature = <115000>; 3575 hysteresis = <5000>; 3576 type = "hot"; 3577 }; 3578 3579 mdmss-critical { 3580 temperature = <125000>; 3581 hysteresis = <0>; 3582 type = "critical"; 3583 }; 3584 }; 3585 }; 3586 }; 3587}; 3588