1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,icc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 10#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 11#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 12#include <dt-bindings/mailbox/qcom-ipcc.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 clocks { 23 xo_board_clk: xo-board-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "qcom,kryo"; 41 reg = <0x0 0x0>; 42 enable-method = "psci"; 43 qcom,freq-domain = <&cpufreq_hw 0>; 44 next-level-cache = <&L2_0>; 45 L2_0: l2-cache { 46 compatible = "cache"; 47 cache-level = <2>; 48 cache-unified; 49 next-level-cache = <&L3_0>; 50 L3_0: l3-cache { 51 compatible = "cache"; 52 cache-level = <3>; 53 cache-unified; 54 }; 55 }; 56 }; 57 58 CPU1: cpu@100 { 59 device_type = "cpu"; 60 compatible = "qcom,kryo"; 61 reg = <0x0 0x100>; 62 enable-method = "psci"; 63 qcom,freq-domain = <&cpufreq_hw 0>; 64 next-level-cache = <&L2_1>; 65 L2_1: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&L3_0>; 70 }; 71 }; 72 73 CPU2: cpu@200 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo"; 76 reg = <0x0 0x200>; 77 enable-method = "psci"; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 next-level-cache = <&L2_2>; 80 L2_2: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 next-level-cache = <&L3_0>; 85 }; 86 }; 87 88 CPU3: cpu@300 { 89 device_type = "cpu"; 90 compatible = "qcom,kryo"; 91 reg = <0x0 0x300>; 92 enable-method = "psci"; 93 qcom,freq-domain = <&cpufreq_hw 0>; 94 next-level-cache = <&L2_3>; 95 L2_3: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 next-level-cache = <&L3_0>; 100 }; 101 }; 102 103 CPU4: cpu@10000 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo"; 106 reg = <0x0 0x10000>; 107 enable-method = "psci"; 108 qcom,freq-domain = <&cpufreq_hw 1>; 109 next-level-cache = <&L2_4>; 110 L2_4: l2-cache { 111 compatible = "cache"; 112 cache-level = <2>; 113 cache-unified; 114 next-level-cache = <&L3_1>; 115 L3_1: l3-cache { 116 compatible = "cache"; 117 cache-level = <3>; 118 cache-unified; 119 }; 120 121 }; 122 }; 123 124 CPU5: cpu@10100 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo"; 127 reg = <0x0 0x10100>; 128 enable-method = "psci"; 129 qcom,freq-domain = <&cpufreq_hw 1>; 130 next-level-cache = <&L2_5>; 131 L2_5: l2-cache { 132 compatible = "cache"; 133 cache-level = <2>; 134 cache-unified; 135 next-level-cache = <&L3_1>; 136 }; 137 }; 138 139 CPU6: cpu@10200 { 140 device_type = "cpu"; 141 compatible = "qcom,kryo"; 142 reg = <0x0 0x10200>; 143 enable-method = "psci"; 144 qcom,freq-domain = <&cpufreq_hw 1>; 145 next-level-cache = <&L2_6>; 146 L2_6: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&L3_1>; 151 }; 152 }; 153 154 CPU7: cpu@10300 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo"; 157 reg = <0x0 0x10300>; 158 enable-method = "psci"; 159 qcom,freq-domain = <&cpufreq_hw 1>; 160 next-level-cache = <&L2_7>; 161 L2_7: l2-cache { 162 compatible = "cache"; 163 cache-level = <2>; 164 cache-unified; 165 next-level-cache = <&L3_1>; 166 }; 167 }; 168 169 cpu-map { 170 cluster0 { 171 core0 { 172 cpu = <&CPU0>; 173 }; 174 175 core1 { 176 cpu = <&CPU1>; 177 }; 178 179 core2 { 180 cpu = <&CPU2>; 181 }; 182 183 core3 { 184 cpu = <&CPU3>; 185 }; 186 }; 187 188 cluster1 { 189 core0 { 190 cpu = <&CPU4>; 191 }; 192 193 core1 { 194 cpu = <&CPU5>; 195 }; 196 197 core2 { 198 cpu = <&CPU6>; 199 }; 200 201 core3 { 202 cpu = <&CPU7>; 203 }; 204 }; 205 }; 206 }; 207 208 firmware { 209 scm { 210 compatible = "qcom,scm-sa8775p", "qcom,scm"; 211 }; 212 }; 213 214 aggre1_noc: interconnect-aggre1-noc { 215 compatible = "qcom,sa8775p-aggre1-noc"; 216 #interconnect-cells = <2>; 217 qcom,bcm-voters = <&apps_bcm_voter>; 218 }; 219 220 aggre2_noc: interconnect-aggre2-noc { 221 compatible = "qcom,sa8775p-aggre2-noc"; 222 #interconnect-cells = <2>; 223 qcom,bcm-voters = <&apps_bcm_voter>; 224 }; 225 226 clk_virt: interconnect-clk-virt { 227 compatible = "qcom,sa8775p-clk-virt"; 228 #interconnect-cells = <2>; 229 qcom,bcm-voters = <&apps_bcm_voter>; 230 }; 231 232 config_noc: interconnect-config-noc { 233 compatible = "qcom,sa8775p-config-noc"; 234 #interconnect-cells = <2>; 235 qcom,bcm-voters = <&apps_bcm_voter>; 236 }; 237 238 dc_noc: interconnect-dc-noc { 239 compatible = "qcom,sa8775p-dc-noc"; 240 #interconnect-cells = <2>; 241 qcom,bcm-voters = <&apps_bcm_voter>; 242 }; 243 244 gem_noc: interconnect-gem-noc { 245 compatible = "qcom,sa8775p-gem-noc"; 246 #interconnect-cells = <2>; 247 qcom,bcm-voters = <&apps_bcm_voter>; 248 }; 249 250 gpdsp_anoc: interconnect-gpdsp-anoc { 251 compatible = "qcom,sa8775p-gpdsp-anoc"; 252 #interconnect-cells = <2>; 253 qcom,bcm-voters = <&apps_bcm_voter>; 254 }; 255 256 lpass_ag_noc: interconnect-lpass-ag-noc { 257 compatible = "qcom,sa8775p-lpass-ag-noc"; 258 #interconnect-cells = <2>; 259 qcom,bcm-voters = <&apps_bcm_voter>; 260 }; 261 262 mc_virt: interconnect-mc-virt { 263 compatible = "qcom,sa8775p-mc-virt"; 264 #interconnect-cells = <2>; 265 qcom,bcm-voters = <&apps_bcm_voter>; 266 }; 267 268 mmss_noc: interconnect-mmss-noc { 269 compatible = "qcom,sa8775p-mmss-noc"; 270 #interconnect-cells = <2>; 271 qcom,bcm-voters = <&apps_bcm_voter>; 272 }; 273 274 nspa_noc: interconnect-nspa-noc { 275 compatible = "qcom,sa8775p-nspa-noc"; 276 #interconnect-cells = <2>; 277 qcom,bcm-voters = <&apps_bcm_voter>; 278 }; 279 280 nspb_noc: interconnect-nspb-noc { 281 compatible = "qcom,sa8775p-nspb-noc"; 282 #interconnect-cells = <2>; 283 qcom,bcm-voters = <&apps_bcm_voter>; 284 }; 285 286 pcie_anoc: interconnect-pcie-anoc { 287 compatible = "qcom,sa8775p-pcie-anoc"; 288 #interconnect-cells = <2>; 289 qcom,bcm-voters = <&apps_bcm_voter>; 290 }; 291 292 system_noc: interconnect-system-noc { 293 compatible = "qcom,sa8775p-system-noc"; 294 #interconnect-cells = <2>; 295 qcom,bcm-voters = <&apps_bcm_voter>; 296 }; 297 298 /* Will be updated by the bootloader. */ 299 memory@80000000 { 300 device_type = "memory"; 301 reg = <0x0 0x80000000 0x0 0x0>; 302 }; 303 304 qup_opp_table_100mhz: opp-table-qup100mhz { 305 compatible = "operating-points-v2"; 306 307 opp-100000000 { 308 opp-hz = /bits/ 64 <100000000>; 309 required-opps = <&rpmhpd_opp_svs_l1>; 310 }; 311 }; 312 313 pmu { 314 compatible = "arm,armv8-pmuv3"; 315 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 316 }; 317 318 psci { 319 compatible = "arm,psci-1.0"; 320 method = "smc"; 321 }; 322 323 reserved-memory { 324 #address-cells = <2>; 325 #size-cells = <2>; 326 ranges; 327 328 sail_ss_mem: sail-ss@80000000 { 329 reg = <0x0 0x80000000 0x0 0x10000000>; 330 no-map; 331 }; 332 333 hyp_mem: hyp@90000000 { 334 reg = <0x0 0x90000000 0x0 0x600000>; 335 no-map; 336 }; 337 338 xbl_boot_mem: xbl-boot@90600000 { 339 reg = <0x0 0x90600000 0x0 0x200000>; 340 no-map; 341 }; 342 343 aop_image_mem: aop-image@90800000 { 344 reg = <0x0 0x90800000 0x0 0x60000>; 345 no-map; 346 }; 347 348 aop_cmd_db_mem: aop-cmd-db@90860000 { 349 compatible = "qcom,cmd-db"; 350 reg = <0x0 0x90860000 0x0 0x20000>; 351 no-map; 352 }; 353 354 uefi_log: uefi-log@908b0000 { 355 reg = <0x0 0x908b0000 0x0 0x10000>; 356 no-map; 357 }; 358 359 ddr_training_checksum: ddr-training-checksum@908c0000 { 360 reg = <0x0 0x908c0000 0x0 0x1000>; 361 no-map; 362 }; 363 364 reserved_mem: reserved@908f0000 { 365 reg = <0x0 0x908f0000 0x0 0xe000>; 366 no-map; 367 }; 368 369 secdata_apss_mem: secdata-apss@908fe000 { 370 reg = <0x0 0x908fe000 0x0 0x2000>; 371 no-map; 372 }; 373 374 smem_mem: smem@90900000 { 375 compatible = "qcom,smem"; 376 reg = <0x0 0x90900000 0x0 0x200000>; 377 no-map; 378 hwlocks = <&tcsr_mutex 3>; 379 }; 380 381 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { 382 reg = <0x0 0x90c00000 0x0 0x100000>; 383 no-map; 384 }; 385 386 sail_mailbox_mem: sail-ss@90d00000 { 387 reg = <0x0 0x90d00000 0x0 0x100000>; 388 no-map; 389 }; 390 391 sail_ota_mem: sail-ss@90e00000 { 392 reg = <0x0 0x90e00000 0x0 0x300000>; 393 no-map; 394 }; 395 396 aoss_backup_mem: aoss-backup@91b00000 { 397 reg = <0x0 0x91b00000 0x0 0x40000>; 398 no-map; 399 }; 400 401 cpucp_backup_mem: cpucp-backup@91b40000 { 402 reg = <0x0 0x91b40000 0x0 0x40000>; 403 no-map; 404 }; 405 406 tz_config_backup_mem: tz-config-backup@91b80000 { 407 reg = <0x0 0x91b80000 0x0 0x10000>; 408 no-map; 409 }; 410 411 ddr_training_data_mem: ddr-training-data@91b90000 { 412 reg = <0x0 0x91b90000 0x0 0x10000>; 413 no-map; 414 }; 415 416 cdt_data_backup_mem: cdt-data-backup@91ba0000 { 417 reg = <0x0 0x91ba0000 0x0 0x1000>; 418 no-map; 419 }; 420 421 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 422 reg = <0x0 0x93b00000 0x0 0xf00000>; 423 no-map; 424 }; 425 426 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 427 reg = <0x0 0x94a00000 0x0 0x800000>; 428 no-map; 429 }; 430 431 pil_camera_mem: pil-camera@95200000 { 432 reg = <0x0 0x95200000 0x0 0x500000>; 433 no-map; 434 }; 435 436 pil_adsp_mem: pil-adsp@95c00000 { 437 reg = <0x0 0x95c00000 0x0 0x1e00000>; 438 no-map; 439 }; 440 441 pil_gdsp0_mem: pil-gdsp0@97b00000 { 442 reg = <0x0 0x97b00000 0x0 0x1e00000>; 443 no-map; 444 }; 445 446 pil_gdsp1_mem: pil-gdsp1@99900000 { 447 reg = <0x0 0x99900000 0x0 0x1e00000>; 448 no-map; 449 }; 450 451 pil_cdsp0_mem: pil-cdsp0@9b800000 { 452 reg = <0x0 0x9b800000 0x0 0x1e00000>; 453 no-map; 454 }; 455 456 pil_gpu_mem: pil-gpu@9d600000 { 457 reg = <0x0 0x9d600000 0x0 0x2000>; 458 no-map; 459 }; 460 461 pil_cdsp1_mem: pil-cdsp1@9d700000 { 462 reg = <0x0 0x9d700000 0x0 0x1e00000>; 463 no-map; 464 }; 465 466 pil_cvp_mem: pil-cvp@9f500000 { 467 reg = <0x0 0x9f500000 0x0 0x700000>; 468 no-map; 469 }; 470 471 pil_video_mem: pil-video@9fc00000 { 472 reg = <0x0 0x9fc00000 0x0 0x700000>; 473 no-map; 474 }; 475 476 audio_mdf_mem: audio-mdf-region@ae000000 { 477 reg = <0x0 0xae000000 0x0 0x1000000>; 478 no-map; 479 }; 480 481 firmware_mem: firmware-region@b0000000 { 482 reg = <0x0 0xb0000000 0x0 0x800000>; 483 no-map; 484 }; 485 486 hyptz_reserved_mem: hyptz-reserved@beb00000 { 487 reg = <0x0 0xbeb00000 0x0 0x11500000>; 488 no-map; 489 }; 490 491 scmi_mem: scmi-region@d0000000 { 492 reg = <0x0 0xd0000000 0x0 0x40000>; 493 no-map; 494 }; 495 496 firmware_logs_mem: firmware-logs@d0040000 { 497 reg = <0x0 0xd0040000 0x0 0x10000>; 498 no-map; 499 }; 500 501 firmware_audio_mem: firmware-audio@d0050000 { 502 reg = <0x0 0xd0050000 0x0 0x4000>; 503 no-map; 504 }; 505 506 firmware_reserved_mem: firmware-reserved@d0054000 { 507 reg = <0x0 0xd0054000 0x0 0x9c000>; 508 no-map; 509 }; 510 511 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { 512 reg = <0x0 0xd00f0000 0x0 0x10000>; 513 no-map; 514 }; 515 516 tags_mem: tags@d0100000 { 517 reg = <0x0 0xd0100000 0x0 0x1200000>; 518 no-map; 519 }; 520 521 qtee_mem: qtee@d1300000 { 522 reg = <0x0 0xd1300000 0x0 0x500000>; 523 no-map; 524 }; 525 526 deepsleep_backup_mem: deepsleep-backup@d1800000 { 527 reg = <0x0 0xd1800000 0x0 0x100000>; 528 no-map; 529 }; 530 531 trusted_apps_mem: trusted-apps@d1900000 { 532 reg = <0x0 0xd1900000 0x0 0x3800000>; 533 no-map; 534 }; 535 536 tz_stat_mem: tz-stat@db100000 { 537 reg = <0x0 0xdb100000 0x0 0x100000>; 538 no-map; 539 }; 540 541 cpucp_fw_mem: cpucp-fw@db200000 { 542 reg = <0x0 0xdb200000 0x0 0x100000>; 543 no-map; 544 }; 545 }; 546 547 soc: soc@0 { 548 compatible = "simple-bus"; 549 #address-cells = <2>; 550 #size-cells = <2>; 551 ranges = <0 0 0 0 0x10 0>; 552 553 gcc: clock-controller@100000 { 554 compatible = "qcom,sa8775p-gcc"; 555 reg = <0x0 0x00100000 0x0 0xc7018>; 556 #clock-cells = <1>; 557 #reset-cells = <1>; 558 #power-domain-cells = <1>; 559 clocks = <&rpmhcc RPMH_CXO_CLK>, 560 <&sleep_clk>, 561 <0>, 562 <0>, 563 <0>, 564 <&usb_0_qmpphy>, 565 <&usb_1_qmpphy>, 566 <0>, 567 <0>, 568 <0>, 569 <&pcie0_phy>, 570 <&pcie1_phy>, 571 <0>, 572 <0>, 573 <0>; 574 power-domains = <&rpmhpd SA8775P_CX>; 575 }; 576 577 ipcc: mailbox@408000 { 578 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 579 reg = <0x0 0x00408000 0x0 0x1000>; 580 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 581 interrupt-controller; 582 #interrupt-cells = <3>; 583 #mbox-cells = <2>; 584 }; 585 586 qupv3_id_2: geniqup@8c0000 { 587 compatible = "qcom,geni-se-qup"; 588 reg = <0x0 0x008c0000 0x0 0x6000>; 589 ranges; 590 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 591 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 592 clock-names = "m-ahb", "s-ahb"; 593 iommus = <&apps_smmu 0x5a3 0x0>; 594 #address-cells = <2>; 595 #size-cells = <2>; 596 status = "disabled"; 597 598 i2c14: i2c@880000 { 599 compatible = "qcom,geni-i2c"; 600 reg = <0x0 0x880000 0x0 0x4000>; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 605 clock-names = "se"; 606 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 607 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 608 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 609 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 610 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 611 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 612 interconnect-names = "qup-core", 613 "qup-config", 614 "qup-memory"; 615 power-domains = <&rpmhpd SA8775P_CX>; 616 status = "disabled"; 617 }; 618 619 spi14: spi@880000 { 620 compatible = "qcom,geni-spi"; 621 reg = <0x0 0x880000 0x0 0x4000>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 626 clock-names = "se"; 627 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 628 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 629 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 630 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 631 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 632 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 633 interconnect-names = "qup-core", 634 "qup-config", 635 "qup-memory"; 636 power-domains = <&rpmhpd SA8775P_CX>; 637 status = "disabled"; 638 }; 639 640 i2c15: i2c@884000 { 641 compatible = "qcom,geni-i2c"; 642 reg = <0x0 0x884000 0x0 0x4000>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 647 clock-names = "se"; 648 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 649 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 650 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 651 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 652 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 653 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 654 interconnect-names = "qup-core", 655 "qup-config", 656 "qup-memory"; 657 power-domains = <&rpmhpd SA8775P_CX>; 658 status = "disabled"; 659 }; 660 661 spi15: spi@884000 { 662 compatible = "qcom,geni-spi"; 663 reg = <0x0 0x884000 0x0 0x4000>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 667 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 668 clock-names = "se"; 669 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 670 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 671 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 672 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 673 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 674 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 675 interconnect-names = "qup-core", 676 "qup-config", 677 "qup-memory"; 678 power-domains = <&rpmhpd SA8775P_CX>; 679 status = "disabled"; 680 }; 681 682 i2c16: i2c@888000 { 683 compatible = "qcom,geni-i2c"; 684 reg = <0x0 0x888000 0x0 0x4000>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 689 clock-names = "se"; 690 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 691 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 692 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 693 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 694 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 695 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 696 interconnect-names = "qup-core", 697 "qup-config", 698 "qup-memory"; 699 power-domains = <&rpmhpd SA8775P_CX>; 700 status = "disabled"; 701 }; 702 703 spi16: spi@888000 { 704 compatible = "qcom,geni-spi"; 705 reg = <0x0 0x00888000 0x0 0x4000>; 706 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 708 clock-names = "se"; 709 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 710 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 711 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 712 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 713 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 714 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 715 interconnect-names = "qup-core", 716 "qup-config", 717 "qup-memory"; 718 power-domains = <&rpmhpd SA8775P_CX>; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 status = "disabled"; 722 }; 723 724 i2c17: i2c@88c000 { 725 compatible = "qcom,geni-i2c"; 726 reg = <0x0 0x88c000 0x0 0x4000>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 731 clock-names = "se"; 732 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 733 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 734 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 735 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 736 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 737 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 738 interconnect-names = "qup-core", 739 "qup-config", 740 "qup-memory"; 741 power-domains = <&rpmhpd SA8775P_CX>; 742 status = "disabled"; 743 }; 744 745 spi17: spi@88c000 { 746 compatible = "qcom,geni-spi"; 747 reg = <0x0 0x88c000 0x0 0x4000>; 748 #address-cells = <1>; 749 #size-cells = <0>; 750 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 752 clock-names = "se"; 753 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 754 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 755 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 756 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 757 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 758 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 759 interconnect-names = "qup-core", 760 "qup-config", 761 "qup-memory"; 762 power-domains = <&rpmhpd SA8775P_CX>; 763 status = "disabled"; 764 }; 765 766 uart17: serial@88c000 { 767 compatible = "qcom,geni-uart"; 768 reg = <0x0 0x0088c000 0x0 0x4000>; 769 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 770 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 771 clock-names = "se"; 772 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 773 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 774 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 775 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 776 interconnect-names = "qup-core", "qup-config"; 777 power-domains = <&rpmhpd SA8775P_CX>; 778 status = "disabled"; 779 }; 780 781 i2c18: i2c@890000 { 782 compatible = "qcom,geni-i2c"; 783 reg = <0x0 0x00890000 0x0 0x4000>; 784 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 786 clock-names = "se"; 787 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 788 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 789 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 790 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 791 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 792 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 793 interconnect-names = "qup-core", 794 "qup-config", 795 "qup-memory"; 796 power-domains = <&rpmhpd SA8775P_CX>; 797 #address-cells = <1>; 798 #size-cells = <0>; 799 status = "disabled"; 800 }; 801 802 spi18: spi@890000 { 803 compatible = "qcom,geni-spi"; 804 reg = <0x0 0x890000 0x0 0x4000>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 808 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 809 clock-names = "se"; 810 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 811 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 812 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 813 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 814 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 815 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 816 interconnect-names = "qup-core", 817 "qup-config", 818 "qup-memory"; 819 power-domains = <&rpmhpd SA8775P_CX>; 820 status = "disabled"; 821 }; 822 823 i2c19: i2c@894000 { 824 compatible = "qcom,geni-i2c"; 825 reg = <0x0 0x894000 0x0 0x4000>; 826 #address-cells = <1>; 827 #size-cells = <0>; 828 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 830 clock-names = "se"; 831 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 832 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 833 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 834 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 835 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 836 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 837 interconnect-names = "qup-core", 838 "qup-config", 839 "qup-memory"; 840 power-domains = <&rpmhpd SA8775P_CX>; 841 status = "disabled"; 842 }; 843 844 spi19: spi@894000 { 845 compatible = "qcom,geni-spi"; 846 reg = <0x0 0x894000 0x0 0x4000>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 851 clock-names = "se"; 852 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 853 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 854 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 855 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 856 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 857 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 858 interconnect-names = "qup-core", 859 "qup-config", 860 "qup-memory"; 861 power-domains = <&rpmhpd SA8775P_CX>; 862 status = "disabled"; 863 }; 864 865 i2c20: i2c@898000 { 866 compatible = "qcom,geni-i2c"; 867 reg = <0x0 0x898000 0x0 0x4000>; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 872 clock-names = "se"; 873 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 874 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 875 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 876 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 877 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 878 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 879 interconnect-names = "qup-core", 880 "qup-config", 881 "qup-memory"; 882 power-domains = <&rpmhpd SA8775P_CX>; 883 status = "disabled"; 884 }; 885 886 spi20: spi@898000 { 887 compatible = "qcom,geni-spi"; 888 reg = <0x0 0x898000 0x0 0x4000>; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 893 clock-names = "se"; 894 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 895 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 896 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 897 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 898 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 899 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 900 interconnect-names = "qup-core", 901 "qup-config", 902 "qup-memory"; 903 power-domains = <&rpmhpd SA8775P_CX>; 904 status = "disabled"; 905 }; 906 }; 907 908 qupv3_id_0: geniqup@9c0000 { 909 compatible = "qcom,geni-se-qup"; 910 reg = <0x0 0x9c0000 0x0 0x6000>; 911 #address-cells = <2>; 912 #size-cells = <2>; 913 ranges; 914 clock-names = "m-ahb", "s-ahb"; 915 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 916 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 917 iommus = <&apps_smmu 0x403 0x0>; 918 status = "disabled"; 919 920 i2c0: i2c@980000 { 921 compatible = "qcom,geni-i2c"; 922 reg = <0x0 0x980000 0x0 0x4000>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 927 clock-names = "se"; 928 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 929 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 930 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 931 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 932 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 933 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 934 interconnect-names = "qup-core", 935 "qup-config", 936 "qup-memory"; 937 power-domains = <&rpmhpd SA8775P_CX>; 938 status = "disabled"; 939 }; 940 941 spi0: spi@980000 { 942 compatible = "qcom,geni-spi"; 943 reg = <0x0 0x980000 0x0 0x4000>; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 947 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 948 clock-names = "se"; 949 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 950 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 951 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 952 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 953 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 954 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 955 interconnect-names = "qup-core", 956 "qup-config", 957 "qup-memory"; 958 power-domains = <&rpmhpd SA8775P_CX>; 959 status = "disabled"; 960 }; 961 962 i2c1: i2c@984000 { 963 compatible = "qcom,geni-i2c"; 964 reg = <0x0 0x984000 0x0 0x4000>; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 969 clock-names = "se"; 970 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 971 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 972 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 973 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 974 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 975 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 976 interconnect-names = "qup-core", 977 "qup-config", 978 "qup-memory"; 979 power-domains = <&rpmhpd SA8775P_CX>; 980 status = "disabled"; 981 }; 982 983 spi1: spi@984000 { 984 compatible = "qcom,geni-spi"; 985 reg = <0x0 0x984000 0x0 0x4000>; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 990 clock-names = "se"; 991 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 992 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 993 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 994 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 995 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 996 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 997 interconnect-names = "qup-core", 998 "qup-config", 999 "qup-memory"; 1000 power-domains = <&rpmhpd SA8775P_CX>; 1001 status = "disabled"; 1002 }; 1003 1004 i2c2: i2c@988000 { 1005 compatible = "qcom,geni-i2c"; 1006 reg = <0x0 0x988000 0x0 0x4000>; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1011 clock-names = "se"; 1012 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1013 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1014 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1015 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1016 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1017 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1018 interconnect-names = "qup-core", 1019 "qup-config", 1020 "qup-memory"; 1021 power-domains = <&rpmhpd SA8775P_CX>; 1022 status = "disabled"; 1023 }; 1024 1025 spi2: spi@988000 { 1026 compatible = "qcom,geni-spi"; 1027 reg = <0x0 0x988000 0x0 0x4000>; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1032 clock-names = "se"; 1033 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1034 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1035 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1036 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1037 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1038 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1039 interconnect-names = "qup-core", 1040 "qup-config", 1041 "qup-memory"; 1042 power-domains = <&rpmhpd SA8775P_CX>; 1043 status = "disabled"; 1044 }; 1045 1046 i2c3: i2c@98c000 { 1047 compatible = "qcom,geni-i2c"; 1048 reg = <0x0 0x98c000 0x0 0x4000>; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1052 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1053 clock-names = "se"; 1054 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1055 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1056 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1057 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1058 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1059 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1060 interconnect-names = "qup-core", 1061 "qup-config", 1062 "qup-memory"; 1063 power-domains = <&rpmhpd SA8775P_CX>; 1064 status = "disabled"; 1065 }; 1066 1067 spi3: spi@98c000 { 1068 compatible = "qcom,geni-spi"; 1069 reg = <0x0 0x98c000 0x0 0x4000>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1074 clock-names = "se"; 1075 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1076 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1077 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1078 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1079 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1080 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1081 interconnect-names = "qup-core", 1082 "qup-config", 1083 "qup-memory"; 1084 power-domains = <&rpmhpd SA8775P_CX>; 1085 status = "disabled"; 1086 }; 1087 1088 i2c4: i2c@990000 { 1089 compatible = "qcom,geni-i2c"; 1090 reg = <0x0 0x990000 0x0 0x4000>; 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1095 clock-names = "se"; 1096 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1097 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1098 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1099 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1100 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1101 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1102 interconnect-names = "qup-core", 1103 "qup-config", 1104 "qup-memory"; 1105 power-domains = <&rpmhpd SA8775P_CX>; 1106 status = "disabled"; 1107 }; 1108 1109 spi4: spi@990000 { 1110 compatible = "qcom,geni-spi"; 1111 reg = <0x0 0x990000 0x0 0x4000>; 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1115 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1116 clock-names = "se"; 1117 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1118 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1119 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1120 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1121 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1122 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1123 interconnect-names = "qup-core", 1124 "qup-config", 1125 "qup-memory"; 1126 power-domains = <&rpmhpd SA8775P_CX>; 1127 status = "disabled"; 1128 }; 1129 1130 i2c5: i2c@994000 { 1131 compatible = "qcom,geni-i2c"; 1132 reg = <0x0 0x994000 0x0 0x4000>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1137 clock-names = "se"; 1138 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1139 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1140 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1141 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1142 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1143 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1144 interconnect-names = "qup-core", 1145 "qup-config", 1146 "qup-memory"; 1147 power-domains = <&rpmhpd SA8775P_CX>; 1148 status = "disabled"; 1149 }; 1150 1151 spi5: spi@994000 { 1152 compatible = "qcom,geni-spi"; 1153 reg = <0x0 0x994000 0x0 0x4000>; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1157 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1158 clock-names = "se"; 1159 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1160 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1161 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1162 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1163 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1164 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1165 interconnect-names = "qup-core", 1166 "qup-config", 1167 "qup-memory"; 1168 power-domains = <&rpmhpd SA8775P_CX>; 1169 status = "disabled"; 1170 }; 1171 1172 uart5: serial@994000 { 1173 compatible = "qcom,geni-uart"; 1174 reg = <0x0 0x994000 0x0 0x4000>; 1175 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1176 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1177 clock-names = "se"; 1178 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1179 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1180 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1181 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1182 interconnect-names = "qup-core", "qup-config"; 1183 power-domains = <&rpmhpd SA8775P_CX>; 1184 status = "disabled"; 1185 }; 1186 }; 1187 1188 qupv3_id_1: geniqup@ac0000 { 1189 compatible = "qcom,geni-se-qup"; 1190 reg = <0x0 0x00ac0000 0x0 0x6000>; 1191 #address-cells = <2>; 1192 #size-cells = <2>; 1193 ranges; 1194 clock-names = "m-ahb", "s-ahb"; 1195 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1196 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1197 iommus = <&apps_smmu 0x443 0x0>; 1198 status = "disabled"; 1199 1200 i2c7: i2c@a80000 { 1201 compatible = "qcom,geni-i2c"; 1202 reg = <0x0 0xa80000 0x0 0x4000>; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1207 clock-names = "se"; 1208 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1209 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1210 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1211 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1212 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1213 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1214 interconnect-names = "qup-core", 1215 "qup-config", 1216 "qup-memory"; 1217 power-domains = <&rpmhpd SA8775P_CX>; 1218 status = "disabled"; 1219 }; 1220 1221 spi7: spi@a80000 { 1222 compatible = "qcom,geni-spi"; 1223 reg = <0x0 0xa80000 0x0 0x4000>; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1227 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1228 clock-names = "se"; 1229 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1230 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1231 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1232 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1233 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1234 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1235 interconnect-names = "qup-core", 1236 "qup-config", 1237 "qup-memory"; 1238 power-domains = <&rpmhpd SA8775P_CX>; 1239 status = "disabled"; 1240 }; 1241 1242 i2c8: i2c@a84000 { 1243 compatible = "qcom,geni-i2c"; 1244 reg = <0x0 0xa84000 0x0 0x4000>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1248 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1249 clock-names = "se"; 1250 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1251 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1252 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1253 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1254 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1255 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1256 interconnect-names = "qup-core", 1257 "qup-config", 1258 "qup-memory"; 1259 power-domains = <&rpmhpd SA8775P_CX>; 1260 status = "disabled"; 1261 }; 1262 1263 spi8: spi@a84000 { 1264 compatible = "qcom,geni-spi"; 1265 reg = <0x0 0xa84000 0x0 0x4000>; 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1269 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1270 clock-names = "se"; 1271 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1272 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1273 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1274 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1275 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1276 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1277 interconnect-names = "qup-core", 1278 "qup-config", 1279 "qup-memory"; 1280 power-domains = <&rpmhpd SA8775P_CX>; 1281 status = "disabled"; 1282 }; 1283 1284 i2c9: i2c@a88000 { 1285 compatible = "qcom,geni-i2c"; 1286 reg = <0x0 0xa88000 0x0 0x4000>; 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1290 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1291 clock-names = "se"; 1292 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1293 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1294 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1295 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1296 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1297 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1298 interconnect-names = "qup-core", 1299 "qup-config", 1300 "qup-memory"; 1301 power-domains = <&rpmhpd SA8775P_CX>; 1302 status = "disabled"; 1303 }; 1304 1305 spi9: spi@a88000 { 1306 compatible = "qcom,geni-spi"; 1307 reg = <0x0 0xa88000 0x0 0x4000>; 1308 #address-cells = <1>; 1309 #size-cells = <0>; 1310 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1311 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1312 clock-names = "se"; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1314 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1315 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1316 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1317 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1318 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1319 interconnect-names = "qup-core", 1320 "qup-config", 1321 "qup-memory"; 1322 power-domains = <&rpmhpd SA8775P_CX>; 1323 status = "disabled"; 1324 }; 1325 1326 uart9: serial@a88000 { 1327 compatible = "qcom,geni-uart"; 1328 reg = <0x0 0xa88000 0x0 0x4000>; 1329 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1330 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1331 clock-names = "se"; 1332 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1333 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1334 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1335 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1336 interconnect-names = "qup-core", "qup-config"; 1337 power-domains = <&rpmhpd SA8775P_CX>; 1338 status = "disabled"; 1339 }; 1340 1341 i2c10: i2c@a8c000 { 1342 compatible = "qcom,geni-i2c"; 1343 reg = <0x0 0xa8c000 0x0 0x4000>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1347 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1348 clock-names = "se"; 1349 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1350 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1351 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1352 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1353 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1354 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1355 interconnect-names = "qup-core", 1356 "qup-config", 1357 "qup-memory"; 1358 power-domains = <&rpmhpd SA8775P_CX>; 1359 status = "disabled"; 1360 }; 1361 1362 spi10: spi@a8c000 { 1363 compatible = "qcom,geni-spi"; 1364 reg = <0x0 0xa8c000 0x0 0x4000>; 1365 #address-cells = <1>; 1366 #size-cells = <0>; 1367 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1368 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1369 clock-names = "se"; 1370 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1371 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1372 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1373 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1374 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1375 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1376 interconnect-names = "qup-core", 1377 "qup-config", 1378 "qup-memory"; 1379 power-domains = <&rpmhpd SA8775P_CX>; 1380 status = "disabled"; 1381 }; 1382 1383 uart10: serial@a8c000 { 1384 compatible = "qcom,geni-uart"; 1385 reg = <0x0 0x00a8c000 0x0 0x4000>; 1386 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1387 clock-names = "se"; 1388 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1389 interconnect-names = "qup-core", "qup-config"; 1390 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 1391 &clk_virt SLAVE_QUP_CORE_1 0>, 1392 <&gem_noc MASTER_APPSS_PROC 0 1393 &config_noc SLAVE_QUP_1 0>; 1394 power-domains = <&rpmhpd SA8775P_CX>; 1395 operating-points-v2 = <&qup_opp_table_100mhz>; 1396 status = "disabled"; 1397 }; 1398 1399 i2c11: i2c@a90000 { 1400 compatible = "qcom,geni-i2c"; 1401 reg = <0x0 0xa90000 0x0 0x4000>; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1405 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1406 clock-names = "se"; 1407 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1408 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1409 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1410 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1411 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1412 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1413 interconnect-names = "qup-core", 1414 "qup-config", 1415 "qup-memory"; 1416 power-domains = <&rpmhpd SA8775P_CX>; 1417 status = "disabled"; 1418 }; 1419 1420 spi11: spi@a90000 { 1421 compatible = "qcom,geni-spi"; 1422 reg = <0x0 0xa90000 0x0 0x4000>; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1426 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1427 clock-names = "se"; 1428 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1429 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1430 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1431 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1432 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1433 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1434 interconnect-names = "qup-core", 1435 "qup-config", 1436 "qup-memory"; 1437 power-domains = <&rpmhpd SA8775P_CX>; 1438 status = "disabled"; 1439 }; 1440 1441 i2c12: i2c@a94000 { 1442 compatible = "qcom,geni-i2c"; 1443 reg = <0x0 0xa94000 0x0 0x4000>; 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1447 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1448 clock-names = "se"; 1449 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1450 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1451 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1452 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1453 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1454 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1455 interconnect-names = "qup-core", 1456 "qup-config", 1457 "qup-memory"; 1458 power-domains = <&rpmhpd SA8775P_CX>; 1459 status = "disabled"; 1460 }; 1461 1462 spi12: spi@a94000 { 1463 compatible = "qcom,geni-spi"; 1464 reg = <0x0 0xa94000 0x0 0x4000>; 1465 #address-cells = <1>; 1466 #size-cells = <0>; 1467 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1468 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1469 clock-names = "se"; 1470 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1471 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1472 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1473 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1474 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1475 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1476 interconnect-names = "qup-core", 1477 "qup-config", 1478 "qup-memory"; 1479 power-domains = <&rpmhpd SA8775P_CX>; 1480 status = "disabled"; 1481 }; 1482 1483 uart12: serial@a94000 { 1484 compatible = "qcom,geni-uart"; 1485 reg = <0x0 0x00a94000 0x0 0x4000>; 1486 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1487 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1488 clock-names = "se"; 1489 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1490 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1491 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1492 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1493 interconnect-names = "qup-core", "qup-config"; 1494 power-domains = <&rpmhpd SA8775P_CX>; 1495 status = "disabled"; 1496 }; 1497 1498 i2c13: i2c@a98000 { 1499 compatible = "qcom,geni-i2c"; 1500 reg = <0x0 0xa98000 0x0 0x4000>; 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1504 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1505 clock-names = "se"; 1506 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1507 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1508 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1509 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1510 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1511 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1512 interconnect-names = "qup-core", 1513 "qup-config", 1514 "qup-memory"; 1515 power-domains = <&rpmhpd SA8775P_CX>; 1516 status = "disabled"; 1517 }; 1518 }; 1519 1520 qupv3_id_3: geniqup@bc0000 { 1521 compatible = "qcom,geni-se-qup"; 1522 reg = <0x0 0xbc0000 0x0 0x6000>; 1523 #address-cells = <2>; 1524 #size-cells = <2>; 1525 ranges; 1526 clock-names = "m-ahb", "s-ahb"; 1527 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 1528 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 1529 iommus = <&apps_smmu 0x43 0x0>; 1530 status = "disabled"; 1531 1532 i2c21: i2c@b80000 { 1533 compatible = "qcom,geni-i2c"; 1534 reg = <0x0 0xb80000 0x0 0x4000>; 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 1538 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 1539 clock-names = "se"; 1540 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1541 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1542 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1543 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 1544 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1545 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1546 interconnect-names = "qup-core", 1547 "qup-config", 1548 "qup-memory"; 1549 power-domains = <&rpmhpd SA8775P_CX>; 1550 status = "disabled"; 1551 }; 1552 1553 spi21: spi@b80000 { 1554 compatible = "qcom,geni-spi"; 1555 reg = <0x0 0xb80000 0x0 0x4000>; 1556 #address-cells = <1>; 1557 #size-cells = <0>; 1558 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 1559 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 1560 clock-names = "se"; 1561 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1562 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1563 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1564 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 1565 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1566 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1567 interconnect-names = "qup-core", 1568 "qup-config", 1569 "qup-memory"; 1570 power-domains = <&rpmhpd SA8775P_CX>; 1571 status = "disabled"; 1572 }; 1573 }; 1574 1575 rng: rng@10d2000 { 1576 compatible = "qcom,sa8775p-trng", "qcom,trng"; 1577 reg = <0 0x010d2000 0 0x1000>; 1578 }; 1579 1580 ufs_mem_hc: ufs@1d84000 { 1581 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1582 reg = <0x0 0x01d84000 0x0 0x3000>; 1583 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1584 phys = <&ufs_mem_phy>; 1585 phy-names = "ufsphy"; 1586 lanes-per-direction = <2>; 1587 #reset-cells = <1>; 1588 resets = <&gcc GCC_UFS_PHY_BCR>; 1589 reset-names = "rst"; 1590 power-domains = <&gcc UFS_PHY_GDSC>; 1591 required-opps = <&rpmhpd_opp_nom>; 1592 iommus = <&apps_smmu 0x100 0x0>; 1593 dma-coherent; 1594 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1595 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1596 <&gcc GCC_UFS_PHY_AHB_CLK>, 1597 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1598 <&rpmhcc RPMH_CXO_CLK>, 1599 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1600 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1601 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1602 clock-names = "core_clk", 1603 "bus_aggr_clk", 1604 "iface_clk", 1605 "core_clk_unipro", 1606 "ref_clk", 1607 "tx_lane0_sync_clk", 1608 "rx_lane0_sync_clk", 1609 "rx_lane1_sync_clk"; 1610 freq-table-hz = <75000000 300000000>, 1611 <0 0>, 1612 <0 0>, 1613 <75000000 300000000>, 1614 <0 0>, 1615 <0 0>, 1616 <0 0>, 1617 <0 0>; 1618 qcom,ice = <&ice>; 1619 status = "disabled"; 1620 }; 1621 1622 ufs_mem_phy: phy@1d87000 { 1623 compatible = "qcom,sa8775p-qmp-ufs-phy"; 1624 reg = <0x0 0x01d87000 0x0 0xe10>; 1625 /* 1626 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 1627 * enables the CXO clock to eDP *and* UFS PHY. 1628 */ 1629 clocks = <&rpmhcc RPMH_CXO_CLK>, 1630 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1631 <&gcc GCC_EDP_REF_CLKREF_EN>; 1632 clock-names = "ref", "ref_aux", "qref"; 1633 power-domains = <&gcc UFS_PHY_GDSC>; 1634 resets = <&ufs_mem_hc 0>; 1635 reset-names = "ufsphy"; 1636 #phy-cells = <0>; 1637 status = "disabled"; 1638 }; 1639 1640 ice: crypto@1d88000 { 1641 compatible = "qcom,sa8775p-inline-crypto-engine", 1642 "qcom,inline-crypto-engine"; 1643 reg = <0x0 0x01d88000 0x0 0x8000>; 1644 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1645 }; 1646 1647 usb_0_hsphy: phy@88e4000 { 1648 compatible = "qcom,sa8775p-usb-hs-phy", 1649 "qcom,usb-snps-hs-5nm-phy"; 1650 reg = <0 0x088e4000 0 0x120>; 1651 clocks = <&rpmhcc RPMH_CXO_CLK>; 1652 clock-names = "ref"; 1653 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 1654 1655 #phy-cells = <0>; 1656 1657 status = "disabled"; 1658 }; 1659 1660 usb_0_qmpphy: phy@88e8000 { 1661 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 1662 reg = <0 0x088e8000 0 0x2000>; 1663 1664 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1665 <&gcc GCC_USB_CLKREF_EN>, 1666 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1667 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1668 clock-names = "aux", "ref", "com_aux", "pipe"; 1669 1670 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1671 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 1672 reset-names = "phy", "phy_phy"; 1673 1674 power-domains = <&gcc USB30_PRIM_GDSC>; 1675 1676 #clock-cells = <0>; 1677 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 1678 1679 #phy-cells = <0>; 1680 1681 status = "disabled"; 1682 }; 1683 1684 usb_0: usb@a6f8800 { 1685 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 1686 reg = <0 0x0a6f8800 0 0x400>; 1687 #address-cells = <2>; 1688 #size-cells = <2>; 1689 ranges; 1690 1691 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1692 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1693 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1694 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1695 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1696 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 1697 1698 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1699 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1700 assigned-clock-rates = <19200000>, <200000000>; 1701 1702 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 1703 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 1704 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1705 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1706 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 1707 interrupt-names = "pwr_event", 1708 "hs_phy_irq", 1709 "dp_hs_phy_irq", 1710 "dm_hs_phy_irq", 1711 "ss_phy_irq"; 1712 1713 power-domains = <&gcc USB30_PRIM_GDSC>; 1714 required-opps = <&rpmhpd_opp_nom>; 1715 1716 resets = <&gcc GCC_USB30_PRIM_BCR>; 1717 1718 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 1719 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 1720 interconnect-names = "usb-ddr", "apps-usb"; 1721 1722 wakeup-source; 1723 1724 status = "disabled"; 1725 1726 usb_0_dwc3: usb@a600000 { 1727 compatible = "snps,dwc3"; 1728 reg = <0 0x0a600000 0 0xe000>; 1729 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 1730 iommus = <&apps_smmu 0x080 0x0>; 1731 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 1732 phy-names = "usb2-phy", "usb3-phy"; 1733 }; 1734 }; 1735 1736 usb_1_hsphy: phy@88e6000 { 1737 compatible = "qcom,sa8775p-usb-hs-phy", 1738 "qcom,usb-snps-hs-5nm-phy"; 1739 reg = <0 0x088e6000 0 0x120>; 1740 clocks = <&gcc GCC_USB_CLKREF_EN>; 1741 clock-names = "ref"; 1742 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 1743 1744 #phy-cells = <0>; 1745 1746 status = "disabled"; 1747 }; 1748 1749 usb_1_qmpphy: phy@88ea000 { 1750 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 1751 reg = <0 0x088ea000 0 0x2000>; 1752 1753 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 1754 <&gcc GCC_USB_CLKREF_EN>, 1755 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 1756 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 1757 clock-names = "aux", "ref", "com_aux", "pipe"; 1758 1759 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 1760 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 1761 reset-names = "phy", "phy_phy"; 1762 1763 power-domains = <&gcc USB30_SEC_GDSC>; 1764 1765 #clock-cells = <0>; 1766 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 1767 1768 #phy-cells = <0>; 1769 1770 status = "disabled"; 1771 }; 1772 1773 usb_1: usb@a8f8800 { 1774 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 1775 reg = <0 0x0a8f8800 0 0x400>; 1776 #address-cells = <2>; 1777 #size-cells = <2>; 1778 ranges; 1779 1780 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 1781 <&gcc GCC_USB30_SEC_MASTER_CLK>, 1782 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 1783 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 1784 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 1785 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 1786 1787 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 1788 <&gcc GCC_USB30_SEC_MASTER_CLK>; 1789 assigned-clock-rates = <19200000>, <200000000>; 1790 1791 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 1792 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 1793 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 1794 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 1795 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 1796 interrupt-names = "pwr_event", 1797 "hs_phy_irq", 1798 "dp_hs_phy_irq", 1799 "dm_hs_phy_irq", 1800 "ss_phy_irq"; 1801 1802 power-domains = <&gcc USB30_SEC_GDSC>; 1803 required-opps = <&rpmhpd_opp_nom>; 1804 1805 resets = <&gcc GCC_USB30_SEC_BCR>; 1806 1807 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 1808 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 1809 interconnect-names = "usb-ddr", "apps-usb"; 1810 1811 wakeup-source; 1812 1813 status = "disabled"; 1814 1815 usb_1_dwc3: usb@a800000 { 1816 compatible = "snps,dwc3"; 1817 reg = <0 0x0a800000 0 0xe000>; 1818 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 1819 iommus = <&apps_smmu 0x0a0 0x0>; 1820 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 1821 phy-names = "usb2-phy", "usb3-phy"; 1822 }; 1823 }; 1824 1825 usb_2_hsphy: phy@88e7000 { 1826 compatible = "qcom,sa8775p-usb-hs-phy", 1827 "qcom,usb-snps-hs-5nm-phy"; 1828 reg = <0 0x088e7000 0 0x120>; 1829 clocks = <&gcc GCC_USB_CLKREF_EN>; 1830 clock-names = "ref"; 1831 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 1832 1833 #phy-cells = <0>; 1834 1835 status = "disabled"; 1836 }; 1837 1838 usb_2: usb@a4f8800 { 1839 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 1840 reg = <0 0x0a4f8800 0 0x400>; 1841 #address-cells = <2>; 1842 #size-cells = <2>; 1843 ranges; 1844 1845 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 1846 <&gcc GCC_USB20_MASTER_CLK>, 1847 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 1848 <&gcc GCC_USB20_SLEEP_CLK>, 1849 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 1850 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 1851 1852 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1853 <&gcc GCC_USB20_MASTER_CLK>; 1854 assigned-clock-rates = <19200000>, <200000000>; 1855 1856 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 1857 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 1858 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 1859 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 1860 interrupt-names = "pwr_event", 1861 "hs_phy_irq", 1862 "dp_hs_phy_irq", 1863 "dm_hs_phy_irq"; 1864 1865 power-domains = <&gcc USB20_PRIM_GDSC>; 1866 required-opps = <&rpmhpd_opp_nom>; 1867 1868 resets = <&gcc GCC_USB20_PRIM_BCR>; 1869 1870 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 1871 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 1872 interconnect-names = "usb-ddr", "apps-usb"; 1873 1874 wakeup-source; 1875 1876 status = "disabled"; 1877 1878 usb_2_dwc3: usb@a400000 { 1879 compatible = "snps,dwc3"; 1880 reg = <0 0x0a400000 0 0xe000>; 1881 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 1882 iommus = <&apps_smmu 0x020 0x0>; 1883 phys = <&usb_2_hsphy>; 1884 phy-names = "usb2-phy"; 1885 }; 1886 }; 1887 1888 tcsr_mutex: hwlock@1f40000 { 1889 compatible = "qcom,tcsr-mutex"; 1890 reg = <0x0 0x01f40000 0x0 0x20000>; 1891 #hwlock-cells = <1>; 1892 }; 1893 1894 gpucc: clock-controller@3d90000 { 1895 compatible = "qcom,sa8775p-gpucc"; 1896 reg = <0x0 0x03d90000 0x0 0xa000>; 1897 clocks = <&rpmhcc RPMH_CXO_CLK>, 1898 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1899 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1900 clock-names = "bi_tcxo", 1901 "gcc_gpu_gpll0_clk_src", 1902 "gcc_gpu_gpll0_div_clk_src"; 1903 #clock-cells = <1>; 1904 #reset-cells = <1>; 1905 #power-domain-cells = <1>; 1906 }; 1907 1908 adreno_smmu: iommu@3da0000 { 1909 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 1910 "qcom,smmu-500", "arm,mmu-500"; 1911 reg = <0x0 0x03da0000 0x0 0x20000>; 1912 #iommu-cells = <2>; 1913 #global-interrupts = <2>; 1914 dma-coherent; 1915 power-domains = <&gpucc GPU_CC_CX_GDSC>; 1916 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1917 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1918 <&gpucc GPU_CC_AHB_CLK>, 1919 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1920 <&gpucc GPU_CC_CX_GMU_CLK>, 1921 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1922 <&gpucc GPU_CC_HUB_AON_CLK>; 1923 clock-names = "gcc_gpu_memnoc_gfx_clk", 1924 "gcc_gpu_snoc_dvm_gfx_clk", 1925 "gpu_cc_ahb_clk", 1926 "gpu_cc_hlos1_vote_gpu_smmu_clk", 1927 "gpu_cc_cx_gmu_clk", 1928 "gpu_cc_hub_cx_int_clk", 1929 "gpu_cc_hub_aon_clk"; 1930 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1942 }; 1943 1944 serdes0: phy@8901000 { 1945 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 1946 reg = <0x0 0x08901000 0x0 0xe10>; 1947 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 1948 clock-names = "sgmi_ref"; 1949 #phy-cells = <0>; 1950 status = "disabled"; 1951 }; 1952 1953 serdes1: phy@8902000 { 1954 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 1955 reg = <0x0 0x08902000 0x0 0xe10>; 1956 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 1957 clock-names = "sgmi_ref"; 1958 #phy-cells = <0>; 1959 status = "disabled"; 1960 }; 1961 1962 pdc: interrupt-controller@b220000 { 1963 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 1964 reg = <0x0 0x0b220000 0x0 0x30000>, 1965 <0x0 0x17c000f0 0x0 0x64>; 1966 qcom,pdc-ranges = <0 480 40>, 1967 <40 140 14>, 1968 <54 263 1>, 1969 <55 306 4>, 1970 <59 312 3>, 1971 <62 374 2>, 1972 <64 434 2>, 1973 <66 438 2>, 1974 <70 520 1>, 1975 <73 523 1>, 1976 <118 568 6>, 1977 <124 609 3>, 1978 <159 638 1>, 1979 <160 720 3>, 1980 <169 728 30>, 1981 <199 416 2>, 1982 <201 449 1>, 1983 <202 89 1>, 1984 <203 451 1>, 1985 <204 462 1>, 1986 <205 264 1>, 1987 <206 579 1>, 1988 <207 653 1>, 1989 <208 656 1>, 1990 <209 659 1>, 1991 <210 122 1>, 1992 <211 699 1>, 1993 <212 705 1>, 1994 <213 450 1>, 1995 <214 643 2>, 1996 <216 646 5>, 1997 <221 390 5>, 1998 <226 700 2>, 1999 <228 440 1>, 2000 <229 663 1>, 2001 <230 524 2>, 2002 <232 612 3>, 2003 <235 723 5>; 2004 #interrupt-cells = <2>; 2005 interrupt-parent = <&intc>; 2006 interrupt-controller; 2007 }; 2008 2009 tsens2: thermal-sensor@c251000 { 2010 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 2011 reg = <0x0 0x0c251000 0x0 0x1ff>, 2012 <0x0 0x0c224000 0x0 0x8>; 2013 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 2015 #qcom,sensors = <13>; 2016 interrupt-names = "uplow", "critical"; 2017 #thermal-sensor-cells = <1>; 2018 }; 2019 2020 tsens3: thermal-sensor@c252000 { 2021 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 2022 reg = <0x0 0x0c252000 0x0 0x1ff>, 2023 <0x0 0x0c225000 0x0 0x8>; 2024 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 2025 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 2026 #qcom,sensors = <13>; 2027 interrupt-names = "uplow", "critical"; 2028 #thermal-sensor-cells = <1>; 2029 }; 2030 2031 tsens0: thermal-sensor@c263000 { 2032 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 2033 reg = <0x0 0x0c263000 0x0 0x1ff>, 2034 <0x0 0x0c222000 0x0 0x8>; 2035 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2037 #qcom,sensors = <12>; 2038 interrupt-names = "uplow", "critical"; 2039 #thermal-sensor-cells = <1>; 2040 }; 2041 2042 tsens1: thermal-sensor@c265000 { 2043 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 2044 reg = <0x0 0x0c265000 0x0 0x1ff>, 2045 <0x0 0x0c223000 0x0 0x8>; 2046 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2048 #qcom,sensors = <12>; 2049 interrupt-names = "uplow", "critical"; 2050 #thermal-sensor-cells = <1>; 2051 }; 2052 2053 aoss_qmp: power-management@c300000 { 2054 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 2055 reg = <0x0 0x0c300000 0x0 0x400>; 2056 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 2057 IPCC_MPROC_SIGNAL_GLINK_QMP 2058 IRQ_TYPE_EDGE_RISING>; 2059 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2060 #clock-cells = <0>; 2061 }; 2062 2063 sram@c3f0000 { 2064 compatible = "qcom,rpmh-stats"; 2065 reg = <0x0 0x0c3f0000 0x0 0x400>; 2066 }; 2067 2068 spmi_bus: spmi@c440000 { 2069 compatible = "qcom,spmi-pmic-arb"; 2070 reg = <0x0 0x0c440000 0x0 0x1100>, 2071 <0x0 0x0c600000 0x0 0x2000000>, 2072 <0x0 0x0e600000 0x0 0x100000>, 2073 <0x0 0x0e700000 0x0 0xa0000>, 2074 <0x0 0x0c40a000 0x0 0x26000>; 2075 reg-names = "core", 2076 "chnls", 2077 "obsrvr", 2078 "intr", 2079 "cnfg"; 2080 qcom,channel = <0>; 2081 qcom,ee = <0>; 2082 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2083 interrupt-names = "periph_irq"; 2084 interrupt-controller; 2085 #interrupt-cells = <4>; 2086 #address-cells = <2>; 2087 #size-cells = <0>; 2088 }; 2089 2090 tlmm: pinctrl@f000000 { 2091 compatible = "qcom,sa8775p-tlmm"; 2092 reg = <0x0 0x0f000000 0x0 0x1000000>; 2093 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2094 gpio-controller; 2095 #gpio-cells = <2>; 2096 interrupt-controller; 2097 #interrupt-cells = <2>; 2098 gpio-ranges = <&tlmm 0 0 149>; 2099 wakeup-parent = <&pdc>; 2100 }; 2101 2102 apps_smmu: iommu@15000000 { 2103 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2104 reg = <0x0 0x15000000 0x0 0x100000>; 2105 #iommu-cells = <2>; 2106 #global-interrupts = <2>; 2107 2108 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2128 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2159 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2160 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2161 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2162 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2163 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2164 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2165 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2166 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2167 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2168 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2169 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2172 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2176 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 2190 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2191 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2192 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 2193 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 2194 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 2195 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 2196 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 2197 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 2198 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 2199 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 2200 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 2201 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2202 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2203 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2206 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 2208 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 2209 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 2210 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 2211 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 2215 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 2223 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 2229 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 2236 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 2237 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 2238 }; 2239 2240 pcie_smmu: iommu@15200000 { 2241 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2242 reg = <0x0 0x15200000 0x0 0x80000>; 2243 #iommu-cells = <2>; 2244 #global-interrupts = <2>; 2245 2246 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 2247 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 2248 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 2249 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 2253 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 2254 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 2255 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 2256 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 2257 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 2258 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 2259 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 2260 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 2261 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 2262 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 2263 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 2264 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 2265 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 2266 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 2267 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 2268 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 2269 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 2270 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 2271 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 2272 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 2273 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 2274 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 2275 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 2276 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 2277 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 2278 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 2279 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 2280 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 2281 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 2282 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 2283 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 2284 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 2285 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 2286 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 2287 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 2288 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 2289 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 2290 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 2291 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 2292 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 2293 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 2294 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 2295 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 2296 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 2297 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 2298 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 2299 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 2300 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 2301 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 2302 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 2303 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 2304 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 2305 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 2306 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 2307 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 2308 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 2309 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 2310 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 2311 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 2312 }; 2313 2314 intc: interrupt-controller@17a00000 { 2315 compatible = "arm,gic-v3"; 2316 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2317 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2318 interrupt-controller; 2319 #interrupt-cells = <3>; 2320 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2321 #redistributor-regions = <1>; 2322 redistributor-stride = <0x0 0x20000>; 2323 }; 2324 2325 watchdog@17c10000 { 2326 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 2327 reg = <0x0 0x17c10000 0x0 0x1000>; 2328 clocks = <&sleep_clk>; 2329 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 2330 }; 2331 2332 memtimer: timer@17c20000 { 2333 compatible = "arm,armv7-timer-mem"; 2334 reg = <0x0 0x17c20000 0x0 0x1000>; 2335 ranges = <0x0 0x0 0x0 0x20000000>; 2336 #address-cells = <1>; 2337 #size-cells = <1>; 2338 2339 frame@17c21000 { 2340 reg = <0x17c21000 0x1000>, 2341 <0x17c22000 0x1000>; 2342 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2343 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2344 frame-number = <0>; 2345 }; 2346 2347 frame@17c23000 { 2348 reg = <0x17c23000 0x1000>; 2349 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2350 frame-number = <1>; 2351 status = "disabled"; 2352 }; 2353 2354 frame@17c25000 { 2355 reg = <0x17c25000 0x1000>; 2356 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2357 frame-number = <2>; 2358 status = "disabled"; 2359 }; 2360 2361 frame@17c27000 { 2362 reg = <0x17c27000 0x1000>; 2363 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2364 frame-number = <3>; 2365 status = "disabled"; 2366 }; 2367 2368 frame@17c29000 { 2369 reg = <0x17c29000 0x1000>; 2370 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2371 frame-number = <4>; 2372 status = "disabled"; 2373 }; 2374 2375 frame@17c2b000 { 2376 reg = <0x17c2b000 0x1000>; 2377 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2378 frame-number = <5>; 2379 status = "disabled"; 2380 }; 2381 2382 frame@17c2d000 { 2383 reg = <0x17c2d000 0x1000>; 2384 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2385 frame-number = <6>; 2386 status = "disabled"; 2387 }; 2388 }; 2389 2390 apps_rsc: rsc@18200000 { 2391 compatible = "qcom,rpmh-rsc"; 2392 reg = <0x0 0x18200000 0x0 0x10000>, 2393 <0x0 0x18210000 0x0 0x10000>, 2394 <0x0 0x18220000 0x0 0x10000>; 2395 reg-names = "drv-0", "drv-1", "drv-2"; 2396 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2399 qcom,tcs-offset = <0xd00>; 2400 qcom,drv-id = <2>; 2401 qcom,tcs-config = <ACTIVE_TCS 2>, 2402 <SLEEP_TCS 3>, 2403 <WAKE_TCS 3>, 2404 <CONTROL_TCS 0>; 2405 label = "apps_rsc"; 2406 2407 apps_bcm_voter: bcm-voter { 2408 compatible = "qcom,bcm-voter"; 2409 }; 2410 2411 rpmhcc: clock-controller { 2412 compatible = "qcom,sa8775p-rpmh-clk"; 2413 #clock-cells = <1>; 2414 clock-names = "xo"; 2415 clocks = <&xo_board_clk>; 2416 }; 2417 2418 rpmhpd: power-controller { 2419 compatible = "qcom,sa8775p-rpmhpd"; 2420 #power-domain-cells = <1>; 2421 operating-points-v2 = <&rpmhpd_opp_table>; 2422 2423 rpmhpd_opp_table: opp-table { 2424 compatible = "operating-points-v2"; 2425 2426 rpmhpd_opp_ret: opp-0 { 2427 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2428 }; 2429 2430 rpmhpd_opp_min_svs: opp-1 { 2431 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2432 }; 2433 2434 rpmhpd_opp_low_svs: opp2 { 2435 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2436 }; 2437 2438 rpmhpd_opp_svs: opp3 { 2439 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2440 }; 2441 2442 rpmhpd_opp_svs_l1: opp-4 { 2443 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2444 }; 2445 2446 rpmhpd_opp_nom: opp-5 { 2447 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2448 }; 2449 2450 rpmhpd_opp_nom_l1: opp-6 { 2451 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2452 }; 2453 2454 rpmhpd_opp_nom_l2: opp-7 { 2455 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2456 }; 2457 2458 rpmhpd_opp_turbo: opp-8 { 2459 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2460 }; 2461 2462 rpmhpd_opp_turbo_l1: opp-9 { 2463 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2464 }; 2465 }; 2466 }; 2467 }; 2468 2469 cpufreq_hw: cpufreq@18591000 { 2470 compatible = "qcom,sa8775p-cpufreq-epss", 2471 "qcom,cpufreq-epss"; 2472 reg = <0x0 0x18591000 0x0 0x1000>, 2473 <0x0 0x18593000 0x0 0x1000>; 2474 reg-names = "freq-domain0", "freq-domain1"; 2475 2476 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 2477 clock-names = "xo", "alternate"; 2478 2479 #freq-domain-cells = <1>; 2480 }; 2481 2482 ethernet1: ethernet@23000000 { 2483 compatible = "qcom,sa8775p-ethqos"; 2484 reg = <0x0 0x23000000 0x0 0x10000>, 2485 <0x0 0x23016000 0x0 0x100>; 2486 reg-names = "stmmaceth", "rgmii"; 2487 2488 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 2490 interrupt-names = "macirq", "sfty"; 2491 2492 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 2493 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 2494 <&gcc GCC_EMAC1_PTP_CLK>, 2495 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 2496 clock-names = "stmmaceth", 2497 "pclk", 2498 "ptp_ref", 2499 "phyaux"; 2500 2501 power-domains = <&gcc EMAC1_GDSC>; 2502 2503 phys = <&serdes1>; 2504 phy-names = "serdes"; 2505 2506 iommus = <&apps_smmu 0x140 0xf>; 2507 2508 snps,tso; 2509 snps,pbl = <32>; 2510 rx-fifo-depth = <16384>; 2511 tx-fifo-depth = <16384>; 2512 2513 status = "disabled"; 2514 }; 2515 2516 ethernet0: ethernet@23040000 { 2517 compatible = "qcom,sa8775p-ethqos"; 2518 reg = <0x0 0x23040000 0x0 0x10000>, 2519 <0x0 0x23056000 0x0 0x100>; 2520 reg-names = "stmmaceth", "rgmii"; 2521 2522 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 2523 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; 2524 interrupt-names = "macirq", "sfty"; 2525 2526 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 2527 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 2528 <&gcc GCC_EMAC0_PTP_CLK>, 2529 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 2530 clock-names = "stmmaceth", 2531 "pclk", 2532 "ptp_ref", 2533 "phyaux"; 2534 2535 power-domains = <&gcc EMAC0_GDSC>; 2536 2537 phys = <&serdes0>; 2538 phy-names = "serdes"; 2539 2540 iommus = <&apps_smmu 0x120 0xf>; 2541 2542 snps,tso; 2543 snps,pbl = <32>; 2544 rx-fifo-depth = <16384>; 2545 tx-fifo-depth = <16384>; 2546 2547 status = "disabled"; 2548 }; 2549 }; 2550 2551 thermal-zones { 2552 aoss-0-thermal { 2553 polling-delay-passive = <0>; 2554 polling-delay = <0>; 2555 2556 thermal-sensors = <&tsens0 0>; 2557 2558 trips { 2559 trip-point0 { 2560 temperature = <105000>; 2561 hysteresis = <5000>; 2562 type = "passive"; 2563 }; 2564 2565 trip-point1 { 2566 temperature = <115000>; 2567 hysteresis = <5000>; 2568 type = "passive"; 2569 }; 2570 }; 2571 }; 2572 2573 cpu-0-0-0-thermal { 2574 polling-delay-passive = <10>; 2575 polling-delay = <0>; 2576 2577 thermal-sensors = <&tsens0 1>; 2578 2579 trips { 2580 trip-point0 { 2581 temperature = <105000>; 2582 hysteresis = <5000>; 2583 type = "passive"; 2584 }; 2585 2586 trip-point1 { 2587 temperature = <115000>; 2588 hysteresis = <5000>; 2589 type = "passive"; 2590 }; 2591 }; 2592 }; 2593 2594 cpu-0-1-0-thermal { 2595 polling-delay-passive = <10>; 2596 polling-delay = <0>; 2597 2598 thermal-sensors = <&tsens0 2>; 2599 2600 trips { 2601 trip-point0 { 2602 temperature = <105000>; 2603 hysteresis = <5000>; 2604 type = "passive"; 2605 }; 2606 2607 trip-point1 { 2608 temperature = <115000>; 2609 hysteresis = <5000>; 2610 type = "passive"; 2611 }; 2612 }; 2613 }; 2614 2615 cpu-0-2-0-thermal { 2616 polling-delay-passive = <10>; 2617 polling-delay = <0>; 2618 2619 thermal-sensors = <&tsens0 3>; 2620 2621 trips { 2622 trip-point0 { 2623 temperature = <105000>; 2624 hysteresis = <5000>; 2625 type = "passive"; 2626 }; 2627 2628 trip-point1 { 2629 temperature = <115000>; 2630 hysteresis = <5000>; 2631 type = "passive"; 2632 }; 2633 }; 2634 }; 2635 2636 cpu-0-3-0-thermal { 2637 polling-delay-passive = <10>; 2638 polling-delay = <0>; 2639 2640 thermal-sensors = <&tsens0 4>; 2641 2642 trips { 2643 trip-point0 { 2644 temperature = <105000>; 2645 hysteresis = <5000>; 2646 type = "passive"; 2647 }; 2648 2649 trip-point1 { 2650 temperature = <115000>; 2651 hysteresis = <5000>; 2652 type = "passive"; 2653 }; 2654 }; 2655 }; 2656 2657 gpuss-0-thermal { 2658 polling-delay-passive = <10>; 2659 polling-delay = <0>; 2660 2661 thermal-sensors = <&tsens0 5>; 2662 2663 trips { 2664 trip-point0 { 2665 temperature = <105000>; 2666 hysteresis = <5000>; 2667 type = "passive"; 2668 }; 2669 2670 trip-point1 { 2671 temperature = <115000>; 2672 hysteresis = <5000>; 2673 type = "passive"; 2674 }; 2675 }; 2676 }; 2677 2678 gpuss-1-thermal { 2679 polling-delay-passive = <10>; 2680 polling-delay = <0>; 2681 2682 thermal-sensors = <&tsens0 6>; 2683 2684 trips { 2685 trip-point0 { 2686 temperature = <105000>; 2687 hysteresis = <5000>; 2688 type = "passive"; 2689 }; 2690 2691 trip-point1 { 2692 temperature = <115000>; 2693 hysteresis = <5000>; 2694 type = "passive"; 2695 }; 2696 }; 2697 }; 2698 2699 gpuss-2-thermal { 2700 polling-delay-passive = <10>; 2701 polling-delay = <0>; 2702 2703 thermal-sensors = <&tsens0 7>; 2704 2705 trips { 2706 trip-point0 { 2707 temperature = <105000>; 2708 hysteresis = <5000>; 2709 type = "passive"; 2710 }; 2711 2712 trip-point1 { 2713 temperature = <115000>; 2714 hysteresis = <5000>; 2715 type = "passive"; 2716 }; 2717 }; 2718 }; 2719 2720 audio-thermal { 2721 polling-delay-passive = <0>; 2722 polling-delay = <0>; 2723 2724 thermal-sensors = <&tsens0 8>; 2725 2726 trips { 2727 trip-point0 { 2728 temperature = <105000>; 2729 hysteresis = <5000>; 2730 type = "passive"; 2731 }; 2732 2733 trip-point1 { 2734 temperature = <115000>; 2735 hysteresis = <5000>; 2736 type = "passive"; 2737 }; 2738 }; 2739 }; 2740 2741 camss-0-thermal { 2742 polling-delay-passive = <0>; 2743 polling-delay = <0>; 2744 2745 thermal-sensors = <&tsens0 9>; 2746 2747 trips { 2748 trip-point0 { 2749 temperature = <105000>; 2750 hysteresis = <5000>; 2751 type = "passive"; 2752 }; 2753 2754 trip-point1 { 2755 temperature = <115000>; 2756 hysteresis = <5000>; 2757 type = "passive"; 2758 }; 2759 }; 2760 }; 2761 2762 pcie-0-thermal { 2763 polling-delay-passive = <0>; 2764 polling-delay = <0>; 2765 2766 thermal-sensors = <&tsens0 10>; 2767 2768 trips { 2769 trip-point0 { 2770 temperature = <105000>; 2771 hysteresis = <5000>; 2772 type = "passive"; 2773 }; 2774 2775 trip-point1 { 2776 temperature = <115000>; 2777 hysteresis = <5000>; 2778 type = "passive"; 2779 }; 2780 }; 2781 }; 2782 2783 cpuss-0-0-thermal { 2784 polling-delay-passive = <0>; 2785 polling-delay = <0>; 2786 2787 thermal-sensors = <&tsens0 11>; 2788 2789 trips { 2790 trip-point0 { 2791 temperature = <105000>; 2792 hysteresis = <5000>; 2793 type = "passive"; 2794 }; 2795 2796 trip-point1 { 2797 temperature = <115000>; 2798 hysteresis = <5000>; 2799 type = "passive"; 2800 }; 2801 }; 2802 }; 2803 2804 aoss-1-thermal { 2805 polling-delay-passive = <0>; 2806 polling-delay = <0>; 2807 2808 thermal-sensors = <&tsens1 0>; 2809 2810 trips { 2811 trip-point0 { 2812 temperature = <105000>; 2813 hysteresis = <5000>; 2814 type = "passive"; 2815 }; 2816 2817 trip-point1 { 2818 temperature = <115000>; 2819 hysteresis = <5000>; 2820 type = "passive"; 2821 }; 2822 }; 2823 }; 2824 2825 cpu-0-0-1-thermal { 2826 polling-delay-passive = <10>; 2827 polling-delay = <0>; 2828 2829 thermal-sensors = <&tsens1 1>; 2830 2831 trips { 2832 trip-point0 { 2833 temperature = <105000>; 2834 hysteresis = <5000>; 2835 type = "passive"; 2836 }; 2837 2838 trip-point1 { 2839 temperature = <115000>; 2840 hysteresis = <5000>; 2841 type = "passive"; 2842 }; 2843 }; 2844 }; 2845 2846 cpu-0-1-1-thermal { 2847 polling-delay-passive = <10>; 2848 polling-delay = <0>; 2849 2850 thermal-sensors = <&tsens1 2>; 2851 2852 trips { 2853 trip-point0 { 2854 temperature = <105000>; 2855 hysteresis = <5000>; 2856 type = "passive"; 2857 }; 2858 2859 trip-point1 { 2860 temperature = <115000>; 2861 hysteresis = <5000>; 2862 type = "passive"; 2863 }; 2864 }; 2865 }; 2866 2867 cpu-0-2-1-thermal { 2868 polling-delay-passive = <10>; 2869 polling-delay = <0>; 2870 2871 thermal-sensors = <&tsens1 3>; 2872 2873 trips { 2874 trip-point0 { 2875 temperature = <105000>; 2876 hysteresis = <5000>; 2877 type = "passive"; 2878 }; 2879 2880 trip-point1 { 2881 temperature = <115000>; 2882 hysteresis = <5000>; 2883 type = "passive"; 2884 }; 2885 }; 2886 }; 2887 2888 cpu-0-3-1-thermal { 2889 polling-delay-passive = <10>; 2890 polling-delay = <0>; 2891 2892 thermal-sensors = <&tsens1 4>; 2893 2894 trips { 2895 trip-point0 { 2896 temperature = <105000>; 2897 hysteresis = <5000>; 2898 type = "passive"; 2899 }; 2900 2901 trip-point1 { 2902 temperature = <115000>; 2903 hysteresis = <5000>; 2904 type = "passive"; 2905 }; 2906 }; 2907 }; 2908 2909 gpuss-3-thermal { 2910 polling-delay-passive = <10>; 2911 polling-delay = <0>; 2912 2913 thermal-sensors = <&tsens1 5>; 2914 2915 trips { 2916 trip-point0 { 2917 temperature = <105000>; 2918 hysteresis = <5000>; 2919 type = "passive"; 2920 }; 2921 2922 trip-point1 { 2923 temperature = <115000>; 2924 hysteresis = <5000>; 2925 type = "passive"; 2926 }; 2927 }; 2928 }; 2929 2930 gpuss-4-thermal { 2931 polling-delay-passive = <10>; 2932 polling-delay = <0>; 2933 2934 thermal-sensors = <&tsens1 6>; 2935 2936 trips { 2937 trip-point0 { 2938 temperature = <105000>; 2939 hysteresis = <5000>; 2940 type = "passive"; 2941 }; 2942 2943 trip-point1 { 2944 temperature = <115000>; 2945 hysteresis = <5000>; 2946 type = "passive"; 2947 }; 2948 }; 2949 }; 2950 2951 gpuss-5-thermal { 2952 polling-delay-passive = <10>; 2953 polling-delay = <0>; 2954 2955 thermal-sensors = <&tsens1 7>; 2956 2957 trips { 2958 trip-point0 { 2959 temperature = <105000>; 2960 hysteresis = <5000>; 2961 type = "passive"; 2962 }; 2963 2964 trip-point1 { 2965 temperature = <115000>; 2966 hysteresis = <5000>; 2967 type = "passive"; 2968 }; 2969 }; 2970 }; 2971 2972 video-thermal { 2973 polling-delay-passive = <0>; 2974 polling-delay = <0>; 2975 2976 thermal-sensors = <&tsens1 8>; 2977 2978 trips { 2979 trip-point0 { 2980 temperature = <105000>; 2981 hysteresis = <5000>; 2982 type = "passive"; 2983 }; 2984 2985 trip-point1 { 2986 temperature = <115000>; 2987 hysteresis = <5000>; 2988 type = "passive"; 2989 }; 2990 }; 2991 }; 2992 2993 camss-1-thermal { 2994 polling-delay-passive = <0>; 2995 polling-delay = <0>; 2996 2997 thermal-sensors = <&tsens1 9>; 2998 2999 trips { 3000 trip-point0 { 3001 temperature = <105000>; 3002 hysteresis = <5000>; 3003 type = "passive"; 3004 }; 3005 3006 trip-point1 { 3007 temperature = <115000>; 3008 hysteresis = <5000>; 3009 type = "passive"; 3010 }; 3011 }; 3012 }; 3013 3014 pcie-1-thermal { 3015 polling-delay-passive = <0>; 3016 polling-delay = <0>; 3017 3018 thermal-sensors = <&tsens1 10>; 3019 3020 trips { 3021 trip-point0 { 3022 temperature = <105000>; 3023 hysteresis = <5000>; 3024 type = "passive"; 3025 }; 3026 3027 trip-point1 { 3028 temperature = <115000>; 3029 hysteresis = <5000>; 3030 type = "passive"; 3031 }; 3032 }; 3033 }; 3034 3035 cpuss-0-1-thermal { 3036 polling-delay-passive = <0>; 3037 polling-delay = <0>; 3038 3039 thermal-sensors = <&tsens1 11>; 3040 3041 trips { 3042 trip-point0 { 3043 temperature = <105000>; 3044 hysteresis = <5000>; 3045 type = "passive"; 3046 }; 3047 3048 trip-point1 { 3049 temperature = <115000>; 3050 hysteresis = <5000>; 3051 type = "passive"; 3052 }; 3053 }; 3054 }; 3055 3056 aoss-2-thermal { 3057 polling-delay-passive = <0>; 3058 polling-delay = <0>; 3059 3060 thermal-sensors = <&tsens2 0>; 3061 3062 trips { 3063 trip-point0 { 3064 temperature = <105000>; 3065 hysteresis = <5000>; 3066 type = "passive"; 3067 }; 3068 3069 trip-point1 { 3070 temperature = <115000>; 3071 hysteresis = <5000>; 3072 type = "passive"; 3073 }; 3074 }; 3075 }; 3076 3077 cpu-1-0-0-thermal { 3078 polling-delay-passive = <10>; 3079 polling-delay = <0>; 3080 3081 thermal-sensors = <&tsens2 1>; 3082 3083 trips { 3084 trip-point0 { 3085 temperature = <105000>; 3086 hysteresis = <5000>; 3087 type = "passive"; 3088 }; 3089 3090 trip-point1 { 3091 temperature = <115000>; 3092 hysteresis = <5000>; 3093 type = "passive"; 3094 }; 3095 }; 3096 }; 3097 3098 cpu-1-1-0-thermal { 3099 polling-delay-passive = <10>; 3100 polling-delay = <0>; 3101 3102 thermal-sensors = <&tsens2 2>; 3103 3104 trips { 3105 trip-point0 { 3106 temperature = <105000>; 3107 hysteresis = <5000>; 3108 type = "passive"; 3109 }; 3110 3111 trip-point1 { 3112 temperature = <115000>; 3113 hysteresis = <5000>; 3114 type = "passive"; 3115 }; 3116 }; 3117 }; 3118 3119 cpu-1-2-0-thermal { 3120 polling-delay-passive = <10>; 3121 polling-delay = <0>; 3122 3123 thermal-sensors = <&tsens2 3>; 3124 3125 trips { 3126 trip-point0 { 3127 temperature = <105000>; 3128 hysteresis = <5000>; 3129 type = "passive"; 3130 }; 3131 3132 trip-point1 { 3133 temperature = <115000>; 3134 hysteresis = <5000>; 3135 type = "passive"; 3136 }; 3137 }; 3138 }; 3139 3140 cpu-1-3-0-thermal { 3141 polling-delay-passive = <10>; 3142 polling-delay = <0>; 3143 3144 thermal-sensors = <&tsens2 4>; 3145 3146 trips { 3147 trip-point0 { 3148 temperature = <105000>; 3149 hysteresis = <5000>; 3150 type = "passive"; 3151 }; 3152 3153 trip-point1 { 3154 temperature = <115000>; 3155 hysteresis = <5000>; 3156 type = "passive"; 3157 }; 3158 }; 3159 }; 3160 3161 nsp-0-0-0-thermal { 3162 polling-delay-passive = <10>; 3163 polling-delay = <0>; 3164 3165 thermal-sensors = <&tsens2 5>; 3166 3167 trips { 3168 trip-point0 { 3169 temperature = <105000>; 3170 hysteresis = <5000>; 3171 type = "passive"; 3172 }; 3173 3174 trip-point1 { 3175 temperature = <115000>; 3176 hysteresis = <5000>; 3177 type = "passive"; 3178 }; 3179 }; 3180 }; 3181 3182 nsp-0-1-0-thermal { 3183 polling-delay-passive = <10>; 3184 polling-delay = <0>; 3185 3186 thermal-sensors = <&tsens2 6>; 3187 3188 trips { 3189 trip-point0 { 3190 temperature = <105000>; 3191 hysteresis = <5000>; 3192 type = "passive"; 3193 }; 3194 3195 trip-point1 { 3196 temperature = <115000>; 3197 hysteresis = <5000>; 3198 type = "passive"; 3199 }; 3200 }; 3201 }; 3202 3203 nsp-0-2-0-thermal { 3204 polling-delay-passive = <10>; 3205 polling-delay = <0>; 3206 3207 thermal-sensors = <&tsens2 7>; 3208 3209 trips { 3210 trip-point0 { 3211 temperature = <105000>; 3212 hysteresis = <5000>; 3213 type = "passive"; 3214 }; 3215 3216 trip-point1 { 3217 temperature = <115000>; 3218 hysteresis = <5000>; 3219 type = "passive"; 3220 }; 3221 }; 3222 }; 3223 3224 nsp-1-0-0-thermal { 3225 polling-delay-passive = <10>; 3226 polling-delay = <0>; 3227 3228 thermal-sensors = <&tsens2 8>; 3229 3230 trips { 3231 trip-point0 { 3232 temperature = <105000>; 3233 hysteresis = <5000>; 3234 type = "passive"; 3235 }; 3236 3237 trip-point1 { 3238 temperature = <115000>; 3239 hysteresis = <5000>; 3240 type = "passive"; 3241 }; 3242 }; 3243 }; 3244 3245 nsp-1-1-0-thermal { 3246 polling-delay-passive = <10>; 3247 polling-delay = <0>; 3248 3249 thermal-sensors = <&tsens2 9>; 3250 3251 trips { 3252 trip-point0 { 3253 temperature = <105000>; 3254 hysteresis = <5000>; 3255 type = "passive"; 3256 }; 3257 3258 trip-point1 { 3259 temperature = <115000>; 3260 hysteresis = <5000>; 3261 type = "passive"; 3262 }; 3263 }; 3264 }; 3265 3266 nsp-1-2-0-thermal { 3267 polling-delay-passive = <10>; 3268 polling-delay = <0>; 3269 3270 thermal-sensors = <&tsens2 10>; 3271 3272 trips { 3273 trip-point0 { 3274 temperature = <105000>; 3275 hysteresis = <5000>; 3276 type = "passive"; 3277 }; 3278 3279 trip-point1 { 3280 temperature = <115000>; 3281 hysteresis = <5000>; 3282 type = "passive"; 3283 }; 3284 }; 3285 }; 3286 3287 ddrss-0-thermal { 3288 polling-delay-passive = <0>; 3289 polling-delay = <0>; 3290 3291 thermal-sensors = <&tsens2 11>; 3292 3293 trips { 3294 trip-point0 { 3295 temperature = <105000>; 3296 hysteresis = <5000>; 3297 type = "passive"; 3298 }; 3299 3300 trip-point1 { 3301 temperature = <115000>; 3302 hysteresis = <5000>; 3303 type = "passive"; 3304 }; 3305 }; 3306 }; 3307 3308 cpuss-1-0-thermal { 3309 polling-delay-passive = <0>; 3310 polling-delay = <0>; 3311 3312 thermal-sensors = <&tsens2 12>; 3313 3314 trips { 3315 trip-point0 { 3316 temperature = <105000>; 3317 hysteresis = <5000>; 3318 type = "passive"; 3319 }; 3320 3321 trip-point1 { 3322 temperature = <115000>; 3323 hysteresis = <5000>; 3324 type = "passive"; 3325 }; 3326 }; 3327 }; 3328 3329 aoss-3-thermal { 3330 polling-delay-passive = <0>; 3331 polling-delay = <0>; 3332 3333 thermal-sensors = <&tsens3 0>; 3334 3335 trips { 3336 trip-point0 { 3337 temperature = <105000>; 3338 hysteresis = <5000>; 3339 type = "passive"; 3340 }; 3341 3342 trip-point1 { 3343 temperature = <115000>; 3344 hysteresis = <5000>; 3345 type = "passive"; 3346 }; 3347 }; 3348 }; 3349 3350 cpu-1-0-1-thermal { 3351 polling-delay-passive = <10>; 3352 polling-delay = <0>; 3353 3354 thermal-sensors = <&tsens3 1>; 3355 3356 trips { 3357 trip-point0 { 3358 temperature = <105000>; 3359 hysteresis = <5000>; 3360 type = "passive"; 3361 }; 3362 3363 trip-point1 { 3364 temperature = <115000>; 3365 hysteresis = <5000>; 3366 type = "passive"; 3367 }; 3368 }; 3369 }; 3370 3371 cpu-1-1-1-thermal { 3372 polling-delay-passive = <10>; 3373 polling-delay = <0>; 3374 3375 thermal-sensors = <&tsens3 2>; 3376 3377 trips { 3378 trip-point0 { 3379 temperature = <105000>; 3380 hysteresis = <5000>; 3381 type = "passive"; 3382 }; 3383 3384 trip-point1 { 3385 temperature = <115000>; 3386 hysteresis = <5000>; 3387 type = "passive"; 3388 }; 3389 }; 3390 }; 3391 3392 cpu-1-2-1-thermal { 3393 polling-delay-passive = <10>; 3394 polling-delay = <0>; 3395 3396 thermal-sensors = <&tsens3 3>; 3397 3398 trips { 3399 trip-point0 { 3400 temperature = <105000>; 3401 hysteresis = <5000>; 3402 type = "passive"; 3403 }; 3404 3405 trip-point1 { 3406 temperature = <115000>; 3407 hysteresis = <5000>; 3408 type = "passive"; 3409 }; 3410 }; 3411 }; 3412 3413 cpu-1-3-1-thermal { 3414 polling-delay-passive = <10>; 3415 polling-delay = <0>; 3416 3417 thermal-sensors = <&tsens3 4>; 3418 3419 trips { 3420 trip-point0 { 3421 temperature = <105000>; 3422 hysteresis = <5000>; 3423 type = "passive"; 3424 }; 3425 3426 trip-point1 { 3427 temperature = <115000>; 3428 hysteresis = <5000>; 3429 type = "passive"; 3430 }; 3431 }; 3432 }; 3433 3434 nsp-0-0-1-thermal { 3435 polling-delay-passive = <10>; 3436 polling-delay = <0>; 3437 3438 thermal-sensors = <&tsens3 5>; 3439 3440 trips { 3441 trip-point0 { 3442 temperature = <105000>; 3443 hysteresis = <5000>; 3444 type = "passive"; 3445 }; 3446 3447 trip-point1 { 3448 temperature = <115000>; 3449 hysteresis = <5000>; 3450 type = "passive"; 3451 }; 3452 }; 3453 }; 3454 3455 nsp-0-1-1-thermal { 3456 polling-delay-passive = <10>; 3457 polling-delay = <0>; 3458 3459 thermal-sensors = <&tsens3 6>; 3460 3461 trips { 3462 trip-point0 { 3463 temperature = <105000>; 3464 hysteresis = <5000>; 3465 type = "passive"; 3466 }; 3467 3468 trip-point1 { 3469 temperature = <115000>; 3470 hysteresis = <5000>; 3471 type = "passive"; 3472 }; 3473 }; 3474 }; 3475 3476 nsp-0-2-1-thermal { 3477 polling-delay-passive = <10>; 3478 polling-delay = <0>; 3479 3480 thermal-sensors = <&tsens3 7>; 3481 3482 trips { 3483 trip-point0 { 3484 temperature = <105000>; 3485 hysteresis = <5000>; 3486 type = "passive"; 3487 }; 3488 3489 trip-point1 { 3490 temperature = <115000>; 3491 hysteresis = <5000>; 3492 type = "passive"; 3493 }; 3494 }; 3495 }; 3496 3497 nsp-1-0-1-thermal { 3498 polling-delay-passive = <10>; 3499 polling-delay = <0>; 3500 3501 thermal-sensors = <&tsens3 8>; 3502 3503 trips { 3504 trip-point0 { 3505 temperature = <105000>; 3506 hysteresis = <5000>; 3507 type = "passive"; 3508 }; 3509 3510 trip-point1 { 3511 temperature = <115000>; 3512 hysteresis = <5000>; 3513 type = "passive"; 3514 }; 3515 }; 3516 }; 3517 3518 nsp-1-1-1-thermal { 3519 polling-delay-passive = <10>; 3520 polling-delay = <0>; 3521 3522 thermal-sensors = <&tsens3 9>; 3523 3524 trips { 3525 trip-point0 { 3526 temperature = <105000>; 3527 hysteresis = <5000>; 3528 type = "passive"; 3529 }; 3530 3531 trip-point1 { 3532 temperature = <115000>; 3533 hysteresis = <5000>; 3534 type = "passive"; 3535 }; 3536 }; 3537 }; 3538 3539 nsp-1-2-1-thermal { 3540 polling-delay-passive = <10>; 3541 polling-delay = <0>; 3542 3543 thermal-sensors = <&tsens3 10>; 3544 3545 trips { 3546 trip-point0 { 3547 temperature = <105000>; 3548 hysteresis = <5000>; 3549 type = "passive"; 3550 }; 3551 3552 trip-point1 { 3553 temperature = <115000>; 3554 hysteresis = <5000>; 3555 type = "passive"; 3556 }; 3557 }; 3558 }; 3559 3560 ddrss-1-thermal { 3561 polling-delay-passive = <0>; 3562 polling-delay = <0>; 3563 3564 thermal-sensors = <&tsens3 11>; 3565 3566 trips { 3567 trip-point0 { 3568 temperature = <105000>; 3569 hysteresis = <5000>; 3570 type = "passive"; 3571 }; 3572 3573 trip-point1 { 3574 temperature = <115000>; 3575 hysteresis = <5000>; 3576 type = "passive"; 3577 }; 3578 }; 3579 }; 3580 3581 cpuss-1-1-thermal { 3582 polling-delay-passive = <0>; 3583 polling-delay = <0>; 3584 3585 thermal-sensors = <&tsens3 12>; 3586 3587 trips { 3588 trip-point0 { 3589 temperature = <105000>; 3590 hysteresis = <5000>; 3591 type = "passive"; 3592 }; 3593 3594 trip-point1 { 3595 temperature = <115000>; 3596 hysteresis = <5000>; 3597 type = "passive"; 3598 }; 3599 }; 3600 }; 3601 }; 3602 3603 arch_timer: timer { 3604 compatible = "arm,armv8-timer"; 3605 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3606 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3607 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3608 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3609 }; 3610 3611 pcie0: pcie@1c00000 { 3612 compatible = "qcom,pcie-sa8775p"; 3613 reg = <0x0 0x01c00000 0x0 0x3000>, 3614 <0x0 0x40000000 0x0 0xf20>, 3615 <0x0 0x40000f20 0x0 0xa8>, 3616 <0x0 0x40001000 0x0 0x4000>, 3617 <0x0 0x40100000 0x0 0x100000>, 3618 <0x0 0x01c03000 0x0 0x1000>; 3619 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 3620 device_type = "pci"; 3621 3622 #address-cells = <3>; 3623 #size-cells = <2>; 3624 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 3625 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 3626 bus-range = <0x00 0xff>; 3627 3628 dma-coherent; 3629 3630 linux,pci-domain = <0>; 3631 num-lanes = <2>; 3632 3633 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 3641 interrupt-names = "msi0", "msi1", "msi2", "msi3", 3642 "msi4", "msi5", "msi6", "msi7"; 3643 #interrupt-cells = <1>; 3644 interrupt-map-mask = <0 0 0 0x7>; 3645 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 3646 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 3647 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 3648 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 3649 3650 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3651 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3652 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 3653 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 3654 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 3655 3656 clock-names = "aux", 3657 "cfg", 3658 "bus_master", 3659 "bus_slave", 3660 "slave_q2a"; 3661 3662 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 3663 assigned-clock-rates = <19200000>; 3664 3665 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 3666 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 3667 interconnect-names = "pcie-mem", "cpu-pcie"; 3668 3669 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 3670 <0x100 &pcie_smmu 0x0001 0x1>; 3671 3672 resets = <&gcc GCC_PCIE_0_BCR>; 3673 reset-names = "pci"; 3674 power-domains = <&gcc PCIE_0_GDSC>; 3675 3676 phys = <&pcie0_phy>; 3677 phy-names = "pciephy"; 3678 3679 status = "disabled"; 3680 }; 3681 3682 pcie0_phy: phy@1c04000 { 3683 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 3684 reg = <0x0 0x1c04000 0x0 0x2000>; 3685 3686 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3687 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3688 <&gcc GCC_PCIE_CLKREF_EN>, 3689 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 3690 <&gcc GCC_PCIE_0_PIPE_CLK>, 3691 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, 3692 <&gcc GCC_PCIE_0_PHY_AUX_CLK>; 3693 3694 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 3695 "pipediv2", "phy_aux"; 3696 3697 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 3698 assigned-clock-rates = <100000000>; 3699 3700 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 3701 reset-names = "phy"; 3702 3703 #clock-cells = <0>; 3704 clock-output-names = "pcie_0_pipe_clk"; 3705 3706 #phy-cells = <0>; 3707 3708 status = "disabled"; 3709 }; 3710 3711 pcie1: pcie@1c10000 { 3712 compatible = "qcom,pcie-sa8775p"; 3713 reg = <0x0 0x01c10000 0x0 0x3000>, 3714 <0x0 0x60000000 0x0 0xf20>, 3715 <0x0 0x60000f20 0x0 0xa8>, 3716 <0x0 0x60001000 0x0 0x4000>, 3717 <0x0 0x60100000 0x0 0x100000>, 3718 <0x0 0x01c13000 0x0 0x1000>; 3719 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 3720 device_type = "pci"; 3721 3722 #address-cells = <3>; 3723 #size-cells = <2>; 3724 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 3725 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 3726 bus-range = <0x00 0xff>; 3727 3728 dma-coherent; 3729 3730 linux,pci-domain = <1>; 3731 num-lanes = <4>; 3732 3733 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3736 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 3741 interrupt-names = "msi0", "msi1", "msi2", "msi3", 3742 "msi4", "msi5", "msi6", "msi7"; 3743 #interrupt-cells = <1>; 3744 interrupt-map-mask = <0 0 0 0x7>; 3745 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 3746 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 3747 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 3748 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 3749 3750 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 3751 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3752 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 3753 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 3754 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 3755 3756 clock-names = "aux", 3757 "cfg", 3758 "bus_master", 3759 "bus_slave", 3760 "slave_q2a"; 3761 3762 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 3763 assigned-clock-rates = <19200000>; 3764 3765 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 3766 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 3767 interconnect-names = "pcie-mem", "cpu-pcie"; 3768 3769 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 3770 <0x100 &pcie_smmu 0x0081 0x1>; 3771 3772 resets = <&gcc GCC_PCIE_1_BCR>; 3773 reset-names = "pci"; 3774 power-domains = <&gcc PCIE_1_GDSC>; 3775 3776 phys = <&pcie1_phy>; 3777 phy-names = "pciephy"; 3778 3779 status = "disabled"; 3780 }; 3781 3782 pcie1_phy: phy@1c14000 { 3783 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 3784 reg = <0x0 0x1c14000 0x0 0x4000>; 3785 3786 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 3787 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3788 <&gcc GCC_PCIE_CLKREF_EN>, 3789 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 3790 <&gcc GCC_PCIE_1_PIPE_CLK>, 3791 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, 3792 <&gcc GCC_PCIE_1_PHY_AUX_CLK>; 3793 3794 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 3795 "pipediv2", "phy_aux"; 3796 3797 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 3798 assigned-clock-rates = <100000000>; 3799 3800 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 3801 reset-names = "phy"; 3802 3803 #clock-cells = <0>; 3804 clock-output-names = "pcie_1_pipe_clk"; 3805 3806 #phy-cells = <0>; 3807 3808 status = "disabled"; 3809 }; 3810}; 3811