1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#include <dt-bindings/interconnect/qcom,icc.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 11#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/power/qcom,rpmhpd.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19 20/ { 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 clocks { 27 xo_board_clk: xo-board-clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 }; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "qcom,kryo"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 qcom,freq-domain = <&cpufreq_hw 0>; 48 next-level-cache = <&l2_0>; 49 capacity-dmips-mhz = <1024>; 50 dynamic-power-coefficient = <100>; 51 l2_0: l2-cache { 52 compatible = "cache"; 53 cache-level = <2>; 54 cache-unified; 55 next-level-cache = <&l3_0>; 56 l3_0: l3-cache { 57 compatible = "cache"; 58 cache-level = <3>; 59 cache-unified; 60 }; 61 }; 62 }; 63 64 cpu1: cpu@100 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo"; 67 reg = <0x0 0x100>; 68 enable-method = "psci"; 69 qcom,freq-domain = <&cpufreq_hw 0>; 70 next-level-cache = <&l2_1>; 71 capacity-dmips-mhz = <1024>; 72 dynamic-power-coefficient = <100>; 73 l2_1: l2-cache { 74 compatible = "cache"; 75 cache-level = <2>; 76 cache-unified; 77 next-level-cache = <&l3_0>; 78 }; 79 }; 80 81 cpu2: cpu@200 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo"; 84 reg = <0x0 0x200>; 85 enable-method = "psci"; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 next-level-cache = <&l2_2>; 88 capacity-dmips-mhz = <1024>; 89 dynamic-power-coefficient = <100>; 90 l2_2: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 next-level-cache = <&l3_0>; 95 }; 96 }; 97 98 cpu3: cpu@300 { 99 device_type = "cpu"; 100 compatible = "qcom,kryo"; 101 reg = <0x0 0x300>; 102 enable-method = "psci"; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 next-level-cache = <&l2_3>; 105 capacity-dmips-mhz = <1024>; 106 dynamic-power-coefficient = <100>; 107 l2_3: l2-cache { 108 compatible = "cache"; 109 cache-level = <2>; 110 cache-unified; 111 next-level-cache = <&l3_0>; 112 }; 113 }; 114 115 cpu4: cpu@10000 { 116 device_type = "cpu"; 117 compatible = "qcom,kryo"; 118 reg = <0x0 0x10000>; 119 enable-method = "psci"; 120 qcom,freq-domain = <&cpufreq_hw 1>; 121 next-level-cache = <&l2_4>; 122 capacity-dmips-mhz = <1024>; 123 dynamic-power-coefficient = <100>; 124 l2_4: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 cache-unified; 128 next-level-cache = <&l3_1>; 129 l3_1: l3-cache { 130 compatible = "cache"; 131 cache-level = <3>; 132 cache-unified; 133 }; 134 135 }; 136 }; 137 138 cpu5: cpu@10100 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo"; 141 reg = <0x0 0x10100>; 142 enable-method = "psci"; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 next-level-cache = <&l2_5>; 145 capacity-dmips-mhz = <1024>; 146 dynamic-power-coefficient = <100>; 147 l2_5: l2-cache { 148 compatible = "cache"; 149 cache-level = <2>; 150 cache-unified; 151 next-level-cache = <&l3_1>; 152 }; 153 }; 154 155 cpu6: cpu@10200 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo"; 158 reg = <0x0 0x10200>; 159 enable-method = "psci"; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 next-level-cache = <&l2_6>; 162 capacity-dmips-mhz = <1024>; 163 dynamic-power-coefficient = <100>; 164 l2_6: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&l3_1>; 169 }; 170 }; 171 172 cpu7: cpu@10300 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo"; 175 reg = <0x0 0x10300>; 176 enable-method = "psci"; 177 qcom,freq-domain = <&cpufreq_hw 1>; 178 next-level-cache = <&l2_7>; 179 capacity-dmips-mhz = <1024>; 180 dynamic-power-coefficient = <100>; 181 l2_7: l2-cache { 182 compatible = "cache"; 183 cache-level = <2>; 184 cache-unified; 185 next-level-cache = <&l3_1>; 186 }; 187 }; 188 189 cpu-map { 190 cluster0 { 191 core0 { 192 cpu = <&cpu0>; 193 }; 194 195 core1 { 196 cpu = <&cpu1>; 197 }; 198 199 core2 { 200 cpu = <&cpu2>; 201 }; 202 203 core3 { 204 cpu = <&cpu3>; 205 }; 206 }; 207 208 cluster1 { 209 core0 { 210 cpu = <&cpu4>; 211 }; 212 213 core1 { 214 cpu = <&cpu5>; 215 }; 216 217 core2 { 218 cpu = <&cpu6>; 219 }; 220 221 core3 { 222 cpu = <&cpu7>; 223 }; 224 }; 225 }; 226 227 idle-states { 228 entry-method = "psci"; 229 230 gold_cpu_sleep_0: cpu-sleep-0 { 231 compatible = "arm,idle-state"; 232 idle-state-name = "gold-power-collapse"; 233 arm,psci-suspend-param = <0x40000003>; 234 entry-latency-us = <549>; 235 exit-latency-us = <901>; 236 min-residency-us = <1774>; 237 local-timer-stop; 238 }; 239 240 gold_rail_cpu_sleep_0: cpu-sleep-1 { 241 compatible = "arm,idle-state"; 242 idle-state-name = "gold-rail-power-collapse"; 243 arm,psci-suspend-param = <0x40000004>; 244 entry-latency-us = <702>; 245 exit-latency-us = <1061>; 246 min-residency-us = <4488>; 247 local-timer-stop; 248 }; 249 }; 250 251 domain-idle-states { 252 cluster_sleep_gold: cluster-sleep-0 { 253 compatible = "domain-idle-state"; 254 arm,psci-suspend-param = <0x41000044>; 255 entry-latency-us = <2752>; 256 exit-latency-us = <3048>; 257 min-residency-us = <6118>; 258 }; 259 260 cluster_sleep_apss_rsc_pc: cluster-sleep-1 { 261 compatible = "domain-idle-state"; 262 arm,psci-suspend-param = <0x42000144>; 263 entry-latency-us = <3263>; 264 exit-latency-us = <6562>; 265 min-residency-us = <9987>; 266 }; 267 }; 268 }; 269 270 dummy-sink { 271 compatible = "arm,coresight-dummy-sink"; 272 273 in-ports { 274 port { 275 eud_in: endpoint { 276 remote-endpoint = 277 <&swao_rep_out1>; 278 }; 279 }; 280 }; 281 }; 282 283 firmware { 284 scm { 285 compatible = "qcom,scm-sa8775p", "qcom,scm"; 286 qcom,dload-mode = <&tcsr 0x13000>; 287 memory-region = <&tz_ffi_mem>; 288 }; 289 }; 290 291 aggre1_noc: interconnect-aggre1-noc { 292 compatible = "qcom,sa8775p-aggre1-noc"; 293 #interconnect-cells = <2>; 294 qcom,bcm-voters = <&apps_bcm_voter>; 295 }; 296 297 aggre2_noc: interconnect-aggre2-noc { 298 compatible = "qcom,sa8775p-aggre2-noc"; 299 #interconnect-cells = <2>; 300 qcom,bcm-voters = <&apps_bcm_voter>; 301 }; 302 303 clk_virt: interconnect-clk-virt { 304 compatible = "qcom,sa8775p-clk-virt"; 305 #interconnect-cells = <2>; 306 qcom,bcm-voters = <&apps_bcm_voter>; 307 }; 308 309 config_noc: interconnect-config-noc { 310 compatible = "qcom,sa8775p-config-noc"; 311 #interconnect-cells = <2>; 312 qcom,bcm-voters = <&apps_bcm_voter>; 313 }; 314 315 dc_noc: interconnect-dc-noc { 316 compatible = "qcom,sa8775p-dc-noc"; 317 #interconnect-cells = <2>; 318 qcom,bcm-voters = <&apps_bcm_voter>; 319 }; 320 321 gem_noc: interconnect-gem-noc { 322 compatible = "qcom,sa8775p-gem-noc"; 323 #interconnect-cells = <2>; 324 qcom,bcm-voters = <&apps_bcm_voter>; 325 }; 326 327 gpdsp_anoc: interconnect-gpdsp-anoc { 328 compatible = "qcom,sa8775p-gpdsp-anoc"; 329 #interconnect-cells = <2>; 330 qcom,bcm-voters = <&apps_bcm_voter>; 331 }; 332 333 lpass_ag_noc: interconnect-lpass-ag-noc { 334 compatible = "qcom,sa8775p-lpass-ag-noc"; 335 #interconnect-cells = <2>; 336 qcom,bcm-voters = <&apps_bcm_voter>; 337 }; 338 339 mc_virt: interconnect-mc-virt { 340 compatible = "qcom,sa8775p-mc-virt"; 341 #interconnect-cells = <2>; 342 qcom,bcm-voters = <&apps_bcm_voter>; 343 }; 344 345 mmss_noc: interconnect-mmss-noc { 346 compatible = "qcom,sa8775p-mmss-noc"; 347 #interconnect-cells = <2>; 348 qcom,bcm-voters = <&apps_bcm_voter>; 349 }; 350 351 nspa_noc: interconnect-nspa-noc { 352 compatible = "qcom,sa8775p-nspa-noc"; 353 #interconnect-cells = <2>; 354 qcom,bcm-voters = <&apps_bcm_voter>; 355 }; 356 357 nspb_noc: interconnect-nspb-noc { 358 compatible = "qcom,sa8775p-nspb-noc"; 359 #interconnect-cells = <2>; 360 qcom,bcm-voters = <&apps_bcm_voter>; 361 }; 362 363 pcie_anoc: interconnect-pcie-anoc { 364 compatible = "qcom,sa8775p-pcie-anoc"; 365 #interconnect-cells = <2>; 366 qcom,bcm-voters = <&apps_bcm_voter>; 367 }; 368 369 system_noc: interconnect-system-noc { 370 compatible = "qcom,sa8775p-system-noc"; 371 #interconnect-cells = <2>; 372 qcom,bcm-voters = <&apps_bcm_voter>; 373 }; 374 375 /* Will be updated by the bootloader. */ 376 memory@80000000 { 377 device_type = "memory"; 378 reg = <0x0 0x80000000 0x0 0x0>; 379 }; 380 381 qup_opp_table_100mhz: opp-table-qup100mhz { 382 compatible = "operating-points-v2"; 383 384 opp-100000000 { 385 opp-hz = /bits/ 64 <100000000>; 386 required-opps = <&rpmhpd_opp_svs_l1>; 387 }; 388 }; 389 390 pmu { 391 compatible = "arm,armv8-pmuv3"; 392 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 393 }; 394 395 psci { 396 compatible = "arm,psci-1.0"; 397 method = "smc"; 398 399 cpu_pd0: power-domain-cpu0 { 400 #power-domain-cells = <0>; 401 power-domains = <&cluster_0_pd>; 402 domain-idle-states = <&gold_cpu_sleep_0>, 403 <&gold_rail_cpu_sleep_0>; 404 }; 405 406 cpu_pd1: power-domain-cpu1 { 407 #power-domain-cells = <0>; 408 power-domains = <&cluster_0_pd>; 409 domain-idle-states = <&gold_cpu_sleep_0>, 410 <&gold_rail_cpu_sleep_0>; 411 }; 412 413 cpu_pd2: power-domain-cpu2 { 414 #power-domain-cells = <0>; 415 power-domains = <&cluster_0_pd>; 416 domain-idle-states = <&gold_cpu_sleep_0>, 417 <&gold_rail_cpu_sleep_0>; 418 }; 419 420 cpu_pd3: power-domain-cpu3 { 421 #power-domain-cells = <0>; 422 power-domains = <&cluster_0_pd>; 423 domain-idle-states = <&gold_cpu_sleep_0>, 424 <&gold_rail_cpu_sleep_0>; 425 }; 426 427 cpu_pd4: power-domain-cpu4 { 428 #power-domain-cells = <0>; 429 power-domains = <&cluster_1_pd>; 430 domain-idle-states = <&gold_cpu_sleep_0>, 431 <&gold_rail_cpu_sleep_0>; 432 }; 433 434 cpu_pd5: power-domain-cpu5 { 435 #power-domain-cells = <0>; 436 power-domains = <&cluster_1_pd>; 437 domain-idle-states = <&gold_cpu_sleep_0>, 438 <&gold_rail_cpu_sleep_0>; 439 }; 440 441 cpu_pd6: power-domain-cpu6 { 442 #power-domain-cells = <0>; 443 power-domains = <&cluster_1_pd>; 444 domain-idle-states = <&gold_cpu_sleep_0>, 445 <&gold_rail_cpu_sleep_0>; 446 }; 447 448 cpu_pd7: power-domain-cpu7 { 449 #power-domain-cells = <0>; 450 power-domains = <&cluster_1_pd>; 451 domain-idle-states = <&gold_cpu_sleep_0>, 452 <&gold_rail_cpu_sleep_0>; 453 }; 454 455 cluster_0_pd: power-domain-cluster0 { 456 #power-domain-cells = <0>; 457 power-domains = <&cluster_2_pd>; 458 domain-idle-states = <&cluster_sleep_gold>; 459 }; 460 461 cluster_1_pd: power-domain-cluster1 { 462 #power-domain-cells = <0>; 463 power-domains = <&cluster_2_pd>; 464 domain-idle-states = <&cluster_sleep_gold>; 465 }; 466 467 cluster_2_pd: power-domain-cluster2 { 468 #power-domain-cells = <0>; 469 domain-idle-states = <&cluster_sleep_apss_rsc_pc>; 470 }; 471 }; 472 473 reserved-memory { 474 #address-cells = <2>; 475 #size-cells = <2>; 476 ranges; 477 478 sail_ss_mem: sail-ss@80000000 { 479 reg = <0x0 0x80000000 0x0 0x10000000>; 480 no-map; 481 }; 482 483 hyp_mem: hyp@90000000 { 484 reg = <0x0 0x90000000 0x0 0x600000>; 485 no-map; 486 }; 487 488 xbl_boot_mem: xbl-boot@90600000 { 489 reg = <0x0 0x90600000 0x0 0x200000>; 490 no-map; 491 }; 492 493 aop_image_mem: aop-image@90800000 { 494 reg = <0x0 0x90800000 0x0 0x60000>; 495 no-map; 496 }; 497 498 aop_cmd_db_mem: aop-cmd-db@90860000 { 499 compatible = "qcom,cmd-db"; 500 reg = <0x0 0x90860000 0x0 0x20000>; 501 no-map; 502 }; 503 504 uefi_log: uefi-log@908b0000 { 505 reg = <0x0 0x908b0000 0x0 0x10000>; 506 no-map; 507 }; 508 509 ddr_training_checksum: ddr-training-checksum@908c0000 { 510 reg = <0x0 0x908c0000 0x0 0x1000>; 511 no-map; 512 }; 513 514 reserved_mem: reserved@908f0000 { 515 reg = <0x0 0x908f0000 0x0 0xe000>; 516 no-map; 517 }; 518 519 secdata_apss_mem: secdata-apss@908fe000 { 520 reg = <0x0 0x908fe000 0x0 0x2000>; 521 no-map; 522 }; 523 524 smem_mem: smem@90900000 { 525 compatible = "qcom,smem"; 526 reg = <0x0 0x90900000 0x0 0x200000>; 527 no-map; 528 hwlocks = <&tcsr_mutex 3>; 529 }; 530 531 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { 532 reg = <0x0 0x90c00000 0x0 0x100000>; 533 no-map; 534 }; 535 536 sail_mailbox_mem: sail-ss@90d00000 { 537 reg = <0x0 0x90d00000 0x0 0x100000>; 538 no-map; 539 }; 540 541 sail_ota_mem: sail-ss@90e00000 { 542 reg = <0x0 0x90e00000 0x0 0x300000>; 543 no-map; 544 }; 545 546 aoss_backup_mem: aoss-backup@91b00000 { 547 reg = <0x0 0x91b00000 0x0 0x40000>; 548 no-map; 549 }; 550 551 cpucp_backup_mem: cpucp-backup@91b40000 { 552 reg = <0x0 0x91b40000 0x0 0x40000>; 553 no-map; 554 }; 555 556 tz_config_backup_mem: tz-config-backup@91b80000 { 557 reg = <0x0 0x91b80000 0x0 0x10000>; 558 no-map; 559 }; 560 561 ddr_training_data_mem: ddr-training-data@91b90000 { 562 reg = <0x0 0x91b90000 0x0 0x10000>; 563 no-map; 564 }; 565 566 cdt_data_backup_mem: cdt-data-backup@91ba0000 { 567 reg = <0x0 0x91ba0000 0x0 0x1000>; 568 no-map; 569 }; 570 571 tz_ffi_mem: tz-ffi@91c00000 { 572 compatible = "shared-dma-pool"; 573 reg = <0x0 0x91c00000 0x0 0x1400000>; 574 no-map; 575 }; 576 577 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 578 reg = <0x0 0x93b00000 0x0 0xf00000>; 579 no-map; 580 }; 581 582 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 583 reg = <0x0 0x94a00000 0x0 0x800000>; 584 no-map; 585 }; 586 587 pil_camera_mem: pil-camera@95200000 { 588 reg = <0x0 0x95200000 0x0 0x500000>; 589 no-map; 590 }; 591 592 pil_adsp_mem: pil-adsp@95c00000 { 593 reg = <0x0 0x95c00000 0x0 0x1e00000>; 594 no-map; 595 }; 596 597 pil_gdsp0_mem: pil-gdsp0@97b00000 { 598 reg = <0x0 0x97b00000 0x0 0x1e00000>; 599 no-map; 600 }; 601 602 pil_gdsp1_mem: pil-gdsp1@99900000 { 603 reg = <0x0 0x99900000 0x0 0x1e00000>; 604 no-map; 605 }; 606 607 pil_cdsp0_mem: pil-cdsp0@9b800000 { 608 reg = <0x0 0x9b800000 0x0 0x1e00000>; 609 no-map; 610 }; 611 612 pil_gpu_mem: pil-gpu@9d600000 { 613 reg = <0x0 0x9d600000 0x0 0x2000>; 614 no-map; 615 }; 616 617 pil_cdsp1_mem: pil-cdsp1@9d700000 { 618 reg = <0x0 0x9d700000 0x0 0x1e00000>; 619 no-map; 620 }; 621 622 pil_cvp_mem: pil-cvp@9f500000 { 623 reg = <0x0 0x9f500000 0x0 0x700000>; 624 no-map; 625 }; 626 627 pil_video_mem: pil-video@9fc00000 { 628 reg = <0x0 0x9fc00000 0x0 0x700000>; 629 no-map; 630 }; 631 632 audio_mdf_mem: audio-mdf-region@ae000000 { 633 reg = <0x0 0xae000000 0x0 0x1000000>; 634 no-map; 635 }; 636 637 firmware_mem: firmware-region@b0000000 { 638 reg = <0x0 0xb0000000 0x0 0x800000>; 639 no-map; 640 }; 641 642 hyptz_reserved_mem: hyptz-reserved@beb00000 { 643 reg = <0x0 0xbeb00000 0x0 0x11500000>; 644 no-map; 645 }; 646 647 scmi_mem: scmi-region@d0000000 { 648 reg = <0x0 0xd0000000 0x0 0x40000>; 649 no-map; 650 }; 651 652 firmware_logs_mem: firmware-logs@d0040000 { 653 reg = <0x0 0xd0040000 0x0 0x10000>; 654 no-map; 655 }; 656 657 firmware_audio_mem: firmware-audio@d0050000 { 658 reg = <0x0 0xd0050000 0x0 0x4000>; 659 no-map; 660 }; 661 662 firmware_reserved_mem: firmware-reserved@d0054000 { 663 reg = <0x0 0xd0054000 0x0 0x9c000>; 664 no-map; 665 }; 666 667 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { 668 reg = <0x0 0xd00f0000 0x0 0x10000>; 669 no-map; 670 }; 671 672 tags_mem: tags@d0100000 { 673 reg = <0x0 0xd0100000 0x0 0x1200000>; 674 no-map; 675 }; 676 677 qtee_mem: qtee@d1300000 { 678 reg = <0x0 0xd1300000 0x0 0x500000>; 679 no-map; 680 }; 681 682 deepsleep_backup_mem: deepsleep-backup@d1800000 { 683 reg = <0x0 0xd1800000 0x0 0x100000>; 684 no-map; 685 }; 686 687 trusted_apps_mem: trusted-apps@d1900000 { 688 reg = <0x0 0xd1900000 0x0 0x3800000>; 689 no-map; 690 }; 691 692 tz_stat_mem: tz-stat@db100000 { 693 reg = <0x0 0xdb100000 0x0 0x100000>; 694 no-map; 695 }; 696 697 cpucp_fw_mem: cpucp-fw@db200000 { 698 reg = <0x0 0xdb200000 0x0 0x100000>; 699 no-map; 700 }; 701 }; 702 703 smp2p-adsp { 704 compatible = "qcom,smp2p"; 705 qcom,smem = <443>, <429>; 706 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 707 IPCC_MPROC_SIGNAL_SMP2P 708 IRQ_TYPE_EDGE_RISING>; 709 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 710 711 qcom,local-pid = <0>; 712 qcom,remote-pid = <2>; 713 714 smp2p_adsp_out: master-kernel { 715 qcom,entry-name = "master-kernel"; 716 #qcom,smem-state-cells = <1>; 717 }; 718 719 smp2p_adsp_in: slave-kernel { 720 qcom,entry-name = "slave-kernel"; 721 interrupt-controller; 722 #interrupt-cells = <2>; 723 }; 724 }; 725 726 smp2p-cdsp0 { 727 compatible = "qcom,smp2p"; 728 qcom,smem = <94>, <432>; 729 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 730 IPCC_MPROC_SIGNAL_SMP2P 731 IRQ_TYPE_EDGE_RISING>; 732 mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 733 734 qcom,local-pid = <0>; 735 qcom,remote-pid = <5>; 736 737 smp2p_cdsp0_out: master-kernel { 738 qcom,entry-name = "master-kernel"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 smp2p_cdsp0_in: slave-kernel { 743 qcom,entry-name = "slave-kernel"; 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 }; 748 749 smp2p-cdsp1 { 750 compatible = "qcom,smp2p"; 751 qcom,smem = <617>, <616>; 752 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 753 IPCC_MPROC_SIGNAL_SMP2P 754 IRQ_TYPE_EDGE_RISING>; 755 mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; 756 757 qcom,local-pid = <0>; 758 qcom,remote-pid = <12>; 759 760 smp2p_cdsp1_out: master-kernel { 761 qcom,entry-name = "master-kernel"; 762 #qcom,smem-state-cells = <1>; 763 }; 764 765 smp2p_cdsp1_in: slave-kernel { 766 qcom,entry-name = "slave-kernel"; 767 interrupt-controller; 768 #interrupt-cells = <2>; 769 }; 770 }; 771 772 smp2p-gpdsp0 { 773 compatible = "qcom,smp2p"; 774 qcom,smem = <617>, <616>; 775 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 776 IPCC_MPROC_SIGNAL_SMP2P 777 IRQ_TYPE_EDGE_RISING>; 778 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; 779 780 qcom,local-pid = <0>; 781 qcom,remote-pid = <17>; 782 783 smp2p_gpdsp0_out: master-kernel { 784 qcom,entry-name = "master-kernel"; 785 #qcom,smem-state-cells = <1>; 786 }; 787 788 smp2p_gpdsp0_in: slave-kernel { 789 qcom,entry-name = "slave-kernel"; 790 interrupt-controller; 791 #interrupt-cells = <2>; 792 }; 793 }; 794 795 smp2p-gpdsp1 { 796 compatible = "qcom,smp2p"; 797 qcom,smem = <617>, <616>; 798 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 799 IPCC_MPROC_SIGNAL_SMP2P 800 IRQ_TYPE_EDGE_RISING>; 801 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>; 802 803 qcom,local-pid = <0>; 804 qcom,remote-pid = <18>; 805 806 smp2p_gpdsp1_out: master-kernel { 807 qcom,entry-name = "master-kernel"; 808 #qcom,smem-state-cells = <1>; 809 }; 810 811 smp2p_gpdsp1_in: slave-kernel { 812 qcom,entry-name = "slave-kernel"; 813 interrupt-controller; 814 #interrupt-cells = <2>; 815 }; 816 }; 817 818 soc: soc@0 { 819 compatible = "simple-bus"; 820 #address-cells = <2>; 821 #size-cells = <2>; 822 ranges = <0 0 0 0 0x10 0>; 823 824 gcc: clock-controller@100000 { 825 compatible = "qcom,sa8775p-gcc"; 826 reg = <0x0 0x00100000 0x0 0xc7018>; 827 #clock-cells = <1>; 828 #reset-cells = <1>; 829 #power-domain-cells = <1>; 830 clocks = <&rpmhcc RPMH_CXO_CLK>, 831 <&sleep_clk>, 832 <0>, 833 <0>, 834 <0>, 835 <&usb_0_qmpphy>, 836 <&usb_1_qmpphy>, 837 <0>, 838 <0>, 839 <0>, 840 <&pcie0_phy>, 841 <&pcie1_phy>, 842 <0>, 843 <0>, 844 <0>; 845 power-domains = <&rpmhpd SA8775P_CX>; 846 }; 847 848 ipcc: mailbox@408000 { 849 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 850 reg = <0x0 0x00408000 0x0 0x1000>; 851 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 852 interrupt-controller; 853 #interrupt-cells = <3>; 854 #mbox-cells = <2>; 855 }; 856 857 gpi_dma2: qcom,gpi-dma@800000 { 858 compatible = "qcom,sm6350-gpi-dma"; 859 reg = <0x0 0x00800000 0x0 0x60000>; 860 #dma-cells = <3>; 861 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 873 dma-channels = <12>; 874 dma-channel-mask = <0xfff>; 875 iommus = <&apps_smmu 0x5b6 0x0>; 876 status = "disabled"; 877 }; 878 879 qupv3_id_2: geniqup@8c0000 { 880 compatible = "qcom,geni-se-qup"; 881 reg = <0x0 0x008c0000 0x0 0x6000>; 882 ranges; 883 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 884 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 885 clock-names = "m-ahb", "s-ahb"; 886 iommus = <&apps_smmu 0x5a3 0x0>; 887 #address-cells = <2>; 888 #size-cells = <2>; 889 status = "disabled"; 890 891 i2c14: i2c@880000 { 892 compatible = "qcom,geni-i2c"; 893 reg = <0x0 0x880000 0x0 0x4000>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 898 clock-names = "se"; 899 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 900 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 901 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 902 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 903 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 904 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 905 interconnect-names = "qup-core", 906 "qup-config", 907 "qup-memory"; 908 power-domains = <&rpmhpd SA8775P_CX>; 909 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 910 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 911 dma-names = "tx", 912 "rx"; 913 status = "disabled"; 914 }; 915 916 spi14: spi@880000 { 917 compatible = "qcom,geni-spi"; 918 reg = <0x0 0x880000 0x0 0x4000>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 923 clock-names = "se"; 924 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 925 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 926 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 927 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 928 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 929 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 930 interconnect-names = "qup-core", 931 "qup-config", 932 "qup-memory"; 933 power-domains = <&rpmhpd SA8775P_CX>; 934 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 935 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 936 dma-names = "tx", 937 "rx"; 938 status = "disabled"; 939 }; 940 941 uart14: serial@880000 { 942 compatible = "qcom,geni-uart"; 943 reg = <0x0 0x00880000 0x0 0x4000>; 944 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 946 clock-names = "se"; 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 948 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 949 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 950 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 951 interconnect-names = "qup-core", "qup-config"; 952 power-domains = <&rpmhpd SA8775P_CX>; 953 status = "disabled"; 954 }; 955 956 i2c15: i2c@884000 { 957 compatible = "qcom,geni-i2c"; 958 reg = <0x0 0x884000 0x0 0x4000>; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 963 clock-names = "se"; 964 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 965 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 966 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 967 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 968 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 969 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 970 interconnect-names = "qup-core", 971 "qup-config", 972 "qup-memory"; 973 power-domains = <&rpmhpd SA8775P_CX>; 974 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 975 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 976 dma-names = "tx", 977 "rx"; 978 status = "disabled"; 979 }; 980 981 spi15: spi@884000 { 982 compatible = "qcom,geni-spi"; 983 reg = <0x0 0x884000 0x0 0x4000>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 988 clock-names = "se"; 989 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 990 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 992 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 993 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 995 interconnect-names = "qup-core", 996 "qup-config", 997 "qup-memory"; 998 power-domains = <&rpmhpd SA8775P_CX>; 999 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1000 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1001 dma-names = "tx", 1002 "rx"; 1003 status = "disabled"; 1004 }; 1005 1006 uart15: serial@884000 { 1007 compatible = "qcom,geni-uart"; 1008 reg = <0x0 0x00884000 0x0 0x4000>; 1009 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1011 clock-names = "se"; 1012 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1013 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1014 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1015 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1016 interconnect-names = "qup-core", "qup-config"; 1017 power-domains = <&rpmhpd SA8775P_CX>; 1018 status = "disabled"; 1019 }; 1020 1021 i2c16: i2c@888000 { 1022 compatible = "qcom,geni-i2c"; 1023 reg = <0x0 0x888000 0x0 0x4000>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1028 clock-names = "se"; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1030 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1031 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1032 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1033 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1034 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1035 interconnect-names = "qup-core", 1036 "qup-config", 1037 "qup-memory"; 1038 power-domains = <&rpmhpd SA8775P_CX>; 1039 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1040 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1041 dma-names = "tx", 1042 "rx"; 1043 status = "disabled"; 1044 }; 1045 1046 spi16: spi@888000 { 1047 compatible = "qcom,geni-spi"; 1048 reg = <0x0 0x00888000 0x0 0x4000>; 1049 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1051 clock-names = "se"; 1052 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1053 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1054 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1055 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1056 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1057 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1058 interconnect-names = "qup-core", 1059 "qup-config", 1060 "qup-memory"; 1061 power-domains = <&rpmhpd SA8775P_CX>; 1062 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1063 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1064 dma-names = "tx", 1065 "rx"; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 status = "disabled"; 1069 }; 1070 1071 uart16: serial@888000 { 1072 compatible = "qcom,geni-uart"; 1073 reg = <0x0 0x00888000 0x0 0x4000>; 1074 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1076 clock-names = "se"; 1077 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1078 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1079 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1080 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1081 interconnect-names = "qup-core", "qup-config"; 1082 power-domains = <&rpmhpd SA8775P_CX>; 1083 status = "disabled"; 1084 }; 1085 1086 i2c17: i2c@88c000 { 1087 compatible = "qcom,geni-i2c"; 1088 reg = <0x0 0x88c000 0x0 0x4000>; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1093 clock-names = "se"; 1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1095 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1096 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1097 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1098 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1099 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1100 interconnect-names = "qup-core", 1101 "qup-config", 1102 "qup-memory"; 1103 power-domains = <&rpmhpd SA8775P_CX>; 1104 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1105 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1106 dma-names = "tx", 1107 "rx"; 1108 status = "disabled"; 1109 }; 1110 1111 spi17: spi@88c000 { 1112 compatible = "qcom,geni-spi"; 1113 reg = <0x0 0x88c000 0x0 0x4000>; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1118 clock-names = "se"; 1119 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1120 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1121 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1122 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1123 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1124 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1125 interconnect-names = "qup-core", 1126 "qup-config", 1127 "qup-memory"; 1128 power-domains = <&rpmhpd SA8775P_CX>; 1129 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1130 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1131 dma-names = "tx", 1132 "rx"; 1133 status = "disabled"; 1134 }; 1135 1136 uart17: serial@88c000 { 1137 compatible = "qcom,geni-uart"; 1138 reg = <0x0 0x0088c000 0x0 0x4000>; 1139 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1141 clock-names = "se"; 1142 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1143 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1144 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1145 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1146 interconnect-names = "qup-core", "qup-config"; 1147 power-domains = <&rpmhpd SA8775P_CX>; 1148 status = "disabled"; 1149 }; 1150 1151 i2c18: i2c@890000 { 1152 compatible = "qcom,geni-i2c"; 1153 reg = <0x0 0x00890000 0x0 0x4000>; 1154 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1156 clock-names = "se"; 1157 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1158 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1159 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1160 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1161 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1162 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1163 interconnect-names = "qup-core", 1164 "qup-config", 1165 "qup-memory"; 1166 power-domains = <&rpmhpd SA8775P_CX>; 1167 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1168 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1169 dma-names = "tx", 1170 "rx"; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 status = "disabled"; 1174 }; 1175 1176 spi18: spi@890000 { 1177 compatible = "qcom,geni-spi"; 1178 reg = <0x0 0x890000 0x0 0x4000>; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1183 clock-names = "se"; 1184 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1185 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1186 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1187 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1188 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1189 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1190 interconnect-names = "qup-core", 1191 "qup-config", 1192 "qup-memory"; 1193 power-domains = <&rpmhpd SA8775P_CX>; 1194 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1195 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1196 dma-names = "tx", 1197 "rx"; 1198 status = "disabled"; 1199 }; 1200 1201 uart18: serial@890000 { 1202 compatible = "qcom,geni-uart"; 1203 reg = <0x0 0x00890000 0x0 0x4000>; 1204 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1205 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1206 clock-names = "se"; 1207 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1208 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1209 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1210 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1211 interconnect-names = "qup-core", "qup-config"; 1212 power-domains = <&rpmhpd SA8775P_CX>; 1213 status = "disabled"; 1214 }; 1215 1216 i2c19: i2c@894000 { 1217 compatible = "qcom,geni-i2c"; 1218 reg = <0x0 0x894000 0x0 0x4000>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1223 clock-names = "se"; 1224 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1225 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1226 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1227 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1228 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1229 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1230 interconnect-names = "qup-core", 1231 "qup-config", 1232 "qup-memory"; 1233 power-domains = <&rpmhpd SA8775P_CX>; 1234 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1235 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1236 dma-names = "tx", 1237 "rx"; 1238 status = "disabled"; 1239 }; 1240 1241 spi19: spi@894000 { 1242 compatible = "qcom,geni-spi"; 1243 reg = <0x0 0x894000 0x0 0x4000>; 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1248 clock-names = "se"; 1249 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1250 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1251 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1252 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1253 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1254 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1255 interconnect-names = "qup-core", 1256 "qup-config", 1257 "qup-memory"; 1258 power-domains = <&rpmhpd SA8775P_CX>; 1259 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1260 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1261 dma-names = "tx", 1262 "rx"; 1263 status = "disabled"; 1264 }; 1265 1266 uart19: serial@894000 { 1267 compatible = "qcom,geni-uart"; 1268 reg = <0x0 0x00894000 0x0 0x4000>; 1269 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1270 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1271 clock-names = "se"; 1272 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1273 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1274 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1275 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1276 interconnect-names = "qup-core", "qup-config"; 1277 power-domains = <&rpmhpd SA8775P_CX>; 1278 status = "disabled"; 1279 }; 1280 1281 i2c20: i2c@898000 { 1282 compatible = "qcom,geni-i2c"; 1283 reg = <0x0 0x898000 0x0 0x4000>; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1288 clock-names = "se"; 1289 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1290 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1291 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1292 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1293 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1294 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1295 interconnect-names = "qup-core", 1296 "qup-config", 1297 "qup-memory"; 1298 power-domains = <&rpmhpd SA8775P_CX>; 1299 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1300 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1301 dma-names = "tx", 1302 "rx"; 1303 status = "disabled"; 1304 }; 1305 1306 spi20: spi@898000 { 1307 compatible = "qcom,geni-spi"; 1308 reg = <0x0 0x898000 0x0 0x4000>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1312 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1313 clock-names = "se"; 1314 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1315 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1316 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1317 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1318 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1319 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1320 interconnect-names = "qup-core", 1321 "qup-config", 1322 "qup-memory"; 1323 power-domains = <&rpmhpd SA8775P_CX>; 1324 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1325 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1326 dma-names = "tx", 1327 "rx"; 1328 status = "disabled"; 1329 }; 1330 1331 uart20: serial@898000 { 1332 compatible = "qcom,geni-uart"; 1333 reg = <0x0 0x00898000 0x0 0x4000>; 1334 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1335 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1336 clock-names = "se"; 1337 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1338 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1339 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1340 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1341 interconnect-names = "qup-core", "qup-config"; 1342 power-domains = <&rpmhpd SA8775P_CX>; 1343 status = "disabled"; 1344 }; 1345 1346 }; 1347 1348 gpi_dma0: qcom,gpi-dma@900000 { 1349 compatible = "qcom,sm6350-gpi-dma"; 1350 reg = <0x0 0x00900000 0x0 0x60000>; 1351 #dma-cells = <3>; 1352 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1364 dma-channels = <12>; 1365 dma-channel-mask = <0xfff>; 1366 iommus = <&apps_smmu 0x416 0x0>; 1367 status = "disabled"; 1368 }; 1369 1370 qupv3_id_0: geniqup@9c0000 { 1371 compatible = "qcom,geni-se-qup"; 1372 reg = <0x0 0x9c0000 0x0 0x6000>; 1373 #address-cells = <2>; 1374 #size-cells = <2>; 1375 ranges; 1376 clock-names = "m-ahb", "s-ahb"; 1377 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1378 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1379 iommus = <&apps_smmu 0x403 0x0>; 1380 status = "disabled"; 1381 1382 i2c0: i2c@980000 { 1383 compatible = "qcom,geni-i2c"; 1384 reg = <0x0 0x980000 0x0 0x4000>; 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1388 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1389 clock-names = "se"; 1390 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1391 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1392 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1393 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1394 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1395 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1396 interconnect-names = "qup-core", 1397 "qup-config", 1398 "qup-memory"; 1399 power-domains = <&rpmhpd SA8775P_CX>; 1400 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1401 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1402 dma-names = "tx", 1403 "rx"; 1404 status = "disabled"; 1405 }; 1406 1407 spi0: spi@980000 { 1408 compatible = "qcom,geni-spi"; 1409 reg = <0x0 0x980000 0x0 0x4000>; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1413 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1414 clock-names = "se"; 1415 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1416 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1417 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1418 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1419 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1420 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1421 interconnect-names = "qup-core", 1422 "qup-config", 1423 "qup-memory"; 1424 power-domains = <&rpmhpd SA8775P_CX>; 1425 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1426 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1427 dma-names = "tx", 1428 "rx"; 1429 status = "disabled"; 1430 }; 1431 1432 uart0: serial@980000 { 1433 compatible = "qcom,geni-uart"; 1434 reg = <0x0 0x980000 0x0 0x4000>; 1435 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1436 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1437 clock-names = "se"; 1438 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1439 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1440 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1441 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1442 interconnect-names = "qup-core", "qup-config"; 1443 power-domains = <&rpmhpd SA8775P_CX>; 1444 status = "disabled"; 1445 }; 1446 1447 i2c1: i2c@984000 { 1448 compatible = "qcom,geni-i2c"; 1449 reg = <0x0 0x984000 0x0 0x4000>; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1453 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1454 clock-names = "se"; 1455 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1456 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1457 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1458 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1459 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1460 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1461 interconnect-names = "qup-core", 1462 "qup-config", 1463 "qup-memory"; 1464 power-domains = <&rpmhpd SA8775P_CX>; 1465 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1466 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1467 dma-names = "tx", 1468 "rx"; 1469 status = "disabled"; 1470 }; 1471 1472 spi1: spi@984000 { 1473 compatible = "qcom,geni-spi"; 1474 reg = <0x0 0x984000 0x0 0x4000>; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1478 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1479 clock-names = "se"; 1480 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1481 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1482 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1483 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1484 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1485 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1486 interconnect-names = "qup-core", 1487 "qup-config", 1488 "qup-memory"; 1489 power-domains = <&rpmhpd SA8775P_CX>; 1490 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1491 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1492 dma-names = "tx", 1493 "rx"; 1494 status = "disabled"; 1495 }; 1496 1497 uart1: serial@984000 { 1498 compatible = "qcom,geni-uart"; 1499 reg = <0x0 0x984000 0x0 0x4000>; 1500 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1501 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1502 clock-names = "se"; 1503 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1504 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1505 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1506 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1507 interconnect-names = "qup-core", "qup-config"; 1508 power-domains = <&rpmhpd SA8775P_CX>; 1509 status = "disabled"; 1510 }; 1511 1512 i2c2: i2c@988000 { 1513 compatible = "qcom,geni-i2c"; 1514 reg = <0x0 0x988000 0x0 0x4000>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1518 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1519 clock-names = "se"; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1521 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1522 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1523 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1524 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1525 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1526 interconnect-names = "qup-core", 1527 "qup-config", 1528 "qup-memory"; 1529 power-domains = <&rpmhpd SA8775P_CX>; 1530 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1531 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1532 dma-names = "tx", 1533 "rx"; 1534 status = "disabled"; 1535 }; 1536 1537 spi2: spi@988000 { 1538 compatible = "qcom,geni-spi"; 1539 reg = <0x0 0x988000 0x0 0x4000>; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1543 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1544 clock-names = "se"; 1545 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1546 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1547 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1548 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1549 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1550 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1551 interconnect-names = "qup-core", 1552 "qup-config", 1553 "qup-memory"; 1554 power-domains = <&rpmhpd SA8775P_CX>; 1555 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1556 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1557 dma-names = "tx", 1558 "rx"; 1559 status = "disabled"; 1560 }; 1561 1562 uart2: serial@988000 { 1563 compatible = "qcom,geni-uart"; 1564 reg = <0x0 0x988000 0x0 0x4000>; 1565 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1566 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1567 clock-names = "se"; 1568 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1569 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1570 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1571 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1572 interconnect-names = "qup-core", "qup-config"; 1573 power-domains = <&rpmhpd SA8775P_CX>; 1574 status = "disabled"; 1575 }; 1576 1577 i2c3: i2c@98c000 { 1578 compatible = "qcom,geni-i2c"; 1579 reg = <0x0 0x98c000 0x0 0x4000>; 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1583 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1584 clock-names = "se"; 1585 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1586 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1587 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1588 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1589 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1590 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1591 interconnect-names = "qup-core", 1592 "qup-config", 1593 "qup-memory"; 1594 power-domains = <&rpmhpd SA8775P_CX>; 1595 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1596 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1597 dma-names = "tx", 1598 "rx"; 1599 status = "disabled"; 1600 }; 1601 1602 spi3: spi@98c000 { 1603 compatible = "qcom,geni-spi"; 1604 reg = <0x0 0x98c000 0x0 0x4000>; 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1608 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1609 clock-names = "se"; 1610 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1611 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1612 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1613 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1614 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1615 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1616 interconnect-names = "qup-core", 1617 "qup-config", 1618 "qup-memory"; 1619 power-domains = <&rpmhpd SA8775P_CX>; 1620 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1621 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1622 dma-names = "tx", 1623 "rx"; 1624 status = "disabled"; 1625 }; 1626 1627 uart3: serial@98c000 { 1628 compatible = "qcom,geni-uart"; 1629 reg = <0x0 0x98c000 0x0 0x4000>; 1630 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1631 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1632 clock-names = "se"; 1633 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1634 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1635 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1636 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1637 interconnect-names = "qup-core", "qup-config"; 1638 power-domains = <&rpmhpd SA8775P_CX>; 1639 status = "disabled"; 1640 }; 1641 1642 i2c4: i2c@990000 { 1643 compatible = "qcom,geni-i2c"; 1644 reg = <0x0 0x990000 0x0 0x4000>; 1645 #address-cells = <1>; 1646 #size-cells = <0>; 1647 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1648 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1649 clock-names = "se"; 1650 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1651 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1652 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1653 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1654 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1655 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1656 interconnect-names = "qup-core", 1657 "qup-config", 1658 "qup-memory"; 1659 power-domains = <&rpmhpd SA8775P_CX>; 1660 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1661 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1662 dma-names = "tx", 1663 "rx"; 1664 status = "disabled"; 1665 }; 1666 1667 spi4: spi@990000 { 1668 compatible = "qcom,geni-spi"; 1669 reg = <0x0 0x990000 0x0 0x4000>; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1673 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1674 clock-names = "se"; 1675 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1676 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1677 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1678 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1679 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1680 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1681 interconnect-names = "qup-core", 1682 "qup-config", 1683 "qup-memory"; 1684 power-domains = <&rpmhpd SA8775P_CX>; 1685 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1686 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1687 dma-names = "tx", 1688 "rx"; 1689 status = "disabled"; 1690 }; 1691 1692 uart4: serial@990000 { 1693 compatible = "qcom,geni-uart"; 1694 reg = <0x0 0x990000 0x0 0x4000>; 1695 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1696 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1697 clock-names = "se"; 1698 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1699 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1700 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1701 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1702 interconnect-names = "qup-core", "qup-config"; 1703 power-domains = <&rpmhpd SA8775P_CX>; 1704 status = "disabled"; 1705 }; 1706 1707 i2c5: i2c@994000 { 1708 compatible = "qcom,geni-i2c"; 1709 reg = <0x0 0x994000 0x0 0x4000>; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1713 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1714 clock-names = "se"; 1715 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1716 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1717 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1718 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1719 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1720 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1721 interconnect-names = "qup-core", 1722 "qup-config", 1723 "qup-memory"; 1724 power-domains = <&rpmhpd SA8775P_CX>; 1725 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1726 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1727 dma-names = "tx", 1728 "rx"; 1729 status = "disabled"; 1730 }; 1731 1732 spi5: spi@994000 { 1733 compatible = "qcom,geni-spi"; 1734 reg = <0x0 0x994000 0x0 0x4000>; 1735 #address-cells = <1>; 1736 #size-cells = <0>; 1737 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1738 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1739 clock-names = "se"; 1740 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1741 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1742 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1743 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1744 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1745 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1746 interconnect-names = "qup-core", 1747 "qup-config", 1748 "qup-memory"; 1749 power-domains = <&rpmhpd SA8775P_CX>; 1750 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1751 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1752 dma-names = "tx", 1753 "rx"; 1754 status = "disabled"; 1755 }; 1756 1757 uart5: serial@994000 { 1758 compatible = "qcom,geni-uart"; 1759 reg = <0x0 0x994000 0x0 0x4000>; 1760 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1761 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1762 clock-names = "se"; 1763 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1764 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1765 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1766 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1767 interconnect-names = "qup-core", "qup-config"; 1768 power-domains = <&rpmhpd SA8775P_CX>; 1769 status = "disabled"; 1770 }; 1771 }; 1772 1773 gpi_dma1: qcom,gpi-dma@a00000 { 1774 compatible = "qcom,sm6350-gpi-dma"; 1775 reg = <0x0 0x00a00000 0x0 0x60000>; 1776 #dma-cells = <3>; 1777 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1789 iommus = <&apps_smmu 0x456 0x0>; 1790 dma-channels = <12>; 1791 dma-channel-mask = <0xfff>; 1792 status = "disabled"; 1793 }; 1794 1795 qupv3_id_1: geniqup@ac0000 { 1796 compatible = "qcom,geni-se-qup"; 1797 reg = <0x0 0x00ac0000 0x0 0x6000>; 1798 #address-cells = <2>; 1799 #size-cells = <2>; 1800 ranges; 1801 clock-names = "m-ahb", "s-ahb"; 1802 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1803 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1804 iommus = <&apps_smmu 0x443 0x0>; 1805 status = "disabled"; 1806 1807 i2c7: i2c@a80000 { 1808 compatible = "qcom,geni-i2c"; 1809 reg = <0x0 0xa80000 0x0 0x4000>; 1810 #address-cells = <1>; 1811 #size-cells = <0>; 1812 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1813 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1814 clock-names = "se"; 1815 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1816 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1817 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1818 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1819 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1820 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1821 interconnect-names = "qup-core", 1822 "qup-config", 1823 "qup-memory"; 1824 power-domains = <&rpmhpd SA8775P_CX>; 1825 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1826 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1827 dma-names = "tx", 1828 "rx"; 1829 status = "disabled"; 1830 }; 1831 1832 spi7: spi@a80000 { 1833 compatible = "qcom,geni-spi"; 1834 reg = <0x0 0xa80000 0x0 0x4000>; 1835 #address-cells = <1>; 1836 #size-cells = <0>; 1837 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1838 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1839 clock-names = "se"; 1840 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1841 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1842 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1843 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1844 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1845 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1846 interconnect-names = "qup-core", 1847 "qup-config", 1848 "qup-memory"; 1849 power-domains = <&rpmhpd SA8775P_CX>; 1850 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1851 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1852 dma-names = "tx", 1853 "rx"; 1854 status = "disabled"; 1855 }; 1856 1857 uart7: serial@a80000 { 1858 compatible = "qcom,geni-uart"; 1859 reg = <0x0 0x00a80000 0x0 0x4000>; 1860 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1861 clock-names = "se"; 1862 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1863 interconnect-names = "qup-core", "qup-config"; 1864 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1865 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1866 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1867 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1868 power-domains = <&rpmhpd SA8775P_CX>; 1869 operating-points-v2 = <&qup_opp_table_100mhz>; 1870 status = "disabled"; 1871 }; 1872 1873 i2c8: i2c@a84000 { 1874 compatible = "qcom,geni-i2c"; 1875 reg = <0x0 0xa84000 0x0 0x4000>; 1876 #address-cells = <1>; 1877 #size-cells = <0>; 1878 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1879 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1880 clock-names = "se"; 1881 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1882 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1883 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1884 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1885 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1886 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1887 interconnect-names = "qup-core", 1888 "qup-config", 1889 "qup-memory"; 1890 power-domains = <&rpmhpd SA8775P_CX>; 1891 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1892 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1893 dma-names = "tx", 1894 "rx"; 1895 status = "disabled"; 1896 }; 1897 1898 spi8: spi@a84000 { 1899 compatible = "qcom,geni-spi"; 1900 reg = <0x0 0xa84000 0x0 0x4000>; 1901 #address-cells = <1>; 1902 #size-cells = <0>; 1903 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1905 clock-names = "se"; 1906 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1907 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1908 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1909 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1910 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1911 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1912 interconnect-names = "qup-core", 1913 "qup-config", 1914 "qup-memory"; 1915 power-domains = <&rpmhpd SA8775P_CX>; 1916 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1917 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1918 dma-names = "tx", 1919 "rx"; 1920 status = "disabled"; 1921 }; 1922 1923 uart8: serial@a84000 { 1924 compatible = "qcom,geni-uart"; 1925 reg = <0x0 0x00a84000 0x0 0x4000>; 1926 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1927 clock-names = "se"; 1928 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1929 interconnect-names = "qup-core", "qup-config"; 1930 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1931 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1932 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1933 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1934 power-domains = <&rpmhpd SA8775P_CX>; 1935 operating-points-v2 = <&qup_opp_table_100mhz>; 1936 status = "disabled"; 1937 }; 1938 1939 i2c9: i2c@a88000 { 1940 compatible = "qcom,geni-i2c"; 1941 reg = <0x0 0xa88000 0x0 0x4000>; 1942 #address-cells = <1>; 1943 #size-cells = <0>; 1944 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1945 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1946 clock-names = "se"; 1947 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1948 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1949 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1950 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1951 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1953 interconnect-names = "qup-core", 1954 "qup-config", 1955 "qup-memory"; 1956 power-domains = <&rpmhpd SA8775P_CX>; 1957 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1958 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1959 dma-names = "tx", 1960 "rx"; 1961 status = "disabled"; 1962 }; 1963 1964 spi9: spi@a88000 { 1965 compatible = "qcom,geni-spi"; 1966 reg = <0x0 0xa88000 0x0 0x4000>; 1967 #address-cells = <1>; 1968 #size-cells = <0>; 1969 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1970 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1971 clock-names = "se"; 1972 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1973 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1974 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1975 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1976 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1977 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1978 interconnect-names = "qup-core", 1979 "qup-config", 1980 "qup-memory"; 1981 power-domains = <&rpmhpd SA8775P_CX>; 1982 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1983 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1984 dma-names = "tx", 1985 "rx"; 1986 status = "disabled"; 1987 }; 1988 1989 uart9: serial@a88000 { 1990 compatible = "qcom,geni-uart"; 1991 reg = <0x0 0xa88000 0x0 0x4000>; 1992 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1993 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1994 clock-names = "se"; 1995 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1996 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1997 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1998 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1999 interconnect-names = "qup-core", "qup-config"; 2000 power-domains = <&rpmhpd SA8775P_CX>; 2001 status = "disabled"; 2002 }; 2003 2004 i2c10: i2c@a8c000 { 2005 compatible = "qcom,geni-i2c"; 2006 reg = <0x0 0xa8c000 0x0 0x4000>; 2007 #address-cells = <1>; 2008 #size-cells = <0>; 2009 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2010 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2011 clock-names = "se"; 2012 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2013 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2014 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2015 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2016 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2017 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2018 interconnect-names = "qup-core", 2019 "qup-config", 2020 "qup-memory"; 2021 power-domains = <&rpmhpd SA8775P_CX>; 2022 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 2023 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 2024 dma-names = "tx", 2025 "rx"; 2026 status = "disabled"; 2027 }; 2028 2029 spi10: spi@a8c000 { 2030 compatible = "qcom,geni-spi"; 2031 reg = <0x0 0xa8c000 0x0 0x4000>; 2032 #address-cells = <1>; 2033 #size-cells = <0>; 2034 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2035 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2036 clock-names = "se"; 2037 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2038 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2039 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2040 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2041 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2042 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2043 interconnect-names = "qup-core", 2044 "qup-config", 2045 "qup-memory"; 2046 power-domains = <&rpmhpd SA8775P_CX>; 2047 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 2048 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 2049 dma-names = "tx", 2050 "rx"; 2051 status = "disabled"; 2052 }; 2053 2054 uart10: serial@a8c000 { 2055 compatible = "qcom,geni-uart"; 2056 reg = <0x0 0x00a8c000 0x0 0x4000>; 2057 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2058 clock-names = "se"; 2059 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2060 interconnect-names = "qup-core", "qup-config"; 2061 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 2062 &clk_virt SLAVE_QUP_CORE_1 0>, 2063 <&gem_noc MASTER_APPSS_PROC 0 2064 &config_noc SLAVE_QUP_1 0>; 2065 power-domains = <&rpmhpd SA8775P_CX>; 2066 operating-points-v2 = <&qup_opp_table_100mhz>; 2067 status = "disabled"; 2068 }; 2069 2070 i2c11: i2c@a90000 { 2071 compatible = "qcom,geni-i2c"; 2072 reg = <0x0 0xa90000 0x0 0x4000>; 2073 #address-cells = <1>; 2074 #size-cells = <0>; 2075 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2076 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2077 clock-names = "se"; 2078 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2079 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2080 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2081 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2082 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2083 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2084 interconnect-names = "qup-core", 2085 "qup-config", 2086 "qup-memory"; 2087 power-domains = <&rpmhpd SA8775P_CX>; 2088 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2089 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2090 dma-names = "tx", 2091 "rx"; 2092 status = "disabled"; 2093 }; 2094 2095 spi11: spi@a90000 { 2096 compatible = "qcom,geni-spi"; 2097 reg = <0x0 0xa90000 0x0 0x4000>; 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2101 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2102 clock-names = "se"; 2103 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2104 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2105 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2106 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2107 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2108 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2109 interconnect-names = "qup-core", 2110 "qup-config", 2111 "qup-memory"; 2112 power-domains = <&rpmhpd SA8775P_CX>; 2113 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2114 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2115 dma-names = "tx", 2116 "rx"; 2117 status = "disabled"; 2118 }; 2119 2120 uart11: serial@a90000 { 2121 compatible = "qcom,geni-uart"; 2122 reg = <0x0 0x00a90000 0x0 0x4000>; 2123 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2124 clock-names = "se"; 2125 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2126 interconnect-names = "qup-core", "qup-config"; 2127 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2128 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2129 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2130 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2131 power-domains = <&rpmhpd SA8775P_CX>; 2132 operating-points-v2 = <&qup_opp_table_100mhz>; 2133 status = "disabled"; 2134 }; 2135 2136 i2c12: i2c@a94000 { 2137 compatible = "qcom,geni-i2c"; 2138 reg = <0x0 0xa94000 0x0 0x4000>; 2139 #address-cells = <1>; 2140 #size-cells = <0>; 2141 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2142 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2143 clock-names = "se"; 2144 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2145 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2146 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2147 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2148 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2149 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2150 interconnect-names = "qup-core", 2151 "qup-config", 2152 "qup-memory"; 2153 power-domains = <&rpmhpd SA8775P_CX>; 2154 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2155 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2156 dma-names = "tx", 2157 "rx"; 2158 status = "disabled"; 2159 }; 2160 2161 spi12: spi@a94000 { 2162 compatible = "qcom,geni-spi"; 2163 reg = <0x0 0xa94000 0x0 0x4000>; 2164 #address-cells = <1>; 2165 #size-cells = <0>; 2166 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2167 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2168 clock-names = "se"; 2169 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2170 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2171 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2172 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2173 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2174 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2175 interconnect-names = "qup-core", 2176 "qup-config", 2177 "qup-memory"; 2178 power-domains = <&rpmhpd SA8775P_CX>; 2179 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2180 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2181 dma-names = "tx", 2182 "rx"; 2183 status = "disabled"; 2184 }; 2185 2186 uart12: serial@a94000 { 2187 compatible = "qcom,geni-uart"; 2188 reg = <0x0 0x00a94000 0x0 0x4000>; 2189 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2190 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2191 clock-names = "se"; 2192 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2193 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2194 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2195 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2196 interconnect-names = "qup-core", "qup-config"; 2197 power-domains = <&rpmhpd SA8775P_CX>; 2198 status = "disabled"; 2199 }; 2200 2201 i2c13: i2c@a98000 { 2202 compatible = "qcom,geni-i2c"; 2203 reg = <0x0 0xa98000 0x0 0x4000>; 2204 #address-cells = <1>; 2205 #size-cells = <0>; 2206 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2207 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2208 clock-names = "se"; 2209 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2210 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2211 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2212 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2213 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2214 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2215 interconnect-names = "qup-core", 2216 "qup-config", 2217 "qup-memory"; 2218 power-domains = <&rpmhpd SA8775P_CX>; 2219 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2220 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2221 dma-names = "tx", 2222 "rx"; 2223 status = "disabled"; 2224 2225 }; 2226 }; 2227 2228 gpi_dma3: qcom,gpi-dma@b00000 { 2229 compatible = "qcom,sm6350-gpi-dma"; 2230 reg = <0x0 0x00b00000 0x0 0x58000>; 2231 #dma-cells = <3>; 2232 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2236 iommus = <&apps_smmu 0x056 0x0>; 2237 dma-channels = <4>; 2238 dma-channel-mask = <0xf>; 2239 status = "disabled"; 2240 }; 2241 2242 qupv3_id_3: geniqup@bc0000 { 2243 compatible = "qcom,geni-se-qup"; 2244 reg = <0x0 0xbc0000 0x0 0x6000>; 2245 #address-cells = <2>; 2246 #size-cells = <2>; 2247 ranges; 2248 clock-names = "m-ahb", "s-ahb"; 2249 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2250 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2251 iommus = <&apps_smmu 0x43 0x0>; 2252 status = "disabled"; 2253 2254 i2c21: i2c@b80000 { 2255 compatible = "qcom,geni-i2c"; 2256 reg = <0x0 0xb80000 0x0 0x4000>; 2257 #address-cells = <1>; 2258 #size-cells = <0>; 2259 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2260 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2261 clock-names = "se"; 2262 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2263 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2264 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2265 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2266 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2267 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2268 interconnect-names = "qup-core", 2269 "qup-config", 2270 "qup-memory"; 2271 power-domains = <&rpmhpd SA8775P_CX>; 2272 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2273 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2274 dma-names = "tx", 2275 "rx"; 2276 status = "disabled"; 2277 }; 2278 2279 spi21: spi@b80000 { 2280 compatible = "qcom,geni-spi"; 2281 reg = <0x0 0xb80000 0x0 0x4000>; 2282 #address-cells = <1>; 2283 #size-cells = <0>; 2284 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2285 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2286 clock-names = "se"; 2287 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2288 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2289 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2290 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2291 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2292 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2293 interconnect-names = "qup-core", 2294 "qup-config", 2295 "qup-memory"; 2296 power-domains = <&rpmhpd SA8775P_CX>; 2297 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2298 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2299 dma-names = "tx", 2300 "rx"; 2301 status = "disabled"; 2302 }; 2303 2304 uart21: serial@b80000 { 2305 compatible = "qcom,geni-uart"; 2306 reg = <0x0 0x00b80000 0x0 0x4000>; 2307 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2308 clock-names = "se"; 2309 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2310 interconnect-names = "qup-core", "qup-config"; 2311 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2312 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2313 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2314 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2315 power-domains = <&rpmhpd SA8775P_CX>; 2316 operating-points-v2 = <&qup_opp_table_100mhz>; 2317 status = "disabled"; 2318 }; 2319 }; 2320 2321 rng: rng@10d2000 { 2322 compatible = "qcom,sa8775p-trng", "qcom,trng"; 2323 reg = <0 0x010d2000 0 0x1000>; 2324 }; 2325 2326 ufs_mem_hc: ufshc@1d84000 { 2327 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2328 reg = <0x0 0x01d84000 0x0 0x3000>; 2329 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2330 phys = <&ufs_mem_phy>; 2331 phy-names = "ufsphy"; 2332 lanes-per-direction = <2>; 2333 #reset-cells = <1>; 2334 resets = <&gcc GCC_UFS_PHY_BCR>; 2335 reset-names = "rst"; 2336 power-domains = <&gcc UFS_PHY_GDSC>; 2337 required-opps = <&rpmhpd_opp_nom>; 2338 iommus = <&apps_smmu 0x100 0x0>; 2339 dma-coherent; 2340 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2341 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2342 <&gcc GCC_UFS_PHY_AHB_CLK>, 2343 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2344 <&rpmhcc RPMH_CXO_CLK>, 2345 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2346 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2347 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2348 clock-names = "core_clk", 2349 "bus_aggr_clk", 2350 "iface_clk", 2351 "core_clk_unipro", 2352 "ref_clk", 2353 "tx_lane0_sync_clk", 2354 "rx_lane0_sync_clk", 2355 "rx_lane1_sync_clk"; 2356 freq-table-hz = <75000000 300000000>, 2357 <0 0>, 2358 <0 0>, 2359 <75000000 300000000>, 2360 <0 0>, 2361 <0 0>, 2362 <0 0>, 2363 <0 0>; 2364 qcom,ice = <&ice>; 2365 status = "disabled"; 2366 }; 2367 2368 ufs_mem_phy: phy@1d87000 { 2369 compatible = "qcom,sa8775p-qmp-ufs-phy"; 2370 reg = <0x0 0x01d87000 0x0 0xe10>; 2371 /* 2372 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2373 * enables the CXO clock to eDP *and* UFS PHY. 2374 */ 2375 clocks = <&rpmhcc RPMH_CXO_CLK>, 2376 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2377 <&gcc GCC_EDP_REF_CLKREF_EN>; 2378 clock-names = "ref", "ref_aux", "qref"; 2379 power-domains = <&gcc UFS_PHY_GDSC>; 2380 resets = <&ufs_mem_hc 0>; 2381 reset-names = "ufsphy"; 2382 #phy-cells = <0>; 2383 status = "disabled"; 2384 }; 2385 2386 ice: crypto@1d88000 { 2387 compatible = "qcom,sa8775p-inline-crypto-engine", 2388 "qcom,inline-crypto-engine"; 2389 reg = <0x0 0x01d88000 0x0 0x18000>; 2390 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2391 }; 2392 2393 cryptobam: dma-controller@1dc4000 { 2394 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2395 reg = <0x0 0x01dc4000 0x0 0x28000>; 2396 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2397 #dma-cells = <1>; 2398 qcom,ee = <0>; 2399 qcom,controlled-remotely; 2400 iommus = <&apps_smmu 0x480 0x00>, 2401 <&apps_smmu 0x481 0x00>; 2402 }; 2403 2404 crypto: crypto@1dfa000 { 2405 compatible = "qcom,sa8775p-qce", "qcom,qce"; 2406 reg = <0x0 0x01dfa000 0x0 0x6000>; 2407 dmas = <&cryptobam 4>, <&cryptobam 5>; 2408 dma-names = "rx", "tx"; 2409 iommus = <&apps_smmu 0x480 0x00>, 2410 <&apps_smmu 0x481 0x00>; 2411 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 0 &mc_virt SLAVE_EBI1 0>; 2412 interconnect-names = "memory"; 2413 }; 2414 2415 stm: stm@4002000 { 2416 compatible = "arm,coresight-stm", "arm,primecell"; 2417 reg = <0x0 0x4002000 0x0 0x1000>, 2418 <0x0 0x16280000 0x0 0x180000>; 2419 reg-names = "stm-base", "stm-stimulus-base"; 2420 2421 clocks = <&aoss_qmp>; 2422 clock-names = "apb_pclk"; 2423 2424 out-ports { 2425 port { 2426 stm_out: endpoint { 2427 remote-endpoint = 2428 <&funnel0_in7>; 2429 }; 2430 }; 2431 }; 2432 }; 2433 2434 tpdm@4003000 { 2435 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2436 reg = <0x0 0x4003000 0x0 0x1000>; 2437 2438 clocks = <&aoss_qmp>; 2439 clock-names = "apb_pclk"; 2440 2441 qcom,cmb-element-bits = <32>; 2442 qcom,cmb-msrs-num = <32>; 2443 2444 out-ports { 2445 port { 2446 qdss_tpdm0_out: endpoint { 2447 remote-endpoint = 2448 <&qdss_tpda_in0>; 2449 }; 2450 }; 2451 }; 2452 }; 2453 2454 tpda@4004000 { 2455 compatible = "qcom,coresight-tpda", "arm,primecell"; 2456 reg = <0x0 0x4004000 0x0 0x1000>; 2457 2458 clocks = <&aoss_qmp>; 2459 clock-names = "apb_pclk"; 2460 2461 out-ports { 2462 port { 2463 qdss_tpda_out: endpoint { 2464 remote-endpoint = 2465 <&funnel0_in6>; 2466 }; 2467 }; 2468 }; 2469 2470 in-ports { 2471 #address-cells = <1>; 2472 #size-cells = <0>; 2473 2474 port@0 { 2475 reg = <0>; 2476 qdss_tpda_in0: endpoint { 2477 remote-endpoint = 2478 <&qdss_tpdm0_out>; 2479 }; 2480 }; 2481 2482 port@1 { 2483 reg = <1>; 2484 qdss_tpda_in1: endpoint { 2485 remote-endpoint = 2486 <&qdss_tpdm1_out>; 2487 }; 2488 }; 2489 }; 2490 }; 2491 2492 tpdm@400f000 { 2493 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2494 reg = <0x0 0x400f000 0x0 0x1000>; 2495 2496 clocks = <&aoss_qmp>; 2497 clock-names = "apb_pclk"; 2498 2499 qcom,cmb-element-bits = <32>; 2500 qcom,cmb-msrs-num = <32>; 2501 2502 out-ports { 2503 port { 2504 qdss_tpdm1_out: endpoint { 2505 remote-endpoint = 2506 <&qdss_tpda_in1>; 2507 }; 2508 }; 2509 }; 2510 }; 2511 2512 funnel@4041000 { 2513 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2514 reg = <0x0 0x4041000 0x0 0x1000>; 2515 2516 clocks = <&aoss_qmp>; 2517 clock-names = "apb_pclk"; 2518 2519 out-ports { 2520 port { 2521 funnel0_out: endpoint { 2522 remote-endpoint = 2523 <&qdss_funnel_in0>; 2524 }; 2525 }; 2526 }; 2527 2528 in-ports { 2529 #address-cells = <1>; 2530 #size-cells = <0>; 2531 2532 port@6 { 2533 reg = <6>; 2534 funnel0_in6: endpoint { 2535 remote-endpoint = 2536 <&qdss_tpda_out>; 2537 }; 2538 }; 2539 2540 port@7 { 2541 reg = <7>; 2542 funnel0_in7: endpoint { 2543 remote-endpoint = 2544 <&stm_out>; 2545 }; 2546 }; 2547 }; 2548 }; 2549 2550 funnel@4042000 { 2551 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2552 reg = <0x0 0x4042000 0x0 0x1000>; 2553 2554 clocks = <&aoss_qmp>; 2555 clock-names = "apb_pclk"; 2556 2557 out-ports { 2558 port { 2559 funnel1_out: endpoint { 2560 remote-endpoint = 2561 <&qdss_funnel_in1>; 2562 }; 2563 }; 2564 }; 2565 2566 in-ports { 2567 #address-cells = <1>; 2568 #size-cells = <0>; 2569 2570 port@4 { 2571 reg = <4>; 2572 funnel1_in4: endpoint { 2573 remote-endpoint = 2574 <&apss_funnel1_out>; 2575 }; 2576 }; 2577 }; 2578 }; 2579 2580 funnel@4045000 { 2581 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2582 reg = <0x0 0x4045000 0x0 0x1000>; 2583 2584 clocks = <&aoss_qmp>; 2585 clock-names = "apb_pclk"; 2586 2587 out-ports { 2588 port { 2589 qdss_funnel_out: endpoint { 2590 remote-endpoint = 2591 <&aoss_funnel_in7>; 2592 }; 2593 }; 2594 }; 2595 2596 in-ports { 2597 #address-cells = <1>; 2598 #size-cells = <0>; 2599 2600 port@0 { 2601 reg = <0>; 2602 qdss_funnel_in0: endpoint { 2603 remote-endpoint = 2604 <&funnel0_out>; 2605 }; 2606 }; 2607 2608 port@1 { 2609 reg = <1>; 2610 qdss_funnel_in1: endpoint { 2611 remote-endpoint = 2612 <&funnel1_out>; 2613 }; 2614 }; 2615 }; 2616 }; 2617 2618 funnel@4b04000 { 2619 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2620 reg = <0x0 0x4b04000 0x0 0x1000>; 2621 2622 clocks = <&aoss_qmp>; 2623 clock-names = "apb_pclk"; 2624 2625 out-ports { 2626 port { 2627 aoss_funnel_out: endpoint { 2628 remote-endpoint = 2629 <&etf0_in>; 2630 }; 2631 }; 2632 }; 2633 2634 in-ports { 2635 #address-cells = <1>; 2636 #size-cells = <0>; 2637 2638 port@6 { 2639 reg = <6>; 2640 aoss_funnel_in6: endpoint { 2641 remote-endpoint = 2642 <&aoss_tpda_out>; 2643 }; 2644 }; 2645 2646 port@7 { 2647 reg = <7>; 2648 aoss_funnel_in7: endpoint { 2649 remote-endpoint = 2650 <&qdss_funnel_out>; 2651 }; 2652 }; 2653 }; 2654 }; 2655 2656 tmc_etf: tmc@4b05000 { 2657 compatible = "arm,coresight-tmc", "arm,primecell"; 2658 reg = <0x0 0x4b05000 0x0 0x1000>; 2659 2660 clocks = <&aoss_qmp>; 2661 clock-names = "apb_pclk"; 2662 2663 out-ports { 2664 port { 2665 etf0_out: endpoint { 2666 remote-endpoint = 2667 <&swao_rep_in>; 2668 }; 2669 }; 2670 }; 2671 2672 in-ports { 2673 port { 2674 etf0_in: endpoint { 2675 remote-endpoint = 2676 <&aoss_funnel_out>; 2677 }; 2678 }; 2679 }; 2680 }; 2681 2682 replicator@4b06000 { 2683 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2684 reg = <0x0 0x4b06000 0x0 0x1000>; 2685 2686 clocks = <&aoss_qmp>; 2687 clock-names = "apb_pclk"; 2688 2689 out-ports { 2690 #address-cells = <1>; 2691 #size-cells = <0>; 2692 2693 port@1 { 2694 reg = <1>; 2695 swao_rep_out1: endpoint { 2696 remote-endpoint = 2697 <&eud_in>; 2698 }; 2699 }; 2700 }; 2701 2702 in-ports { 2703 port { 2704 swao_rep_in: endpoint { 2705 remote-endpoint = 2706 <&etf0_out>; 2707 }; 2708 }; 2709 }; 2710 }; 2711 2712 tpda@4b08000 { 2713 compatible = "qcom,coresight-tpda", "arm,primecell"; 2714 reg = <0x0 0x4b08000 0x0 0x1000>; 2715 2716 clocks = <&aoss_qmp>; 2717 clock-names = "apb_pclk"; 2718 2719 out-ports { 2720 port { 2721 aoss_tpda_out: endpoint { 2722 remote-endpoint = 2723 <&aoss_funnel_in6>; 2724 }; 2725 }; 2726 }; 2727 2728 in-ports { 2729 #address-cells = <1>; 2730 #size-cells = <0>; 2731 2732 port@0 { 2733 reg = <0>; 2734 aoss_tpda_in0: endpoint { 2735 remote-endpoint = 2736 <&aoss_tpdm0_out>; 2737 }; 2738 }; 2739 2740 port@1 { 2741 reg = <1>; 2742 aoss_tpda_in1: endpoint { 2743 remote-endpoint = 2744 <&aoss_tpdm1_out>; 2745 }; 2746 }; 2747 2748 port@2 { 2749 reg = <2>; 2750 aoss_tpda_in2: endpoint { 2751 remote-endpoint = 2752 <&aoss_tpdm2_out>; 2753 }; 2754 }; 2755 2756 port@3 { 2757 reg = <3>; 2758 aoss_tpda_in3: endpoint { 2759 remote-endpoint = 2760 <&aoss_tpdm3_out>; 2761 }; 2762 }; 2763 2764 port@4 { 2765 reg = <4>; 2766 aoss_tpda_in4: endpoint { 2767 remote-endpoint = 2768 <&aoss_tpdm4_out>; 2769 }; 2770 }; 2771 }; 2772 }; 2773 2774 tpdm@4b09000 { 2775 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2776 reg = <0x0 0x4b09000 0x0 0x1000>; 2777 2778 clocks = <&aoss_qmp>; 2779 clock-names = "apb_pclk"; 2780 2781 qcom,cmb-element-bits = <64>; 2782 qcom,cmb-msrs-num = <32>; 2783 2784 out-ports { 2785 port { 2786 aoss_tpdm0_out: endpoint { 2787 remote-endpoint = 2788 <&aoss_tpda_in0>; 2789 }; 2790 }; 2791 }; 2792 }; 2793 2794 tpdm@4b0a000 { 2795 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2796 reg = <0x0 0x4b0a000 0x0 0x1000>; 2797 2798 clocks = <&aoss_qmp>; 2799 clock-names = "apb_pclk"; 2800 2801 qcom,cmb-element-bits = <64>; 2802 qcom,cmb-msrs-num = <32>; 2803 2804 out-ports { 2805 port { 2806 aoss_tpdm1_out: endpoint { 2807 remote-endpoint = 2808 <&aoss_tpda_in1>; 2809 }; 2810 }; 2811 }; 2812 }; 2813 2814 tpdm@4b0b000 { 2815 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2816 reg = <0x0 0x4b0b000 0x0 0x1000>; 2817 2818 clocks = <&aoss_qmp>; 2819 clock-names = "apb_pclk"; 2820 2821 qcom,cmb-element-bits = <64>; 2822 qcom,cmb-msrs-num = <32>; 2823 2824 out-ports { 2825 port { 2826 aoss_tpdm2_out: endpoint { 2827 remote-endpoint = 2828 <&aoss_tpda_in2>; 2829 }; 2830 }; 2831 }; 2832 }; 2833 2834 tpdm@4b0c000 { 2835 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2836 reg = <0x0 0x4b0c000 0x0 0x1000>; 2837 2838 clocks = <&aoss_qmp>; 2839 clock-names = "apb_pclk"; 2840 2841 qcom,cmb-element-bits = <64>; 2842 qcom,cmb-msrs-num = <32>; 2843 2844 out-ports { 2845 port { 2846 aoss_tpdm3_out: endpoint { 2847 remote-endpoint = 2848 <&aoss_tpda_in3>; 2849 }; 2850 }; 2851 }; 2852 }; 2853 2854 tpdm@4b0d000 { 2855 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2856 reg = <0x0 0x4b0d000 0x0 0x1000>; 2857 2858 clocks = <&aoss_qmp>; 2859 clock-names = "apb_pclk"; 2860 2861 qcom,dsb-element-bits = <32>; 2862 qcom,dsb-msrs-num = <32>; 2863 2864 out-ports { 2865 port { 2866 aoss_tpdm4_out: endpoint { 2867 remote-endpoint = 2868 <&aoss_tpda_in4>; 2869 }; 2870 }; 2871 }; 2872 }; 2873 2874 aoss_cti: cti@4b13000 { 2875 compatible = "arm,coresight-cti", "arm,primecell"; 2876 reg = <0x0 0x4b13000 0x0 0x1000>; 2877 2878 clocks = <&aoss_qmp>; 2879 clock-names = "apb_pclk"; 2880 }; 2881 2882 etm@6040000 { 2883 compatible = "arm,primecell"; 2884 reg = <0x0 0x6040000 0x0 0x1000>; 2885 cpu = <&cpu0>; 2886 2887 clocks = <&aoss_qmp>; 2888 clock-names = "apb_pclk"; 2889 arm,coresight-loses-context-with-cpu; 2890 qcom,skip-power-up; 2891 2892 out-ports { 2893 port { 2894 etm0_out: endpoint { 2895 remote-endpoint = 2896 <&apss_funnel0_in0>; 2897 }; 2898 }; 2899 }; 2900 }; 2901 2902 etm@6140000 { 2903 compatible = "arm,primecell"; 2904 reg = <0x0 0x6140000 0x0 0x1000>; 2905 cpu = <&cpu1>; 2906 2907 clocks = <&aoss_qmp>; 2908 clock-names = "apb_pclk"; 2909 arm,coresight-loses-context-with-cpu; 2910 qcom,skip-power-up; 2911 2912 out-ports { 2913 port { 2914 etm1_out: endpoint { 2915 remote-endpoint = 2916 <&apss_funnel0_in1>; 2917 }; 2918 }; 2919 }; 2920 }; 2921 2922 etm@6240000 { 2923 compatible = "arm,primecell"; 2924 reg = <0x0 0x6240000 0x0 0x1000>; 2925 cpu = <&cpu2>; 2926 2927 clocks = <&aoss_qmp>; 2928 clock-names = "apb_pclk"; 2929 arm,coresight-loses-context-with-cpu; 2930 qcom,skip-power-up; 2931 2932 out-ports { 2933 port { 2934 etm2_out: endpoint { 2935 remote-endpoint = 2936 <&apss_funnel0_in2>; 2937 }; 2938 }; 2939 }; 2940 }; 2941 2942 etm@6340000 { 2943 compatible = "arm,primecell"; 2944 reg = <0x0 0x6340000 0x0 0x1000>; 2945 cpu = <&cpu3>; 2946 2947 clocks = <&aoss_qmp>; 2948 clock-names = "apb_pclk"; 2949 arm,coresight-loses-context-with-cpu; 2950 qcom,skip-power-up; 2951 2952 out-ports { 2953 port { 2954 etm3_out: endpoint { 2955 remote-endpoint = 2956 <&apss_funnel0_in3>; 2957 }; 2958 }; 2959 }; 2960 }; 2961 2962 etm@6440000 { 2963 compatible = "arm,primecell"; 2964 reg = <0x0 0x6440000 0x0 0x1000>; 2965 cpu = <&cpu4>; 2966 2967 clocks = <&aoss_qmp>; 2968 clock-names = "apb_pclk"; 2969 arm,coresight-loses-context-with-cpu; 2970 qcom,skip-power-up; 2971 2972 out-ports { 2973 port { 2974 etm4_out: endpoint { 2975 remote-endpoint = 2976 <&apss_funnel0_in4>; 2977 }; 2978 }; 2979 }; 2980 }; 2981 2982 etm@6540000 { 2983 compatible = "arm,primecell"; 2984 reg = <0x0 0x6540000 0x0 0x1000>; 2985 cpu = <&cpu5>; 2986 2987 clocks = <&aoss_qmp>; 2988 clock-names = "apb_pclk"; 2989 arm,coresight-loses-context-with-cpu; 2990 qcom,skip-power-up; 2991 2992 out-ports { 2993 port { 2994 etm5_out: endpoint { 2995 remote-endpoint = 2996 <&apss_funnel0_in5>; 2997 }; 2998 }; 2999 }; 3000 }; 3001 3002 etm@6640000 { 3003 compatible = "arm,primecell"; 3004 reg = <0x0 0x6640000 0x0 0x1000>; 3005 cpu = <&cpu6>; 3006 3007 clocks = <&aoss_qmp>; 3008 clock-names = "apb_pclk"; 3009 arm,coresight-loses-context-with-cpu; 3010 qcom,skip-power-up; 3011 3012 out-ports { 3013 port { 3014 etm6_out: endpoint { 3015 remote-endpoint = 3016 <&apss_funnel0_in6>; 3017 }; 3018 }; 3019 }; 3020 }; 3021 3022 etm@6740000 { 3023 compatible = "arm,primecell"; 3024 reg = <0x0 0x6740000 0x0 0x1000>; 3025 cpu = <&cpu7>; 3026 3027 clocks = <&aoss_qmp>; 3028 clock-names = "apb_pclk"; 3029 arm,coresight-loses-context-with-cpu; 3030 qcom,skip-power-up; 3031 3032 out-ports { 3033 port { 3034 etm7_out: endpoint { 3035 remote-endpoint = 3036 <&apss_funnel0_in7>; 3037 }; 3038 }; 3039 }; 3040 }; 3041 3042 funnel@6800000 { 3043 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3044 reg = <0x0 0x6800000 0x0 0x1000>; 3045 3046 clocks = <&aoss_qmp>; 3047 clock-names = "apb_pclk"; 3048 3049 out-ports { 3050 port { 3051 apss_funnel0_out: endpoint { 3052 remote-endpoint = 3053 <&apss_funnel1_in0>; 3054 }; 3055 }; 3056 }; 3057 3058 in-ports { 3059 #address-cells = <1>; 3060 #size-cells = <0>; 3061 3062 port@0 { 3063 reg = <0>; 3064 apss_funnel0_in0: endpoint { 3065 remote-endpoint = 3066 <&etm0_out>; 3067 }; 3068 }; 3069 3070 port@1 { 3071 reg = <1>; 3072 apss_funnel0_in1: endpoint { 3073 remote-endpoint = 3074 <&etm1_out>; 3075 }; 3076 }; 3077 3078 port@2 { 3079 reg = <2>; 3080 apss_funnel0_in2: endpoint { 3081 remote-endpoint = 3082 <&etm2_out>; 3083 }; 3084 }; 3085 3086 port@3 { 3087 reg = <3>; 3088 apss_funnel0_in3: endpoint { 3089 remote-endpoint = 3090 <&etm3_out>; 3091 }; 3092 }; 3093 3094 port@4 { 3095 reg = <4>; 3096 apss_funnel0_in4: endpoint { 3097 remote-endpoint = 3098 <&etm4_out>; 3099 }; 3100 }; 3101 3102 port@5 { 3103 reg = <5>; 3104 apss_funnel0_in5: endpoint { 3105 remote-endpoint = 3106 <&etm5_out>; 3107 }; 3108 }; 3109 3110 port@6 { 3111 reg = <6>; 3112 apss_funnel0_in6: endpoint { 3113 remote-endpoint = 3114 <&etm6_out>; 3115 }; 3116 }; 3117 3118 port@7 { 3119 reg = <7>; 3120 apss_funnel0_in7: endpoint { 3121 remote-endpoint = 3122 <&etm7_out>; 3123 }; 3124 }; 3125 }; 3126 }; 3127 3128 funnel@6810000 { 3129 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3130 reg = <0x0 0x6810000 0x0 0x1000>; 3131 3132 clocks = <&aoss_qmp>; 3133 clock-names = "apb_pclk"; 3134 3135 out-ports { 3136 port { 3137 apss_funnel1_out: endpoint { 3138 remote-endpoint = 3139 <&funnel1_in4>; 3140 }; 3141 }; 3142 }; 3143 3144 in-ports { 3145 #address-cells = <1>; 3146 #size-cells = <0>; 3147 3148 port@0 { 3149 reg = <0>; 3150 apss_funnel1_in0: endpoint { 3151 remote-endpoint = 3152 <&apss_funnel0_out>; 3153 }; 3154 }; 3155 3156 port@3 { 3157 reg = <3>; 3158 apss_funnel1_in3: endpoint { 3159 remote-endpoint = 3160 <&apss_tpda_out>; 3161 }; 3162 }; 3163 }; 3164 }; 3165 3166 tpdm@6860000 { 3167 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3168 reg = <0x0 0x6860000 0x0 0x1000>; 3169 3170 clocks = <&aoss_qmp>; 3171 clock-names = "apb_pclk"; 3172 3173 qcom,cmb-element-bits = <64>; 3174 qcom,cmb-msrs-num = <32>; 3175 3176 out-ports { 3177 port { 3178 apss_tpdm3_out: endpoint { 3179 remote-endpoint = 3180 <&apss_tpda_in3>; 3181 }; 3182 }; 3183 }; 3184 }; 3185 3186 tpdm@6861000 { 3187 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3188 reg = <0x0 0x6861000 0x0 0x1000>; 3189 3190 clocks = <&aoss_qmp>; 3191 clock-names = "apb_pclk"; 3192 3193 qcom,dsb-element-bits = <32>; 3194 qcom,dsb-msrs-num = <32>; 3195 3196 out-ports { 3197 port { 3198 apss_tpdm4_out: endpoint { 3199 remote-endpoint = 3200 <&apss_tpda_in4>; 3201 }; 3202 }; 3203 }; 3204 }; 3205 3206 tpda@6863000 { 3207 compatible = "qcom,coresight-tpda", "arm,primecell"; 3208 reg = <0x0 0x6863000 0x0 0x1000>; 3209 3210 clocks = <&aoss_qmp>; 3211 clock-names = "apb_pclk"; 3212 3213 out-ports { 3214 port { 3215 apss_tpda_out: endpoint { 3216 remote-endpoint = 3217 <&apss_funnel1_in3>; 3218 }; 3219 }; 3220 }; 3221 3222 in-ports { 3223 #address-cells = <1>; 3224 #size-cells = <0>; 3225 3226 port@0 { 3227 reg = <0>; 3228 apss_tpda_in0: endpoint { 3229 remote-endpoint = 3230 <&apss_tpdm0_out>; 3231 }; 3232 }; 3233 3234 port@1 { 3235 reg = <1>; 3236 apss_tpda_in1: endpoint { 3237 remote-endpoint = 3238 <&apss_tpdm1_out>; 3239 }; 3240 }; 3241 3242 port@2 { 3243 reg = <2>; 3244 apss_tpda_in2: endpoint { 3245 remote-endpoint = 3246 <&apss_tpdm2_out>; 3247 }; 3248 }; 3249 3250 port@3 { 3251 reg = <3>; 3252 apss_tpda_in3: endpoint { 3253 remote-endpoint = 3254 <&apss_tpdm3_out>; 3255 }; 3256 }; 3257 3258 port@4 { 3259 reg = <4>; 3260 apss_tpda_in4: endpoint { 3261 remote-endpoint = 3262 <&apss_tpdm4_out>; 3263 }; 3264 }; 3265 }; 3266 }; 3267 3268 tpdm@68a0000 { 3269 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3270 reg = <0x0 0x68a0000 0x0 0x1000>; 3271 3272 clocks = <&aoss_qmp>; 3273 clock-names = "apb_pclk"; 3274 3275 qcom,cmb-element-bits = <32>; 3276 qcom,cmb-msrs-num = <32>; 3277 3278 out-ports { 3279 port { 3280 apss_tpdm0_out: endpoint { 3281 remote-endpoint = 3282 <&apss_tpda_in0>; 3283 }; 3284 }; 3285 }; 3286 }; 3287 3288 tpdm@68b0000 { 3289 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3290 reg = <0x0 0x68b0000 0x0 0x1000>; 3291 3292 clocks = <&aoss_qmp>; 3293 clock-names = "apb_pclk"; 3294 3295 qcom,cmb-element-bits = <32>; 3296 qcom,cmb-msrs-num = <32>; 3297 3298 out-ports { 3299 port { 3300 apss_tpdm1_out: endpoint { 3301 remote-endpoint = 3302 <&apss_tpda_in1>; 3303 }; 3304 }; 3305 }; 3306 }; 3307 3308 tpdm@68c0000 { 3309 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3310 reg = <0x0 0x68c0000 0x0 0x1000>; 3311 3312 clocks = <&aoss_qmp>; 3313 clock-names = "apb_pclk"; 3314 3315 qcom,dsb-element-bits = <32>; 3316 qcom,dsb-msrs-num = <32>; 3317 3318 out-ports { 3319 port { 3320 apss_tpdm2_out: endpoint { 3321 remote-endpoint = 3322 <&apss_tpda_in2>; 3323 }; 3324 }; 3325 }; 3326 }; 3327 3328 usb_0_hsphy: phy@88e4000 { 3329 compatible = "qcom,sa8775p-usb-hs-phy", 3330 "qcom,usb-snps-hs-5nm-phy"; 3331 reg = <0 0x088e4000 0 0x120>; 3332 clocks = <&rpmhcc RPMH_CXO_CLK>; 3333 clock-names = "ref"; 3334 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 3335 3336 #phy-cells = <0>; 3337 3338 status = "disabled"; 3339 }; 3340 3341 usb_0_qmpphy: phy@88e8000 { 3342 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 3343 reg = <0 0x088e8000 0 0x2000>; 3344 3345 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3346 <&gcc GCC_USB_CLKREF_EN>, 3347 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3348 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3349 clock-names = "aux", "ref", "com_aux", "pipe"; 3350 3351 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3352 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 3353 reset-names = "phy", "phy_phy"; 3354 3355 power-domains = <&gcc USB30_PRIM_GDSC>; 3356 3357 #clock-cells = <0>; 3358 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 3359 3360 #phy-cells = <0>; 3361 3362 status = "disabled"; 3363 }; 3364 3365 usb_0: usb@a6f8800 { 3366 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 3367 reg = <0 0x0a6f8800 0 0x400>; 3368 #address-cells = <2>; 3369 #size-cells = <2>; 3370 ranges; 3371 3372 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3373 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3374 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3375 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3376 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3377 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3378 3379 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3380 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3381 assigned-clock-rates = <19200000>, <200000000>; 3382 3383 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 3384 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3385 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3386 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3387 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 3388 interrupt-names = "pwr_event", 3389 "hs_phy_irq", 3390 "dp_hs_phy_irq", 3391 "dm_hs_phy_irq", 3392 "ss_phy_irq"; 3393 3394 power-domains = <&gcc USB30_PRIM_GDSC>; 3395 required-opps = <&rpmhpd_opp_nom>; 3396 3397 resets = <&gcc GCC_USB30_PRIM_BCR>; 3398 3399 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3400 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3401 interconnect-names = "usb-ddr", "apps-usb"; 3402 3403 wakeup-source; 3404 3405 status = "disabled"; 3406 3407 usb_0_dwc3: usb@a600000 { 3408 compatible = "snps,dwc3"; 3409 reg = <0 0x0a600000 0 0xe000>; 3410 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 3411 iommus = <&apps_smmu 0x080 0x0>; 3412 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 3413 phy-names = "usb2-phy", "usb3-phy"; 3414 }; 3415 }; 3416 3417 usb_1_hsphy: phy@88e6000 { 3418 compatible = "qcom,sa8775p-usb-hs-phy", 3419 "qcom,usb-snps-hs-5nm-phy"; 3420 reg = <0 0x088e6000 0 0x120>; 3421 clocks = <&gcc GCC_USB_CLKREF_EN>; 3422 clock-names = "ref"; 3423 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 3424 3425 #phy-cells = <0>; 3426 3427 status = "disabled"; 3428 }; 3429 3430 usb_1_qmpphy: phy@88ea000 { 3431 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 3432 reg = <0 0x088ea000 0 0x2000>; 3433 3434 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3435 <&gcc GCC_USB_CLKREF_EN>, 3436 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3437 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3438 clock-names = "aux", "ref", "com_aux", "pipe"; 3439 3440 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3441 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3442 reset-names = "phy", "phy_phy"; 3443 3444 power-domains = <&gcc USB30_SEC_GDSC>; 3445 3446 #clock-cells = <0>; 3447 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 3448 3449 #phy-cells = <0>; 3450 3451 status = "disabled"; 3452 }; 3453 3454 usb_1: usb@a8f8800 { 3455 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 3456 reg = <0 0x0a8f8800 0 0x400>; 3457 #address-cells = <2>; 3458 #size-cells = <2>; 3459 ranges; 3460 3461 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3462 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3463 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3464 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3465 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3466 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3467 3468 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3469 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3470 assigned-clock-rates = <19200000>, <200000000>; 3471 3472 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 3473 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 3474 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3475 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 3476 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 3477 interrupt-names = "pwr_event", 3478 "hs_phy_irq", 3479 "dp_hs_phy_irq", 3480 "dm_hs_phy_irq", 3481 "ss_phy_irq"; 3482 3483 power-domains = <&gcc USB30_SEC_GDSC>; 3484 required-opps = <&rpmhpd_opp_nom>; 3485 3486 resets = <&gcc GCC_USB30_SEC_BCR>; 3487 3488 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3489 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3490 interconnect-names = "usb-ddr", "apps-usb"; 3491 3492 wakeup-source; 3493 3494 status = "disabled"; 3495 3496 usb_1_dwc3: usb@a800000 { 3497 compatible = "snps,dwc3"; 3498 reg = <0 0x0a800000 0 0xe000>; 3499 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 3500 iommus = <&apps_smmu 0x0a0 0x0>; 3501 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 3502 phy-names = "usb2-phy", "usb3-phy"; 3503 }; 3504 }; 3505 3506 usb_2_hsphy: phy@88e7000 { 3507 compatible = "qcom,sa8775p-usb-hs-phy", 3508 "qcom,usb-snps-hs-5nm-phy"; 3509 reg = <0 0x088e7000 0 0x120>; 3510 clocks = <&gcc GCC_USB_CLKREF_EN>; 3511 clock-names = "ref"; 3512 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 3513 3514 #phy-cells = <0>; 3515 3516 status = "disabled"; 3517 }; 3518 3519 usb_2: usb@a4f8800 { 3520 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 3521 reg = <0 0x0a4f8800 0 0x400>; 3522 #address-cells = <2>; 3523 #size-cells = <2>; 3524 ranges; 3525 3526 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 3527 <&gcc GCC_USB20_MASTER_CLK>, 3528 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 3529 <&gcc GCC_USB20_SLEEP_CLK>, 3530 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 3531 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3532 3533 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3534 <&gcc GCC_USB20_MASTER_CLK>; 3535 assigned-clock-rates = <19200000>, <200000000>; 3536 3537 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 3538 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 3539 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 3540 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 3541 interrupt-names = "pwr_event", 3542 "hs_phy_irq", 3543 "dp_hs_phy_irq", 3544 "dm_hs_phy_irq"; 3545 3546 power-domains = <&gcc USB20_PRIM_GDSC>; 3547 required-opps = <&rpmhpd_opp_nom>; 3548 3549 resets = <&gcc GCC_USB20_PRIM_BCR>; 3550 3551 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3552 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 3553 interconnect-names = "usb-ddr", "apps-usb"; 3554 3555 wakeup-source; 3556 3557 status = "disabled"; 3558 3559 usb_2_dwc3: usb@a400000 { 3560 compatible = "snps,dwc3"; 3561 reg = <0 0x0a400000 0 0xe000>; 3562 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 3563 iommus = <&apps_smmu 0x020 0x0>; 3564 phys = <&usb_2_hsphy>; 3565 phy-names = "usb2-phy"; 3566 }; 3567 }; 3568 3569 tcsr_mutex: hwlock@1f40000 { 3570 compatible = "qcom,tcsr-mutex"; 3571 reg = <0x0 0x01f40000 0x0 0x20000>; 3572 #hwlock-cells = <1>; 3573 }; 3574 3575 tcsr: syscon@1fc0000 { 3576 compatible = "qcom,sa8775p-tcsr", "syscon"; 3577 reg = <0x0 0x1fc0000 0x0 0x30000>; 3578 }; 3579 3580 gpucc: clock-controller@3d90000 { 3581 compatible = "qcom,sa8775p-gpucc"; 3582 reg = <0x0 0x03d90000 0x0 0xa000>; 3583 clocks = <&rpmhcc RPMH_CXO_CLK>, 3584 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3585 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3586 clock-names = "bi_tcxo", 3587 "gcc_gpu_gpll0_clk_src", 3588 "gcc_gpu_gpll0_div_clk_src"; 3589 #clock-cells = <1>; 3590 #reset-cells = <1>; 3591 #power-domain-cells = <1>; 3592 }; 3593 3594 adreno_smmu: iommu@3da0000 { 3595 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 3596 "qcom,smmu-500", "arm,mmu-500"; 3597 reg = <0x0 0x03da0000 0x0 0x20000>; 3598 #iommu-cells = <2>; 3599 #global-interrupts = <2>; 3600 dma-coherent; 3601 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3602 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3603 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3604 <&gpucc GPU_CC_AHB_CLK>, 3605 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3606 <&gpucc GPU_CC_CX_GMU_CLK>, 3607 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3608 <&gpucc GPU_CC_HUB_AON_CLK>; 3609 clock-names = "gcc_gpu_memnoc_gfx_clk", 3610 "gcc_gpu_snoc_dvm_gfx_clk", 3611 "gpu_cc_ahb_clk", 3612 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3613 "gpu_cc_cx_gmu_clk", 3614 "gpu_cc_hub_cx_int_clk", 3615 "gpu_cc_hub_aon_clk"; 3616 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 3628 }; 3629 3630 serdes0: phy@8901000 { 3631 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 3632 reg = <0x0 0x08901000 0x0 0xe10>; 3633 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 3634 clock-names = "sgmi_ref"; 3635 #phy-cells = <0>; 3636 status = "disabled"; 3637 }; 3638 3639 serdes1: phy@8902000 { 3640 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 3641 reg = <0x0 0x08902000 0x0 0xe10>; 3642 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 3643 clock-names = "sgmi_ref"; 3644 #phy-cells = <0>; 3645 status = "disabled"; 3646 }; 3647 3648 pmu@9091000 { 3649 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3650 reg = <0x0 0x9091000 0x0 0x1000>; 3651 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 3652 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3653 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3654 3655 operating-points-v2 = <&llcc_bwmon_opp_table>; 3656 3657 llcc_bwmon_opp_table: opp-table { 3658 compatible = "operating-points-v2"; 3659 3660 opp-0 { 3661 opp-peak-kBps = <762000>; 3662 }; 3663 3664 opp-1 { 3665 opp-peak-kBps = <1720000>; 3666 }; 3667 3668 opp-2 { 3669 opp-peak-kBps = <2086000>; 3670 }; 3671 3672 opp-3 { 3673 opp-peak-kBps = <2601000>; 3674 }; 3675 3676 opp-4 { 3677 opp-peak-kBps = <2929000>; 3678 }; 3679 3680 opp-5 { 3681 opp-peak-kBps = <5931000>; 3682 }; 3683 3684 opp-6 { 3685 opp-peak-kBps = <6515000>; 3686 }; 3687 3688 opp-7 { 3689 opp-peak-kBps = <7984000>; 3690 }; 3691 3692 opp-8 { 3693 opp-peak-kBps = <10437000>; 3694 }; 3695 3696 opp-9 { 3697 opp-peak-kBps = <12195000>; 3698 }; 3699 }; 3700 }; 3701 3702 pmu@90b5400 { 3703 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 3704 reg = <0x0 0x90b5400 0x0 0x600>; 3705 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3706 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3707 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3708 3709 operating-points-v2 = <&cpu_bwmon_opp_table>; 3710 3711 cpu_bwmon_opp_table: opp-table { 3712 compatible = "operating-points-v2"; 3713 3714 opp-0 { 3715 opp-peak-kBps = <9155000>; 3716 }; 3717 3718 opp-1 { 3719 opp-peak-kBps = <12298000>; 3720 }; 3721 3722 opp-2 { 3723 opp-peak-kBps = <14236000>; 3724 }; 3725 3726 opp-3 { 3727 opp-peak-kBps = <16265000>; 3728 }; 3729 }; 3730 3731 }; 3732 3733 pmu@90b6400 { 3734 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 3735 reg = <0x0 0x90b6400 0x0 0x600>; 3736 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3737 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3738 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3739 3740 operating-points-v2 = <&cpu_bwmon_opp_table>; 3741 }; 3742 3743 llcc: system-cache-controller@9200000 { 3744 compatible = "qcom,sa8775p-llcc"; 3745 reg = <0x0 0x09200000 0x0 0x80000>, 3746 <0x0 0x09300000 0x0 0x80000>, 3747 <0x0 0x09400000 0x0 0x80000>, 3748 <0x0 0x09500000 0x0 0x80000>, 3749 <0x0 0x09600000 0x0 0x80000>, 3750 <0x0 0x09700000 0x0 0x80000>, 3751 <0x0 0x09a00000 0x0 0x80000>; 3752 reg-names = "llcc0_base", 3753 "llcc1_base", 3754 "llcc2_base", 3755 "llcc3_base", 3756 "llcc4_base", 3757 "llcc5_base", 3758 "llcc_broadcast_base"; 3759 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 3760 }; 3761 3762 pdc: interrupt-controller@b220000 { 3763 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 3764 reg = <0x0 0x0b220000 0x0 0x30000>, 3765 <0x0 0x17c000f0 0x0 0x64>; 3766 qcom,pdc-ranges = <0 480 40>, 3767 <40 140 14>, 3768 <54 263 1>, 3769 <55 306 4>, 3770 <59 312 3>, 3771 <62 374 2>, 3772 <64 434 2>, 3773 <66 438 2>, 3774 <70 520 1>, 3775 <73 523 1>, 3776 <118 568 6>, 3777 <124 609 3>, 3778 <159 638 1>, 3779 <160 720 3>, 3780 <169 728 30>, 3781 <199 416 2>, 3782 <201 449 1>, 3783 <202 89 1>, 3784 <203 451 1>, 3785 <204 462 1>, 3786 <205 264 1>, 3787 <206 579 1>, 3788 <207 653 1>, 3789 <208 656 1>, 3790 <209 659 1>, 3791 <210 122 1>, 3792 <211 699 1>, 3793 <212 705 1>, 3794 <213 450 1>, 3795 <214 643 2>, 3796 <216 646 5>, 3797 <221 390 5>, 3798 <226 700 2>, 3799 <228 440 1>, 3800 <229 663 1>, 3801 <230 524 2>, 3802 <232 612 3>, 3803 <235 723 5>; 3804 #interrupt-cells = <2>; 3805 interrupt-parent = <&intc>; 3806 interrupt-controller; 3807 }; 3808 3809 tsens2: thermal-sensor@c251000 { 3810 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 3811 reg = <0x0 0x0c251000 0x0 0x1ff>, 3812 <0x0 0x0c224000 0x0 0x8>; 3813 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 3815 #qcom,sensors = <13>; 3816 interrupt-names = "uplow", "critical"; 3817 #thermal-sensor-cells = <1>; 3818 }; 3819 3820 tsens3: thermal-sensor@c252000 { 3821 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 3822 reg = <0x0 0x0c252000 0x0 0x1ff>, 3823 <0x0 0x0c225000 0x0 0x8>; 3824 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 3825 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 3826 #qcom,sensors = <13>; 3827 interrupt-names = "uplow", "critical"; 3828 #thermal-sensor-cells = <1>; 3829 }; 3830 3831 tsens0: thermal-sensor@c263000 { 3832 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 3833 reg = <0x0 0x0c263000 0x0 0x1ff>, 3834 <0x0 0x0c222000 0x0 0x8>; 3835 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3836 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3837 #qcom,sensors = <12>; 3838 interrupt-names = "uplow", "critical"; 3839 #thermal-sensor-cells = <1>; 3840 }; 3841 3842 tsens1: thermal-sensor@c265000 { 3843 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 3844 reg = <0x0 0x0c265000 0x0 0x1ff>, 3845 <0x0 0x0c223000 0x0 0x8>; 3846 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3848 #qcom,sensors = <12>; 3849 interrupt-names = "uplow", "critical"; 3850 #thermal-sensor-cells = <1>; 3851 }; 3852 3853 aoss_qmp: power-management@c300000 { 3854 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 3855 reg = <0x0 0x0c300000 0x0 0x400>; 3856 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3857 IPCC_MPROC_SIGNAL_GLINK_QMP 3858 IRQ_TYPE_EDGE_RISING>; 3859 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3860 #clock-cells = <0>; 3861 }; 3862 3863 sram@c3f0000 { 3864 compatible = "qcom,rpmh-stats"; 3865 reg = <0x0 0x0c3f0000 0x0 0x400>; 3866 }; 3867 3868 spmi_bus: spmi@c440000 { 3869 compatible = "qcom,spmi-pmic-arb"; 3870 reg = <0x0 0x0c440000 0x0 0x1100>, 3871 <0x0 0x0c600000 0x0 0x2000000>, 3872 <0x0 0x0e600000 0x0 0x100000>, 3873 <0x0 0x0e700000 0x0 0xa0000>, 3874 <0x0 0x0c40a000 0x0 0x26000>; 3875 reg-names = "core", 3876 "chnls", 3877 "obsrvr", 3878 "intr", 3879 "cnfg"; 3880 qcom,channel = <0>; 3881 qcom,ee = <0>; 3882 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3883 interrupt-names = "periph_irq"; 3884 interrupt-controller; 3885 #interrupt-cells = <4>; 3886 #address-cells = <2>; 3887 #size-cells = <0>; 3888 }; 3889 3890 tlmm: pinctrl@f000000 { 3891 compatible = "qcom,sa8775p-tlmm"; 3892 reg = <0x0 0x0f000000 0x0 0x1000000>; 3893 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3894 gpio-controller; 3895 #gpio-cells = <2>; 3896 interrupt-controller; 3897 #interrupt-cells = <2>; 3898 gpio-ranges = <&tlmm 0 0 149>; 3899 wakeup-parent = <&pdc>; 3900 }; 3901 3902 sram: sram@146d8000 { 3903 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; 3904 reg = <0x0 0x146d8000 0x0 0x1000>; 3905 ranges = <0x0 0x0 0x146d8000 0x1000>; 3906 3907 #address-cells = <1>; 3908 #size-cells = <1>; 3909 3910 pil-reloc@94c { 3911 compatible = "qcom,pil-reloc-info"; 3912 reg = <0x94c 0xc8>; 3913 }; 3914 }; 3915 3916 apps_smmu: iommu@15000000 { 3917 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3918 reg = <0x0 0x15000000 0x0 0x100000>; 3919 #iommu-cells = <2>; 3920 #global-interrupts = <2>; 3921 dma-coherent; 3922 3923 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 3924 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 3925 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3926 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3927 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3931 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3932 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3933 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3934 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3935 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3936 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3937 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3938 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3939 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3940 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3941 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3942 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3943 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3944 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3945 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3946 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3947 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3948 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3949 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3950 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3951 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3952 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3953 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3954 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3955 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3956 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3957 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3958 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3959 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3960 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3961 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3962 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3963 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3964 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3965 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3966 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3967 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3968 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3969 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3970 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3971 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3972 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3973 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3974 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3975 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3976 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3977 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3978 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3979 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3980 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3981 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3982 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3983 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3984 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3985 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3986 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3987 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3988 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3989 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3990 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3991 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3992 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3993 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3994 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3995 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3996 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3997 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3998 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3999 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4000 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4001 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4002 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4003 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4004 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4005 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4006 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4007 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4008 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4009 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4010 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4011 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4012 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4013 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4014 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4016 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 4017 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 4018 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4019 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4021 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4022 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 4023 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 4024 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 4025 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 4026 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4027 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 4028 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 4029 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 4030 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 4031 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 4032 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 4033 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 4034 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 4035 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 4036 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 4037 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 4038 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 4039 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 4040 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 4041 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 4042 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 4043 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 4044 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 4045 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 4047 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 4053 }; 4054 4055 pcie_smmu: iommu@15200000 { 4056 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4057 reg = <0x0 0x15200000 0x0 0x80000>; 4058 #iommu-cells = <2>; 4059 #global-interrupts = <2>; 4060 dma-coherent; 4061 4062 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 4128 }; 4129 4130 intc: interrupt-controller@17a00000 { 4131 compatible = "arm,gic-v3"; 4132 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4133 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4134 interrupt-controller; 4135 #interrupt-cells = <3>; 4136 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4137 #redistributor-regions = <1>; 4138 redistributor-stride = <0x0 0x20000>; 4139 }; 4140 4141 watchdog@17c10000 { 4142 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 4143 reg = <0x0 0x17c10000 0x0 0x1000>; 4144 clocks = <&sleep_clk>; 4145 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4146 }; 4147 4148 memtimer: timer@17c20000 { 4149 compatible = "arm,armv7-timer-mem"; 4150 reg = <0x0 0x17c20000 0x0 0x1000>; 4151 ranges = <0x0 0x0 0x0 0x20000000>; 4152 #address-cells = <1>; 4153 #size-cells = <1>; 4154 4155 frame@17c21000 { 4156 reg = <0x17c21000 0x1000>, 4157 <0x17c22000 0x1000>; 4158 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4160 frame-number = <0>; 4161 }; 4162 4163 frame@17c23000 { 4164 reg = <0x17c23000 0x1000>; 4165 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4166 frame-number = <1>; 4167 status = "disabled"; 4168 }; 4169 4170 frame@17c25000 { 4171 reg = <0x17c25000 0x1000>; 4172 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4173 frame-number = <2>; 4174 status = "disabled"; 4175 }; 4176 4177 frame@17c27000 { 4178 reg = <0x17c27000 0x1000>; 4179 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4180 frame-number = <3>; 4181 status = "disabled"; 4182 }; 4183 4184 frame@17c29000 { 4185 reg = <0x17c29000 0x1000>; 4186 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4187 frame-number = <4>; 4188 status = "disabled"; 4189 }; 4190 4191 frame@17c2b000 { 4192 reg = <0x17c2b000 0x1000>; 4193 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4194 frame-number = <5>; 4195 status = "disabled"; 4196 }; 4197 4198 frame@17c2d000 { 4199 reg = <0x17c2d000 0x1000>; 4200 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4201 frame-number = <6>; 4202 status = "disabled"; 4203 }; 4204 }; 4205 4206 apps_rsc: rsc@18200000 { 4207 compatible = "qcom,rpmh-rsc"; 4208 reg = <0x0 0x18200000 0x0 0x10000>, 4209 <0x0 0x18210000 0x0 0x10000>, 4210 <0x0 0x18220000 0x0 0x10000>; 4211 reg-names = "drv-0", "drv-1", "drv-2"; 4212 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4213 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4214 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4215 qcom,tcs-offset = <0xd00>; 4216 qcom,drv-id = <2>; 4217 qcom,tcs-config = <ACTIVE_TCS 2>, 4218 <SLEEP_TCS 3>, 4219 <WAKE_TCS 3>, 4220 <CONTROL_TCS 0>; 4221 label = "apps_rsc"; 4222 4223 apps_bcm_voter: bcm-voter { 4224 compatible = "qcom,bcm-voter"; 4225 }; 4226 4227 rpmhcc: clock-controller { 4228 compatible = "qcom,sa8775p-rpmh-clk"; 4229 #clock-cells = <1>; 4230 clock-names = "xo"; 4231 clocks = <&xo_board_clk>; 4232 }; 4233 4234 rpmhpd: power-controller { 4235 compatible = "qcom,sa8775p-rpmhpd"; 4236 #power-domain-cells = <1>; 4237 operating-points-v2 = <&rpmhpd_opp_table>; 4238 4239 rpmhpd_opp_table: opp-table { 4240 compatible = "operating-points-v2"; 4241 4242 rpmhpd_opp_ret: opp-0 { 4243 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4244 }; 4245 4246 rpmhpd_opp_min_svs: opp-1 { 4247 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4248 }; 4249 4250 rpmhpd_opp_low_svs: opp2 { 4251 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4252 }; 4253 4254 rpmhpd_opp_svs: opp3 { 4255 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4256 }; 4257 4258 rpmhpd_opp_svs_l1: opp-4 { 4259 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4260 }; 4261 4262 rpmhpd_opp_nom: opp-5 { 4263 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4264 }; 4265 4266 rpmhpd_opp_nom_l1: opp-6 { 4267 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4268 }; 4269 4270 rpmhpd_opp_nom_l2: opp-7 { 4271 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4272 }; 4273 4274 rpmhpd_opp_turbo: opp-8 { 4275 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4276 }; 4277 4278 rpmhpd_opp_turbo_l1: opp-9 { 4279 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4280 }; 4281 }; 4282 }; 4283 }; 4284 4285 cpufreq_hw: cpufreq@18591000 { 4286 compatible = "qcom,sa8775p-cpufreq-epss", 4287 "qcom,cpufreq-epss"; 4288 reg = <0x0 0x18591000 0x0 0x1000>, 4289 <0x0 0x18593000 0x0 0x1000>; 4290 reg-names = "freq-domain0", "freq-domain1"; 4291 4292 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4293 clock-names = "xo", "alternate"; 4294 4295 #freq-domain-cells = <1>; 4296 }; 4297 4298 remoteproc_gpdsp0: remoteproc@20c00000 { 4299 compatible = "qcom,sa8775p-gpdsp0-pas"; 4300 reg = <0x0 0x20c00000 0x0 0x10000>; 4301 4302 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 4303 <&smp2p_gpdsp0_in 0 0>, 4304 <&smp2p_gpdsp0_in 2 0>, 4305 <&smp2p_gpdsp0_in 1 0>, 4306 <&smp2p_gpdsp0_in 3 0>; 4307 interrupt-names = "wdog", "fatal", "ready", 4308 "handover", "stop-ack"; 4309 4310 clocks = <&rpmhcc RPMH_CXO_CLK>; 4311 clock-names = "xo"; 4312 4313 power-domains = <&rpmhpd RPMHPD_CX>, 4314 <&rpmhpd RPMHPD_MXC>; 4315 power-domain-names = "cx", "mxc"; 4316 4317 interconnects = <&gpdsp_anoc MASTER_DSP0 0 4318 &config_noc SLAVE_CLK_CTL 0>; 4319 4320 memory-region = <&pil_gdsp0_mem>; 4321 4322 qcom,qmp = <&aoss_qmp>; 4323 4324 qcom,smem-states = <&smp2p_gpdsp0_out 0>; 4325 qcom,smem-state-names = "stop"; 4326 4327 status = "disabled"; 4328 4329 glink-edge { 4330 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 4331 IPCC_MPROC_SIGNAL_GLINK_QMP 4332 IRQ_TYPE_EDGE_RISING>; 4333 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 4334 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4335 4336 label = "gpdsp0"; 4337 qcom,remote-pid = <17>; 4338 }; 4339 }; 4340 4341 remoteproc_gpdsp1: remoteproc@21c00000 { 4342 compatible = "qcom,sa8775p-gpdsp1-pas"; 4343 reg = <0x0 0x21c00000 0x0 0x10000>; 4344 4345 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 4346 <&smp2p_gpdsp1_in 0 0>, 4347 <&smp2p_gpdsp1_in 2 0>, 4348 <&smp2p_gpdsp1_in 1 0>, 4349 <&smp2p_gpdsp1_in 3 0>; 4350 interrupt-names = "wdog", "fatal", "ready", 4351 "handover", "stop-ack"; 4352 4353 clocks = <&rpmhcc RPMH_CXO_CLK>; 4354 clock-names = "xo"; 4355 4356 power-domains = <&rpmhpd RPMHPD_CX>, 4357 <&rpmhpd RPMHPD_MXC>; 4358 power-domain-names = "cx", "mxc"; 4359 4360 interconnects = <&gpdsp_anoc MASTER_DSP1 0 4361 &config_noc SLAVE_CLK_CTL 0>; 4362 4363 memory-region = <&pil_gdsp1_mem>; 4364 4365 qcom,qmp = <&aoss_qmp>; 4366 4367 qcom,smem-states = <&smp2p_gpdsp1_out 0>; 4368 qcom,smem-state-names = "stop"; 4369 4370 status = "disabled"; 4371 4372 glink-edge { 4373 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 4374 IPCC_MPROC_SIGNAL_GLINK_QMP 4375 IRQ_TYPE_EDGE_RISING>; 4376 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 4377 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4378 4379 label = "gpdsp1"; 4380 qcom,remote-pid = <18>; 4381 }; 4382 }; 4383 4384 ethernet1: ethernet@23000000 { 4385 compatible = "qcom,sa8775p-ethqos"; 4386 reg = <0x0 0x23000000 0x0 0x10000>, 4387 <0x0 0x23016000 0x0 0x100>; 4388 reg-names = "stmmaceth", "rgmii"; 4389 4390 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 4391 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 4392 interrupt-names = "macirq", "sfty"; 4393 4394 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 4395 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 4396 <&gcc GCC_EMAC1_PTP_CLK>, 4397 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 4398 clock-names = "stmmaceth", 4399 "pclk", 4400 "ptp_ref", 4401 "phyaux"; 4402 4403 interconnects = <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS 4404 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4405 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4406 &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>; 4407 interconnect-names = "mac-mem", "cpu-mac"; 4408 4409 power-domains = <&gcc EMAC1_GDSC>; 4410 4411 phys = <&serdes1>; 4412 phy-names = "serdes"; 4413 4414 iommus = <&apps_smmu 0x140 0xf>; 4415 dma-coherent; 4416 4417 snps,tso; 4418 snps,pbl = <32>; 4419 rx-fifo-depth = <16384>; 4420 tx-fifo-depth = <16384>; 4421 4422 status = "disabled"; 4423 }; 4424 4425 ethernet0: ethernet@23040000 { 4426 compatible = "qcom,sa8775p-ethqos"; 4427 reg = <0x0 0x23040000 0x0 0x10000>, 4428 <0x0 0x23056000 0x0 0x100>; 4429 reg-names = "stmmaceth", "rgmii"; 4430 4431 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 4432 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; 4433 interrupt-names = "macirq", "sfty"; 4434 4435 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 4436 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 4437 <&gcc GCC_EMAC0_PTP_CLK>, 4438 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 4439 clock-names = "stmmaceth", 4440 "pclk", 4441 "ptp_ref", 4442 "phyaux"; 4443 4444 interconnects = <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS 4445 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4446 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4447 &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>; 4448 interconnect-names = "mac-mem", "cpu-mac"; 4449 4450 power-domains = <&gcc EMAC0_GDSC>; 4451 4452 phys = <&serdes0>; 4453 phy-names = "serdes"; 4454 4455 iommus = <&apps_smmu 0x120 0xf>; 4456 dma-coherent; 4457 4458 snps,tso; 4459 snps,pbl = <32>; 4460 rx-fifo-depth = <16384>; 4461 tx-fifo-depth = <16384>; 4462 4463 status = "disabled"; 4464 }; 4465 4466 remoteproc_cdsp0: remoteproc@26300000 { 4467 compatible = "qcom,sa8775p-cdsp0-pas"; 4468 reg = <0x0 0x26300000 0x0 0x10000>; 4469 4470 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4471 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>, 4472 <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>, 4473 <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>, 4474 <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>; 4475 interrupt-names = "wdog", "fatal", "ready", 4476 "handover", "stop-ack"; 4477 4478 clocks = <&rpmhcc RPMH_CXO_CLK>; 4479 clock-names = "xo"; 4480 4481 power-domains = <&rpmhpd RPMHPD_CX>, 4482 <&rpmhpd RPMHPD_MXC>, 4483 <&rpmhpd RPMHPD_NSP0>; 4484 power-domain-names = "cx", "mxc", "nsp"; 4485 4486 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 4487 &mc_virt SLAVE_EBI1 0>; 4488 4489 memory-region = <&pil_cdsp0_mem>; 4490 4491 qcom,qmp = <&aoss_qmp>; 4492 4493 qcom,smem-states = <&smp2p_cdsp0_out 0>; 4494 qcom,smem-state-names = "stop"; 4495 4496 status = "disabled"; 4497 4498 glink-edge { 4499 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4500 IPCC_MPROC_SIGNAL_GLINK_QMP 4501 IRQ_TYPE_EDGE_RISING>; 4502 mboxes = <&ipcc IPCC_CLIENT_CDSP 4503 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4504 4505 label = "cdsp"; 4506 qcom,remote-pid = <5>; 4507 4508 fastrpc { 4509 compatible = "qcom,fastrpc"; 4510 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4511 label = "cdsp"; 4512 #address-cells = <1>; 4513 #size-cells = <0>; 4514 4515 compute-cb@1 { 4516 compatible = "qcom,fastrpc-compute-cb"; 4517 reg = <1>; 4518 iommus = <&apps_smmu 0x2141 0x04a0>, 4519 <&apps_smmu 0x2161 0x04a0>, 4520 <&apps_smmu 0x2181 0x0400>, 4521 <&apps_smmu 0x21c1 0x04a0>, 4522 <&apps_smmu 0x21e1 0x04a0>, 4523 <&apps_smmu 0x2541 0x04a0>, 4524 <&apps_smmu 0x2561 0x04a0>, 4525 <&apps_smmu 0x2581 0x0400>, 4526 <&apps_smmu 0x25c1 0x04a0>, 4527 <&apps_smmu 0x25e1 0x04a0>; 4528 dma-coherent; 4529 }; 4530 4531 compute-cb@2 { 4532 compatible = "qcom,fastrpc-compute-cb"; 4533 reg = <2>; 4534 iommus = <&apps_smmu 0x2142 0x04a0>, 4535 <&apps_smmu 0x2162 0x04a0>, 4536 <&apps_smmu 0x2182 0x0400>, 4537 <&apps_smmu 0x21c2 0x04a0>, 4538 <&apps_smmu 0x21e2 0x04a0>, 4539 <&apps_smmu 0x2542 0x04a0>, 4540 <&apps_smmu 0x2562 0x04a0>, 4541 <&apps_smmu 0x2582 0x0400>, 4542 <&apps_smmu 0x25c2 0x04a0>, 4543 <&apps_smmu 0x25e2 0x04a0>; 4544 dma-coherent; 4545 }; 4546 4547 compute-cb@3 { 4548 compatible = "qcom,fastrpc-compute-cb"; 4549 reg = <3>; 4550 iommus = <&apps_smmu 0x2143 0x04a0>, 4551 <&apps_smmu 0x2163 0x04a0>, 4552 <&apps_smmu 0x2183 0x0400>, 4553 <&apps_smmu 0x21c3 0x04a0>, 4554 <&apps_smmu 0x21e3 0x04a0>, 4555 <&apps_smmu 0x2543 0x04a0>, 4556 <&apps_smmu 0x2563 0x04a0>, 4557 <&apps_smmu 0x2583 0x0400>, 4558 <&apps_smmu 0x25c3 0x04a0>, 4559 <&apps_smmu 0x25e3 0x04a0>; 4560 dma-coherent; 4561 }; 4562 4563 compute-cb@4 { 4564 compatible = "qcom,fastrpc-compute-cb"; 4565 reg = <4>; 4566 iommus = <&apps_smmu 0x2144 0x04a0>, 4567 <&apps_smmu 0x2164 0x04a0>, 4568 <&apps_smmu 0x2184 0x0400>, 4569 <&apps_smmu 0x21c4 0x04a0>, 4570 <&apps_smmu 0x21e4 0x04a0>, 4571 <&apps_smmu 0x2544 0x04a0>, 4572 <&apps_smmu 0x2564 0x04a0>, 4573 <&apps_smmu 0x2584 0x0400>, 4574 <&apps_smmu 0x25c4 0x04a0>, 4575 <&apps_smmu 0x25e4 0x04a0>; 4576 dma-coherent; 4577 }; 4578 4579 compute-cb@5 { 4580 compatible = "qcom,fastrpc-compute-cb"; 4581 reg = <5>; 4582 iommus = <&apps_smmu 0x2145 0x04a0>, 4583 <&apps_smmu 0x2165 0x04a0>, 4584 <&apps_smmu 0x2185 0x0400>, 4585 <&apps_smmu 0x21c5 0x04a0>, 4586 <&apps_smmu 0x21e5 0x04a0>, 4587 <&apps_smmu 0x2545 0x04a0>, 4588 <&apps_smmu 0x2565 0x04a0>, 4589 <&apps_smmu 0x2585 0x0400>, 4590 <&apps_smmu 0x25c5 0x04a0>, 4591 <&apps_smmu 0x25e5 0x04a0>; 4592 dma-coherent; 4593 }; 4594 4595 compute-cb@6 { 4596 compatible = "qcom,fastrpc-compute-cb"; 4597 reg = <6>; 4598 iommus = <&apps_smmu 0x2146 0x04a0>, 4599 <&apps_smmu 0x2166 0x04a0>, 4600 <&apps_smmu 0x2186 0x0400>, 4601 <&apps_smmu 0x21c6 0x04a0>, 4602 <&apps_smmu 0x21e6 0x04a0>, 4603 <&apps_smmu 0x2546 0x04a0>, 4604 <&apps_smmu 0x2566 0x04a0>, 4605 <&apps_smmu 0x2586 0x0400>, 4606 <&apps_smmu 0x25c6 0x04a0>, 4607 <&apps_smmu 0x25e6 0x04a0>; 4608 dma-coherent; 4609 }; 4610 4611 compute-cb@7 { 4612 compatible = "qcom,fastrpc-compute-cb"; 4613 reg = <7>; 4614 iommus = <&apps_smmu 0x2147 0x04a0>, 4615 <&apps_smmu 0x2167 0x04a0>, 4616 <&apps_smmu 0x2187 0x0400>, 4617 <&apps_smmu 0x21c7 0x04a0>, 4618 <&apps_smmu 0x21e7 0x04a0>, 4619 <&apps_smmu 0x2547 0x04a0>, 4620 <&apps_smmu 0x2567 0x04a0>, 4621 <&apps_smmu 0x2587 0x0400>, 4622 <&apps_smmu 0x25c7 0x04a0>, 4623 <&apps_smmu 0x25e7 0x04a0>; 4624 dma-coherent; 4625 }; 4626 4627 compute-cb@8 { 4628 compatible = "qcom,fastrpc-compute-cb"; 4629 reg = <8>; 4630 iommus = <&apps_smmu 0x2148 0x04a0>, 4631 <&apps_smmu 0x2168 0x04a0>, 4632 <&apps_smmu 0x2188 0x0400>, 4633 <&apps_smmu 0x21c8 0x04a0>, 4634 <&apps_smmu 0x21e8 0x04a0>, 4635 <&apps_smmu 0x2548 0x04a0>, 4636 <&apps_smmu 0x2568 0x04a0>, 4637 <&apps_smmu 0x2588 0x0400>, 4638 <&apps_smmu 0x25c8 0x04a0>, 4639 <&apps_smmu 0x25e8 0x04a0>; 4640 dma-coherent; 4641 }; 4642 4643 compute-cb@9 { 4644 compatible = "qcom,fastrpc-compute-cb"; 4645 reg = <9>; 4646 iommus = <&apps_smmu 0x2149 0x04a0>, 4647 <&apps_smmu 0x2169 0x04a0>, 4648 <&apps_smmu 0x2189 0x0400>, 4649 <&apps_smmu 0x21c9 0x04a0>, 4650 <&apps_smmu 0x21e9 0x04a0>, 4651 <&apps_smmu 0x2549 0x04a0>, 4652 <&apps_smmu 0x2569 0x04a0>, 4653 <&apps_smmu 0x2589 0x0400>, 4654 <&apps_smmu 0x25c9 0x04a0>, 4655 <&apps_smmu 0x25e9 0x04a0>; 4656 dma-coherent; 4657 }; 4658 4659 compute-cb@10 { 4660 compatible = "qcom,fastrpc-compute-cb"; 4661 reg = <10>; 4662 iommus = <&apps_smmu 0x214a 0x04a0>, 4663 <&apps_smmu 0x216a 0x04a0>, 4664 <&apps_smmu 0x218a 0x0400>, 4665 <&apps_smmu 0x21ca 0x04a0>, 4666 <&apps_smmu 0x21ea 0x04a0>, 4667 <&apps_smmu 0x254a 0x04a0>, 4668 <&apps_smmu 0x256a 0x04a0>, 4669 <&apps_smmu 0x258a 0x0400>, 4670 <&apps_smmu 0x25ca 0x04a0>, 4671 <&apps_smmu 0x25ea 0x04a0>; 4672 dma-coherent; 4673 }; 4674 4675 compute-cb@11 { 4676 compatible = "qcom,fastrpc-compute-cb"; 4677 reg = <11>; 4678 iommus = <&apps_smmu 0x214b 0x04a0>, 4679 <&apps_smmu 0x216b 0x04a0>, 4680 <&apps_smmu 0x218b 0x0400>, 4681 <&apps_smmu 0x21cb 0x04a0>, 4682 <&apps_smmu 0x21eb 0x04a0>, 4683 <&apps_smmu 0x254b 0x04a0>, 4684 <&apps_smmu 0x256b 0x04a0>, 4685 <&apps_smmu 0x258b 0x0400>, 4686 <&apps_smmu 0x25cb 0x04a0>, 4687 <&apps_smmu 0x25eb 0x04a0>; 4688 dma-coherent; 4689 }; 4690 }; 4691 }; 4692 }; 4693 4694 remoteproc_cdsp1: remoteproc@2a300000 { 4695 compatible = "qcom,sa8775p-cdsp1-pas"; 4696 reg = <0x0 0x2A300000 0x0 0x10000>; 4697 4698 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 4699 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, 4700 <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>, 4701 <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>, 4702 <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>; 4703 interrupt-names = "wdog", "fatal", "ready", 4704 "handover", "stop-ack"; 4705 4706 clocks = <&rpmhcc RPMH_CXO_CLK>; 4707 clock-names = "xo"; 4708 4709 power-domains = <&rpmhpd RPMHPD_CX>, 4710 <&rpmhpd RPMHPD_MXC>, 4711 <&rpmhpd RPMHPD_NSP1>; 4712 power-domain-names = "cx", "mxc", "nsp"; 4713 4714 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 4715 &mc_virt SLAVE_EBI1 0>; 4716 4717 memory-region = <&pil_cdsp1_mem>; 4718 4719 qcom,qmp = <&aoss_qmp>; 4720 4721 qcom,smem-states = <&smp2p_cdsp1_out 0>; 4722 qcom,smem-state-names = "stop"; 4723 4724 status = "disabled"; 4725 4726 glink-edge { 4727 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 4728 IPCC_MPROC_SIGNAL_GLINK_QMP 4729 IRQ_TYPE_EDGE_RISING>; 4730 mboxes = <&ipcc IPCC_CLIENT_NSP1 4731 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4732 4733 label = "cdsp"; 4734 qcom,remote-pid = <12>; 4735 4736 fastrpc { 4737 compatible = "qcom,fastrpc"; 4738 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4739 label = "cdsp1"; 4740 #address-cells = <1>; 4741 #size-cells = <0>; 4742 4743 compute-cb@1 { 4744 compatible = "qcom,fastrpc-compute-cb"; 4745 reg = <1>; 4746 iommus = <&apps_smmu 0x2941 0x04a0>, 4747 <&apps_smmu 0x2961 0x04a0>, 4748 <&apps_smmu 0x2981 0x0400>, 4749 <&apps_smmu 0x29c1 0x04a0>, 4750 <&apps_smmu 0x29e1 0x04a0>, 4751 <&apps_smmu 0x2d41 0x04a0>, 4752 <&apps_smmu 0x2d61 0x04a0>, 4753 <&apps_smmu 0x2d81 0x0400>, 4754 <&apps_smmu 0x2dc1 0x04a0>, 4755 <&apps_smmu 0x2de1 0x04a0>; 4756 dma-coherent; 4757 }; 4758 4759 compute-cb@2 { 4760 compatible = "qcom,fastrpc-compute-cb"; 4761 reg = <2>; 4762 iommus = <&apps_smmu 0x2942 0x04a0>, 4763 <&apps_smmu 0x2962 0x04a0>, 4764 <&apps_smmu 0x2982 0x0400>, 4765 <&apps_smmu 0x29c2 0x04a0>, 4766 <&apps_smmu 0x29e2 0x04a0>, 4767 <&apps_smmu 0x2d42 0x04a0>, 4768 <&apps_smmu 0x2d62 0x04a0>, 4769 <&apps_smmu 0x2d82 0x0400>, 4770 <&apps_smmu 0x2dc2 0x04a0>, 4771 <&apps_smmu 0x2de2 0x04a0>; 4772 dma-coherent; 4773 }; 4774 4775 compute-cb@3 { 4776 compatible = "qcom,fastrpc-compute-cb"; 4777 reg = <3>; 4778 iommus = <&apps_smmu 0x2943 0x04a0>, 4779 <&apps_smmu 0x2963 0x04a0>, 4780 <&apps_smmu 0x2983 0x0400>, 4781 <&apps_smmu 0x29c3 0x04a0>, 4782 <&apps_smmu 0x29e3 0x04a0>, 4783 <&apps_smmu 0x2d43 0x04a0>, 4784 <&apps_smmu 0x2d63 0x04a0>, 4785 <&apps_smmu 0x2d83 0x0400>, 4786 <&apps_smmu 0x2dc3 0x04a0>, 4787 <&apps_smmu 0x2de3 0x04a0>; 4788 dma-coherent; 4789 }; 4790 4791 compute-cb@4 { 4792 compatible = "qcom,fastrpc-compute-cb"; 4793 reg = <4>; 4794 iommus = <&apps_smmu 0x2944 0x04a0>, 4795 <&apps_smmu 0x2964 0x04a0>, 4796 <&apps_smmu 0x2984 0x0400>, 4797 <&apps_smmu 0x29c4 0x04a0>, 4798 <&apps_smmu 0x29e4 0x04a0>, 4799 <&apps_smmu 0x2d44 0x04a0>, 4800 <&apps_smmu 0x2d64 0x04a0>, 4801 <&apps_smmu 0x2d84 0x0400>, 4802 <&apps_smmu 0x2dc4 0x04a0>, 4803 <&apps_smmu 0x2de4 0x04a0>; 4804 dma-coherent; 4805 }; 4806 4807 compute-cb@5 { 4808 compatible = "qcom,fastrpc-compute-cb"; 4809 reg = <5>; 4810 iommus = <&apps_smmu 0x2945 0x04a0>, 4811 <&apps_smmu 0x2965 0x04a0>, 4812 <&apps_smmu 0x2985 0x0400>, 4813 <&apps_smmu 0x29c5 0x04a0>, 4814 <&apps_smmu 0x29e5 0x04a0>, 4815 <&apps_smmu 0x2d45 0x04a0>, 4816 <&apps_smmu 0x2d65 0x04a0>, 4817 <&apps_smmu 0x2d85 0x0400>, 4818 <&apps_smmu 0x2dc5 0x04a0>, 4819 <&apps_smmu 0x2de5 0x04a0>; 4820 dma-coherent; 4821 }; 4822 4823 compute-cb@6 { 4824 compatible = "qcom,fastrpc-compute-cb"; 4825 reg = <6>; 4826 iommus = <&apps_smmu 0x2946 0x04a0>, 4827 <&apps_smmu 0x2966 0x04a0>, 4828 <&apps_smmu 0x2986 0x0400>, 4829 <&apps_smmu 0x29c6 0x04a0>, 4830 <&apps_smmu 0x29e6 0x04a0>, 4831 <&apps_smmu 0x2d46 0x04a0>, 4832 <&apps_smmu 0x2d66 0x04a0>, 4833 <&apps_smmu 0x2d86 0x0400>, 4834 <&apps_smmu 0x2dc6 0x04a0>, 4835 <&apps_smmu 0x2de6 0x04a0>; 4836 dma-coherent; 4837 }; 4838 4839 compute-cb@7 { 4840 compatible = "qcom,fastrpc-compute-cb"; 4841 reg = <7>; 4842 iommus = <&apps_smmu 0x2947 0x04a0>, 4843 <&apps_smmu 0x2967 0x04a0>, 4844 <&apps_smmu 0x2987 0x0400>, 4845 <&apps_smmu 0x29c7 0x04a0>, 4846 <&apps_smmu 0x29e7 0x04a0>, 4847 <&apps_smmu 0x2d47 0x04a0>, 4848 <&apps_smmu 0x2d67 0x04a0>, 4849 <&apps_smmu 0x2d87 0x0400>, 4850 <&apps_smmu 0x2dc7 0x04a0>, 4851 <&apps_smmu 0x2de7 0x04a0>; 4852 dma-coherent; 4853 }; 4854 4855 compute-cb@8 { 4856 compatible = "qcom,fastrpc-compute-cb"; 4857 reg = <8>; 4858 iommus = <&apps_smmu 0x2948 0x04a0>, 4859 <&apps_smmu 0x2968 0x04a0>, 4860 <&apps_smmu 0x2988 0x0400>, 4861 <&apps_smmu 0x29c8 0x04a0>, 4862 <&apps_smmu 0x29e8 0x04a0>, 4863 <&apps_smmu 0x2d48 0x04a0>, 4864 <&apps_smmu 0x2d68 0x04a0>, 4865 <&apps_smmu 0x2d88 0x0400>, 4866 <&apps_smmu 0x2dc8 0x04a0>, 4867 <&apps_smmu 0x2de8 0x04a0>; 4868 dma-coherent; 4869 }; 4870 4871 compute-cb@9 { 4872 compatible = "qcom,fastrpc-compute-cb"; 4873 reg = <9>; 4874 iommus = <&apps_smmu 0x2949 0x04a0>, 4875 <&apps_smmu 0x2969 0x04a0>, 4876 <&apps_smmu 0x2989 0x0400>, 4877 <&apps_smmu 0x29c9 0x04a0>, 4878 <&apps_smmu 0x29e9 0x04a0>, 4879 <&apps_smmu 0x2d49 0x04a0>, 4880 <&apps_smmu 0x2d69 0x04a0>, 4881 <&apps_smmu 0x2d89 0x0400>, 4882 <&apps_smmu 0x2dc9 0x04a0>, 4883 <&apps_smmu 0x2de9 0x04a0>; 4884 dma-coherent; 4885 }; 4886 4887 compute-cb@10 { 4888 compatible = "qcom,fastrpc-compute-cb"; 4889 reg = <10>; 4890 iommus = <&apps_smmu 0x294a 0x04a0>, 4891 <&apps_smmu 0x296a 0x04a0>, 4892 <&apps_smmu 0x298a 0x0400>, 4893 <&apps_smmu 0x29ca 0x04a0>, 4894 <&apps_smmu 0x29ea 0x04a0>, 4895 <&apps_smmu 0x2d4a 0x04a0>, 4896 <&apps_smmu 0x2d6a 0x04a0>, 4897 <&apps_smmu 0x2d8a 0x0400>, 4898 <&apps_smmu 0x2dca 0x04a0>, 4899 <&apps_smmu 0x2dea 0x04a0>; 4900 dma-coherent; 4901 }; 4902 4903 compute-cb@11 { 4904 compatible = "qcom,fastrpc-compute-cb"; 4905 reg = <11>; 4906 iommus = <&apps_smmu 0x294b 0x04a0>, 4907 <&apps_smmu 0x296b 0x04a0>, 4908 <&apps_smmu 0x298b 0x0400>, 4909 <&apps_smmu 0x29cb 0x04a0>, 4910 <&apps_smmu 0x29eb 0x04a0>, 4911 <&apps_smmu 0x2d4b 0x04a0>, 4912 <&apps_smmu 0x2d6b 0x04a0>, 4913 <&apps_smmu 0x2d8b 0x0400>, 4914 <&apps_smmu 0x2dcb 0x04a0>, 4915 <&apps_smmu 0x2deb 0x04a0>; 4916 dma-coherent; 4917 }; 4918 4919 compute-cb@12 { 4920 compatible = "qcom,fastrpc-compute-cb"; 4921 reg = <12>; 4922 iommus = <&apps_smmu 0x294c 0x04a0>, 4923 <&apps_smmu 0x296c 0x04a0>, 4924 <&apps_smmu 0x298c 0x0400>, 4925 <&apps_smmu 0x29cc 0x04a0>, 4926 <&apps_smmu 0x29ec 0x04a0>, 4927 <&apps_smmu 0x2d4c 0x04a0>, 4928 <&apps_smmu 0x2d6c 0x04a0>, 4929 <&apps_smmu 0x2d8c 0x0400>, 4930 <&apps_smmu 0x2dcc 0x04a0>, 4931 <&apps_smmu 0x2dec 0x04a0>; 4932 dma-coherent; 4933 }; 4934 4935 compute-cb@13 { 4936 compatible = "qcom,fastrpc-compute-cb"; 4937 reg = <13>; 4938 iommus = <&apps_smmu 0x294d 0x04a0>, 4939 <&apps_smmu 0x296d 0x04a0>, 4940 <&apps_smmu 0x298d 0x0400>, 4941 <&apps_smmu 0x29Cd 0x04a0>, 4942 <&apps_smmu 0x29ed 0x04a0>, 4943 <&apps_smmu 0x2d4d 0x04a0>, 4944 <&apps_smmu 0x2d6d 0x04a0>, 4945 <&apps_smmu 0x2d8d 0x0400>, 4946 <&apps_smmu 0x2dcd 0x04a0>, 4947 <&apps_smmu 0x2ded 0x04a0>; 4948 dma-coherent; 4949 }; 4950 }; 4951 }; 4952 }; 4953 4954 remoteproc_adsp: remoteproc@30000000 { 4955 compatible = "qcom,sa8775p-adsp-pas"; 4956 reg = <0x0 0x30000000 0x0 0x100>; 4957 4958 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4959 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4960 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4961 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4962 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4963 interrupt-names = "wdog", "fatal", "ready", "handover", 4964 "stop-ack"; 4965 4966 clocks = <&rpmhcc RPMH_CXO_CLK>; 4967 clock-names = "xo"; 4968 4969 power-domains = <&rpmhpd RPMHPD_LCX>, 4970 <&rpmhpd RPMHPD_LMX>; 4971 power-domain-names = "lcx", "lmx"; 4972 4973 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 4974 4975 memory-region = <&pil_adsp_mem>; 4976 4977 qcom,qmp = <&aoss_qmp>; 4978 4979 qcom,smem-states = <&smp2p_adsp_out 0>; 4980 qcom,smem-state-names = "stop"; 4981 4982 status = "disabled"; 4983 4984 remoteproc_adsp_glink: glink-edge { 4985 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4986 IPCC_MPROC_SIGNAL_GLINK_QMP 4987 IRQ_TYPE_EDGE_RISING>; 4988 mboxes = <&ipcc IPCC_CLIENT_LPASS 4989 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4990 4991 label = "lpass"; 4992 qcom,remote-pid = <2>; 4993 4994 fastrpc { 4995 compatible = "qcom,fastrpc"; 4996 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4997 label = "adsp"; 4998 memory-region = <&adsp_rpc_remote_heap_mem>; 4999 qcom,vmids = <QCOM_SCM_VMID_LPASS 5000 QCOM_SCM_VMID_ADSP_HEAP>; 5001 #address-cells = <1>; 5002 #size-cells = <0>; 5003 5004 compute-cb@3 { 5005 compatible = "qcom,fastrpc-compute-cb"; 5006 reg = <3>; 5007 iommus = <&apps_smmu 0x3003 0x0>; 5008 dma-coherent; 5009 }; 5010 5011 compute-cb@4 { 5012 compatible = "qcom,fastrpc-compute-cb"; 5013 reg = <4>; 5014 iommus = <&apps_smmu 0x3004 0x0>; 5015 dma-coherent; 5016 }; 5017 5018 compute-cb@5 { 5019 compatible = "qcom,fastrpc-compute-cb"; 5020 reg = <5>; 5021 iommus = <&apps_smmu 0x3005 0x0>; 5022 qcom,nsessions = <5>; 5023 dma-coherent; 5024 }; 5025 }; 5026 }; 5027 }; 5028 }; 5029 5030 thermal-zones { 5031 aoss-0-thermal { 5032 thermal-sensors = <&tsens0 0>; 5033 5034 trips { 5035 trip-point0 { 5036 temperature = <105000>; 5037 hysteresis = <5000>; 5038 type = "passive"; 5039 }; 5040 5041 trip-point1 { 5042 temperature = <115000>; 5043 hysteresis = <5000>; 5044 type = "passive"; 5045 }; 5046 }; 5047 }; 5048 5049 cpu-0-0-0-thermal { 5050 polling-delay-passive = <10>; 5051 5052 thermal-sensors = <&tsens0 1>; 5053 5054 trips { 5055 trip-point0 { 5056 temperature = <105000>; 5057 hysteresis = <5000>; 5058 type = "passive"; 5059 }; 5060 5061 trip-point1 { 5062 temperature = <115000>; 5063 hysteresis = <5000>; 5064 type = "passive"; 5065 }; 5066 }; 5067 }; 5068 5069 cpu-0-1-0-thermal { 5070 polling-delay-passive = <10>; 5071 5072 thermal-sensors = <&tsens0 2>; 5073 5074 trips { 5075 trip-point0 { 5076 temperature = <105000>; 5077 hysteresis = <5000>; 5078 type = "passive"; 5079 }; 5080 5081 trip-point1 { 5082 temperature = <115000>; 5083 hysteresis = <5000>; 5084 type = "passive"; 5085 }; 5086 }; 5087 }; 5088 5089 cpu-0-2-0-thermal { 5090 polling-delay-passive = <10>; 5091 5092 thermal-sensors = <&tsens0 3>; 5093 5094 trips { 5095 trip-point0 { 5096 temperature = <105000>; 5097 hysteresis = <5000>; 5098 type = "passive"; 5099 }; 5100 5101 trip-point1 { 5102 temperature = <115000>; 5103 hysteresis = <5000>; 5104 type = "passive"; 5105 }; 5106 }; 5107 }; 5108 5109 cpu-0-3-0-thermal { 5110 polling-delay-passive = <10>; 5111 5112 thermal-sensors = <&tsens0 4>; 5113 5114 trips { 5115 trip-point0 { 5116 temperature = <105000>; 5117 hysteresis = <5000>; 5118 type = "passive"; 5119 }; 5120 5121 trip-point1 { 5122 temperature = <115000>; 5123 hysteresis = <5000>; 5124 type = "passive"; 5125 }; 5126 }; 5127 }; 5128 5129 gpuss-0-thermal { 5130 polling-delay-passive = <10>; 5131 5132 thermal-sensors = <&tsens0 5>; 5133 5134 trips { 5135 trip-point0 { 5136 temperature = <105000>; 5137 hysteresis = <5000>; 5138 type = "passive"; 5139 }; 5140 5141 trip-point1 { 5142 temperature = <115000>; 5143 hysteresis = <5000>; 5144 type = "passive"; 5145 }; 5146 }; 5147 }; 5148 5149 gpuss-1-thermal { 5150 polling-delay-passive = <10>; 5151 5152 thermal-sensors = <&tsens0 6>; 5153 5154 trips { 5155 trip-point0 { 5156 temperature = <105000>; 5157 hysteresis = <5000>; 5158 type = "passive"; 5159 }; 5160 5161 trip-point1 { 5162 temperature = <115000>; 5163 hysteresis = <5000>; 5164 type = "passive"; 5165 }; 5166 }; 5167 }; 5168 5169 gpuss-2-thermal { 5170 polling-delay-passive = <10>; 5171 5172 thermal-sensors = <&tsens0 7>; 5173 5174 trips { 5175 trip-point0 { 5176 temperature = <105000>; 5177 hysteresis = <5000>; 5178 type = "passive"; 5179 }; 5180 5181 trip-point1 { 5182 temperature = <115000>; 5183 hysteresis = <5000>; 5184 type = "passive"; 5185 }; 5186 }; 5187 }; 5188 5189 audio-thermal { 5190 thermal-sensors = <&tsens0 8>; 5191 5192 trips { 5193 trip-point0 { 5194 temperature = <105000>; 5195 hysteresis = <5000>; 5196 type = "passive"; 5197 }; 5198 5199 trip-point1 { 5200 temperature = <115000>; 5201 hysteresis = <5000>; 5202 type = "passive"; 5203 }; 5204 }; 5205 }; 5206 5207 camss-0-thermal { 5208 thermal-sensors = <&tsens0 9>; 5209 5210 trips { 5211 trip-point0 { 5212 temperature = <105000>; 5213 hysteresis = <5000>; 5214 type = "passive"; 5215 }; 5216 5217 trip-point1 { 5218 temperature = <115000>; 5219 hysteresis = <5000>; 5220 type = "passive"; 5221 }; 5222 }; 5223 }; 5224 5225 pcie-0-thermal { 5226 thermal-sensors = <&tsens0 10>; 5227 5228 trips { 5229 trip-point0 { 5230 temperature = <105000>; 5231 hysteresis = <5000>; 5232 type = "passive"; 5233 }; 5234 5235 trip-point1 { 5236 temperature = <115000>; 5237 hysteresis = <5000>; 5238 type = "passive"; 5239 }; 5240 }; 5241 }; 5242 5243 cpuss-0-0-thermal { 5244 thermal-sensors = <&tsens0 11>; 5245 5246 trips { 5247 trip-point0 { 5248 temperature = <105000>; 5249 hysteresis = <5000>; 5250 type = "passive"; 5251 }; 5252 5253 trip-point1 { 5254 temperature = <115000>; 5255 hysteresis = <5000>; 5256 type = "passive"; 5257 }; 5258 }; 5259 }; 5260 5261 aoss-1-thermal { 5262 thermal-sensors = <&tsens1 0>; 5263 5264 trips { 5265 trip-point0 { 5266 temperature = <105000>; 5267 hysteresis = <5000>; 5268 type = "passive"; 5269 }; 5270 5271 trip-point1 { 5272 temperature = <115000>; 5273 hysteresis = <5000>; 5274 type = "passive"; 5275 }; 5276 }; 5277 }; 5278 5279 cpu-0-0-1-thermal { 5280 polling-delay-passive = <10>; 5281 5282 thermal-sensors = <&tsens1 1>; 5283 5284 trips { 5285 trip-point0 { 5286 temperature = <105000>; 5287 hysteresis = <5000>; 5288 type = "passive"; 5289 }; 5290 5291 trip-point1 { 5292 temperature = <115000>; 5293 hysteresis = <5000>; 5294 type = "passive"; 5295 }; 5296 }; 5297 }; 5298 5299 cpu-0-1-1-thermal { 5300 polling-delay-passive = <10>; 5301 5302 thermal-sensors = <&tsens1 2>; 5303 5304 trips { 5305 trip-point0 { 5306 temperature = <105000>; 5307 hysteresis = <5000>; 5308 type = "passive"; 5309 }; 5310 5311 trip-point1 { 5312 temperature = <115000>; 5313 hysteresis = <5000>; 5314 type = "passive"; 5315 }; 5316 }; 5317 }; 5318 5319 cpu-0-2-1-thermal { 5320 polling-delay-passive = <10>; 5321 5322 thermal-sensors = <&tsens1 3>; 5323 5324 trips { 5325 trip-point0 { 5326 temperature = <105000>; 5327 hysteresis = <5000>; 5328 type = "passive"; 5329 }; 5330 5331 trip-point1 { 5332 temperature = <115000>; 5333 hysteresis = <5000>; 5334 type = "passive"; 5335 }; 5336 }; 5337 }; 5338 5339 cpu-0-3-1-thermal { 5340 polling-delay-passive = <10>; 5341 5342 thermal-sensors = <&tsens1 4>; 5343 5344 trips { 5345 trip-point0 { 5346 temperature = <105000>; 5347 hysteresis = <5000>; 5348 type = "passive"; 5349 }; 5350 5351 trip-point1 { 5352 temperature = <115000>; 5353 hysteresis = <5000>; 5354 type = "passive"; 5355 }; 5356 }; 5357 }; 5358 5359 gpuss-3-thermal { 5360 polling-delay-passive = <10>; 5361 5362 thermal-sensors = <&tsens1 5>; 5363 5364 trips { 5365 trip-point0 { 5366 temperature = <105000>; 5367 hysteresis = <5000>; 5368 type = "passive"; 5369 }; 5370 5371 trip-point1 { 5372 temperature = <115000>; 5373 hysteresis = <5000>; 5374 type = "passive"; 5375 }; 5376 }; 5377 }; 5378 5379 gpuss-4-thermal { 5380 polling-delay-passive = <10>; 5381 5382 thermal-sensors = <&tsens1 6>; 5383 5384 trips { 5385 trip-point0 { 5386 temperature = <105000>; 5387 hysteresis = <5000>; 5388 type = "passive"; 5389 }; 5390 5391 trip-point1 { 5392 temperature = <115000>; 5393 hysteresis = <5000>; 5394 type = "passive"; 5395 }; 5396 }; 5397 }; 5398 5399 gpuss-5-thermal { 5400 polling-delay-passive = <10>; 5401 5402 thermal-sensors = <&tsens1 7>; 5403 5404 trips { 5405 trip-point0 { 5406 temperature = <105000>; 5407 hysteresis = <5000>; 5408 type = "passive"; 5409 }; 5410 5411 trip-point1 { 5412 temperature = <115000>; 5413 hysteresis = <5000>; 5414 type = "passive"; 5415 }; 5416 }; 5417 }; 5418 5419 video-thermal { 5420 thermal-sensors = <&tsens1 8>; 5421 5422 trips { 5423 trip-point0 { 5424 temperature = <105000>; 5425 hysteresis = <5000>; 5426 type = "passive"; 5427 }; 5428 5429 trip-point1 { 5430 temperature = <115000>; 5431 hysteresis = <5000>; 5432 type = "passive"; 5433 }; 5434 }; 5435 }; 5436 5437 camss-1-thermal { 5438 thermal-sensors = <&tsens1 9>; 5439 5440 trips { 5441 trip-point0 { 5442 temperature = <105000>; 5443 hysteresis = <5000>; 5444 type = "passive"; 5445 }; 5446 5447 trip-point1 { 5448 temperature = <115000>; 5449 hysteresis = <5000>; 5450 type = "passive"; 5451 }; 5452 }; 5453 }; 5454 5455 pcie-1-thermal { 5456 thermal-sensors = <&tsens1 10>; 5457 5458 trips { 5459 trip-point0 { 5460 temperature = <105000>; 5461 hysteresis = <5000>; 5462 type = "passive"; 5463 }; 5464 5465 trip-point1 { 5466 temperature = <115000>; 5467 hysteresis = <5000>; 5468 type = "passive"; 5469 }; 5470 }; 5471 }; 5472 5473 cpuss-0-1-thermal { 5474 thermal-sensors = <&tsens1 11>; 5475 5476 trips { 5477 trip-point0 { 5478 temperature = <105000>; 5479 hysteresis = <5000>; 5480 type = "passive"; 5481 }; 5482 5483 trip-point1 { 5484 temperature = <115000>; 5485 hysteresis = <5000>; 5486 type = "passive"; 5487 }; 5488 }; 5489 }; 5490 5491 aoss-2-thermal { 5492 thermal-sensors = <&tsens2 0>; 5493 5494 trips { 5495 trip-point0 { 5496 temperature = <105000>; 5497 hysteresis = <5000>; 5498 type = "passive"; 5499 }; 5500 5501 trip-point1 { 5502 temperature = <115000>; 5503 hysteresis = <5000>; 5504 type = "passive"; 5505 }; 5506 }; 5507 }; 5508 5509 cpu-1-0-0-thermal { 5510 polling-delay-passive = <10>; 5511 5512 thermal-sensors = <&tsens2 1>; 5513 5514 trips { 5515 trip-point0 { 5516 temperature = <105000>; 5517 hysteresis = <5000>; 5518 type = "passive"; 5519 }; 5520 5521 trip-point1 { 5522 temperature = <115000>; 5523 hysteresis = <5000>; 5524 type = "passive"; 5525 }; 5526 }; 5527 }; 5528 5529 cpu-1-1-0-thermal { 5530 polling-delay-passive = <10>; 5531 5532 thermal-sensors = <&tsens2 2>; 5533 5534 trips { 5535 trip-point0 { 5536 temperature = <105000>; 5537 hysteresis = <5000>; 5538 type = "passive"; 5539 }; 5540 5541 trip-point1 { 5542 temperature = <115000>; 5543 hysteresis = <5000>; 5544 type = "passive"; 5545 }; 5546 }; 5547 }; 5548 5549 cpu-1-2-0-thermal { 5550 polling-delay-passive = <10>; 5551 5552 thermal-sensors = <&tsens2 3>; 5553 5554 trips { 5555 trip-point0 { 5556 temperature = <105000>; 5557 hysteresis = <5000>; 5558 type = "passive"; 5559 }; 5560 5561 trip-point1 { 5562 temperature = <115000>; 5563 hysteresis = <5000>; 5564 type = "passive"; 5565 }; 5566 }; 5567 }; 5568 5569 cpu-1-3-0-thermal { 5570 polling-delay-passive = <10>; 5571 5572 thermal-sensors = <&tsens2 4>; 5573 5574 trips { 5575 trip-point0 { 5576 temperature = <105000>; 5577 hysteresis = <5000>; 5578 type = "passive"; 5579 }; 5580 5581 trip-point1 { 5582 temperature = <115000>; 5583 hysteresis = <5000>; 5584 type = "passive"; 5585 }; 5586 }; 5587 }; 5588 5589 nsp-0-0-0-thermal { 5590 polling-delay-passive = <10>; 5591 5592 thermal-sensors = <&tsens2 5>; 5593 5594 trips { 5595 trip-point0 { 5596 temperature = <105000>; 5597 hysteresis = <5000>; 5598 type = "passive"; 5599 }; 5600 5601 trip-point1 { 5602 temperature = <115000>; 5603 hysteresis = <5000>; 5604 type = "passive"; 5605 }; 5606 }; 5607 }; 5608 5609 nsp-0-1-0-thermal { 5610 polling-delay-passive = <10>; 5611 5612 thermal-sensors = <&tsens2 6>; 5613 5614 trips { 5615 trip-point0 { 5616 temperature = <105000>; 5617 hysteresis = <5000>; 5618 type = "passive"; 5619 }; 5620 5621 trip-point1 { 5622 temperature = <115000>; 5623 hysteresis = <5000>; 5624 type = "passive"; 5625 }; 5626 }; 5627 }; 5628 5629 nsp-0-2-0-thermal { 5630 polling-delay-passive = <10>; 5631 5632 thermal-sensors = <&tsens2 7>; 5633 5634 trips { 5635 trip-point0 { 5636 temperature = <105000>; 5637 hysteresis = <5000>; 5638 type = "passive"; 5639 }; 5640 5641 trip-point1 { 5642 temperature = <115000>; 5643 hysteresis = <5000>; 5644 type = "passive"; 5645 }; 5646 }; 5647 }; 5648 5649 nsp-1-0-0-thermal { 5650 polling-delay-passive = <10>; 5651 5652 thermal-sensors = <&tsens2 8>; 5653 5654 trips { 5655 trip-point0 { 5656 temperature = <105000>; 5657 hysteresis = <5000>; 5658 type = "passive"; 5659 }; 5660 5661 trip-point1 { 5662 temperature = <115000>; 5663 hysteresis = <5000>; 5664 type = "passive"; 5665 }; 5666 }; 5667 }; 5668 5669 nsp-1-1-0-thermal { 5670 polling-delay-passive = <10>; 5671 5672 thermal-sensors = <&tsens2 9>; 5673 5674 trips { 5675 trip-point0 { 5676 temperature = <105000>; 5677 hysteresis = <5000>; 5678 type = "passive"; 5679 }; 5680 5681 trip-point1 { 5682 temperature = <115000>; 5683 hysteresis = <5000>; 5684 type = "passive"; 5685 }; 5686 }; 5687 }; 5688 5689 nsp-1-2-0-thermal { 5690 polling-delay-passive = <10>; 5691 5692 thermal-sensors = <&tsens2 10>; 5693 5694 trips { 5695 trip-point0 { 5696 temperature = <105000>; 5697 hysteresis = <5000>; 5698 type = "passive"; 5699 }; 5700 5701 trip-point1 { 5702 temperature = <115000>; 5703 hysteresis = <5000>; 5704 type = "passive"; 5705 }; 5706 }; 5707 }; 5708 5709 ddrss-0-thermal { 5710 thermal-sensors = <&tsens2 11>; 5711 5712 trips { 5713 trip-point0 { 5714 temperature = <105000>; 5715 hysteresis = <5000>; 5716 type = "passive"; 5717 }; 5718 5719 trip-point1 { 5720 temperature = <115000>; 5721 hysteresis = <5000>; 5722 type = "passive"; 5723 }; 5724 }; 5725 }; 5726 5727 cpuss-1-0-thermal { 5728 thermal-sensors = <&tsens2 12>; 5729 5730 trips { 5731 trip-point0 { 5732 temperature = <105000>; 5733 hysteresis = <5000>; 5734 type = "passive"; 5735 }; 5736 5737 trip-point1 { 5738 temperature = <115000>; 5739 hysteresis = <5000>; 5740 type = "passive"; 5741 }; 5742 }; 5743 }; 5744 5745 aoss-3-thermal { 5746 thermal-sensors = <&tsens3 0>; 5747 5748 trips { 5749 trip-point0 { 5750 temperature = <105000>; 5751 hysteresis = <5000>; 5752 type = "passive"; 5753 }; 5754 5755 trip-point1 { 5756 temperature = <115000>; 5757 hysteresis = <5000>; 5758 type = "passive"; 5759 }; 5760 }; 5761 }; 5762 5763 cpu-1-0-1-thermal { 5764 polling-delay-passive = <10>; 5765 5766 thermal-sensors = <&tsens3 1>; 5767 5768 trips { 5769 trip-point0 { 5770 temperature = <105000>; 5771 hysteresis = <5000>; 5772 type = "passive"; 5773 }; 5774 5775 trip-point1 { 5776 temperature = <115000>; 5777 hysteresis = <5000>; 5778 type = "passive"; 5779 }; 5780 }; 5781 }; 5782 5783 cpu-1-1-1-thermal { 5784 polling-delay-passive = <10>; 5785 5786 thermal-sensors = <&tsens3 2>; 5787 5788 trips { 5789 trip-point0 { 5790 temperature = <105000>; 5791 hysteresis = <5000>; 5792 type = "passive"; 5793 }; 5794 5795 trip-point1 { 5796 temperature = <115000>; 5797 hysteresis = <5000>; 5798 type = "passive"; 5799 }; 5800 }; 5801 }; 5802 5803 cpu-1-2-1-thermal { 5804 polling-delay-passive = <10>; 5805 5806 thermal-sensors = <&tsens3 3>; 5807 5808 trips { 5809 trip-point0 { 5810 temperature = <105000>; 5811 hysteresis = <5000>; 5812 type = "passive"; 5813 }; 5814 5815 trip-point1 { 5816 temperature = <115000>; 5817 hysteresis = <5000>; 5818 type = "passive"; 5819 }; 5820 }; 5821 }; 5822 5823 cpu-1-3-1-thermal { 5824 polling-delay-passive = <10>; 5825 5826 thermal-sensors = <&tsens3 4>; 5827 5828 trips { 5829 trip-point0 { 5830 temperature = <105000>; 5831 hysteresis = <5000>; 5832 type = "passive"; 5833 }; 5834 5835 trip-point1 { 5836 temperature = <115000>; 5837 hysteresis = <5000>; 5838 type = "passive"; 5839 }; 5840 }; 5841 }; 5842 5843 nsp-0-0-1-thermal { 5844 polling-delay-passive = <10>; 5845 5846 thermal-sensors = <&tsens3 5>; 5847 5848 trips { 5849 trip-point0 { 5850 temperature = <105000>; 5851 hysteresis = <5000>; 5852 type = "passive"; 5853 }; 5854 5855 trip-point1 { 5856 temperature = <115000>; 5857 hysteresis = <5000>; 5858 type = "passive"; 5859 }; 5860 }; 5861 }; 5862 5863 nsp-0-1-1-thermal { 5864 polling-delay-passive = <10>; 5865 5866 thermal-sensors = <&tsens3 6>; 5867 5868 trips { 5869 trip-point0 { 5870 temperature = <105000>; 5871 hysteresis = <5000>; 5872 type = "passive"; 5873 }; 5874 5875 trip-point1 { 5876 temperature = <115000>; 5877 hysteresis = <5000>; 5878 type = "passive"; 5879 }; 5880 }; 5881 }; 5882 5883 nsp-0-2-1-thermal { 5884 polling-delay-passive = <10>; 5885 5886 thermal-sensors = <&tsens3 7>; 5887 5888 trips { 5889 trip-point0 { 5890 temperature = <105000>; 5891 hysteresis = <5000>; 5892 type = "passive"; 5893 }; 5894 5895 trip-point1 { 5896 temperature = <115000>; 5897 hysteresis = <5000>; 5898 type = "passive"; 5899 }; 5900 }; 5901 }; 5902 5903 nsp-1-0-1-thermal { 5904 polling-delay-passive = <10>; 5905 5906 thermal-sensors = <&tsens3 8>; 5907 5908 trips { 5909 trip-point0 { 5910 temperature = <105000>; 5911 hysteresis = <5000>; 5912 type = "passive"; 5913 }; 5914 5915 trip-point1 { 5916 temperature = <115000>; 5917 hysteresis = <5000>; 5918 type = "passive"; 5919 }; 5920 }; 5921 }; 5922 5923 nsp-1-1-1-thermal { 5924 polling-delay-passive = <10>; 5925 5926 thermal-sensors = <&tsens3 9>; 5927 5928 trips { 5929 trip-point0 { 5930 temperature = <105000>; 5931 hysteresis = <5000>; 5932 type = "passive"; 5933 }; 5934 5935 trip-point1 { 5936 temperature = <115000>; 5937 hysteresis = <5000>; 5938 type = "passive"; 5939 }; 5940 }; 5941 }; 5942 5943 nsp-1-2-1-thermal { 5944 polling-delay-passive = <10>; 5945 5946 thermal-sensors = <&tsens3 10>; 5947 5948 trips { 5949 trip-point0 { 5950 temperature = <105000>; 5951 hysteresis = <5000>; 5952 type = "passive"; 5953 }; 5954 5955 trip-point1 { 5956 temperature = <115000>; 5957 hysteresis = <5000>; 5958 type = "passive"; 5959 }; 5960 }; 5961 }; 5962 5963 ddrss-1-thermal { 5964 thermal-sensors = <&tsens3 11>; 5965 5966 trips { 5967 trip-point0 { 5968 temperature = <105000>; 5969 hysteresis = <5000>; 5970 type = "passive"; 5971 }; 5972 5973 trip-point1 { 5974 temperature = <115000>; 5975 hysteresis = <5000>; 5976 type = "passive"; 5977 }; 5978 }; 5979 }; 5980 5981 cpuss-1-1-thermal { 5982 thermal-sensors = <&tsens3 12>; 5983 5984 trips { 5985 trip-point0 { 5986 temperature = <105000>; 5987 hysteresis = <5000>; 5988 type = "passive"; 5989 }; 5990 5991 trip-point1 { 5992 temperature = <115000>; 5993 hysteresis = <5000>; 5994 type = "passive"; 5995 }; 5996 }; 5997 }; 5998 }; 5999 6000 arch_timer: timer { 6001 compatible = "arm,armv8-timer"; 6002 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6003 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6004 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6005 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6006 }; 6007 6008 pcie0: pcie@1c00000 { 6009 compatible = "qcom,pcie-sa8775p"; 6010 reg = <0x0 0x01c00000 0x0 0x3000>, 6011 <0x0 0x40000000 0x0 0xf20>, 6012 <0x0 0x40000f20 0x0 0xa8>, 6013 <0x0 0x40001000 0x0 0x4000>, 6014 <0x0 0x40100000 0x0 0x100000>, 6015 <0x0 0x01c03000 0x0 0x1000>; 6016 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 6017 device_type = "pci"; 6018 6019 #address-cells = <3>; 6020 #size-cells = <2>; 6021 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 6022 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 6023 bus-range = <0x00 0xff>; 6024 6025 dma-coherent; 6026 6027 linux,pci-domain = <0>; 6028 num-lanes = <2>; 6029 6030 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 6031 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 6032 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 6033 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 6034 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 6035 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 6036 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 6037 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 6038 interrupt-names = "msi0", "msi1", "msi2", "msi3", 6039 "msi4", "msi5", "msi6", "msi7"; 6040 #interrupt-cells = <1>; 6041 interrupt-map-mask = <0 0 0 0x7>; 6042 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 6043 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 6044 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 6045 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 6046 6047 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 6048 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 6049 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 6050 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 6051 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 6052 6053 clock-names = "aux", 6054 "cfg", 6055 "bus_master", 6056 "bus_slave", 6057 "slave_q2a"; 6058 6059 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 6060 assigned-clock-rates = <19200000>; 6061 6062 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 6063 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 6064 interconnect-names = "pcie-mem", "cpu-pcie"; 6065 6066 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 6067 <0x100 &pcie_smmu 0x0001 0x1>; 6068 6069 resets = <&gcc GCC_PCIE_0_BCR>; 6070 reset-names = "pci"; 6071 power-domains = <&gcc PCIE_0_GDSC>; 6072 6073 phys = <&pcie0_phy>; 6074 phy-names = "pciephy"; 6075 6076 status = "disabled"; 6077 6078 pcieport0: pcie@0 { 6079 device_type = "pci"; 6080 reg = <0x0 0x0 0x0 0x0 0x0>; 6081 bus-range = <0x01 0xff>; 6082 6083 #address-cells = <3>; 6084 #size-cells = <2>; 6085 ranges; 6086 }; 6087 }; 6088 6089 pcie0_ep: pcie-ep@1c00000 { 6090 compatible = "qcom,sa8775p-pcie-ep"; 6091 reg = <0x0 0x01c00000 0x0 0x3000>, 6092 <0x0 0x40000000 0x0 0xf20>, 6093 <0x0 0x40000f20 0x0 0xa8>, 6094 <0x0 0x40001000 0x0 0x4000>, 6095 <0x0 0x40200000 0x0 0x100000>, 6096 <0x0 0x01c03000 0x0 0x1000>, 6097 <0x0 0x40005000 0x0 0x2000>; 6098 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 6099 "mmio", "dma"; 6100 6101 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 6102 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 6103 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 6104 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 6105 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 6106 6107 clock-names = "aux", 6108 "cfg", 6109 "bus_master", 6110 "bus_slave", 6111 "slave_q2a"; 6112 6113 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 6114 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 6115 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; 6116 6117 interrupt-names = "global", "doorbell", "dma"; 6118 6119 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 6120 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 6121 interconnect-names = "pcie-mem", "cpu-pcie"; 6122 6123 dma-coherent; 6124 iommus = <&pcie_smmu 0x0000 0x7f>; 6125 resets = <&gcc GCC_PCIE_0_BCR>; 6126 reset-names = "core"; 6127 power-domains = <&gcc PCIE_0_GDSC>; 6128 phys = <&pcie0_phy>; 6129 phy-names = "pciephy"; 6130 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ 6131 num-lanes = <2>; 6132 linux,pci-domain = <0>; 6133 6134 status = "disabled"; 6135 }; 6136 6137 pcie0_phy: phy@1c04000 { 6138 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 6139 reg = <0x0 0x1c04000 0x0 0x2000>; 6140 6141 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 6142 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 6143 <&gcc GCC_PCIE_CLKREF_EN>, 6144 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 6145 <&gcc GCC_PCIE_0_PIPE_CLK>, 6146 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, 6147 <&gcc GCC_PCIE_0_PHY_AUX_CLK>; 6148 6149 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 6150 "pipediv2", "phy_aux"; 6151 6152 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 6153 assigned-clock-rates = <100000000>; 6154 6155 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 6156 reset-names = "phy"; 6157 6158 #clock-cells = <0>; 6159 clock-output-names = "pcie_0_pipe_clk"; 6160 6161 #phy-cells = <0>; 6162 6163 status = "disabled"; 6164 }; 6165 6166 pcie1: pcie@1c10000 { 6167 compatible = "qcom,pcie-sa8775p"; 6168 reg = <0x0 0x01c10000 0x0 0x3000>, 6169 <0x0 0x60000000 0x0 0xf20>, 6170 <0x0 0x60000f20 0x0 0xa8>, 6171 <0x0 0x60001000 0x0 0x4000>, 6172 <0x0 0x60100000 0x0 0x100000>, 6173 <0x0 0x01c13000 0x0 0x1000>; 6174 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 6175 device_type = "pci"; 6176 6177 #address-cells = <3>; 6178 #size-cells = <2>; 6179 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 6180 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 6181 bus-range = <0x00 0xff>; 6182 6183 dma-coherent; 6184 6185 linux,pci-domain = <1>; 6186 num-lanes = <4>; 6187 6188 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 6189 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 6190 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 6191 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 6192 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 6193 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 6194 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 6195 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 6196 interrupt-names = "msi0", "msi1", "msi2", "msi3", 6197 "msi4", "msi5", "msi6", "msi7"; 6198 #interrupt-cells = <1>; 6199 interrupt-map-mask = <0 0 0 0x7>; 6200 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 6201 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 6202 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 6203 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 6204 6205 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 6206 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 6207 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 6208 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 6209 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 6210 6211 clock-names = "aux", 6212 "cfg", 6213 "bus_master", 6214 "bus_slave", 6215 "slave_q2a"; 6216 6217 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 6218 assigned-clock-rates = <19200000>; 6219 6220 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 6221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 6222 interconnect-names = "pcie-mem", "cpu-pcie"; 6223 6224 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 6225 <0x100 &pcie_smmu 0x0081 0x1>; 6226 6227 resets = <&gcc GCC_PCIE_1_BCR>; 6228 reset-names = "pci"; 6229 power-domains = <&gcc PCIE_1_GDSC>; 6230 6231 phys = <&pcie1_phy>; 6232 phy-names = "pciephy"; 6233 6234 status = "disabled"; 6235 6236 pcie@0 { 6237 device_type = "pci"; 6238 reg = <0x0 0x0 0x0 0x0 0x0>; 6239 bus-range = <0x01 0xff>; 6240 6241 #address-cells = <3>; 6242 #size-cells = <2>; 6243 ranges; 6244 }; 6245 }; 6246 6247 pcie1_ep: pcie-ep@1c10000 { 6248 compatible = "qcom,sa8775p-pcie-ep"; 6249 reg = <0x0 0x01c10000 0x0 0x3000>, 6250 <0x0 0x60000000 0x0 0xf20>, 6251 <0x0 0x60000f20 0x0 0xa8>, 6252 <0x0 0x60001000 0x0 0x4000>, 6253 <0x0 0x60200000 0x0 0x100000>, 6254 <0x0 0x01c13000 0x0 0x1000>, 6255 <0x0 0x60005000 0x0 0x2000>; 6256 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 6257 "mmio", "dma"; 6258 6259 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 6260 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 6261 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 6262 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 6263 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 6264 6265 clock-names = "aux", 6266 "cfg", 6267 "bus_master", 6268 "bus_slave", 6269 "slave_q2a"; 6270 6271 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 6272 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 6273 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 6274 6275 interrupt-names = "global", "doorbell", "dma"; 6276 6277 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 6278 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 6279 interconnect-names = "pcie-mem", "cpu-pcie"; 6280 6281 dma-coherent; 6282 iommus = <&pcie_smmu 0x80 0x7f>; 6283 resets = <&gcc GCC_PCIE_1_BCR>; 6284 reset-names = "core"; 6285 power-domains = <&gcc PCIE_1_GDSC>; 6286 phys = <&pcie1_phy>; 6287 phy-names = "pciephy"; 6288 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ 6289 num-lanes = <4>; 6290 linux,pci-domain = <1>; 6291 6292 status = "disabled"; 6293 }; 6294 6295 pcie1_phy: phy@1c14000 { 6296 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 6297 reg = <0x0 0x1c14000 0x0 0x4000>; 6298 6299 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 6300 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 6301 <&gcc GCC_PCIE_CLKREF_EN>, 6302 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 6303 <&gcc GCC_PCIE_1_PIPE_CLK>, 6304 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, 6305 <&gcc GCC_PCIE_1_PHY_AUX_CLK>; 6306 6307 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 6308 "pipediv2", "phy_aux"; 6309 6310 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 6311 assigned-clock-rates = <100000000>; 6312 6313 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 6314 reset-names = "phy"; 6315 6316 #clock-cells = <0>; 6317 clock-output-names = "pcie_1_pipe_clk"; 6318 6319 #phy-cells = <0>; 6320 6321 status = "disabled"; 6322 }; 6323}; 6324