1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#include <dt-bindings/interconnect/qcom,icc.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 11#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/power/qcom,rpmhpd.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19 20/ { 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 clocks { 27 xo_board_clk: xo-board-clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 }; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "qcom,kryo"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 qcom,freq-domain = <&cpufreq_hw 0>; 48 next-level-cache = <&l2_0>; 49 capacity-dmips-mhz = <1024>; 50 dynamic-power-coefficient = <100>; 51 l2_0: l2-cache { 52 compatible = "cache"; 53 cache-level = <2>; 54 cache-unified; 55 next-level-cache = <&l3_0>; 56 l3_0: l3-cache { 57 compatible = "cache"; 58 cache-level = <3>; 59 cache-unified; 60 }; 61 }; 62 }; 63 64 cpu1: cpu@100 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo"; 67 reg = <0x0 0x100>; 68 enable-method = "psci"; 69 qcom,freq-domain = <&cpufreq_hw 0>; 70 next-level-cache = <&l2_1>; 71 capacity-dmips-mhz = <1024>; 72 dynamic-power-coefficient = <100>; 73 l2_1: l2-cache { 74 compatible = "cache"; 75 cache-level = <2>; 76 cache-unified; 77 next-level-cache = <&l3_0>; 78 }; 79 }; 80 81 cpu2: cpu@200 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo"; 84 reg = <0x0 0x200>; 85 enable-method = "psci"; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 next-level-cache = <&l2_2>; 88 capacity-dmips-mhz = <1024>; 89 dynamic-power-coefficient = <100>; 90 l2_2: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 next-level-cache = <&l3_0>; 95 }; 96 }; 97 98 cpu3: cpu@300 { 99 device_type = "cpu"; 100 compatible = "qcom,kryo"; 101 reg = <0x0 0x300>; 102 enable-method = "psci"; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 next-level-cache = <&l2_3>; 105 capacity-dmips-mhz = <1024>; 106 dynamic-power-coefficient = <100>; 107 l2_3: l2-cache { 108 compatible = "cache"; 109 cache-level = <2>; 110 cache-unified; 111 next-level-cache = <&l3_0>; 112 }; 113 }; 114 115 cpu4: cpu@10000 { 116 device_type = "cpu"; 117 compatible = "qcom,kryo"; 118 reg = <0x0 0x10000>; 119 enable-method = "psci"; 120 qcom,freq-domain = <&cpufreq_hw 1>; 121 next-level-cache = <&l2_4>; 122 capacity-dmips-mhz = <1024>; 123 dynamic-power-coefficient = <100>; 124 l2_4: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 cache-unified; 128 next-level-cache = <&l3_1>; 129 l3_1: l3-cache { 130 compatible = "cache"; 131 cache-level = <3>; 132 cache-unified; 133 }; 134 135 }; 136 }; 137 138 cpu5: cpu@10100 { 139 device_type = "cpu"; 140 compatible = "qcom,kryo"; 141 reg = <0x0 0x10100>; 142 enable-method = "psci"; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 next-level-cache = <&l2_5>; 145 capacity-dmips-mhz = <1024>; 146 dynamic-power-coefficient = <100>; 147 l2_5: l2-cache { 148 compatible = "cache"; 149 cache-level = <2>; 150 cache-unified; 151 next-level-cache = <&l3_1>; 152 }; 153 }; 154 155 cpu6: cpu@10200 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo"; 158 reg = <0x0 0x10200>; 159 enable-method = "psci"; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 next-level-cache = <&l2_6>; 162 capacity-dmips-mhz = <1024>; 163 dynamic-power-coefficient = <100>; 164 l2_6: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&l3_1>; 169 }; 170 }; 171 172 cpu7: cpu@10300 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo"; 175 reg = <0x0 0x10300>; 176 enable-method = "psci"; 177 qcom,freq-domain = <&cpufreq_hw 1>; 178 next-level-cache = <&l2_7>; 179 capacity-dmips-mhz = <1024>; 180 dynamic-power-coefficient = <100>; 181 l2_7: l2-cache { 182 compatible = "cache"; 183 cache-level = <2>; 184 cache-unified; 185 next-level-cache = <&l3_1>; 186 }; 187 }; 188 189 cpu-map { 190 cluster0 { 191 core0 { 192 cpu = <&cpu0>; 193 }; 194 195 core1 { 196 cpu = <&cpu1>; 197 }; 198 199 core2 { 200 cpu = <&cpu2>; 201 }; 202 203 core3 { 204 cpu = <&cpu3>; 205 }; 206 }; 207 208 cluster1 { 209 core0 { 210 cpu = <&cpu4>; 211 }; 212 213 core1 { 214 cpu = <&cpu5>; 215 }; 216 217 core2 { 218 cpu = <&cpu6>; 219 }; 220 221 core3 { 222 cpu = <&cpu7>; 223 }; 224 }; 225 }; 226 227 idle-states { 228 entry-method = "psci"; 229 230 gold_cpu_sleep_0: cpu-sleep-0 { 231 compatible = "arm,idle-state"; 232 idle-state-name = "gold-power-collapse"; 233 arm,psci-suspend-param = <0x40000003>; 234 entry-latency-us = <549>; 235 exit-latency-us = <901>; 236 min-residency-us = <1774>; 237 local-timer-stop; 238 }; 239 240 gold_rail_cpu_sleep_0: cpu-sleep-1 { 241 compatible = "arm,idle-state"; 242 idle-state-name = "gold-rail-power-collapse"; 243 arm,psci-suspend-param = <0x40000004>; 244 entry-latency-us = <702>; 245 exit-latency-us = <1061>; 246 min-residency-us = <4488>; 247 local-timer-stop; 248 }; 249 }; 250 251 domain-idle-states { 252 cluster_sleep_gold: cluster-sleep-0 { 253 compatible = "domain-idle-state"; 254 arm,psci-suspend-param = <0x41000044>; 255 entry-latency-us = <2752>; 256 exit-latency-us = <3048>; 257 min-residency-us = <6118>; 258 }; 259 260 cluster_sleep_apss_rsc_pc: cluster-sleep-1 { 261 compatible = "domain-idle-state"; 262 arm,psci-suspend-param = <0x42000144>; 263 entry-latency-us = <3263>; 264 exit-latency-us = <6562>; 265 min-residency-us = <9987>; 266 }; 267 }; 268 }; 269 270 dummy-sink { 271 compatible = "arm,coresight-dummy-sink"; 272 273 in-ports { 274 port { 275 eud_in: endpoint { 276 remote-endpoint = 277 <&swao_rep_out1>; 278 }; 279 }; 280 }; 281 }; 282 283 firmware { 284 scm { 285 compatible = "qcom,scm-sa8775p", "qcom,scm"; 286 qcom,dload-mode = <&tcsr 0x13000>; 287 memory-region = <&tz_ffi_mem>; 288 }; 289 }; 290 291 aggre1_noc: interconnect-aggre1-noc { 292 compatible = "qcom,sa8775p-aggre1-noc"; 293 #interconnect-cells = <2>; 294 qcom,bcm-voters = <&apps_bcm_voter>; 295 }; 296 297 aggre2_noc: interconnect-aggre2-noc { 298 compatible = "qcom,sa8775p-aggre2-noc"; 299 #interconnect-cells = <2>; 300 qcom,bcm-voters = <&apps_bcm_voter>; 301 }; 302 303 clk_virt: interconnect-clk-virt { 304 compatible = "qcom,sa8775p-clk-virt"; 305 #interconnect-cells = <2>; 306 qcom,bcm-voters = <&apps_bcm_voter>; 307 }; 308 309 config_noc: interconnect-config-noc { 310 compatible = "qcom,sa8775p-config-noc"; 311 #interconnect-cells = <2>; 312 qcom,bcm-voters = <&apps_bcm_voter>; 313 }; 314 315 dc_noc: interconnect-dc-noc { 316 compatible = "qcom,sa8775p-dc-noc"; 317 #interconnect-cells = <2>; 318 qcom,bcm-voters = <&apps_bcm_voter>; 319 }; 320 321 gem_noc: interconnect-gem-noc { 322 compatible = "qcom,sa8775p-gem-noc"; 323 #interconnect-cells = <2>; 324 qcom,bcm-voters = <&apps_bcm_voter>; 325 }; 326 327 gpdsp_anoc: interconnect-gpdsp-anoc { 328 compatible = "qcom,sa8775p-gpdsp-anoc"; 329 #interconnect-cells = <2>; 330 qcom,bcm-voters = <&apps_bcm_voter>; 331 }; 332 333 lpass_ag_noc: interconnect-lpass-ag-noc { 334 compatible = "qcom,sa8775p-lpass-ag-noc"; 335 #interconnect-cells = <2>; 336 qcom,bcm-voters = <&apps_bcm_voter>; 337 }; 338 339 mc_virt: interconnect-mc-virt { 340 compatible = "qcom,sa8775p-mc-virt"; 341 #interconnect-cells = <2>; 342 qcom,bcm-voters = <&apps_bcm_voter>; 343 }; 344 345 mmss_noc: interconnect-mmss-noc { 346 compatible = "qcom,sa8775p-mmss-noc"; 347 #interconnect-cells = <2>; 348 qcom,bcm-voters = <&apps_bcm_voter>; 349 }; 350 351 nspa_noc: interconnect-nspa-noc { 352 compatible = "qcom,sa8775p-nspa-noc"; 353 #interconnect-cells = <2>; 354 qcom,bcm-voters = <&apps_bcm_voter>; 355 }; 356 357 nspb_noc: interconnect-nspb-noc { 358 compatible = "qcom,sa8775p-nspb-noc"; 359 #interconnect-cells = <2>; 360 qcom,bcm-voters = <&apps_bcm_voter>; 361 }; 362 363 pcie_anoc: interconnect-pcie-anoc { 364 compatible = "qcom,sa8775p-pcie-anoc"; 365 #interconnect-cells = <2>; 366 qcom,bcm-voters = <&apps_bcm_voter>; 367 }; 368 369 system_noc: interconnect-system-noc { 370 compatible = "qcom,sa8775p-system-noc"; 371 #interconnect-cells = <2>; 372 qcom,bcm-voters = <&apps_bcm_voter>; 373 }; 374 375 /* Will be updated by the bootloader. */ 376 memory@80000000 { 377 device_type = "memory"; 378 reg = <0x0 0x80000000 0x0 0x0>; 379 }; 380 381 qup_opp_table_100mhz: opp-table-qup100mhz { 382 compatible = "operating-points-v2"; 383 384 opp-100000000 { 385 opp-hz = /bits/ 64 <100000000>; 386 required-opps = <&rpmhpd_opp_svs_l1>; 387 }; 388 }; 389 390 pmu { 391 compatible = "arm,armv8-pmuv3"; 392 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 393 }; 394 395 psci { 396 compatible = "arm,psci-1.0"; 397 method = "smc"; 398 399 cpu_pd0: power-domain-cpu0 { 400 #power-domain-cells = <0>; 401 power-domains = <&cluster_0_pd>; 402 domain-idle-states = <&gold_cpu_sleep_0>, 403 <&gold_rail_cpu_sleep_0>; 404 }; 405 406 cpu_pd1: power-domain-cpu1 { 407 #power-domain-cells = <0>; 408 power-domains = <&cluster_0_pd>; 409 domain-idle-states = <&gold_cpu_sleep_0>, 410 <&gold_rail_cpu_sleep_0>; 411 }; 412 413 cpu_pd2: power-domain-cpu2 { 414 #power-domain-cells = <0>; 415 power-domains = <&cluster_0_pd>; 416 domain-idle-states = <&gold_cpu_sleep_0>, 417 <&gold_rail_cpu_sleep_0>; 418 }; 419 420 cpu_pd3: power-domain-cpu3 { 421 #power-domain-cells = <0>; 422 power-domains = <&cluster_0_pd>; 423 domain-idle-states = <&gold_cpu_sleep_0>, 424 <&gold_rail_cpu_sleep_0>; 425 }; 426 427 cpu_pd4: power-domain-cpu4 { 428 #power-domain-cells = <0>; 429 power-domains = <&cluster_1_pd>; 430 domain-idle-states = <&gold_cpu_sleep_0>, 431 <&gold_rail_cpu_sleep_0>; 432 }; 433 434 cpu_pd5: power-domain-cpu5 { 435 #power-domain-cells = <0>; 436 power-domains = <&cluster_1_pd>; 437 domain-idle-states = <&gold_cpu_sleep_0>, 438 <&gold_rail_cpu_sleep_0>; 439 }; 440 441 cpu_pd6: power-domain-cpu6 { 442 #power-domain-cells = <0>; 443 power-domains = <&cluster_1_pd>; 444 domain-idle-states = <&gold_cpu_sleep_0>, 445 <&gold_rail_cpu_sleep_0>; 446 }; 447 448 cpu_pd7: power-domain-cpu7 { 449 #power-domain-cells = <0>; 450 power-domains = <&cluster_1_pd>; 451 domain-idle-states = <&gold_cpu_sleep_0>, 452 <&gold_rail_cpu_sleep_0>; 453 }; 454 455 cluster_0_pd: power-domain-cluster0 { 456 #power-domain-cells = <0>; 457 power-domains = <&cluster_2_pd>; 458 domain-idle-states = <&cluster_sleep_gold>; 459 }; 460 461 cluster_1_pd: power-domain-cluster1 { 462 #power-domain-cells = <0>; 463 power-domains = <&cluster_2_pd>; 464 domain-idle-states = <&cluster_sleep_gold>; 465 }; 466 467 cluster_2_pd: power-domain-cluster2 { 468 #power-domain-cells = <0>; 469 domain-idle-states = <&cluster_sleep_apss_rsc_pc>; 470 }; 471 }; 472 473 reserved-memory { 474 #address-cells = <2>; 475 #size-cells = <2>; 476 ranges; 477 478 sail_ss_mem: sail-ss@80000000 { 479 reg = <0x0 0x80000000 0x0 0x10000000>; 480 no-map; 481 }; 482 483 hyp_mem: hyp@90000000 { 484 reg = <0x0 0x90000000 0x0 0x600000>; 485 no-map; 486 }; 487 488 xbl_boot_mem: xbl-boot@90600000 { 489 reg = <0x0 0x90600000 0x0 0x200000>; 490 no-map; 491 }; 492 493 aop_image_mem: aop-image@90800000 { 494 reg = <0x0 0x90800000 0x0 0x60000>; 495 no-map; 496 }; 497 498 aop_cmd_db_mem: aop-cmd-db@90860000 { 499 compatible = "qcom,cmd-db"; 500 reg = <0x0 0x90860000 0x0 0x20000>; 501 no-map; 502 }; 503 504 uefi_log: uefi-log@908b0000 { 505 reg = <0x0 0x908b0000 0x0 0x10000>; 506 no-map; 507 }; 508 509 ddr_training_checksum: ddr-training-checksum@908c0000 { 510 reg = <0x0 0x908c0000 0x0 0x1000>; 511 no-map; 512 }; 513 514 reserved_mem: reserved@908f0000 { 515 reg = <0x0 0x908f0000 0x0 0xe000>; 516 no-map; 517 }; 518 519 secdata_apss_mem: secdata-apss@908fe000 { 520 reg = <0x0 0x908fe000 0x0 0x2000>; 521 no-map; 522 }; 523 524 smem_mem: smem@90900000 { 525 compatible = "qcom,smem"; 526 reg = <0x0 0x90900000 0x0 0x200000>; 527 no-map; 528 hwlocks = <&tcsr_mutex 3>; 529 }; 530 531 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { 532 reg = <0x0 0x90c00000 0x0 0x100000>; 533 no-map; 534 }; 535 536 sail_mailbox_mem: sail-ss@90d00000 { 537 reg = <0x0 0x90d00000 0x0 0x100000>; 538 no-map; 539 }; 540 541 sail_ota_mem: sail-ss@90e00000 { 542 reg = <0x0 0x90e00000 0x0 0x300000>; 543 no-map; 544 }; 545 546 aoss_backup_mem: aoss-backup@91b00000 { 547 reg = <0x0 0x91b00000 0x0 0x40000>; 548 no-map; 549 }; 550 551 cpucp_backup_mem: cpucp-backup@91b40000 { 552 reg = <0x0 0x91b40000 0x0 0x40000>; 553 no-map; 554 }; 555 556 tz_config_backup_mem: tz-config-backup@91b80000 { 557 reg = <0x0 0x91b80000 0x0 0x10000>; 558 no-map; 559 }; 560 561 ddr_training_data_mem: ddr-training-data@91b90000 { 562 reg = <0x0 0x91b90000 0x0 0x10000>; 563 no-map; 564 }; 565 566 cdt_data_backup_mem: cdt-data-backup@91ba0000 { 567 reg = <0x0 0x91ba0000 0x0 0x1000>; 568 no-map; 569 }; 570 571 tz_ffi_mem: tz-ffi@91c00000 { 572 compatible = "shared-dma-pool"; 573 reg = <0x0 0x91c00000 0x0 0x1400000>; 574 no-map; 575 }; 576 577 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 578 reg = <0x0 0x93b00000 0x0 0xf00000>; 579 no-map; 580 }; 581 582 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 583 reg = <0x0 0x94a00000 0x0 0x800000>; 584 no-map; 585 }; 586 587 pil_camera_mem: pil-camera@95200000 { 588 reg = <0x0 0x95200000 0x0 0x500000>; 589 no-map; 590 }; 591 592 pil_adsp_mem: pil-adsp@95c00000 { 593 reg = <0x0 0x95c00000 0x0 0x1e00000>; 594 no-map; 595 }; 596 597 pil_gdsp0_mem: pil-gdsp0@97b00000 { 598 reg = <0x0 0x97b00000 0x0 0x1e00000>; 599 no-map; 600 }; 601 602 pil_gdsp1_mem: pil-gdsp1@99900000 { 603 reg = <0x0 0x99900000 0x0 0x1e00000>; 604 no-map; 605 }; 606 607 pil_cdsp0_mem: pil-cdsp0@9b800000 { 608 reg = <0x0 0x9b800000 0x0 0x1e00000>; 609 no-map; 610 }; 611 612 pil_gpu_mem: pil-gpu@9d600000 { 613 reg = <0x0 0x9d600000 0x0 0x2000>; 614 no-map; 615 }; 616 617 pil_cdsp1_mem: pil-cdsp1@9d700000 { 618 reg = <0x0 0x9d700000 0x0 0x1e00000>; 619 no-map; 620 }; 621 622 pil_cvp_mem: pil-cvp@9f500000 { 623 reg = <0x0 0x9f500000 0x0 0x700000>; 624 no-map; 625 }; 626 627 pil_video_mem: pil-video@9fc00000 { 628 reg = <0x0 0x9fc00000 0x0 0x700000>; 629 no-map; 630 }; 631 632 audio_mdf_mem: audio-mdf-region@ae000000 { 633 reg = <0x0 0xae000000 0x0 0x1000000>; 634 no-map; 635 }; 636 637 firmware_mem: firmware-region@b0000000 { 638 reg = <0x0 0xb0000000 0x0 0x800000>; 639 no-map; 640 }; 641 642 hyptz_reserved_mem: hyptz-reserved@beb00000 { 643 reg = <0x0 0xbeb00000 0x0 0x11500000>; 644 no-map; 645 }; 646 647 scmi_mem: scmi-region@d0000000 { 648 reg = <0x0 0xd0000000 0x0 0x40000>; 649 no-map; 650 }; 651 652 firmware_logs_mem: firmware-logs@d0040000 { 653 reg = <0x0 0xd0040000 0x0 0x10000>; 654 no-map; 655 }; 656 657 firmware_audio_mem: firmware-audio@d0050000 { 658 reg = <0x0 0xd0050000 0x0 0x4000>; 659 no-map; 660 }; 661 662 firmware_reserved_mem: firmware-reserved@d0054000 { 663 reg = <0x0 0xd0054000 0x0 0x9c000>; 664 no-map; 665 }; 666 667 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { 668 reg = <0x0 0xd00f0000 0x0 0x10000>; 669 no-map; 670 }; 671 672 tags_mem: tags@d0100000 { 673 reg = <0x0 0xd0100000 0x0 0x1200000>; 674 no-map; 675 }; 676 677 qtee_mem: qtee@d1300000 { 678 reg = <0x0 0xd1300000 0x0 0x500000>; 679 no-map; 680 }; 681 682 deepsleep_backup_mem: deepsleep-backup@d1800000 { 683 reg = <0x0 0xd1800000 0x0 0x100000>; 684 no-map; 685 }; 686 687 trusted_apps_mem: trusted-apps@d1900000 { 688 reg = <0x0 0xd1900000 0x0 0x3800000>; 689 no-map; 690 }; 691 692 tz_stat_mem: tz-stat@db100000 { 693 reg = <0x0 0xdb100000 0x0 0x100000>; 694 no-map; 695 }; 696 697 cpucp_fw_mem: cpucp-fw@db200000 { 698 reg = <0x0 0xdb200000 0x0 0x100000>; 699 no-map; 700 }; 701 }; 702 703 smp2p-adsp { 704 compatible = "qcom,smp2p"; 705 qcom,smem = <443>, <429>; 706 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 707 IPCC_MPROC_SIGNAL_SMP2P 708 IRQ_TYPE_EDGE_RISING>; 709 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 710 711 qcom,local-pid = <0>; 712 qcom,remote-pid = <2>; 713 714 smp2p_adsp_out: master-kernel { 715 qcom,entry-name = "master-kernel"; 716 #qcom,smem-state-cells = <1>; 717 }; 718 719 smp2p_adsp_in: slave-kernel { 720 qcom,entry-name = "slave-kernel"; 721 interrupt-controller; 722 #interrupt-cells = <2>; 723 }; 724 }; 725 726 smp2p-cdsp0 { 727 compatible = "qcom,smp2p"; 728 qcom,smem = <94>, <432>; 729 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 730 IPCC_MPROC_SIGNAL_SMP2P 731 IRQ_TYPE_EDGE_RISING>; 732 mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 733 734 qcom,local-pid = <0>; 735 qcom,remote-pid = <5>; 736 737 smp2p_cdsp0_out: master-kernel { 738 qcom,entry-name = "master-kernel"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 smp2p_cdsp0_in: slave-kernel { 743 qcom,entry-name = "slave-kernel"; 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 }; 748 749 smp2p-cdsp1 { 750 compatible = "qcom,smp2p"; 751 qcom,smem = <617>, <616>; 752 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 753 IPCC_MPROC_SIGNAL_SMP2P 754 IRQ_TYPE_EDGE_RISING>; 755 mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; 756 757 qcom,local-pid = <0>; 758 qcom,remote-pid = <12>; 759 760 smp2p_cdsp1_out: master-kernel { 761 qcom,entry-name = "master-kernel"; 762 #qcom,smem-state-cells = <1>; 763 }; 764 765 smp2p_cdsp1_in: slave-kernel { 766 qcom,entry-name = "slave-kernel"; 767 interrupt-controller; 768 #interrupt-cells = <2>; 769 }; 770 }; 771 772 smp2p-gpdsp0 { 773 compatible = "qcom,smp2p"; 774 qcom,smem = <617>, <616>; 775 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 776 IPCC_MPROC_SIGNAL_SMP2P 777 IRQ_TYPE_EDGE_RISING>; 778 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; 779 780 qcom,local-pid = <0>; 781 qcom,remote-pid = <17>; 782 783 smp2p_gpdsp0_out: master-kernel { 784 qcom,entry-name = "master-kernel"; 785 #qcom,smem-state-cells = <1>; 786 }; 787 788 smp2p_gpdsp0_in: slave-kernel { 789 qcom,entry-name = "slave-kernel"; 790 interrupt-controller; 791 #interrupt-cells = <2>; 792 }; 793 }; 794 795 smp2p-gpdsp1 { 796 compatible = "qcom,smp2p"; 797 qcom,smem = <617>, <616>; 798 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 799 IPCC_MPROC_SIGNAL_SMP2P 800 IRQ_TYPE_EDGE_RISING>; 801 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>; 802 803 qcom,local-pid = <0>; 804 qcom,remote-pid = <18>; 805 806 smp2p_gpdsp1_out: master-kernel { 807 qcom,entry-name = "master-kernel"; 808 #qcom,smem-state-cells = <1>; 809 }; 810 811 smp2p_gpdsp1_in: slave-kernel { 812 qcom,entry-name = "slave-kernel"; 813 interrupt-controller; 814 #interrupt-cells = <2>; 815 }; 816 }; 817 818 soc: soc@0 { 819 compatible = "simple-bus"; 820 #address-cells = <2>; 821 #size-cells = <2>; 822 ranges = <0 0 0 0 0x10 0>; 823 824 gcc: clock-controller@100000 { 825 compatible = "qcom,sa8775p-gcc"; 826 reg = <0x0 0x00100000 0x0 0xc7018>; 827 #clock-cells = <1>; 828 #reset-cells = <1>; 829 #power-domain-cells = <1>; 830 clocks = <&rpmhcc RPMH_CXO_CLK>, 831 <&sleep_clk>, 832 <0>, 833 <0>, 834 <0>, 835 <&usb_0_qmpphy>, 836 <&usb_1_qmpphy>, 837 <0>, 838 <0>, 839 <0>, 840 <&pcie0_phy>, 841 <&pcie1_phy>, 842 <0>, 843 <0>, 844 <0>; 845 power-domains = <&rpmhpd SA8775P_CX>; 846 }; 847 848 ipcc: mailbox@408000 { 849 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 850 reg = <0x0 0x00408000 0x0 0x1000>; 851 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 852 interrupt-controller; 853 #interrupt-cells = <3>; 854 #mbox-cells = <2>; 855 }; 856 857 gpi_dma2: qcom,gpi-dma@800000 { 858 compatible = "qcom,sm6350-gpi-dma"; 859 reg = <0x0 0x00800000 0x0 0x60000>; 860 #dma-cells = <3>; 861 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 873 dma-channels = <12>; 874 dma-channel-mask = <0xfff>; 875 iommus = <&apps_smmu 0x5b6 0x0>; 876 status = "disabled"; 877 }; 878 879 qupv3_id_2: geniqup@8c0000 { 880 compatible = "qcom,geni-se-qup"; 881 reg = <0x0 0x008c0000 0x0 0x6000>; 882 ranges; 883 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 884 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 885 clock-names = "m-ahb", "s-ahb"; 886 iommus = <&apps_smmu 0x5a3 0x0>; 887 #address-cells = <2>; 888 #size-cells = <2>; 889 status = "disabled"; 890 891 i2c14: i2c@880000 { 892 compatible = "qcom,geni-i2c"; 893 reg = <0x0 0x880000 0x0 0x4000>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 898 clock-names = "se"; 899 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 900 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 901 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 902 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 903 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 904 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 905 interconnect-names = "qup-core", 906 "qup-config", 907 "qup-memory"; 908 power-domains = <&rpmhpd SA8775P_CX>; 909 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 910 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 911 dma-names = "tx", 912 "rx"; 913 status = "disabled"; 914 }; 915 916 spi14: spi@880000 { 917 compatible = "qcom,geni-spi"; 918 reg = <0x0 0x880000 0x0 0x4000>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 923 clock-names = "se"; 924 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 925 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 926 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 927 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 928 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 929 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 930 interconnect-names = "qup-core", 931 "qup-config", 932 "qup-memory"; 933 power-domains = <&rpmhpd SA8775P_CX>; 934 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 935 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 936 dma-names = "tx", 937 "rx"; 938 status = "disabled"; 939 }; 940 941 uart14: serial@880000 { 942 compatible = "qcom,geni-uart"; 943 reg = <0x0 0x00880000 0x0 0x4000>; 944 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 946 clock-names = "se"; 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 948 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 949 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 950 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 951 interconnect-names = "qup-core", "qup-config"; 952 power-domains = <&rpmhpd SA8775P_CX>; 953 status = "disabled"; 954 }; 955 956 i2c15: i2c@884000 { 957 compatible = "qcom,geni-i2c"; 958 reg = <0x0 0x884000 0x0 0x4000>; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 963 clock-names = "se"; 964 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 965 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 966 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 967 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 968 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 969 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 970 interconnect-names = "qup-core", 971 "qup-config", 972 "qup-memory"; 973 power-domains = <&rpmhpd SA8775P_CX>; 974 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 975 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 976 dma-names = "tx", 977 "rx"; 978 status = "disabled"; 979 }; 980 981 spi15: spi@884000 { 982 compatible = "qcom,geni-spi"; 983 reg = <0x0 0x884000 0x0 0x4000>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 988 clock-names = "se"; 989 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 990 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 992 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 993 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 995 interconnect-names = "qup-core", 996 "qup-config", 997 "qup-memory"; 998 power-domains = <&rpmhpd SA8775P_CX>; 999 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1000 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1001 dma-names = "tx", 1002 "rx"; 1003 status = "disabled"; 1004 }; 1005 1006 uart15: serial@884000 { 1007 compatible = "qcom,geni-uart"; 1008 reg = <0x0 0x00884000 0x0 0x4000>; 1009 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1011 clock-names = "se"; 1012 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1013 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1014 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1015 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1016 interconnect-names = "qup-core", "qup-config"; 1017 power-domains = <&rpmhpd SA8775P_CX>; 1018 status = "disabled"; 1019 }; 1020 1021 i2c16: i2c@888000 { 1022 compatible = "qcom,geni-i2c"; 1023 reg = <0x0 0x888000 0x0 0x4000>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1028 clock-names = "se"; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1030 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1031 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1032 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1033 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1034 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1035 interconnect-names = "qup-core", 1036 "qup-config", 1037 "qup-memory"; 1038 power-domains = <&rpmhpd SA8775P_CX>; 1039 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1040 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1041 dma-names = "tx", 1042 "rx"; 1043 status = "disabled"; 1044 }; 1045 1046 spi16: spi@888000 { 1047 compatible = "qcom,geni-spi"; 1048 reg = <0x0 0x00888000 0x0 0x4000>; 1049 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1051 clock-names = "se"; 1052 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1053 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1054 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1055 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1056 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1057 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1058 interconnect-names = "qup-core", 1059 "qup-config", 1060 "qup-memory"; 1061 power-domains = <&rpmhpd SA8775P_CX>; 1062 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1063 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1064 dma-names = "tx", 1065 "rx"; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 status = "disabled"; 1069 }; 1070 1071 uart16: serial@888000 { 1072 compatible = "qcom,geni-uart"; 1073 reg = <0x0 0x00888000 0x0 0x4000>; 1074 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1076 clock-names = "se"; 1077 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1078 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1079 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1080 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1081 interconnect-names = "qup-core", "qup-config"; 1082 power-domains = <&rpmhpd SA8775P_CX>; 1083 status = "disabled"; 1084 }; 1085 1086 i2c17: i2c@88c000 { 1087 compatible = "qcom,geni-i2c"; 1088 reg = <0x0 0x88c000 0x0 0x4000>; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1093 clock-names = "se"; 1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1095 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1096 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1097 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1098 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1099 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1100 interconnect-names = "qup-core", 1101 "qup-config", 1102 "qup-memory"; 1103 power-domains = <&rpmhpd SA8775P_CX>; 1104 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1105 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1106 dma-names = "tx", 1107 "rx"; 1108 status = "disabled"; 1109 }; 1110 1111 spi17: spi@88c000 { 1112 compatible = "qcom,geni-spi"; 1113 reg = <0x0 0x88c000 0x0 0x4000>; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1118 clock-names = "se"; 1119 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1120 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1121 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1122 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1123 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1124 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1125 interconnect-names = "qup-core", 1126 "qup-config", 1127 "qup-memory"; 1128 power-domains = <&rpmhpd SA8775P_CX>; 1129 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1130 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1131 dma-names = "tx", 1132 "rx"; 1133 status = "disabled"; 1134 }; 1135 1136 uart17: serial@88c000 { 1137 compatible = "qcom,geni-uart"; 1138 reg = <0x0 0x0088c000 0x0 0x4000>; 1139 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1141 clock-names = "se"; 1142 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1143 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1144 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1145 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1146 interconnect-names = "qup-core", "qup-config"; 1147 power-domains = <&rpmhpd SA8775P_CX>; 1148 status = "disabled"; 1149 }; 1150 1151 i2c18: i2c@890000 { 1152 compatible = "qcom,geni-i2c"; 1153 reg = <0x0 0x00890000 0x0 0x4000>; 1154 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1156 clock-names = "se"; 1157 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1158 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1159 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1160 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1161 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1162 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1163 interconnect-names = "qup-core", 1164 "qup-config", 1165 "qup-memory"; 1166 power-domains = <&rpmhpd SA8775P_CX>; 1167 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1168 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1169 dma-names = "tx", 1170 "rx"; 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 status = "disabled"; 1174 }; 1175 1176 spi18: spi@890000 { 1177 compatible = "qcom,geni-spi"; 1178 reg = <0x0 0x890000 0x0 0x4000>; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1183 clock-names = "se"; 1184 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1185 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1186 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1187 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1188 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1189 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1190 interconnect-names = "qup-core", 1191 "qup-config", 1192 "qup-memory"; 1193 power-domains = <&rpmhpd SA8775P_CX>; 1194 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1195 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1196 dma-names = "tx", 1197 "rx"; 1198 status = "disabled"; 1199 }; 1200 1201 uart18: serial@890000 { 1202 compatible = "qcom,geni-uart"; 1203 reg = <0x0 0x00890000 0x0 0x4000>; 1204 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1205 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1206 clock-names = "se"; 1207 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1208 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1209 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1210 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1211 interconnect-names = "qup-core", "qup-config"; 1212 power-domains = <&rpmhpd SA8775P_CX>; 1213 status = "disabled"; 1214 }; 1215 1216 i2c19: i2c@894000 { 1217 compatible = "qcom,geni-i2c"; 1218 reg = <0x0 0x894000 0x0 0x4000>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1223 clock-names = "se"; 1224 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1225 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1226 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1227 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1228 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1229 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1230 interconnect-names = "qup-core", 1231 "qup-config", 1232 "qup-memory"; 1233 power-domains = <&rpmhpd SA8775P_CX>; 1234 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1235 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1236 dma-names = "tx", 1237 "rx"; 1238 status = "disabled"; 1239 }; 1240 1241 spi19: spi@894000 { 1242 compatible = "qcom,geni-spi"; 1243 reg = <0x0 0x894000 0x0 0x4000>; 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1248 clock-names = "se"; 1249 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1250 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1251 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1252 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1253 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1254 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1255 interconnect-names = "qup-core", 1256 "qup-config", 1257 "qup-memory"; 1258 power-domains = <&rpmhpd SA8775P_CX>; 1259 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1260 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1261 dma-names = "tx", 1262 "rx"; 1263 status = "disabled"; 1264 }; 1265 1266 uart19: serial@894000 { 1267 compatible = "qcom,geni-uart"; 1268 reg = <0x0 0x00894000 0x0 0x4000>; 1269 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1270 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1271 clock-names = "se"; 1272 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1273 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1274 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1275 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1276 interconnect-names = "qup-core", "qup-config"; 1277 power-domains = <&rpmhpd SA8775P_CX>; 1278 status = "disabled"; 1279 }; 1280 1281 i2c20: i2c@898000 { 1282 compatible = "qcom,geni-i2c"; 1283 reg = <0x0 0x898000 0x0 0x4000>; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1288 clock-names = "se"; 1289 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1290 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1291 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1292 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1293 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1294 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1295 interconnect-names = "qup-core", 1296 "qup-config", 1297 "qup-memory"; 1298 power-domains = <&rpmhpd SA8775P_CX>; 1299 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1300 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1301 dma-names = "tx", 1302 "rx"; 1303 status = "disabled"; 1304 }; 1305 1306 spi20: spi@898000 { 1307 compatible = "qcom,geni-spi"; 1308 reg = <0x0 0x898000 0x0 0x4000>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1312 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1313 clock-names = "se"; 1314 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1315 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1316 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1317 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1318 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1319 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1320 interconnect-names = "qup-core", 1321 "qup-config", 1322 "qup-memory"; 1323 power-domains = <&rpmhpd SA8775P_CX>; 1324 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1325 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1326 dma-names = "tx", 1327 "rx"; 1328 status = "disabled"; 1329 }; 1330 1331 uart20: serial@898000 { 1332 compatible = "qcom,geni-uart"; 1333 reg = <0x0 0x00898000 0x0 0x4000>; 1334 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1335 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1336 clock-names = "se"; 1337 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1338 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1339 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1340 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1341 interconnect-names = "qup-core", "qup-config"; 1342 power-domains = <&rpmhpd SA8775P_CX>; 1343 status = "disabled"; 1344 }; 1345 1346 }; 1347 1348 gpi_dma0: qcom,gpi-dma@900000 { 1349 compatible = "qcom,sm6350-gpi-dma"; 1350 reg = <0x0 0x00900000 0x0 0x60000>; 1351 #dma-cells = <3>; 1352 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1364 dma-channels = <12>; 1365 dma-channel-mask = <0xfff>; 1366 iommus = <&apps_smmu 0x416 0x0>; 1367 status = "disabled"; 1368 }; 1369 1370 qupv3_id_0: geniqup@9c0000 { 1371 compatible = "qcom,geni-se-qup"; 1372 reg = <0x0 0x9c0000 0x0 0x6000>; 1373 #address-cells = <2>; 1374 #size-cells = <2>; 1375 ranges; 1376 clock-names = "m-ahb", "s-ahb"; 1377 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1378 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1379 iommus = <&apps_smmu 0x403 0x0>; 1380 status = "disabled"; 1381 1382 i2c0: i2c@980000 { 1383 compatible = "qcom,geni-i2c"; 1384 reg = <0x0 0x980000 0x0 0x4000>; 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1388 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1389 clock-names = "se"; 1390 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1391 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1392 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1393 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1394 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1395 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1396 interconnect-names = "qup-core", 1397 "qup-config", 1398 "qup-memory"; 1399 power-domains = <&rpmhpd SA8775P_CX>; 1400 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1401 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1402 dma-names = "tx", 1403 "rx"; 1404 status = "disabled"; 1405 }; 1406 1407 spi0: spi@980000 { 1408 compatible = "qcom,geni-spi"; 1409 reg = <0x0 0x980000 0x0 0x4000>; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1413 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1414 clock-names = "se"; 1415 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1416 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1417 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1418 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1419 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1420 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1421 interconnect-names = "qup-core", 1422 "qup-config", 1423 "qup-memory"; 1424 power-domains = <&rpmhpd SA8775P_CX>; 1425 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1426 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1427 dma-names = "tx", 1428 "rx"; 1429 status = "disabled"; 1430 }; 1431 1432 uart0: serial@980000 { 1433 compatible = "qcom,geni-uart"; 1434 reg = <0x0 0x980000 0x0 0x4000>; 1435 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1436 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1437 clock-names = "se"; 1438 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1439 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1440 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1441 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1442 interconnect-names = "qup-core", "qup-config"; 1443 power-domains = <&rpmhpd SA8775P_CX>; 1444 status = "disabled"; 1445 }; 1446 1447 i2c1: i2c@984000 { 1448 compatible = "qcom,geni-i2c"; 1449 reg = <0x0 0x984000 0x0 0x4000>; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1453 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1454 clock-names = "se"; 1455 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1456 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1457 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1458 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1459 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1460 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1461 interconnect-names = "qup-core", 1462 "qup-config", 1463 "qup-memory"; 1464 power-domains = <&rpmhpd SA8775P_CX>; 1465 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1466 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1467 dma-names = "tx", 1468 "rx"; 1469 status = "disabled"; 1470 }; 1471 1472 spi1: spi@984000 { 1473 compatible = "qcom,geni-spi"; 1474 reg = <0x0 0x984000 0x0 0x4000>; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1478 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1479 clock-names = "se"; 1480 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1481 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1482 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1483 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1484 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1485 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1486 interconnect-names = "qup-core", 1487 "qup-config", 1488 "qup-memory"; 1489 power-domains = <&rpmhpd SA8775P_CX>; 1490 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1491 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1492 dma-names = "tx", 1493 "rx"; 1494 status = "disabled"; 1495 }; 1496 1497 uart1: serial@984000 { 1498 compatible = "qcom,geni-uart"; 1499 reg = <0x0 0x984000 0x0 0x4000>; 1500 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1501 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1502 clock-names = "se"; 1503 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1504 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1505 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1506 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1507 interconnect-names = "qup-core", "qup-config"; 1508 power-domains = <&rpmhpd SA8775P_CX>; 1509 status = "disabled"; 1510 }; 1511 1512 i2c2: i2c@988000 { 1513 compatible = "qcom,geni-i2c"; 1514 reg = <0x0 0x988000 0x0 0x4000>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1518 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1519 clock-names = "se"; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1521 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1522 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1523 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1524 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1525 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1526 interconnect-names = "qup-core", 1527 "qup-config", 1528 "qup-memory"; 1529 power-domains = <&rpmhpd SA8775P_CX>; 1530 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1531 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1532 dma-names = "tx", 1533 "rx"; 1534 status = "disabled"; 1535 }; 1536 1537 spi2: spi@988000 { 1538 compatible = "qcom,geni-spi"; 1539 reg = <0x0 0x988000 0x0 0x4000>; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1543 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1544 clock-names = "se"; 1545 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1546 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1547 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1548 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1549 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1550 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1551 interconnect-names = "qup-core", 1552 "qup-config", 1553 "qup-memory"; 1554 power-domains = <&rpmhpd SA8775P_CX>; 1555 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1556 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1557 dma-names = "tx", 1558 "rx"; 1559 status = "disabled"; 1560 }; 1561 1562 uart2: serial@988000 { 1563 compatible = "qcom,geni-uart"; 1564 reg = <0x0 0x988000 0x0 0x4000>; 1565 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1566 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1567 clock-names = "se"; 1568 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1569 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1570 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1571 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1572 interconnect-names = "qup-core", "qup-config"; 1573 power-domains = <&rpmhpd SA8775P_CX>; 1574 status = "disabled"; 1575 }; 1576 1577 i2c3: i2c@98c000 { 1578 compatible = "qcom,geni-i2c"; 1579 reg = <0x0 0x98c000 0x0 0x4000>; 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1583 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1584 clock-names = "se"; 1585 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1586 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1587 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1588 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1589 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1590 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1591 interconnect-names = "qup-core", 1592 "qup-config", 1593 "qup-memory"; 1594 power-domains = <&rpmhpd SA8775P_CX>; 1595 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1596 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1597 dma-names = "tx", 1598 "rx"; 1599 status = "disabled"; 1600 }; 1601 1602 spi3: spi@98c000 { 1603 compatible = "qcom,geni-spi"; 1604 reg = <0x0 0x98c000 0x0 0x4000>; 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1608 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1609 clock-names = "se"; 1610 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1611 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1612 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1613 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1614 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1615 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1616 interconnect-names = "qup-core", 1617 "qup-config", 1618 "qup-memory"; 1619 power-domains = <&rpmhpd SA8775P_CX>; 1620 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1621 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1622 dma-names = "tx", 1623 "rx"; 1624 status = "disabled"; 1625 }; 1626 1627 uart3: serial@98c000 { 1628 compatible = "qcom,geni-uart"; 1629 reg = <0x0 0x98c000 0x0 0x4000>; 1630 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1631 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1632 clock-names = "se"; 1633 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1634 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1635 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1636 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1637 interconnect-names = "qup-core", "qup-config"; 1638 power-domains = <&rpmhpd SA8775P_CX>; 1639 status = "disabled"; 1640 }; 1641 1642 i2c4: i2c@990000 { 1643 compatible = "qcom,geni-i2c"; 1644 reg = <0x0 0x990000 0x0 0x4000>; 1645 #address-cells = <1>; 1646 #size-cells = <0>; 1647 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1648 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1649 clock-names = "se"; 1650 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1651 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1652 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1653 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1654 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1655 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1656 interconnect-names = "qup-core", 1657 "qup-config", 1658 "qup-memory"; 1659 power-domains = <&rpmhpd SA8775P_CX>; 1660 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1661 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1662 dma-names = "tx", 1663 "rx"; 1664 status = "disabled"; 1665 }; 1666 1667 spi4: spi@990000 { 1668 compatible = "qcom,geni-spi"; 1669 reg = <0x0 0x990000 0x0 0x4000>; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1673 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1674 clock-names = "se"; 1675 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1676 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1677 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1678 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1679 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1680 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1681 interconnect-names = "qup-core", 1682 "qup-config", 1683 "qup-memory"; 1684 power-domains = <&rpmhpd SA8775P_CX>; 1685 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1686 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1687 dma-names = "tx", 1688 "rx"; 1689 status = "disabled"; 1690 }; 1691 1692 uart4: serial@990000 { 1693 compatible = "qcom,geni-uart"; 1694 reg = <0x0 0x990000 0x0 0x4000>; 1695 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1696 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1697 clock-names = "se"; 1698 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1699 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1700 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1701 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1702 interconnect-names = "qup-core", "qup-config"; 1703 power-domains = <&rpmhpd SA8775P_CX>; 1704 status = "disabled"; 1705 }; 1706 1707 i2c5: i2c@994000 { 1708 compatible = "qcom,geni-i2c"; 1709 reg = <0x0 0x994000 0x0 0x4000>; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1713 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1714 clock-names = "se"; 1715 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1716 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1717 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1718 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1719 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1720 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1721 interconnect-names = "qup-core", 1722 "qup-config", 1723 "qup-memory"; 1724 power-domains = <&rpmhpd SA8775P_CX>; 1725 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1726 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1727 dma-names = "tx", 1728 "rx"; 1729 status = "disabled"; 1730 }; 1731 1732 spi5: spi@994000 { 1733 compatible = "qcom,geni-spi"; 1734 reg = <0x0 0x994000 0x0 0x4000>; 1735 #address-cells = <1>; 1736 #size-cells = <0>; 1737 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1738 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1739 clock-names = "se"; 1740 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1741 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1742 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1743 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1744 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1745 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1746 interconnect-names = "qup-core", 1747 "qup-config", 1748 "qup-memory"; 1749 power-domains = <&rpmhpd SA8775P_CX>; 1750 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1751 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1752 dma-names = "tx", 1753 "rx"; 1754 status = "disabled"; 1755 }; 1756 1757 uart5: serial@994000 { 1758 compatible = "qcom,geni-uart"; 1759 reg = <0x0 0x994000 0x0 0x4000>; 1760 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1761 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1762 clock-names = "se"; 1763 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1764 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1765 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1766 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1767 interconnect-names = "qup-core", "qup-config"; 1768 power-domains = <&rpmhpd SA8775P_CX>; 1769 status = "disabled"; 1770 }; 1771 }; 1772 1773 gpi_dma1: qcom,gpi-dma@a00000 { 1774 compatible = "qcom,sm6350-gpi-dma"; 1775 reg = <0x0 0x00a00000 0x0 0x60000>; 1776 #dma-cells = <3>; 1777 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1789 iommus = <&apps_smmu 0x456 0x0>; 1790 dma-channels = <12>; 1791 dma-channel-mask = <0xfff>; 1792 status = "disabled"; 1793 }; 1794 1795 qupv3_id_1: geniqup@ac0000 { 1796 compatible = "qcom,geni-se-qup"; 1797 reg = <0x0 0x00ac0000 0x0 0x6000>; 1798 #address-cells = <2>; 1799 #size-cells = <2>; 1800 ranges; 1801 clock-names = "m-ahb", "s-ahb"; 1802 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1803 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1804 iommus = <&apps_smmu 0x443 0x0>; 1805 status = "disabled"; 1806 1807 i2c7: i2c@a80000 { 1808 compatible = "qcom,geni-i2c"; 1809 reg = <0x0 0xa80000 0x0 0x4000>; 1810 #address-cells = <1>; 1811 #size-cells = <0>; 1812 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1813 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1814 clock-names = "se"; 1815 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1816 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1817 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1818 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1819 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1820 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1821 interconnect-names = "qup-core", 1822 "qup-config", 1823 "qup-memory"; 1824 power-domains = <&rpmhpd SA8775P_CX>; 1825 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1826 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1827 dma-names = "tx", 1828 "rx"; 1829 status = "disabled"; 1830 }; 1831 1832 spi7: spi@a80000 { 1833 compatible = "qcom,geni-spi"; 1834 reg = <0x0 0xa80000 0x0 0x4000>; 1835 #address-cells = <1>; 1836 #size-cells = <0>; 1837 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1838 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1839 clock-names = "se"; 1840 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1841 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1842 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1843 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1844 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1845 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1846 interconnect-names = "qup-core", 1847 "qup-config", 1848 "qup-memory"; 1849 power-domains = <&rpmhpd SA8775P_CX>; 1850 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1851 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1852 dma-names = "tx", 1853 "rx"; 1854 status = "disabled"; 1855 }; 1856 1857 uart7: serial@a80000 { 1858 compatible = "qcom,geni-uart"; 1859 reg = <0x0 0x00a80000 0x0 0x4000>; 1860 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1861 clock-names = "se"; 1862 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1863 interconnect-names = "qup-core", "qup-config"; 1864 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1865 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1866 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1867 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1868 power-domains = <&rpmhpd SA8775P_CX>; 1869 operating-points-v2 = <&qup_opp_table_100mhz>; 1870 status = "disabled"; 1871 }; 1872 1873 i2c8: i2c@a84000 { 1874 compatible = "qcom,geni-i2c"; 1875 reg = <0x0 0xa84000 0x0 0x4000>; 1876 #address-cells = <1>; 1877 #size-cells = <0>; 1878 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1879 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1880 clock-names = "se"; 1881 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1882 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1883 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1884 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1885 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1886 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1887 interconnect-names = "qup-core", 1888 "qup-config", 1889 "qup-memory"; 1890 power-domains = <&rpmhpd SA8775P_CX>; 1891 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1892 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1893 dma-names = "tx", 1894 "rx"; 1895 status = "disabled"; 1896 }; 1897 1898 spi8: spi@a84000 { 1899 compatible = "qcom,geni-spi"; 1900 reg = <0x0 0xa84000 0x0 0x4000>; 1901 #address-cells = <1>; 1902 #size-cells = <0>; 1903 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1905 clock-names = "se"; 1906 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1907 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1908 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1909 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1910 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1911 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1912 interconnect-names = "qup-core", 1913 "qup-config", 1914 "qup-memory"; 1915 power-domains = <&rpmhpd SA8775P_CX>; 1916 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1917 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1918 dma-names = "tx", 1919 "rx"; 1920 status = "disabled"; 1921 }; 1922 1923 uart8: serial@a84000 { 1924 compatible = "qcom,geni-uart"; 1925 reg = <0x0 0x00a84000 0x0 0x4000>; 1926 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1927 clock-names = "se"; 1928 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1929 interconnect-names = "qup-core", "qup-config"; 1930 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1931 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1932 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1933 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1934 power-domains = <&rpmhpd SA8775P_CX>; 1935 operating-points-v2 = <&qup_opp_table_100mhz>; 1936 status = "disabled"; 1937 }; 1938 1939 i2c9: i2c@a88000 { 1940 compatible = "qcom,geni-i2c"; 1941 reg = <0x0 0xa88000 0x0 0x4000>; 1942 #address-cells = <1>; 1943 #size-cells = <0>; 1944 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1945 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1946 clock-names = "se"; 1947 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1948 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1949 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1950 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1951 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1953 interconnect-names = "qup-core", 1954 "qup-config", 1955 "qup-memory"; 1956 power-domains = <&rpmhpd SA8775P_CX>; 1957 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1958 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1959 dma-names = "tx", 1960 "rx"; 1961 status = "disabled"; 1962 }; 1963 1964 spi9: spi@a88000 { 1965 compatible = "qcom,geni-spi"; 1966 reg = <0x0 0xa88000 0x0 0x4000>; 1967 #address-cells = <1>; 1968 #size-cells = <0>; 1969 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1970 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1971 clock-names = "se"; 1972 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1973 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1974 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1975 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1976 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1977 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1978 interconnect-names = "qup-core", 1979 "qup-config", 1980 "qup-memory"; 1981 power-domains = <&rpmhpd SA8775P_CX>; 1982 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1983 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1984 dma-names = "tx", 1985 "rx"; 1986 status = "disabled"; 1987 }; 1988 1989 uart9: serial@a88000 { 1990 compatible = "qcom,geni-uart"; 1991 reg = <0x0 0xa88000 0x0 0x4000>; 1992 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1993 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1994 clock-names = "se"; 1995 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1996 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1997 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1998 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1999 interconnect-names = "qup-core", "qup-config"; 2000 power-domains = <&rpmhpd SA8775P_CX>; 2001 status = "disabled"; 2002 }; 2003 2004 i2c10: i2c@a8c000 { 2005 compatible = "qcom,geni-i2c"; 2006 reg = <0x0 0xa8c000 0x0 0x4000>; 2007 #address-cells = <1>; 2008 #size-cells = <0>; 2009 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2010 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2011 clock-names = "se"; 2012 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2013 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2014 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2015 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2016 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2017 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2018 interconnect-names = "qup-core", 2019 "qup-config", 2020 "qup-memory"; 2021 power-domains = <&rpmhpd SA8775P_CX>; 2022 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 2023 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 2024 dma-names = "tx", 2025 "rx"; 2026 status = "disabled"; 2027 }; 2028 2029 spi10: spi@a8c000 { 2030 compatible = "qcom,geni-spi"; 2031 reg = <0x0 0xa8c000 0x0 0x4000>; 2032 #address-cells = <1>; 2033 #size-cells = <0>; 2034 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2035 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2036 clock-names = "se"; 2037 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2038 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2039 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2040 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2041 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2042 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2043 interconnect-names = "qup-core", 2044 "qup-config", 2045 "qup-memory"; 2046 power-domains = <&rpmhpd SA8775P_CX>; 2047 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 2048 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 2049 dma-names = "tx", 2050 "rx"; 2051 status = "disabled"; 2052 }; 2053 2054 uart10: serial@a8c000 { 2055 compatible = "qcom,geni-uart"; 2056 reg = <0x0 0x00a8c000 0x0 0x4000>; 2057 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2058 clock-names = "se"; 2059 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2060 interconnect-names = "qup-core", "qup-config"; 2061 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 2062 &clk_virt SLAVE_QUP_CORE_1 0>, 2063 <&gem_noc MASTER_APPSS_PROC 0 2064 &config_noc SLAVE_QUP_1 0>; 2065 power-domains = <&rpmhpd SA8775P_CX>; 2066 operating-points-v2 = <&qup_opp_table_100mhz>; 2067 status = "disabled"; 2068 }; 2069 2070 i2c11: i2c@a90000 { 2071 compatible = "qcom,geni-i2c"; 2072 reg = <0x0 0xa90000 0x0 0x4000>; 2073 #address-cells = <1>; 2074 #size-cells = <0>; 2075 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2076 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2077 clock-names = "se"; 2078 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2079 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2080 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2081 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2082 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2083 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2084 interconnect-names = "qup-core", 2085 "qup-config", 2086 "qup-memory"; 2087 power-domains = <&rpmhpd SA8775P_CX>; 2088 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2089 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2090 dma-names = "tx", 2091 "rx"; 2092 status = "disabled"; 2093 }; 2094 2095 spi11: spi@a90000 { 2096 compatible = "qcom,geni-spi"; 2097 reg = <0x0 0xa90000 0x0 0x4000>; 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2101 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2102 clock-names = "se"; 2103 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2104 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2105 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2106 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2107 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2108 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2109 interconnect-names = "qup-core", 2110 "qup-config", 2111 "qup-memory"; 2112 power-domains = <&rpmhpd SA8775P_CX>; 2113 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2114 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2115 dma-names = "tx", 2116 "rx"; 2117 status = "disabled"; 2118 }; 2119 2120 uart11: serial@a90000 { 2121 compatible = "qcom,geni-uart"; 2122 reg = <0x0 0x00a90000 0x0 0x4000>; 2123 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2124 clock-names = "se"; 2125 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2126 interconnect-names = "qup-core", "qup-config"; 2127 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2128 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2129 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2130 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2131 power-domains = <&rpmhpd SA8775P_CX>; 2132 operating-points-v2 = <&qup_opp_table_100mhz>; 2133 status = "disabled"; 2134 }; 2135 2136 i2c12: i2c@a94000 { 2137 compatible = "qcom,geni-i2c"; 2138 reg = <0x0 0xa94000 0x0 0x4000>; 2139 #address-cells = <1>; 2140 #size-cells = <0>; 2141 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2142 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2143 clock-names = "se"; 2144 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2145 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2146 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2147 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2148 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2149 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2150 interconnect-names = "qup-core", 2151 "qup-config", 2152 "qup-memory"; 2153 power-domains = <&rpmhpd SA8775P_CX>; 2154 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2155 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2156 dma-names = "tx", 2157 "rx"; 2158 status = "disabled"; 2159 }; 2160 2161 spi12: spi@a94000 { 2162 compatible = "qcom,geni-spi"; 2163 reg = <0x0 0xa94000 0x0 0x4000>; 2164 #address-cells = <1>; 2165 #size-cells = <0>; 2166 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2167 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2168 clock-names = "se"; 2169 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2170 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2171 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2172 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2173 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2174 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2175 interconnect-names = "qup-core", 2176 "qup-config", 2177 "qup-memory"; 2178 power-domains = <&rpmhpd SA8775P_CX>; 2179 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2180 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2181 dma-names = "tx", 2182 "rx"; 2183 status = "disabled"; 2184 }; 2185 2186 uart12: serial@a94000 { 2187 compatible = "qcom,geni-uart"; 2188 reg = <0x0 0x00a94000 0x0 0x4000>; 2189 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2190 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2191 clock-names = "se"; 2192 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2193 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2194 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2195 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2196 interconnect-names = "qup-core", "qup-config"; 2197 power-domains = <&rpmhpd SA8775P_CX>; 2198 status = "disabled"; 2199 }; 2200 2201 i2c13: i2c@a98000 { 2202 compatible = "qcom,geni-i2c"; 2203 reg = <0x0 0xa98000 0x0 0x4000>; 2204 #address-cells = <1>; 2205 #size-cells = <0>; 2206 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2207 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2208 clock-names = "se"; 2209 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2210 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2211 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2212 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2213 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2214 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2215 interconnect-names = "qup-core", 2216 "qup-config", 2217 "qup-memory"; 2218 power-domains = <&rpmhpd SA8775P_CX>; 2219 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2220 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2221 dma-names = "tx", 2222 "rx"; 2223 status = "disabled"; 2224 2225 }; 2226 }; 2227 2228 gpi_dma3: qcom,gpi-dma@b00000 { 2229 compatible = "qcom,sm6350-gpi-dma"; 2230 reg = <0x0 0x00b00000 0x0 0x58000>; 2231 #dma-cells = <3>; 2232 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2236 iommus = <&apps_smmu 0x056 0x0>; 2237 dma-channels = <4>; 2238 dma-channel-mask = <0xf>; 2239 status = "disabled"; 2240 }; 2241 2242 qupv3_id_3: geniqup@bc0000 { 2243 compatible = "qcom,geni-se-qup"; 2244 reg = <0x0 0xbc0000 0x0 0x6000>; 2245 #address-cells = <2>; 2246 #size-cells = <2>; 2247 ranges; 2248 clock-names = "m-ahb", "s-ahb"; 2249 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2250 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2251 iommus = <&apps_smmu 0x43 0x0>; 2252 status = "disabled"; 2253 2254 i2c21: i2c@b80000 { 2255 compatible = "qcom,geni-i2c"; 2256 reg = <0x0 0xb80000 0x0 0x4000>; 2257 #address-cells = <1>; 2258 #size-cells = <0>; 2259 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2260 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2261 clock-names = "se"; 2262 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2263 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2264 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2265 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2266 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2267 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2268 interconnect-names = "qup-core", 2269 "qup-config", 2270 "qup-memory"; 2271 power-domains = <&rpmhpd SA8775P_CX>; 2272 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2273 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2274 dma-names = "tx", 2275 "rx"; 2276 status = "disabled"; 2277 }; 2278 2279 spi21: spi@b80000 { 2280 compatible = "qcom,geni-spi"; 2281 reg = <0x0 0xb80000 0x0 0x4000>; 2282 #address-cells = <1>; 2283 #size-cells = <0>; 2284 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2285 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2286 clock-names = "se"; 2287 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2288 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2289 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2290 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2291 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2292 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2293 interconnect-names = "qup-core", 2294 "qup-config", 2295 "qup-memory"; 2296 power-domains = <&rpmhpd SA8775P_CX>; 2297 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2298 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2299 dma-names = "tx", 2300 "rx"; 2301 status = "disabled"; 2302 }; 2303 2304 uart21: serial@b80000 { 2305 compatible = "qcom,geni-uart"; 2306 reg = <0x0 0x00b80000 0x0 0x4000>; 2307 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2308 clock-names = "se"; 2309 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2310 interconnect-names = "qup-core", "qup-config"; 2311 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2312 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2313 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2314 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2315 power-domains = <&rpmhpd SA8775P_CX>; 2316 operating-points-v2 = <&qup_opp_table_100mhz>; 2317 status = "disabled"; 2318 }; 2319 }; 2320 2321 rng: rng@10d2000 { 2322 compatible = "qcom,sa8775p-trng", "qcom,trng"; 2323 reg = <0 0x010d2000 0 0x1000>; 2324 }; 2325 2326 ufs_mem_hc: ufshc@1d84000 { 2327 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2328 reg = <0x0 0x01d84000 0x0 0x3000>; 2329 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2330 phys = <&ufs_mem_phy>; 2331 phy-names = "ufsphy"; 2332 lanes-per-direction = <2>; 2333 #reset-cells = <1>; 2334 resets = <&gcc GCC_UFS_PHY_BCR>; 2335 reset-names = "rst"; 2336 power-domains = <&gcc UFS_PHY_GDSC>; 2337 required-opps = <&rpmhpd_opp_nom>; 2338 iommus = <&apps_smmu 0x100 0x0>; 2339 dma-coherent; 2340 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2341 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2342 <&gcc GCC_UFS_PHY_AHB_CLK>, 2343 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2344 <&rpmhcc RPMH_CXO_CLK>, 2345 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2346 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2347 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2348 clock-names = "core_clk", 2349 "bus_aggr_clk", 2350 "iface_clk", 2351 "core_clk_unipro", 2352 "ref_clk", 2353 "tx_lane0_sync_clk", 2354 "rx_lane0_sync_clk", 2355 "rx_lane1_sync_clk"; 2356 freq-table-hz = <75000000 300000000>, 2357 <0 0>, 2358 <0 0>, 2359 <75000000 300000000>, 2360 <0 0>, 2361 <0 0>, 2362 <0 0>, 2363 <0 0>; 2364 qcom,ice = <&ice>; 2365 status = "disabled"; 2366 }; 2367 2368 ufs_mem_phy: phy@1d87000 { 2369 compatible = "qcom,sa8775p-qmp-ufs-phy"; 2370 reg = <0x0 0x01d87000 0x0 0xe10>; 2371 /* 2372 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2373 * enables the CXO clock to eDP *and* UFS PHY. 2374 */ 2375 clocks = <&rpmhcc RPMH_CXO_CLK>, 2376 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2377 <&gcc GCC_EDP_REF_CLKREF_EN>; 2378 clock-names = "ref", "ref_aux", "qref"; 2379 power-domains = <&gcc UFS_PHY_GDSC>; 2380 resets = <&ufs_mem_hc 0>; 2381 reset-names = "ufsphy"; 2382 #phy-cells = <0>; 2383 status = "disabled"; 2384 }; 2385 2386 ice: crypto@1d88000 { 2387 compatible = "qcom,sa8775p-inline-crypto-engine", 2388 "qcom,inline-crypto-engine"; 2389 reg = <0x0 0x01d88000 0x0 0x18000>; 2390 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2391 }; 2392 2393 cryptobam: dma-controller@1dc4000 { 2394 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2395 reg = <0x0 0x01dc4000 0x0 0x28000>; 2396 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2397 #dma-cells = <1>; 2398 qcom,ee = <0>; 2399 qcom,controlled-remotely; 2400 iommus = <&apps_smmu 0x480 0x00>, 2401 <&apps_smmu 0x481 0x00>; 2402 }; 2403 2404 crypto: crypto@1dfa000 { 2405 compatible = "qcom,sa8775p-qce", "qcom,qce"; 2406 reg = <0x0 0x01dfa000 0x0 0x6000>; 2407 dmas = <&cryptobam 4>, <&cryptobam 5>; 2408 dma-names = "rx", "tx"; 2409 iommus = <&apps_smmu 0x480 0x00>, 2410 <&apps_smmu 0x481 0x00>; 2411 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 0 &mc_virt SLAVE_EBI1 0>; 2412 interconnect-names = "memory"; 2413 }; 2414 2415 stm: stm@4002000 { 2416 compatible = "arm,coresight-stm", "arm,primecell"; 2417 reg = <0x0 0x4002000 0x0 0x1000>, 2418 <0x0 0x16280000 0x0 0x180000>; 2419 reg-names = "stm-base", "stm-stimulus-base"; 2420 2421 clocks = <&aoss_qmp>; 2422 clock-names = "apb_pclk"; 2423 2424 out-ports { 2425 port { 2426 stm_out: endpoint { 2427 remote-endpoint = 2428 <&funnel0_in7>; 2429 }; 2430 }; 2431 }; 2432 }; 2433 2434 tpdm@4003000 { 2435 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2436 reg = <0x0 0x4003000 0x0 0x1000>; 2437 2438 clocks = <&aoss_qmp>; 2439 clock-names = "apb_pclk"; 2440 2441 qcom,cmb-element-bits = <32>; 2442 qcom,cmb-msrs-num = <32>; 2443 status = "disabled"; 2444 2445 out-ports { 2446 port { 2447 qdss_tpdm0_out: endpoint { 2448 remote-endpoint = 2449 <&qdss_tpda_in0>; 2450 }; 2451 }; 2452 }; 2453 }; 2454 2455 tpda@4004000 { 2456 compatible = "qcom,coresight-tpda", "arm,primecell"; 2457 reg = <0x0 0x4004000 0x0 0x1000>; 2458 2459 clocks = <&aoss_qmp>; 2460 clock-names = "apb_pclk"; 2461 2462 out-ports { 2463 port { 2464 qdss_tpda_out: endpoint { 2465 remote-endpoint = 2466 <&funnel0_in6>; 2467 }; 2468 }; 2469 }; 2470 2471 in-ports { 2472 #address-cells = <1>; 2473 #size-cells = <0>; 2474 2475 port@0 { 2476 reg = <0>; 2477 qdss_tpda_in0: endpoint { 2478 remote-endpoint = 2479 <&qdss_tpdm0_out>; 2480 }; 2481 }; 2482 2483 port@1 { 2484 reg = <1>; 2485 qdss_tpda_in1: endpoint { 2486 remote-endpoint = 2487 <&qdss_tpdm1_out>; 2488 }; 2489 }; 2490 }; 2491 }; 2492 2493 tpdm@400f000 { 2494 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2495 reg = <0x0 0x400f000 0x0 0x1000>; 2496 2497 clocks = <&aoss_qmp>; 2498 clock-names = "apb_pclk"; 2499 2500 qcom,cmb-element-bits = <32>; 2501 qcom,cmb-msrs-num = <32>; 2502 2503 out-ports { 2504 port { 2505 qdss_tpdm1_out: endpoint { 2506 remote-endpoint = 2507 <&qdss_tpda_in1>; 2508 }; 2509 }; 2510 }; 2511 }; 2512 2513 funnel@4041000 { 2514 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2515 reg = <0x0 0x4041000 0x0 0x1000>; 2516 2517 clocks = <&aoss_qmp>; 2518 clock-names = "apb_pclk"; 2519 2520 out-ports { 2521 port { 2522 funnel0_out: endpoint { 2523 remote-endpoint = 2524 <&qdss_funnel_in0>; 2525 }; 2526 }; 2527 }; 2528 2529 in-ports { 2530 #address-cells = <1>; 2531 #size-cells = <0>; 2532 2533 port@6 { 2534 reg = <6>; 2535 funnel0_in6: endpoint { 2536 remote-endpoint = 2537 <&qdss_tpda_out>; 2538 }; 2539 }; 2540 2541 port@7 { 2542 reg = <7>; 2543 funnel0_in7: endpoint { 2544 remote-endpoint = 2545 <&stm_out>; 2546 }; 2547 }; 2548 }; 2549 }; 2550 2551 funnel@4042000 { 2552 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2553 reg = <0x0 0x4042000 0x0 0x1000>; 2554 2555 clocks = <&aoss_qmp>; 2556 clock-names = "apb_pclk"; 2557 2558 out-ports { 2559 port { 2560 funnel1_out: endpoint { 2561 remote-endpoint = 2562 <&qdss_funnel_in1>; 2563 }; 2564 }; 2565 }; 2566 2567 in-ports { 2568 #address-cells = <1>; 2569 #size-cells = <0>; 2570 2571 port@4 { 2572 reg = <4>; 2573 funnel1_in4: endpoint { 2574 remote-endpoint = 2575 <&apss_funnel1_out>; 2576 }; 2577 }; 2578 }; 2579 }; 2580 2581 funnel@4045000 { 2582 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2583 reg = <0x0 0x4045000 0x0 0x1000>; 2584 2585 clocks = <&aoss_qmp>; 2586 clock-names = "apb_pclk"; 2587 2588 out-ports { 2589 port { 2590 qdss_funnel_out: endpoint { 2591 remote-endpoint = 2592 <&aoss_funnel_in7>; 2593 }; 2594 }; 2595 }; 2596 2597 in-ports { 2598 #address-cells = <1>; 2599 #size-cells = <0>; 2600 2601 port@0 { 2602 reg = <0>; 2603 qdss_funnel_in0: endpoint { 2604 remote-endpoint = 2605 <&funnel0_out>; 2606 }; 2607 }; 2608 2609 port@1 { 2610 reg = <1>; 2611 qdss_funnel_in1: endpoint { 2612 remote-endpoint = 2613 <&funnel1_out>; 2614 }; 2615 }; 2616 }; 2617 }; 2618 2619 funnel@4b04000 { 2620 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2621 reg = <0x0 0x4b04000 0x0 0x1000>; 2622 2623 clocks = <&aoss_qmp>; 2624 clock-names = "apb_pclk"; 2625 2626 out-ports { 2627 port { 2628 aoss_funnel_out: endpoint { 2629 remote-endpoint = 2630 <&etf0_in>; 2631 }; 2632 }; 2633 }; 2634 2635 in-ports { 2636 #address-cells = <1>; 2637 #size-cells = <0>; 2638 2639 port@6 { 2640 reg = <6>; 2641 aoss_funnel_in6: endpoint { 2642 remote-endpoint = 2643 <&aoss_tpda_out>; 2644 }; 2645 }; 2646 2647 port@7 { 2648 reg = <7>; 2649 aoss_funnel_in7: endpoint { 2650 remote-endpoint = 2651 <&qdss_funnel_out>; 2652 }; 2653 }; 2654 }; 2655 }; 2656 2657 tmc_etf: tmc@4b05000 { 2658 compatible = "arm,coresight-tmc", "arm,primecell"; 2659 reg = <0x0 0x4b05000 0x0 0x1000>; 2660 2661 clocks = <&aoss_qmp>; 2662 clock-names = "apb_pclk"; 2663 2664 out-ports { 2665 port { 2666 etf0_out: endpoint { 2667 remote-endpoint = 2668 <&swao_rep_in>; 2669 }; 2670 }; 2671 }; 2672 2673 in-ports { 2674 port { 2675 etf0_in: endpoint { 2676 remote-endpoint = 2677 <&aoss_funnel_out>; 2678 }; 2679 }; 2680 }; 2681 }; 2682 2683 replicator@4b06000 { 2684 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2685 reg = <0x0 0x4b06000 0x0 0x1000>; 2686 2687 clocks = <&aoss_qmp>; 2688 clock-names = "apb_pclk"; 2689 2690 out-ports { 2691 #address-cells = <1>; 2692 #size-cells = <0>; 2693 2694 port@1 { 2695 reg = <1>; 2696 swao_rep_out1: endpoint { 2697 remote-endpoint = 2698 <&eud_in>; 2699 }; 2700 }; 2701 }; 2702 2703 in-ports { 2704 port { 2705 swao_rep_in: endpoint { 2706 remote-endpoint = 2707 <&etf0_out>; 2708 }; 2709 }; 2710 }; 2711 }; 2712 2713 tpda@4b08000 { 2714 compatible = "qcom,coresight-tpda", "arm,primecell"; 2715 reg = <0x0 0x4b08000 0x0 0x1000>; 2716 2717 clocks = <&aoss_qmp>; 2718 clock-names = "apb_pclk"; 2719 2720 out-ports { 2721 port { 2722 aoss_tpda_out: endpoint { 2723 remote-endpoint = 2724 <&aoss_funnel_in6>; 2725 }; 2726 }; 2727 }; 2728 2729 in-ports { 2730 #address-cells = <1>; 2731 #size-cells = <0>; 2732 2733 port@0 { 2734 reg = <0>; 2735 aoss_tpda_in0: endpoint { 2736 remote-endpoint = 2737 <&aoss_tpdm0_out>; 2738 }; 2739 }; 2740 2741 port@1 { 2742 reg = <1>; 2743 aoss_tpda_in1: endpoint { 2744 remote-endpoint = 2745 <&aoss_tpdm1_out>; 2746 }; 2747 }; 2748 2749 port@2 { 2750 reg = <2>; 2751 aoss_tpda_in2: endpoint { 2752 remote-endpoint = 2753 <&aoss_tpdm2_out>; 2754 }; 2755 }; 2756 2757 port@3 { 2758 reg = <3>; 2759 aoss_tpda_in3: endpoint { 2760 remote-endpoint = 2761 <&aoss_tpdm3_out>; 2762 }; 2763 }; 2764 2765 port@4 { 2766 reg = <4>; 2767 aoss_tpda_in4: endpoint { 2768 remote-endpoint = 2769 <&aoss_tpdm4_out>; 2770 }; 2771 }; 2772 }; 2773 }; 2774 2775 tpdm@4b09000 { 2776 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2777 reg = <0x0 0x4b09000 0x0 0x1000>; 2778 2779 clocks = <&aoss_qmp>; 2780 clock-names = "apb_pclk"; 2781 2782 qcom,cmb-element-bits = <64>; 2783 qcom,cmb-msrs-num = <32>; 2784 2785 out-ports { 2786 port { 2787 aoss_tpdm0_out: endpoint { 2788 remote-endpoint = 2789 <&aoss_tpda_in0>; 2790 }; 2791 }; 2792 }; 2793 }; 2794 2795 tpdm@4b0a000 { 2796 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2797 reg = <0x0 0x4b0a000 0x0 0x1000>; 2798 2799 clocks = <&aoss_qmp>; 2800 clock-names = "apb_pclk"; 2801 2802 qcom,cmb-element-bits = <64>; 2803 qcom,cmb-msrs-num = <32>; 2804 2805 out-ports { 2806 port { 2807 aoss_tpdm1_out: endpoint { 2808 remote-endpoint = 2809 <&aoss_tpda_in1>; 2810 }; 2811 }; 2812 }; 2813 }; 2814 2815 tpdm@4b0b000 { 2816 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2817 reg = <0x0 0x4b0b000 0x0 0x1000>; 2818 2819 clocks = <&aoss_qmp>; 2820 clock-names = "apb_pclk"; 2821 2822 qcom,cmb-element-bits = <64>; 2823 qcom,cmb-msrs-num = <32>; 2824 2825 out-ports { 2826 port { 2827 aoss_tpdm2_out: endpoint { 2828 remote-endpoint = 2829 <&aoss_tpda_in2>; 2830 }; 2831 }; 2832 }; 2833 }; 2834 2835 tpdm@4b0c000 { 2836 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2837 reg = <0x0 0x4b0c000 0x0 0x1000>; 2838 2839 clocks = <&aoss_qmp>; 2840 clock-names = "apb_pclk"; 2841 2842 qcom,cmb-element-bits = <64>; 2843 qcom,cmb-msrs-num = <32>; 2844 2845 out-ports { 2846 port { 2847 aoss_tpdm3_out: endpoint { 2848 remote-endpoint = 2849 <&aoss_tpda_in3>; 2850 }; 2851 }; 2852 }; 2853 }; 2854 2855 tpdm@4b0d000 { 2856 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2857 reg = <0x0 0x4b0d000 0x0 0x1000>; 2858 2859 clocks = <&aoss_qmp>; 2860 clock-names = "apb_pclk"; 2861 2862 qcom,dsb-element-bits = <32>; 2863 qcom,dsb-msrs-num = <32>; 2864 2865 out-ports { 2866 port { 2867 aoss_tpdm4_out: endpoint { 2868 remote-endpoint = 2869 <&aoss_tpda_in4>; 2870 }; 2871 }; 2872 }; 2873 }; 2874 2875 aoss_cti: cti@4b13000 { 2876 compatible = "arm,coresight-cti", "arm,primecell"; 2877 reg = <0x0 0x4b13000 0x0 0x1000>; 2878 2879 clocks = <&aoss_qmp>; 2880 clock-names = "apb_pclk"; 2881 }; 2882 2883 etm@6040000 { 2884 compatible = "arm,primecell"; 2885 reg = <0x0 0x6040000 0x0 0x1000>; 2886 cpu = <&cpu0>; 2887 2888 clocks = <&aoss_qmp>; 2889 clock-names = "apb_pclk"; 2890 arm,coresight-loses-context-with-cpu; 2891 qcom,skip-power-up; 2892 2893 out-ports { 2894 port { 2895 etm0_out: endpoint { 2896 remote-endpoint = 2897 <&apss_funnel0_in0>; 2898 }; 2899 }; 2900 }; 2901 }; 2902 2903 etm@6140000 { 2904 compatible = "arm,primecell"; 2905 reg = <0x0 0x6140000 0x0 0x1000>; 2906 cpu = <&cpu1>; 2907 2908 clocks = <&aoss_qmp>; 2909 clock-names = "apb_pclk"; 2910 arm,coresight-loses-context-with-cpu; 2911 qcom,skip-power-up; 2912 2913 out-ports { 2914 port { 2915 etm1_out: endpoint { 2916 remote-endpoint = 2917 <&apss_funnel0_in1>; 2918 }; 2919 }; 2920 }; 2921 }; 2922 2923 etm@6240000 { 2924 compatible = "arm,primecell"; 2925 reg = <0x0 0x6240000 0x0 0x1000>; 2926 cpu = <&cpu2>; 2927 2928 clocks = <&aoss_qmp>; 2929 clock-names = "apb_pclk"; 2930 arm,coresight-loses-context-with-cpu; 2931 qcom,skip-power-up; 2932 2933 out-ports { 2934 port { 2935 etm2_out: endpoint { 2936 remote-endpoint = 2937 <&apss_funnel0_in2>; 2938 }; 2939 }; 2940 }; 2941 }; 2942 2943 etm@6340000 { 2944 compatible = "arm,primecell"; 2945 reg = <0x0 0x6340000 0x0 0x1000>; 2946 cpu = <&cpu3>; 2947 2948 clocks = <&aoss_qmp>; 2949 clock-names = "apb_pclk"; 2950 arm,coresight-loses-context-with-cpu; 2951 qcom,skip-power-up; 2952 2953 out-ports { 2954 port { 2955 etm3_out: endpoint { 2956 remote-endpoint = 2957 <&apss_funnel0_in3>; 2958 }; 2959 }; 2960 }; 2961 }; 2962 2963 etm@6440000 { 2964 compatible = "arm,primecell"; 2965 reg = <0x0 0x6440000 0x0 0x1000>; 2966 cpu = <&cpu4>; 2967 2968 clocks = <&aoss_qmp>; 2969 clock-names = "apb_pclk"; 2970 arm,coresight-loses-context-with-cpu; 2971 qcom,skip-power-up; 2972 2973 out-ports { 2974 port { 2975 etm4_out: endpoint { 2976 remote-endpoint = 2977 <&apss_funnel0_in4>; 2978 }; 2979 }; 2980 }; 2981 }; 2982 2983 etm@6540000 { 2984 compatible = "arm,primecell"; 2985 reg = <0x0 0x6540000 0x0 0x1000>; 2986 cpu = <&cpu5>; 2987 2988 clocks = <&aoss_qmp>; 2989 clock-names = "apb_pclk"; 2990 arm,coresight-loses-context-with-cpu; 2991 qcom,skip-power-up; 2992 2993 out-ports { 2994 port { 2995 etm5_out: endpoint { 2996 remote-endpoint = 2997 <&apss_funnel0_in5>; 2998 }; 2999 }; 3000 }; 3001 }; 3002 3003 etm@6640000 { 3004 compatible = "arm,primecell"; 3005 reg = <0x0 0x6640000 0x0 0x1000>; 3006 cpu = <&cpu6>; 3007 3008 clocks = <&aoss_qmp>; 3009 clock-names = "apb_pclk"; 3010 arm,coresight-loses-context-with-cpu; 3011 qcom,skip-power-up; 3012 3013 out-ports { 3014 port { 3015 etm6_out: endpoint { 3016 remote-endpoint = 3017 <&apss_funnel0_in6>; 3018 }; 3019 }; 3020 }; 3021 }; 3022 3023 etm@6740000 { 3024 compatible = "arm,primecell"; 3025 reg = <0x0 0x6740000 0x0 0x1000>; 3026 cpu = <&cpu7>; 3027 3028 clocks = <&aoss_qmp>; 3029 clock-names = "apb_pclk"; 3030 arm,coresight-loses-context-with-cpu; 3031 qcom,skip-power-up; 3032 3033 out-ports { 3034 port { 3035 etm7_out: endpoint { 3036 remote-endpoint = 3037 <&apss_funnel0_in7>; 3038 }; 3039 }; 3040 }; 3041 }; 3042 3043 funnel@6800000 { 3044 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3045 reg = <0x0 0x6800000 0x0 0x1000>; 3046 3047 clocks = <&aoss_qmp>; 3048 clock-names = "apb_pclk"; 3049 3050 out-ports { 3051 port { 3052 apss_funnel0_out: endpoint { 3053 remote-endpoint = 3054 <&apss_funnel1_in0>; 3055 }; 3056 }; 3057 }; 3058 3059 in-ports { 3060 #address-cells = <1>; 3061 #size-cells = <0>; 3062 3063 port@0 { 3064 reg = <0>; 3065 apss_funnel0_in0: endpoint { 3066 remote-endpoint = 3067 <&etm0_out>; 3068 }; 3069 }; 3070 3071 port@1 { 3072 reg = <1>; 3073 apss_funnel0_in1: endpoint { 3074 remote-endpoint = 3075 <&etm1_out>; 3076 }; 3077 }; 3078 3079 port@2 { 3080 reg = <2>; 3081 apss_funnel0_in2: endpoint { 3082 remote-endpoint = 3083 <&etm2_out>; 3084 }; 3085 }; 3086 3087 port@3 { 3088 reg = <3>; 3089 apss_funnel0_in3: endpoint { 3090 remote-endpoint = 3091 <&etm3_out>; 3092 }; 3093 }; 3094 3095 port@4 { 3096 reg = <4>; 3097 apss_funnel0_in4: endpoint { 3098 remote-endpoint = 3099 <&etm4_out>; 3100 }; 3101 }; 3102 3103 port@5 { 3104 reg = <5>; 3105 apss_funnel0_in5: endpoint { 3106 remote-endpoint = 3107 <&etm5_out>; 3108 }; 3109 }; 3110 3111 port@6 { 3112 reg = <6>; 3113 apss_funnel0_in6: endpoint { 3114 remote-endpoint = 3115 <&etm6_out>; 3116 }; 3117 }; 3118 3119 port@7 { 3120 reg = <7>; 3121 apss_funnel0_in7: endpoint { 3122 remote-endpoint = 3123 <&etm7_out>; 3124 }; 3125 }; 3126 }; 3127 }; 3128 3129 funnel@6810000 { 3130 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3131 reg = <0x0 0x6810000 0x0 0x1000>; 3132 3133 clocks = <&aoss_qmp>; 3134 clock-names = "apb_pclk"; 3135 3136 out-ports { 3137 port { 3138 apss_funnel1_out: endpoint { 3139 remote-endpoint = 3140 <&funnel1_in4>; 3141 }; 3142 }; 3143 }; 3144 3145 in-ports { 3146 #address-cells = <1>; 3147 #size-cells = <0>; 3148 3149 port@0 { 3150 reg = <0>; 3151 apss_funnel1_in0: endpoint { 3152 remote-endpoint = 3153 <&apss_funnel0_out>; 3154 }; 3155 }; 3156 3157 port@3 { 3158 reg = <3>; 3159 apss_funnel1_in3: endpoint { 3160 remote-endpoint = 3161 <&apss_tpda_out>; 3162 }; 3163 }; 3164 }; 3165 }; 3166 3167 tpdm@6860000 { 3168 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3169 reg = <0x0 0x6860000 0x0 0x1000>; 3170 3171 clocks = <&aoss_qmp>; 3172 clock-names = "apb_pclk"; 3173 3174 qcom,cmb-element-bits = <64>; 3175 qcom,cmb-msrs-num = <32>; 3176 3177 out-ports { 3178 port { 3179 apss_tpdm3_out: endpoint { 3180 remote-endpoint = 3181 <&apss_tpda_in3>; 3182 }; 3183 }; 3184 }; 3185 }; 3186 3187 tpdm@6861000 { 3188 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3189 reg = <0x0 0x6861000 0x0 0x1000>; 3190 3191 clocks = <&aoss_qmp>; 3192 clock-names = "apb_pclk"; 3193 3194 qcom,dsb-element-bits = <32>; 3195 qcom,dsb-msrs-num = <32>; 3196 3197 out-ports { 3198 port { 3199 apss_tpdm4_out: endpoint { 3200 remote-endpoint = 3201 <&apss_tpda_in4>; 3202 }; 3203 }; 3204 }; 3205 }; 3206 3207 tpda@6863000 { 3208 compatible = "qcom,coresight-tpda", "arm,primecell"; 3209 reg = <0x0 0x6863000 0x0 0x1000>; 3210 3211 clocks = <&aoss_qmp>; 3212 clock-names = "apb_pclk"; 3213 3214 out-ports { 3215 port { 3216 apss_tpda_out: endpoint { 3217 remote-endpoint = 3218 <&apss_funnel1_in3>; 3219 }; 3220 }; 3221 }; 3222 3223 in-ports { 3224 #address-cells = <1>; 3225 #size-cells = <0>; 3226 3227 port@0 { 3228 reg = <0>; 3229 apss_tpda_in0: endpoint { 3230 remote-endpoint = 3231 <&apss_tpdm0_out>; 3232 }; 3233 }; 3234 3235 port@1 { 3236 reg = <1>; 3237 apss_tpda_in1: endpoint { 3238 remote-endpoint = 3239 <&apss_tpdm1_out>; 3240 }; 3241 }; 3242 3243 port@2 { 3244 reg = <2>; 3245 apss_tpda_in2: endpoint { 3246 remote-endpoint = 3247 <&apss_tpdm2_out>; 3248 }; 3249 }; 3250 3251 port@3 { 3252 reg = <3>; 3253 apss_tpda_in3: endpoint { 3254 remote-endpoint = 3255 <&apss_tpdm3_out>; 3256 }; 3257 }; 3258 3259 port@4 { 3260 reg = <4>; 3261 apss_tpda_in4: endpoint { 3262 remote-endpoint = 3263 <&apss_tpdm4_out>; 3264 }; 3265 }; 3266 }; 3267 }; 3268 3269 tpdm@68a0000 { 3270 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3271 reg = <0x0 0x68a0000 0x0 0x1000>; 3272 3273 clocks = <&aoss_qmp>; 3274 clock-names = "apb_pclk"; 3275 3276 qcom,cmb-element-bits = <32>; 3277 qcom,cmb-msrs-num = <32>; 3278 3279 out-ports { 3280 port { 3281 apss_tpdm0_out: endpoint { 3282 remote-endpoint = 3283 <&apss_tpda_in0>; 3284 }; 3285 }; 3286 }; 3287 }; 3288 3289 tpdm@68b0000 { 3290 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3291 reg = <0x0 0x68b0000 0x0 0x1000>; 3292 3293 clocks = <&aoss_qmp>; 3294 clock-names = "apb_pclk"; 3295 3296 qcom,cmb-element-bits = <32>; 3297 qcom,cmb-msrs-num = <32>; 3298 3299 out-ports { 3300 port { 3301 apss_tpdm1_out: endpoint { 3302 remote-endpoint = 3303 <&apss_tpda_in1>; 3304 }; 3305 }; 3306 }; 3307 }; 3308 3309 tpdm@68c0000 { 3310 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3311 reg = <0x0 0x68c0000 0x0 0x1000>; 3312 3313 clocks = <&aoss_qmp>; 3314 clock-names = "apb_pclk"; 3315 3316 qcom,dsb-element-bits = <32>; 3317 qcom,dsb-msrs-num = <32>; 3318 3319 out-ports { 3320 port { 3321 apss_tpdm2_out: endpoint { 3322 remote-endpoint = 3323 <&apss_tpda_in2>; 3324 }; 3325 }; 3326 }; 3327 }; 3328 3329 usb_0_hsphy: phy@88e4000 { 3330 compatible = "qcom,sa8775p-usb-hs-phy", 3331 "qcom,usb-snps-hs-5nm-phy"; 3332 reg = <0 0x088e4000 0 0x120>; 3333 clocks = <&rpmhcc RPMH_CXO_CLK>; 3334 clock-names = "ref"; 3335 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 3336 3337 #phy-cells = <0>; 3338 3339 status = "disabled"; 3340 }; 3341 3342 usb_0_qmpphy: phy@88e8000 { 3343 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 3344 reg = <0 0x088e8000 0 0x2000>; 3345 3346 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3347 <&gcc GCC_USB_CLKREF_EN>, 3348 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3349 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3350 clock-names = "aux", "ref", "com_aux", "pipe"; 3351 3352 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3353 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 3354 reset-names = "phy", "phy_phy"; 3355 3356 power-domains = <&gcc USB30_PRIM_GDSC>; 3357 3358 #clock-cells = <0>; 3359 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 3360 3361 #phy-cells = <0>; 3362 3363 status = "disabled"; 3364 }; 3365 3366 usb_0: usb@a6f8800 { 3367 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 3368 reg = <0 0x0a6f8800 0 0x400>; 3369 #address-cells = <2>; 3370 #size-cells = <2>; 3371 ranges; 3372 3373 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3374 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3375 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3376 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3377 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3378 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3379 3380 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3381 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3382 assigned-clock-rates = <19200000>, <200000000>; 3383 3384 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 3385 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3386 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3387 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3388 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 3389 interrupt-names = "pwr_event", 3390 "hs_phy_irq", 3391 "dp_hs_phy_irq", 3392 "dm_hs_phy_irq", 3393 "ss_phy_irq"; 3394 3395 power-domains = <&gcc USB30_PRIM_GDSC>; 3396 required-opps = <&rpmhpd_opp_nom>; 3397 3398 resets = <&gcc GCC_USB30_PRIM_BCR>; 3399 3400 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3401 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3402 interconnect-names = "usb-ddr", "apps-usb"; 3403 3404 wakeup-source; 3405 3406 status = "disabled"; 3407 3408 usb_0_dwc3: usb@a600000 { 3409 compatible = "snps,dwc3"; 3410 reg = <0 0x0a600000 0 0xe000>; 3411 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 3412 iommus = <&apps_smmu 0x080 0x0>; 3413 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 3414 phy-names = "usb2-phy", "usb3-phy"; 3415 }; 3416 }; 3417 3418 usb_1_hsphy: phy@88e6000 { 3419 compatible = "qcom,sa8775p-usb-hs-phy", 3420 "qcom,usb-snps-hs-5nm-phy"; 3421 reg = <0 0x088e6000 0 0x120>; 3422 clocks = <&gcc GCC_USB_CLKREF_EN>; 3423 clock-names = "ref"; 3424 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 3425 3426 #phy-cells = <0>; 3427 3428 status = "disabled"; 3429 }; 3430 3431 usb_1_qmpphy: phy@88ea000 { 3432 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 3433 reg = <0 0x088ea000 0 0x2000>; 3434 3435 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3436 <&gcc GCC_USB_CLKREF_EN>, 3437 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3438 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3439 clock-names = "aux", "ref", "com_aux", "pipe"; 3440 3441 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3442 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3443 reset-names = "phy", "phy_phy"; 3444 3445 power-domains = <&gcc USB30_SEC_GDSC>; 3446 3447 #clock-cells = <0>; 3448 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 3449 3450 #phy-cells = <0>; 3451 3452 status = "disabled"; 3453 }; 3454 3455 usb_1: usb@a8f8800 { 3456 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 3457 reg = <0 0x0a8f8800 0 0x400>; 3458 #address-cells = <2>; 3459 #size-cells = <2>; 3460 ranges; 3461 3462 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3463 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3464 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3465 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3466 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3467 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3468 3469 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3470 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3471 assigned-clock-rates = <19200000>, <200000000>; 3472 3473 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 3474 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 3475 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3476 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 3477 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 3478 interrupt-names = "pwr_event", 3479 "hs_phy_irq", 3480 "dp_hs_phy_irq", 3481 "dm_hs_phy_irq", 3482 "ss_phy_irq"; 3483 3484 power-domains = <&gcc USB30_SEC_GDSC>; 3485 required-opps = <&rpmhpd_opp_nom>; 3486 3487 resets = <&gcc GCC_USB30_SEC_BCR>; 3488 3489 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3490 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3491 interconnect-names = "usb-ddr", "apps-usb"; 3492 3493 wakeup-source; 3494 3495 status = "disabled"; 3496 3497 usb_1_dwc3: usb@a800000 { 3498 compatible = "snps,dwc3"; 3499 reg = <0 0x0a800000 0 0xe000>; 3500 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 3501 iommus = <&apps_smmu 0x0a0 0x0>; 3502 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 3503 phy-names = "usb2-phy", "usb3-phy"; 3504 }; 3505 }; 3506 3507 usb_2_hsphy: phy@88e7000 { 3508 compatible = "qcom,sa8775p-usb-hs-phy", 3509 "qcom,usb-snps-hs-5nm-phy"; 3510 reg = <0 0x088e7000 0 0x120>; 3511 clocks = <&gcc GCC_USB_CLKREF_EN>; 3512 clock-names = "ref"; 3513 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 3514 3515 #phy-cells = <0>; 3516 3517 status = "disabled"; 3518 }; 3519 3520 usb_2: usb@a4f8800 { 3521 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 3522 reg = <0 0x0a4f8800 0 0x400>; 3523 #address-cells = <2>; 3524 #size-cells = <2>; 3525 ranges; 3526 3527 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 3528 <&gcc GCC_USB20_MASTER_CLK>, 3529 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 3530 <&gcc GCC_USB20_SLEEP_CLK>, 3531 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 3532 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3533 3534 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3535 <&gcc GCC_USB20_MASTER_CLK>; 3536 assigned-clock-rates = <19200000>, <200000000>; 3537 3538 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 3539 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 3540 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 3541 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 3542 interrupt-names = "pwr_event", 3543 "hs_phy_irq", 3544 "dp_hs_phy_irq", 3545 "dm_hs_phy_irq"; 3546 3547 power-domains = <&gcc USB20_PRIM_GDSC>; 3548 required-opps = <&rpmhpd_opp_nom>; 3549 3550 resets = <&gcc GCC_USB20_PRIM_BCR>; 3551 3552 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3553 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 3554 interconnect-names = "usb-ddr", "apps-usb"; 3555 3556 wakeup-source; 3557 3558 status = "disabled"; 3559 3560 usb_2_dwc3: usb@a400000 { 3561 compatible = "snps,dwc3"; 3562 reg = <0 0x0a400000 0 0xe000>; 3563 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 3564 iommus = <&apps_smmu 0x020 0x0>; 3565 phys = <&usb_2_hsphy>; 3566 phy-names = "usb2-phy"; 3567 }; 3568 }; 3569 3570 tcsr_mutex: hwlock@1f40000 { 3571 compatible = "qcom,tcsr-mutex"; 3572 reg = <0x0 0x01f40000 0x0 0x20000>; 3573 #hwlock-cells = <1>; 3574 }; 3575 3576 tcsr: syscon@1fc0000 { 3577 compatible = "qcom,sa8775p-tcsr", "syscon"; 3578 reg = <0x0 0x1fc0000 0x0 0x30000>; 3579 }; 3580 3581 gpucc: clock-controller@3d90000 { 3582 compatible = "qcom,sa8775p-gpucc"; 3583 reg = <0x0 0x03d90000 0x0 0xa000>; 3584 clocks = <&rpmhcc RPMH_CXO_CLK>, 3585 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3586 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3587 clock-names = "bi_tcxo", 3588 "gcc_gpu_gpll0_clk_src", 3589 "gcc_gpu_gpll0_div_clk_src"; 3590 #clock-cells = <1>; 3591 #reset-cells = <1>; 3592 #power-domain-cells = <1>; 3593 }; 3594 3595 adreno_smmu: iommu@3da0000 { 3596 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 3597 "qcom,smmu-500", "arm,mmu-500"; 3598 reg = <0x0 0x03da0000 0x0 0x20000>; 3599 #iommu-cells = <2>; 3600 #global-interrupts = <2>; 3601 dma-coherent; 3602 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3603 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3604 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3605 <&gpucc GPU_CC_AHB_CLK>, 3606 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3607 <&gpucc GPU_CC_CX_GMU_CLK>, 3608 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3609 <&gpucc GPU_CC_HUB_AON_CLK>; 3610 clock-names = "gcc_gpu_memnoc_gfx_clk", 3611 "gcc_gpu_snoc_dvm_gfx_clk", 3612 "gpu_cc_ahb_clk", 3613 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3614 "gpu_cc_cx_gmu_clk", 3615 "gpu_cc_hub_cx_int_clk", 3616 "gpu_cc_hub_aon_clk"; 3617 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 3629 }; 3630 3631 serdes0: phy@8901000 { 3632 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 3633 reg = <0x0 0x08901000 0x0 0xe10>; 3634 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 3635 clock-names = "sgmi_ref"; 3636 #phy-cells = <0>; 3637 status = "disabled"; 3638 }; 3639 3640 serdes1: phy@8902000 { 3641 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 3642 reg = <0x0 0x08902000 0x0 0xe10>; 3643 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 3644 clock-names = "sgmi_ref"; 3645 #phy-cells = <0>; 3646 status = "disabled"; 3647 }; 3648 3649 pmu@9091000 { 3650 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3651 reg = <0x0 0x9091000 0x0 0x1000>; 3652 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 3653 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3654 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3655 3656 operating-points-v2 = <&llcc_bwmon_opp_table>; 3657 3658 llcc_bwmon_opp_table: opp-table { 3659 compatible = "operating-points-v2"; 3660 3661 opp-0 { 3662 opp-peak-kBps = <762000>; 3663 }; 3664 3665 opp-1 { 3666 opp-peak-kBps = <1720000>; 3667 }; 3668 3669 opp-2 { 3670 opp-peak-kBps = <2086000>; 3671 }; 3672 3673 opp-3 { 3674 opp-peak-kBps = <2601000>; 3675 }; 3676 3677 opp-4 { 3678 opp-peak-kBps = <2929000>; 3679 }; 3680 3681 opp-5 { 3682 opp-peak-kBps = <5931000>; 3683 }; 3684 3685 opp-6 { 3686 opp-peak-kBps = <6515000>; 3687 }; 3688 3689 opp-7 { 3690 opp-peak-kBps = <7984000>; 3691 }; 3692 3693 opp-8 { 3694 opp-peak-kBps = <10437000>; 3695 }; 3696 3697 opp-9 { 3698 opp-peak-kBps = <12195000>; 3699 }; 3700 }; 3701 }; 3702 3703 pmu@90b5400 { 3704 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 3705 reg = <0x0 0x90b5400 0x0 0x600>; 3706 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3707 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3708 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3709 3710 operating-points-v2 = <&cpu_bwmon_opp_table>; 3711 3712 cpu_bwmon_opp_table: opp-table { 3713 compatible = "operating-points-v2"; 3714 3715 opp-0 { 3716 opp-peak-kBps = <9155000>; 3717 }; 3718 3719 opp-1 { 3720 opp-peak-kBps = <12298000>; 3721 }; 3722 3723 opp-2 { 3724 opp-peak-kBps = <14236000>; 3725 }; 3726 3727 opp-3 { 3728 opp-peak-kBps = <16265000>; 3729 }; 3730 }; 3731 3732 }; 3733 3734 pmu@90b6400 { 3735 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 3736 reg = <0x0 0x90b6400 0x0 0x600>; 3737 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3738 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3739 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3740 3741 operating-points-v2 = <&cpu_bwmon_opp_table>; 3742 }; 3743 3744 llcc: system-cache-controller@9200000 { 3745 compatible = "qcom,sa8775p-llcc"; 3746 reg = <0x0 0x09200000 0x0 0x80000>, 3747 <0x0 0x09300000 0x0 0x80000>, 3748 <0x0 0x09400000 0x0 0x80000>, 3749 <0x0 0x09500000 0x0 0x80000>, 3750 <0x0 0x09600000 0x0 0x80000>, 3751 <0x0 0x09700000 0x0 0x80000>, 3752 <0x0 0x09a00000 0x0 0x80000>; 3753 reg-names = "llcc0_base", 3754 "llcc1_base", 3755 "llcc2_base", 3756 "llcc3_base", 3757 "llcc4_base", 3758 "llcc5_base", 3759 "llcc_broadcast_base"; 3760 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 3761 }; 3762 3763 pdc: interrupt-controller@b220000 { 3764 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 3765 reg = <0x0 0x0b220000 0x0 0x30000>, 3766 <0x0 0x17c000f0 0x0 0x64>; 3767 qcom,pdc-ranges = <0 480 40>, 3768 <40 140 14>, 3769 <54 263 1>, 3770 <55 306 4>, 3771 <59 312 3>, 3772 <62 374 2>, 3773 <64 434 2>, 3774 <66 438 2>, 3775 <70 520 1>, 3776 <73 523 1>, 3777 <118 568 6>, 3778 <124 609 3>, 3779 <159 638 1>, 3780 <160 720 3>, 3781 <169 728 30>, 3782 <199 416 2>, 3783 <201 449 1>, 3784 <202 89 1>, 3785 <203 451 1>, 3786 <204 462 1>, 3787 <205 264 1>, 3788 <206 579 1>, 3789 <207 653 1>, 3790 <208 656 1>, 3791 <209 659 1>, 3792 <210 122 1>, 3793 <211 699 1>, 3794 <212 705 1>, 3795 <213 450 1>, 3796 <214 643 2>, 3797 <216 646 5>, 3798 <221 390 5>, 3799 <226 700 2>, 3800 <228 440 1>, 3801 <229 663 1>, 3802 <230 524 2>, 3803 <232 612 3>, 3804 <235 723 5>; 3805 #interrupt-cells = <2>; 3806 interrupt-parent = <&intc>; 3807 interrupt-controller; 3808 }; 3809 3810 tsens2: thermal-sensor@c251000 { 3811 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 3812 reg = <0x0 0x0c251000 0x0 0x1ff>, 3813 <0x0 0x0c224000 0x0 0x8>; 3814 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 3816 #qcom,sensors = <13>; 3817 interrupt-names = "uplow", "critical"; 3818 #thermal-sensor-cells = <1>; 3819 }; 3820 3821 tsens3: thermal-sensor@c252000 { 3822 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 3823 reg = <0x0 0x0c252000 0x0 0x1ff>, 3824 <0x0 0x0c225000 0x0 0x8>; 3825 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 3826 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 3827 #qcom,sensors = <13>; 3828 interrupt-names = "uplow", "critical"; 3829 #thermal-sensor-cells = <1>; 3830 }; 3831 3832 tsens0: thermal-sensor@c263000 { 3833 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 3834 reg = <0x0 0x0c263000 0x0 0x1ff>, 3835 <0x0 0x0c222000 0x0 0x8>; 3836 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3837 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3838 #qcom,sensors = <12>; 3839 interrupt-names = "uplow", "critical"; 3840 #thermal-sensor-cells = <1>; 3841 }; 3842 3843 tsens1: thermal-sensor@c265000 { 3844 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 3845 reg = <0x0 0x0c265000 0x0 0x1ff>, 3846 <0x0 0x0c223000 0x0 0x8>; 3847 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3849 #qcom,sensors = <12>; 3850 interrupt-names = "uplow", "critical"; 3851 #thermal-sensor-cells = <1>; 3852 }; 3853 3854 aoss_qmp: power-management@c300000 { 3855 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 3856 reg = <0x0 0x0c300000 0x0 0x400>; 3857 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3858 IPCC_MPROC_SIGNAL_GLINK_QMP 3859 IRQ_TYPE_EDGE_RISING>; 3860 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3861 #clock-cells = <0>; 3862 }; 3863 3864 sram@c3f0000 { 3865 compatible = "qcom,rpmh-stats"; 3866 reg = <0x0 0x0c3f0000 0x0 0x400>; 3867 }; 3868 3869 spmi_bus: spmi@c440000 { 3870 compatible = "qcom,spmi-pmic-arb"; 3871 reg = <0x0 0x0c440000 0x0 0x1100>, 3872 <0x0 0x0c600000 0x0 0x2000000>, 3873 <0x0 0x0e600000 0x0 0x100000>, 3874 <0x0 0x0e700000 0x0 0xa0000>, 3875 <0x0 0x0c40a000 0x0 0x26000>; 3876 reg-names = "core", 3877 "chnls", 3878 "obsrvr", 3879 "intr", 3880 "cnfg"; 3881 qcom,channel = <0>; 3882 qcom,ee = <0>; 3883 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3884 interrupt-names = "periph_irq"; 3885 interrupt-controller; 3886 #interrupt-cells = <4>; 3887 #address-cells = <2>; 3888 #size-cells = <0>; 3889 }; 3890 3891 tlmm: pinctrl@f000000 { 3892 compatible = "qcom,sa8775p-tlmm"; 3893 reg = <0x0 0x0f000000 0x0 0x1000000>; 3894 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3895 gpio-controller; 3896 #gpio-cells = <2>; 3897 interrupt-controller; 3898 #interrupt-cells = <2>; 3899 gpio-ranges = <&tlmm 0 0 149>; 3900 wakeup-parent = <&pdc>; 3901 }; 3902 3903 sram: sram@146d8000 { 3904 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; 3905 reg = <0x0 0x146d8000 0x0 0x1000>; 3906 ranges = <0x0 0x0 0x146d8000 0x1000>; 3907 3908 #address-cells = <1>; 3909 #size-cells = <1>; 3910 3911 pil-reloc@94c { 3912 compatible = "qcom,pil-reloc-info"; 3913 reg = <0x94c 0xc8>; 3914 }; 3915 }; 3916 3917 apps_smmu: iommu@15000000 { 3918 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3919 reg = <0x0 0x15000000 0x0 0x100000>; 3920 #iommu-cells = <2>; 3921 #global-interrupts = <2>; 3922 dma-coherent; 3923 3924 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 3925 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 3926 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3927 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3928 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3929 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3930 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3931 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3932 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3933 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3934 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3935 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3936 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3937 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3938 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3939 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3940 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3941 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3942 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3943 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3944 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3945 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3946 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3947 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3948 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3949 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3950 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3951 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3952 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3953 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3954 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3955 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3956 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3957 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3958 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3959 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3960 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3961 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3962 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3963 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3964 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3965 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3966 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3967 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3968 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3969 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3970 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3971 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3972 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3973 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3974 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3975 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3976 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3977 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3978 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3979 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3980 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3981 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3982 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3983 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3984 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3985 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3986 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3987 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3988 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3989 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3990 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3991 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3992 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3993 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3994 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3995 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3996 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3997 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3998 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3999 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4000 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4001 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4002 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4003 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4004 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4005 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4006 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4007 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4008 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4009 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4010 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4011 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4012 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4013 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4014 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4016 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4017 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 4018 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 4019 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 4021 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4022 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4023 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 4024 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 4025 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 4026 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 4027 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4028 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 4029 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 4030 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 4031 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 4032 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 4033 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 4034 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 4035 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 4036 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 4037 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 4038 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 4039 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 4040 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 4041 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 4042 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 4043 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 4044 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 4045 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 4047 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 4054 }; 4055 4056 pcie_smmu: iommu@15200000 { 4057 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4058 reg = <0x0 0x15200000 0x0 0x80000>; 4059 #iommu-cells = <2>; 4060 #global-interrupts = <2>; 4061 dma-coherent; 4062 4063 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 4129 }; 4130 4131 intc: interrupt-controller@17a00000 { 4132 compatible = "arm,gic-v3"; 4133 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4134 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4135 interrupt-controller; 4136 #interrupt-cells = <3>; 4137 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4138 #redistributor-regions = <1>; 4139 redistributor-stride = <0x0 0x20000>; 4140 }; 4141 4142 watchdog@17c10000 { 4143 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 4144 reg = <0x0 0x17c10000 0x0 0x1000>; 4145 clocks = <&sleep_clk>; 4146 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4147 }; 4148 4149 memtimer: timer@17c20000 { 4150 compatible = "arm,armv7-timer-mem"; 4151 reg = <0x0 0x17c20000 0x0 0x1000>; 4152 ranges = <0x0 0x0 0x0 0x20000000>; 4153 #address-cells = <1>; 4154 #size-cells = <1>; 4155 4156 frame@17c21000 { 4157 reg = <0x17c21000 0x1000>, 4158 <0x17c22000 0x1000>; 4159 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4160 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4161 frame-number = <0>; 4162 }; 4163 4164 frame@17c23000 { 4165 reg = <0x17c23000 0x1000>; 4166 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4167 frame-number = <1>; 4168 status = "disabled"; 4169 }; 4170 4171 frame@17c25000 { 4172 reg = <0x17c25000 0x1000>; 4173 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4174 frame-number = <2>; 4175 status = "disabled"; 4176 }; 4177 4178 frame@17c27000 { 4179 reg = <0x17c27000 0x1000>; 4180 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4181 frame-number = <3>; 4182 status = "disabled"; 4183 }; 4184 4185 frame@17c29000 { 4186 reg = <0x17c29000 0x1000>; 4187 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4188 frame-number = <4>; 4189 status = "disabled"; 4190 }; 4191 4192 frame@17c2b000 { 4193 reg = <0x17c2b000 0x1000>; 4194 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4195 frame-number = <5>; 4196 status = "disabled"; 4197 }; 4198 4199 frame@17c2d000 { 4200 reg = <0x17c2d000 0x1000>; 4201 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4202 frame-number = <6>; 4203 status = "disabled"; 4204 }; 4205 }; 4206 4207 apps_rsc: rsc@18200000 { 4208 compatible = "qcom,rpmh-rsc"; 4209 reg = <0x0 0x18200000 0x0 0x10000>, 4210 <0x0 0x18210000 0x0 0x10000>, 4211 <0x0 0x18220000 0x0 0x10000>; 4212 reg-names = "drv-0", "drv-1", "drv-2"; 4213 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4214 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4215 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4216 qcom,tcs-offset = <0xd00>; 4217 qcom,drv-id = <2>; 4218 qcom,tcs-config = <ACTIVE_TCS 2>, 4219 <SLEEP_TCS 3>, 4220 <WAKE_TCS 3>, 4221 <CONTROL_TCS 0>; 4222 label = "apps_rsc"; 4223 4224 apps_bcm_voter: bcm-voter { 4225 compatible = "qcom,bcm-voter"; 4226 }; 4227 4228 rpmhcc: clock-controller { 4229 compatible = "qcom,sa8775p-rpmh-clk"; 4230 #clock-cells = <1>; 4231 clock-names = "xo"; 4232 clocks = <&xo_board_clk>; 4233 }; 4234 4235 rpmhpd: power-controller { 4236 compatible = "qcom,sa8775p-rpmhpd"; 4237 #power-domain-cells = <1>; 4238 operating-points-v2 = <&rpmhpd_opp_table>; 4239 4240 rpmhpd_opp_table: opp-table { 4241 compatible = "operating-points-v2"; 4242 4243 rpmhpd_opp_ret: opp-0 { 4244 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4245 }; 4246 4247 rpmhpd_opp_min_svs: opp-1 { 4248 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4249 }; 4250 4251 rpmhpd_opp_low_svs: opp2 { 4252 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4253 }; 4254 4255 rpmhpd_opp_svs: opp3 { 4256 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4257 }; 4258 4259 rpmhpd_opp_svs_l1: opp-4 { 4260 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4261 }; 4262 4263 rpmhpd_opp_nom: opp-5 { 4264 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4265 }; 4266 4267 rpmhpd_opp_nom_l1: opp-6 { 4268 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4269 }; 4270 4271 rpmhpd_opp_nom_l2: opp-7 { 4272 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4273 }; 4274 4275 rpmhpd_opp_turbo: opp-8 { 4276 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4277 }; 4278 4279 rpmhpd_opp_turbo_l1: opp-9 { 4280 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4281 }; 4282 }; 4283 }; 4284 }; 4285 4286 cpufreq_hw: cpufreq@18591000 { 4287 compatible = "qcom,sa8775p-cpufreq-epss", 4288 "qcom,cpufreq-epss"; 4289 reg = <0x0 0x18591000 0x0 0x1000>, 4290 <0x0 0x18593000 0x0 0x1000>; 4291 reg-names = "freq-domain0", "freq-domain1"; 4292 4293 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4294 clock-names = "xo", "alternate"; 4295 4296 #freq-domain-cells = <1>; 4297 }; 4298 4299 remoteproc_gpdsp0: remoteproc@20c00000 { 4300 compatible = "qcom,sa8775p-gpdsp0-pas"; 4301 reg = <0x0 0x20c00000 0x0 0x10000>; 4302 4303 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 4304 <&smp2p_gpdsp0_in 0 0>, 4305 <&smp2p_gpdsp0_in 2 0>, 4306 <&smp2p_gpdsp0_in 1 0>, 4307 <&smp2p_gpdsp0_in 3 0>; 4308 interrupt-names = "wdog", "fatal", "ready", 4309 "handover", "stop-ack"; 4310 4311 clocks = <&rpmhcc RPMH_CXO_CLK>; 4312 clock-names = "xo"; 4313 4314 power-domains = <&rpmhpd RPMHPD_CX>, 4315 <&rpmhpd RPMHPD_MXC>; 4316 power-domain-names = "cx", "mxc"; 4317 4318 interconnects = <&gpdsp_anoc MASTER_DSP0 0 4319 &config_noc SLAVE_CLK_CTL 0>; 4320 4321 memory-region = <&pil_gdsp0_mem>; 4322 4323 qcom,qmp = <&aoss_qmp>; 4324 4325 qcom,smem-states = <&smp2p_gpdsp0_out 0>; 4326 qcom,smem-state-names = "stop"; 4327 4328 status = "disabled"; 4329 4330 glink-edge { 4331 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 4332 IPCC_MPROC_SIGNAL_GLINK_QMP 4333 IRQ_TYPE_EDGE_RISING>; 4334 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 4335 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4336 4337 label = "gpdsp0"; 4338 qcom,remote-pid = <17>; 4339 }; 4340 }; 4341 4342 remoteproc_gpdsp1: remoteproc@21c00000 { 4343 compatible = "qcom,sa8775p-gpdsp1-pas"; 4344 reg = <0x0 0x21c00000 0x0 0x10000>; 4345 4346 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 4347 <&smp2p_gpdsp1_in 0 0>, 4348 <&smp2p_gpdsp1_in 2 0>, 4349 <&smp2p_gpdsp1_in 1 0>, 4350 <&smp2p_gpdsp1_in 3 0>; 4351 interrupt-names = "wdog", "fatal", "ready", 4352 "handover", "stop-ack"; 4353 4354 clocks = <&rpmhcc RPMH_CXO_CLK>; 4355 clock-names = "xo"; 4356 4357 power-domains = <&rpmhpd RPMHPD_CX>, 4358 <&rpmhpd RPMHPD_MXC>; 4359 power-domain-names = "cx", "mxc"; 4360 4361 interconnects = <&gpdsp_anoc MASTER_DSP1 0 4362 &config_noc SLAVE_CLK_CTL 0>; 4363 4364 memory-region = <&pil_gdsp1_mem>; 4365 4366 qcom,qmp = <&aoss_qmp>; 4367 4368 qcom,smem-states = <&smp2p_gpdsp1_out 0>; 4369 qcom,smem-state-names = "stop"; 4370 4371 status = "disabled"; 4372 4373 glink-edge { 4374 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 4375 IPCC_MPROC_SIGNAL_GLINK_QMP 4376 IRQ_TYPE_EDGE_RISING>; 4377 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 4378 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4379 4380 label = "gpdsp1"; 4381 qcom,remote-pid = <18>; 4382 }; 4383 }; 4384 4385 ethernet1: ethernet@23000000 { 4386 compatible = "qcom,sa8775p-ethqos"; 4387 reg = <0x0 0x23000000 0x0 0x10000>, 4388 <0x0 0x23016000 0x0 0x100>; 4389 reg-names = "stmmaceth", "rgmii"; 4390 4391 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 4392 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 4393 interrupt-names = "macirq", "sfty"; 4394 4395 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 4396 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 4397 <&gcc GCC_EMAC1_PTP_CLK>, 4398 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 4399 clock-names = "stmmaceth", 4400 "pclk", 4401 "ptp_ref", 4402 "phyaux"; 4403 4404 interconnects = <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS 4405 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4406 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4407 &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>; 4408 interconnect-names = "mac-mem", "cpu-mac"; 4409 4410 power-domains = <&gcc EMAC1_GDSC>; 4411 4412 phys = <&serdes1>; 4413 phy-names = "serdes"; 4414 4415 iommus = <&apps_smmu 0x140 0xf>; 4416 dma-coherent; 4417 4418 snps,tso; 4419 snps,pbl = <32>; 4420 rx-fifo-depth = <16384>; 4421 tx-fifo-depth = <16384>; 4422 4423 status = "disabled"; 4424 }; 4425 4426 ethernet0: ethernet@23040000 { 4427 compatible = "qcom,sa8775p-ethqos"; 4428 reg = <0x0 0x23040000 0x0 0x10000>, 4429 <0x0 0x23056000 0x0 0x100>; 4430 reg-names = "stmmaceth", "rgmii"; 4431 4432 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 4433 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; 4434 interrupt-names = "macirq", "sfty"; 4435 4436 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 4437 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 4438 <&gcc GCC_EMAC0_PTP_CLK>, 4439 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 4440 clock-names = "stmmaceth", 4441 "pclk", 4442 "ptp_ref", 4443 "phyaux"; 4444 4445 interconnects = <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS 4446 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4447 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4448 &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>; 4449 interconnect-names = "mac-mem", "cpu-mac"; 4450 4451 power-domains = <&gcc EMAC0_GDSC>; 4452 4453 phys = <&serdes0>; 4454 phy-names = "serdes"; 4455 4456 iommus = <&apps_smmu 0x120 0xf>; 4457 dma-coherent; 4458 4459 snps,tso; 4460 snps,pbl = <32>; 4461 rx-fifo-depth = <16384>; 4462 tx-fifo-depth = <16384>; 4463 4464 status = "disabled"; 4465 }; 4466 4467 remoteproc_cdsp0: remoteproc@26300000 { 4468 compatible = "qcom,sa8775p-cdsp0-pas"; 4469 reg = <0x0 0x26300000 0x0 0x10000>; 4470 4471 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4472 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>, 4473 <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>, 4474 <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>, 4475 <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>; 4476 interrupt-names = "wdog", "fatal", "ready", 4477 "handover", "stop-ack"; 4478 4479 clocks = <&rpmhcc RPMH_CXO_CLK>; 4480 clock-names = "xo"; 4481 4482 power-domains = <&rpmhpd RPMHPD_CX>, 4483 <&rpmhpd RPMHPD_MXC>, 4484 <&rpmhpd RPMHPD_NSP0>; 4485 power-domain-names = "cx", "mxc", "nsp"; 4486 4487 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 4488 &mc_virt SLAVE_EBI1 0>; 4489 4490 memory-region = <&pil_cdsp0_mem>; 4491 4492 qcom,qmp = <&aoss_qmp>; 4493 4494 qcom,smem-states = <&smp2p_cdsp0_out 0>; 4495 qcom,smem-state-names = "stop"; 4496 4497 status = "disabled"; 4498 4499 glink-edge { 4500 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4501 IPCC_MPROC_SIGNAL_GLINK_QMP 4502 IRQ_TYPE_EDGE_RISING>; 4503 mboxes = <&ipcc IPCC_CLIENT_CDSP 4504 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4505 4506 label = "cdsp"; 4507 qcom,remote-pid = <5>; 4508 4509 fastrpc { 4510 compatible = "qcom,fastrpc"; 4511 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4512 label = "cdsp"; 4513 #address-cells = <1>; 4514 #size-cells = <0>; 4515 4516 compute-cb@1 { 4517 compatible = "qcom,fastrpc-compute-cb"; 4518 reg = <1>; 4519 iommus = <&apps_smmu 0x2141 0x04a0>, 4520 <&apps_smmu 0x2161 0x04a0>, 4521 <&apps_smmu 0x2181 0x0400>, 4522 <&apps_smmu 0x21c1 0x04a0>, 4523 <&apps_smmu 0x21e1 0x04a0>, 4524 <&apps_smmu 0x2541 0x04a0>, 4525 <&apps_smmu 0x2561 0x04a0>, 4526 <&apps_smmu 0x2581 0x0400>, 4527 <&apps_smmu 0x25c1 0x04a0>, 4528 <&apps_smmu 0x25e1 0x04a0>; 4529 dma-coherent; 4530 }; 4531 4532 compute-cb@2 { 4533 compatible = "qcom,fastrpc-compute-cb"; 4534 reg = <2>; 4535 iommus = <&apps_smmu 0x2142 0x04a0>, 4536 <&apps_smmu 0x2162 0x04a0>, 4537 <&apps_smmu 0x2182 0x0400>, 4538 <&apps_smmu 0x21c2 0x04a0>, 4539 <&apps_smmu 0x21e2 0x04a0>, 4540 <&apps_smmu 0x2542 0x04a0>, 4541 <&apps_smmu 0x2562 0x04a0>, 4542 <&apps_smmu 0x2582 0x0400>, 4543 <&apps_smmu 0x25c2 0x04a0>, 4544 <&apps_smmu 0x25e2 0x04a0>; 4545 dma-coherent; 4546 }; 4547 4548 compute-cb@3 { 4549 compatible = "qcom,fastrpc-compute-cb"; 4550 reg = <3>; 4551 iommus = <&apps_smmu 0x2143 0x04a0>, 4552 <&apps_smmu 0x2163 0x04a0>, 4553 <&apps_smmu 0x2183 0x0400>, 4554 <&apps_smmu 0x21c3 0x04a0>, 4555 <&apps_smmu 0x21e3 0x04a0>, 4556 <&apps_smmu 0x2543 0x04a0>, 4557 <&apps_smmu 0x2563 0x04a0>, 4558 <&apps_smmu 0x2583 0x0400>, 4559 <&apps_smmu 0x25c3 0x04a0>, 4560 <&apps_smmu 0x25e3 0x04a0>; 4561 dma-coherent; 4562 }; 4563 4564 compute-cb@4 { 4565 compatible = "qcom,fastrpc-compute-cb"; 4566 reg = <4>; 4567 iommus = <&apps_smmu 0x2144 0x04a0>, 4568 <&apps_smmu 0x2164 0x04a0>, 4569 <&apps_smmu 0x2184 0x0400>, 4570 <&apps_smmu 0x21c4 0x04a0>, 4571 <&apps_smmu 0x21e4 0x04a0>, 4572 <&apps_smmu 0x2544 0x04a0>, 4573 <&apps_smmu 0x2564 0x04a0>, 4574 <&apps_smmu 0x2584 0x0400>, 4575 <&apps_smmu 0x25c4 0x04a0>, 4576 <&apps_smmu 0x25e4 0x04a0>; 4577 dma-coherent; 4578 }; 4579 4580 compute-cb@5 { 4581 compatible = "qcom,fastrpc-compute-cb"; 4582 reg = <5>; 4583 iommus = <&apps_smmu 0x2145 0x04a0>, 4584 <&apps_smmu 0x2165 0x04a0>, 4585 <&apps_smmu 0x2185 0x0400>, 4586 <&apps_smmu 0x21c5 0x04a0>, 4587 <&apps_smmu 0x21e5 0x04a0>, 4588 <&apps_smmu 0x2545 0x04a0>, 4589 <&apps_smmu 0x2565 0x04a0>, 4590 <&apps_smmu 0x2585 0x0400>, 4591 <&apps_smmu 0x25c5 0x04a0>, 4592 <&apps_smmu 0x25e5 0x04a0>; 4593 dma-coherent; 4594 }; 4595 4596 compute-cb@6 { 4597 compatible = "qcom,fastrpc-compute-cb"; 4598 reg = <6>; 4599 iommus = <&apps_smmu 0x2146 0x04a0>, 4600 <&apps_smmu 0x2166 0x04a0>, 4601 <&apps_smmu 0x2186 0x0400>, 4602 <&apps_smmu 0x21c6 0x04a0>, 4603 <&apps_smmu 0x21e6 0x04a0>, 4604 <&apps_smmu 0x2546 0x04a0>, 4605 <&apps_smmu 0x2566 0x04a0>, 4606 <&apps_smmu 0x2586 0x0400>, 4607 <&apps_smmu 0x25c6 0x04a0>, 4608 <&apps_smmu 0x25e6 0x04a0>; 4609 dma-coherent; 4610 }; 4611 4612 compute-cb@7 { 4613 compatible = "qcom,fastrpc-compute-cb"; 4614 reg = <7>; 4615 iommus = <&apps_smmu 0x2147 0x04a0>, 4616 <&apps_smmu 0x2167 0x04a0>, 4617 <&apps_smmu 0x2187 0x0400>, 4618 <&apps_smmu 0x21c7 0x04a0>, 4619 <&apps_smmu 0x21e7 0x04a0>, 4620 <&apps_smmu 0x2547 0x04a0>, 4621 <&apps_smmu 0x2567 0x04a0>, 4622 <&apps_smmu 0x2587 0x0400>, 4623 <&apps_smmu 0x25c7 0x04a0>, 4624 <&apps_smmu 0x25e7 0x04a0>; 4625 dma-coherent; 4626 }; 4627 4628 compute-cb@8 { 4629 compatible = "qcom,fastrpc-compute-cb"; 4630 reg = <8>; 4631 iommus = <&apps_smmu 0x2148 0x04a0>, 4632 <&apps_smmu 0x2168 0x04a0>, 4633 <&apps_smmu 0x2188 0x0400>, 4634 <&apps_smmu 0x21c8 0x04a0>, 4635 <&apps_smmu 0x21e8 0x04a0>, 4636 <&apps_smmu 0x2548 0x04a0>, 4637 <&apps_smmu 0x2568 0x04a0>, 4638 <&apps_smmu 0x2588 0x0400>, 4639 <&apps_smmu 0x25c8 0x04a0>, 4640 <&apps_smmu 0x25e8 0x04a0>; 4641 dma-coherent; 4642 }; 4643 4644 compute-cb@9 { 4645 compatible = "qcom,fastrpc-compute-cb"; 4646 reg = <9>; 4647 iommus = <&apps_smmu 0x2149 0x04a0>, 4648 <&apps_smmu 0x2169 0x04a0>, 4649 <&apps_smmu 0x2189 0x0400>, 4650 <&apps_smmu 0x21c9 0x04a0>, 4651 <&apps_smmu 0x21e9 0x04a0>, 4652 <&apps_smmu 0x2549 0x04a0>, 4653 <&apps_smmu 0x2569 0x04a0>, 4654 <&apps_smmu 0x2589 0x0400>, 4655 <&apps_smmu 0x25c9 0x04a0>, 4656 <&apps_smmu 0x25e9 0x04a0>; 4657 dma-coherent; 4658 }; 4659 4660 compute-cb@10 { 4661 compatible = "qcom,fastrpc-compute-cb"; 4662 reg = <10>; 4663 iommus = <&apps_smmu 0x214a 0x04a0>, 4664 <&apps_smmu 0x216a 0x04a0>, 4665 <&apps_smmu 0x218a 0x0400>, 4666 <&apps_smmu 0x21ca 0x04a0>, 4667 <&apps_smmu 0x21ea 0x04a0>, 4668 <&apps_smmu 0x254a 0x04a0>, 4669 <&apps_smmu 0x256a 0x04a0>, 4670 <&apps_smmu 0x258a 0x0400>, 4671 <&apps_smmu 0x25ca 0x04a0>, 4672 <&apps_smmu 0x25ea 0x04a0>; 4673 dma-coherent; 4674 }; 4675 4676 compute-cb@11 { 4677 compatible = "qcom,fastrpc-compute-cb"; 4678 reg = <11>; 4679 iommus = <&apps_smmu 0x214b 0x04a0>, 4680 <&apps_smmu 0x216b 0x04a0>, 4681 <&apps_smmu 0x218b 0x0400>, 4682 <&apps_smmu 0x21cb 0x04a0>, 4683 <&apps_smmu 0x21eb 0x04a0>, 4684 <&apps_smmu 0x254b 0x04a0>, 4685 <&apps_smmu 0x256b 0x04a0>, 4686 <&apps_smmu 0x258b 0x0400>, 4687 <&apps_smmu 0x25cb 0x04a0>, 4688 <&apps_smmu 0x25eb 0x04a0>; 4689 dma-coherent; 4690 }; 4691 }; 4692 }; 4693 }; 4694 4695 remoteproc_cdsp1: remoteproc@2a300000 { 4696 compatible = "qcom,sa8775p-cdsp1-pas"; 4697 reg = <0x0 0x2A300000 0x0 0x10000>; 4698 4699 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 4700 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, 4701 <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>, 4702 <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>, 4703 <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>; 4704 interrupt-names = "wdog", "fatal", "ready", 4705 "handover", "stop-ack"; 4706 4707 clocks = <&rpmhcc RPMH_CXO_CLK>; 4708 clock-names = "xo"; 4709 4710 power-domains = <&rpmhpd RPMHPD_CX>, 4711 <&rpmhpd RPMHPD_MXC>, 4712 <&rpmhpd RPMHPD_NSP1>; 4713 power-domain-names = "cx", "mxc", "nsp"; 4714 4715 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 4716 &mc_virt SLAVE_EBI1 0>; 4717 4718 memory-region = <&pil_cdsp1_mem>; 4719 4720 qcom,qmp = <&aoss_qmp>; 4721 4722 qcom,smem-states = <&smp2p_cdsp1_out 0>; 4723 qcom,smem-state-names = "stop"; 4724 4725 status = "disabled"; 4726 4727 glink-edge { 4728 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 4729 IPCC_MPROC_SIGNAL_GLINK_QMP 4730 IRQ_TYPE_EDGE_RISING>; 4731 mboxes = <&ipcc IPCC_CLIENT_NSP1 4732 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4733 4734 label = "cdsp"; 4735 qcom,remote-pid = <12>; 4736 4737 fastrpc { 4738 compatible = "qcom,fastrpc"; 4739 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4740 label = "cdsp1"; 4741 #address-cells = <1>; 4742 #size-cells = <0>; 4743 4744 compute-cb@1 { 4745 compatible = "qcom,fastrpc-compute-cb"; 4746 reg = <1>; 4747 iommus = <&apps_smmu 0x2941 0x04a0>, 4748 <&apps_smmu 0x2961 0x04a0>, 4749 <&apps_smmu 0x2981 0x0400>, 4750 <&apps_smmu 0x29c1 0x04a0>, 4751 <&apps_smmu 0x29e1 0x04a0>, 4752 <&apps_smmu 0x2d41 0x04a0>, 4753 <&apps_smmu 0x2d61 0x04a0>, 4754 <&apps_smmu 0x2d81 0x0400>, 4755 <&apps_smmu 0x2dc1 0x04a0>, 4756 <&apps_smmu 0x2de1 0x04a0>; 4757 dma-coherent; 4758 }; 4759 4760 compute-cb@2 { 4761 compatible = "qcom,fastrpc-compute-cb"; 4762 reg = <2>; 4763 iommus = <&apps_smmu 0x2942 0x04a0>, 4764 <&apps_smmu 0x2962 0x04a0>, 4765 <&apps_smmu 0x2982 0x0400>, 4766 <&apps_smmu 0x29c2 0x04a0>, 4767 <&apps_smmu 0x29e2 0x04a0>, 4768 <&apps_smmu 0x2d42 0x04a0>, 4769 <&apps_smmu 0x2d62 0x04a0>, 4770 <&apps_smmu 0x2d82 0x0400>, 4771 <&apps_smmu 0x2dc2 0x04a0>, 4772 <&apps_smmu 0x2de2 0x04a0>; 4773 dma-coherent; 4774 }; 4775 4776 compute-cb@3 { 4777 compatible = "qcom,fastrpc-compute-cb"; 4778 reg = <3>; 4779 iommus = <&apps_smmu 0x2943 0x04a0>, 4780 <&apps_smmu 0x2963 0x04a0>, 4781 <&apps_smmu 0x2983 0x0400>, 4782 <&apps_smmu 0x29c3 0x04a0>, 4783 <&apps_smmu 0x29e3 0x04a0>, 4784 <&apps_smmu 0x2d43 0x04a0>, 4785 <&apps_smmu 0x2d63 0x04a0>, 4786 <&apps_smmu 0x2d83 0x0400>, 4787 <&apps_smmu 0x2dc3 0x04a0>, 4788 <&apps_smmu 0x2de3 0x04a0>; 4789 dma-coherent; 4790 }; 4791 4792 compute-cb@4 { 4793 compatible = "qcom,fastrpc-compute-cb"; 4794 reg = <4>; 4795 iommus = <&apps_smmu 0x2944 0x04a0>, 4796 <&apps_smmu 0x2964 0x04a0>, 4797 <&apps_smmu 0x2984 0x0400>, 4798 <&apps_smmu 0x29c4 0x04a0>, 4799 <&apps_smmu 0x29e4 0x04a0>, 4800 <&apps_smmu 0x2d44 0x04a0>, 4801 <&apps_smmu 0x2d64 0x04a0>, 4802 <&apps_smmu 0x2d84 0x0400>, 4803 <&apps_smmu 0x2dc4 0x04a0>, 4804 <&apps_smmu 0x2de4 0x04a0>; 4805 dma-coherent; 4806 }; 4807 4808 compute-cb@5 { 4809 compatible = "qcom,fastrpc-compute-cb"; 4810 reg = <5>; 4811 iommus = <&apps_smmu 0x2945 0x04a0>, 4812 <&apps_smmu 0x2965 0x04a0>, 4813 <&apps_smmu 0x2985 0x0400>, 4814 <&apps_smmu 0x29c5 0x04a0>, 4815 <&apps_smmu 0x29e5 0x04a0>, 4816 <&apps_smmu 0x2d45 0x04a0>, 4817 <&apps_smmu 0x2d65 0x04a0>, 4818 <&apps_smmu 0x2d85 0x0400>, 4819 <&apps_smmu 0x2dc5 0x04a0>, 4820 <&apps_smmu 0x2de5 0x04a0>; 4821 dma-coherent; 4822 }; 4823 4824 compute-cb@6 { 4825 compatible = "qcom,fastrpc-compute-cb"; 4826 reg = <6>; 4827 iommus = <&apps_smmu 0x2946 0x04a0>, 4828 <&apps_smmu 0x2966 0x04a0>, 4829 <&apps_smmu 0x2986 0x0400>, 4830 <&apps_smmu 0x29c6 0x04a0>, 4831 <&apps_smmu 0x29e6 0x04a0>, 4832 <&apps_smmu 0x2d46 0x04a0>, 4833 <&apps_smmu 0x2d66 0x04a0>, 4834 <&apps_smmu 0x2d86 0x0400>, 4835 <&apps_smmu 0x2dc6 0x04a0>, 4836 <&apps_smmu 0x2de6 0x04a0>; 4837 dma-coherent; 4838 }; 4839 4840 compute-cb@7 { 4841 compatible = "qcom,fastrpc-compute-cb"; 4842 reg = <7>; 4843 iommus = <&apps_smmu 0x2947 0x04a0>, 4844 <&apps_smmu 0x2967 0x04a0>, 4845 <&apps_smmu 0x2987 0x0400>, 4846 <&apps_smmu 0x29c7 0x04a0>, 4847 <&apps_smmu 0x29e7 0x04a0>, 4848 <&apps_smmu 0x2d47 0x04a0>, 4849 <&apps_smmu 0x2d67 0x04a0>, 4850 <&apps_smmu 0x2d87 0x0400>, 4851 <&apps_smmu 0x2dc7 0x04a0>, 4852 <&apps_smmu 0x2de7 0x04a0>; 4853 dma-coherent; 4854 }; 4855 4856 compute-cb@8 { 4857 compatible = "qcom,fastrpc-compute-cb"; 4858 reg = <8>; 4859 iommus = <&apps_smmu 0x2948 0x04a0>, 4860 <&apps_smmu 0x2968 0x04a0>, 4861 <&apps_smmu 0x2988 0x0400>, 4862 <&apps_smmu 0x29c8 0x04a0>, 4863 <&apps_smmu 0x29e8 0x04a0>, 4864 <&apps_smmu 0x2d48 0x04a0>, 4865 <&apps_smmu 0x2d68 0x04a0>, 4866 <&apps_smmu 0x2d88 0x0400>, 4867 <&apps_smmu 0x2dc8 0x04a0>, 4868 <&apps_smmu 0x2de8 0x04a0>; 4869 dma-coherent; 4870 }; 4871 4872 compute-cb@9 { 4873 compatible = "qcom,fastrpc-compute-cb"; 4874 reg = <9>; 4875 iommus = <&apps_smmu 0x2949 0x04a0>, 4876 <&apps_smmu 0x2969 0x04a0>, 4877 <&apps_smmu 0x2989 0x0400>, 4878 <&apps_smmu 0x29c9 0x04a0>, 4879 <&apps_smmu 0x29e9 0x04a0>, 4880 <&apps_smmu 0x2d49 0x04a0>, 4881 <&apps_smmu 0x2d69 0x04a0>, 4882 <&apps_smmu 0x2d89 0x0400>, 4883 <&apps_smmu 0x2dc9 0x04a0>, 4884 <&apps_smmu 0x2de9 0x04a0>; 4885 dma-coherent; 4886 }; 4887 4888 compute-cb@10 { 4889 compatible = "qcom,fastrpc-compute-cb"; 4890 reg = <10>; 4891 iommus = <&apps_smmu 0x294a 0x04a0>, 4892 <&apps_smmu 0x296a 0x04a0>, 4893 <&apps_smmu 0x298a 0x0400>, 4894 <&apps_smmu 0x29ca 0x04a0>, 4895 <&apps_smmu 0x29ea 0x04a0>, 4896 <&apps_smmu 0x2d4a 0x04a0>, 4897 <&apps_smmu 0x2d6a 0x04a0>, 4898 <&apps_smmu 0x2d8a 0x0400>, 4899 <&apps_smmu 0x2dca 0x04a0>, 4900 <&apps_smmu 0x2dea 0x04a0>; 4901 dma-coherent; 4902 }; 4903 4904 compute-cb@11 { 4905 compatible = "qcom,fastrpc-compute-cb"; 4906 reg = <11>; 4907 iommus = <&apps_smmu 0x294b 0x04a0>, 4908 <&apps_smmu 0x296b 0x04a0>, 4909 <&apps_smmu 0x298b 0x0400>, 4910 <&apps_smmu 0x29cb 0x04a0>, 4911 <&apps_smmu 0x29eb 0x04a0>, 4912 <&apps_smmu 0x2d4b 0x04a0>, 4913 <&apps_smmu 0x2d6b 0x04a0>, 4914 <&apps_smmu 0x2d8b 0x0400>, 4915 <&apps_smmu 0x2dcb 0x04a0>, 4916 <&apps_smmu 0x2deb 0x04a0>; 4917 dma-coherent; 4918 }; 4919 4920 compute-cb@12 { 4921 compatible = "qcom,fastrpc-compute-cb"; 4922 reg = <12>; 4923 iommus = <&apps_smmu 0x294c 0x04a0>, 4924 <&apps_smmu 0x296c 0x04a0>, 4925 <&apps_smmu 0x298c 0x0400>, 4926 <&apps_smmu 0x29cc 0x04a0>, 4927 <&apps_smmu 0x29ec 0x04a0>, 4928 <&apps_smmu 0x2d4c 0x04a0>, 4929 <&apps_smmu 0x2d6c 0x04a0>, 4930 <&apps_smmu 0x2d8c 0x0400>, 4931 <&apps_smmu 0x2dcc 0x04a0>, 4932 <&apps_smmu 0x2dec 0x04a0>; 4933 dma-coherent; 4934 }; 4935 4936 compute-cb@13 { 4937 compatible = "qcom,fastrpc-compute-cb"; 4938 reg = <13>; 4939 iommus = <&apps_smmu 0x294d 0x04a0>, 4940 <&apps_smmu 0x296d 0x04a0>, 4941 <&apps_smmu 0x298d 0x0400>, 4942 <&apps_smmu 0x29Cd 0x04a0>, 4943 <&apps_smmu 0x29ed 0x04a0>, 4944 <&apps_smmu 0x2d4d 0x04a0>, 4945 <&apps_smmu 0x2d6d 0x04a0>, 4946 <&apps_smmu 0x2d8d 0x0400>, 4947 <&apps_smmu 0x2dcd 0x04a0>, 4948 <&apps_smmu 0x2ded 0x04a0>; 4949 dma-coherent; 4950 }; 4951 }; 4952 }; 4953 }; 4954 4955 remoteproc_adsp: remoteproc@30000000 { 4956 compatible = "qcom,sa8775p-adsp-pas"; 4957 reg = <0x0 0x30000000 0x0 0x100>; 4958 4959 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4960 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4961 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4962 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4963 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 4964 interrupt-names = "wdog", "fatal", "ready", "handover", 4965 "stop-ack"; 4966 4967 clocks = <&rpmhcc RPMH_CXO_CLK>; 4968 clock-names = "xo"; 4969 4970 power-domains = <&rpmhpd RPMHPD_LCX>, 4971 <&rpmhpd RPMHPD_LMX>; 4972 power-domain-names = "lcx", "lmx"; 4973 4974 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 4975 4976 memory-region = <&pil_adsp_mem>; 4977 4978 qcom,qmp = <&aoss_qmp>; 4979 4980 qcom,smem-states = <&smp2p_adsp_out 0>; 4981 qcom,smem-state-names = "stop"; 4982 4983 status = "disabled"; 4984 4985 remoteproc_adsp_glink: glink-edge { 4986 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4987 IPCC_MPROC_SIGNAL_GLINK_QMP 4988 IRQ_TYPE_EDGE_RISING>; 4989 mboxes = <&ipcc IPCC_CLIENT_LPASS 4990 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4991 4992 label = "lpass"; 4993 qcom,remote-pid = <2>; 4994 4995 fastrpc { 4996 compatible = "qcom,fastrpc"; 4997 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4998 label = "adsp"; 4999 memory-region = <&adsp_rpc_remote_heap_mem>; 5000 qcom,vmids = <QCOM_SCM_VMID_LPASS 5001 QCOM_SCM_VMID_ADSP_HEAP>; 5002 #address-cells = <1>; 5003 #size-cells = <0>; 5004 5005 compute-cb@3 { 5006 compatible = "qcom,fastrpc-compute-cb"; 5007 reg = <3>; 5008 iommus = <&apps_smmu 0x3003 0x0>; 5009 dma-coherent; 5010 }; 5011 5012 compute-cb@4 { 5013 compatible = "qcom,fastrpc-compute-cb"; 5014 reg = <4>; 5015 iommus = <&apps_smmu 0x3004 0x0>; 5016 dma-coherent; 5017 }; 5018 5019 compute-cb@5 { 5020 compatible = "qcom,fastrpc-compute-cb"; 5021 reg = <5>; 5022 iommus = <&apps_smmu 0x3005 0x0>; 5023 qcom,nsessions = <5>; 5024 dma-coherent; 5025 }; 5026 }; 5027 }; 5028 }; 5029 }; 5030 5031 thermal-zones { 5032 aoss-0-thermal { 5033 thermal-sensors = <&tsens0 0>; 5034 5035 trips { 5036 trip-point0 { 5037 temperature = <105000>; 5038 hysteresis = <5000>; 5039 type = "passive"; 5040 }; 5041 5042 trip-point1 { 5043 temperature = <115000>; 5044 hysteresis = <5000>; 5045 type = "passive"; 5046 }; 5047 }; 5048 }; 5049 5050 cpu-0-0-0-thermal { 5051 polling-delay-passive = <10>; 5052 5053 thermal-sensors = <&tsens0 1>; 5054 5055 trips { 5056 trip-point0 { 5057 temperature = <105000>; 5058 hysteresis = <5000>; 5059 type = "passive"; 5060 }; 5061 5062 trip-point1 { 5063 temperature = <115000>; 5064 hysteresis = <5000>; 5065 type = "passive"; 5066 }; 5067 }; 5068 }; 5069 5070 cpu-0-1-0-thermal { 5071 polling-delay-passive = <10>; 5072 5073 thermal-sensors = <&tsens0 2>; 5074 5075 trips { 5076 trip-point0 { 5077 temperature = <105000>; 5078 hysteresis = <5000>; 5079 type = "passive"; 5080 }; 5081 5082 trip-point1 { 5083 temperature = <115000>; 5084 hysteresis = <5000>; 5085 type = "passive"; 5086 }; 5087 }; 5088 }; 5089 5090 cpu-0-2-0-thermal { 5091 polling-delay-passive = <10>; 5092 5093 thermal-sensors = <&tsens0 3>; 5094 5095 trips { 5096 trip-point0 { 5097 temperature = <105000>; 5098 hysteresis = <5000>; 5099 type = "passive"; 5100 }; 5101 5102 trip-point1 { 5103 temperature = <115000>; 5104 hysteresis = <5000>; 5105 type = "passive"; 5106 }; 5107 }; 5108 }; 5109 5110 cpu-0-3-0-thermal { 5111 polling-delay-passive = <10>; 5112 5113 thermal-sensors = <&tsens0 4>; 5114 5115 trips { 5116 trip-point0 { 5117 temperature = <105000>; 5118 hysteresis = <5000>; 5119 type = "passive"; 5120 }; 5121 5122 trip-point1 { 5123 temperature = <115000>; 5124 hysteresis = <5000>; 5125 type = "passive"; 5126 }; 5127 }; 5128 }; 5129 5130 gpuss-0-thermal { 5131 polling-delay-passive = <10>; 5132 5133 thermal-sensors = <&tsens0 5>; 5134 5135 trips { 5136 trip-point0 { 5137 temperature = <105000>; 5138 hysteresis = <5000>; 5139 type = "passive"; 5140 }; 5141 5142 trip-point1 { 5143 temperature = <115000>; 5144 hysteresis = <5000>; 5145 type = "passive"; 5146 }; 5147 }; 5148 }; 5149 5150 gpuss-1-thermal { 5151 polling-delay-passive = <10>; 5152 5153 thermal-sensors = <&tsens0 6>; 5154 5155 trips { 5156 trip-point0 { 5157 temperature = <105000>; 5158 hysteresis = <5000>; 5159 type = "passive"; 5160 }; 5161 5162 trip-point1 { 5163 temperature = <115000>; 5164 hysteresis = <5000>; 5165 type = "passive"; 5166 }; 5167 }; 5168 }; 5169 5170 gpuss-2-thermal { 5171 polling-delay-passive = <10>; 5172 5173 thermal-sensors = <&tsens0 7>; 5174 5175 trips { 5176 trip-point0 { 5177 temperature = <105000>; 5178 hysteresis = <5000>; 5179 type = "passive"; 5180 }; 5181 5182 trip-point1 { 5183 temperature = <115000>; 5184 hysteresis = <5000>; 5185 type = "passive"; 5186 }; 5187 }; 5188 }; 5189 5190 audio-thermal { 5191 thermal-sensors = <&tsens0 8>; 5192 5193 trips { 5194 trip-point0 { 5195 temperature = <105000>; 5196 hysteresis = <5000>; 5197 type = "passive"; 5198 }; 5199 5200 trip-point1 { 5201 temperature = <115000>; 5202 hysteresis = <5000>; 5203 type = "passive"; 5204 }; 5205 }; 5206 }; 5207 5208 camss-0-thermal { 5209 thermal-sensors = <&tsens0 9>; 5210 5211 trips { 5212 trip-point0 { 5213 temperature = <105000>; 5214 hysteresis = <5000>; 5215 type = "passive"; 5216 }; 5217 5218 trip-point1 { 5219 temperature = <115000>; 5220 hysteresis = <5000>; 5221 type = "passive"; 5222 }; 5223 }; 5224 }; 5225 5226 pcie-0-thermal { 5227 thermal-sensors = <&tsens0 10>; 5228 5229 trips { 5230 trip-point0 { 5231 temperature = <105000>; 5232 hysteresis = <5000>; 5233 type = "passive"; 5234 }; 5235 5236 trip-point1 { 5237 temperature = <115000>; 5238 hysteresis = <5000>; 5239 type = "passive"; 5240 }; 5241 }; 5242 }; 5243 5244 cpuss-0-0-thermal { 5245 thermal-sensors = <&tsens0 11>; 5246 5247 trips { 5248 trip-point0 { 5249 temperature = <105000>; 5250 hysteresis = <5000>; 5251 type = "passive"; 5252 }; 5253 5254 trip-point1 { 5255 temperature = <115000>; 5256 hysteresis = <5000>; 5257 type = "passive"; 5258 }; 5259 }; 5260 }; 5261 5262 aoss-1-thermal { 5263 thermal-sensors = <&tsens1 0>; 5264 5265 trips { 5266 trip-point0 { 5267 temperature = <105000>; 5268 hysteresis = <5000>; 5269 type = "passive"; 5270 }; 5271 5272 trip-point1 { 5273 temperature = <115000>; 5274 hysteresis = <5000>; 5275 type = "passive"; 5276 }; 5277 }; 5278 }; 5279 5280 cpu-0-0-1-thermal { 5281 polling-delay-passive = <10>; 5282 5283 thermal-sensors = <&tsens1 1>; 5284 5285 trips { 5286 trip-point0 { 5287 temperature = <105000>; 5288 hysteresis = <5000>; 5289 type = "passive"; 5290 }; 5291 5292 trip-point1 { 5293 temperature = <115000>; 5294 hysteresis = <5000>; 5295 type = "passive"; 5296 }; 5297 }; 5298 }; 5299 5300 cpu-0-1-1-thermal { 5301 polling-delay-passive = <10>; 5302 5303 thermal-sensors = <&tsens1 2>; 5304 5305 trips { 5306 trip-point0 { 5307 temperature = <105000>; 5308 hysteresis = <5000>; 5309 type = "passive"; 5310 }; 5311 5312 trip-point1 { 5313 temperature = <115000>; 5314 hysteresis = <5000>; 5315 type = "passive"; 5316 }; 5317 }; 5318 }; 5319 5320 cpu-0-2-1-thermal { 5321 polling-delay-passive = <10>; 5322 5323 thermal-sensors = <&tsens1 3>; 5324 5325 trips { 5326 trip-point0 { 5327 temperature = <105000>; 5328 hysteresis = <5000>; 5329 type = "passive"; 5330 }; 5331 5332 trip-point1 { 5333 temperature = <115000>; 5334 hysteresis = <5000>; 5335 type = "passive"; 5336 }; 5337 }; 5338 }; 5339 5340 cpu-0-3-1-thermal { 5341 polling-delay-passive = <10>; 5342 5343 thermal-sensors = <&tsens1 4>; 5344 5345 trips { 5346 trip-point0 { 5347 temperature = <105000>; 5348 hysteresis = <5000>; 5349 type = "passive"; 5350 }; 5351 5352 trip-point1 { 5353 temperature = <115000>; 5354 hysteresis = <5000>; 5355 type = "passive"; 5356 }; 5357 }; 5358 }; 5359 5360 gpuss-3-thermal { 5361 polling-delay-passive = <10>; 5362 5363 thermal-sensors = <&tsens1 5>; 5364 5365 trips { 5366 trip-point0 { 5367 temperature = <105000>; 5368 hysteresis = <5000>; 5369 type = "passive"; 5370 }; 5371 5372 trip-point1 { 5373 temperature = <115000>; 5374 hysteresis = <5000>; 5375 type = "passive"; 5376 }; 5377 }; 5378 }; 5379 5380 gpuss-4-thermal { 5381 polling-delay-passive = <10>; 5382 5383 thermal-sensors = <&tsens1 6>; 5384 5385 trips { 5386 trip-point0 { 5387 temperature = <105000>; 5388 hysteresis = <5000>; 5389 type = "passive"; 5390 }; 5391 5392 trip-point1 { 5393 temperature = <115000>; 5394 hysteresis = <5000>; 5395 type = "passive"; 5396 }; 5397 }; 5398 }; 5399 5400 gpuss-5-thermal { 5401 polling-delay-passive = <10>; 5402 5403 thermal-sensors = <&tsens1 7>; 5404 5405 trips { 5406 trip-point0 { 5407 temperature = <105000>; 5408 hysteresis = <5000>; 5409 type = "passive"; 5410 }; 5411 5412 trip-point1 { 5413 temperature = <115000>; 5414 hysteresis = <5000>; 5415 type = "passive"; 5416 }; 5417 }; 5418 }; 5419 5420 video-thermal { 5421 thermal-sensors = <&tsens1 8>; 5422 5423 trips { 5424 trip-point0 { 5425 temperature = <105000>; 5426 hysteresis = <5000>; 5427 type = "passive"; 5428 }; 5429 5430 trip-point1 { 5431 temperature = <115000>; 5432 hysteresis = <5000>; 5433 type = "passive"; 5434 }; 5435 }; 5436 }; 5437 5438 camss-1-thermal { 5439 thermal-sensors = <&tsens1 9>; 5440 5441 trips { 5442 trip-point0 { 5443 temperature = <105000>; 5444 hysteresis = <5000>; 5445 type = "passive"; 5446 }; 5447 5448 trip-point1 { 5449 temperature = <115000>; 5450 hysteresis = <5000>; 5451 type = "passive"; 5452 }; 5453 }; 5454 }; 5455 5456 pcie-1-thermal { 5457 thermal-sensors = <&tsens1 10>; 5458 5459 trips { 5460 trip-point0 { 5461 temperature = <105000>; 5462 hysteresis = <5000>; 5463 type = "passive"; 5464 }; 5465 5466 trip-point1 { 5467 temperature = <115000>; 5468 hysteresis = <5000>; 5469 type = "passive"; 5470 }; 5471 }; 5472 }; 5473 5474 cpuss-0-1-thermal { 5475 thermal-sensors = <&tsens1 11>; 5476 5477 trips { 5478 trip-point0 { 5479 temperature = <105000>; 5480 hysteresis = <5000>; 5481 type = "passive"; 5482 }; 5483 5484 trip-point1 { 5485 temperature = <115000>; 5486 hysteresis = <5000>; 5487 type = "passive"; 5488 }; 5489 }; 5490 }; 5491 5492 aoss-2-thermal { 5493 thermal-sensors = <&tsens2 0>; 5494 5495 trips { 5496 trip-point0 { 5497 temperature = <105000>; 5498 hysteresis = <5000>; 5499 type = "passive"; 5500 }; 5501 5502 trip-point1 { 5503 temperature = <115000>; 5504 hysteresis = <5000>; 5505 type = "passive"; 5506 }; 5507 }; 5508 }; 5509 5510 cpu-1-0-0-thermal { 5511 polling-delay-passive = <10>; 5512 5513 thermal-sensors = <&tsens2 1>; 5514 5515 trips { 5516 trip-point0 { 5517 temperature = <105000>; 5518 hysteresis = <5000>; 5519 type = "passive"; 5520 }; 5521 5522 trip-point1 { 5523 temperature = <115000>; 5524 hysteresis = <5000>; 5525 type = "passive"; 5526 }; 5527 }; 5528 }; 5529 5530 cpu-1-1-0-thermal { 5531 polling-delay-passive = <10>; 5532 5533 thermal-sensors = <&tsens2 2>; 5534 5535 trips { 5536 trip-point0 { 5537 temperature = <105000>; 5538 hysteresis = <5000>; 5539 type = "passive"; 5540 }; 5541 5542 trip-point1 { 5543 temperature = <115000>; 5544 hysteresis = <5000>; 5545 type = "passive"; 5546 }; 5547 }; 5548 }; 5549 5550 cpu-1-2-0-thermal { 5551 polling-delay-passive = <10>; 5552 5553 thermal-sensors = <&tsens2 3>; 5554 5555 trips { 5556 trip-point0 { 5557 temperature = <105000>; 5558 hysteresis = <5000>; 5559 type = "passive"; 5560 }; 5561 5562 trip-point1 { 5563 temperature = <115000>; 5564 hysteresis = <5000>; 5565 type = "passive"; 5566 }; 5567 }; 5568 }; 5569 5570 cpu-1-3-0-thermal { 5571 polling-delay-passive = <10>; 5572 5573 thermal-sensors = <&tsens2 4>; 5574 5575 trips { 5576 trip-point0 { 5577 temperature = <105000>; 5578 hysteresis = <5000>; 5579 type = "passive"; 5580 }; 5581 5582 trip-point1 { 5583 temperature = <115000>; 5584 hysteresis = <5000>; 5585 type = "passive"; 5586 }; 5587 }; 5588 }; 5589 5590 nsp-0-0-0-thermal { 5591 polling-delay-passive = <10>; 5592 5593 thermal-sensors = <&tsens2 5>; 5594 5595 trips { 5596 trip-point0 { 5597 temperature = <105000>; 5598 hysteresis = <5000>; 5599 type = "passive"; 5600 }; 5601 5602 trip-point1 { 5603 temperature = <115000>; 5604 hysteresis = <5000>; 5605 type = "passive"; 5606 }; 5607 }; 5608 }; 5609 5610 nsp-0-1-0-thermal { 5611 polling-delay-passive = <10>; 5612 5613 thermal-sensors = <&tsens2 6>; 5614 5615 trips { 5616 trip-point0 { 5617 temperature = <105000>; 5618 hysteresis = <5000>; 5619 type = "passive"; 5620 }; 5621 5622 trip-point1 { 5623 temperature = <115000>; 5624 hysteresis = <5000>; 5625 type = "passive"; 5626 }; 5627 }; 5628 }; 5629 5630 nsp-0-2-0-thermal { 5631 polling-delay-passive = <10>; 5632 5633 thermal-sensors = <&tsens2 7>; 5634 5635 trips { 5636 trip-point0 { 5637 temperature = <105000>; 5638 hysteresis = <5000>; 5639 type = "passive"; 5640 }; 5641 5642 trip-point1 { 5643 temperature = <115000>; 5644 hysteresis = <5000>; 5645 type = "passive"; 5646 }; 5647 }; 5648 }; 5649 5650 nsp-1-0-0-thermal { 5651 polling-delay-passive = <10>; 5652 5653 thermal-sensors = <&tsens2 8>; 5654 5655 trips { 5656 trip-point0 { 5657 temperature = <105000>; 5658 hysteresis = <5000>; 5659 type = "passive"; 5660 }; 5661 5662 trip-point1 { 5663 temperature = <115000>; 5664 hysteresis = <5000>; 5665 type = "passive"; 5666 }; 5667 }; 5668 }; 5669 5670 nsp-1-1-0-thermal { 5671 polling-delay-passive = <10>; 5672 5673 thermal-sensors = <&tsens2 9>; 5674 5675 trips { 5676 trip-point0 { 5677 temperature = <105000>; 5678 hysteresis = <5000>; 5679 type = "passive"; 5680 }; 5681 5682 trip-point1 { 5683 temperature = <115000>; 5684 hysteresis = <5000>; 5685 type = "passive"; 5686 }; 5687 }; 5688 }; 5689 5690 nsp-1-2-0-thermal { 5691 polling-delay-passive = <10>; 5692 5693 thermal-sensors = <&tsens2 10>; 5694 5695 trips { 5696 trip-point0 { 5697 temperature = <105000>; 5698 hysteresis = <5000>; 5699 type = "passive"; 5700 }; 5701 5702 trip-point1 { 5703 temperature = <115000>; 5704 hysteresis = <5000>; 5705 type = "passive"; 5706 }; 5707 }; 5708 }; 5709 5710 ddrss-0-thermal { 5711 thermal-sensors = <&tsens2 11>; 5712 5713 trips { 5714 trip-point0 { 5715 temperature = <105000>; 5716 hysteresis = <5000>; 5717 type = "passive"; 5718 }; 5719 5720 trip-point1 { 5721 temperature = <115000>; 5722 hysteresis = <5000>; 5723 type = "passive"; 5724 }; 5725 }; 5726 }; 5727 5728 cpuss-1-0-thermal { 5729 thermal-sensors = <&tsens2 12>; 5730 5731 trips { 5732 trip-point0 { 5733 temperature = <105000>; 5734 hysteresis = <5000>; 5735 type = "passive"; 5736 }; 5737 5738 trip-point1 { 5739 temperature = <115000>; 5740 hysteresis = <5000>; 5741 type = "passive"; 5742 }; 5743 }; 5744 }; 5745 5746 aoss-3-thermal { 5747 thermal-sensors = <&tsens3 0>; 5748 5749 trips { 5750 trip-point0 { 5751 temperature = <105000>; 5752 hysteresis = <5000>; 5753 type = "passive"; 5754 }; 5755 5756 trip-point1 { 5757 temperature = <115000>; 5758 hysteresis = <5000>; 5759 type = "passive"; 5760 }; 5761 }; 5762 }; 5763 5764 cpu-1-0-1-thermal { 5765 polling-delay-passive = <10>; 5766 5767 thermal-sensors = <&tsens3 1>; 5768 5769 trips { 5770 trip-point0 { 5771 temperature = <105000>; 5772 hysteresis = <5000>; 5773 type = "passive"; 5774 }; 5775 5776 trip-point1 { 5777 temperature = <115000>; 5778 hysteresis = <5000>; 5779 type = "passive"; 5780 }; 5781 }; 5782 }; 5783 5784 cpu-1-1-1-thermal { 5785 polling-delay-passive = <10>; 5786 5787 thermal-sensors = <&tsens3 2>; 5788 5789 trips { 5790 trip-point0 { 5791 temperature = <105000>; 5792 hysteresis = <5000>; 5793 type = "passive"; 5794 }; 5795 5796 trip-point1 { 5797 temperature = <115000>; 5798 hysteresis = <5000>; 5799 type = "passive"; 5800 }; 5801 }; 5802 }; 5803 5804 cpu-1-2-1-thermal { 5805 polling-delay-passive = <10>; 5806 5807 thermal-sensors = <&tsens3 3>; 5808 5809 trips { 5810 trip-point0 { 5811 temperature = <105000>; 5812 hysteresis = <5000>; 5813 type = "passive"; 5814 }; 5815 5816 trip-point1 { 5817 temperature = <115000>; 5818 hysteresis = <5000>; 5819 type = "passive"; 5820 }; 5821 }; 5822 }; 5823 5824 cpu-1-3-1-thermal { 5825 polling-delay-passive = <10>; 5826 5827 thermal-sensors = <&tsens3 4>; 5828 5829 trips { 5830 trip-point0 { 5831 temperature = <105000>; 5832 hysteresis = <5000>; 5833 type = "passive"; 5834 }; 5835 5836 trip-point1 { 5837 temperature = <115000>; 5838 hysteresis = <5000>; 5839 type = "passive"; 5840 }; 5841 }; 5842 }; 5843 5844 nsp-0-0-1-thermal { 5845 polling-delay-passive = <10>; 5846 5847 thermal-sensors = <&tsens3 5>; 5848 5849 trips { 5850 trip-point0 { 5851 temperature = <105000>; 5852 hysteresis = <5000>; 5853 type = "passive"; 5854 }; 5855 5856 trip-point1 { 5857 temperature = <115000>; 5858 hysteresis = <5000>; 5859 type = "passive"; 5860 }; 5861 }; 5862 }; 5863 5864 nsp-0-1-1-thermal { 5865 polling-delay-passive = <10>; 5866 5867 thermal-sensors = <&tsens3 6>; 5868 5869 trips { 5870 trip-point0 { 5871 temperature = <105000>; 5872 hysteresis = <5000>; 5873 type = "passive"; 5874 }; 5875 5876 trip-point1 { 5877 temperature = <115000>; 5878 hysteresis = <5000>; 5879 type = "passive"; 5880 }; 5881 }; 5882 }; 5883 5884 nsp-0-2-1-thermal { 5885 polling-delay-passive = <10>; 5886 5887 thermal-sensors = <&tsens3 7>; 5888 5889 trips { 5890 trip-point0 { 5891 temperature = <105000>; 5892 hysteresis = <5000>; 5893 type = "passive"; 5894 }; 5895 5896 trip-point1 { 5897 temperature = <115000>; 5898 hysteresis = <5000>; 5899 type = "passive"; 5900 }; 5901 }; 5902 }; 5903 5904 nsp-1-0-1-thermal { 5905 polling-delay-passive = <10>; 5906 5907 thermal-sensors = <&tsens3 8>; 5908 5909 trips { 5910 trip-point0 { 5911 temperature = <105000>; 5912 hysteresis = <5000>; 5913 type = "passive"; 5914 }; 5915 5916 trip-point1 { 5917 temperature = <115000>; 5918 hysteresis = <5000>; 5919 type = "passive"; 5920 }; 5921 }; 5922 }; 5923 5924 nsp-1-1-1-thermal { 5925 polling-delay-passive = <10>; 5926 5927 thermal-sensors = <&tsens3 9>; 5928 5929 trips { 5930 trip-point0 { 5931 temperature = <105000>; 5932 hysteresis = <5000>; 5933 type = "passive"; 5934 }; 5935 5936 trip-point1 { 5937 temperature = <115000>; 5938 hysteresis = <5000>; 5939 type = "passive"; 5940 }; 5941 }; 5942 }; 5943 5944 nsp-1-2-1-thermal { 5945 polling-delay-passive = <10>; 5946 5947 thermal-sensors = <&tsens3 10>; 5948 5949 trips { 5950 trip-point0 { 5951 temperature = <105000>; 5952 hysteresis = <5000>; 5953 type = "passive"; 5954 }; 5955 5956 trip-point1 { 5957 temperature = <115000>; 5958 hysteresis = <5000>; 5959 type = "passive"; 5960 }; 5961 }; 5962 }; 5963 5964 ddrss-1-thermal { 5965 thermal-sensors = <&tsens3 11>; 5966 5967 trips { 5968 trip-point0 { 5969 temperature = <105000>; 5970 hysteresis = <5000>; 5971 type = "passive"; 5972 }; 5973 5974 trip-point1 { 5975 temperature = <115000>; 5976 hysteresis = <5000>; 5977 type = "passive"; 5978 }; 5979 }; 5980 }; 5981 5982 cpuss-1-1-thermal { 5983 thermal-sensors = <&tsens3 12>; 5984 5985 trips { 5986 trip-point0 { 5987 temperature = <105000>; 5988 hysteresis = <5000>; 5989 type = "passive"; 5990 }; 5991 5992 trip-point1 { 5993 temperature = <115000>; 5994 hysteresis = <5000>; 5995 type = "passive"; 5996 }; 5997 }; 5998 }; 5999 }; 6000 6001 arch_timer: timer { 6002 compatible = "arm,armv8-timer"; 6003 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6004 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6005 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6006 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6007 }; 6008 6009 pcie0: pcie@1c00000 { 6010 compatible = "qcom,pcie-sa8775p"; 6011 reg = <0x0 0x01c00000 0x0 0x3000>, 6012 <0x0 0x40000000 0x0 0xf20>, 6013 <0x0 0x40000f20 0x0 0xa8>, 6014 <0x0 0x40001000 0x0 0x4000>, 6015 <0x0 0x40100000 0x0 0x100000>, 6016 <0x0 0x01c03000 0x0 0x1000>; 6017 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 6018 device_type = "pci"; 6019 6020 #address-cells = <3>; 6021 #size-cells = <2>; 6022 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 6023 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 6024 bus-range = <0x00 0xff>; 6025 6026 dma-coherent; 6027 6028 linux,pci-domain = <0>; 6029 num-lanes = <2>; 6030 6031 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 6032 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 6033 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 6034 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 6035 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 6036 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 6037 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 6038 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 6039 interrupt-names = "msi0", "msi1", "msi2", "msi3", 6040 "msi4", "msi5", "msi6", "msi7"; 6041 #interrupt-cells = <1>; 6042 interrupt-map-mask = <0 0 0 0x7>; 6043 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 6044 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 6045 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 6046 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 6047 6048 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 6049 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 6050 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 6051 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 6052 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 6053 6054 clock-names = "aux", 6055 "cfg", 6056 "bus_master", 6057 "bus_slave", 6058 "slave_q2a"; 6059 6060 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 6061 assigned-clock-rates = <19200000>; 6062 6063 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 6064 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 6065 interconnect-names = "pcie-mem", "cpu-pcie"; 6066 6067 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 6068 <0x100 &pcie_smmu 0x0001 0x1>; 6069 6070 resets = <&gcc GCC_PCIE_0_BCR>; 6071 reset-names = "pci"; 6072 power-domains = <&gcc PCIE_0_GDSC>; 6073 6074 phys = <&pcie0_phy>; 6075 phy-names = "pciephy"; 6076 6077 status = "disabled"; 6078 6079 pcieport0: pcie@0 { 6080 device_type = "pci"; 6081 reg = <0x0 0x0 0x0 0x0 0x0>; 6082 bus-range = <0x01 0xff>; 6083 6084 #address-cells = <3>; 6085 #size-cells = <2>; 6086 ranges; 6087 }; 6088 }; 6089 6090 pcie0_ep: pcie-ep@1c00000 { 6091 compatible = "qcom,sa8775p-pcie-ep"; 6092 reg = <0x0 0x01c00000 0x0 0x3000>, 6093 <0x0 0x40000000 0x0 0xf20>, 6094 <0x0 0x40000f20 0x0 0xa8>, 6095 <0x0 0x40001000 0x0 0x4000>, 6096 <0x0 0x40200000 0x0 0x1fe00000>, 6097 <0x0 0x01c03000 0x0 0x1000>, 6098 <0x0 0x40005000 0x0 0x2000>; 6099 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 6100 "mmio", "dma"; 6101 6102 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 6103 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 6104 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 6105 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 6106 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 6107 6108 clock-names = "aux", 6109 "cfg", 6110 "bus_master", 6111 "bus_slave", 6112 "slave_q2a"; 6113 6114 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 6115 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 6116 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; 6117 6118 interrupt-names = "global", "doorbell", "dma"; 6119 6120 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 6121 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 6122 interconnect-names = "pcie-mem", "cpu-pcie"; 6123 6124 dma-coherent; 6125 iommus = <&pcie_smmu 0x0000 0x7f>; 6126 resets = <&gcc GCC_PCIE_0_BCR>; 6127 reset-names = "core"; 6128 power-domains = <&gcc PCIE_0_GDSC>; 6129 phys = <&pcie0_phy>; 6130 phy-names = "pciephy"; 6131 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ 6132 num-lanes = <2>; 6133 linux,pci-domain = <0>; 6134 6135 status = "disabled"; 6136 }; 6137 6138 pcie0_phy: phy@1c04000 { 6139 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 6140 reg = <0x0 0x1c04000 0x0 0x2000>; 6141 6142 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 6143 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 6144 <&gcc GCC_PCIE_CLKREF_EN>, 6145 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 6146 <&gcc GCC_PCIE_0_PIPE_CLK>, 6147 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, 6148 <&gcc GCC_PCIE_0_PHY_AUX_CLK>; 6149 6150 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 6151 "pipediv2", "phy_aux"; 6152 6153 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 6154 assigned-clock-rates = <100000000>; 6155 6156 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 6157 reset-names = "phy"; 6158 6159 #clock-cells = <0>; 6160 clock-output-names = "pcie_0_pipe_clk"; 6161 6162 #phy-cells = <0>; 6163 6164 status = "disabled"; 6165 }; 6166 6167 pcie1: pcie@1c10000 { 6168 compatible = "qcom,pcie-sa8775p"; 6169 reg = <0x0 0x01c10000 0x0 0x3000>, 6170 <0x0 0x60000000 0x0 0xf20>, 6171 <0x0 0x60000f20 0x0 0xa8>, 6172 <0x0 0x60001000 0x0 0x4000>, 6173 <0x0 0x60100000 0x0 0x100000>, 6174 <0x0 0x01c13000 0x0 0x1000>; 6175 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 6176 device_type = "pci"; 6177 6178 #address-cells = <3>; 6179 #size-cells = <2>; 6180 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 6181 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 6182 bus-range = <0x00 0xff>; 6183 6184 dma-coherent; 6185 6186 linux,pci-domain = <1>; 6187 num-lanes = <4>; 6188 6189 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 6190 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 6191 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 6192 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 6193 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 6194 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 6195 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 6196 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 6197 interrupt-names = "msi0", "msi1", "msi2", "msi3", 6198 "msi4", "msi5", "msi6", "msi7"; 6199 #interrupt-cells = <1>; 6200 interrupt-map-mask = <0 0 0 0x7>; 6201 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 6202 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 6203 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 6204 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 6205 6206 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 6207 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 6208 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 6209 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 6210 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 6211 6212 clock-names = "aux", 6213 "cfg", 6214 "bus_master", 6215 "bus_slave", 6216 "slave_q2a"; 6217 6218 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 6219 assigned-clock-rates = <19200000>; 6220 6221 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 6222 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 6223 interconnect-names = "pcie-mem", "cpu-pcie"; 6224 6225 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 6226 <0x100 &pcie_smmu 0x0081 0x1>; 6227 6228 resets = <&gcc GCC_PCIE_1_BCR>; 6229 reset-names = "pci"; 6230 power-domains = <&gcc PCIE_1_GDSC>; 6231 6232 phys = <&pcie1_phy>; 6233 phy-names = "pciephy"; 6234 6235 status = "disabled"; 6236 6237 pcie@0 { 6238 device_type = "pci"; 6239 reg = <0x0 0x0 0x0 0x0 0x0>; 6240 bus-range = <0x01 0xff>; 6241 6242 #address-cells = <3>; 6243 #size-cells = <2>; 6244 ranges; 6245 }; 6246 }; 6247 6248 pcie1_ep: pcie-ep@1c10000 { 6249 compatible = "qcom,sa8775p-pcie-ep"; 6250 reg = <0x0 0x01c10000 0x0 0x3000>, 6251 <0x0 0x60000000 0x0 0xf20>, 6252 <0x0 0x60000f20 0x0 0xa8>, 6253 <0x0 0x60001000 0x0 0x4000>, 6254 <0x0 0x60200000 0x0 0x1fe00000>, 6255 <0x0 0x01c13000 0x0 0x1000>, 6256 <0x0 0x60005000 0x0 0x2000>; 6257 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 6258 "mmio", "dma"; 6259 6260 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 6261 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 6262 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 6263 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 6264 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 6265 6266 clock-names = "aux", 6267 "cfg", 6268 "bus_master", 6269 "bus_slave", 6270 "slave_q2a"; 6271 6272 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 6273 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 6274 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 6275 6276 interrupt-names = "global", "doorbell", "dma"; 6277 6278 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 6279 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 6280 interconnect-names = "pcie-mem", "cpu-pcie"; 6281 6282 dma-coherent; 6283 iommus = <&pcie_smmu 0x80 0x7f>; 6284 resets = <&gcc GCC_PCIE_1_BCR>; 6285 reset-names = "core"; 6286 power-domains = <&gcc PCIE_1_GDSC>; 6287 phys = <&pcie1_phy>; 6288 phy-names = "pciephy"; 6289 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ 6290 num-lanes = <4>; 6291 linux,pci-domain = <1>; 6292 6293 status = "disabled"; 6294 }; 6295 6296 pcie1_phy: phy@1c14000 { 6297 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 6298 reg = <0x0 0x1c14000 0x0 0x4000>; 6299 6300 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 6301 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 6302 <&gcc GCC_PCIE_CLKREF_EN>, 6303 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 6304 <&gcc GCC_PCIE_1_PIPE_CLK>, 6305 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, 6306 <&gcc GCC_PCIE_1_PHY_AUX_CLK>; 6307 6308 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 6309 "pipediv2", "phy_aux"; 6310 6311 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 6312 assigned-clock-rates = <100000000>; 6313 6314 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 6315 reset-names = "phy"; 6316 6317 #clock-cells = <0>; 6318 clock-output-names = "pcie_1_pipe_clk"; 6319 6320 #phy-cells = <0>; 6321 6322 status = "disabled"; 6323 }; 6324}; 6325