1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,icc.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 10#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 11#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 12#include <dt-bindings/mailbox/qcom-ipcc.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 clocks { 23 xo_board_clk: xo-board-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 CPU0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "qcom,kryo"; 41 reg = <0x0 0x0>; 42 enable-method = "psci"; 43 qcom,freq-domain = <&cpufreq_hw 0>; 44 next-level-cache = <&L2_0>; 45 L2_0: l2-cache { 46 compatible = "cache"; 47 cache-level = <2>; 48 cache-unified; 49 next-level-cache = <&L3_0>; 50 L3_0: l3-cache { 51 compatible = "cache"; 52 cache-level = <3>; 53 cache-unified; 54 }; 55 }; 56 }; 57 58 CPU1: cpu@100 { 59 device_type = "cpu"; 60 compatible = "qcom,kryo"; 61 reg = <0x0 0x100>; 62 enable-method = "psci"; 63 qcom,freq-domain = <&cpufreq_hw 0>; 64 next-level-cache = <&L2_1>; 65 L2_1: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&L3_0>; 70 }; 71 }; 72 73 CPU2: cpu@200 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo"; 76 reg = <0x0 0x200>; 77 enable-method = "psci"; 78 qcom,freq-domain = <&cpufreq_hw 0>; 79 next-level-cache = <&L2_2>; 80 L2_2: l2-cache { 81 compatible = "cache"; 82 cache-level = <2>; 83 cache-unified; 84 next-level-cache = <&L3_0>; 85 }; 86 }; 87 88 CPU3: cpu@300 { 89 device_type = "cpu"; 90 compatible = "qcom,kryo"; 91 reg = <0x0 0x300>; 92 enable-method = "psci"; 93 qcom,freq-domain = <&cpufreq_hw 0>; 94 next-level-cache = <&L2_3>; 95 L2_3: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 next-level-cache = <&L3_0>; 100 }; 101 }; 102 103 CPU4: cpu@10000 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo"; 106 reg = <0x0 0x10000>; 107 enable-method = "psci"; 108 qcom,freq-domain = <&cpufreq_hw 1>; 109 next-level-cache = <&L2_4>; 110 L2_4: l2-cache { 111 compatible = "cache"; 112 cache-level = <2>; 113 cache-unified; 114 next-level-cache = <&L3_1>; 115 L3_1: l3-cache { 116 compatible = "cache"; 117 cache-level = <3>; 118 cache-unified; 119 }; 120 121 }; 122 }; 123 124 CPU5: cpu@10100 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo"; 127 reg = <0x0 0x10100>; 128 enable-method = "psci"; 129 qcom,freq-domain = <&cpufreq_hw 1>; 130 next-level-cache = <&L2_5>; 131 L2_5: l2-cache { 132 compatible = "cache"; 133 cache-level = <2>; 134 cache-unified; 135 next-level-cache = <&L3_1>; 136 }; 137 }; 138 139 CPU6: cpu@10200 { 140 device_type = "cpu"; 141 compatible = "qcom,kryo"; 142 reg = <0x0 0x10200>; 143 enable-method = "psci"; 144 qcom,freq-domain = <&cpufreq_hw 1>; 145 next-level-cache = <&L2_6>; 146 L2_6: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&L3_1>; 151 }; 152 }; 153 154 CPU7: cpu@10300 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo"; 157 reg = <0x0 0x10300>; 158 enable-method = "psci"; 159 qcom,freq-domain = <&cpufreq_hw 1>; 160 next-level-cache = <&L2_7>; 161 L2_7: l2-cache { 162 compatible = "cache"; 163 cache-level = <2>; 164 cache-unified; 165 next-level-cache = <&L3_1>; 166 }; 167 }; 168 169 cpu-map { 170 cluster0 { 171 core0 { 172 cpu = <&CPU0>; 173 }; 174 175 core1 { 176 cpu = <&CPU1>; 177 }; 178 179 core2 { 180 cpu = <&CPU2>; 181 }; 182 183 core3 { 184 cpu = <&CPU3>; 185 }; 186 }; 187 188 cluster1 { 189 core0 { 190 cpu = <&CPU4>; 191 }; 192 193 core1 { 194 cpu = <&CPU5>; 195 }; 196 197 core2 { 198 cpu = <&CPU6>; 199 }; 200 201 core3 { 202 cpu = <&CPU7>; 203 }; 204 }; 205 }; 206 }; 207 208 dummy-sink { 209 compatible = "arm,coresight-dummy-sink"; 210 211 in-ports { 212 port { 213 eud_in: endpoint { 214 remote-endpoint = 215 <&swao_rep_out1>; 216 }; 217 }; 218 }; 219 }; 220 221 firmware { 222 scm { 223 compatible = "qcom,scm-sa8775p", "qcom,scm"; 224 memory-region = <&tz_ffi_mem>; 225 }; 226 }; 227 228 aggre1_noc: interconnect-aggre1-noc { 229 compatible = "qcom,sa8775p-aggre1-noc"; 230 #interconnect-cells = <2>; 231 qcom,bcm-voters = <&apps_bcm_voter>; 232 }; 233 234 aggre2_noc: interconnect-aggre2-noc { 235 compatible = "qcom,sa8775p-aggre2-noc"; 236 #interconnect-cells = <2>; 237 qcom,bcm-voters = <&apps_bcm_voter>; 238 }; 239 240 clk_virt: interconnect-clk-virt { 241 compatible = "qcom,sa8775p-clk-virt"; 242 #interconnect-cells = <2>; 243 qcom,bcm-voters = <&apps_bcm_voter>; 244 }; 245 246 config_noc: interconnect-config-noc { 247 compatible = "qcom,sa8775p-config-noc"; 248 #interconnect-cells = <2>; 249 qcom,bcm-voters = <&apps_bcm_voter>; 250 }; 251 252 dc_noc: interconnect-dc-noc { 253 compatible = "qcom,sa8775p-dc-noc"; 254 #interconnect-cells = <2>; 255 qcom,bcm-voters = <&apps_bcm_voter>; 256 }; 257 258 gem_noc: interconnect-gem-noc { 259 compatible = "qcom,sa8775p-gem-noc"; 260 #interconnect-cells = <2>; 261 qcom,bcm-voters = <&apps_bcm_voter>; 262 }; 263 264 gpdsp_anoc: interconnect-gpdsp-anoc { 265 compatible = "qcom,sa8775p-gpdsp-anoc"; 266 #interconnect-cells = <2>; 267 qcom,bcm-voters = <&apps_bcm_voter>; 268 }; 269 270 lpass_ag_noc: interconnect-lpass-ag-noc { 271 compatible = "qcom,sa8775p-lpass-ag-noc"; 272 #interconnect-cells = <2>; 273 qcom,bcm-voters = <&apps_bcm_voter>; 274 }; 275 276 mc_virt: interconnect-mc-virt { 277 compatible = "qcom,sa8775p-mc-virt"; 278 #interconnect-cells = <2>; 279 qcom,bcm-voters = <&apps_bcm_voter>; 280 }; 281 282 mmss_noc: interconnect-mmss-noc { 283 compatible = "qcom,sa8775p-mmss-noc"; 284 #interconnect-cells = <2>; 285 qcom,bcm-voters = <&apps_bcm_voter>; 286 }; 287 288 nspa_noc: interconnect-nspa-noc { 289 compatible = "qcom,sa8775p-nspa-noc"; 290 #interconnect-cells = <2>; 291 qcom,bcm-voters = <&apps_bcm_voter>; 292 }; 293 294 nspb_noc: interconnect-nspb-noc { 295 compatible = "qcom,sa8775p-nspb-noc"; 296 #interconnect-cells = <2>; 297 qcom,bcm-voters = <&apps_bcm_voter>; 298 }; 299 300 pcie_anoc: interconnect-pcie-anoc { 301 compatible = "qcom,sa8775p-pcie-anoc"; 302 #interconnect-cells = <2>; 303 qcom,bcm-voters = <&apps_bcm_voter>; 304 }; 305 306 system_noc: interconnect-system-noc { 307 compatible = "qcom,sa8775p-system-noc"; 308 #interconnect-cells = <2>; 309 qcom,bcm-voters = <&apps_bcm_voter>; 310 }; 311 312 /* Will be updated by the bootloader. */ 313 memory@80000000 { 314 device_type = "memory"; 315 reg = <0x0 0x80000000 0x0 0x0>; 316 }; 317 318 qup_opp_table_100mhz: opp-table-qup100mhz { 319 compatible = "operating-points-v2"; 320 321 opp-100000000 { 322 opp-hz = /bits/ 64 <100000000>; 323 required-opps = <&rpmhpd_opp_svs_l1>; 324 }; 325 }; 326 327 pmu { 328 compatible = "arm,armv8-pmuv3"; 329 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 330 }; 331 332 psci { 333 compatible = "arm,psci-1.0"; 334 method = "smc"; 335 }; 336 337 reserved-memory { 338 #address-cells = <2>; 339 #size-cells = <2>; 340 ranges; 341 342 sail_ss_mem: sail-ss@80000000 { 343 reg = <0x0 0x80000000 0x0 0x10000000>; 344 no-map; 345 }; 346 347 hyp_mem: hyp@90000000 { 348 reg = <0x0 0x90000000 0x0 0x600000>; 349 no-map; 350 }; 351 352 xbl_boot_mem: xbl-boot@90600000 { 353 reg = <0x0 0x90600000 0x0 0x200000>; 354 no-map; 355 }; 356 357 aop_image_mem: aop-image@90800000 { 358 reg = <0x0 0x90800000 0x0 0x60000>; 359 no-map; 360 }; 361 362 aop_cmd_db_mem: aop-cmd-db@90860000 { 363 compatible = "qcom,cmd-db"; 364 reg = <0x0 0x90860000 0x0 0x20000>; 365 no-map; 366 }; 367 368 uefi_log: uefi-log@908b0000 { 369 reg = <0x0 0x908b0000 0x0 0x10000>; 370 no-map; 371 }; 372 373 ddr_training_checksum: ddr-training-checksum@908c0000 { 374 reg = <0x0 0x908c0000 0x0 0x1000>; 375 no-map; 376 }; 377 378 reserved_mem: reserved@908f0000 { 379 reg = <0x0 0x908f0000 0x0 0xe000>; 380 no-map; 381 }; 382 383 secdata_apss_mem: secdata-apss@908fe000 { 384 reg = <0x0 0x908fe000 0x0 0x2000>; 385 no-map; 386 }; 387 388 smem_mem: smem@90900000 { 389 compatible = "qcom,smem"; 390 reg = <0x0 0x90900000 0x0 0x200000>; 391 no-map; 392 hwlocks = <&tcsr_mutex 3>; 393 }; 394 395 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { 396 reg = <0x0 0x90c00000 0x0 0x100000>; 397 no-map; 398 }; 399 400 sail_mailbox_mem: sail-ss@90d00000 { 401 reg = <0x0 0x90d00000 0x0 0x100000>; 402 no-map; 403 }; 404 405 sail_ota_mem: sail-ss@90e00000 { 406 reg = <0x0 0x90e00000 0x0 0x300000>; 407 no-map; 408 }; 409 410 aoss_backup_mem: aoss-backup@91b00000 { 411 reg = <0x0 0x91b00000 0x0 0x40000>; 412 no-map; 413 }; 414 415 cpucp_backup_mem: cpucp-backup@91b40000 { 416 reg = <0x0 0x91b40000 0x0 0x40000>; 417 no-map; 418 }; 419 420 tz_config_backup_mem: tz-config-backup@91b80000 { 421 reg = <0x0 0x91b80000 0x0 0x10000>; 422 no-map; 423 }; 424 425 ddr_training_data_mem: ddr-training-data@91b90000 { 426 reg = <0x0 0x91b90000 0x0 0x10000>; 427 no-map; 428 }; 429 430 cdt_data_backup_mem: cdt-data-backup@91ba0000 { 431 reg = <0x0 0x91ba0000 0x0 0x1000>; 432 no-map; 433 }; 434 435 tz_ffi_mem: tz-ffi@91c00000 { 436 compatible = "shared-dma-pool"; 437 reg = <0x0 0x91c00000 0x0 0x1400000>; 438 no-map; 439 }; 440 441 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 442 reg = <0x0 0x93b00000 0x0 0xf00000>; 443 no-map; 444 }; 445 446 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 447 reg = <0x0 0x94a00000 0x0 0x800000>; 448 no-map; 449 }; 450 451 pil_camera_mem: pil-camera@95200000 { 452 reg = <0x0 0x95200000 0x0 0x500000>; 453 no-map; 454 }; 455 456 pil_adsp_mem: pil-adsp@95c00000 { 457 reg = <0x0 0x95c00000 0x0 0x1e00000>; 458 no-map; 459 }; 460 461 pil_gdsp0_mem: pil-gdsp0@97b00000 { 462 reg = <0x0 0x97b00000 0x0 0x1e00000>; 463 no-map; 464 }; 465 466 pil_gdsp1_mem: pil-gdsp1@99900000 { 467 reg = <0x0 0x99900000 0x0 0x1e00000>; 468 no-map; 469 }; 470 471 pil_cdsp0_mem: pil-cdsp0@9b800000 { 472 reg = <0x0 0x9b800000 0x0 0x1e00000>; 473 no-map; 474 }; 475 476 pil_gpu_mem: pil-gpu@9d600000 { 477 reg = <0x0 0x9d600000 0x0 0x2000>; 478 no-map; 479 }; 480 481 pil_cdsp1_mem: pil-cdsp1@9d700000 { 482 reg = <0x0 0x9d700000 0x0 0x1e00000>; 483 no-map; 484 }; 485 486 pil_cvp_mem: pil-cvp@9f500000 { 487 reg = <0x0 0x9f500000 0x0 0x700000>; 488 no-map; 489 }; 490 491 pil_video_mem: pil-video@9fc00000 { 492 reg = <0x0 0x9fc00000 0x0 0x700000>; 493 no-map; 494 }; 495 496 audio_mdf_mem: audio-mdf-region@ae000000 { 497 reg = <0x0 0xae000000 0x0 0x1000000>; 498 no-map; 499 }; 500 501 firmware_mem: firmware-region@b0000000 { 502 reg = <0x0 0xb0000000 0x0 0x800000>; 503 no-map; 504 }; 505 506 hyptz_reserved_mem: hyptz-reserved@beb00000 { 507 reg = <0x0 0xbeb00000 0x0 0x11500000>; 508 no-map; 509 }; 510 511 scmi_mem: scmi-region@d0000000 { 512 reg = <0x0 0xd0000000 0x0 0x40000>; 513 no-map; 514 }; 515 516 firmware_logs_mem: firmware-logs@d0040000 { 517 reg = <0x0 0xd0040000 0x0 0x10000>; 518 no-map; 519 }; 520 521 firmware_audio_mem: firmware-audio@d0050000 { 522 reg = <0x0 0xd0050000 0x0 0x4000>; 523 no-map; 524 }; 525 526 firmware_reserved_mem: firmware-reserved@d0054000 { 527 reg = <0x0 0xd0054000 0x0 0x9c000>; 528 no-map; 529 }; 530 531 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { 532 reg = <0x0 0xd00f0000 0x0 0x10000>; 533 no-map; 534 }; 535 536 tags_mem: tags@d0100000 { 537 reg = <0x0 0xd0100000 0x0 0x1200000>; 538 no-map; 539 }; 540 541 qtee_mem: qtee@d1300000 { 542 reg = <0x0 0xd1300000 0x0 0x500000>; 543 no-map; 544 }; 545 546 deepsleep_backup_mem: deepsleep-backup@d1800000 { 547 reg = <0x0 0xd1800000 0x0 0x100000>; 548 no-map; 549 }; 550 551 trusted_apps_mem: trusted-apps@d1900000 { 552 reg = <0x0 0xd1900000 0x0 0x3800000>; 553 no-map; 554 }; 555 556 tz_stat_mem: tz-stat@db100000 { 557 reg = <0x0 0xdb100000 0x0 0x100000>; 558 no-map; 559 }; 560 561 cpucp_fw_mem: cpucp-fw@db200000 { 562 reg = <0x0 0xdb200000 0x0 0x100000>; 563 no-map; 564 }; 565 }; 566 567 soc: soc@0 { 568 compatible = "simple-bus"; 569 #address-cells = <2>; 570 #size-cells = <2>; 571 ranges = <0 0 0 0 0x10 0>; 572 573 gcc: clock-controller@100000 { 574 compatible = "qcom,sa8775p-gcc"; 575 reg = <0x0 0x00100000 0x0 0xc7018>; 576 #clock-cells = <1>; 577 #reset-cells = <1>; 578 #power-domain-cells = <1>; 579 clocks = <&rpmhcc RPMH_CXO_CLK>, 580 <&sleep_clk>, 581 <0>, 582 <0>, 583 <0>, 584 <&usb_0_qmpphy>, 585 <&usb_1_qmpphy>, 586 <0>, 587 <0>, 588 <0>, 589 <&pcie0_phy>, 590 <&pcie1_phy>, 591 <0>, 592 <0>, 593 <0>; 594 power-domains = <&rpmhpd SA8775P_CX>; 595 }; 596 597 ipcc: mailbox@408000 { 598 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 599 reg = <0x0 0x00408000 0x0 0x1000>; 600 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 601 interrupt-controller; 602 #interrupt-cells = <3>; 603 #mbox-cells = <2>; 604 }; 605 606 qupv3_id_2: geniqup@8c0000 { 607 compatible = "qcom,geni-se-qup"; 608 reg = <0x0 0x008c0000 0x0 0x6000>; 609 ranges; 610 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 611 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 612 clock-names = "m-ahb", "s-ahb"; 613 iommus = <&apps_smmu 0x5a3 0x0>; 614 #address-cells = <2>; 615 #size-cells = <2>; 616 status = "disabled"; 617 618 i2c14: i2c@880000 { 619 compatible = "qcom,geni-i2c"; 620 reg = <0x0 0x880000 0x0 0x4000>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 625 clock-names = "se"; 626 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 627 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 628 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 629 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 630 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 631 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 632 interconnect-names = "qup-core", 633 "qup-config", 634 "qup-memory"; 635 power-domains = <&rpmhpd SA8775P_CX>; 636 status = "disabled"; 637 }; 638 639 spi14: spi@880000 { 640 compatible = "qcom,geni-spi"; 641 reg = <0x0 0x880000 0x0 0x4000>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 645 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 646 clock-names = "se"; 647 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 648 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 649 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 650 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 651 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 652 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 653 interconnect-names = "qup-core", 654 "qup-config", 655 "qup-memory"; 656 power-domains = <&rpmhpd SA8775P_CX>; 657 status = "disabled"; 658 }; 659 660 i2c15: i2c@884000 { 661 compatible = "qcom,geni-i2c"; 662 reg = <0x0 0x884000 0x0 0x4000>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 667 clock-names = "se"; 668 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 669 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 670 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 671 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 672 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 673 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 674 interconnect-names = "qup-core", 675 "qup-config", 676 "qup-memory"; 677 power-domains = <&rpmhpd SA8775P_CX>; 678 status = "disabled"; 679 }; 680 681 spi15: spi@884000 { 682 compatible = "qcom,geni-spi"; 683 reg = <0x0 0x884000 0x0 0x4000>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 688 clock-names = "se"; 689 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 690 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 691 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 692 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 693 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 694 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 695 interconnect-names = "qup-core", 696 "qup-config", 697 "qup-memory"; 698 power-domains = <&rpmhpd SA8775P_CX>; 699 status = "disabled"; 700 }; 701 702 i2c16: i2c@888000 { 703 compatible = "qcom,geni-i2c"; 704 reg = <0x0 0x888000 0x0 0x4000>; 705 #address-cells = <1>; 706 #size-cells = <0>; 707 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 709 clock-names = "se"; 710 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 711 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 712 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 713 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 714 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 715 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 716 interconnect-names = "qup-core", 717 "qup-config", 718 "qup-memory"; 719 power-domains = <&rpmhpd SA8775P_CX>; 720 status = "disabled"; 721 }; 722 723 spi16: spi@888000 { 724 compatible = "qcom,geni-spi"; 725 reg = <0x0 0x00888000 0x0 0x4000>; 726 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 728 clock-names = "se"; 729 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 730 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 731 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 732 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 733 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 734 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 735 interconnect-names = "qup-core", 736 "qup-config", 737 "qup-memory"; 738 power-domains = <&rpmhpd SA8775P_CX>; 739 #address-cells = <1>; 740 #size-cells = <0>; 741 status = "disabled"; 742 }; 743 744 i2c17: i2c@88c000 { 745 compatible = "qcom,geni-i2c"; 746 reg = <0x0 0x88c000 0x0 0x4000>; 747 #address-cells = <1>; 748 #size-cells = <0>; 749 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 750 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 751 clock-names = "se"; 752 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 753 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 754 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 755 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 756 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 757 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 758 interconnect-names = "qup-core", 759 "qup-config", 760 "qup-memory"; 761 power-domains = <&rpmhpd SA8775P_CX>; 762 status = "disabled"; 763 }; 764 765 spi17: spi@88c000 { 766 compatible = "qcom,geni-spi"; 767 reg = <0x0 0x88c000 0x0 0x4000>; 768 #address-cells = <1>; 769 #size-cells = <0>; 770 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 772 clock-names = "se"; 773 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 774 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 775 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 776 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 777 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 778 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 779 interconnect-names = "qup-core", 780 "qup-config", 781 "qup-memory"; 782 power-domains = <&rpmhpd SA8775P_CX>; 783 status = "disabled"; 784 }; 785 786 uart17: serial@88c000 { 787 compatible = "qcom,geni-uart"; 788 reg = <0x0 0x0088c000 0x0 0x4000>; 789 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 790 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 791 clock-names = "se"; 792 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 793 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 794 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 795 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 796 interconnect-names = "qup-core", "qup-config"; 797 power-domains = <&rpmhpd SA8775P_CX>; 798 status = "disabled"; 799 }; 800 801 i2c18: i2c@890000 { 802 compatible = "qcom,geni-i2c"; 803 reg = <0x0 0x00890000 0x0 0x4000>; 804 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 805 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 806 clock-names = "se"; 807 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 808 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 809 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 810 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 811 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 812 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 813 interconnect-names = "qup-core", 814 "qup-config", 815 "qup-memory"; 816 power-domains = <&rpmhpd SA8775P_CX>; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 status = "disabled"; 820 }; 821 822 spi18: spi@890000 { 823 compatible = "qcom,geni-spi"; 824 reg = <0x0 0x890000 0x0 0x4000>; 825 #address-cells = <1>; 826 #size-cells = <0>; 827 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 829 clock-names = "se"; 830 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 831 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 832 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 833 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 834 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 835 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 836 interconnect-names = "qup-core", 837 "qup-config", 838 "qup-memory"; 839 power-domains = <&rpmhpd SA8775P_CX>; 840 status = "disabled"; 841 }; 842 843 i2c19: i2c@894000 { 844 compatible = "qcom,geni-i2c"; 845 reg = <0x0 0x894000 0x0 0x4000>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 850 clock-names = "se"; 851 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 852 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 853 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 854 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 855 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 856 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 857 interconnect-names = "qup-core", 858 "qup-config", 859 "qup-memory"; 860 power-domains = <&rpmhpd SA8775P_CX>; 861 status = "disabled"; 862 }; 863 864 spi19: spi@894000 { 865 compatible = "qcom,geni-spi"; 866 reg = <0x0 0x894000 0x0 0x4000>; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 871 clock-names = "se"; 872 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 873 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 874 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 875 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 876 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 877 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 878 interconnect-names = "qup-core", 879 "qup-config", 880 "qup-memory"; 881 power-domains = <&rpmhpd SA8775P_CX>; 882 status = "disabled"; 883 }; 884 885 i2c20: i2c@898000 { 886 compatible = "qcom,geni-i2c"; 887 reg = <0x0 0x898000 0x0 0x4000>; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 892 clock-names = "se"; 893 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 894 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 895 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 896 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 897 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 898 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 899 interconnect-names = "qup-core", 900 "qup-config", 901 "qup-memory"; 902 power-domains = <&rpmhpd SA8775P_CX>; 903 status = "disabled"; 904 }; 905 906 spi20: spi@898000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0x0 0x898000 0x0 0x4000>; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 913 clock-names = "se"; 914 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 915 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 916 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 917 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 918 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 919 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 920 interconnect-names = "qup-core", 921 "qup-config", 922 "qup-memory"; 923 power-domains = <&rpmhpd SA8775P_CX>; 924 status = "disabled"; 925 }; 926 }; 927 928 qupv3_id_0: geniqup@9c0000 { 929 compatible = "qcom,geni-se-qup"; 930 reg = <0x0 0x9c0000 0x0 0x6000>; 931 #address-cells = <2>; 932 #size-cells = <2>; 933 ranges; 934 clock-names = "m-ahb", "s-ahb"; 935 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 936 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 937 iommus = <&apps_smmu 0x403 0x0>; 938 status = "disabled"; 939 940 i2c0: i2c@980000 { 941 compatible = "qcom,geni-i2c"; 942 reg = <0x0 0x980000 0x0 0x4000>; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 947 clock-names = "se"; 948 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 949 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 950 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 951 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 952 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 953 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 954 interconnect-names = "qup-core", 955 "qup-config", 956 "qup-memory"; 957 power-domains = <&rpmhpd SA8775P_CX>; 958 status = "disabled"; 959 }; 960 961 spi0: spi@980000 { 962 compatible = "qcom,geni-spi"; 963 reg = <0x0 0x980000 0x0 0x4000>; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 968 clock-names = "se"; 969 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 970 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 971 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 972 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 973 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 974 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 975 interconnect-names = "qup-core", 976 "qup-config", 977 "qup-memory"; 978 power-domains = <&rpmhpd SA8775P_CX>; 979 status = "disabled"; 980 }; 981 982 i2c1: i2c@984000 { 983 compatible = "qcom,geni-i2c"; 984 reg = <0x0 0x984000 0x0 0x4000>; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 989 clock-names = "se"; 990 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 991 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 992 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 993 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 994 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 996 interconnect-names = "qup-core", 997 "qup-config", 998 "qup-memory"; 999 power-domains = <&rpmhpd SA8775P_CX>; 1000 status = "disabled"; 1001 }; 1002 1003 spi1: spi@984000 { 1004 compatible = "qcom,geni-spi"; 1005 reg = <0x0 0x984000 0x0 0x4000>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1010 clock-names = "se"; 1011 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1012 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1013 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1014 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1015 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1016 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1017 interconnect-names = "qup-core", 1018 "qup-config", 1019 "qup-memory"; 1020 power-domains = <&rpmhpd SA8775P_CX>; 1021 status = "disabled"; 1022 }; 1023 1024 i2c2: i2c@988000 { 1025 compatible = "qcom,geni-i2c"; 1026 reg = <0x0 0x988000 0x0 0x4000>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1030 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1031 clock-names = "se"; 1032 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1033 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1034 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1035 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1036 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1037 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1038 interconnect-names = "qup-core", 1039 "qup-config", 1040 "qup-memory"; 1041 power-domains = <&rpmhpd SA8775P_CX>; 1042 status = "disabled"; 1043 }; 1044 1045 spi2: spi@988000 { 1046 compatible = "qcom,geni-spi"; 1047 reg = <0x0 0x988000 0x0 0x4000>; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1052 clock-names = "se"; 1053 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1054 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1055 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1056 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1057 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1058 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1059 interconnect-names = "qup-core", 1060 "qup-config", 1061 "qup-memory"; 1062 power-domains = <&rpmhpd SA8775P_CX>; 1063 status = "disabled"; 1064 }; 1065 1066 i2c3: i2c@98c000 { 1067 compatible = "qcom,geni-i2c"; 1068 reg = <0x0 0x98c000 0x0 0x4000>; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1073 clock-names = "se"; 1074 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1075 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1076 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1077 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1078 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1079 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1080 interconnect-names = "qup-core", 1081 "qup-config", 1082 "qup-memory"; 1083 power-domains = <&rpmhpd SA8775P_CX>; 1084 status = "disabled"; 1085 }; 1086 1087 spi3: spi@98c000 { 1088 compatible = "qcom,geni-spi"; 1089 reg = <0x0 0x98c000 0x0 0x4000>; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1094 clock-names = "se"; 1095 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1096 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1097 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1098 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1099 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1100 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1101 interconnect-names = "qup-core", 1102 "qup-config", 1103 "qup-memory"; 1104 power-domains = <&rpmhpd SA8775P_CX>; 1105 status = "disabled"; 1106 }; 1107 1108 i2c4: i2c@990000 { 1109 compatible = "qcom,geni-i2c"; 1110 reg = <0x0 0x990000 0x0 0x4000>; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1114 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1115 clock-names = "se"; 1116 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1117 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1118 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1119 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1120 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1121 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1122 interconnect-names = "qup-core", 1123 "qup-config", 1124 "qup-memory"; 1125 power-domains = <&rpmhpd SA8775P_CX>; 1126 status = "disabled"; 1127 }; 1128 1129 spi4: spi@990000 { 1130 compatible = "qcom,geni-spi"; 1131 reg = <0x0 0x990000 0x0 0x4000>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1136 clock-names = "se"; 1137 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1138 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1139 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1140 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1141 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1143 interconnect-names = "qup-core", 1144 "qup-config", 1145 "qup-memory"; 1146 power-domains = <&rpmhpd SA8775P_CX>; 1147 status = "disabled"; 1148 }; 1149 1150 i2c5: i2c@994000 { 1151 compatible = "qcom,geni-i2c"; 1152 reg = <0x0 0x994000 0x0 0x4000>; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1156 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1157 clock-names = "se"; 1158 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1159 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1160 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1161 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1162 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1163 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1164 interconnect-names = "qup-core", 1165 "qup-config", 1166 "qup-memory"; 1167 power-domains = <&rpmhpd SA8775P_CX>; 1168 status = "disabled"; 1169 }; 1170 1171 spi5: spi@994000 { 1172 compatible = "qcom,geni-spi"; 1173 reg = <0x0 0x994000 0x0 0x4000>; 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1178 clock-names = "se"; 1179 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1180 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1181 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1182 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1183 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1184 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1185 interconnect-names = "qup-core", 1186 "qup-config", 1187 "qup-memory"; 1188 power-domains = <&rpmhpd SA8775P_CX>; 1189 status = "disabled"; 1190 }; 1191 1192 uart5: serial@994000 { 1193 compatible = "qcom,geni-uart"; 1194 reg = <0x0 0x994000 0x0 0x4000>; 1195 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1196 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1197 clock-names = "se"; 1198 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1199 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1200 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1201 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1202 interconnect-names = "qup-core", "qup-config"; 1203 power-domains = <&rpmhpd SA8775P_CX>; 1204 status = "disabled"; 1205 }; 1206 }; 1207 1208 qupv3_id_1: geniqup@ac0000 { 1209 compatible = "qcom,geni-se-qup"; 1210 reg = <0x0 0x00ac0000 0x0 0x6000>; 1211 #address-cells = <2>; 1212 #size-cells = <2>; 1213 ranges; 1214 clock-names = "m-ahb", "s-ahb"; 1215 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1216 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1217 iommus = <&apps_smmu 0x443 0x0>; 1218 status = "disabled"; 1219 1220 i2c7: i2c@a80000 { 1221 compatible = "qcom,geni-i2c"; 1222 reg = <0x0 0xa80000 0x0 0x4000>; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1226 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1227 clock-names = "se"; 1228 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1229 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1230 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1231 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1232 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1233 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1234 interconnect-names = "qup-core", 1235 "qup-config", 1236 "qup-memory"; 1237 power-domains = <&rpmhpd SA8775P_CX>; 1238 status = "disabled"; 1239 }; 1240 1241 spi7: spi@a80000 { 1242 compatible = "qcom,geni-spi"; 1243 reg = <0x0 0xa80000 0x0 0x4000>; 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1247 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1248 clock-names = "se"; 1249 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1250 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1251 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1252 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1253 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1254 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1255 interconnect-names = "qup-core", 1256 "qup-config", 1257 "qup-memory"; 1258 power-domains = <&rpmhpd SA8775P_CX>; 1259 status = "disabled"; 1260 }; 1261 1262 i2c8: i2c@a84000 { 1263 compatible = "qcom,geni-i2c"; 1264 reg = <0x0 0xa84000 0x0 0x4000>; 1265 #address-cells = <1>; 1266 #size-cells = <0>; 1267 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1268 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1269 clock-names = "se"; 1270 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1271 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1272 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1273 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1274 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1275 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1276 interconnect-names = "qup-core", 1277 "qup-config", 1278 "qup-memory"; 1279 power-domains = <&rpmhpd SA8775P_CX>; 1280 status = "disabled"; 1281 }; 1282 1283 spi8: spi@a84000 { 1284 compatible = "qcom,geni-spi"; 1285 reg = <0x0 0xa84000 0x0 0x4000>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1290 clock-names = "se"; 1291 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1292 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1293 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1294 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1295 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1296 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1297 interconnect-names = "qup-core", 1298 "qup-config", 1299 "qup-memory"; 1300 power-domains = <&rpmhpd SA8775P_CX>; 1301 status = "disabled"; 1302 }; 1303 1304 i2c9: i2c@a88000 { 1305 compatible = "qcom,geni-i2c"; 1306 reg = <0x0 0xa88000 0x0 0x4000>; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1310 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1311 clock-names = "se"; 1312 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1313 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1314 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1315 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1316 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1317 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1318 interconnect-names = "qup-core", 1319 "qup-config", 1320 "qup-memory"; 1321 power-domains = <&rpmhpd SA8775P_CX>; 1322 status = "disabled"; 1323 }; 1324 1325 spi9: spi@a88000 { 1326 compatible = "qcom,geni-spi"; 1327 reg = <0x0 0xa88000 0x0 0x4000>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1331 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1332 clock-names = "se"; 1333 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1334 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1335 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1336 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1337 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1338 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1339 interconnect-names = "qup-core", 1340 "qup-config", 1341 "qup-memory"; 1342 power-domains = <&rpmhpd SA8775P_CX>; 1343 status = "disabled"; 1344 }; 1345 1346 uart9: serial@a88000 { 1347 compatible = "qcom,geni-uart"; 1348 reg = <0x0 0xa88000 0x0 0x4000>; 1349 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1350 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1351 clock-names = "se"; 1352 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1353 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1354 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1355 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1356 interconnect-names = "qup-core", "qup-config"; 1357 power-domains = <&rpmhpd SA8775P_CX>; 1358 status = "disabled"; 1359 }; 1360 1361 i2c10: i2c@a8c000 { 1362 compatible = "qcom,geni-i2c"; 1363 reg = <0x0 0xa8c000 0x0 0x4000>; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1367 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1368 clock-names = "se"; 1369 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1370 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1371 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1372 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1373 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1374 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1375 interconnect-names = "qup-core", 1376 "qup-config", 1377 "qup-memory"; 1378 power-domains = <&rpmhpd SA8775P_CX>; 1379 status = "disabled"; 1380 }; 1381 1382 spi10: spi@a8c000 { 1383 compatible = "qcom,geni-spi"; 1384 reg = <0x0 0xa8c000 0x0 0x4000>; 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1388 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1389 clock-names = "se"; 1390 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1391 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1392 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1393 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1394 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1395 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1396 interconnect-names = "qup-core", 1397 "qup-config", 1398 "qup-memory"; 1399 power-domains = <&rpmhpd SA8775P_CX>; 1400 status = "disabled"; 1401 }; 1402 1403 uart10: serial@a8c000 { 1404 compatible = "qcom,geni-uart"; 1405 reg = <0x0 0x00a8c000 0x0 0x4000>; 1406 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1409 interconnect-names = "qup-core", "qup-config"; 1410 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 1411 &clk_virt SLAVE_QUP_CORE_1 0>, 1412 <&gem_noc MASTER_APPSS_PROC 0 1413 &config_noc SLAVE_QUP_1 0>; 1414 power-domains = <&rpmhpd SA8775P_CX>; 1415 operating-points-v2 = <&qup_opp_table_100mhz>; 1416 status = "disabled"; 1417 }; 1418 1419 i2c11: i2c@a90000 { 1420 compatible = "qcom,geni-i2c"; 1421 reg = <0x0 0xa90000 0x0 0x4000>; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1426 clock-names = "se"; 1427 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1428 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1429 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1430 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1431 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1432 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1433 interconnect-names = "qup-core", 1434 "qup-config", 1435 "qup-memory"; 1436 power-domains = <&rpmhpd SA8775P_CX>; 1437 status = "disabled"; 1438 }; 1439 1440 spi11: spi@a90000 { 1441 compatible = "qcom,geni-spi"; 1442 reg = <0x0 0xa90000 0x0 0x4000>; 1443 #address-cells = <1>; 1444 #size-cells = <0>; 1445 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1446 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1447 clock-names = "se"; 1448 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1449 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1450 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1451 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1452 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1453 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1454 interconnect-names = "qup-core", 1455 "qup-config", 1456 "qup-memory"; 1457 power-domains = <&rpmhpd SA8775P_CX>; 1458 status = "disabled"; 1459 }; 1460 1461 i2c12: i2c@a94000 { 1462 compatible = "qcom,geni-i2c"; 1463 reg = <0x0 0xa94000 0x0 0x4000>; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1467 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1468 clock-names = "se"; 1469 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1470 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1471 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1472 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1473 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1474 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1475 interconnect-names = "qup-core", 1476 "qup-config", 1477 "qup-memory"; 1478 power-domains = <&rpmhpd SA8775P_CX>; 1479 status = "disabled"; 1480 }; 1481 1482 spi12: spi@a94000 { 1483 compatible = "qcom,geni-spi"; 1484 reg = <0x0 0xa94000 0x0 0x4000>; 1485 #address-cells = <1>; 1486 #size-cells = <0>; 1487 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1488 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1489 clock-names = "se"; 1490 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1491 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1492 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1493 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1494 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1495 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1496 interconnect-names = "qup-core", 1497 "qup-config", 1498 "qup-memory"; 1499 power-domains = <&rpmhpd SA8775P_CX>; 1500 status = "disabled"; 1501 }; 1502 1503 uart12: serial@a94000 { 1504 compatible = "qcom,geni-uart"; 1505 reg = <0x0 0x00a94000 0x0 0x4000>; 1506 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1508 clock-names = "se"; 1509 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1510 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1511 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1512 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1513 interconnect-names = "qup-core", "qup-config"; 1514 power-domains = <&rpmhpd SA8775P_CX>; 1515 status = "disabled"; 1516 }; 1517 1518 i2c13: i2c@a98000 { 1519 compatible = "qcom,geni-i2c"; 1520 reg = <0x0 0xa98000 0x0 0x4000>; 1521 #address-cells = <1>; 1522 #size-cells = <0>; 1523 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1524 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1525 clock-names = "se"; 1526 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1527 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1528 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1529 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1530 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1531 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1532 interconnect-names = "qup-core", 1533 "qup-config", 1534 "qup-memory"; 1535 power-domains = <&rpmhpd SA8775P_CX>; 1536 status = "disabled"; 1537 }; 1538 }; 1539 1540 qupv3_id_3: geniqup@bc0000 { 1541 compatible = "qcom,geni-se-qup"; 1542 reg = <0x0 0xbc0000 0x0 0x6000>; 1543 #address-cells = <2>; 1544 #size-cells = <2>; 1545 ranges; 1546 clock-names = "m-ahb", "s-ahb"; 1547 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 1548 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 1549 iommus = <&apps_smmu 0x43 0x0>; 1550 status = "disabled"; 1551 1552 i2c21: i2c@b80000 { 1553 compatible = "qcom,geni-i2c"; 1554 reg = <0x0 0xb80000 0x0 0x4000>; 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 1558 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 1559 clock-names = "se"; 1560 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1561 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1562 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1563 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 1564 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1565 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1566 interconnect-names = "qup-core", 1567 "qup-config", 1568 "qup-memory"; 1569 power-domains = <&rpmhpd SA8775P_CX>; 1570 status = "disabled"; 1571 }; 1572 1573 spi21: spi@b80000 { 1574 compatible = "qcom,geni-spi"; 1575 reg = <0x0 0xb80000 0x0 0x4000>; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 1579 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 1580 clock-names = "se"; 1581 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1582 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1583 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1584 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 1585 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1586 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1587 interconnect-names = "qup-core", 1588 "qup-config", 1589 "qup-memory"; 1590 power-domains = <&rpmhpd SA8775P_CX>; 1591 status = "disabled"; 1592 }; 1593 }; 1594 1595 rng: rng@10d2000 { 1596 compatible = "qcom,sa8775p-trng", "qcom,trng"; 1597 reg = <0 0x010d2000 0 0x1000>; 1598 }; 1599 1600 ufs_mem_hc: ufs@1d84000 { 1601 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1602 reg = <0x0 0x01d84000 0x0 0x3000>; 1603 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1604 phys = <&ufs_mem_phy>; 1605 phy-names = "ufsphy"; 1606 lanes-per-direction = <2>; 1607 #reset-cells = <1>; 1608 resets = <&gcc GCC_UFS_PHY_BCR>; 1609 reset-names = "rst"; 1610 power-domains = <&gcc UFS_PHY_GDSC>; 1611 required-opps = <&rpmhpd_opp_nom>; 1612 iommus = <&apps_smmu 0x100 0x0>; 1613 dma-coherent; 1614 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1615 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1616 <&gcc GCC_UFS_PHY_AHB_CLK>, 1617 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1618 <&rpmhcc RPMH_CXO_CLK>, 1619 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1620 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1621 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1622 clock-names = "core_clk", 1623 "bus_aggr_clk", 1624 "iface_clk", 1625 "core_clk_unipro", 1626 "ref_clk", 1627 "tx_lane0_sync_clk", 1628 "rx_lane0_sync_clk", 1629 "rx_lane1_sync_clk"; 1630 freq-table-hz = <75000000 300000000>, 1631 <0 0>, 1632 <0 0>, 1633 <75000000 300000000>, 1634 <0 0>, 1635 <0 0>, 1636 <0 0>, 1637 <0 0>; 1638 qcom,ice = <&ice>; 1639 status = "disabled"; 1640 }; 1641 1642 ufs_mem_phy: phy@1d87000 { 1643 compatible = "qcom,sa8775p-qmp-ufs-phy"; 1644 reg = <0x0 0x01d87000 0x0 0xe10>; 1645 /* 1646 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 1647 * enables the CXO clock to eDP *and* UFS PHY. 1648 */ 1649 clocks = <&rpmhcc RPMH_CXO_CLK>, 1650 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1651 <&gcc GCC_EDP_REF_CLKREF_EN>; 1652 clock-names = "ref", "ref_aux", "qref"; 1653 power-domains = <&gcc UFS_PHY_GDSC>; 1654 resets = <&ufs_mem_hc 0>; 1655 reset-names = "ufsphy"; 1656 #phy-cells = <0>; 1657 status = "disabled"; 1658 }; 1659 1660 ice: crypto@1d88000 { 1661 compatible = "qcom,sa8775p-inline-crypto-engine", 1662 "qcom,inline-crypto-engine"; 1663 reg = <0x0 0x01d88000 0x0 0x8000>; 1664 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1665 }; 1666 1667 stm: stm@4002000 { 1668 compatible = "arm,coresight-stm", "arm,primecell"; 1669 reg = <0x0 0x4002000 0x0 0x1000>, 1670 <0x0 0x16280000 0x0 0x180000>; 1671 reg-names = "stm-base", "stm-stimulus-base"; 1672 1673 clocks = <&aoss_qmp>; 1674 clock-names = "apb_pclk"; 1675 1676 out-ports { 1677 port { 1678 stm_out: endpoint { 1679 remote-endpoint = 1680 <&funnel0_in7>; 1681 }; 1682 }; 1683 }; 1684 }; 1685 1686 tpdm@4003000 { 1687 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1688 reg = <0x0 0x4003000 0x0 0x1000>; 1689 1690 clocks = <&aoss_qmp>; 1691 clock-names = "apb_pclk"; 1692 1693 qcom,cmb-element-bits = <32>; 1694 qcom,cmb-msrs-num = <32>; 1695 1696 out-ports { 1697 port { 1698 qdss_tpdm0_out: endpoint { 1699 remote-endpoint = 1700 <&qdss_tpda_in0>; 1701 }; 1702 }; 1703 }; 1704 }; 1705 1706 tpda@4004000 { 1707 compatible = "qcom,coresight-tpda", "arm,primecell"; 1708 reg = <0x0 0x4004000 0x0 0x1000>; 1709 1710 clocks = <&aoss_qmp>; 1711 clock-names = "apb_pclk"; 1712 1713 out-ports { 1714 port { 1715 qdss_tpda_out: endpoint { 1716 remote-endpoint = 1717 <&funnel0_in6>; 1718 }; 1719 }; 1720 }; 1721 1722 in-ports { 1723 #address-cells = <1>; 1724 #size-cells = <0>; 1725 1726 port@0 { 1727 reg = <0>; 1728 qdss_tpda_in0: endpoint { 1729 remote-endpoint = 1730 <&qdss_tpdm0_out>; 1731 }; 1732 }; 1733 1734 port@1 { 1735 reg = <1>; 1736 qdss_tpda_in1: endpoint { 1737 remote-endpoint = 1738 <&qdss_tpdm1_out>; 1739 }; 1740 }; 1741 }; 1742 }; 1743 1744 tpdm@400f000 { 1745 compatible = "qcom,coresight-tpdm", "arm,primecell"; 1746 reg = <0x0 0x400f000 0x0 0x1000>; 1747 1748 clocks = <&aoss_qmp>; 1749 clock-names = "apb_pclk"; 1750 1751 qcom,cmb-element-bits = <32>; 1752 qcom,cmb-msrs-num = <32>; 1753 1754 out-ports { 1755 port { 1756 qdss_tpdm1_out: endpoint { 1757 remote-endpoint = 1758 <&qdss_tpda_in1>; 1759 }; 1760 }; 1761 }; 1762 }; 1763 1764 funnel@4041000 { 1765 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1766 reg = <0x0 0x4041000 0x0 0x1000>; 1767 1768 clocks = <&aoss_qmp>; 1769 clock-names = "apb_pclk"; 1770 1771 out-ports { 1772 port { 1773 funnel0_out: endpoint { 1774 remote-endpoint = 1775 <&qdss_funnel_in0>; 1776 }; 1777 }; 1778 }; 1779 1780 in-ports { 1781 #address-cells = <1>; 1782 #size-cells = <0>; 1783 1784 port@6 { 1785 reg = <6>; 1786 funnel0_in6: endpoint { 1787 remote-endpoint = 1788 <&qdss_tpda_out>; 1789 }; 1790 }; 1791 1792 port@7 { 1793 reg = <7>; 1794 funnel0_in7: endpoint { 1795 remote-endpoint = 1796 <&stm_out>; 1797 }; 1798 }; 1799 }; 1800 }; 1801 1802 funnel@4042000 { 1803 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1804 reg = <0x0 0x4042000 0x0 0x1000>; 1805 1806 clocks = <&aoss_qmp>; 1807 clock-names = "apb_pclk"; 1808 1809 out-ports { 1810 port { 1811 funnel1_out: endpoint { 1812 remote-endpoint = 1813 <&qdss_funnel_in1>; 1814 }; 1815 }; 1816 }; 1817 1818 in-ports { 1819 #address-cells = <1>; 1820 #size-cells = <0>; 1821 1822 port@4 { 1823 reg = <4>; 1824 funnel1_in4: endpoint { 1825 remote-endpoint = 1826 <&apss_funnel1_out>; 1827 }; 1828 }; 1829 }; 1830 }; 1831 1832 funnel@4045000 { 1833 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1834 reg = <0x0 0x4045000 0x0 0x1000>; 1835 1836 clocks = <&aoss_qmp>; 1837 clock-names = "apb_pclk"; 1838 1839 out-ports { 1840 port { 1841 qdss_funnel_out: endpoint { 1842 remote-endpoint = 1843 <&aoss_funnel_in7>; 1844 }; 1845 }; 1846 }; 1847 1848 in-ports { 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 1852 port@0 { 1853 reg = <0>; 1854 qdss_funnel_in0: endpoint { 1855 remote-endpoint = 1856 <&funnel0_out>; 1857 }; 1858 }; 1859 1860 port@1 { 1861 reg = <1>; 1862 qdss_funnel_in1: endpoint { 1863 remote-endpoint = 1864 <&funnel1_out>; 1865 }; 1866 }; 1867 }; 1868 }; 1869 1870 funnel@4b04000 { 1871 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1872 reg = <0x0 0x4b04000 0x0 0x1000>; 1873 1874 clocks = <&aoss_qmp>; 1875 clock-names = "apb_pclk"; 1876 1877 out-ports { 1878 port { 1879 aoss_funnel_out: endpoint { 1880 remote-endpoint = 1881 <&etf0_in>; 1882 }; 1883 }; 1884 }; 1885 1886 in-ports { 1887 #address-cells = <1>; 1888 #size-cells = <0>; 1889 1890 port@6 { 1891 reg = <6>; 1892 aoss_funnel_in6: endpoint { 1893 remote-endpoint = 1894 <&aoss_tpda_out>; 1895 }; 1896 }; 1897 1898 port@7 { 1899 reg = <7>; 1900 aoss_funnel_in7: endpoint { 1901 remote-endpoint = 1902 <&qdss_funnel_out>; 1903 }; 1904 }; 1905 }; 1906 }; 1907 1908 tmc_etf: tmc@4b05000 { 1909 compatible = "arm,coresight-tmc", "arm,primecell"; 1910 reg = <0x0 0x4b05000 0x0 0x1000>; 1911 1912 clocks = <&aoss_qmp>; 1913 clock-names = "apb_pclk"; 1914 1915 out-ports { 1916 port { 1917 etf0_out: endpoint { 1918 remote-endpoint = 1919 <&swao_rep_in>; 1920 }; 1921 }; 1922 }; 1923 1924 in-ports { 1925 port { 1926 etf0_in: endpoint { 1927 remote-endpoint = 1928 <&aoss_funnel_out>; 1929 }; 1930 }; 1931 }; 1932 }; 1933 1934 replicator@4b06000 { 1935 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1936 reg = <0x0 0x4b06000 0x0 0x1000>; 1937 1938 clocks = <&aoss_qmp>; 1939 clock-names = "apb_pclk"; 1940 1941 out-ports { 1942 #address-cells = <1>; 1943 #size-cells = <0>; 1944 1945 port@1 { 1946 reg = <1>; 1947 swao_rep_out1: endpoint { 1948 remote-endpoint = 1949 <&eud_in>; 1950 }; 1951 }; 1952 }; 1953 1954 in-ports { 1955 port { 1956 swao_rep_in: endpoint { 1957 remote-endpoint = 1958 <&etf0_out>; 1959 }; 1960 }; 1961 }; 1962 }; 1963 1964 tpda@4b08000 { 1965 compatible = "qcom,coresight-tpda", "arm,primecell"; 1966 reg = <0x0 0x4b08000 0x0 0x1000>; 1967 1968 clocks = <&aoss_qmp>; 1969 clock-names = "apb_pclk"; 1970 1971 out-ports { 1972 port { 1973 aoss_tpda_out: endpoint { 1974 remote-endpoint = 1975 <&aoss_funnel_in6>; 1976 }; 1977 }; 1978 }; 1979 1980 in-ports { 1981 #address-cells = <1>; 1982 #size-cells = <0>; 1983 1984 port@0 { 1985 reg = <0>; 1986 aoss_tpda_in0: endpoint { 1987 remote-endpoint = 1988 <&aoss_tpdm0_out>; 1989 }; 1990 }; 1991 1992 port@1 { 1993 reg = <1>; 1994 aoss_tpda_in1: endpoint { 1995 remote-endpoint = 1996 <&aoss_tpdm1_out>; 1997 }; 1998 }; 1999 2000 port@2 { 2001 reg = <2>; 2002 aoss_tpda_in2: endpoint { 2003 remote-endpoint = 2004 <&aoss_tpdm2_out>; 2005 }; 2006 }; 2007 2008 port@3 { 2009 reg = <3>; 2010 aoss_tpda_in3: endpoint { 2011 remote-endpoint = 2012 <&aoss_tpdm3_out>; 2013 }; 2014 }; 2015 2016 port@4 { 2017 reg = <4>; 2018 aoss_tpda_in4: endpoint { 2019 remote-endpoint = 2020 <&aoss_tpdm4_out>; 2021 }; 2022 }; 2023 }; 2024 }; 2025 2026 tpdm@4b09000 { 2027 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2028 reg = <0x0 0x4b09000 0x0 0x1000>; 2029 2030 clocks = <&aoss_qmp>; 2031 clock-names = "apb_pclk"; 2032 2033 qcom,cmb-element-bits = <64>; 2034 qcom,cmb-msrs-num = <32>; 2035 2036 out-ports { 2037 port { 2038 aoss_tpdm0_out: endpoint { 2039 remote-endpoint = 2040 <&aoss_tpda_in0>; 2041 }; 2042 }; 2043 }; 2044 }; 2045 2046 tpdm@4b0a000 { 2047 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2048 reg = <0x0 0x4b0a000 0x0 0x1000>; 2049 2050 clocks = <&aoss_qmp>; 2051 clock-names = "apb_pclk"; 2052 2053 qcom,cmb-element-bits = <64>; 2054 qcom,cmb-msrs-num = <32>; 2055 2056 out-ports { 2057 port { 2058 aoss_tpdm1_out: endpoint { 2059 remote-endpoint = 2060 <&aoss_tpda_in1>; 2061 }; 2062 }; 2063 }; 2064 }; 2065 2066 tpdm@4b0b000 { 2067 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2068 reg = <0x0 0x4b0b000 0x0 0x1000>; 2069 2070 clocks = <&aoss_qmp>; 2071 clock-names = "apb_pclk"; 2072 2073 qcom,cmb-element-bits = <64>; 2074 qcom,cmb-msrs-num = <32>; 2075 2076 out-ports { 2077 port { 2078 aoss_tpdm2_out: endpoint { 2079 remote-endpoint = 2080 <&aoss_tpda_in2>; 2081 }; 2082 }; 2083 }; 2084 }; 2085 2086 tpdm@4b0c000 { 2087 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2088 reg = <0x0 0x4b0c000 0x0 0x1000>; 2089 2090 clocks = <&aoss_qmp>; 2091 clock-names = "apb_pclk"; 2092 2093 qcom,cmb-element-bits = <64>; 2094 qcom,cmb-msrs-num = <32>; 2095 2096 out-ports { 2097 port { 2098 aoss_tpdm3_out: endpoint { 2099 remote-endpoint = 2100 <&aoss_tpda_in3>; 2101 }; 2102 }; 2103 }; 2104 }; 2105 2106 tpdm@4b0d000 { 2107 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2108 reg = <0x0 0x4b0d000 0x0 0x1000>; 2109 2110 clocks = <&aoss_qmp>; 2111 clock-names = "apb_pclk"; 2112 2113 qcom,dsb-element-bits = <32>; 2114 qcom,dsb-msrs-num = <32>; 2115 2116 out-ports { 2117 port { 2118 aoss_tpdm4_out: endpoint { 2119 remote-endpoint = 2120 <&aoss_tpda_in4>; 2121 }; 2122 }; 2123 }; 2124 }; 2125 2126 aoss_cti: cti@4b13000 { 2127 compatible = "arm,coresight-cti", "arm,primecell"; 2128 reg = <0x0 0x4b13000 0x0 0x1000>; 2129 2130 clocks = <&aoss_qmp>; 2131 clock-names = "apb_pclk"; 2132 }; 2133 2134 etm@6040000 { 2135 compatible = "arm,primecell"; 2136 reg = <0x0 0x6040000 0x0 0x1000>; 2137 cpu = <&CPU0>; 2138 2139 clocks = <&aoss_qmp>; 2140 clock-names = "apb_pclk"; 2141 arm,coresight-loses-context-with-cpu; 2142 qcom,skip-power-up; 2143 2144 out-ports { 2145 port { 2146 etm0_out: endpoint { 2147 remote-endpoint = 2148 <&apss_funnel0_in0>; 2149 }; 2150 }; 2151 }; 2152 }; 2153 2154 etm@6140000 { 2155 compatible = "arm,primecell"; 2156 reg = <0x0 0x6140000 0x0 0x1000>; 2157 cpu = <&CPU1>; 2158 2159 clocks = <&aoss_qmp>; 2160 clock-names = "apb_pclk"; 2161 arm,coresight-loses-context-with-cpu; 2162 qcom,skip-power-up; 2163 2164 out-ports { 2165 port { 2166 etm1_out: endpoint { 2167 remote-endpoint = 2168 <&apss_funnel0_in1>; 2169 }; 2170 }; 2171 }; 2172 }; 2173 2174 etm@6240000 { 2175 compatible = "arm,primecell"; 2176 reg = <0x0 0x6240000 0x0 0x1000>; 2177 cpu = <&CPU2>; 2178 2179 clocks = <&aoss_qmp>; 2180 clock-names = "apb_pclk"; 2181 arm,coresight-loses-context-with-cpu; 2182 qcom,skip-power-up; 2183 2184 out-ports { 2185 port { 2186 etm2_out: endpoint { 2187 remote-endpoint = 2188 <&apss_funnel0_in2>; 2189 }; 2190 }; 2191 }; 2192 }; 2193 2194 etm@6340000 { 2195 compatible = "arm,primecell"; 2196 reg = <0x0 0x6340000 0x0 0x1000>; 2197 cpu = <&CPU3>; 2198 2199 clocks = <&aoss_qmp>; 2200 clock-names = "apb_pclk"; 2201 arm,coresight-loses-context-with-cpu; 2202 qcom,skip-power-up; 2203 2204 out-ports { 2205 port { 2206 etm3_out: endpoint { 2207 remote-endpoint = 2208 <&apss_funnel0_in3>; 2209 }; 2210 }; 2211 }; 2212 }; 2213 2214 etm@6440000 { 2215 compatible = "arm,primecell"; 2216 reg = <0x0 0x6440000 0x0 0x1000>; 2217 cpu = <&CPU4>; 2218 2219 clocks = <&aoss_qmp>; 2220 clock-names = "apb_pclk"; 2221 arm,coresight-loses-context-with-cpu; 2222 qcom,skip-power-up; 2223 2224 out-ports { 2225 port { 2226 etm4_out: endpoint { 2227 remote-endpoint = 2228 <&apss_funnel0_in4>; 2229 }; 2230 }; 2231 }; 2232 }; 2233 2234 etm@6540000 { 2235 compatible = "arm,primecell"; 2236 reg = <0x0 0x6540000 0x0 0x1000>; 2237 cpu = <&CPU5>; 2238 2239 clocks = <&aoss_qmp>; 2240 clock-names = "apb_pclk"; 2241 arm,coresight-loses-context-with-cpu; 2242 qcom,skip-power-up; 2243 2244 out-ports { 2245 port { 2246 etm5_out: endpoint { 2247 remote-endpoint = 2248 <&apss_funnel0_in5>; 2249 }; 2250 }; 2251 }; 2252 }; 2253 2254 etm@6640000 { 2255 compatible = "arm,primecell"; 2256 reg = <0x0 0x6640000 0x0 0x1000>; 2257 cpu = <&CPU6>; 2258 2259 clocks = <&aoss_qmp>; 2260 clock-names = "apb_pclk"; 2261 arm,coresight-loses-context-with-cpu; 2262 qcom,skip-power-up; 2263 2264 out-ports { 2265 port { 2266 etm6_out: endpoint { 2267 remote-endpoint = 2268 <&apss_funnel0_in6>; 2269 }; 2270 }; 2271 }; 2272 }; 2273 2274 etm@6740000 { 2275 compatible = "arm,primecell"; 2276 reg = <0x0 0x6740000 0x0 0x1000>; 2277 cpu = <&CPU7>; 2278 2279 clocks = <&aoss_qmp>; 2280 clock-names = "apb_pclk"; 2281 arm,coresight-loses-context-with-cpu; 2282 qcom,skip-power-up; 2283 2284 out-ports { 2285 port { 2286 etm7_out: endpoint { 2287 remote-endpoint = 2288 <&apss_funnel0_in7>; 2289 }; 2290 }; 2291 }; 2292 }; 2293 2294 funnel@6800000 { 2295 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2296 reg = <0x0 0x6800000 0x0 0x1000>; 2297 2298 clocks = <&aoss_qmp>; 2299 clock-names = "apb_pclk"; 2300 2301 out-ports { 2302 port { 2303 apss_funnel0_out: endpoint { 2304 remote-endpoint = 2305 <&apss_funnel1_in0>; 2306 }; 2307 }; 2308 }; 2309 2310 in-ports { 2311 #address-cells = <1>; 2312 #size-cells = <0>; 2313 2314 port@0 { 2315 reg = <0>; 2316 apss_funnel0_in0: endpoint { 2317 remote-endpoint = 2318 <&etm0_out>; 2319 }; 2320 }; 2321 2322 port@1 { 2323 reg = <1>; 2324 apss_funnel0_in1: endpoint { 2325 remote-endpoint = 2326 <&etm1_out>; 2327 }; 2328 }; 2329 2330 port@2 { 2331 reg = <2>; 2332 apss_funnel0_in2: endpoint { 2333 remote-endpoint = 2334 <&etm2_out>; 2335 }; 2336 }; 2337 2338 port@3 { 2339 reg = <3>; 2340 apss_funnel0_in3: endpoint { 2341 remote-endpoint = 2342 <&etm3_out>; 2343 }; 2344 }; 2345 2346 port@4 { 2347 reg = <4>; 2348 apss_funnel0_in4: endpoint { 2349 remote-endpoint = 2350 <&etm4_out>; 2351 }; 2352 }; 2353 2354 port@5 { 2355 reg = <5>; 2356 apss_funnel0_in5: endpoint { 2357 remote-endpoint = 2358 <&etm5_out>; 2359 }; 2360 }; 2361 2362 port@6 { 2363 reg = <6>; 2364 apss_funnel0_in6: endpoint { 2365 remote-endpoint = 2366 <&etm6_out>; 2367 }; 2368 }; 2369 2370 port@7 { 2371 reg = <7>; 2372 apss_funnel0_in7: endpoint { 2373 remote-endpoint = 2374 <&etm7_out>; 2375 }; 2376 }; 2377 }; 2378 }; 2379 2380 funnel@6810000 { 2381 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2382 reg = <0x0 0x6810000 0x0 0x1000>; 2383 2384 clocks = <&aoss_qmp>; 2385 clock-names = "apb_pclk"; 2386 2387 out-ports { 2388 port { 2389 apss_funnel1_out: endpoint { 2390 remote-endpoint = 2391 <&funnel1_in4>; 2392 }; 2393 }; 2394 }; 2395 2396 in-ports { 2397 #address-cells = <1>; 2398 #size-cells = <0>; 2399 2400 port@0 { 2401 reg = <0>; 2402 apss_funnel1_in0: endpoint { 2403 remote-endpoint = 2404 <&apss_funnel0_out>; 2405 }; 2406 }; 2407 2408 port@3 { 2409 reg = <3>; 2410 apss_funnel1_in3: endpoint { 2411 remote-endpoint = 2412 <&apss_tpda_out>; 2413 }; 2414 }; 2415 }; 2416 }; 2417 2418 tpdm@6860000 { 2419 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2420 reg = <0x0 0x6860000 0x0 0x1000>; 2421 2422 clocks = <&aoss_qmp>; 2423 clock-names = "apb_pclk"; 2424 2425 qcom,cmb-element-bits = <64>; 2426 qcom,cmb-msrs-num = <32>; 2427 2428 out-ports { 2429 port { 2430 apss_tpdm3_out: endpoint { 2431 remote-endpoint = 2432 <&apss_tpda_in3>; 2433 }; 2434 }; 2435 }; 2436 }; 2437 2438 tpdm@6861000 { 2439 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2440 reg = <0x0 0x6861000 0x0 0x1000>; 2441 2442 clocks = <&aoss_qmp>; 2443 clock-names = "apb_pclk"; 2444 2445 qcom,dsb-element-bits = <32>; 2446 qcom,dsb-msrs-num = <32>; 2447 2448 out-ports { 2449 port { 2450 apss_tpdm4_out: endpoint { 2451 remote-endpoint = 2452 <&apss_tpda_in4>; 2453 }; 2454 }; 2455 }; 2456 }; 2457 2458 tpda@6863000 { 2459 compatible = "qcom,coresight-tpda", "arm,primecell"; 2460 reg = <0x0 0x6863000 0x0 0x1000>; 2461 2462 clocks = <&aoss_qmp>; 2463 clock-names = "apb_pclk"; 2464 2465 out-ports { 2466 port { 2467 apss_tpda_out: endpoint { 2468 remote-endpoint = 2469 <&apss_funnel1_in3>; 2470 }; 2471 }; 2472 }; 2473 2474 in-ports { 2475 #address-cells = <1>; 2476 #size-cells = <0>; 2477 2478 port@0 { 2479 reg = <0>; 2480 apss_tpda_in0: endpoint { 2481 remote-endpoint = 2482 <&apss_tpdm0_out>; 2483 }; 2484 }; 2485 2486 port@1 { 2487 reg = <1>; 2488 apss_tpda_in1: endpoint { 2489 remote-endpoint = 2490 <&apss_tpdm1_out>; 2491 }; 2492 }; 2493 2494 port@2 { 2495 reg = <2>; 2496 apss_tpda_in2: endpoint { 2497 remote-endpoint = 2498 <&apss_tpdm2_out>; 2499 }; 2500 }; 2501 2502 port@3 { 2503 reg = <3>; 2504 apss_tpda_in3: endpoint { 2505 remote-endpoint = 2506 <&apss_tpdm3_out>; 2507 }; 2508 }; 2509 2510 port@4 { 2511 reg = <4>; 2512 apss_tpda_in4: endpoint { 2513 remote-endpoint = 2514 <&apss_tpdm4_out>; 2515 }; 2516 }; 2517 }; 2518 }; 2519 2520 tpdm@68a0000 { 2521 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2522 reg = <0x0 0x68a0000 0x0 0x1000>; 2523 2524 clocks = <&aoss_qmp>; 2525 clock-names = "apb_pclk"; 2526 2527 qcom,cmb-element-bits = <32>; 2528 qcom,cmb-msrs-num = <32>; 2529 2530 out-ports { 2531 port { 2532 apss_tpdm0_out: endpoint { 2533 remote-endpoint = 2534 <&apss_tpda_in0>; 2535 }; 2536 }; 2537 }; 2538 }; 2539 2540 tpdm@68b0000 { 2541 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2542 reg = <0x0 0x68b0000 0x0 0x1000>; 2543 2544 clocks = <&aoss_qmp>; 2545 clock-names = "apb_pclk"; 2546 2547 qcom,cmb-element-bits = <32>; 2548 qcom,cmb-msrs-num = <32>; 2549 2550 out-ports { 2551 port { 2552 apss_tpdm1_out: endpoint { 2553 remote-endpoint = 2554 <&apss_tpda_in1>; 2555 }; 2556 }; 2557 }; 2558 }; 2559 2560 tpdm@68c0000 { 2561 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2562 reg = <0x0 0x68c0000 0x0 0x1000>; 2563 2564 clocks = <&aoss_qmp>; 2565 clock-names = "apb_pclk"; 2566 2567 qcom,dsb-element-bits = <32>; 2568 qcom,dsb-msrs-num = <32>; 2569 2570 out-ports { 2571 port { 2572 apss_tpdm2_out: endpoint { 2573 remote-endpoint = 2574 <&apss_tpda_in2>; 2575 }; 2576 }; 2577 }; 2578 }; 2579 2580 usb_0_hsphy: phy@88e4000 { 2581 compatible = "qcom,sa8775p-usb-hs-phy", 2582 "qcom,usb-snps-hs-5nm-phy"; 2583 reg = <0 0x088e4000 0 0x120>; 2584 clocks = <&rpmhcc RPMH_CXO_CLK>; 2585 clock-names = "ref"; 2586 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 2587 2588 #phy-cells = <0>; 2589 2590 status = "disabled"; 2591 }; 2592 2593 usb_0_qmpphy: phy@88e8000 { 2594 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 2595 reg = <0 0x088e8000 0 0x2000>; 2596 2597 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2598 <&gcc GCC_USB_CLKREF_EN>, 2599 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2600 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2601 clock-names = "aux", "ref", "com_aux", "pipe"; 2602 2603 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2604 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 2605 reset-names = "phy", "phy_phy"; 2606 2607 power-domains = <&gcc USB30_PRIM_GDSC>; 2608 2609 #clock-cells = <0>; 2610 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 2611 2612 #phy-cells = <0>; 2613 2614 status = "disabled"; 2615 }; 2616 2617 usb_0: usb@a6f8800 { 2618 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 2619 reg = <0 0x0a6f8800 0 0x400>; 2620 #address-cells = <2>; 2621 #size-cells = <2>; 2622 ranges; 2623 2624 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2625 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2626 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2627 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2628 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2629 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 2630 2631 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2632 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2633 assigned-clock-rates = <19200000>, <200000000>; 2634 2635 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 2636 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2637 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2638 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2639 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 2640 interrupt-names = "pwr_event", 2641 "hs_phy_irq", 2642 "dp_hs_phy_irq", 2643 "dm_hs_phy_irq", 2644 "ss_phy_irq"; 2645 2646 power-domains = <&gcc USB30_PRIM_GDSC>; 2647 required-opps = <&rpmhpd_opp_nom>; 2648 2649 resets = <&gcc GCC_USB30_PRIM_BCR>; 2650 2651 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2652 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2653 interconnect-names = "usb-ddr", "apps-usb"; 2654 2655 wakeup-source; 2656 2657 status = "disabled"; 2658 2659 usb_0_dwc3: usb@a600000 { 2660 compatible = "snps,dwc3"; 2661 reg = <0 0x0a600000 0 0xe000>; 2662 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 2663 iommus = <&apps_smmu 0x080 0x0>; 2664 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 2665 phy-names = "usb2-phy", "usb3-phy"; 2666 }; 2667 }; 2668 2669 usb_1_hsphy: phy@88e6000 { 2670 compatible = "qcom,sa8775p-usb-hs-phy", 2671 "qcom,usb-snps-hs-5nm-phy"; 2672 reg = <0 0x088e6000 0 0x120>; 2673 clocks = <&gcc GCC_USB_CLKREF_EN>; 2674 clock-names = "ref"; 2675 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 2676 2677 #phy-cells = <0>; 2678 2679 status = "disabled"; 2680 }; 2681 2682 usb_1_qmpphy: phy@88ea000 { 2683 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 2684 reg = <0 0x088ea000 0 0x2000>; 2685 2686 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2687 <&gcc GCC_USB_CLKREF_EN>, 2688 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2689 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2690 clock-names = "aux", "ref", "com_aux", "pipe"; 2691 2692 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2693 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2694 reset-names = "phy", "phy_phy"; 2695 2696 power-domains = <&gcc USB30_SEC_GDSC>; 2697 2698 #clock-cells = <0>; 2699 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 2700 2701 #phy-cells = <0>; 2702 2703 status = "disabled"; 2704 }; 2705 2706 usb_1: usb@a8f8800 { 2707 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 2708 reg = <0 0x0a8f8800 0 0x400>; 2709 #address-cells = <2>; 2710 #size-cells = <2>; 2711 ranges; 2712 2713 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2714 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2715 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2716 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2717 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 2718 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 2719 2720 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2721 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2722 assigned-clock-rates = <19200000>, <200000000>; 2723 2724 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 2725 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2726 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2727 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 2728 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 2729 interrupt-names = "pwr_event", 2730 "hs_phy_irq", 2731 "dp_hs_phy_irq", 2732 "dm_hs_phy_irq", 2733 "ss_phy_irq"; 2734 2735 power-domains = <&gcc USB30_SEC_GDSC>; 2736 required-opps = <&rpmhpd_opp_nom>; 2737 2738 resets = <&gcc GCC_USB30_SEC_BCR>; 2739 2740 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2741 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2742 interconnect-names = "usb-ddr", "apps-usb"; 2743 2744 wakeup-source; 2745 2746 status = "disabled"; 2747 2748 usb_1_dwc3: usb@a800000 { 2749 compatible = "snps,dwc3"; 2750 reg = <0 0x0a800000 0 0xe000>; 2751 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 2752 iommus = <&apps_smmu 0x0a0 0x0>; 2753 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 2754 phy-names = "usb2-phy", "usb3-phy"; 2755 }; 2756 }; 2757 2758 usb_2_hsphy: phy@88e7000 { 2759 compatible = "qcom,sa8775p-usb-hs-phy", 2760 "qcom,usb-snps-hs-5nm-phy"; 2761 reg = <0 0x088e7000 0 0x120>; 2762 clocks = <&gcc GCC_USB_CLKREF_EN>; 2763 clock-names = "ref"; 2764 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 2765 2766 #phy-cells = <0>; 2767 2768 status = "disabled"; 2769 }; 2770 2771 usb_2: usb@a4f8800 { 2772 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 2773 reg = <0 0x0a4f8800 0 0x400>; 2774 #address-cells = <2>; 2775 #size-cells = <2>; 2776 ranges; 2777 2778 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 2779 <&gcc GCC_USB20_MASTER_CLK>, 2780 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 2781 <&gcc GCC_USB20_SLEEP_CLK>, 2782 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 2783 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 2784 2785 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 2786 <&gcc GCC_USB20_MASTER_CLK>; 2787 assigned-clock-rates = <19200000>, <200000000>; 2788 2789 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 2790 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 2791 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 2792 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 2793 interrupt-names = "pwr_event", 2794 "hs_phy_irq", 2795 "dp_hs_phy_irq", 2796 "dm_hs_phy_irq"; 2797 2798 power-domains = <&gcc USB20_PRIM_GDSC>; 2799 required-opps = <&rpmhpd_opp_nom>; 2800 2801 resets = <&gcc GCC_USB20_PRIM_BCR>; 2802 2803 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 2804 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 2805 interconnect-names = "usb-ddr", "apps-usb"; 2806 2807 wakeup-source; 2808 2809 status = "disabled"; 2810 2811 usb_2_dwc3: usb@a400000 { 2812 compatible = "snps,dwc3"; 2813 reg = <0 0x0a400000 0 0xe000>; 2814 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 2815 iommus = <&apps_smmu 0x020 0x0>; 2816 phys = <&usb_2_hsphy>; 2817 phy-names = "usb2-phy"; 2818 }; 2819 }; 2820 2821 tcsr_mutex: hwlock@1f40000 { 2822 compatible = "qcom,tcsr-mutex"; 2823 reg = <0x0 0x01f40000 0x0 0x20000>; 2824 #hwlock-cells = <1>; 2825 }; 2826 2827 gpucc: clock-controller@3d90000 { 2828 compatible = "qcom,sa8775p-gpucc"; 2829 reg = <0x0 0x03d90000 0x0 0xa000>; 2830 clocks = <&rpmhcc RPMH_CXO_CLK>, 2831 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2832 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2833 clock-names = "bi_tcxo", 2834 "gcc_gpu_gpll0_clk_src", 2835 "gcc_gpu_gpll0_div_clk_src"; 2836 #clock-cells = <1>; 2837 #reset-cells = <1>; 2838 #power-domain-cells = <1>; 2839 }; 2840 2841 adreno_smmu: iommu@3da0000 { 2842 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 2843 "qcom,smmu-500", "arm,mmu-500"; 2844 reg = <0x0 0x03da0000 0x0 0x20000>; 2845 #iommu-cells = <2>; 2846 #global-interrupts = <2>; 2847 dma-coherent; 2848 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2849 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2850 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2851 <&gpucc GPU_CC_AHB_CLK>, 2852 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2853 <&gpucc GPU_CC_CX_GMU_CLK>, 2854 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2855 <&gpucc GPU_CC_HUB_AON_CLK>; 2856 clock-names = "gcc_gpu_memnoc_gfx_clk", 2857 "gcc_gpu_snoc_dvm_gfx_clk", 2858 "gpu_cc_ahb_clk", 2859 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2860 "gpu_cc_cx_gmu_clk", 2861 "gpu_cc_hub_cx_int_clk", 2862 "gpu_cc_hub_aon_clk"; 2863 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2864 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2865 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2866 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2867 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2868 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2869 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2870 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2871 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2872 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2873 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2874 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2875 }; 2876 2877 serdes0: phy@8901000 { 2878 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 2879 reg = <0x0 0x08901000 0x0 0xe10>; 2880 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 2881 clock-names = "sgmi_ref"; 2882 #phy-cells = <0>; 2883 status = "disabled"; 2884 }; 2885 2886 serdes1: phy@8902000 { 2887 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 2888 reg = <0x0 0x08902000 0x0 0xe10>; 2889 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 2890 clock-names = "sgmi_ref"; 2891 #phy-cells = <0>; 2892 status = "disabled"; 2893 }; 2894 2895 llcc: system-cache-controller@9200000 { 2896 compatible = "qcom,sa8775p-llcc"; 2897 reg = <0x0 0x09200000 0x0 0x80000>, 2898 <0x0 0x09300000 0x0 0x80000>, 2899 <0x0 0x09400000 0x0 0x80000>, 2900 <0x0 0x09500000 0x0 0x80000>, 2901 <0x0 0x09600000 0x0 0x80000>, 2902 <0x0 0x09700000 0x0 0x80000>, 2903 <0x0 0x09a00000 0x0 0x80000>; 2904 reg-names = "llcc0_base", 2905 "llcc1_base", 2906 "llcc2_base", 2907 "llcc3_base", 2908 "llcc4_base", 2909 "llcc5_base", 2910 "llcc_broadcast_base"; 2911 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 2912 }; 2913 2914 pdc: interrupt-controller@b220000 { 2915 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 2916 reg = <0x0 0x0b220000 0x0 0x30000>, 2917 <0x0 0x17c000f0 0x0 0x64>; 2918 qcom,pdc-ranges = <0 480 40>, 2919 <40 140 14>, 2920 <54 263 1>, 2921 <55 306 4>, 2922 <59 312 3>, 2923 <62 374 2>, 2924 <64 434 2>, 2925 <66 438 2>, 2926 <70 520 1>, 2927 <73 523 1>, 2928 <118 568 6>, 2929 <124 609 3>, 2930 <159 638 1>, 2931 <160 720 3>, 2932 <169 728 30>, 2933 <199 416 2>, 2934 <201 449 1>, 2935 <202 89 1>, 2936 <203 451 1>, 2937 <204 462 1>, 2938 <205 264 1>, 2939 <206 579 1>, 2940 <207 653 1>, 2941 <208 656 1>, 2942 <209 659 1>, 2943 <210 122 1>, 2944 <211 699 1>, 2945 <212 705 1>, 2946 <213 450 1>, 2947 <214 643 2>, 2948 <216 646 5>, 2949 <221 390 5>, 2950 <226 700 2>, 2951 <228 440 1>, 2952 <229 663 1>, 2953 <230 524 2>, 2954 <232 612 3>, 2955 <235 723 5>; 2956 #interrupt-cells = <2>; 2957 interrupt-parent = <&intc>; 2958 interrupt-controller; 2959 }; 2960 2961 tsens2: thermal-sensor@c251000 { 2962 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 2963 reg = <0x0 0x0c251000 0x0 0x1ff>, 2964 <0x0 0x0c224000 0x0 0x8>; 2965 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 2966 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 2967 #qcom,sensors = <13>; 2968 interrupt-names = "uplow", "critical"; 2969 #thermal-sensor-cells = <1>; 2970 }; 2971 2972 tsens3: thermal-sensor@c252000 { 2973 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 2974 reg = <0x0 0x0c252000 0x0 0x1ff>, 2975 <0x0 0x0c225000 0x0 0x8>; 2976 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 2977 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 2978 #qcom,sensors = <13>; 2979 interrupt-names = "uplow", "critical"; 2980 #thermal-sensor-cells = <1>; 2981 }; 2982 2983 tsens0: thermal-sensor@c263000 { 2984 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 2985 reg = <0x0 0x0c263000 0x0 0x1ff>, 2986 <0x0 0x0c222000 0x0 0x8>; 2987 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2988 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2989 #qcom,sensors = <12>; 2990 interrupt-names = "uplow", "critical"; 2991 #thermal-sensor-cells = <1>; 2992 }; 2993 2994 tsens1: thermal-sensor@c265000 { 2995 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 2996 reg = <0x0 0x0c265000 0x0 0x1ff>, 2997 <0x0 0x0c223000 0x0 0x8>; 2998 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2999 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3000 #qcom,sensors = <12>; 3001 interrupt-names = "uplow", "critical"; 3002 #thermal-sensor-cells = <1>; 3003 }; 3004 3005 aoss_qmp: power-management@c300000 { 3006 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 3007 reg = <0x0 0x0c300000 0x0 0x400>; 3008 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 3009 IPCC_MPROC_SIGNAL_GLINK_QMP 3010 IRQ_TYPE_EDGE_RISING>; 3011 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3012 #clock-cells = <0>; 3013 }; 3014 3015 sram@c3f0000 { 3016 compatible = "qcom,rpmh-stats"; 3017 reg = <0x0 0x0c3f0000 0x0 0x400>; 3018 }; 3019 3020 spmi_bus: spmi@c440000 { 3021 compatible = "qcom,spmi-pmic-arb"; 3022 reg = <0x0 0x0c440000 0x0 0x1100>, 3023 <0x0 0x0c600000 0x0 0x2000000>, 3024 <0x0 0x0e600000 0x0 0x100000>, 3025 <0x0 0x0e700000 0x0 0xa0000>, 3026 <0x0 0x0c40a000 0x0 0x26000>; 3027 reg-names = "core", 3028 "chnls", 3029 "obsrvr", 3030 "intr", 3031 "cnfg"; 3032 qcom,channel = <0>; 3033 qcom,ee = <0>; 3034 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3035 interrupt-names = "periph_irq"; 3036 interrupt-controller; 3037 #interrupt-cells = <4>; 3038 #address-cells = <2>; 3039 #size-cells = <0>; 3040 }; 3041 3042 tlmm: pinctrl@f000000 { 3043 compatible = "qcom,sa8775p-tlmm"; 3044 reg = <0x0 0x0f000000 0x0 0x1000000>; 3045 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3046 gpio-controller; 3047 #gpio-cells = <2>; 3048 interrupt-controller; 3049 #interrupt-cells = <2>; 3050 gpio-ranges = <&tlmm 0 0 149>; 3051 wakeup-parent = <&pdc>; 3052 }; 3053 3054 sram: sram@146d8000 { 3055 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; 3056 reg = <0x0 0x146d8000 0x0 0x1000>; 3057 ranges = <0x0 0x0 0x146d8000 0x1000>; 3058 3059 #address-cells = <1>; 3060 #size-cells = <1>; 3061 3062 pil-reloc@94c { 3063 compatible = "qcom,pil-reloc-info"; 3064 reg = <0x94c 0xc8>; 3065 }; 3066 }; 3067 3068 apps_smmu: iommu@15000000 { 3069 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3070 reg = <0x0 0x15000000 0x0 0x100000>; 3071 #iommu-cells = <2>; 3072 #global-interrupts = <2>; 3073 3074 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 3076 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3077 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3078 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3089 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3091 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3092 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3095 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3097 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3098 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3099 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3100 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3101 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3165 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3166 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3167 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3171 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 3195 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 3196 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 3199 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 3201 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 3202 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 3203 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 3204 }; 3205 3206 pcie_smmu: iommu@15200000 { 3207 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3208 reg = <0x0 0x15200000 0x0 0x80000>; 3209 #iommu-cells = <2>; 3210 #global-interrupts = <2>; 3211 3212 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 3213 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 3214 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 3215 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 3216 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 3217 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 3218 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 3219 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 3220 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 3221 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 3222 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 3223 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 3224 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 3225 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 3226 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 3227 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 3228 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 3229 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 3230 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 3231 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 3232 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 3238 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 3239 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 3278 }; 3279 3280 intc: interrupt-controller@17a00000 { 3281 compatible = "arm,gic-v3"; 3282 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3283 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3284 interrupt-controller; 3285 #interrupt-cells = <3>; 3286 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3287 #redistributor-regions = <1>; 3288 redistributor-stride = <0x0 0x20000>; 3289 }; 3290 3291 watchdog@17c10000 { 3292 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 3293 reg = <0x0 0x17c10000 0x0 0x1000>; 3294 clocks = <&sleep_clk>; 3295 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 3296 }; 3297 3298 memtimer: timer@17c20000 { 3299 compatible = "arm,armv7-timer-mem"; 3300 reg = <0x0 0x17c20000 0x0 0x1000>; 3301 ranges = <0x0 0x0 0x0 0x20000000>; 3302 #address-cells = <1>; 3303 #size-cells = <1>; 3304 3305 frame@17c21000 { 3306 reg = <0x17c21000 0x1000>, 3307 <0x17c22000 0x1000>; 3308 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3310 frame-number = <0>; 3311 }; 3312 3313 frame@17c23000 { 3314 reg = <0x17c23000 0x1000>; 3315 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3316 frame-number = <1>; 3317 status = "disabled"; 3318 }; 3319 3320 frame@17c25000 { 3321 reg = <0x17c25000 0x1000>; 3322 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3323 frame-number = <2>; 3324 status = "disabled"; 3325 }; 3326 3327 frame@17c27000 { 3328 reg = <0x17c27000 0x1000>; 3329 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3330 frame-number = <3>; 3331 status = "disabled"; 3332 }; 3333 3334 frame@17c29000 { 3335 reg = <0x17c29000 0x1000>; 3336 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3337 frame-number = <4>; 3338 status = "disabled"; 3339 }; 3340 3341 frame@17c2b000 { 3342 reg = <0x17c2b000 0x1000>; 3343 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3344 frame-number = <5>; 3345 status = "disabled"; 3346 }; 3347 3348 frame@17c2d000 { 3349 reg = <0x17c2d000 0x1000>; 3350 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3351 frame-number = <6>; 3352 status = "disabled"; 3353 }; 3354 }; 3355 3356 apps_rsc: rsc@18200000 { 3357 compatible = "qcom,rpmh-rsc"; 3358 reg = <0x0 0x18200000 0x0 0x10000>, 3359 <0x0 0x18210000 0x0 0x10000>, 3360 <0x0 0x18220000 0x0 0x10000>; 3361 reg-names = "drv-0", "drv-1", "drv-2"; 3362 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3365 qcom,tcs-offset = <0xd00>; 3366 qcom,drv-id = <2>; 3367 qcom,tcs-config = <ACTIVE_TCS 2>, 3368 <SLEEP_TCS 3>, 3369 <WAKE_TCS 3>, 3370 <CONTROL_TCS 0>; 3371 label = "apps_rsc"; 3372 3373 apps_bcm_voter: bcm-voter { 3374 compatible = "qcom,bcm-voter"; 3375 }; 3376 3377 rpmhcc: clock-controller { 3378 compatible = "qcom,sa8775p-rpmh-clk"; 3379 #clock-cells = <1>; 3380 clock-names = "xo"; 3381 clocks = <&xo_board_clk>; 3382 }; 3383 3384 rpmhpd: power-controller { 3385 compatible = "qcom,sa8775p-rpmhpd"; 3386 #power-domain-cells = <1>; 3387 operating-points-v2 = <&rpmhpd_opp_table>; 3388 3389 rpmhpd_opp_table: opp-table { 3390 compatible = "operating-points-v2"; 3391 3392 rpmhpd_opp_ret: opp-0 { 3393 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3394 }; 3395 3396 rpmhpd_opp_min_svs: opp-1 { 3397 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3398 }; 3399 3400 rpmhpd_opp_low_svs: opp2 { 3401 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3402 }; 3403 3404 rpmhpd_opp_svs: opp3 { 3405 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3406 }; 3407 3408 rpmhpd_opp_svs_l1: opp-4 { 3409 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3410 }; 3411 3412 rpmhpd_opp_nom: opp-5 { 3413 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3414 }; 3415 3416 rpmhpd_opp_nom_l1: opp-6 { 3417 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3418 }; 3419 3420 rpmhpd_opp_nom_l2: opp-7 { 3421 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3422 }; 3423 3424 rpmhpd_opp_turbo: opp-8 { 3425 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3426 }; 3427 3428 rpmhpd_opp_turbo_l1: opp-9 { 3429 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3430 }; 3431 }; 3432 }; 3433 }; 3434 3435 cpufreq_hw: cpufreq@18591000 { 3436 compatible = "qcom,sa8775p-cpufreq-epss", 3437 "qcom,cpufreq-epss"; 3438 reg = <0x0 0x18591000 0x0 0x1000>, 3439 <0x0 0x18593000 0x0 0x1000>; 3440 reg-names = "freq-domain0", "freq-domain1"; 3441 3442 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3443 clock-names = "xo", "alternate"; 3444 3445 #freq-domain-cells = <1>; 3446 }; 3447 3448 ethernet1: ethernet@23000000 { 3449 compatible = "qcom,sa8775p-ethqos"; 3450 reg = <0x0 0x23000000 0x0 0x10000>, 3451 <0x0 0x23016000 0x0 0x100>; 3452 reg-names = "stmmaceth", "rgmii"; 3453 3454 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 3456 interrupt-names = "macirq", "sfty"; 3457 3458 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 3459 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 3460 <&gcc GCC_EMAC1_PTP_CLK>, 3461 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 3462 clock-names = "stmmaceth", 3463 "pclk", 3464 "ptp_ref", 3465 "phyaux"; 3466 3467 power-domains = <&gcc EMAC1_GDSC>; 3468 3469 phys = <&serdes1>; 3470 phy-names = "serdes"; 3471 3472 iommus = <&apps_smmu 0x140 0xf>; 3473 dma-coherent; 3474 3475 snps,tso; 3476 snps,pbl = <32>; 3477 rx-fifo-depth = <16384>; 3478 tx-fifo-depth = <16384>; 3479 3480 status = "disabled"; 3481 }; 3482 3483 ethernet0: ethernet@23040000 { 3484 compatible = "qcom,sa8775p-ethqos"; 3485 reg = <0x0 0x23040000 0x0 0x10000>, 3486 <0x0 0x23056000 0x0 0x100>; 3487 reg-names = "stmmaceth", "rgmii"; 3488 3489 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; 3491 interrupt-names = "macirq", "sfty"; 3492 3493 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 3494 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 3495 <&gcc GCC_EMAC0_PTP_CLK>, 3496 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 3497 clock-names = "stmmaceth", 3498 "pclk", 3499 "ptp_ref", 3500 "phyaux"; 3501 3502 power-domains = <&gcc EMAC0_GDSC>; 3503 3504 phys = <&serdes0>; 3505 phy-names = "serdes"; 3506 3507 iommus = <&apps_smmu 0x120 0xf>; 3508 dma-coherent; 3509 3510 snps,tso; 3511 snps,pbl = <32>; 3512 rx-fifo-depth = <16384>; 3513 tx-fifo-depth = <16384>; 3514 3515 status = "disabled"; 3516 }; 3517 }; 3518 3519 thermal-zones { 3520 aoss-0-thermal { 3521 thermal-sensors = <&tsens0 0>; 3522 3523 trips { 3524 trip-point0 { 3525 temperature = <105000>; 3526 hysteresis = <5000>; 3527 type = "passive"; 3528 }; 3529 3530 trip-point1 { 3531 temperature = <115000>; 3532 hysteresis = <5000>; 3533 type = "passive"; 3534 }; 3535 }; 3536 }; 3537 3538 cpu-0-0-0-thermal { 3539 polling-delay-passive = <10>; 3540 3541 thermal-sensors = <&tsens0 1>; 3542 3543 trips { 3544 trip-point0 { 3545 temperature = <105000>; 3546 hysteresis = <5000>; 3547 type = "passive"; 3548 }; 3549 3550 trip-point1 { 3551 temperature = <115000>; 3552 hysteresis = <5000>; 3553 type = "passive"; 3554 }; 3555 }; 3556 }; 3557 3558 cpu-0-1-0-thermal { 3559 polling-delay-passive = <10>; 3560 3561 thermal-sensors = <&tsens0 2>; 3562 3563 trips { 3564 trip-point0 { 3565 temperature = <105000>; 3566 hysteresis = <5000>; 3567 type = "passive"; 3568 }; 3569 3570 trip-point1 { 3571 temperature = <115000>; 3572 hysteresis = <5000>; 3573 type = "passive"; 3574 }; 3575 }; 3576 }; 3577 3578 cpu-0-2-0-thermal { 3579 polling-delay-passive = <10>; 3580 3581 thermal-sensors = <&tsens0 3>; 3582 3583 trips { 3584 trip-point0 { 3585 temperature = <105000>; 3586 hysteresis = <5000>; 3587 type = "passive"; 3588 }; 3589 3590 trip-point1 { 3591 temperature = <115000>; 3592 hysteresis = <5000>; 3593 type = "passive"; 3594 }; 3595 }; 3596 }; 3597 3598 cpu-0-3-0-thermal { 3599 polling-delay-passive = <10>; 3600 3601 thermal-sensors = <&tsens0 4>; 3602 3603 trips { 3604 trip-point0 { 3605 temperature = <105000>; 3606 hysteresis = <5000>; 3607 type = "passive"; 3608 }; 3609 3610 trip-point1 { 3611 temperature = <115000>; 3612 hysteresis = <5000>; 3613 type = "passive"; 3614 }; 3615 }; 3616 }; 3617 3618 gpuss-0-thermal { 3619 polling-delay-passive = <10>; 3620 3621 thermal-sensors = <&tsens0 5>; 3622 3623 trips { 3624 trip-point0 { 3625 temperature = <105000>; 3626 hysteresis = <5000>; 3627 type = "passive"; 3628 }; 3629 3630 trip-point1 { 3631 temperature = <115000>; 3632 hysteresis = <5000>; 3633 type = "passive"; 3634 }; 3635 }; 3636 }; 3637 3638 gpuss-1-thermal { 3639 polling-delay-passive = <10>; 3640 3641 thermal-sensors = <&tsens0 6>; 3642 3643 trips { 3644 trip-point0 { 3645 temperature = <105000>; 3646 hysteresis = <5000>; 3647 type = "passive"; 3648 }; 3649 3650 trip-point1 { 3651 temperature = <115000>; 3652 hysteresis = <5000>; 3653 type = "passive"; 3654 }; 3655 }; 3656 }; 3657 3658 gpuss-2-thermal { 3659 polling-delay-passive = <10>; 3660 3661 thermal-sensors = <&tsens0 7>; 3662 3663 trips { 3664 trip-point0 { 3665 temperature = <105000>; 3666 hysteresis = <5000>; 3667 type = "passive"; 3668 }; 3669 3670 trip-point1 { 3671 temperature = <115000>; 3672 hysteresis = <5000>; 3673 type = "passive"; 3674 }; 3675 }; 3676 }; 3677 3678 audio-thermal { 3679 thermal-sensors = <&tsens0 8>; 3680 3681 trips { 3682 trip-point0 { 3683 temperature = <105000>; 3684 hysteresis = <5000>; 3685 type = "passive"; 3686 }; 3687 3688 trip-point1 { 3689 temperature = <115000>; 3690 hysteresis = <5000>; 3691 type = "passive"; 3692 }; 3693 }; 3694 }; 3695 3696 camss-0-thermal { 3697 thermal-sensors = <&tsens0 9>; 3698 3699 trips { 3700 trip-point0 { 3701 temperature = <105000>; 3702 hysteresis = <5000>; 3703 type = "passive"; 3704 }; 3705 3706 trip-point1 { 3707 temperature = <115000>; 3708 hysteresis = <5000>; 3709 type = "passive"; 3710 }; 3711 }; 3712 }; 3713 3714 pcie-0-thermal { 3715 thermal-sensors = <&tsens0 10>; 3716 3717 trips { 3718 trip-point0 { 3719 temperature = <105000>; 3720 hysteresis = <5000>; 3721 type = "passive"; 3722 }; 3723 3724 trip-point1 { 3725 temperature = <115000>; 3726 hysteresis = <5000>; 3727 type = "passive"; 3728 }; 3729 }; 3730 }; 3731 3732 cpuss-0-0-thermal { 3733 thermal-sensors = <&tsens0 11>; 3734 3735 trips { 3736 trip-point0 { 3737 temperature = <105000>; 3738 hysteresis = <5000>; 3739 type = "passive"; 3740 }; 3741 3742 trip-point1 { 3743 temperature = <115000>; 3744 hysteresis = <5000>; 3745 type = "passive"; 3746 }; 3747 }; 3748 }; 3749 3750 aoss-1-thermal { 3751 thermal-sensors = <&tsens1 0>; 3752 3753 trips { 3754 trip-point0 { 3755 temperature = <105000>; 3756 hysteresis = <5000>; 3757 type = "passive"; 3758 }; 3759 3760 trip-point1 { 3761 temperature = <115000>; 3762 hysteresis = <5000>; 3763 type = "passive"; 3764 }; 3765 }; 3766 }; 3767 3768 cpu-0-0-1-thermal { 3769 polling-delay-passive = <10>; 3770 3771 thermal-sensors = <&tsens1 1>; 3772 3773 trips { 3774 trip-point0 { 3775 temperature = <105000>; 3776 hysteresis = <5000>; 3777 type = "passive"; 3778 }; 3779 3780 trip-point1 { 3781 temperature = <115000>; 3782 hysteresis = <5000>; 3783 type = "passive"; 3784 }; 3785 }; 3786 }; 3787 3788 cpu-0-1-1-thermal { 3789 polling-delay-passive = <10>; 3790 3791 thermal-sensors = <&tsens1 2>; 3792 3793 trips { 3794 trip-point0 { 3795 temperature = <105000>; 3796 hysteresis = <5000>; 3797 type = "passive"; 3798 }; 3799 3800 trip-point1 { 3801 temperature = <115000>; 3802 hysteresis = <5000>; 3803 type = "passive"; 3804 }; 3805 }; 3806 }; 3807 3808 cpu-0-2-1-thermal { 3809 polling-delay-passive = <10>; 3810 3811 thermal-sensors = <&tsens1 3>; 3812 3813 trips { 3814 trip-point0 { 3815 temperature = <105000>; 3816 hysteresis = <5000>; 3817 type = "passive"; 3818 }; 3819 3820 trip-point1 { 3821 temperature = <115000>; 3822 hysteresis = <5000>; 3823 type = "passive"; 3824 }; 3825 }; 3826 }; 3827 3828 cpu-0-3-1-thermal { 3829 polling-delay-passive = <10>; 3830 3831 thermal-sensors = <&tsens1 4>; 3832 3833 trips { 3834 trip-point0 { 3835 temperature = <105000>; 3836 hysteresis = <5000>; 3837 type = "passive"; 3838 }; 3839 3840 trip-point1 { 3841 temperature = <115000>; 3842 hysteresis = <5000>; 3843 type = "passive"; 3844 }; 3845 }; 3846 }; 3847 3848 gpuss-3-thermal { 3849 polling-delay-passive = <10>; 3850 3851 thermal-sensors = <&tsens1 5>; 3852 3853 trips { 3854 trip-point0 { 3855 temperature = <105000>; 3856 hysteresis = <5000>; 3857 type = "passive"; 3858 }; 3859 3860 trip-point1 { 3861 temperature = <115000>; 3862 hysteresis = <5000>; 3863 type = "passive"; 3864 }; 3865 }; 3866 }; 3867 3868 gpuss-4-thermal { 3869 polling-delay-passive = <10>; 3870 3871 thermal-sensors = <&tsens1 6>; 3872 3873 trips { 3874 trip-point0 { 3875 temperature = <105000>; 3876 hysteresis = <5000>; 3877 type = "passive"; 3878 }; 3879 3880 trip-point1 { 3881 temperature = <115000>; 3882 hysteresis = <5000>; 3883 type = "passive"; 3884 }; 3885 }; 3886 }; 3887 3888 gpuss-5-thermal { 3889 polling-delay-passive = <10>; 3890 3891 thermal-sensors = <&tsens1 7>; 3892 3893 trips { 3894 trip-point0 { 3895 temperature = <105000>; 3896 hysteresis = <5000>; 3897 type = "passive"; 3898 }; 3899 3900 trip-point1 { 3901 temperature = <115000>; 3902 hysteresis = <5000>; 3903 type = "passive"; 3904 }; 3905 }; 3906 }; 3907 3908 video-thermal { 3909 thermal-sensors = <&tsens1 8>; 3910 3911 trips { 3912 trip-point0 { 3913 temperature = <105000>; 3914 hysteresis = <5000>; 3915 type = "passive"; 3916 }; 3917 3918 trip-point1 { 3919 temperature = <115000>; 3920 hysteresis = <5000>; 3921 type = "passive"; 3922 }; 3923 }; 3924 }; 3925 3926 camss-1-thermal { 3927 thermal-sensors = <&tsens1 9>; 3928 3929 trips { 3930 trip-point0 { 3931 temperature = <105000>; 3932 hysteresis = <5000>; 3933 type = "passive"; 3934 }; 3935 3936 trip-point1 { 3937 temperature = <115000>; 3938 hysteresis = <5000>; 3939 type = "passive"; 3940 }; 3941 }; 3942 }; 3943 3944 pcie-1-thermal { 3945 thermal-sensors = <&tsens1 10>; 3946 3947 trips { 3948 trip-point0 { 3949 temperature = <105000>; 3950 hysteresis = <5000>; 3951 type = "passive"; 3952 }; 3953 3954 trip-point1 { 3955 temperature = <115000>; 3956 hysteresis = <5000>; 3957 type = "passive"; 3958 }; 3959 }; 3960 }; 3961 3962 cpuss-0-1-thermal { 3963 thermal-sensors = <&tsens1 11>; 3964 3965 trips { 3966 trip-point0 { 3967 temperature = <105000>; 3968 hysteresis = <5000>; 3969 type = "passive"; 3970 }; 3971 3972 trip-point1 { 3973 temperature = <115000>; 3974 hysteresis = <5000>; 3975 type = "passive"; 3976 }; 3977 }; 3978 }; 3979 3980 aoss-2-thermal { 3981 thermal-sensors = <&tsens2 0>; 3982 3983 trips { 3984 trip-point0 { 3985 temperature = <105000>; 3986 hysteresis = <5000>; 3987 type = "passive"; 3988 }; 3989 3990 trip-point1 { 3991 temperature = <115000>; 3992 hysteresis = <5000>; 3993 type = "passive"; 3994 }; 3995 }; 3996 }; 3997 3998 cpu-1-0-0-thermal { 3999 polling-delay-passive = <10>; 4000 4001 thermal-sensors = <&tsens2 1>; 4002 4003 trips { 4004 trip-point0 { 4005 temperature = <105000>; 4006 hysteresis = <5000>; 4007 type = "passive"; 4008 }; 4009 4010 trip-point1 { 4011 temperature = <115000>; 4012 hysteresis = <5000>; 4013 type = "passive"; 4014 }; 4015 }; 4016 }; 4017 4018 cpu-1-1-0-thermal { 4019 polling-delay-passive = <10>; 4020 4021 thermal-sensors = <&tsens2 2>; 4022 4023 trips { 4024 trip-point0 { 4025 temperature = <105000>; 4026 hysteresis = <5000>; 4027 type = "passive"; 4028 }; 4029 4030 trip-point1 { 4031 temperature = <115000>; 4032 hysteresis = <5000>; 4033 type = "passive"; 4034 }; 4035 }; 4036 }; 4037 4038 cpu-1-2-0-thermal { 4039 polling-delay-passive = <10>; 4040 4041 thermal-sensors = <&tsens2 3>; 4042 4043 trips { 4044 trip-point0 { 4045 temperature = <105000>; 4046 hysteresis = <5000>; 4047 type = "passive"; 4048 }; 4049 4050 trip-point1 { 4051 temperature = <115000>; 4052 hysteresis = <5000>; 4053 type = "passive"; 4054 }; 4055 }; 4056 }; 4057 4058 cpu-1-3-0-thermal { 4059 polling-delay-passive = <10>; 4060 4061 thermal-sensors = <&tsens2 4>; 4062 4063 trips { 4064 trip-point0 { 4065 temperature = <105000>; 4066 hysteresis = <5000>; 4067 type = "passive"; 4068 }; 4069 4070 trip-point1 { 4071 temperature = <115000>; 4072 hysteresis = <5000>; 4073 type = "passive"; 4074 }; 4075 }; 4076 }; 4077 4078 nsp-0-0-0-thermal { 4079 polling-delay-passive = <10>; 4080 4081 thermal-sensors = <&tsens2 5>; 4082 4083 trips { 4084 trip-point0 { 4085 temperature = <105000>; 4086 hysteresis = <5000>; 4087 type = "passive"; 4088 }; 4089 4090 trip-point1 { 4091 temperature = <115000>; 4092 hysteresis = <5000>; 4093 type = "passive"; 4094 }; 4095 }; 4096 }; 4097 4098 nsp-0-1-0-thermal { 4099 polling-delay-passive = <10>; 4100 4101 thermal-sensors = <&tsens2 6>; 4102 4103 trips { 4104 trip-point0 { 4105 temperature = <105000>; 4106 hysteresis = <5000>; 4107 type = "passive"; 4108 }; 4109 4110 trip-point1 { 4111 temperature = <115000>; 4112 hysteresis = <5000>; 4113 type = "passive"; 4114 }; 4115 }; 4116 }; 4117 4118 nsp-0-2-0-thermal { 4119 polling-delay-passive = <10>; 4120 4121 thermal-sensors = <&tsens2 7>; 4122 4123 trips { 4124 trip-point0 { 4125 temperature = <105000>; 4126 hysteresis = <5000>; 4127 type = "passive"; 4128 }; 4129 4130 trip-point1 { 4131 temperature = <115000>; 4132 hysteresis = <5000>; 4133 type = "passive"; 4134 }; 4135 }; 4136 }; 4137 4138 nsp-1-0-0-thermal { 4139 polling-delay-passive = <10>; 4140 4141 thermal-sensors = <&tsens2 8>; 4142 4143 trips { 4144 trip-point0 { 4145 temperature = <105000>; 4146 hysteresis = <5000>; 4147 type = "passive"; 4148 }; 4149 4150 trip-point1 { 4151 temperature = <115000>; 4152 hysteresis = <5000>; 4153 type = "passive"; 4154 }; 4155 }; 4156 }; 4157 4158 nsp-1-1-0-thermal { 4159 polling-delay-passive = <10>; 4160 4161 thermal-sensors = <&tsens2 9>; 4162 4163 trips { 4164 trip-point0 { 4165 temperature = <105000>; 4166 hysteresis = <5000>; 4167 type = "passive"; 4168 }; 4169 4170 trip-point1 { 4171 temperature = <115000>; 4172 hysteresis = <5000>; 4173 type = "passive"; 4174 }; 4175 }; 4176 }; 4177 4178 nsp-1-2-0-thermal { 4179 polling-delay-passive = <10>; 4180 4181 thermal-sensors = <&tsens2 10>; 4182 4183 trips { 4184 trip-point0 { 4185 temperature = <105000>; 4186 hysteresis = <5000>; 4187 type = "passive"; 4188 }; 4189 4190 trip-point1 { 4191 temperature = <115000>; 4192 hysteresis = <5000>; 4193 type = "passive"; 4194 }; 4195 }; 4196 }; 4197 4198 ddrss-0-thermal { 4199 thermal-sensors = <&tsens2 11>; 4200 4201 trips { 4202 trip-point0 { 4203 temperature = <105000>; 4204 hysteresis = <5000>; 4205 type = "passive"; 4206 }; 4207 4208 trip-point1 { 4209 temperature = <115000>; 4210 hysteresis = <5000>; 4211 type = "passive"; 4212 }; 4213 }; 4214 }; 4215 4216 cpuss-1-0-thermal { 4217 thermal-sensors = <&tsens2 12>; 4218 4219 trips { 4220 trip-point0 { 4221 temperature = <105000>; 4222 hysteresis = <5000>; 4223 type = "passive"; 4224 }; 4225 4226 trip-point1 { 4227 temperature = <115000>; 4228 hysteresis = <5000>; 4229 type = "passive"; 4230 }; 4231 }; 4232 }; 4233 4234 aoss-3-thermal { 4235 thermal-sensors = <&tsens3 0>; 4236 4237 trips { 4238 trip-point0 { 4239 temperature = <105000>; 4240 hysteresis = <5000>; 4241 type = "passive"; 4242 }; 4243 4244 trip-point1 { 4245 temperature = <115000>; 4246 hysteresis = <5000>; 4247 type = "passive"; 4248 }; 4249 }; 4250 }; 4251 4252 cpu-1-0-1-thermal { 4253 polling-delay-passive = <10>; 4254 4255 thermal-sensors = <&tsens3 1>; 4256 4257 trips { 4258 trip-point0 { 4259 temperature = <105000>; 4260 hysteresis = <5000>; 4261 type = "passive"; 4262 }; 4263 4264 trip-point1 { 4265 temperature = <115000>; 4266 hysteresis = <5000>; 4267 type = "passive"; 4268 }; 4269 }; 4270 }; 4271 4272 cpu-1-1-1-thermal { 4273 polling-delay-passive = <10>; 4274 4275 thermal-sensors = <&tsens3 2>; 4276 4277 trips { 4278 trip-point0 { 4279 temperature = <105000>; 4280 hysteresis = <5000>; 4281 type = "passive"; 4282 }; 4283 4284 trip-point1 { 4285 temperature = <115000>; 4286 hysteresis = <5000>; 4287 type = "passive"; 4288 }; 4289 }; 4290 }; 4291 4292 cpu-1-2-1-thermal { 4293 polling-delay-passive = <10>; 4294 4295 thermal-sensors = <&tsens3 3>; 4296 4297 trips { 4298 trip-point0 { 4299 temperature = <105000>; 4300 hysteresis = <5000>; 4301 type = "passive"; 4302 }; 4303 4304 trip-point1 { 4305 temperature = <115000>; 4306 hysteresis = <5000>; 4307 type = "passive"; 4308 }; 4309 }; 4310 }; 4311 4312 cpu-1-3-1-thermal { 4313 polling-delay-passive = <10>; 4314 4315 thermal-sensors = <&tsens3 4>; 4316 4317 trips { 4318 trip-point0 { 4319 temperature = <105000>; 4320 hysteresis = <5000>; 4321 type = "passive"; 4322 }; 4323 4324 trip-point1 { 4325 temperature = <115000>; 4326 hysteresis = <5000>; 4327 type = "passive"; 4328 }; 4329 }; 4330 }; 4331 4332 nsp-0-0-1-thermal { 4333 polling-delay-passive = <10>; 4334 4335 thermal-sensors = <&tsens3 5>; 4336 4337 trips { 4338 trip-point0 { 4339 temperature = <105000>; 4340 hysteresis = <5000>; 4341 type = "passive"; 4342 }; 4343 4344 trip-point1 { 4345 temperature = <115000>; 4346 hysteresis = <5000>; 4347 type = "passive"; 4348 }; 4349 }; 4350 }; 4351 4352 nsp-0-1-1-thermal { 4353 polling-delay-passive = <10>; 4354 4355 thermal-sensors = <&tsens3 6>; 4356 4357 trips { 4358 trip-point0 { 4359 temperature = <105000>; 4360 hysteresis = <5000>; 4361 type = "passive"; 4362 }; 4363 4364 trip-point1 { 4365 temperature = <115000>; 4366 hysteresis = <5000>; 4367 type = "passive"; 4368 }; 4369 }; 4370 }; 4371 4372 nsp-0-2-1-thermal { 4373 polling-delay-passive = <10>; 4374 4375 thermal-sensors = <&tsens3 7>; 4376 4377 trips { 4378 trip-point0 { 4379 temperature = <105000>; 4380 hysteresis = <5000>; 4381 type = "passive"; 4382 }; 4383 4384 trip-point1 { 4385 temperature = <115000>; 4386 hysteresis = <5000>; 4387 type = "passive"; 4388 }; 4389 }; 4390 }; 4391 4392 nsp-1-0-1-thermal { 4393 polling-delay-passive = <10>; 4394 4395 thermal-sensors = <&tsens3 8>; 4396 4397 trips { 4398 trip-point0 { 4399 temperature = <105000>; 4400 hysteresis = <5000>; 4401 type = "passive"; 4402 }; 4403 4404 trip-point1 { 4405 temperature = <115000>; 4406 hysteresis = <5000>; 4407 type = "passive"; 4408 }; 4409 }; 4410 }; 4411 4412 nsp-1-1-1-thermal { 4413 polling-delay-passive = <10>; 4414 4415 thermal-sensors = <&tsens3 9>; 4416 4417 trips { 4418 trip-point0 { 4419 temperature = <105000>; 4420 hysteresis = <5000>; 4421 type = "passive"; 4422 }; 4423 4424 trip-point1 { 4425 temperature = <115000>; 4426 hysteresis = <5000>; 4427 type = "passive"; 4428 }; 4429 }; 4430 }; 4431 4432 nsp-1-2-1-thermal { 4433 polling-delay-passive = <10>; 4434 4435 thermal-sensors = <&tsens3 10>; 4436 4437 trips { 4438 trip-point0 { 4439 temperature = <105000>; 4440 hysteresis = <5000>; 4441 type = "passive"; 4442 }; 4443 4444 trip-point1 { 4445 temperature = <115000>; 4446 hysteresis = <5000>; 4447 type = "passive"; 4448 }; 4449 }; 4450 }; 4451 4452 ddrss-1-thermal { 4453 thermal-sensors = <&tsens3 11>; 4454 4455 trips { 4456 trip-point0 { 4457 temperature = <105000>; 4458 hysteresis = <5000>; 4459 type = "passive"; 4460 }; 4461 4462 trip-point1 { 4463 temperature = <115000>; 4464 hysteresis = <5000>; 4465 type = "passive"; 4466 }; 4467 }; 4468 }; 4469 4470 cpuss-1-1-thermal { 4471 thermal-sensors = <&tsens3 12>; 4472 4473 trips { 4474 trip-point0 { 4475 temperature = <105000>; 4476 hysteresis = <5000>; 4477 type = "passive"; 4478 }; 4479 4480 trip-point1 { 4481 temperature = <115000>; 4482 hysteresis = <5000>; 4483 type = "passive"; 4484 }; 4485 }; 4486 }; 4487 }; 4488 4489 arch_timer: timer { 4490 compatible = "arm,armv8-timer"; 4491 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4492 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4493 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4494 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4495 }; 4496 4497 pcie0: pcie@1c00000 { 4498 compatible = "qcom,pcie-sa8775p"; 4499 reg = <0x0 0x01c00000 0x0 0x3000>, 4500 <0x0 0x40000000 0x0 0xf20>, 4501 <0x0 0x40000f20 0x0 0xa8>, 4502 <0x0 0x40001000 0x0 0x4000>, 4503 <0x0 0x40100000 0x0 0x100000>, 4504 <0x0 0x01c03000 0x0 0x1000>; 4505 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 4506 device_type = "pci"; 4507 4508 #address-cells = <3>; 4509 #size-cells = <2>; 4510 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 4511 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 4512 bus-range = <0x00 0xff>; 4513 4514 dma-coherent; 4515 4516 linux,pci-domain = <0>; 4517 num-lanes = <2>; 4518 4519 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 4520 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 4521 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 4522 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 4523 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 4524 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 4525 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 4526 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 4527 interrupt-names = "msi0", "msi1", "msi2", "msi3", 4528 "msi4", "msi5", "msi6", "msi7"; 4529 #interrupt-cells = <1>; 4530 interrupt-map-mask = <0 0 0 0x7>; 4531 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 4532 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 4533 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 4534 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 4535 4536 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 4537 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 4538 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 4539 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 4540 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 4541 4542 clock-names = "aux", 4543 "cfg", 4544 "bus_master", 4545 "bus_slave", 4546 "slave_q2a"; 4547 4548 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 4549 assigned-clock-rates = <19200000>; 4550 4551 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 4552 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 4553 interconnect-names = "pcie-mem", "cpu-pcie"; 4554 4555 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 4556 <0x100 &pcie_smmu 0x0001 0x1>; 4557 4558 resets = <&gcc GCC_PCIE_0_BCR>; 4559 reset-names = "pci"; 4560 power-domains = <&gcc PCIE_0_GDSC>; 4561 4562 phys = <&pcie0_phy>; 4563 phy-names = "pciephy"; 4564 4565 status = "disabled"; 4566 4567 pcie@0 { 4568 device_type = "pci"; 4569 reg = <0x0 0x0 0x0 0x0 0x0>; 4570 bus-range = <0x01 0xff>; 4571 4572 #address-cells = <3>; 4573 #size-cells = <2>; 4574 ranges; 4575 }; 4576 }; 4577 4578 pcie0_ep: pcie-ep@1c00000 { 4579 compatible = "qcom,sa8775p-pcie-ep"; 4580 reg = <0x0 0x01c00000 0x0 0x3000>, 4581 <0x0 0x40000000 0x0 0xf20>, 4582 <0x0 0x40000f20 0x0 0xa8>, 4583 <0x0 0x40001000 0x0 0x4000>, 4584 <0x0 0x40200000 0x0 0x100000>, 4585 <0x0 0x01c03000 0x0 0x1000>, 4586 <0x0 0x40005000 0x0 0x2000>; 4587 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 4588 "mmio", "dma"; 4589 4590 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 4591 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 4592 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 4593 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 4594 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 4595 4596 clock-names = "aux", 4597 "cfg", 4598 "bus_master", 4599 "bus_slave", 4600 "slave_q2a"; 4601 4602 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 4603 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 4604 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; 4605 4606 interrupt-names = "global", "doorbell", "dma"; 4607 4608 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 4609 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 4610 interconnect-names = "pcie-mem", "cpu-pcie"; 4611 4612 dma-coherent; 4613 iommus = <&pcie_smmu 0x0000 0x7f>; 4614 resets = <&gcc GCC_PCIE_0_BCR>; 4615 reset-names = "core"; 4616 power-domains = <&gcc PCIE_0_GDSC>; 4617 phys = <&pcie0_phy>; 4618 phy-names = "pciephy"; 4619 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ 4620 num-lanes = <2>; 4621 4622 status = "disabled"; 4623 }; 4624 4625 pcie0_phy: phy@1c04000 { 4626 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 4627 reg = <0x0 0x1c04000 0x0 0x2000>; 4628 4629 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 4630 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 4631 <&gcc GCC_PCIE_CLKREF_EN>, 4632 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 4633 <&gcc GCC_PCIE_0_PIPE_CLK>, 4634 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, 4635 <&gcc GCC_PCIE_0_PHY_AUX_CLK>; 4636 4637 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 4638 "pipediv2", "phy_aux"; 4639 4640 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 4641 assigned-clock-rates = <100000000>; 4642 4643 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 4644 reset-names = "phy"; 4645 4646 #clock-cells = <0>; 4647 clock-output-names = "pcie_0_pipe_clk"; 4648 4649 #phy-cells = <0>; 4650 4651 status = "disabled"; 4652 }; 4653 4654 pcie1: pcie@1c10000 { 4655 compatible = "qcom,pcie-sa8775p"; 4656 reg = <0x0 0x01c10000 0x0 0x3000>, 4657 <0x0 0x60000000 0x0 0xf20>, 4658 <0x0 0x60000f20 0x0 0xa8>, 4659 <0x0 0x60001000 0x0 0x4000>, 4660 <0x0 0x60100000 0x0 0x100000>, 4661 <0x0 0x01c13000 0x0 0x1000>; 4662 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 4663 device_type = "pci"; 4664 4665 #address-cells = <3>; 4666 #size-cells = <2>; 4667 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 4668 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 4669 bus-range = <0x00 0xff>; 4670 4671 dma-coherent; 4672 4673 linux,pci-domain = <1>; 4674 num-lanes = <4>; 4675 4676 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 4677 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 4678 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 4679 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 4680 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 4681 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 4682 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 4683 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 4684 interrupt-names = "msi0", "msi1", "msi2", "msi3", 4685 "msi4", "msi5", "msi6", "msi7"; 4686 #interrupt-cells = <1>; 4687 interrupt-map-mask = <0 0 0 0x7>; 4688 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 4689 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 4690 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 4691 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 4692 4693 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 4694 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 4695 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 4696 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 4697 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 4698 4699 clock-names = "aux", 4700 "cfg", 4701 "bus_master", 4702 "bus_slave", 4703 "slave_q2a"; 4704 4705 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 4706 assigned-clock-rates = <19200000>; 4707 4708 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 4709 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 4710 interconnect-names = "pcie-mem", "cpu-pcie"; 4711 4712 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 4713 <0x100 &pcie_smmu 0x0081 0x1>; 4714 4715 resets = <&gcc GCC_PCIE_1_BCR>; 4716 reset-names = "pci"; 4717 power-domains = <&gcc PCIE_1_GDSC>; 4718 4719 phys = <&pcie1_phy>; 4720 phy-names = "pciephy"; 4721 4722 status = "disabled"; 4723 4724 pcie@0 { 4725 device_type = "pci"; 4726 reg = <0x0 0x0 0x0 0x0 0x0>; 4727 bus-range = <0x01 0xff>; 4728 4729 #address-cells = <3>; 4730 #size-cells = <2>; 4731 ranges; 4732 }; 4733 }; 4734 4735 pcie1_ep: pcie-ep@1c10000 { 4736 compatible = "qcom,sa8775p-pcie-ep"; 4737 reg = <0x0 0x01c10000 0x0 0x3000>, 4738 <0x0 0x60000000 0x0 0xf20>, 4739 <0x0 0x60000f20 0x0 0xa8>, 4740 <0x0 0x60001000 0x0 0x4000>, 4741 <0x0 0x60200000 0x0 0x100000>, 4742 <0x0 0x01c13000 0x0 0x1000>, 4743 <0x0 0x60005000 0x0 0x2000>; 4744 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 4745 "mmio", "dma"; 4746 4747 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 4748 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 4749 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 4750 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 4751 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 4752 4753 clock-names = "aux", 4754 "cfg", 4755 "bus_master", 4756 "bus_slave", 4757 "slave_q2a"; 4758 4759 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 4760 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 4761 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 4762 4763 interrupt-names = "global", "doorbell", "dma"; 4764 4765 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 4766 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 4767 interconnect-names = "pcie-mem", "cpu-pcie"; 4768 4769 dma-coherent; 4770 iommus = <&pcie_smmu 0x80 0x7f>; 4771 resets = <&gcc GCC_PCIE_1_BCR>; 4772 reset-names = "core"; 4773 power-domains = <&gcc PCIE_1_GDSC>; 4774 phys = <&pcie1_phy>; 4775 phy-names = "pciephy"; 4776 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ 4777 num-lanes = <4>; 4778 4779 status = "disabled"; 4780 }; 4781 4782 pcie1_phy: phy@1c14000 { 4783 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 4784 reg = <0x0 0x1c14000 0x0 0x4000>; 4785 4786 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 4787 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 4788 <&gcc GCC_PCIE_CLKREF_EN>, 4789 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 4790 <&gcc GCC_PCIE_1_PIPE_CLK>, 4791 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, 4792 <&gcc GCC_PCIE_1_PHY_AUX_CLK>; 4793 4794 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 4795 "pipediv2", "phy_aux"; 4796 4797 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 4798 assigned-clock-rates = <100000000>; 4799 4800 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 4801 reset-names = "phy"; 4802 4803 #clock-cells = <0>; 4804 clock-output-names = "pcie_1_pipe_clk"; 4805 4806 #phy-cells = <0>; 4807 4808 status = "disabled"; 4809 }; 4810}; 4811