1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-qcs404.h> 8#include <dt-bindings/clock/qcom,turingcc-qcs404.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <19200000>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32768>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 CPU0: cpu@100 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x100>; 43 enable-method = "psci"; 44 cpu-idle-states = <&CPU_SLEEP_0>; 45 next-level-cache = <&L2_0>; 46 #cooling-cells = <2>; 47 clocks = <&apcs_glb>; 48 operating-points-v2 = <&cpu_opp_table>; 49 power-domains = <&cpr>; 50 power-domain-names = "cpr"; 51 }; 52 53 CPU1: cpu@101 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x101>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CPU_SLEEP_0>; 59 next-level-cache = <&L2_0>; 60 #cooling-cells = <2>; 61 clocks = <&apcs_glb>; 62 operating-points-v2 = <&cpu_opp_table>; 63 power-domains = <&cpr>; 64 power-domain-names = "cpr"; 65 }; 66 67 CPU2: cpu@102 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x102>; 71 enable-method = "psci"; 72 cpu-idle-states = <&CPU_SLEEP_0>; 73 next-level-cache = <&L2_0>; 74 #cooling-cells = <2>; 75 clocks = <&apcs_glb>; 76 operating-points-v2 = <&cpu_opp_table>; 77 power-domains = <&cpr>; 78 power-domain-names = "cpr"; 79 }; 80 81 CPU3: cpu@103 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x103>; 85 enable-method = "psci"; 86 cpu-idle-states = <&CPU_SLEEP_0>; 87 next-level-cache = <&L2_0>; 88 #cooling-cells = <2>; 89 clocks = <&apcs_glb>; 90 operating-points-v2 = <&cpu_opp_table>; 91 power-domains = <&cpr>; 92 power-domain-names = "cpr"; 93 }; 94 95 L2_0: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 }; 100 101 idle-states { 102 entry-method = "psci"; 103 104 CPU_SLEEP_0: cpu-sleep-0 { 105 compatible = "arm,idle-state"; 106 idle-state-name = "standalone-power-collapse"; 107 arm,psci-suspend-param = <0x40000003>; 108 entry-latency-us = <125>; 109 exit-latency-us = <180>; 110 min-residency-us = <595>; 111 local-timer-stop; 112 }; 113 }; 114 }; 115 116 cpu_opp_table: opp-table-cpu { 117 compatible = "operating-points-v2-kryo-cpu"; 118 opp-shared; 119 120 opp-1094400000 { 121 opp-hz = /bits/ 64 <1094400000>; 122 required-opps = <&cpr_opp1>; 123 }; 124 opp-1248000000 { 125 opp-hz = /bits/ 64 <1248000000>; 126 required-opps = <&cpr_opp2>; 127 }; 128 opp-1401600000 { 129 opp-hz = /bits/ 64 <1401600000>; 130 required-opps = <&cpr_opp3>; 131 }; 132 }; 133 134 cpr_opp_table: opp-table-cpr { 135 compatible = "operating-points-v2-qcom-level"; 136 137 cpr_opp1: opp1 { 138 opp-level = <1>; 139 qcom,opp-fuse-level = <1>; 140 }; 141 cpr_opp2: opp2 { 142 opp-level = <2>; 143 qcom,opp-fuse-level = <2>; 144 }; 145 cpr_opp3: opp3 { 146 opp-level = <3>; 147 qcom,opp-fuse-level = <3>; 148 }; 149 }; 150 151 firmware { 152 scm: scm { 153 compatible = "qcom,scm-qcs404", "qcom,scm"; 154 #reset-cells = <1>; 155 }; 156 }; 157 158 memory@80000000 { 159 device_type = "memory"; 160 /* We expect the bootloader to fill in the size */ 161 reg = <0 0x80000000 0 0>; 162 }; 163 164 psci { 165 compatible = "arm,psci-1.0"; 166 method = "smc"; 167 }; 168 169 rpm: remoteproc { 170 compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc"; 171 172 glink-edge { 173 compatible = "qcom,glink-rpm"; 174 175 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 176 qcom,rpm-msg-ram = <&rpm_msg_ram>; 177 mboxes = <&apcs_glb 0>; 178 179 rpm_requests: rpm-requests { 180 compatible = "qcom,rpm-qcs404"; 181 qcom,glink-channels = "rpm_requests"; 182 183 rpmcc: clock-controller { 184 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; 185 #clock-cells = <1>; 186 clocks = <&xo_board>; 187 clock-names = "xo"; 188 }; 189 190 rpmpd: power-controller { 191 compatible = "qcom,qcs404-rpmpd"; 192 #power-domain-cells = <1>; 193 operating-points-v2 = <&rpmpd_opp_table>; 194 195 rpmpd_opp_table: opp-table { 196 compatible = "operating-points-v2"; 197 198 rpmpd_opp_ret: opp1 { 199 opp-level = <16>; 200 }; 201 202 rpmpd_opp_ret_plus: opp2 { 203 opp-level = <32>; 204 }; 205 206 rpmpd_opp_min_svs: opp3 { 207 opp-level = <48>; 208 }; 209 210 rpmpd_opp_low_svs: opp4 { 211 opp-level = <64>; 212 }; 213 214 rpmpd_opp_svs: opp5 { 215 opp-level = <128>; 216 }; 217 218 rpmpd_opp_svs_plus: opp6 { 219 opp-level = <192>; 220 }; 221 222 rpmpd_opp_nom: opp7 { 223 opp-level = <256>; 224 }; 225 226 rpmpd_opp_nom_plus: opp8 { 227 opp-level = <320>; 228 }; 229 230 rpmpd_opp_turbo: opp9 { 231 opp-level = <384>; 232 }; 233 234 rpmpd_opp_turbo_no_cpr: opp10 { 235 opp-level = <416>; 236 }; 237 238 rpmpd_opp_turbo_plus: opp11 { 239 opp-level = <512>; 240 }; 241 }; 242 }; 243 }; 244 }; 245 }; 246 247 reserved-memory { 248 #address-cells = <2>; 249 #size-cells = <2>; 250 ranges; 251 252 tz_apps_mem: memory@85900000 { 253 reg = <0 0x85900000 0 0x500000>; 254 no-map; 255 }; 256 257 xbl_mem: memory@85e00000 { 258 reg = <0 0x85e00000 0 0x100000>; 259 no-map; 260 }; 261 262 smem_region: memory@85f00000 { 263 reg = <0 0x85f00000 0 0x200000>; 264 no-map; 265 }; 266 267 tz_mem: memory@86100000 { 268 reg = <0 0x86100000 0 0x300000>; 269 no-map; 270 }; 271 272 wlan_fw_mem: memory@86400000 { 273 reg = <0 0x86400000 0 0x1100000>; 274 no-map; 275 }; 276 277 adsp_fw_mem: memory@87500000 { 278 reg = <0 0x87500000 0 0x1a00000>; 279 no-map; 280 }; 281 282 cdsp_fw_mem: memory@88f00000 { 283 reg = <0 0x88f00000 0 0x600000>; 284 no-map; 285 }; 286 287 wlan_msa_mem: memory@89500000 { 288 reg = <0 0x89500000 0 0x100000>; 289 no-map; 290 }; 291 292 uefi_mem: memory@9f800000 { 293 reg = <0 0x9f800000 0 0x800000>; 294 no-map; 295 }; 296 }; 297 298 smem { 299 compatible = "qcom,smem"; 300 301 memory-region = <&smem_region>; 302 qcom,rpm-msg-ram = <&rpm_msg_ram>; 303 304 hwlocks = <&tcsr_mutex 3>; 305 }; 306 307 soc: soc@0 { 308 #address-cells = <1>; 309 #size-cells = <1>; 310 ranges = <0 0 0 0xffffffff>; 311 compatible = "simple-bus"; 312 313 turingcc: clock-controller@800000 { 314 compatible = "qcom,qcs404-turingcc"; 315 reg = <0x00800000 0x30000>; 316 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; 317 318 #clock-cells = <1>; 319 #reset-cells = <1>; 320 321 status = "disabled"; 322 }; 323 324 rpm_msg_ram: sram@60000 { 325 compatible = "qcom,rpm-msg-ram"; 326 reg = <0x00060000 0x6000>; 327 }; 328 329 usb3_phy: phy@78000 { 330 compatible = "qcom,usb-ss-28nm-phy"; 331 reg = <0x00078000 0x400>; 332 #phy-cells = <0>; 333 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 334 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 335 <&gcc GCC_USB3_PHY_PIPE_CLK>; 336 clock-names = "ref", "ahb", "pipe"; 337 resets = <&gcc GCC_USB3_PHY_BCR>, 338 <&gcc GCC_USB3PHY_PHY_BCR>; 339 reset-names = "com", "phy"; 340 status = "disabled"; 341 }; 342 343 usb2_phy_prim: phy@7a000 { 344 compatible = "qcom,usb-hs-28nm-femtophy"; 345 reg = <0x0007a000 0x200>; 346 #phy-cells = <0>; 347 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 348 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 349 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 350 clock-names = "ref", "ahb", "sleep"; 351 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, 352 <&gcc GCC_USB2A_PHY_BCR>; 353 reset-names = "phy", "por"; 354 status = "disabled"; 355 }; 356 357 usb2_phy_sec: phy@7c000 { 358 compatible = "qcom,usb-hs-28nm-femtophy"; 359 reg = <0x0007c000 0x200>; 360 #phy-cells = <0>; 361 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 362 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 363 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 364 clock-names = "ref", "ahb", "sleep"; 365 resets = <&gcc GCC_QUSB2_PHY_BCR>, 366 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; 367 reset-names = "phy", "por"; 368 status = "disabled"; 369 }; 370 371 qfprom: qfprom@a4000 { 372 compatible = "qcom,qcs404-qfprom", "qcom,qfprom"; 373 reg = <0x000a4000 0x1000>; 374 #address-cells = <1>; 375 #size-cells = <1>; 376 cpr_efuse_speedbin: speedbin@13c { 377 reg = <0x13c 0x4>; 378 bits = <2 3>; 379 }; 380 381 tsens_s0_p1: s0-p1@1f8 { 382 reg = <0x1f8 0x1>; 383 bits = <0 6>; 384 }; 385 386 tsens_s0_p2: s0-p2@1f8 { 387 reg = <0x1f8 0x2>; 388 bits = <6 6>; 389 }; 390 391 tsens_s1_p1: s1-p1@1f9 { 392 reg = <0x1f9 0x2>; 393 bits = <4 6>; 394 }; 395 396 tsens_s1_p2: s1-p2@1fa { 397 reg = <0x1fa 0x1>; 398 bits = <2 6>; 399 }; 400 401 tsens_s2_p1: s2-p1@1fb { 402 reg = <0x1fb 0x1>; 403 bits = <0 6>; 404 }; 405 406 tsens_s2_p2: s2-p2@1fb { 407 reg = <0x1fb 0x2>; 408 bits = <6 6>; 409 }; 410 411 tsens_s3_p1: s3-p1@1fc { 412 reg = <0x1fc 0x2>; 413 bits = <4 6>; 414 }; 415 416 tsens_s3_p2: s3-p2@1fd { 417 reg = <0x1fd 0x1>; 418 bits = <2 6>; 419 }; 420 421 tsens_s4_p1: s4-p1@1fe { 422 reg = <0x1fe 0x1>; 423 bits = <0 6>; 424 }; 425 426 tsens_s4_p2: s4-p2@1fe { 427 reg = <0x1fe 0x2>; 428 bits = <6 6>; 429 }; 430 431 tsens_s5_p1: s5-p1@200 { 432 reg = <0x200 0x1>; 433 bits = <0 6>; 434 }; 435 436 tsens_s5_p2: s5-p2@200 { 437 reg = <0x200 0x2>; 438 bits = <6 6>; 439 }; 440 441 tsens_s6_p1: s6-p1@201 { 442 reg = <0x201 0x2>; 443 bits = <4 6>; 444 }; 445 446 tsens_s6_p2: s6-p2@202 { 447 reg = <0x202 0x1>; 448 bits = <2 6>; 449 }; 450 451 tsens_s7_p1: s7-p1@203 { 452 reg = <0x203 0x1>; 453 bits = <0 6>; 454 }; 455 456 tsens_s7_p2: s7-p2@203 { 457 reg = <0x203 0x2>; 458 bits = <6 6>; 459 }; 460 461 tsens_s8_p1: s8-p1@204 { 462 reg = <0x204 0x2>; 463 bits = <4 6>; 464 }; 465 466 tsens_s8_p2: s8-p2@205 { 467 reg = <0x205 0x1>; 468 bits = <2 6>; 469 }; 470 471 tsens_s9_p1: s9-p1@206 { 472 reg = <0x206 0x1>; 473 bits = <0 6>; 474 }; 475 476 tsens_s9_p2: s9-p2@206 { 477 reg = <0x206 0x2>; 478 bits = <6 6>; 479 }; 480 481 tsens_mode: mode@208 { 482 reg = <0x208 1>; 483 bits = <0 3>; 484 }; 485 486 tsens_base1: base1@208 { 487 reg = <0x208 2>; 488 bits = <3 8>; 489 }; 490 491 tsens_base2: base2@208 { 492 reg = <0x209 2>; 493 bits = <3 8>; 494 }; 495 496 cpr_efuse_quot_offset1: qoffset1@231 { 497 reg = <0x231 0x4>; 498 bits = <4 7>; 499 }; 500 cpr_efuse_quot_offset2: qoffset2@232 { 501 reg = <0x232 0x4>; 502 bits = <3 7>; 503 }; 504 cpr_efuse_quot_offset3: qoffset3@233 { 505 reg = <0x233 0x4>; 506 bits = <2 7>; 507 }; 508 cpr_efuse_init_voltage1: ivoltage1@229 { 509 reg = <0x229 0x4>; 510 bits = <4 6>; 511 }; 512 cpr_efuse_init_voltage2: ivoltage2@22a { 513 reg = <0x22a 0x4>; 514 bits = <2 6>; 515 }; 516 cpr_efuse_init_voltage3: ivoltage3@22b { 517 reg = <0x22b 0x4>; 518 bits = <0 6>; 519 }; 520 cpr_efuse_quot1: quot1@22b { 521 reg = <0x22b 0x4>; 522 bits = <6 12>; 523 }; 524 cpr_efuse_quot2: quot2@22d { 525 reg = <0x22d 0x4>; 526 bits = <2 12>; 527 }; 528 cpr_efuse_quot3: quot3@230 { 529 reg = <0x230 0x4>; 530 bits = <0 12>; 531 }; 532 cpr_efuse_ring1: ring1@228 { 533 reg = <0x228 0x4>; 534 bits = <0 3>; 535 }; 536 cpr_efuse_ring2: ring2@228 { 537 reg = <0x228 0x4>; 538 bits = <4 3>; 539 }; 540 cpr_efuse_ring3: ring3@229 { 541 reg = <0x229 0x4>; 542 bits = <0 3>; 543 }; 544 cpr_efuse_revision: revision@218 { 545 reg = <0x218 0x4>; 546 bits = <3 3>; 547 }; 548 }; 549 550 rng: rng@e3000 { 551 compatible = "qcom,prng-ee"; 552 reg = <0x000e3000 0x1000>; 553 clocks = <&gcc GCC_PRNG_AHB_CLK>; 554 clock-names = "core"; 555 }; 556 557 bimc: interconnect@400000 { 558 reg = <0x00400000 0x80000>; 559 compatible = "qcom,qcs404-bimc"; 560 #interconnect-cells = <1>; 561 }; 562 563 tsens: thermal-sensor@4a9000 { 564 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 565 reg = <0x004a9000 0x1000>, /* TM */ 566 <0x004a8000 0x1000>; /* SROT */ 567 nvmem-cells = <&tsens_mode>, 568 <&tsens_base1>, <&tsens_base2>, 569 <&tsens_s0_p1>, <&tsens_s0_p2>, 570 <&tsens_s1_p1>, <&tsens_s1_p2>, 571 <&tsens_s2_p1>, <&tsens_s2_p2>, 572 <&tsens_s3_p1>, <&tsens_s3_p2>, 573 <&tsens_s4_p1>, <&tsens_s4_p2>, 574 <&tsens_s5_p1>, <&tsens_s5_p2>, 575 <&tsens_s6_p1>, <&tsens_s6_p2>, 576 <&tsens_s7_p1>, <&tsens_s7_p2>, 577 <&tsens_s8_p1>, <&tsens_s8_p2>, 578 <&tsens_s9_p1>, <&tsens_s9_p2>; 579 nvmem-cell-names = "mode", 580 "base1", "base2", 581 "s0_p1", "s0_p2", 582 "s1_p1", "s1_p2", 583 "s2_p1", "s2_p2", 584 "s3_p1", "s3_p2", 585 "s4_p1", "s4_p2", 586 "s5_p1", "s5_p2", 587 "s6_p1", "s6_p2", 588 "s7_p1", "s7_p2", 589 "s8_p1", "s8_p2", 590 "s9_p1", "s9_p2"; 591 #qcom,sensors = <10>; 592 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 593 interrupt-names = "uplow"; 594 #thermal-sensor-cells = <1>; 595 }; 596 597 pcnoc: interconnect@500000 { 598 reg = <0x00500000 0x15080>; 599 compatible = "qcom,qcs404-pcnoc"; 600 #interconnect-cells = <1>; 601 }; 602 603 snoc: interconnect@580000 { 604 reg = <0x00580000 0x23080>; 605 compatible = "qcom,qcs404-snoc"; 606 #interconnect-cells = <1>; 607 }; 608 609 remoteproc_cdsp: remoteproc@b00000 { 610 compatible = "qcom,qcs404-cdsp-pas"; 611 reg = <0x00b00000 0x4040>; 612 613 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 614 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 615 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 616 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 617 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 618 interrupt-names = "wdog", "fatal", "ready", 619 "handover", "stop-ack"; 620 621 clocks = <&xo_board>; 622 clock-names = "xo"; 623 624 /* 625 * If the node was using the PIL binding, then include properties: 626 * clocks = <&xo_board>, 627 * <&gcc GCC_CDSP_CFG_AHB_CLK>, 628 * <&gcc GCC_CDSP_TBU_CLK>, 629 * <&gcc GCC_BIMC_CDSP_CLK>, 630 * <&turingcc TURING_WRAPPER_AON_CLK>, 631 * <&turingcc TURING_Q6SS_AHBS_AON_CLK>, 632 * <&turingcc TURING_Q6SS_AHBM_AON_CLK>, 633 * <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; 634 * clock-names = "xo", 635 * "sway", 636 * "tbu", 637 * "bimc", 638 * "ahb_aon", 639 * "q6ss_slave", 640 * "q6ss_master", 641 * "q6_axim"; 642 * resets = <&gcc GCC_CDSP_RESTART>; 643 * reset-names = "restart"; 644 * qcom,halt-regs = <&tcsr 0x19004>; 645 */ 646 647 memory-region = <&cdsp_fw_mem>; 648 649 qcom,smem-states = <&cdsp_smp2p_out 0>; 650 qcom,smem-state-names = "stop"; 651 652 status = "disabled"; 653 654 glink-edge { 655 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 656 657 qcom,remote-pid = <5>; 658 mboxes = <&apcs_glb 12>; 659 660 label = "cdsp"; 661 }; 662 }; 663 664 usb3: usb@7678800 { 665 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 666 reg = <0x07678800 0x400>; 667 #address-cells = <1>; 668 #size-cells = <1>; 669 ranges; 670 clocks = <&gcc GCC_USB30_MASTER_CLK>, 671 <&gcc GCC_SYS_NOC_USB3_CLK>, 672 <&gcc GCC_USB30_SLEEP_CLK>, 673 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 674 clock-names = "core", "iface", "sleep", "mock_utmi"; 675 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 676 <&gcc GCC_USB30_MASTER_CLK>; 677 assigned-clock-rates = <19200000>, <200000000>; 678 679 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 682 interrupt-names = "pwr_event", 683 "hs_phy_irq", 684 "qusb2_phy"; 685 686 status = "disabled"; 687 688 usb3_dwc3: usb@7580000 { 689 compatible = "snps,dwc3"; 690 reg = <0x07580000 0xcd00>; 691 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 692 phys = <&usb2_phy_prim>, <&usb3_phy>; 693 phy-names = "usb2-phy", "usb3-phy"; 694 snps,has-lpm-erratum; 695 snps,hird-threshold = /bits/ 8 <0x10>; 696 snps,usb3_lpm_capable; 697 dr_mode = "otg"; 698 }; 699 }; 700 701 usb2: usb@79b8800 { 702 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 703 reg = <0x079b8800 0x400>; 704 #address-cells = <1>; 705 #size-cells = <1>; 706 ranges; 707 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, 708 <&gcc GCC_PCNOC_USB2_CLK>, 709 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, 710 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 711 clock-names = "core", "iface", "sleep", "mock_utmi"; 712 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 713 <&gcc GCC_USB_HS_SYSTEM_CLK>; 714 assigned-clock-rates = <19200000>, <133333333>; 715 716 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 719 interrupt-names = "pwr_event", 720 "hs_phy_irq", 721 "qusb2_phy"; 722 723 status = "disabled"; 724 725 usb@78c0000 { 726 compatible = "snps,dwc3"; 727 reg = <0x078c0000 0xcc00>; 728 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 729 phys = <&usb2_phy_sec>; 730 phy-names = "usb2-phy"; 731 snps,has-lpm-erratum; 732 snps,hird-threshold = /bits/ 8 <0x10>; 733 snps,usb3_lpm_capable; 734 dr_mode = "peripheral"; 735 }; 736 }; 737 738 tlmm: pinctrl@1000000 { 739 compatible = "qcom,qcs404-pinctrl"; 740 reg = <0x01000000 0x200000>, 741 <0x01300000 0x200000>, 742 <0x07b00000 0x200000>; 743 reg-names = "south", "north", "east"; 744 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 745 gpio-ranges = <&tlmm 0 0 120>; 746 gpio-controller; 747 #gpio-cells = <2>; 748 interrupt-controller; 749 #interrupt-cells = <2>; 750 751 blsp1_i2c0_default: blsp1-i2c0-default-state { 752 pins = "gpio32", "gpio33"; 753 function = "blsp_i2c0"; 754 }; 755 756 blsp1_i2c1_default: blsp1-i2c1-default-state { 757 pins = "gpio24", "gpio25"; 758 function = "blsp_i2c1"; 759 }; 760 761 blsp1_i2c2_default: blsp1-i2c2-default-state { 762 sda-pins { 763 pins = "gpio19"; 764 function = "blsp_i2c_sda_a2"; 765 }; 766 767 scl-pins { 768 pins = "gpio20"; 769 function = "blsp_i2c_scl_a2"; 770 }; 771 }; 772 773 blsp1_i2c3_default: blsp1-i2c3-default-state { 774 pins = "gpio84", "gpio85"; 775 function = "blsp_i2c3"; 776 }; 777 778 blsp1_i2c4_default: blsp1-i2c4-default-state { 779 pins = "gpio117", "gpio118"; 780 function = "blsp_i2c4"; 781 }; 782 783 blsp1_uart0_default: blsp1-uart0-default-state { 784 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 785 function = "blsp_uart0"; 786 }; 787 788 blsp1_uart1_default: blsp1-uart1-default-state { 789 pins = "gpio22", "gpio23"; 790 function = "blsp_uart1"; 791 }; 792 793 blsp1_uart2_default: blsp1-uart2-default-state { 794 rx-pins { 795 pins = "gpio18"; 796 function = "blsp_uart_rx_a2"; 797 }; 798 799 tx-pins { 800 pins = "gpio17"; 801 function = "blsp_uart_tx_a2"; 802 }; 803 }; 804 805 blsp1_uart3_default: blsp1-uart3-default-state { 806 cts-pins { 807 pins = "gpio84"; 808 function = "blsp_uart3"; 809 }; 810 811 rts-tx-pins { 812 pins = "gpio85", "gpio82"; 813 function = "blsp_uart3"; 814 }; 815 816 rx-pins { 817 pins = "gpio83"; 818 function = "blsp_uart3"; 819 }; 820 }; 821 822 blsp2_i2c0_default: blsp2-i2c0-default-state { 823 pins = "gpio28", "gpio29"; 824 function = "blsp_i2c5"; 825 }; 826 827 blsp1_spi0_default: blsp1-spi0-default-state { 828 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 829 function = "blsp_spi0"; 830 }; 831 832 blsp1_spi1_default: blsp1-spi1-default-state { 833 mosi-pins { 834 pins = "gpio22"; 835 function = "blsp_spi_mosi_a1"; 836 }; 837 838 miso-pins { 839 pins = "gpio23"; 840 function = "blsp_spi_miso_a1"; 841 }; 842 843 cs-n-pins { 844 pins = "gpio24"; 845 function = "blsp_spi_cs_n_a1"; 846 }; 847 848 clk-pins { 849 pins = "gpio25"; 850 function = "blsp_spi_clk_a1"; 851 }; 852 }; 853 854 blsp1_spi2_default: blsp1-spi2-default-state { 855 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 856 function = "blsp_spi2"; 857 }; 858 859 blsp1_spi3_default: blsp1-spi3-default-state { 860 pins = "gpio82", "gpio83", "gpio84", "gpio85"; 861 function = "blsp_spi3"; 862 }; 863 864 blsp1_spi4_default: blsp1-spi4-default-state { 865 pins = "gpio37", "gpio38", "gpio117", "gpio118"; 866 function = "blsp_spi4"; 867 }; 868 869 blsp2_spi0_default: blsp2-spi0-default-state { 870 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 871 function = "blsp_spi5"; 872 }; 873 874 blsp2_uart0_default: blsp2-uart0-default-state { 875 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 876 function = "blsp_uart5"; 877 }; 878 }; 879 880 gcc: clock-controller@1800000 { 881 compatible = "qcom,gcc-qcs404"; 882 reg = <0x01800000 0x80000>; 883 #clock-cells = <1>; 884 #reset-cells = <1>; 885 #power-domain-cells = <1>; 886 887 clocks = <&xo_board>, 888 <&sleep_clk>, 889 <&pcie_phy>, 890 <0>, 891 <0>, 892 <0>; 893 894 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; 895 assigned-clock-rates = <19200000>; 896 }; 897 898 tcsr_mutex: hwlock@1905000 { 899 compatible = "qcom,tcsr-mutex"; 900 reg = <0x01905000 0x20000>; 901 #hwlock-cells = <1>; 902 }; 903 904 tcsr: syscon@1937000 { 905 compatible = "qcom,qcs404-tcsr", "syscon"; 906 reg = <0x01937000 0x25000>; 907 }; 908 909 sram@290000 { 910 compatible = "qcom,rpm-stats"; 911 reg = <0x00290000 0x10000>; 912 }; 913 914 spmi_bus: spmi@200f000 { 915 compatible = "qcom,spmi-pmic-arb"; 916 reg = <0x0200f000 0x001000>, 917 <0x02400000 0x800000>, 918 <0x02c00000 0x800000>, 919 <0x03800000 0x200000>, 920 <0x0200a000 0x002100>; 921 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 922 interrupt-names = "periph_irq"; 923 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 924 qcom,ee = <0>; 925 qcom,channel = <0>; 926 #address-cells = <2>; 927 #size-cells = <0>; 928 interrupt-controller; 929 #interrupt-cells = <4>; 930 }; 931 932 remoteproc_wcss: remoteproc@7400000 { 933 compatible = "qcom,qcs404-wcss-pas"; 934 reg = <0x07400000 0x4040>; 935 936 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, 937 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 938 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 939 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 940 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 941 interrupt-names = "wdog", "fatal", "ready", 942 "handover", "stop-ack"; 943 944 clocks = <&xo_board>; 945 clock-names = "xo"; 946 947 memory-region = <&wlan_fw_mem>; 948 949 qcom,smem-states = <&wcss_smp2p_out 0>; 950 qcom,smem-state-names = "stop"; 951 952 status = "disabled"; 953 954 glink-edge { 955 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 956 957 qcom,remote-pid = <1>; 958 mboxes = <&apcs_glb 16>; 959 960 label = "wcss"; 961 }; 962 }; 963 964 pcie_phy: phy@7786000 { 965 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 966 reg = <0x07786000 0xb8>; 967 968 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 969 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 970 <&gcc GCC_PCIE_0_PIPE_ARES>; 971 reset-names = "phy", "pipe"; 972 973 clock-output-names = "pcie_0_pipe_clk"; 974 #clock-cells = <0>; 975 #phy-cells = <0>; 976 977 status = "disabled"; 978 }; 979 980 sdcc1: mmc@7804000 { 981 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; 982 reg = <0x07804000 0x1000>, <0x7805000 0x1000>; 983 reg-names = "hc", "cqhci"; 984 985 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 987 interrupt-names = "hc_irq", "pwr_irq"; 988 989 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 990 <&gcc GCC_SDCC1_APPS_CLK>, 991 <&xo_board>; 992 clock-names = "iface", "core", "xo"; 993 994 status = "disabled"; 995 }; 996 997 blsp1_dma: dma-controller@7884000 { 998 compatible = "qcom,bam-v1.7.0"; 999 reg = <0x07884000 0x25000>; 1000 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1002 clock-names = "bam_clk"; 1003 #dma-cells = <1>; 1004 qcom,ee = <0>; 1005 status = "okay"; 1006 }; 1007 1008 blsp1_uart0: serial@78af000 { 1009 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1010 reg = <0x078af000 0x200>; 1011 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1013 clock-names = "core", "iface"; 1014 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1015 dma-names = "tx", "rx"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&blsp1_uart0_default>; 1018 status = "disabled"; 1019 }; 1020 1021 blsp1_uart1: serial@78b0000 { 1022 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1023 reg = <0x078b0000 0x200>; 1024 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1026 clock-names = "core", "iface"; 1027 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1028 dma-names = "tx", "rx"; 1029 pinctrl-names = "default"; 1030 pinctrl-0 = <&blsp1_uart1_default>; 1031 status = "disabled"; 1032 }; 1033 1034 blsp1_uart2: serial@78b1000 { 1035 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1036 reg = <0x078b1000 0x200>; 1037 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1039 clock-names = "core", "iface"; 1040 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1041 dma-names = "tx", "rx"; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&blsp1_uart2_default>; 1044 status = "okay"; 1045 }; 1046 1047 ethernet: ethernet@7a80000 { 1048 compatible = "qcom,qcs404-ethqos"; 1049 reg = <0x07a80000 0x10000>, 1050 <0x07a96000 0x100>; 1051 reg-names = "stmmaceth", "rgmii"; 1052 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 1053 clocks = <&gcc GCC_ETH_AXI_CLK>, 1054 <&gcc GCC_ETH_SLAVE_AHB_CLK>, 1055 <&gcc GCC_ETH_PTP_CLK>, 1056 <&gcc GCC_ETH_RGMII_CLK>; 1057 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1059 interrupt-names = "macirq", "eth_lpi"; 1060 1061 snps,tso; 1062 rx-fifo-depth = <4096>; 1063 tx-fifo-depth = <4096>; 1064 1065 status = "disabled"; 1066 }; 1067 1068 wifi: wifi@a000000 { 1069 compatible = "qcom,wcn3990-wifi"; 1070 reg = <0xa000000 0x800000>; 1071 reg-names = "membase"; 1072 memory-region = <&wlan_msa_mem>; 1073 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 1085 status = "disabled"; 1086 }; 1087 1088 blsp1_uart3: serial@78b2000 { 1089 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1090 reg = <0x078b2000 0x200>; 1091 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1093 clock-names = "core", "iface"; 1094 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1095 dma-names = "tx", "rx"; 1096 pinctrl-names = "default"; 1097 pinctrl-0 = <&blsp1_uart3_default>; 1098 status = "disabled"; 1099 }; 1100 1101 blsp1_i2c0: i2c@78b5000 { 1102 compatible = "qcom,i2c-qup-v2.2.1"; 1103 reg = <0x078b5000 0x600>; 1104 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1105 clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>, 1106 <&gcc GCC_BLSP1_AHB_CLK>; 1107 clock-names = "core", "iface"; 1108 pinctrl-names = "default"; 1109 pinctrl-0 = <&blsp1_i2c0_default>; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 status = "disabled"; 1113 }; 1114 1115 blsp1_spi0: spi@78b5000 { 1116 compatible = "qcom,spi-qup-v2.2.1"; 1117 reg = <0x078b5000 0x600>; 1118 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, 1120 <&gcc GCC_BLSP1_AHB_CLK>; 1121 clock-names = "core", "iface"; 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&blsp1_spi0_default>; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 status = "disabled"; 1127 }; 1128 1129 blsp1_i2c1: i2c@78b6000 { 1130 compatible = "qcom,i2c-qup-v2.2.1"; 1131 reg = <0x078b6000 0x600>; 1132 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1134 <&gcc GCC_BLSP1_AHB_CLK>; 1135 clock-names = "core", "iface"; 1136 pinctrl-names = "default"; 1137 pinctrl-0 = <&blsp1_i2c1_default>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 blsp1_spi1: spi@78b6000 { 1144 compatible = "qcom,spi-qup-v2.2.1"; 1145 reg = <0x078b6000 0x600>; 1146 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1147 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1148 <&gcc GCC_BLSP1_AHB_CLK>; 1149 clock-names = "core", "iface"; 1150 pinctrl-names = "default"; 1151 pinctrl-0 = <&blsp1_spi1_default>; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 status = "disabled"; 1155 }; 1156 1157 blsp1_i2c2: i2c@78b7000 { 1158 compatible = "qcom,i2c-qup-v2.2.1"; 1159 reg = <0x078b7000 0x600>; 1160 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1162 <&gcc GCC_BLSP1_AHB_CLK>; 1163 clock-names = "core", "iface"; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&blsp1_i2c2_default>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 status = "disabled"; 1169 }; 1170 1171 blsp1_spi2: spi@78b7000 { 1172 compatible = "qcom,spi-qup-v2.2.1"; 1173 reg = <0x078b7000 0x600>; 1174 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1175 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1176 <&gcc GCC_BLSP1_AHB_CLK>; 1177 clock-names = "core", "iface"; 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&blsp1_spi2_default>; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 status = "disabled"; 1183 }; 1184 1185 blsp1_i2c3: i2c@78b8000 { 1186 compatible = "qcom,i2c-qup-v2.2.1"; 1187 reg = <0x078b8000 0x600>; 1188 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1189 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1190 <&gcc GCC_BLSP1_AHB_CLK>; 1191 clock-names = "core", "iface"; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&blsp1_i2c3_default>; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 status = "disabled"; 1197 }; 1198 1199 blsp1_spi3: spi@78b8000 { 1200 compatible = "qcom,spi-qup-v2.2.1"; 1201 reg = <0x078b8000 0x600>; 1202 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1204 <&gcc GCC_BLSP1_AHB_CLK>; 1205 clock-names = "core", "iface"; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&blsp1_spi3_default>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 status = "disabled"; 1211 }; 1212 1213 blsp1_i2c4: i2c@78b9000 { 1214 compatible = "qcom,i2c-qup-v2.2.1"; 1215 reg = <0x078b9000 0x600>; 1216 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1217 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1218 <&gcc GCC_BLSP1_AHB_CLK>; 1219 clock-names = "core", "iface"; 1220 pinctrl-names = "default"; 1221 pinctrl-0 = <&blsp1_i2c4_default>; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 status = "disabled"; 1225 }; 1226 1227 blsp1_spi4: spi@78b9000 { 1228 compatible = "qcom,spi-qup-v2.2.1"; 1229 reg = <0x078b9000 0x600>; 1230 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1232 <&gcc GCC_BLSP1_AHB_CLK>; 1233 clock-names = "core", "iface"; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&blsp1_spi4_default>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 status = "disabled"; 1239 }; 1240 1241 blsp2_dma: dma-controller@7ac4000 { 1242 compatible = "qcom,bam-v1.7.0"; 1243 reg = <0x07ac4000 0x17000>; 1244 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1246 clock-names = "bam_clk"; 1247 #dma-cells = <1>; 1248 qcom,ee = <0>; 1249 status = "disabled"; 1250 }; 1251 1252 blsp2_uart0: serial@7aef000 { 1253 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1254 reg = <0x07aef000 0x200>; 1255 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1256 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1257 clock-names = "core", "iface"; 1258 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1259 dma-names = "tx", "rx"; 1260 pinctrl-names = "default"; 1261 pinctrl-0 = <&blsp2_uart0_default>; 1262 status = "disabled"; 1263 }; 1264 1265 blsp2_i2c0: i2c@7af5000 { 1266 compatible = "qcom,i2c-qup-v2.2.1"; 1267 reg = <0x07af5000 0x600>; 1268 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1269 clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>, 1270 <&gcc GCC_BLSP2_AHB_CLK>; 1271 clock-names = "core", "iface"; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&blsp2_i2c0_default>; 1274 #address-cells = <1>; 1275 #size-cells = <0>; 1276 status = "disabled"; 1277 }; 1278 1279 blsp2_spi0: spi@7af5000 { 1280 compatible = "qcom,spi-qup-v2.2.1"; 1281 reg = <0x07af5000 0x600>; 1282 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, 1284 <&gcc GCC_BLSP2_AHB_CLK>; 1285 clock-names = "core", "iface"; 1286 pinctrl-names = "default"; 1287 pinctrl-0 = <&blsp2_spi0_default>; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 status = "disabled"; 1291 }; 1292 1293 sram@8600000 { 1294 compatible = "qcom,qcs404-imem", "syscon", "simple-mfd"; 1295 reg = <0x08600000 0x1000>; 1296 1297 #address-cells = <1>; 1298 #size-cells = <1>; 1299 1300 ranges = <0 0x08600000 0x1000>; 1301 1302 pil-reloc@94c { 1303 compatible = "qcom,pil-reloc-info"; 1304 reg = <0x94c 0xc8>; 1305 }; 1306 }; 1307 1308 intc: interrupt-controller@b000000 { 1309 compatible = "qcom,msm-qgic2"; 1310 interrupt-controller; 1311 #interrupt-cells = <3>; 1312 reg = <0x0b000000 0x1000>, 1313 <0x0b002000 0x1000>; 1314 }; 1315 1316 apcs_glb: mailbox@b011000 { 1317 compatible = "qcom,qcs404-apcs-apps-global", 1318 "qcom,msm8916-apcs-kpss-global", "syscon"; 1319 reg = <0x0b011000 0x1000>; 1320 #mbox-cells = <1>; 1321 clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; 1322 clock-names = "pll", "aux"; 1323 #clock-cells = <0>; 1324 }; 1325 1326 apcs_hfpll: clock-controller@b016000 { 1327 compatible = "qcom,hfpll"; 1328 reg = <0x0b016000 0x30>; 1329 #clock-cells = <0>; 1330 clock-output-names = "apcs_hfpll"; 1331 clocks = <&xo_board>; 1332 clock-names = "xo"; 1333 }; 1334 1335 watchdog@b017000 { 1336 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; 1337 reg = <0x0b017000 0x1000>; 1338 clocks = <&sleep_clk>; 1339 }; 1340 1341 cpr: power-controller@b018000 { 1342 compatible = "qcom,qcs404-cpr", "qcom,cpr"; 1343 reg = <0x0b018000 0x1000>; 1344 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; 1345 clocks = <&xo_board>; 1346 clock-names = "ref"; 1347 vdd-apc-supply = <&pms405_s3>; 1348 #power-domain-cells = <0>; 1349 operating-points-v2 = <&cpr_opp_table>; 1350 acc-syscon = <&tcsr>; 1351 1352 nvmem-cells = <&cpr_efuse_quot_offset1>, 1353 <&cpr_efuse_quot_offset2>, 1354 <&cpr_efuse_quot_offset3>, 1355 <&cpr_efuse_init_voltage1>, 1356 <&cpr_efuse_init_voltage2>, 1357 <&cpr_efuse_init_voltage3>, 1358 <&cpr_efuse_quot1>, 1359 <&cpr_efuse_quot2>, 1360 <&cpr_efuse_quot3>, 1361 <&cpr_efuse_ring1>, 1362 <&cpr_efuse_ring2>, 1363 <&cpr_efuse_ring3>, 1364 <&cpr_efuse_revision>; 1365 nvmem-cell-names = "cpr_quotient_offset1", 1366 "cpr_quotient_offset2", 1367 "cpr_quotient_offset3", 1368 "cpr_init_voltage1", 1369 "cpr_init_voltage2", 1370 "cpr_init_voltage3", 1371 "cpr_quotient1", 1372 "cpr_quotient2", 1373 "cpr_quotient3", 1374 "cpr_ring_osc1", 1375 "cpr_ring_osc2", 1376 "cpr_ring_osc3", 1377 "cpr_fuse_revision"; 1378 }; 1379 1380 timer@b120000 { 1381 #address-cells = <1>; 1382 #size-cells = <1>; 1383 ranges; 1384 compatible = "arm,armv7-timer-mem"; 1385 reg = <0x0b120000 0x1000>; 1386 clock-frequency = <19200000>; 1387 1388 frame@b121000 { 1389 frame-number = <0>; 1390 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1392 reg = <0x0b121000 0x1000>, 1393 <0x0b122000 0x1000>; 1394 }; 1395 1396 frame@b123000 { 1397 frame-number = <1>; 1398 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1399 reg = <0x0b123000 0x1000>; 1400 status = "disabled"; 1401 }; 1402 1403 frame@b124000 { 1404 frame-number = <2>; 1405 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1406 reg = <0x0b124000 0x1000>; 1407 status = "disabled"; 1408 }; 1409 1410 frame@b125000 { 1411 frame-number = <3>; 1412 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1413 reg = <0x0b125000 0x1000>; 1414 status = "disabled"; 1415 }; 1416 1417 frame@b126000 { 1418 frame-number = <4>; 1419 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1420 reg = <0x0b126000 0x1000>; 1421 status = "disabled"; 1422 }; 1423 1424 frame@b127000 { 1425 frame-number = <5>; 1426 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1427 reg = <0xb127000 0x1000>; 1428 status = "disabled"; 1429 }; 1430 1431 frame@b128000 { 1432 frame-number = <6>; 1433 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1434 reg = <0x0b128000 0x1000>; 1435 status = "disabled"; 1436 }; 1437 }; 1438 1439 remoteproc_adsp: remoteproc@c700000 { 1440 compatible = "qcom,qcs404-adsp-pas"; 1441 reg = <0x0c700000 0x4040>; 1442 1443 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, 1444 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1445 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1446 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1447 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1448 interrupt-names = "wdog", "fatal", "ready", 1449 "handover", "stop-ack"; 1450 1451 clocks = <&xo_board>; 1452 clock-names = "xo"; 1453 1454 memory-region = <&adsp_fw_mem>; 1455 1456 qcom,smem-states = <&adsp_smp2p_out 0>; 1457 qcom,smem-state-names = "stop"; 1458 1459 status = "disabled"; 1460 1461 glink-edge { 1462 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 1463 1464 qcom,remote-pid = <2>; 1465 mboxes = <&apcs_glb 8>; 1466 1467 label = "adsp"; 1468 }; 1469 }; 1470 1471 pcie: pcie@10000000 { 1472 compatible = "qcom,pcie-qcs404"; 1473 reg = <0x10000000 0xf1d>, 1474 <0x10000f20 0xa8>, 1475 <0x07780000 0x2000>, 1476 <0x10001000 0x2000>; 1477 reg-names = "dbi", "elbi", "parf", "config"; 1478 device_type = "pci"; 1479 linux,pci-domain = <0>; 1480 bus-range = <0x00 0xff>; 1481 num-lanes = <1>; 1482 #address-cells = <3>; 1483 #size-cells = <2>; 1484 1485 ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */ 1486 <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */ 1487 1488 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1489 interrupt-names = "msi"; 1490 #interrupt-cells = <1>; 1491 interrupt-map-mask = <0 0 0 0x7>; 1492 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1493 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1494 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1495 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1496 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1497 <&gcc GCC_PCIE_0_AUX_CLK>, 1498 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1499 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1500 clock-names = "iface", "aux", "master_bus", "slave_bus"; 1501 1502 resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, 1503 <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, 1504 <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, 1505 <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, 1506 <&gcc GCC_PCIE_0_BCR>, 1507 <&gcc GCC_PCIE_0_AHB_ARES>; 1508 reset-names = "axi_m", 1509 "axi_s", 1510 "axi_m_sticky", 1511 "pipe_sticky", 1512 "pwr", 1513 "ahb"; 1514 1515 phys = <&pcie_phy>; 1516 phy-names = "pciephy"; 1517 1518 status = "disabled"; 1519 1520 pcie@0 { 1521 device_type = "pci"; 1522 reg = <0x0 0x0 0x0 0x0 0x0>; 1523 bus-range = <0x01 0xff>; 1524 1525 #address-cells = <3>; 1526 #size-cells = <2>; 1527 ranges; 1528 }; 1529 }; 1530 }; 1531 1532 timer { 1533 compatible = "arm,armv8-timer"; 1534 interrupts = <GIC_PPI 2 0xff08>, 1535 <GIC_PPI 3 0xff08>, 1536 <GIC_PPI 4 0xff08>, 1537 <GIC_PPI 1 0xff08>; 1538 }; 1539 1540 smp2p-adsp { 1541 compatible = "qcom,smp2p"; 1542 qcom,smem = <443>, <429>; 1543 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 1544 mboxes = <&apcs_glb 10>; 1545 qcom,local-pid = <0>; 1546 qcom,remote-pid = <2>; 1547 1548 adsp_smp2p_out: master-kernel { 1549 qcom,entry-name = "master-kernel"; 1550 #qcom,smem-state-cells = <1>; 1551 }; 1552 1553 adsp_smp2p_in: slave-kernel { 1554 qcom,entry-name = "slave-kernel"; 1555 interrupt-controller; 1556 #interrupt-cells = <2>; 1557 }; 1558 }; 1559 1560 smp2p-cdsp { 1561 compatible = "qcom,smp2p"; 1562 qcom,smem = <94>, <432>; 1563 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 1564 mboxes = <&apcs_glb 14>; 1565 qcom,local-pid = <0>; 1566 qcom,remote-pid = <5>; 1567 1568 cdsp_smp2p_out: master-kernel { 1569 qcom,entry-name = "master-kernel"; 1570 #qcom,smem-state-cells = <1>; 1571 }; 1572 1573 cdsp_smp2p_in: slave-kernel { 1574 qcom,entry-name = "slave-kernel"; 1575 interrupt-controller; 1576 #interrupt-cells = <2>; 1577 }; 1578 }; 1579 1580 smp2p-wcss { 1581 compatible = "qcom,smp2p"; 1582 qcom,smem = <435>, <428>; 1583 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1584 mboxes = <&apcs_glb 18>; 1585 qcom,local-pid = <0>; 1586 qcom,remote-pid = <1>; 1587 1588 wcss_smp2p_out: master-kernel { 1589 qcom,entry-name = "master-kernel"; 1590 #qcom,smem-state-cells = <1>; 1591 }; 1592 1593 wcss_smp2p_in: slave-kernel { 1594 qcom,entry-name = "slave-kernel"; 1595 interrupt-controller; 1596 #interrupt-cells = <2>; 1597 }; 1598 }; 1599 1600 thermal-zones { 1601 aoss-thermal { 1602 polling-delay-passive = <250>; 1603 polling-delay = <1000>; 1604 1605 thermal-sensors = <&tsens 0>; 1606 1607 trips { 1608 aoss_alert0: trip-point0 { 1609 temperature = <105000>; 1610 hysteresis = <2000>; 1611 type = "hot"; 1612 }; 1613 }; 1614 }; 1615 1616 q6-hvx-thermal { 1617 polling-delay-passive = <250>; 1618 polling-delay = <1000>; 1619 1620 thermal-sensors = <&tsens 1>; 1621 1622 trips { 1623 q6_hvx_alert0: trip-point0 { 1624 temperature = <105000>; 1625 hysteresis = <2000>; 1626 type = "hot"; 1627 }; 1628 }; 1629 }; 1630 1631 lpass-thermal { 1632 polling-delay-passive = <250>; 1633 polling-delay = <1000>; 1634 1635 thermal-sensors = <&tsens 2>; 1636 1637 trips { 1638 lpass_alert0: trip-point0 { 1639 temperature = <105000>; 1640 hysteresis = <2000>; 1641 type = "hot"; 1642 }; 1643 }; 1644 }; 1645 1646 wlan-thermal { 1647 polling-delay-passive = <250>; 1648 polling-delay = <1000>; 1649 1650 thermal-sensors = <&tsens 3>; 1651 1652 trips { 1653 wlan_alert0: trip-point0 { 1654 temperature = <105000>; 1655 hysteresis = <2000>; 1656 type = "hot"; 1657 }; 1658 }; 1659 }; 1660 1661 cluster-thermal { 1662 polling-delay-passive = <250>; 1663 polling-delay = <1000>; 1664 1665 thermal-sensors = <&tsens 4>; 1666 1667 trips { 1668 cluster_alert0: trip-point0 { 1669 temperature = <95000>; 1670 hysteresis = <2000>; 1671 type = "hot"; 1672 }; 1673 cluster_alert1: trip-point1 { 1674 temperature = <105000>; 1675 hysteresis = <2000>; 1676 type = "passive"; 1677 }; 1678 cluster_crit: cluster-crit { 1679 temperature = <120000>; 1680 hysteresis = <2000>; 1681 type = "critical"; 1682 }; 1683 }; 1684 cooling-maps { 1685 map0 { 1686 trip = <&cluster_alert1>; 1687 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1688 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1689 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1690 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1691 }; 1692 }; 1693 }; 1694 1695 cpu0-thermal { 1696 polling-delay-passive = <250>; 1697 polling-delay = <1000>; 1698 1699 thermal-sensors = <&tsens 5>; 1700 1701 trips { 1702 cpu0_alert0: trip-point0 { 1703 temperature = <95000>; 1704 hysteresis = <2000>; 1705 type = "hot"; 1706 }; 1707 cpu0_alert1: trip-point1 { 1708 temperature = <105000>; 1709 hysteresis = <2000>; 1710 type = "passive"; 1711 }; 1712 cpu0_crit: cpu-crit { 1713 temperature = <120000>; 1714 hysteresis = <2000>; 1715 type = "critical"; 1716 }; 1717 }; 1718 cooling-maps { 1719 map0 { 1720 trip = <&cpu0_alert1>; 1721 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1722 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1723 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1724 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1725 }; 1726 }; 1727 }; 1728 1729 cpu1-thermal { 1730 polling-delay-passive = <250>; 1731 polling-delay = <1000>; 1732 1733 thermal-sensors = <&tsens 6>; 1734 1735 trips { 1736 cpu1_alert0: trip-point0 { 1737 temperature = <95000>; 1738 hysteresis = <2000>; 1739 type = "hot"; 1740 }; 1741 cpu1_alert1: trip-point1 { 1742 temperature = <105000>; 1743 hysteresis = <2000>; 1744 type = "passive"; 1745 }; 1746 cpu1_crit: cpu-crit { 1747 temperature = <120000>; 1748 hysteresis = <2000>; 1749 type = "critical"; 1750 }; 1751 }; 1752 cooling-maps { 1753 map0 { 1754 trip = <&cpu1_alert1>; 1755 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1756 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1757 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1758 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1759 }; 1760 }; 1761 }; 1762 1763 cpu2-thermal { 1764 polling-delay-passive = <250>; 1765 polling-delay = <1000>; 1766 1767 thermal-sensors = <&tsens 7>; 1768 1769 trips { 1770 cpu2_alert0: trip-point0 { 1771 temperature = <95000>; 1772 hysteresis = <2000>; 1773 type = "hot"; 1774 }; 1775 cpu2_alert1: trip-point1 { 1776 temperature = <105000>; 1777 hysteresis = <2000>; 1778 type = "passive"; 1779 }; 1780 cpu2_crit: cpu-crit { 1781 temperature = <120000>; 1782 hysteresis = <2000>; 1783 type = "critical"; 1784 }; 1785 }; 1786 cooling-maps { 1787 map0 { 1788 trip = <&cpu2_alert1>; 1789 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1790 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1791 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1792 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1793 }; 1794 }; 1795 }; 1796 1797 cpu3-thermal { 1798 polling-delay-passive = <250>; 1799 polling-delay = <1000>; 1800 1801 thermal-sensors = <&tsens 8>; 1802 1803 trips { 1804 cpu3_alert0: trip-point0 { 1805 temperature = <95000>; 1806 hysteresis = <2000>; 1807 type = "hot"; 1808 }; 1809 cpu3_alert1: trip-point1 { 1810 temperature = <105000>; 1811 hysteresis = <2000>; 1812 type = "passive"; 1813 }; 1814 cpu3_crit: cpu-crit { 1815 temperature = <120000>; 1816 hysteresis = <2000>; 1817 type = "critical"; 1818 }; 1819 }; 1820 cooling-maps { 1821 map0 { 1822 trip = <&cpu3_alert1>; 1823 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1824 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1825 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1826 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1827 }; 1828 }; 1829 }; 1830 1831 gpu-thermal { 1832 polling-delay-passive = <250>; 1833 polling-delay = <1000>; 1834 1835 thermal-sensors = <&tsens 9>; 1836 1837 trips { 1838 gpu_alert0: trip-point0 { 1839 temperature = <95000>; 1840 hysteresis = <2000>; 1841 type = "hot"; 1842 }; 1843 }; 1844 }; 1845 }; 1846}; 1847