1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2023, Linaro Ltd 4 * 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-qcm2290.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-qcm2290.h> 11#include <dt-bindings/clock/qcom,qcm2290-gpucc.h> 12#include <dt-bindings/clock/qcom,rpmcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/interconnect/qcom,qcm2290.h> 18#include <dt-bindings/interconnect/qcom,rpm-icc.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 chosen { }; 28 29 clocks { 30 xo_board: xo-board { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 clock-frequency = <32764>; 38 #clock-cells = <0>; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0x0 0x0>; 50 clocks = <&cpufreq_hw 0>; 51 capacity-dmips-mhz = <1024>; 52 dynamic-power-coefficient = <100>; 53 enable-method = "psci"; 54 next-level-cache = <&l2_0>; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 power-domains = <&cpu_pd0>; 57 power-domain-names = "psci"; 58 l2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 }; 63 }; 64 65 cpu1: cpu@1 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53"; 68 reg = <0x0 0x1>; 69 clocks = <&cpufreq_hw 0>; 70 capacity-dmips-mhz = <1024>; 71 dynamic-power-coefficient = <100>; 72 enable-method = "psci"; 73 next-level-cache = <&l2_0>; 74 qcom,freq-domain = <&cpufreq_hw 0>; 75 power-domains = <&cpu_pd1>; 76 power-domain-names = "psci"; 77 }; 78 79 cpu2: cpu@2 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53"; 82 reg = <0x0 0x2>; 83 clocks = <&cpufreq_hw 0>; 84 capacity-dmips-mhz = <1024>; 85 dynamic-power-coefficient = <100>; 86 enable-method = "psci"; 87 next-level-cache = <&l2_0>; 88 qcom,freq-domain = <&cpufreq_hw 0>; 89 power-domains = <&cpu_pd2>; 90 power-domain-names = "psci"; 91 }; 92 93 cpu3: cpu@3 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x3>; 97 clocks = <&cpufreq_hw 0>; 98 capacity-dmips-mhz = <1024>; 99 dynamic-power-coefficient = <100>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_0>; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 power-domains = <&cpu_pd3>; 104 power-domain-names = "psci"; 105 }; 106 107 cpu-map { 108 cluster0 { 109 core0 { 110 cpu = <&cpu0>; 111 }; 112 113 core1 { 114 cpu = <&cpu1>; 115 }; 116 117 core2 { 118 cpu = <&cpu2>; 119 }; 120 121 core3 { 122 cpu = <&cpu3>; 123 }; 124 }; 125 }; 126 127 domain-idle-states { 128 cluster_sleep: cluster-sleep-0 { 129 compatible = "domain-idle-state"; 130 arm,psci-suspend-param = <0x41000043>; 131 entry-latency-us = <800>; 132 exit-latency-us = <2118>; 133 min-residency-us = <7376>; 134 }; 135 }; 136 137 idle-states { 138 entry-method = "psci"; 139 140 cpu_sleep: cpu-sleep-0 { 141 compatible = "arm,idle-state"; 142 idle-state-name = "power-collapse"; 143 arm,psci-suspend-param = <0x40000003>; 144 entry-latency-us = <290>; 145 exit-latency-us = <376>; 146 min-residency-us = <1182>; 147 local-timer-stop; 148 }; 149 }; 150 }; 151 152 firmware { 153 scm: scm { 154 compatible = "qcom,scm-qcm2290", "qcom,scm"; 155 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 156 clock-names = "core"; 157 #reset-cells = <1>; 158 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 159 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 160 }; 161 }; 162 163 memory@40000000 { 164 device_type = "memory"; 165 /* We expect the bootloader to fill in the size */ 166 reg = <0 0x40000000 0 0>; 167 }; 168 169 pmu { 170 compatible = "arm,cortex-a53-pmu"; 171 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 172 }; 173 174 psci { 175 compatible = "arm,psci-1.0"; 176 method = "smc"; 177 178 cpu_pd0: power-domain-cpu0 { 179 #power-domain-cells = <0>; 180 power-domains = <&cluster_pd>; 181 domain-idle-states = <&cpu_sleep>; 182 }; 183 184 cpu_pd1: power-domain-cpu1 { 185 #power-domain-cells = <0>; 186 power-domains = <&cluster_pd>; 187 domain-idle-states = <&cpu_sleep>; 188 }; 189 190 cpu_pd2: power-domain-cpu2 { 191 #power-domain-cells = <0>; 192 power-domains = <&cluster_pd>; 193 domain-idle-states = <&cpu_sleep>; 194 }; 195 196 cpu_pd3: power-domain-cpu3 { 197 #power-domain-cells = <0>; 198 power-domains = <&cluster_pd>; 199 domain-idle-states = <&cpu_sleep>; 200 }; 201 202 cluster_pd: power-domain-cpu-cluster { 203 #power-domain-cells = <0>; 204 power-domains = <&mpm>; 205 domain-idle-states = <&cluster_sleep>; 206 }; 207 }; 208 209 rpm: remoteproc { 210 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc"; 211 212 glink-edge { 213 compatible = "qcom,glink-rpm"; 214 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 215 qcom,rpm-msg-ram = <&rpm_msg_ram>; 216 mboxes = <&apcs_glb 0>; 217 218 rpm_requests: rpm-requests { 219 compatible = "qcom,rpm-qcm2290", "qcom,glink-smd-rpm"; 220 qcom,glink-channels = "rpm_requests"; 221 222 rpmcc: clock-controller { 223 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; 224 clocks = <&xo_board>; 225 clock-names = "xo"; 226 #clock-cells = <1>; 227 }; 228 229 rpmpd: power-controller { 230 compatible = "qcom,qcm2290-rpmpd"; 231 #power-domain-cells = <1>; 232 operating-points-v2 = <&rpmpd_opp_table>; 233 234 rpmpd_opp_table: opp-table { 235 compatible = "operating-points-v2"; 236 237 rpmpd_opp_min_svs: opp1 { 238 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 239 }; 240 241 rpmpd_opp_low_svs: opp2 { 242 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 243 }; 244 245 rpmpd_opp_svs: opp3 { 246 opp-level = <RPM_SMD_LEVEL_SVS>; 247 }; 248 249 rpmpd_opp_svs_plus: opp4 { 250 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 251 }; 252 253 rpmpd_opp_nom: opp5 { 254 opp-level = <RPM_SMD_LEVEL_NOM>; 255 }; 256 257 rpmpd_opp_nom_plus: opp6 { 258 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 259 }; 260 261 rpmpd_opp_turbo: opp7 { 262 opp-level = <RPM_SMD_LEVEL_TURBO>; 263 }; 264 265 rpmpd_opp_turbo_plus: opp8 { 266 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 267 }; 268 }; 269 }; 270 }; 271 }; 272 273 mpm: interrupt-controller { 274 compatible = "qcom,mpm"; 275 qcom,rpm-msg-ram = <&apss_mpm>; 276 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 277 mboxes = <&apcs_glb 1>; 278 interrupt-controller; 279 #interrupt-cells = <2>; 280 #power-domain-cells = <0>; 281 interrupt-parent = <&intc>; 282 qcom,mpm-pin-count = <96>; 283 qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ 284 <5 296>, /* Soundwire master_irq */ 285 <12 422>, /* DWC3 ss_phy_irq */ 286 <24 79>, /* Soundwire wake_irq */ 287 <86 183>, /* MPM wake, SPMI */ 288 <90 260>; /* QUSB2_PHY DP+DM */ 289 }; 290 }; 291 292 reserved_memory: reserved-memory { 293 #address-cells = <2>; 294 #size-cells = <2>; 295 ranges; 296 297 hyp_mem: hyp@45700000 { 298 reg = <0x0 0x45700000 0x0 0x600000>; 299 no-map; 300 }; 301 302 xbl_aop_mem: xbl-aop@45e00000 { 303 reg = <0x0 0x45e00000 0x0 0x140000>; 304 no-map; 305 }; 306 307 sec_apps_mem: sec-apps@45fff000 { 308 reg = <0x0 0x45fff000 0x0 0x1000>; 309 no-map; 310 }; 311 312 smem_mem: smem@46000000 { 313 compatible = "qcom,smem"; 314 reg = <0x0 0x46000000 0x0 0x200000>; 315 no-map; 316 317 hwlocks = <&tcsr_mutex 3>; 318 qcom,rpm-msg-ram = <&rpm_msg_ram>; 319 }; 320 321 pil_modem_mem: modem@4ab00000 { 322 reg = <0x0 0x4ab00000 0x0 0x6900000>; 323 no-map; 324 }; 325 326 pil_video_mem: video@51400000 { 327 reg = <0x0 0x51400000 0x0 0x500000>; 328 no-map; 329 }; 330 331 wlan_msa_mem: wlan-msa@51900000 { 332 reg = <0x0 0x51900000 0x0 0x100000>; 333 no-map; 334 }; 335 336 pil_adsp_mem: adsp@51a00000 { 337 reg = <0x0 0x51a00000 0x0 0x1c00000>; 338 no-map; 339 }; 340 341 pil_ipa_fw_mem: ipa-fw@53600000 { 342 reg = <0x0 0x53600000 0x0 0x10000>; 343 no-map; 344 }; 345 346 pil_ipa_gsi_mem: ipa-gsi@53610000 { 347 reg = <0x0 0x53610000 0x0 0x5000>; 348 no-map; 349 }; 350 351 pil_gpu_mem: zap@53615000 { 352 compatible = "shared-dma-pool"; 353 reg = <0x0 0x53615000 0x0 0x2000>; 354 no-map; 355 }; 356 357 cont_splash_memory: framebuffer@5c000000 { 358 reg = <0x0 0x5c000000 0x0 0x00f00000>; 359 no-map; 360 }; 361 362 dfps_data_memory: dpfs-data@5cf00000 { 363 reg = <0x0 0x5cf00000 0x0 0x0100000>; 364 no-map; 365 }; 366 367 removed_mem: reserved@60000000 { 368 reg = <0x0 0x60000000 0x0 0x3900000>; 369 no-map; 370 }; 371 372 rmtfs_mem: memory@89b01000 { 373 compatible = "qcom,rmtfs-mem"; 374 reg = <0x0 0x89b01000 0x0 0x200000>; 375 no-map; 376 377 qcom,client-id = <1>; 378 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 379 }; 380 }; 381 382 smp2p-adsp { 383 compatible = "qcom,smp2p"; 384 qcom,smem = <443>, <429>; 385 386 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 387 388 mboxes = <&apcs_glb 10>; 389 390 qcom,local-pid = <0>; 391 qcom,remote-pid = <2>; 392 393 adsp_smp2p_out: master-kernel { 394 qcom,entry-name = "master-kernel"; 395 #qcom,smem-state-cells = <1>; 396 }; 397 398 adsp_smp2p_in: slave-kernel { 399 qcom,entry-name = "slave-kernel"; 400 interrupt-controller; 401 #interrupt-cells = <2>; 402 }; 403 }; 404 405 smp2p-mpss { 406 compatible = "qcom,smp2p"; 407 qcom,smem = <435>, <428>; 408 409 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 410 411 mboxes = <&apcs_glb 14>; 412 413 qcom,local-pid = <0>; 414 qcom,remote-pid = <1>; 415 416 modem_smp2p_out: master-kernel { 417 qcom,entry-name = "master-kernel"; 418 #qcom,smem-state-cells = <1>; 419 }; 420 421 modem_smp2p_in: slave-kernel { 422 qcom,entry-name = "slave-kernel"; 423 interrupt-controller; 424 #interrupt-cells = <2>; 425 }; 426 427 wlan_smp2p_in: wlan-wpss-to-ap { 428 qcom,entry-name = "wlan"; 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 }; 432 }; 433 434 soc: soc@0 { 435 compatible = "simple-bus"; 436 #address-cells = <2>; 437 #size-cells = <2>; 438 ranges = <0 0 0 0 0x10 0>; 439 dma-ranges = <0 0 0 0 0x10 0>; 440 441 tcsr_mutex: hwlock@340000 { 442 compatible = "qcom,tcsr-mutex"; 443 reg = <0x0 0x00340000 0x0 0x20000>; 444 #hwlock-cells = <1>; 445 }; 446 447 tcsr_regs: syscon@3c0000 { 448 compatible = "qcom,qcm2290-tcsr", "syscon"; 449 reg = <0x0 0x003c0000 0x0 0x40000>; 450 }; 451 452 tlmm: pinctrl@500000 { 453 compatible = "qcom,qcm2290-tlmm"; 454 reg = <0x0 0x00500000 0x0 0x300000>; 455 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 456 gpio-controller; 457 gpio-ranges = <&tlmm 0 0 127>; 458 wakeup-parent = <&mpm>; 459 #gpio-cells = <2>; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 463 qup_i2c0_default: qup-i2c0-default-state { 464 pins = "gpio0", "gpio1"; 465 function = "qup0"; 466 drive-strength = <2>; 467 bias-pull-up; 468 }; 469 470 qup_i2c1_default: qup-i2c1-default-state { 471 pins = "gpio4", "gpio5"; 472 function = "qup1"; 473 drive-strength = <2>; 474 bias-pull-up; 475 }; 476 477 qup_i2c2_default: qup-i2c2-default-state { 478 pins = "gpio6", "gpio7"; 479 function = "qup2"; 480 drive-strength = <2>; 481 bias-pull-up; 482 }; 483 484 qup_i2c3_default: qup-i2c3-default-state { 485 pins = "gpio8", "gpio9"; 486 function = "qup3"; 487 drive-strength = <2>; 488 bias-pull-up; 489 }; 490 491 qup_i2c4_default: qup-i2c4-default-state { 492 pins = "gpio12", "gpio13"; 493 function = "qup4"; 494 drive-strength = <2>; 495 bias-pull-up; 496 }; 497 498 qup_i2c5_default: qup-i2c5-default-state { 499 pins = "gpio14", "gpio15"; 500 function = "qup5"; 501 drive-strength = <2>; 502 bias-pull-up; 503 }; 504 505 qup_spi0_default: qup-spi0-default-state { 506 pins = "gpio0", "gpio1","gpio2", "gpio3"; 507 function = "qup0"; 508 drive-strength = <2>; 509 bias-pull-up; 510 }; 511 512 qup_spi1_default: qup-spi1-default-state { 513 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 514 function = "qup1"; 515 drive-strength = <2>; 516 bias-pull-up; 517 }; 518 519 qup_spi2_default: qup-spi2-default-state { 520 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 521 function = "qup2"; 522 drive-strength = <2>; 523 bias-pull-up; 524 }; 525 526 qup_spi3_default: qup-spi3-default-state { 527 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 528 function = "qup3"; 529 drive-strength = <2>; 530 bias-pull-up; 531 }; 532 533 qup_spi4_default: qup-spi4-default-state { 534 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 535 function = "qup4"; 536 drive-strength = <2>; 537 bias-pull-up; 538 }; 539 540 qup_spi5_default: qup-spi5-default-state { 541 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 542 function = "qup5"; 543 drive-strength = <2>; 544 bias-pull-up; 545 }; 546 547 qup_uart0_default: qup-uart0-default-state { 548 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 549 function = "qup0"; 550 drive-strength = <2>; 551 bias-disable; 552 }; 553 554 qup_uart3_default: qup-uart3-default-state { 555 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 556 function = "qup3"; 557 drive-strength = <2>; 558 bias-disable; 559 }; 560 561 qup_uart4_default: qup-uart4-default-state { 562 pins = "gpio12", "gpio13"; 563 function = "qup4"; 564 drive-strength = <2>; 565 bias-disable; 566 }; 567 568 sdc1_state_on: sdc1-on-state { 569 clk-pins { 570 pins = "sdc1_clk"; 571 drive-strength = <16>; 572 bias-disable; 573 }; 574 575 cmd-pins { 576 pins = "sdc1_cmd"; 577 drive-strength = <10>; 578 bias-pull-up; 579 }; 580 581 data-pins { 582 pins = "sdc1_data"; 583 drive-strength = <10>; 584 bias-pull-up; 585 }; 586 587 rclk-pins { 588 pins = "sdc1_rclk"; 589 bias-pull-down; 590 }; 591 }; 592 593 sdc1_state_off: sdc1-off-state { 594 clk-pins { 595 pins = "sdc1_clk"; 596 drive-strength = <2>; 597 bias-disable; 598 }; 599 600 cmd-pins { 601 pins = "sdc1_cmd"; 602 drive-strength = <2>; 603 bias-pull-up; 604 }; 605 606 data-pins { 607 pins = "sdc1_data"; 608 drive-strength = <2>; 609 bias-pull-up; 610 }; 611 612 rclk-pins { 613 pins = "sdc1_rclk"; 614 bias-pull-down; 615 }; 616 }; 617 618 sdc2_state_on: sdc2-on-state { 619 clk-pins { 620 pins = "sdc2_clk"; 621 drive-strength = <16>; 622 bias-disable; 623 }; 624 625 cmd-pins { 626 pins = "sdc2_cmd"; 627 drive-strength = <10>; 628 bias-pull-up; 629 }; 630 631 data-pins { 632 pins = "sdc2_data"; 633 drive-strength = <10>; 634 bias-pull-up; 635 }; 636 }; 637 638 sdc2_state_off: sdc2-off-state { 639 clk-pins { 640 pins = "sdc2_clk"; 641 drive-strength = <2>; 642 bias-disable; 643 }; 644 645 cmd-pins { 646 pins = "sdc2_cmd"; 647 drive-strength = <2>; 648 bias-pull-up; 649 }; 650 651 data-pins { 652 pins = "sdc2_data"; 653 drive-strength = <2>; 654 bias-pull-up; 655 }; 656 }; 657 }; 658 659 gcc: clock-controller@1400000 { 660 compatible = "qcom,gcc-qcm2290"; 661 reg = <0x0 0x01400000 0x0 0x1f0000>; 662 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 663 clock-names = "bi_tcxo", "sleep_clk"; 664 #clock-cells = <1>; 665 #reset-cells = <1>; 666 #power-domain-cells = <1>; 667 }; 668 669 usb_hsphy: phy@1613000 { 670 compatible = "qcom,qcm2290-qusb2-phy"; 671 reg = <0x0 0x01613000 0x0 0x180>; 672 673 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 674 <&rpmcc RPM_SMD_XO_CLK_SRC>; 675 clock-names = "cfg_ahb", "ref"; 676 677 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 678 nvmem-cells = <&qusb2_hstx_trim>; 679 #phy-cells = <0>; 680 681 status = "disabled"; 682 }; 683 684 usb_qmpphy: phy@1615000 { 685 compatible = "qcom,qcm2290-qmp-usb3-phy"; 686 reg = <0x0 0x01615000 0x0 0x1000>; 687 688 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 689 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 690 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 691 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 692 clock-names = "cfg_ahb", 693 "ref", 694 "com_aux", 695 "pipe"; 696 697 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 698 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 699 reset-names = "phy", 700 "phy_phy"; 701 702 #clock-cells = <0>; 703 clock-output-names = "usb3_phy_pipe_clk_src"; 704 705 #phy-cells = <0>; 706 orientation-switch; 707 708 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 709 710 status = "disabled"; 711 712 ports { 713 #address-cells = <1>; 714 #size-cells = <0>; 715 716 port@0 { 717 reg = <0>; 718 719 usb_qmpphy_out: endpoint { 720 }; 721 }; 722 723 port@1 { 724 reg = <1>; 725 726 usb_qmpphy_usb_ss_in: endpoint { 727 remote-endpoint = <&usb_dwc3_ss>; 728 }; 729 }; 730 }; 731 }; 732 733 system_noc: interconnect@1880000 { 734 compatible = "qcom,qcm2290-snoc"; 735 reg = <0x0 0x01880000 0x0 0x60200>; 736 #interconnect-cells = <2>; 737 738 qup_virt: interconnect-qup { 739 compatible = "qcom,qcm2290-qup-virt"; 740 #interconnect-cells = <2>; 741 }; 742 743 mmnrt_virt: interconnect-mmnrt { 744 compatible = "qcom,qcm2290-mmnrt-virt"; 745 #interconnect-cells = <2>; 746 }; 747 748 mmrt_virt: interconnect-mmrt { 749 compatible = "qcom,qcm2290-mmrt-virt"; 750 #interconnect-cells = <2>; 751 }; 752 }; 753 754 config_noc: interconnect@1900000 { 755 compatible = "qcom,qcm2290-cnoc"; 756 reg = <0x0 0x01900000 0x0 0x8200>; 757 #interconnect-cells = <2>; 758 }; 759 760 cryptobam: dma-controller@1b04000 { 761 compatible = "qcom,bam-v1.7.0"; 762 reg = <0x0 0x01b04000 0x0 0x24000>; 763 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 765 clock-names = "bam_clk"; 766 #dma-cells = <1>; 767 qcom,ee = <0>; 768 qcom,controlled-remotely; 769 iommus = <&apps_smmu 0x0084 0x11>, 770 <&apps_smmu 0x0086 0x11>; 771 }; 772 773 crypto: crypto@1b3a000 { 774 compatible = "qcom,qcm2290-qce", "qcom,ipq4019-qce", "qcom,qce"; 775 reg = <0x0 0x01b3a000 0x0 0x6000>; 776 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 777 clock-names = "core"; 778 dmas = <&cryptobam 6>, <&cryptobam 7>; 779 dma-names = "rx", "tx"; 780 iommus = <&apps_smmu 0x0084 0x11>, 781 <&apps_smmu 0x0086 0x11>; 782 }; 783 784 qfprom@1b44000 { 785 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; 786 reg = <0x0 0x01b44000 0x0 0x3000>; 787 #address-cells = <1>; 788 #size-cells = <1>; 789 790 qusb2_hstx_trim: hstx-trim@25b { 791 reg = <0x25b 0x1>; 792 bits = <1 4>; 793 }; 794 795 gpu_speed_bin: gpu-speed-bin@2006 { 796 reg = <0x2006 0x2>; 797 bits = <5 8>; 798 }; 799 }; 800 801 pmu@1b8e300 { 802 compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon"; 803 reg = <0x0 0x01b8e300 0x0 0x600>; 804 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 805 806 operating-points-v2 = <&cpu_bwmon_opp_table>; 807 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 808 &bimc SLAVE_EBI1 RPM_ACTIVE_TAG>; 809 810 cpu_bwmon_opp_table: opp-table { 811 compatible = "operating-points-v2"; 812 813 opp-0 { 814 opp-peak-kBps = <(200 * 4 * 1000)>; 815 }; 816 817 opp-1 { 818 opp-peak-kBps = <(300 * 4 * 1000)>; 819 }; 820 821 opp-2 { 822 opp-peak-kBps = <(451 * 4 * 1000)>; 823 }; 824 825 opp-3 { 826 opp-peak-kBps = <(547 * 4 * 1000)>; 827 }; 828 829 opp-4 { 830 opp-peak-kBps = <(681 * 4 * 1000)>; 831 }; 832 833 opp-5 { 834 opp-peak-kBps = <(768 * 4 * 1000)>; 835 }; 836 837 opp-6 { 838 opp-peak-kBps = <(1017 * 4 * 1000)>; 839 }; 840 841 opp-7 { 842 opp-peak-kBps = <(1353 * 4 * 1000)>; 843 }; 844 845 opp-8 { 846 opp-peak-kBps = <(1555 * 4 * 1000)>; 847 }; 848 849 opp-9 { 850 opp-peak-kBps = <(1804 * 4 * 1000)>; 851 }; 852 }; 853 }; 854 855 spmi_bus: spmi@1c40000 { 856 compatible = "qcom,spmi-pmic-arb"; 857 reg = <0x0 0x01c40000 0x0 0x1100>, 858 <0x0 0x01e00000 0x0 0x2000000>, 859 <0x0 0x03e00000 0x0 0x100000>, 860 <0x0 0x03f00000 0x0 0xa0000>, 861 <0x0 0x01c0a000 0x0 0x26000>; 862 reg-names = "core", 863 "chnls", 864 "obsrvr", 865 "intr", 866 "cnfg"; 867 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; 868 interrupt-names = "periph_irq"; 869 qcom,ee = <0>; 870 qcom,channel = <0>; 871 #address-cells = <2>; 872 #size-cells = <0>; 873 interrupt-controller; 874 #interrupt-cells = <4>; 875 }; 876 877 tsens0: thermal-sensor@4411000 { 878 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; 879 reg = <0x0 0x04411000 0x0 0x1ff>, 880 <0x0 0x04410000 0x0 0x8>; 881 #qcom,sensors = <10>; 882 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, 883 <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 884 interrupt-names = "uplow", "critical"; 885 #thermal-sensor-cells = <1>; 886 }; 887 888 rng: rng@4453000 { 889 compatible = "qcom,prng-ee"; 890 reg = <0x0 0x04453000 0x0 0x1000>; 891 clocks = <&rpmcc RPM_SMD_HWKM_CLK>; 892 clock-names = "core"; 893 }; 894 895 bimc: interconnect@4480000 { 896 compatible = "qcom,qcm2290-bimc"; 897 reg = <0x0 0x04480000 0x0 0x80000>; 898 #interconnect-cells = <2>; 899 }; 900 901 rpm_msg_ram: sram@45f0000 { 902 compatible = "qcom,rpm-msg-ram", "mmio-sram"; 903 reg = <0x0 0x045f0000 0x0 0x7000>; 904 #address-cells = <1>; 905 #size-cells = <1>; 906 ranges = <0 0x0 0x045f0000 0x7000>; 907 908 apss_mpm: sram@1b8 { 909 reg = <0x1b8 0x48>; 910 }; 911 }; 912 913 sram@4690000 { 914 compatible = "qcom,rpm-stats"; 915 reg = <0x0 0x04690000 0x0 0x10000>; 916 }; 917 918 sdhc_1: mmc@4744000 { 919 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 920 reg = <0x0 0x04744000 0x0 0x1000>, 921 <0x0 0x04745000 0x0 0x1000>, 922 <0x0 0x04748000 0x0 0x8000>; 923 reg-names = "hc", 924 "cqhci", 925 "ice"; 926 927 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 929 interrupt-names = "hc_irq", "pwr_irq"; 930 931 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 932 <&gcc GCC_SDCC1_APPS_CLK>, 933 <&rpmcc RPM_SMD_XO_CLK_SRC>, 934 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 935 clock-names = "iface", 936 "core", 937 "xo", 938 "ice"; 939 940 resets = <&gcc GCC_SDCC1_BCR>; 941 942 power-domains = <&rpmpd QCM2290_VDDCX>; 943 operating-points-v2 = <&sdhc1_opp_table>; 944 iommus = <&apps_smmu 0xc0 0x0>; 945 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 946 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 947 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 948 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; 949 interconnect-names = "sdhc-ddr", 950 "cpu-sdhc"; 951 952 qcom,dll-config = <0x000f642c>; 953 qcom,ddr-config = <0x80040868>; 954 bus-width = <8>; 955 956 status = "disabled"; 957 958 sdhc1_opp_table: opp-table { 959 compatible = "operating-points-v2"; 960 961 opp-100000000 { 962 opp-hz = /bits/ 64 <100000000>; 963 required-opps = <&rpmpd_opp_low_svs>; 964 opp-peak-kBps = <250000 133320>; 965 opp-avg-kBps = <102400 65000>; 966 }; 967 968 opp-192000000 { 969 opp-hz = /bits/ 64 <192000000>; 970 required-opps = <&rpmpd_opp_low_svs>; 971 opp-peak-kBps = <800000 300000>; 972 opp-avg-kBps = <204800 200000>; 973 }; 974 975 opp-384000000 { 976 opp-hz = /bits/ 64 <384000000>; 977 required-opps = <&rpmpd_opp_svs_plus>; 978 opp-peak-kBps = <800000 300000>; 979 opp-avg-kBps = <204800 200000>; 980 }; 981 }; 982 }; 983 984 sdhc_2: mmc@4784000 { 985 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 986 reg = <0x0 0x04784000 0x0 0x1000>; 987 reg-names = "hc"; 988 989 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 991 interrupt-names = "hc_irq", "pwr_irq"; 992 993 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 994 <&gcc GCC_SDCC2_APPS_CLK>, 995 <&rpmcc RPM_SMD_XO_CLK_SRC>; 996 clock-names = "iface", 997 "core", 998 "xo"; 999 1000 resets = <&gcc GCC_SDCC2_BCR>; 1001 1002 power-domains = <&rpmpd QCM2290_VDDCX>; 1003 operating-points-v2 = <&sdhc2_opp_table>; 1004 iommus = <&apps_smmu 0xa0 0x0>; 1005 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG 1006 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1007 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1008 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; 1009 interconnect-names = "sdhc-ddr", 1010 "cpu-sdhc"; 1011 1012 qcom,dll-config = <0x0007642c>; 1013 qcom,ddr-config = <0x80040868>; 1014 bus-width = <4>; 1015 1016 status = "disabled"; 1017 1018 sdhc2_opp_table: opp-table { 1019 compatible = "operating-points-v2"; 1020 1021 opp-100000000 { 1022 opp-hz = /bits/ 64 <100000000>; 1023 required-opps = <&rpmpd_opp_low_svs>; 1024 opp-peak-kBps = <250000 133320>; 1025 opp-avg-kBps = <261438 150000>; 1026 }; 1027 1028 opp-202000000 { 1029 opp-hz = /bits/ 64 <202000000>; 1030 required-opps = <&rpmpd_opp_svs_plus>; 1031 opp-peak-kBps = <800000 300000>; 1032 opp-avg-kBps = <261438 300000>; 1033 }; 1034 }; 1035 }; 1036 1037 gpi_dma0: dma-controller@4a00000 { 1038 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; 1039 reg = <0x0 0x04a00000 0x0 0x60000>; 1040 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1050 dma-channels = <10>; 1051 dma-channel-mask = <0x1f>; 1052 iommus = <&apps_smmu 0xf6 0x0>; 1053 #dma-cells = <3>; 1054 status = "disabled"; 1055 }; 1056 1057 qupv3_id_0: geniqup@4ac0000 { 1058 compatible = "qcom,geni-se-qup"; 1059 reg = <0x0 0x04ac0000 0x0 0x2000>; 1060 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1061 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1062 clock-names = "m-ahb", "s-ahb"; 1063 iommus = <&apps_smmu 0xe3 0x0>; 1064 #address-cells = <2>; 1065 #size-cells = <2>; 1066 ranges; 1067 status = "disabled"; 1068 1069 i2c0: i2c@4a80000 { 1070 compatible = "qcom,geni-i2c"; 1071 reg = <0x0 0x04a80000 0x0 0x4000>; 1072 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1074 clock-names = "se"; 1075 pinctrl-0 = <&qup_i2c0_default>; 1076 pinctrl-names = "default"; 1077 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1078 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1079 dma-names = "tx", "rx"; 1080 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1081 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1082 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1083 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1084 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1085 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1086 interconnect-names = "qup-core", 1087 "qup-config", 1088 "qup-memory"; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 status = "disabled"; 1092 }; 1093 1094 spi0: spi@4a80000 { 1095 compatible = "qcom,geni-spi"; 1096 reg = <0x0 0x04a80000 0x0 0x4000>; 1097 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1099 clock-names = "se"; 1100 pinctrl-0 = <&qup_spi0_default>; 1101 pinctrl-names = "default"; 1102 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1103 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1104 dma-names = "tx", "rx"; 1105 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1106 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1107 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1108 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1109 interconnect-names = "qup-core", 1110 "qup-config"; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 status = "disabled"; 1114 }; 1115 1116 uart0: serial@4a80000 { 1117 compatible = "qcom,geni-uart"; 1118 reg = <0x0 0x04a80000 0x0 0x4000>; 1119 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1120 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1121 clock-names = "se"; 1122 pinctrl-0 = <&qup_uart0_default>; 1123 pinctrl-names = "default"; 1124 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1125 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1126 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1127 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1128 interconnect-names = "qup-core", 1129 "qup-config"; 1130 status = "disabled"; 1131 }; 1132 1133 i2c1: i2c@4a84000 { 1134 compatible = "qcom,geni-i2c"; 1135 reg = <0x0 0x04a84000 0x0 0x4000>; 1136 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1138 clock-names = "se"; 1139 pinctrl-0 = <&qup_i2c1_default>; 1140 pinctrl-names = "default"; 1141 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1142 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1143 dma-names = "tx", "rx"; 1144 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1145 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1146 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1147 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1148 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1149 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1150 interconnect-names = "qup-core", 1151 "qup-config", 1152 "qup-memory"; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 status = "disabled"; 1156 }; 1157 1158 spi1: spi@4a84000 { 1159 compatible = "qcom,geni-spi"; 1160 reg = <0x0 0x04a84000 0x0 0x4000>; 1161 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1163 clock-names = "se"; 1164 pinctrl-0 = <&qup_spi1_default>; 1165 pinctrl-names = "default"; 1166 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1167 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1168 dma-names = "tx", "rx"; 1169 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1170 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1171 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1172 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1173 interconnect-names = "qup-core", 1174 "qup-config"; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 status = "disabled"; 1178 }; 1179 1180 i2c2: i2c@4a88000 { 1181 compatible = "qcom,geni-i2c"; 1182 reg = <0x0 0x04a88000 0x0 0x4000>; 1183 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1184 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1185 clock-names = "se"; 1186 pinctrl-0 = <&qup_i2c2_default>; 1187 pinctrl-names = "default"; 1188 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1189 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1190 dma-names = "tx", "rx"; 1191 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1192 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1193 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1194 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1195 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1196 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1197 interconnect-names = "qup-core", 1198 "qup-config", 1199 "qup-memory"; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 spi2: spi@4a88000 { 1206 compatible = "qcom,geni-spi"; 1207 reg = <0x0 0x04a88000 0x0 0x4000>; 1208 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1210 clock-names = "se"; 1211 pinctrl-0 = <&qup_spi2_default>; 1212 pinctrl-names = "default"; 1213 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1214 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1215 dma-names = "tx", "rx"; 1216 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1217 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1218 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1219 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1220 interconnect-names = "qup-core", 1221 "qup-config"; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 status = "disabled"; 1225 }; 1226 1227 i2c3: i2c@4a8c000 { 1228 compatible = "qcom,geni-i2c"; 1229 reg = <0x0 0x04a8c000 0x0 0x4000>; 1230 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1231 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1232 clock-names = "se"; 1233 pinctrl-0 = <&qup_i2c3_default>; 1234 pinctrl-names = "default"; 1235 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1236 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1237 dma-names = "tx", "rx"; 1238 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1239 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1240 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1241 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1242 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1243 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1244 interconnect-names = "qup-core", 1245 "qup-config", 1246 "qup-memory"; 1247 #address-cells = <1>; 1248 #size-cells = <0>; 1249 status = "disabled"; 1250 }; 1251 1252 spi3: spi@4a8c000 { 1253 compatible = "qcom,geni-spi"; 1254 reg = <0x0 0x04a8c000 0x0 0x4000>; 1255 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1256 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1257 clock-names = "se"; 1258 pinctrl-0 = <&qup_spi3_default>; 1259 pinctrl-names = "default"; 1260 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1261 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1262 dma-names = "tx", "rx"; 1263 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1264 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1265 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1266 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1267 interconnect-names = "qup-core", 1268 "qup-config"; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 uart3: serial@4a8c000 { 1275 compatible = "qcom,geni-uart"; 1276 reg = <0x0 0x04a8c000 0x0 0x4000>; 1277 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1279 clock-names = "se"; 1280 pinctrl-0 = <&qup_uart3_default>; 1281 pinctrl-names = "default"; 1282 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1283 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1284 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1285 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1286 interconnect-names = "qup-core", 1287 "qup-config"; 1288 status = "disabled"; 1289 }; 1290 1291 i2c4: i2c@4a90000 { 1292 compatible = "qcom,geni-i2c"; 1293 reg = <0x0 0x04a90000 0x0 0x4000>; 1294 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1295 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1296 clock-names = "se"; 1297 pinctrl-0 = <&qup_i2c4_default>; 1298 pinctrl-names = "default"; 1299 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1300 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1301 dma-names = "tx", "rx"; 1302 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1303 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1304 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1305 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1306 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1307 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1308 interconnect-names = "qup-core", 1309 "qup-config", 1310 "qup-memory"; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 status = "disabled"; 1314 }; 1315 1316 spi4: spi@4a90000 { 1317 compatible = "qcom,geni-spi"; 1318 reg = <0x0 0x04a90000 0x0 0x4000>; 1319 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1320 clock-names = "se"; 1321 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1322 pinctrl-names = "default"; 1323 pinctrl-0 = <&qup_spi4_default>; 1324 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1325 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1326 dma-names = "tx", "rx"; 1327 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1328 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1329 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1330 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1331 interconnect-names = "qup-core", 1332 "qup-config"; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 status = "disabled"; 1336 }; 1337 1338 uart4: serial@4a90000 { 1339 compatible = "qcom,geni-uart"; 1340 reg = <0x0 0x04a90000 0x0 0x4000>; 1341 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1342 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1343 clock-names = "se"; 1344 pinctrl-0 = <&qup_uart4_default>; 1345 pinctrl-names = "default"; 1346 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1347 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1348 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1349 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1350 interconnect-names = "qup-core", 1351 "qup-config"; 1352 status = "disabled"; 1353 }; 1354 1355 i2c5: i2c@4a94000 { 1356 compatible = "qcom,geni-i2c"; 1357 reg = <0x0 0x04a94000 0x0 0x4000>; 1358 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1359 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1360 clock-names = "se"; 1361 pinctrl-0 = <&qup_i2c5_default>; 1362 pinctrl-names = "default"; 1363 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1364 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1365 dma-names = "tx", "rx"; 1366 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1367 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1368 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1369 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1370 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1371 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1372 interconnect-names = "qup-core", 1373 "qup-config", 1374 "qup-memory"; 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 status = "disabled"; 1378 }; 1379 1380 spi5: spi@4a94000 { 1381 compatible = "qcom,geni-spi"; 1382 reg = <0x0 0x04a94000 0x0 0x4000>; 1383 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1385 clock-names = "se"; 1386 pinctrl-0 = <&qup_spi5_default>; 1387 pinctrl-names = "default"; 1388 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1389 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1390 dma-names = "tx", "rx"; 1391 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1392 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1393 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1394 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1395 interconnect-names = "qup-core", 1396 "qup-config"; 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 status = "disabled"; 1400 }; 1401 }; 1402 1403 usb: usb@4ef8800 { 1404 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; 1405 reg = <0x0 0x04ef8800 0x0 0x400>; 1406 interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1407 <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; 1408 interrupt-names = "hs_phy_irq", 1409 "ss_phy_irq"; 1410 1411 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1412 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1413 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1414 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1415 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1416 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1417 clock-names = "cfg_noc", 1418 "core", 1419 "iface", 1420 "sleep", 1421 "mock_utmi", 1422 "xo"; 1423 1424 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1425 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1426 assigned-clock-rates = <19200000>, <133333333>; 1427 1428 resets = <&gcc GCC_USB30_PRIM_BCR>; 1429 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1430 /* TODO: USB<->IPA path */ 1431 interconnects = <&system_noc MASTER_USB3_0 RPM_ALWAYS_TAG 1432 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1433 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1434 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; 1435 interconnect-names = "usb-ddr", 1436 "apps-usb"; 1437 wakeup-source; 1438 1439 #address-cells = <2>; 1440 #size-cells = <2>; 1441 ranges; 1442 1443 status = "disabled"; 1444 1445 usb_dwc3: usb@4e00000 { 1446 compatible = "snps,dwc3"; 1447 reg = <0x0 0x04e00000 0x0 0xcd00>; 1448 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1449 phys = <&usb_hsphy>, <&usb_qmpphy>; 1450 phy-names = "usb2-phy", "usb3-phy"; 1451 iommus = <&apps_smmu 0x120 0x0>; 1452 snps,dis_u2_susphy_quirk; 1453 snps,dis_enblslpm_quirk; 1454 snps,has-lpm-erratum; 1455 snps,hird-threshold = /bits/ 8 <0x10>; 1456 snps,usb3_lpm_capable; 1457 maximum-speed = "super-speed"; 1458 dr_mode = "otg"; 1459 usb-role-switch; 1460 1461 ports { 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 1465 port@0 { 1466 reg = <0>; 1467 1468 usb_dwc3_hs: endpoint { 1469 }; 1470 }; 1471 1472 port@1 { 1473 reg = <1>; 1474 1475 usb_dwc3_ss: endpoint { 1476 remote-endpoint = <&usb_qmpphy_usb_ss_in>; 1477 }; 1478 }; 1479 }; 1480 }; 1481 }; 1482 1483 gpu: gpu@5900000 { 1484 compatible = "qcom,adreno-07000200", "qcom,adreno"; 1485 reg = <0x0 0x05900000 0x0 0x40000>; 1486 reg-names = "kgsl_3d0_reg_memory"; 1487 1488 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1489 1490 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1491 <&gpucc GPU_CC_AHB_CLK>, 1492 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1493 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1494 <&gpucc GPU_CC_CX_GMU_CLK>, 1495 <&gpucc GPU_CC_CXO_CLK>; 1496 clock-names = "core", 1497 "iface", 1498 "mem_iface", 1499 "alt_mem_iface", 1500 "gmu", 1501 "xo"; 1502 1503 interconnects = <&bimc MASTER_GFX3D RPM_ALWAYS_TAG 1504 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1505 interconnect-names = "gfx-mem"; 1506 1507 iommus = <&adreno_smmu 0 1>, 1508 <&adreno_smmu 2 0>; 1509 operating-points-v2 = <&gpu_opp_table>; 1510 power-domains = <&rpmpd QCM2290_VDDCX>; 1511 qcom,gmu = <&gmu_wrapper>; 1512 1513 nvmem-cells = <&gpu_speed_bin>; 1514 nvmem-cell-names = "speed_bin"; 1515 #cooling-cells = <2>; 1516 1517 status = "disabled"; 1518 1519 zap-shader { 1520 memory-region = <&pil_gpu_mem>; 1521 }; 1522 1523 gpu_opp_table: opp-table { 1524 compatible = "operating-points-v2"; 1525 1526 /* TODO: Scale RPM_SMD_BIMC_GPU_CLK w/ turbo freqs */ 1527 opp-1123200000 { 1528 opp-hz = /bits/ 64 <1123200000>; 1529 required-opps = <&rpmpd_opp_turbo_plus>; 1530 opp-peak-kBps = <6881000>; 1531 opp-supported-hw = <0x3>; 1532 turbo-mode; 1533 }; 1534 1535 opp-1017600000 { 1536 opp-hz = /bits/ 64 <1017600000>; 1537 required-opps = <&rpmpd_opp_turbo>; 1538 opp-peak-kBps = <6881000>; 1539 opp-supported-hw = <0x3>; 1540 turbo-mode; 1541 }; 1542 1543 opp-921600000 { 1544 opp-hz = /bits/ 64 <921600000>; 1545 required-opps = <&rpmpd_opp_nom_plus>; 1546 opp-peak-kBps = <6881000>; 1547 opp-supported-hw = <0x3>; 1548 }; 1549 1550 opp-844800000 { 1551 opp-hz = /bits/ 64 <844800000>; 1552 required-opps = <&rpmpd_opp_nom>; 1553 opp-peak-kBps = <6881000>; 1554 opp-supported-hw = <0x7>; 1555 }; 1556 1557 opp-672000000 { 1558 opp-hz = /bits/ 64 <672000000>; 1559 required-opps = <&rpmpd_opp_svs_plus>; 1560 opp-peak-kBps = <3879000>; 1561 opp-supported-hw = <0xf>; 1562 }; 1563 1564 opp-537600000 { 1565 opp-hz = /bits/ 64 <537600000>; 1566 required-opps = <&rpmpd_opp_svs>; 1567 opp-peak-kBps = <2929000>; 1568 opp-supported-hw = <0xf>; 1569 }; 1570 1571 opp-355200000 { 1572 opp-hz = /bits/ 64 <355200000>; 1573 required-opps = <&rpmpd_opp_low_svs>; 1574 opp-peak-kBps = <1720000>; 1575 opp-supported-hw = <0xf>; 1576 }; 1577 }; 1578 }; 1579 1580 gmu_wrapper: gmu@596a000 { 1581 compatible = "qcom,adreno-gmu-wrapper"; 1582 reg = <0x0 0x0596a000 0x0 0x30000>; 1583 reg-names = "gmu"; 1584 power-domains = <&gpucc GPU_CX_GDSC>, 1585 <&gpucc GPU_GX_GDSC>; 1586 power-domain-names = "cx", 1587 "gx"; 1588 }; 1589 1590 gpucc: clock-controller@5990000 { 1591 compatible = "qcom,qcm2290-gpucc"; 1592 reg = <0x0 0x05990000 0x0 0x9000>; 1593 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1594 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1595 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1596 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1597 power-domains = <&rpmpd QCM2290_VDDCX>; 1598 required-opps = <&rpmpd_opp_low_svs>; 1599 #clock-cells = <1>; 1600 #reset-cells = <1>; 1601 #power-domain-cells = <1>; 1602 }; 1603 1604 adreno_smmu: iommu@59a0000 { 1605 compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu", 1606 "qcom,smmu-500", "arm,mmu-500"; 1607 reg = <0x0 0x059a0000 0x0 0x10000>; 1608 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1610 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1612 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1614 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1615 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1616 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1617 1618 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1619 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1620 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1621 clock-names = "mem", 1622 "hlos", 1623 "iface"; 1624 1625 power-domains = <&gpucc GPU_CX_GDSC>; 1626 1627 #global-interrupts = <1>; 1628 #iommu-cells = <2>; 1629 }; 1630 1631 camss: camss@5c6e000 { 1632 compatible = "qcom,qcm2290-camss"; 1633 1634 reg = <0x0 0x5c6e000 0x0 0x1000>, 1635 <0x0 0x5c75000 0x0 0x1000>, 1636 <0x0 0x5c52000 0x0 0x1000>, 1637 <0x0 0x5c53000 0x0 0x1000>, 1638 <0x0 0x5c66000 0x0 0x400>, 1639 <0x0 0x5c68000 0x0 0x400>, 1640 <0x0 0x5c11000 0x0 0x1000>, 1641 <0x0 0x5c6f000 0x0 0x4000>, 1642 <0x0 0x5c76000 0x0 0x4000>; 1643 reg-names = "csid0", 1644 "csid1", 1645 "csiphy0", 1646 "csiphy1", 1647 "csitpg0", 1648 "csitpg1", 1649 "top", 1650 "vfe0", 1651 "vfe1"; 1652 1653 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 1654 <&gcc GCC_CAMSS_AXI_CLK>, 1655 <&gcc GCC_CAMSS_NRT_AXI_CLK>, 1656 <&gcc GCC_CAMSS_RT_AXI_CLK>, 1657 <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, 1658 <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, 1659 <&gcc GCC_CAMSS_CPHY_0_CLK>, 1660 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1661 <&gcc GCC_CAMSS_CPHY_1_CLK>, 1662 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1663 <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1664 <&gcc GCC_CAMSS_TFE_0_CLK>, 1665 <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, 1666 <&gcc GCC_CAMSS_TFE_1_CLK>, 1667 <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK> ; 1668 clock-names = "ahb", 1669 "axi", 1670 "camnoc_nrt_axi", 1671 "camnoc_rt_axi", 1672 "csi0", 1673 "csi1", 1674 "csiphy0", 1675 "csiphy0_timer", 1676 "csiphy1", 1677 "csiphy1_timer", 1678 "top_ahb", 1679 "vfe0", 1680 "vfe0_cphy_rx", 1681 "vfe1", 1682 "vfe1_cphy_rx"; 1683 1684 interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, 1685 <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, 1686 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, 1687 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 1688 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1689 <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>, 1690 <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, 1691 <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; 1692 interrupt-names = "csid0", 1693 "csid1", 1694 "csiphy0", 1695 "csiphy1", 1696 "csitpg0", 1697 "csitpg1", 1698 "vfe0", 1699 "vfe1"; 1700 1701 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 1702 &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>, 1703 <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG 1704 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1705 <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG 1706 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1707 interconnect-names = "ahb", 1708 "hf_mnoc", 1709 "sf_mnoc"; 1710 1711 iommus = <&apps_smmu 0x400 0x0>, 1712 <&apps_smmu 0x800 0x0>, 1713 <&apps_smmu 0x820 0x0>, 1714 <&apps_smmu 0x840 0x0>; 1715 1716 power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; 1717 1718 status = "disabled"; 1719 1720 ports { 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 1724 port@0 { 1725 reg = <0>; 1726 }; 1727 1728 port@1 { 1729 reg = <1>; 1730 }; 1731 }; 1732 }; 1733 1734 mdss: display-subsystem@5e00000 { 1735 compatible = "qcom,qcm2290-mdss"; 1736 reg = <0x0 0x05e00000 0x0 0x1000>; 1737 reg-names = "mdss"; 1738 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1739 interrupt-controller; 1740 #interrupt-cells = <1>; 1741 1742 clocks = <&gcc GCC_DISP_AHB_CLK>, 1743 <&gcc GCC_DISP_HF_AXI_CLK>, 1744 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1745 clock-names = "iface", 1746 "bus", 1747 "core"; 1748 1749 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 1750 1751 power-domains = <&dispcc MDSS_GDSC>; 1752 1753 iommus = <&apps_smmu 0x420 0x2>, 1754 <&apps_smmu 0x421 0x0>; 1755 interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG 1756 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1757 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1758 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; 1759 interconnect-names = "mdp0-mem", 1760 "cpu-cfg"; 1761 1762 #address-cells = <2>; 1763 #size-cells = <2>; 1764 ranges; 1765 1766 status = "disabled"; 1767 1768 mdp: display-controller@5e01000 { 1769 compatible = "qcom,qcm2290-dpu"; 1770 reg = <0x0 0x05e01000 0x0 0x8f000>, 1771 <0x0 0x05eb0000 0x0 0x3000>; 1772 reg-names = "mdp", 1773 "vbif"; 1774 1775 interrupt-parent = <&mdss>; 1776 interrupts = <0>; 1777 1778 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1779 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1780 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1781 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1782 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1783 clock-names = "bus", 1784 "iface", 1785 "core", 1786 "lut", 1787 "vsync"; 1788 1789 operating-points-v2 = <&mdp_opp_table>; 1790 power-domains = <&rpmpd QCM2290_VDDCX>; 1791 1792 ports { 1793 #address-cells = <1>; 1794 #size-cells = <0>; 1795 1796 port@0 { 1797 reg = <0>; 1798 dpu_intf1_out: endpoint { 1799 remote-endpoint = <&mdss_dsi0_in>; 1800 }; 1801 }; 1802 }; 1803 1804 mdp_opp_table: opp-table { 1805 compatible = "operating-points-v2"; 1806 1807 opp-19200000 { 1808 opp-hz = /bits/ 64 <19200000>; 1809 required-opps = <&rpmpd_opp_min_svs>; 1810 }; 1811 1812 opp-192000000 { 1813 opp-hz = /bits/ 64 <192000000>; 1814 required-opps = <&rpmpd_opp_low_svs>; 1815 }; 1816 1817 opp-256000000 { 1818 opp-hz = /bits/ 64 <256000000>; 1819 required-opps = <&rpmpd_opp_svs>; 1820 }; 1821 1822 opp-307200000 { 1823 opp-hz = /bits/ 64 <307200000>; 1824 required-opps = <&rpmpd_opp_svs_plus>; 1825 }; 1826 1827 opp-384000000 { 1828 opp-hz = /bits/ 64 <384000000>; 1829 required-opps = <&rpmpd_opp_nom>; 1830 }; 1831 }; 1832 }; 1833 1834 mdss_dsi0: dsi@5e94000 { 1835 compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1836 reg = <0x0 0x05e94000 0x0 0x400>; 1837 reg-names = "dsi_ctrl"; 1838 1839 interrupt-parent = <&mdss>; 1840 interrupts = <4>; 1841 1842 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1843 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1844 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1845 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1846 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1847 <&gcc GCC_DISP_HF_AXI_CLK>; 1848 clock-names = "byte", 1849 "byte_intf", 1850 "pixel", 1851 "core", 1852 "iface", 1853 "bus"; 1854 1855 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1856 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1857 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1858 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1859 1860 operating-points-v2 = <&dsi_opp_table>; 1861 power-domains = <&rpmpd QCM2290_VDDCX>; 1862 phys = <&mdss_dsi0_phy>; 1863 1864 #address-cells = <1>; 1865 #size-cells = <0>; 1866 1867 status = "disabled"; 1868 1869 dsi_opp_table: opp-table { 1870 compatible = "operating-points-v2"; 1871 1872 opp-19200000 { 1873 opp-hz = /bits/ 64 <19200000>; 1874 required-opps = <&rpmpd_opp_min_svs>; 1875 }; 1876 1877 opp-164000000 { 1878 opp-hz = /bits/ 64 <164000000>; 1879 required-opps = <&rpmpd_opp_low_svs>; 1880 }; 1881 1882 opp-187500000 { 1883 opp-hz = /bits/ 64 <187500000>; 1884 required-opps = <&rpmpd_opp_svs>; 1885 }; 1886 }; 1887 1888 ports { 1889 #address-cells = <1>; 1890 #size-cells = <0>; 1891 1892 port@0 { 1893 reg = <0>; 1894 1895 mdss_dsi0_in: endpoint { 1896 remote-endpoint = <&dpu_intf1_out>; 1897 }; 1898 }; 1899 1900 port@1 { 1901 reg = <1>; 1902 1903 mdss_dsi0_out: endpoint { 1904 }; 1905 }; 1906 }; 1907 }; 1908 1909 mdss_dsi0_phy: phy@5e94400 { 1910 compatible = "qcom,dsi-phy-14nm-2290"; 1911 reg = <0x0 0x05e94400 0x0 0x100>, 1912 <0x0 0x05e94500 0x0 0x300>, 1913 <0x0 0x05e94800 0x0 0x188>; 1914 reg-names = "dsi_phy", 1915 "dsi_phy_lane", 1916 "dsi_pll"; 1917 1918 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1919 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1920 clock-names = "iface", 1921 "ref"; 1922 1923 power-domains = <&rpmpd QCM2290_VDDMX>; 1924 required-opps = <&rpmpd_opp_nom>; 1925 1926 #clock-cells = <1>; 1927 #phy-cells = <0>; 1928 1929 status = "disabled"; 1930 }; 1931 }; 1932 1933 dispcc: clock-controller@5f00000 { 1934 compatible = "qcom,qcm2290-dispcc"; 1935 reg = <0x0 0x05f00000 0x0 0x20000>; 1936 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1937 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 1938 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1939 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 1940 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1941 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1942 clock-names = "bi_tcxo", 1943 "bi_tcxo_ao", 1944 "gcc_disp_gpll0_clk_src", 1945 "gcc_disp_gpll0_div_clk_src", 1946 "dsi0_phy_pll_out_byteclk", 1947 "dsi0_phy_pll_out_dsiclk"; 1948 #power-domain-cells = <1>; 1949 #clock-cells = <1>; 1950 #reset-cells = <1>; 1951 }; 1952 1953 remoteproc_mpss: remoteproc@6080000 { 1954 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; 1955 reg = <0x0 0x06080000 0x0 0x100>; 1956 1957 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1958 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1959 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1960 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1961 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1962 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1963 interrupt-names = "wdog", 1964 "fatal", 1965 "ready", 1966 "handover", 1967 "stop-ack", 1968 "shutdown-ack"; 1969 1970 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1971 clock-names = "xo"; 1972 1973 power-domains = <&rpmpd QCM2290_VDDCX>; 1974 1975 memory-region = <&pil_modem_mem>; 1976 1977 qcom,smem-states = <&modem_smp2p_out 0>; 1978 qcom,smem-state-names = "stop"; 1979 1980 status = "disabled"; 1981 1982 glink-edge { 1983 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1984 label = "mpss"; 1985 qcom,remote-pid = <1>; 1986 mboxes = <&apcs_glb 12>; 1987 }; 1988 }; 1989 1990 remoteproc_adsp: remoteproc@ab00000 { 1991 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; 1992 reg = <0x0 0x0ab00000 0x0 0x100>; 1993 1994 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 1995 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1996 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1997 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1998 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1999 interrupt-names = "wdog", 2000 "fatal", 2001 "ready", 2002 "handover", 2003 "stop-ack"; 2004 2005 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2006 clock-names = "xo"; 2007 2008 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, 2009 <&rpmpd QCM2290_VDD_LPI_MX>; 2010 2011 memory-region = <&pil_adsp_mem>; 2012 2013 qcom,smem-states = <&adsp_smp2p_out 0>; 2014 qcom,smem-state-names = "stop"; 2015 2016 status = "disabled"; 2017 2018 glink-edge { 2019 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2020 label = "lpass"; 2021 qcom,remote-pid = <2>; 2022 mboxes = <&apcs_glb 8>; 2023 }; 2024 }; 2025 2026 apps_smmu: iommu@c600000 { 2027 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2028 reg = <0x0 0x0c600000 0x0 0x80000>; 2029 #iommu-cells = <2>; 2030 #global-interrupts = <1>; 2031 2032 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2061 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2063 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2064 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2065 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2066 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2068 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2069 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2070 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2071 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2072 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2073 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2074 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2075 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2076 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2077 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2078 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2079 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2080 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2081 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2082 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2083 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2097 }; 2098 2099 wifi: wifi@c800000 { 2100 compatible = "qcom,wcn3990-wifi"; 2101 reg = <0x0 0x0c800000 0x0 0x800000>; 2102 reg-names = "membase"; 2103 memory-region = <&wlan_msa_mem>; 2104 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2116 iommus = <&apps_smmu 0x1a0 0x1>; 2117 qcom,msa-fixed-perm; 2118 status = "disabled"; 2119 }; 2120 2121 watchdog@f017000 { 2122 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; 2123 reg = <0x0 0x0f017000 0x0 0x1000>; 2124 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 2125 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 2126 clocks = <&sleep_clk>; 2127 }; 2128 2129 apcs_glb: mailbox@f111000 { 2130 compatible = "qcom,qcm2290-apcs-hmss-global"; 2131 reg = <0x0 0x0f111000 0x0 0x1000>; 2132 #mbox-cells = <1>; 2133 }; 2134 2135 timer@f120000 { 2136 compatible = "arm,armv7-timer-mem"; 2137 reg = <0x0 0x0f120000 0x0 0x1000>; 2138 #address-cells = <1>; 2139 #size-cells = <1>; 2140 ranges = <0 0x0 0x0f121000 0x8000>; 2141 2142 frame@0 { 2143 reg = <0x0 0x1000>, 2144 <0x1000 0x1000>; 2145 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2147 frame-number = <0>; 2148 }; 2149 2150 frame@2000 { 2151 reg = <0x2000 0x1000>; 2152 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2153 frame-number = <1>; 2154 status = "disabled"; 2155 }; 2156 2157 frame@3000 { 2158 reg = <0x3000 0x1000>; 2159 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2160 frame-number = <2>; 2161 status = "disabled"; 2162 }; 2163 2164 frame@4000 { 2165 reg = <0x4000 0x1000>; 2166 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2167 frame-number = <3>; 2168 status = "disabled"; 2169 }; 2170 2171 frame@5000 { 2172 reg = <0x5000 0x1000>; 2173 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2174 frame-number = <4>; 2175 status = "disabled"; 2176 }; 2177 2178 frame@6000 { 2179 reg = <0x6000 0x1000>; 2180 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2181 frame-number = <5>; 2182 status = "disabled"; 2183 }; 2184 2185 frame@7000 { 2186 reg = <0x7000 0x1000>; 2187 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2188 frame-number = <6>; 2189 status = "disabled"; 2190 }; 2191 }; 2192 2193 intc: interrupt-controller@f200000 { 2194 compatible = "arm,gic-v3"; 2195 reg = <0x0 0x0f200000 0x0 0x10000>, 2196 <0x0 0x0f300000 0x0 0x100000>; 2197 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2198 #interrupt-cells = <3>; 2199 interrupt-controller; 2200 interrupt-parent = <&intc>; 2201 #redistributor-regions = <1>; 2202 redistributor-stride = <0x0 0x20000>; 2203 }; 2204 2205 cpufreq_hw: cpufreq@f521000 { 2206 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; 2207 reg = <0x0 0x0f521000 0x0 0x1000>; 2208 reg-names = "freq-domain0"; 2209 interrupts-extended = <&lmh_cluster 0>; 2210 interrupt-names = "dcvsh-irq-0"; 2211 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2212 clock-names = "xo", "alternate"; 2213 2214 #freq-domain-cells = <1>; 2215 #clock-cells = <1>; 2216 }; 2217 2218 lmh_cluster: lmh@f550800 { 2219 compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh"; 2220 reg = <0x0 0x0f550800 0x0 0x400>; 2221 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2222 cpus = <&cpu0>; 2223 qcom,lmh-temp-arm-millicelsius = <65000>; 2224 qcom,lmh-temp-low-millicelsius = <94500>; 2225 qcom,lmh-temp-high-millicelsius = <95000>; 2226 interrupt-controller; 2227 #interrupt-cells = <1>; 2228 }; 2229 }; 2230 2231 thermal-zones { 2232 mapss-thermal { 2233 thermal-sensors = <&tsens0 0>; 2234 2235 trips { 2236 mapss_alert0: trip-point0 { 2237 temperature = <90000>; 2238 hysteresis = <2000>; 2239 type = "passive"; 2240 }; 2241 2242 mapss_alert1: trip-point1 { 2243 temperature = <95000>; 2244 hysteresis = <2000>; 2245 type = "passive"; 2246 }; 2247 2248 mapss_crit: mapss-crit { 2249 temperature = <110000>; 2250 hysteresis = <1000>; 2251 type = "critical"; 2252 }; 2253 }; 2254 }; 2255 2256 video-thermal { 2257 thermal-sensors = <&tsens0 1>; 2258 2259 trips { 2260 video_alert0: trip-point0 { 2261 temperature = <90000>; 2262 hysteresis = <2000>; 2263 type = "passive"; 2264 }; 2265 2266 video_alert1: trip-point1 { 2267 temperature = <95000>; 2268 hysteresis = <2000>; 2269 type = "passive"; 2270 }; 2271 2272 video_crit: video-crit { 2273 temperature = <110000>; 2274 hysteresis = <1000>; 2275 type = "critical"; 2276 }; 2277 }; 2278 }; 2279 2280 wlan-thermal { 2281 thermal-sensors = <&tsens0 2>; 2282 2283 trips { 2284 wlan_alert0: trip-point0 { 2285 temperature = <90000>; 2286 hysteresis = <2000>; 2287 type = "passive"; 2288 }; 2289 2290 wlan_alert1: trip-point1 { 2291 temperature = <95000>; 2292 hysteresis = <2000>; 2293 type = "passive"; 2294 }; 2295 2296 wlan_crit: wlan-crit { 2297 temperature = <110000>; 2298 hysteresis = <1000>; 2299 type = "critical"; 2300 }; 2301 }; 2302 }; 2303 2304 cpuss0-thermal { 2305 thermal-sensors = <&tsens0 3>; 2306 2307 trips { 2308 cpuss0_alert0: trip-point0 { 2309 temperature = <90000>; 2310 hysteresis = <2000>; 2311 type = "passive"; 2312 }; 2313 2314 cpuss0_alert1: trip-point1 { 2315 temperature = <95000>; 2316 hysteresis = <2000>; 2317 type = "passive"; 2318 }; 2319 2320 cpuss0_crit: cpuss0-crit { 2321 temperature = <110000>; 2322 hysteresis = <1000>; 2323 type = "critical"; 2324 }; 2325 }; 2326 }; 2327 2328 cpuss1-thermal { 2329 thermal-sensors = <&tsens0 4>; 2330 2331 trips { 2332 cpuss1_alert0: trip-point0 { 2333 temperature = <90000>; 2334 hysteresis = <2000>; 2335 type = "passive"; 2336 }; 2337 2338 cpuss1_alert1: trip-point1 { 2339 temperature = <95000>; 2340 hysteresis = <2000>; 2341 type = "passive"; 2342 }; 2343 2344 cpuss1_crit: cpuss1-crit { 2345 temperature = <110000>; 2346 hysteresis = <1000>; 2347 type = "critical"; 2348 }; 2349 }; 2350 }; 2351 2352 mdm0-thermal { 2353 thermal-sensors = <&tsens0 5>; 2354 2355 trips { 2356 mdm0_alert0: trip-point0 { 2357 temperature = <90000>; 2358 hysteresis = <2000>; 2359 type = "passive"; 2360 }; 2361 2362 mdm0_alert1: trip-point1 { 2363 temperature = <95000>; 2364 hysteresis = <2000>; 2365 type = "passive"; 2366 }; 2367 2368 mdm0_crit: mdm0-crit { 2369 temperature = <110000>; 2370 hysteresis = <1000>; 2371 type = "critical"; 2372 }; 2373 }; 2374 }; 2375 2376 mdm1-thermal { 2377 thermal-sensors = <&tsens0 6>; 2378 2379 trips { 2380 mdm1_alert0: trip-point0 { 2381 temperature = <90000>; 2382 hysteresis = <2000>; 2383 type = "passive"; 2384 }; 2385 2386 mdm1_alert1: trip-point1 { 2387 temperature = <95000>; 2388 hysteresis = <2000>; 2389 type = "passive"; 2390 }; 2391 2392 mdm1_crit: mdm1-crit { 2393 temperature = <110000>; 2394 hysteresis = <1000>; 2395 type = "critical"; 2396 }; 2397 }; 2398 }; 2399 2400 gpu-thermal { 2401 thermal-sensors = <&tsens0 7>; 2402 2403 trips { 2404 gpu_alert0: trip-point0 { 2405 temperature = <90000>; 2406 hysteresis = <2000>; 2407 type = "passive"; 2408 }; 2409 2410 gpu_alert1: trip-point1 { 2411 temperature = <95000>; 2412 hysteresis = <2000>; 2413 type = "passive"; 2414 }; 2415 2416 gpu_crit: gpu-crit { 2417 temperature = <110000>; 2418 hysteresis = <1000>; 2419 type = "critical"; 2420 }; 2421 }; 2422 }; 2423 2424 hm-center-thermal { 2425 thermal-sensors = <&tsens0 8>; 2426 2427 trips { 2428 hm_center_alert0: trip-point0 { 2429 temperature = <90000>; 2430 hysteresis = <2000>; 2431 type = "passive"; 2432 }; 2433 2434 hm_center_alert1: trip-point1 { 2435 temperature = <95000>; 2436 hysteresis = <2000>; 2437 type = "passive"; 2438 }; 2439 2440 hm_center_crit: hm-center-crit { 2441 temperature = <110000>; 2442 hysteresis = <1000>; 2443 type = "critical"; 2444 }; 2445 }; 2446 }; 2447 2448 camera-thermal { 2449 thermal-sensors = <&tsens0 9>; 2450 2451 trips { 2452 camera_alert0: trip-point0 { 2453 temperature = <90000>; 2454 hysteresis = <2000>; 2455 type = "passive"; 2456 }; 2457 2458 camera_alert1: trip-point1 { 2459 temperature = <95000>; 2460 hysteresis = <2000>; 2461 type = "passive"; 2462 }; 2463 2464 camera_crit: camera-crit { 2465 temperature = <110000>; 2466 hysteresis = <1000>; 2467 type = "critical"; 2468 }; 2469 }; 2470 }; 2471 }; 2472 2473 timer { 2474 compatible = "arm,armv8-timer"; 2475 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2476 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2477 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2478 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2479 }; 2480}; 2481