1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2023, Linaro Ltd 4 * 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-qcm2290.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-qcm2290.h> 11#include <dt-bindings/clock/qcom,qcm2290-gpucc.h> 12#include <dt-bindings/clock/qcom,rpmcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/interconnect/qcom,qcm2290.h> 18#include <dt-bindings/interconnect/qcom,rpm-icc.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 chosen { }; 28 29 clocks { 30 xo_board: xo-board { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 clock-frequency = <32764>; 38 #clock-cells = <0>; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0x0 0x0>; 50 clocks = <&cpufreq_hw 0>; 51 capacity-dmips-mhz = <1024>; 52 dynamic-power-coefficient = <100>; 53 enable-method = "psci"; 54 next-level-cache = <&l2_0>; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 power-domains = <&cpu_pd0>; 57 power-domain-names = "psci"; 58 l2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 }; 63 }; 64 65 cpu1: cpu@1 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53"; 68 reg = <0x0 0x1>; 69 clocks = <&cpufreq_hw 0>; 70 capacity-dmips-mhz = <1024>; 71 dynamic-power-coefficient = <100>; 72 enable-method = "psci"; 73 next-level-cache = <&l2_0>; 74 qcom,freq-domain = <&cpufreq_hw 0>; 75 power-domains = <&cpu_pd1>; 76 power-domain-names = "psci"; 77 }; 78 79 cpu2: cpu@2 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53"; 82 reg = <0x0 0x2>; 83 clocks = <&cpufreq_hw 0>; 84 capacity-dmips-mhz = <1024>; 85 dynamic-power-coefficient = <100>; 86 enable-method = "psci"; 87 next-level-cache = <&l2_0>; 88 qcom,freq-domain = <&cpufreq_hw 0>; 89 power-domains = <&cpu_pd2>; 90 power-domain-names = "psci"; 91 }; 92 93 cpu3: cpu@3 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x3>; 97 clocks = <&cpufreq_hw 0>; 98 capacity-dmips-mhz = <1024>; 99 dynamic-power-coefficient = <100>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_0>; 102 qcom,freq-domain = <&cpufreq_hw 0>; 103 power-domains = <&cpu_pd3>; 104 power-domain-names = "psci"; 105 }; 106 107 cpu-map { 108 cluster0 { 109 core0 { 110 cpu = <&cpu0>; 111 }; 112 113 core1 { 114 cpu = <&cpu1>; 115 }; 116 117 core2 { 118 cpu = <&cpu2>; 119 }; 120 121 core3 { 122 cpu = <&cpu3>; 123 }; 124 }; 125 }; 126 127 domain-idle-states { 128 cluster_sleep: cluster-sleep-0 { 129 compatible = "domain-idle-state"; 130 arm,psci-suspend-param = <0x41000043>; 131 entry-latency-us = <800>; 132 exit-latency-us = <2118>; 133 min-residency-us = <7376>; 134 }; 135 }; 136 137 idle-states { 138 entry-method = "psci"; 139 140 cpu_sleep: cpu-sleep-0 { 141 compatible = "arm,idle-state"; 142 idle-state-name = "power-collapse"; 143 arm,psci-suspend-param = <0x40000003>; 144 entry-latency-us = <290>; 145 exit-latency-us = <376>; 146 min-residency-us = <1182>; 147 local-timer-stop; 148 }; 149 }; 150 }; 151 152 firmware { 153 scm: scm { 154 compatible = "qcom,scm-qcm2290", "qcom,scm"; 155 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 156 clock-names = "core"; 157 qcom,dload-mode = <&tcsr_regs 0x13000>; 158 #reset-cells = <1>; 159 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 160 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 161 }; 162 }; 163 164 memory@40000000 { 165 device_type = "memory"; 166 /* We expect the bootloader to fill in the size */ 167 reg = <0 0x40000000 0 0>; 168 }; 169 170 pmu { 171 compatible = "arm,cortex-a53-pmu"; 172 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 173 }; 174 175 psci { 176 compatible = "arm,psci-1.0"; 177 method = "smc"; 178 179 cpu_pd0: power-domain-cpu0 { 180 #power-domain-cells = <0>; 181 power-domains = <&cluster_pd>; 182 domain-idle-states = <&cpu_sleep>; 183 }; 184 185 cpu_pd1: power-domain-cpu1 { 186 #power-domain-cells = <0>; 187 power-domains = <&cluster_pd>; 188 domain-idle-states = <&cpu_sleep>; 189 }; 190 191 cpu_pd2: power-domain-cpu2 { 192 #power-domain-cells = <0>; 193 power-domains = <&cluster_pd>; 194 domain-idle-states = <&cpu_sleep>; 195 }; 196 197 cpu_pd3: power-domain-cpu3 { 198 #power-domain-cells = <0>; 199 power-domains = <&cluster_pd>; 200 domain-idle-states = <&cpu_sleep>; 201 }; 202 203 cluster_pd: power-domain-cpu-cluster { 204 #power-domain-cells = <0>; 205 power-domains = <&mpm>; 206 domain-idle-states = <&cluster_sleep>; 207 }; 208 }; 209 210 rpm: remoteproc { 211 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc"; 212 213 glink-edge { 214 compatible = "qcom,glink-rpm"; 215 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 216 qcom,rpm-msg-ram = <&rpm_msg_ram>; 217 mboxes = <&apcs_glb 0>; 218 219 rpm_requests: rpm-requests { 220 compatible = "qcom,rpm-qcm2290", "qcom,glink-smd-rpm"; 221 qcom,glink-channels = "rpm_requests"; 222 223 rpmcc: clock-controller { 224 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; 225 clocks = <&xo_board>; 226 clock-names = "xo"; 227 #clock-cells = <1>; 228 }; 229 230 rpmpd: power-controller { 231 compatible = "qcom,qcm2290-rpmpd"; 232 #power-domain-cells = <1>; 233 operating-points-v2 = <&rpmpd_opp_table>; 234 235 rpmpd_opp_table: opp-table { 236 compatible = "operating-points-v2"; 237 238 rpmpd_opp_min_svs: opp1 { 239 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 240 }; 241 242 rpmpd_opp_low_svs: opp2 { 243 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 244 }; 245 246 rpmpd_opp_svs: opp3 { 247 opp-level = <RPM_SMD_LEVEL_SVS>; 248 }; 249 250 rpmpd_opp_svs_plus: opp4 { 251 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 252 }; 253 254 rpmpd_opp_nom: opp5 { 255 opp-level = <RPM_SMD_LEVEL_NOM>; 256 }; 257 258 rpmpd_opp_nom_plus: opp6 { 259 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 260 }; 261 262 rpmpd_opp_turbo: opp7 { 263 opp-level = <RPM_SMD_LEVEL_TURBO>; 264 }; 265 266 rpmpd_opp_turbo_plus: opp8 { 267 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 268 }; 269 }; 270 }; 271 }; 272 }; 273 274 mpm: interrupt-controller { 275 compatible = "qcom,mpm"; 276 qcom,rpm-msg-ram = <&apss_mpm>; 277 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 278 mboxes = <&apcs_glb 1>; 279 interrupt-controller; 280 #interrupt-cells = <2>; 281 #power-domain-cells = <0>; 282 interrupt-parent = <&intc>; 283 qcom,mpm-pin-count = <96>; 284 qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ 285 <5 296>, /* Soundwire master_irq */ 286 <12 422>, /* DWC3 ss_phy_irq */ 287 <24 79>, /* Soundwire wake_irq */ 288 <86 183>, /* MPM wake, SPMI */ 289 <90 260>; /* QUSB2_PHY DP+DM */ 290 }; 291 }; 292 293 reserved_memory: reserved-memory { 294 #address-cells = <2>; 295 #size-cells = <2>; 296 ranges; 297 298 hyp_mem: hyp@45700000 { 299 reg = <0x0 0x45700000 0x0 0x600000>; 300 no-map; 301 }; 302 303 xbl_aop_mem: xbl-aop@45e00000 { 304 reg = <0x0 0x45e00000 0x0 0x140000>; 305 no-map; 306 }; 307 308 sec_apps_mem: sec-apps@45fff000 { 309 reg = <0x0 0x45fff000 0x0 0x1000>; 310 no-map; 311 }; 312 313 smem_mem: smem@46000000 { 314 compatible = "qcom,smem"; 315 reg = <0x0 0x46000000 0x0 0x200000>; 316 no-map; 317 318 hwlocks = <&tcsr_mutex 3>; 319 qcom,rpm-msg-ram = <&rpm_msg_ram>; 320 }; 321 322 pil_modem_mem: modem@4ab00000 { 323 reg = <0x0 0x4ab00000 0x0 0x6900000>; 324 no-map; 325 }; 326 327 pil_video_mem: video@51400000 { 328 reg = <0x0 0x51400000 0x0 0x500000>; 329 no-map; 330 }; 331 332 wlan_msa_mem: wlan-msa@51900000 { 333 reg = <0x0 0x51900000 0x0 0x100000>; 334 no-map; 335 }; 336 337 pil_adsp_mem: adsp@51a00000 { 338 reg = <0x0 0x51a00000 0x0 0x1c00000>; 339 no-map; 340 }; 341 342 pil_ipa_fw_mem: ipa-fw@53600000 { 343 reg = <0x0 0x53600000 0x0 0x10000>; 344 no-map; 345 }; 346 347 pil_ipa_gsi_mem: ipa-gsi@53610000 { 348 reg = <0x0 0x53610000 0x0 0x5000>; 349 no-map; 350 }; 351 352 pil_gpu_mem: zap@53615000 { 353 compatible = "shared-dma-pool"; 354 reg = <0x0 0x53615000 0x0 0x2000>; 355 no-map; 356 }; 357 358 cont_splash_memory: framebuffer@5c000000 { 359 reg = <0x0 0x5c000000 0x0 0x00f00000>; 360 no-map; 361 }; 362 363 dfps_data_memory: dpfs-data@5cf00000 { 364 reg = <0x0 0x5cf00000 0x0 0x0100000>; 365 no-map; 366 }; 367 368 removed_mem: reserved@60000000 { 369 reg = <0x0 0x60000000 0x0 0x3900000>; 370 no-map; 371 }; 372 373 rmtfs_mem: memory@89b01000 { 374 compatible = "qcom,rmtfs-mem"; 375 reg = <0x0 0x89b01000 0x0 0x200000>; 376 no-map; 377 378 qcom,client-id = <1>; 379 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 380 }; 381 }; 382 383 smp2p-adsp { 384 compatible = "qcom,smp2p"; 385 qcom,smem = <443>, <429>; 386 387 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 388 389 mboxes = <&apcs_glb 10>; 390 391 qcom,local-pid = <0>; 392 qcom,remote-pid = <2>; 393 394 adsp_smp2p_out: master-kernel { 395 qcom,entry-name = "master-kernel"; 396 #qcom,smem-state-cells = <1>; 397 }; 398 399 adsp_smp2p_in: slave-kernel { 400 qcom,entry-name = "slave-kernel"; 401 interrupt-controller; 402 #interrupt-cells = <2>; 403 }; 404 }; 405 406 smp2p-mpss { 407 compatible = "qcom,smp2p"; 408 qcom,smem = <435>, <428>; 409 410 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 411 412 mboxes = <&apcs_glb 14>; 413 414 qcom,local-pid = <0>; 415 qcom,remote-pid = <1>; 416 417 modem_smp2p_out: master-kernel { 418 qcom,entry-name = "master-kernel"; 419 #qcom,smem-state-cells = <1>; 420 }; 421 422 modem_smp2p_in: slave-kernel { 423 qcom,entry-name = "slave-kernel"; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 }; 427 428 wlan_smp2p_in: wlan-wpss-to-ap { 429 qcom,entry-name = "wlan"; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 }; 433 }; 434 435 soc: soc@0 { 436 compatible = "simple-bus"; 437 #address-cells = <2>; 438 #size-cells = <2>; 439 ranges = <0 0 0 0 0x10 0>; 440 dma-ranges = <0 0 0 0 0x10 0>; 441 442 tcsr_mutex: hwlock@340000 { 443 compatible = "qcom,tcsr-mutex"; 444 reg = <0x0 0x00340000 0x0 0x20000>; 445 #hwlock-cells = <1>; 446 }; 447 448 tcsr_regs: syscon@3c0000 { 449 compatible = "qcom,qcm2290-tcsr", "syscon"; 450 reg = <0x0 0x003c0000 0x0 0x40000>; 451 }; 452 453 tlmm: pinctrl@500000 { 454 compatible = "qcom,qcm2290-tlmm"; 455 reg = <0x0 0x00500000 0x0 0x300000>; 456 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 457 gpio-controller; 458 gpio-ranges = <&tlmm 0 0 127>; 459 wakeup-parent = <&mpm>; 460 #gpio-cells = <2>; 461 interrupt-controller; 462 #interrupt-cells = <2>; 463 464 qup_i2c0_default: qup-i2c0-default-state { 465 pins = "gpio0", "gpio1"; 466 function = "qup0"; 467 drive-strength = <2>; 468 bias-pull-up; 469 }; 470 471 qup_i2c1_default: qup-i2c1-default-state { 472 pins = "gpio4", "gpio5"; 473 function = "qup1"; 474 drive-strength = <2>; 475 bias-pull-up; 476 }; 477 478 qup_i2c2_default: qup-i2c2-default-state { 479 pins = "gpio6", "gpio7"; 480 function = "qup2"; 481 drive-strength = <2>; 482 bias-pull-up; 483 }; 484 485 qup_i2c3_default: qup-i2c3-default-state { 486 pins = "gpio8", "gpio9"; 487 function = "qup3"; 488 drive-strength = <2>; 489 bias-pull-up; 490 }; 491 492 qup_i2c4_default: qup-i2c4-default-state { 493 pins = "gpio12", "gpio13"; 494 function = "qup4"; 495 drive-strength = <2>; 496 bias-pull-up; 497 }; 498 499 qup_i2c5_default: qup-i2c5-default-state { 500 pins = "gpio14", "gpio15"; 501 function = "qup5"; 502 drive-strength = <2>; 503 bias-pull-up; 504 }; 505 506 qup_spi0_default: qup-spi0-default-state { 507 pins = "gpio0", "gpio1","gpio2", "gpio3"; 508 function = "qup0"; 509 drive-strength = <2>; 510 bias-pull-up; 511 }; 512 513 qup_spi1_default: qup-spi1-default-state { 514 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 515 function = "qup1"; 516 drive-strength = <2>; 517 bias-pull-up; 518 }; 519 520 qup_spi2_default: qup-spi2-default-state { 521 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 522 function = "qup2"; 523 drive-strength = <2>; 524 bias-pull-up; 525 }; 526 527 qup_spi3_default: qup-spi3-default-state { 528 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 529 function = "qup3"; 530 drive-strength = <2>; 531 bias-pull-up; 532 }; 533 534 qup_spi4_default: qup-spi4-default-state { 535 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 536 function = "qup4"; 537 drive-strength = <2>; 538 bias-pull-up; 539 }; 540 541 qup_spi5_default: qup-spi5-default-state { 542 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 543 function = "qup5"; 544 drive-strength = <2>; 545 bias-pull-up; 546 }; 547 548 qup_uart0_default: qup-uart0-default-state { 549 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 550 function = "qup0"; 551 drive-strength = <2>; 552 bias-disable; 553 }; 554 555 qup_uart3_default: qup-uart3-default-state { 556 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 557 function = "qup3"; 558 drive-strength = <2>; 559 bias-disable; 560 }; 561 562 qup_uart4_default: qup-uart4-default-state { 563 pins = "gpio12", "gpio13"; 564 function = "qup4"; 565 drive-strength = <2>; 566 bias-disable; 567 }; 568 569 cci0_default: cci0-default-state { 570 pins = "gpio22", "gpio23"; 571 function = "cci_i2c"; 572 drive-strength = <2>; 573 bias-disable; 574 }; 575 576 cci1_default: cci1-default-state { 577 pins = "gpio29", "gpio30"; 578 function = "cci_i2c"; 579 drive-strength = <2>; 580 bias-disable; 581 }; 582 583 sdc1_state_on: sdc1-on-state { 584 clk-pins { 585 pins = "sdc1_clk"; 586 drive-strength = <16>; 587 bias-disable; 588 }; 589 590 cmd-pins { 591 pins = "sdc1_cmd"; 592 drive-strength = <10>; 593 bias-pull-up; 594 }; 595 596 data-pins { 597 pins = "sdc1_data"; 598 drive-strength = <10>; 599 bias-pull-up; 600 }; 601 602 rclk-pins { 603 pins = "sdc1_rclk"; 604 bias-pull-down; 605 }; 606 }; 607 608 sdc1_state_off: sdc1-off-state { 609 clk-pins { 610 pins = "sdc1_clk"; 611 drive-strength = <2>; 612 bias-disable; 613 }; 614 615 cmd-pins { 616 pins = "sdc1_cmd"; 617 drive-strength = <2>; 618 bias-pull-up; 619 }; 620 621 data-pins { 622 pins = "sdc1_data"; 623 drive-strength = <2>; 624 bias-pull-up; 625 }; 626 627 rclk-pins { 628 pins = "sdc1_rclk"; 629 bias-pull-down; 630 }; 631 }; 632 633 sdc2_state_on: sdc2-on-state { 634 clk-pins { 635 pins = "sdc2_clk"; 636 drive-strength = <16>; 637 bias-disable; 638 }; 639 640 cmd-pins { 641 pins = "sdc2_cmd"; 642 drive-strength = <10>; 643 bias-pull-up; 644 }; 645 646 data-pins { 647 pins = "sdc2_data"; 648 drive-strength = <10>; 649 bias-pull-up; 650 }; 651 }; 652 653 sdc2_state_off: sdc2-off-state { 654 clk-pins { 655 pins = "sdc2_clk"; 656 drive-strength = <2>; 657 bias-disable; 658 }; 659 660 cmd-pins { 661 pins = "sdc2_cmd"; 662 drive-strength = <2>; 663 bias-pull-up; 664 }; 665 666 data-pins { 667 pins = "sdc2_data"; 668 drive-strength = <2>; 669 bias-pull-up; 670 }; 671 }; 672 }; 673 674 gcc: clock-controller@1400000 { 675 compatible = "qcom,gcc-qcm2290"; 676 reg = <0x0 0x01400000 0x0 0x1f0000>; 677 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 678 clock-names = "bi_tcxo", "sleep_clk"; 679 #clock-cells = <1>; 680 #reset-cells = <1>; 681 #power-domain-cells = <1>; 682 }; 683 684 usb_hsphy: phy@1613000 { 685 compatible = "qcom,qcm2290-qusb2-phy"; 686 reg = <0x0 0x01613000 0x0 0x180>; 687 688 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 689 <&rpmcc RPM_SMD_XO_CLK_SRC>; 690 clock-names = "cfg_ahb", "ref"; 691 692 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 693 nvmem-cells = <&qusb2_hstx_trim>; 694 #phy-cells = <0>; 695 696 status = "disabled"; 697 }; 698 699 usb_qmpphy: phy@1615000 { 700 compatible = "qcom,qcm2290-qmp-usb3-phy"; 701 reg = <0x0 0x01615000 0x0 0x1000>; 702 703 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 704 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 705 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 706 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 707 clock-names = "cfg_ahb", 708 "ref", 709 "com_aux", 710 "pipe"; 711 712 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 713 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 714 reset-names = "phy", 715 "phy_phy"; 716 717 #clock-cells = <0>; 718 clock-output-names = "usb3_phy_pipe_clk_src"; 719 720 #phy-cells = <0>; 721 orientation-switch; 722 723 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 724 725 status = "disabled"; 726 727 ports { 728 #address-cells = <1>; 729 #size-cells = <0>; 730 731 port@0 { 732 reg = <0>; 733 734 usb_qmpphy_out: endpoint { 735 }; 736 }; 737 738 port@1 { 739 reg = <1>; 740 741 usb_qmpphy_usb_ss_in: endpoint { 742 remote-endpoint = <&usb_dwc3_ss>; 743 }; 744 }; 745 }; 746 }; 747 748 system_noc: interconnect@1880000 { 749 compatible = "qcom,qcm2290-snoc"; 750 reg = <0x0 0x01880000 0x0 0x60200>; 751 #interconnect-cells = <2>; 752 753 qup_virt: interconnect-qup { 754 compatible = "qcom,qcm2290-qup-virt"; 755 #interconnect-cells = <2>; 756 }; 757 758 mmnrt_virt: interconnect-mmnrt { 759 compatible = "qcom,qcm2290-mmnrt-virt"; 760 #interconnect-cells = <2>; 761 }; 762 763 mmrt_virt: interconnect-mmrt { 764 compatible = "qcom,qcm2290-mmrt-virt"; 765 #interconnect-cells = <2>; 766 }; 767 }; 768 769 config_noc: interconnect@1900000 { 770 compatible = "qcom,qcm2290-cnoc"; 771 reg = <0x0 0x01900000 0x0 0x8200>; 772 #interconnect-cells = <2>; 773 }; 774 775 cryptobam: dma-controller@1b04000 { 776 compatible = "qcom,bam-v1.7.0"; 777 reg = <0x0 0x01b04000 0x0 0x24000>; 778 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 780 clock-names = "bam_clk"; 781 #dma-cells = <1>; 782 qcom,ee = <0>; 783 qcom,controlled-remotely; 784 iommus = <&apps_smmu 0x0084 0x11>, 785 <&apps_smmu 0x0086 0x11>; 786 }; 787 788 crypto: crypto@1b3a000 { 789 compatible = "qcom,qcm2290-qce", "qcom,ipq4019-qce", "qcom,qce"; 790 reg = <0x0 0x01b3a000 0x0 0x6000>; 791 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 792 clock-names = "core"; 793 dmas = <&cryptobam 6>, <&cryptobam 7>; 794 dma-names = "rx", "tx"; 795 iommus = <&apps_smmu 0x0084 0x11>, 796 <&apps_smmu 0x0086 0x11>; 797 }; 798 799 qfprom@1b44000 { 800 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; 801 reg = <0x0 0x01b44000 0x0 0x3000>; 802 #address-cells = <1>; 803 #size-cells = <1>; 804 805 qusb2_hstx_trim: hstx-trim@25b { 806 reg = <0x25b 0x1>; 807 bits = <1 4>; 808 }; 809 810 gpu_speed_bin: gpu-speed-bin@2006 { 811 reg = <0x2006 0x2>; 812 bits = <5 8>; 813 }; 814 }; 815 816 pmu@1b8e300 { 817 compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon"; 818 reg = <0x0 0x01b8e300 0x0 0x600>; 819 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 820 821 operating-points-v2 = <&cpu_bwmon_opp_table>; 822 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 823 &bimc SLAVE_EBI1 RPM_ACTIVE_TAG>; 824 825 cpu_bwmon_opp_table: opp-table { 826 compatible = "operating-points-v2"; 827 828 opp-0 { 829 opp-peak-kBps = <(200 * 4 * 1000)>; 830 }; 831 832 opp-1 { 833 opp-peak-kBps = <(300 * 4 * 1000)>; 834 }; 835 836 opp-2 { 837 opp-peak-kBps = <(451 * 4 * 1000)>; 838 }; 839 840 opp-3 { 841 opp-peak-kBps = <(547 * 4 * 1000)>; 842 }; 843 844 opp-4 { 845 opp-peak-kBps = <(681 * 4 * 1000)>; 846 }; 847 848 opp-5 { 849 opp-peak-kBps = <(768 * 4 * 1000)>; 850 }; 851 852 opp-6 { 853 opp-peak-kBps = <(1017 * 4 * 1000)>; 854 }; 855 856 opp-7 { 857 opp-peak-kBps = <(1353 * 4 * 1000)>; 858 }; 859 860 opp-8 { 861 opp-peak-kBps = <(1555 * 4 * 1000)>; 862 }; 863 864 opp-9 { 865 opp-peak-kBps = <(1804 * 4 * 1000)>; 866 }; 867 }; 868 }; 869 870 spmi_bus: spmi@1c40000 { 871 compatible = "qcom,spmi-pmic-arb"; 872 reg = <0x0 0x01c40000 0x0 0x1100>, 873 <0x0 0x01e00000 0x0 0x2000000>, 874 <0x0 0x03e00000 0x0 0x100000>, 875 <0x0 0x03f00000 0x0 0xa0000>, 876 <0x0 0x01c0a000 0x0 0x26000>; 877 reg-names = "core", 878 "chnls", 879 "obsrvr", 880 "intr", 881 "cnfg"; 882 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; 883 interrupt-names = "periph_irq"; 884 qcom,ee = <0>; 885 qcom,channel = <0>; 886 #address-cells = <2>; 887 #size-cells = <0>; 888 interrupt-controller; 889 #interrupt-cells = <4>; 890 }; 891 892 tsens0: thermal-sensor@4411000 { 893 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; 894 reg = <0x0 0x04411000 0x0 0x1ff>, 895 <0x0 0x04410000 0x0 0x8>; 896 #qcom,sensors = <10>; 897 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, 898 <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 899 interrupt-names = "uplow", "critical"; 900 #thermal-sensor-cells = <1>; 901 }; 902 903 rng: rng@4453000 { 904 compatible = "qcom,prng-ee"; 905 reg = <0x0 0x04453000 0x0 0x1000>; 906 clocks = <&rpmcc RPM_SMD_HWKM_CLK>; 907 clock-names = "core"; 908 }; 909 910 bimc: interconnect@4480000 { 911 compatible = "qcom,qcm2290-bimc"; 912 reg = <0x0 0x04480000 0x0 0x80000>; 913 #interconnect-cells = <2>; 914 }; 915 916 rpm_msg_ram: sram@45f0000 { 917 compatible = "qcom,rpm-msg-ram", "mmio-sram"; 918 reg = <0x0 0x045f0000 0x0 0x7000>; 919 #address-cells = <1>; 920 #size-cells = <1>; 921 ranges = <0 0x0 0x045f0000 0x7000>; 922 923 apss_mpm: sram@1b8 { 924 reg = <0x1b8 0x48>; 925 }; 926 }; 927 928 sram@4690000 { 929 compatible = "qcom,rpm-stats"; 930 reg = <0x0 0x04690000 0x0 0x10000>; 931 }; 932 933 sdhc_1: mmc@4744000 { 934 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 935 reg = <0x0 0x04744000 0x0 0x1000>, 936 <0x0 0x04745000 0x0 0x1000>, 937 <0x0 0x04748000 0x0 0x8000>; 938 reg-names = "hc", 939 "cqhci", 940 "ice"; 941 942 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 944 interrupt-names = "hc_irq", "pwr_irq"; 945 946 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 947 <&gcc GCC_SDCC1_APPS_CLK>, 948 <&rpmcc RPM_SMD_XO_CLK_SRC>, 949 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 950 clock-names = "iface", 951 "core", 952 "xo", 953 "ice"; 954 955 resets = <&gcc GCC_SDCC1_BCR>; 956 957 power-domains = <&rpmpd QCM2290_VDDCX>; 958 operating-points-v2 = <&sdhc1_opp_table>; 959 iommus = <&apps_smmu 0xc0 0x0>; 960 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 961 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 962 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 963 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; 964 interconnect-names = "sdhc-ddr", 965 "cpu-sdhc"; 966 967 qcom,dll-config = <0x000f642c>; 968 qcom,ddr-config = <0x80040868>; 969 bus-width = <8>; 970 971 mmc-ddr-1_8v; 972 mmc-hs200-1_8v; 973 mmc-hs400-1_8v; 974 mmc-hs400-enhanced-strobe; 975 976 status = "disabled"; 977 978 sdhc1_opp_table: opp-table { 979 compatible = "operating-points-v2"; 980 981 opp-100000000 { 982 opp-hz = /bits/ 64 <100000000>; 983 required-opps = <&rpmpd_opp_low_svs>; 984 opp-peak-kBps = <250000 133320>; 985 opp-avg-kBps = <102400 65000>; 986 }; 987 988 opp-192000000 { 989 opp-hz = /bits/ 64 <192000000>; 990 required-opps = <&rpmpd_opp_low_svs>; 991 opp-peak-kBps = <800000 300000>; 992 opp-avg-kBps = <204800 200000>; 993 }; 994 995 opp-384000000 { 996 opp-hz = /bits/ 64 <384000000>; 997 required-opps = <&rpmpd_opp_svs_plus>; 998 opp-peak-kBps = <800000 300000>; 999 opp-avg-kBps = <204800 200000>; 1000 }; 1001 }; 1002 }; 1003 1004 sdhc_2: mmc@4784000 { 1005 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 1006 reg = <0x0 0x04784000 0x0 0x1000>; 1007 reg-names = "hc"; 1008 1009 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1011 interrupt-names = "hc_irq", "pwr_irq"; 1012 1013 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1014 <&gcc GCC_SDCC2_APPS_CLK>, 1015 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1016 clock-names = "iface", 1017 "core", 1018 "xo"; 1019 1020 resets = <&gcc GCC_SDCC2_BCR>; 1021 1022 power-domains = <&rpmpd QCM2290_VDDCX>; 1023 operating-points-v2 = <&sdhc2_opp_table>; 1024 iommus = <&apps_smmu 0xa0 0x0>; 1025 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG 1026 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1027 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1028 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; 1029 interconnect-names = "sdhc-ddr", 1030 "cpu-sdhc"; 1031 1032 qcom,dll-config = <0x0007642c>; 1033 qcom,ddr-config = <0x80040868>; 1034 bus-width = <4>; 1035 1036 status = "disabled"; 1037 1038 sdhc2_opp_table: opp-table { 1039 compatible = "operating-points-v2"; 1040 1041 opp-100000000 { 1042 opp-hz = /bits/ 64 <100000000>; 1043 required-opps = <&rpmpd_opp_low_svs>; 1044 opp-peak-kBps = <250000 133320>; 1045 opp-avg-kBps = <261438 150000>; 1046 }; 1047 1048 opp-202000000 { 1049 opp-hz = /bits/ 64 <202000000>; 1050 required-opps = <&rpmpd_opp_svs_plus>; 1051 opp-peak-kBps = <800000 300000>; 1052 opp-avg-kBps = <261438 300000>; 1053 }; 1054 }; 1055 }; 1056 1057 gpi_dma0: dma-controller@4a00000 { 1058 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; 1059 reg = <0x0 0x04a00000 0x0 0x60000>; 1060 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1070 dma-channels = <10>; 1071 dma-channel-mask = <0x1f>; 1072 iommus = <&apps_smmu 0xf6 0x0>; 1073 #dma-cells = <3>; 1074 status = "disabled"; 1075 }; 1076 1077 qupv3_id_0: geniqup@4ac0000 { 1078 compatible = "qcom,geni-se-qup"; 1079 reg = <0x0 0x04ac0000 0x0 0x2000>; 1080 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1081 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1082 clock-names = "m-ahb", "s-ahb"; 1083 iommus = <&apps_smmu 0xe3 0x0>; 1084 #address-cells = <2>; 1085 #size-cells = <2>; 1086 ranges; 1087 status = "disabled"; 1088 1089 i2c0: i2c@4a80000 { 1090 compatible = "qcom,geni-i2c"; 1091 reg = <0x0 0x04a80000 0x0 0x4000>; 1092 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1094 clock-names = "se"; 1095 pinctrl-0 = <&qup_i2c0_default>; 1096 pinctrl-names = "default"; 1097 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1098 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1099 dma-names = "tx", "rx"; 1100 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1101 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1102 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1103 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1104 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1105 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1106 interconnect-names = "qup-core", 1107 "qup-config", 1108 "qup-memory"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 status = "disabled"; 1112 }; 1113 1114 spi0: spi@4a80000 { 1115 compatible = "qcom,geni-spi"; 1116 reg = <0x0 0x04a80000 0x0 0x4000>; 1117 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1119 clock-names = "se"; 1120 pinctrl-0 = <&qup_spi0_default>; 1121 pinctrl-names = "default"; 1122 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1123 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1124 dma-names = "tx", "rx"; 1125 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1126 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1127 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1128 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1129 interconnect-names = "qup-core", 1130 "qup-config"; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 status = "disabled"; 1134 }; 1135 1136 uart0: serial@4a80000 { 1137 compatible = "qcom,geni-uart"; 1138 reg = <0x0 0x04a80000 0x0 0x4000>; 1139 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1141 clock-names = "se"; 1142 pinctrl-0 = <&qup_uart0_default>; 1143 pinctrl-names = "default"; 1144 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1145 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1146 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1147 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1148 interconnect-names = "qup-core", 1149 "qup-config"; 1150 status = "disabled"; 1151 }; 1152 1153 i2c1: i2c@4a84000 { 1154 compatible = "qcom,geni-i2c"; 1155 reg = <0x0 0x04a84000 0x0 0x4000>; 1156 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1157 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1158 clock-names = "se"; 1159 pinctrl-0 = <&qup_i2c1_default>; 1160 pinctrl-names = "default"; 1161 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1162 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1163 dma-names = "tx", "rx"; 1164 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1165 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1166 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1167 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1168 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1169 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1170 interconnect-names = "qup-core", 1171 "qup-config", 1172 "qup-memory"; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 status = "disabled"; 1176 }; 1177 1178 spi1: spi@4a84000 { 1179 compatible = "qcom,geni-spi"; 1180 reg = <0x0 0x04a84000 0x0 0x4000>; 1181 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1183 clock-names = "se"; 1184 pinctrl-0 = <&qup_spi1_default>; 1185 pinctrl-names = "default"; 1186 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1187 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1188 dma-names = "tx", "rx"; 1189 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1190 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1191 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1192 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1193 interconnect-names = "qup-core", 1194 "qup-config"; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 status = "disabled"; 1198 }; 1199 1200 i2c2: i2c@4a88000 { 1201 compatible = "qcom,geni-i2c"; 1202 reg = <0x0 0x04a88000 0x0 0x4000>; 1203 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1204 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1205 clock-names = "se"; 1206 pinctrl-0 = <&qup_i2c2_default>; 1207 pinctrl-names = "default"; 1208 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1209 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1210 dma-names = "tx", "rx"; 1211 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1212 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1213 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1214 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1215 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1216 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1217 interconnect-names = "qup-core", 1218 "qup-config", 1219 "qup-memory"; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 status = "disabled"; 1223 }; 1224 1225 spi2: spi@4a88000 { 1226 compatible = "qcom,geni-spi"; 1227 reg = <0x0 0x04a88000 0x0 0x4000>; 1228 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1229 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1230 clock-names = "se"; 1231 pinctrl-0 = <&qup_spi2_default>; 1232 pinctrl-names = "default"; 1233 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1234 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1235 dma-names = "tx", "rx"; 1236 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1237 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1238 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1239 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1240 interconnect-names = "qup-core", 1241 "qup-config"; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 status = "disabled"; 1245 }; 1246 1247 i2c3: i2c@4a8c000 { 1248 compatible = "qcom,geni-i2c"; 1249 reg = <0x0 0x04a8c000 0x0 0x4000>; 1250 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1251 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1252 clock-names = "se"; 1253 pinctrl-0 = <&qup_i2c3_default>; 1254 pinctrl-names = "default"; 1255 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1256 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1257 dma-names = "tx", "rx"; 1258 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1259 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1260 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1261 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1262 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1263 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1264 interconnect-names = "qup-core", 1265 "qup-config", 1266 "qup-memory"; 1267 #address-cells = <1>; 1268 #size-cells = <0>; 1269 status = "disabled"; 1270 }; 1271 1272 spi3: spi@4a8c000 { 1273 compatible = "qcom,geni-spi"; 1274 reg = <0x0 0x04a8c000 0x0 0x4000>; 1275 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1276 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1277 clock-names = "se"; 1278 pinctrl-0 = <&qup_spi3_default>; 1279 pinctrl-names = "default"; 1280 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1281 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1282 dma-names = "tx", "rx"; 1283 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1284 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1285 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1286 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1287 interconnect-names = "qup-core", 1288 "qup-config"; 1289 #address-cells = <1>; 1290 #size-cells = <0>; 1291 status = "disabled"; 1292 }; 1293 1294 uart3: serial@4a8c000 { 1295 compatible = "qcom,geni-uart"; 1296 reg = <0x0 0x04a8c000 0x0 0x4000>; 1297 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1298 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1299 clock-names = "se"; 1300 pinctrl-0 = <&qup_uart3_default>; 1301 pinctrl-names = "default"; 1302 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1303 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1304 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1305 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1306 interconnect-names = "qup-core", 1307 "qup-config"; 1308 status = "disabled"; 1309 }; 1310 1311 i2c4: i2c@4a90000 { 1312 compatible = "qcom,geni-i2c"; 1313 reg = <0x0 0x04a90000 0x0 0x4000>; 1314 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1315 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1316 clock-names = "se"; 1317 pinctrl-0 = <&qup_i2c4_default>; 1318 pinctrl-names = "default"; 1319 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1320 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1321 dma-names = "tx", "rx"; 1322 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1323 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1324 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1325 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1326 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1327 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1328 interconnect-names = "qup-core", 1329 "qup-config", 1330 "qup-memory"; 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 status = "disabled"; 1334 }; 1335 1336 spi4: spi@4a90000 { 1337 compatible = "qcom,geni-spi"; 1338 reg = <0x0 0x04a90000 0x0 0x4000>; 1339 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1340 clock-names = "se"; 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_spi4_default>; 1344 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1345 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1346 dma-names = "tx", "rx"; 1347 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1348 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1349 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1350 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1351 interconnect-names = "qup-core", 1352 "qup-config"; 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 status = "disabled"; 1356 }; 1357 1358 uart4: serial@4a90000 { 1359 compatible = "qcom,geni-uart"; 1360 reg = <0x0 0x04a90000 0x0 0x4000>; 1361 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1362 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1363 clock-names = "se"; 1364 pinctrl-0 = <&qup_uart4_default>; 1365 pinctrl-names = "default"; 1366 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1367 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1368 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1369 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1370 interconnect-names = "qup-core", 1371 "qup-config"; 1372 status = "disabled"; 1373 }; 1374 1375 i2c5: i2c@4a94000 { 1376 compatible = "qcom,geni-i2c"; 1377 reg = <0x0 0x04a94000 0x0 0x4000>; 1378 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1379 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1380 clock-names = "se"; 1381 pinctrl-0 = <&qup_i2c5_default>; 1382 pinctrl-names = "default"; 1383 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1384 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1385 dma-names = "tx", "rx"; 1386 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1387 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1388 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1389 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1390 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1391 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1392 interconnect-names = "qup-core", 1393 "qup-config", 1394 "qup-memory"; 1395 #address-cells = <1>; 1396 #size-cells = <0>; 1397 status = "disabled"; 1398 }; 1399 1400 spi5: spi@4a94000 { 1401 compatible = "qcom,geni-spi"; 1402 reg = <0x0 0x04a94000 0x0 0x4000>; 1403 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1404 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1405 clock-names = "se"; 1406 pinctrl-0 = <&qup_spi5_default>; 1407 pinctrl-names = "default"; 1408 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1409 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1410 dma-names = "tx", "rx"; 1411 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1412 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1413 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1414 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1415 interconnect-names = "qup-core", 1416 "qup-config"; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 status = "disabled"; 1420 }; 1421 }; 1422 1423 usb: usb@4ef8800 { 1424 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; 1425 reg = <0x0 0x04ef8800 0x0 0x400>; 1426 interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1427 <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; 1428 interrupt-names = "hs_phy_irq", 1429 "ss_phy_irq"; 1430 1431 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1432 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1433 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1434 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1435 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1436 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1437 clock-names = "cfg_noc", 1438 "core", 1439 "iface", 1440 "sleep", 1441 "mock_utmi", 1442 "xo"; 1443 1444 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1445 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1446 assigned-clock-rates = <19200000>, <133333333>; 1447 1448 resets = <&gcc GCC_USB30_PRIM_BCR>; 1449 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1450 /* TODO: USB<->IPA path */ 1451 interconnects = <&system_noc MASTER_USB3_0 RPM_ALWAYS_TAG 1452 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1453 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1454 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; 1455 interconnect-names = "usb-ddr", 1456 "apps-usb"; 1457 wakeup-source; 1458 1459 #address-cells = <2>; 1460 #size-cells = <2>; 1461 ranges; 1462 1463 status = "disabled"; 1464 1465 usb_dwc3: usb@4e00000 { 1466 compatible = "snps,dwc3"; 1467 reg = <0x0 0x04e00000 0x0 0xcd00>; 1468 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1469 phys = <&usb_hsphy>, <&usb_qmpphy>; 1470 phy-names = "usb2-phy", "usb3-phy"; 1471 iommus = <&apps_smmu 0x120 0x0>; 1472 snps,dis_u2_susphy_quirk; 1473 snps,dis_enblslpm_quirk; 1474 snps,has-lpm-erratum; 1475 snps,hird-threshold = /bits/ 8 <0x10>; 1476 snps,usb3_lpm_capable; 1477 snps,parkmode-disable-ss-quirk; 1478 maximum-speed = "super-speed"; 1479 dr_mode = "otg"; 1480 usb-role-switch; 1481 1482 ports { 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 1486 port@0 { 1487 reg = <0>; 1488 1489 usb_dwc3_hs: endpoint { 1490 }; 1491 }; 1492 1493 port@1 { 1494 reg = <1>; 1495 1496 usb_dwc3_ss: endpoint { 1497 remote-endpoint = <&usb_qmpphy_usb_ss_in>; 1498 }; 1499 }; 1500 }; 1501 }; 1502 }; 1503 1504 gpu: gpu@5900000 { 1505 compatible = "qcom,adreno-07000200", "qcom,adreno"; 1506 reg = <0x0 0x05900000 0x0 0x40000>; 1507 reg-names = "kgsl_3d0_reg_memory"; 1508 1509 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1510 1511 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1512 <&gpucc GPU_CC_AHB_CLK>, 1513 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1514 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1515 <&gpucc GPU_CC_CX_GMU_CLK>, 1516 <&gpucc GPU_CC_CXO_CLK>; 1517 clock-names = "core", 1518 "iface", 1519 "mem_iface", 1520 "alt_mem_iface", 1521 "gmu", 1522 "xo"; 1523 1524 interconnects = <&bimc MASTER_GFX3D RPM_ALWAYS_TAG 1525 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1526 interconnect-names = "gfx-mem"; 1527 1528 iommus = <&adreno_smmu 0 1>, 1529 <&adreno_smmu 2 0>; 1530 operating-points-v2 = <&gpu_opp_table>; 1531 power-domains = <&rpmpd QCM2290_VDDCX>; 1532 qcom,gmu = <&gmu_wrapper>; 1533 1534 nvmem-cells = <&gpu_speed_bin>; 1535 nvmem-cell-names = "speed_bin"; 1536 #cooling-cells = <2>; 1537 1538 status = "disabled"; 1539 1540 zap-shader { 1541 memory-region = <&pil_gpu_mem>; 1542 }; 1543 1544 gpu_opp_table: opp-table { 1545 compatible = "operating-points-v2"; 1546 1547 /* TODO: Scale RPM_SMD_BIMC_GPU_CLK w/ turbo freqs */ 1548 opp-1123200000 { 1549 opp-hz = /bits/ 64 <1123200000>; 1550 required-opps = <&rpmpd_opp_turbo_plus>; 1551 opp-peak-kBps = <6881000>; 1552 opp-supported-hw = <0x3>; 1553 turbo-mode; 1554 }; 1555 1556 opp-1017600000 { 1557 opp-hz = /bits/ 64 <1017600000>; 1558 required-opps = <&rpmpd_opp_turbo>; 1559 opp-peak-kBps = <6881000>; 1560 opp-supported-hw = <0x3>; 1561 turbo-mode; 1562 }; 1563 1564 opp-921600000 { 1565 opp-hz = /bits/ 64 <921600000>; 1566 required-opps = <&rpmpd_opp_nom_plus>; 1567 opp-peak-kBps = <6881000>; 1568 opp-supported-hw = <0x3>; 1569 }; 1570 1571 opp-844800000 { 1572 opp-hz = /bits/ 64 <844800000>; 1573 required-opps = <&rpmpd_opp_nom>; 1574 opp-peak-kBps = <6881000>; 1575 opp-supported-hw = <0x7>; 1576 }; 1577 1578 opp-672000000 { 1579 opp-hz = /bits/ 64 <672000000>; 1580 required-opps = <&rpmpd_opp_svs_plus>; 1581 opp-peak-kBps = <3879000>; 1582 opp-supported-hw = <0xf>; 1583 }; 1584 1585 opp-537600000 { 1586 opp-hz = /bits/ 64 <537600000>; 1587 required-opps = <&rpmpd_opp_svs>; 1588 opp-peak-kBps = <2929000>; 1589 opp-supported-hw = <0xf>; 1590 }; 1591 1592 opp-355200000 { 1593 opp-hz = /bits/ 64 <355200000>; 1594 required-opps = <&rpmpd_opp_low_svs>; 1595 opp-peak-kBps = <1720000>; 1596 opp-supported-hw = <0xf>; 1597 }; 1598 }; 1599 }; 1600 1601 gmu_wrapper: gmu@596a000 { 1602 compatible = "qcom,adreno-gmu-wrapper"; 1603 reg = <0x0 0x0596a000 0x0 0x30000>; 1604 reg-names = "gmu"; 1605 power-domains = <&gpucc GPU_CX_GDSC>, 1606 <&gpucc GPU_GX_GDSC>; 1607 power-domain-names = "cx", 1608 "gx"; 1609 }; 1610 1611 gpucc: clock-controller@5990000 { 1612 compatible = "qcom,qcm2290-gpucc"; 1613 reg = <0x0 0x05990000 0x0 0x9000>; 1614 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1615 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1616 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1617 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1618 power-domains = <&rpmpd QCM2290_VDDCX>; 1619 required-opps = <&rpmpd_opp_low_svs>; 1620 #clock-cells = <1>; 1621 #reset-cells = <1>; 1622 #power-domain-cells = <1>; 1623 }; 1624 1625 adreno_smmu: iommu@59a0000 { 1626 compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu", 1627 "qcom,smmu-500", "arm,mmu-500"; 1628 reg = <0x0 0x059a0000 0x0 0x10000>; 1629 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1638 1639 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1640 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1641 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1642 clock-names = "mem", 1643 "hlos", 1644 "iface"; 1645 1646 power-domains = <&gpucc GPU_CX_GDSC>; 1647 1648 #global-interrupts = <1>; 1649 #iommu-cells = <2>; 1650 }; 1651 1652 cci: cci@5c1b000 { 1653 compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci"; 1654 reg = <0x0 0x5c1b000 0x0 0x1000>; 1655 1656 interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>; 1657 1658 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>; 1659 clock-names = "ahb", "cci"; 1660 assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>; 1661 assigned-clock-rates = <37500000>; 1662 1663 power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; 1664 1665 pinctrl-0 = <&cci0_default &cci1_default>; 1666 pinctrl-names = "default"; 1667 1668 #address-cells = <1>; 1669 #size-cells = <0>; 1670 1671 status = "disabled"; 1672 1673 cci_i2c0: i2c-bus@0 { 1674 reg = <0>; 1675 clock-frequency = <400000>; 1676 #address-cells = <1>; 1677 #size-cells = <0>; 1678 }; 1679 1680 cci_i2c1: i2c-bus@1 { 1681 reg = <1>; 1682 clock-frequency = <400000>; 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 }; 1686 }; 1687 1688 camss: camss@5c6e000 { 1689 compatible = "qcom,qcm2290-camss"; 1690 1691 reg = <0x0 0x5c6e000 0x0 0x1000>, 1692 <0x0 0x5c75000 0x0 0x1000>, 1693 <0x0 0x5c52000 0x0 0x1000>, 1694 <0x0 0x5c53000 0x0 0x1000>, 1695 <0x0 0x5c66000 0x0 0x400>, 1696 <0x0 0x5c68000 0x0 0x400>, 1697 <0x0 0x5c11000 0x0 0x1000>, 1698 <0x0 0x5c6f000 0x0 0x4000>, 1699 <0x0 0x5c76000 0x0 0x4000>; 1700 reg-names = "csid0", 1701 "csid1", 1702 "csiphy0", 1703 "csiphy1", 1704 "csitpg0", 1705 "csitpg1", 1706 "top", 1707 "vfe0", 1708 "vfe1"; 1709 1710 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 1711 <&gcc GCC_CAMSS_AXI_CLK>, 1712 <&gcc GCC_CAMSS_NRT_AXI_CLK>, 1713 <&gcc GCC_CAMSS_RT_AXI_CLK>, 1714 <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, 1715 <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, 1716 <&gcc GCC_CAMSS_CPHY_0_CLK>, 1717 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1718 <&gcc GCC_CAMSS_CPHY_1_CLK>, 1719 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1720 <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1721 <&gcc GCC_CAMSS_TFE_0_CLK>, 1722 <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, 1723 <&gcc GCC_CAMSS_TFE_1_CLK>, 1724 <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK> ; 1725 clock-names = "ahb", 1726 "axi", 1727 "camnoc_nrt_axi", 1728 "camnoc_rt_axi", 1729 "csi0", 1730 "csi1", 1731 "csiphy0", 1732 "csiphy0_timer", 1733 "csiphy1", 1734 "csiphy1_timer", 1735 "top_ahb", 1736 "vfe0", 1737 "vfe0_cphy_rx", 1738 "vfe1", 1739 "vfe1_cphy_rx"; 1740 1741 interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, 1742 <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, 1743 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, 1744 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 1745 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1746 <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>, 1747 <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, 1748 <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; 1749 interrupt-names = "csid0", 1750 "csid1", 1751 "csiphy0", 1752 "csiphy1", 1753 "csitpg0", 1754 "csitpg1", 1755 "vfe0", 1756 "vfe1"; 1757 1758 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 1759 &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>, 1760 <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG 1761 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1762 <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG 1763 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1764 interconnect-names = "ahb", 1765 "hf_mnoc", 1766 "sf_mnoc"; 1767 1768 iommus = <&apps_smmu 0x400 0x0>, 1769 <&apps_smmu 0x800 0x0>, 1770 <&apps_smmu 0x820 0x0>, 1771 <&apps_smmu 0x840 0x0>; 1772 1773 power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; 1774 1775 status = "disabled"; 1776 1777 ports { 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 1781 port@0 { 1782 reg = <0>; 1783 }; 1784 1785 port@1 { 1786 reg = <1>; 1787 }; 1788 }; 1789 }; 1790 1791 mdss: display-subsystem@5e00000 { 1792 compatible = "qcom,qcm2290-mdss"; 1793 reg = <0x0 0x05e00000 0x0 0x1000>; 1794 reg-names = "mdss"; 1795 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1796 interrupt-controller; 1797 #interrupt-cells = <1>; 1798 1799 clocks = <&gcc GCC_DISP_AHB_CLK>, 1800 <&gcc GCC_DISP_HF_AXI_CLK>, 1801 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1802 clock-names = "iface", 1803 "bus", 1804 "core"; 1805 1806 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 1807 1808 power-domains = <&dispcc MDSS_GDSC>; 1809 1810 iommus = <&apps_smmu 0x420 0x2>, 1811 <&apps_smmu 0x421 0x0>; 1812 interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG 1813 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1814 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1815 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; 1816 interconnect-names = "mdp0-mem", 1817 "cpu-cfg"; 1818 1819 #address-cells = <2>; 1820 #size-cells = <2>; 1821 ranges; 1822 1823 status = "disabled"; 1824 1825 mdp: display-controller@5e01000 { 1826 compatible = "qcom,qcm2290-dpu"; 1827 reg = <0x0 0x05e01000 0x0 0x8f000>, 1828 <0x0 0x05eb0000 0x0 0x3000>; 1829 reg-names = "mdp", 1830 "vbif"; 1831 1832 interrupt-parent = <&mdss>; 1833 interrupts = <0>; 1834 1835 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1836 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1837 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1838 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1839 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1840 clock-names = "bus", 1841 "iface", 1842 "core", 1843 "lut", 1844 "vsync"; 1845 1846 operating-points-v2 = <&mdp_opp_table>; 1847 power-domains = <&rpmpd QCM2290_VDDCX>; 1848 1849 ports { 1850 #address-cells = <1>; 1851 #size-cells = <0>; 1852 1853 port@0 { 1854 reg = <0>; 1855 dpu_intf1_out: endpoint { 1856 remote-endpoint = <&mdss_dsi0_in>; 1857 }; 1858 }; 1859 }; 1860 1861 mdp_opp_table: opp-table { 1862 compatible = "operating-points-v2"; 1863 1864 opp-19200000 { 1865 opp-hz = /bits/ 64 <19200000>; 1866 required-opps = <&rpmpd_opp_min_svs>; 1867 }; 1868 1869 opp-192000000 { 1870 opp-hz = /bits/ 64 <192000000>; 1871 required-opps = <&rpmpd_opp_low_svs>; 1872 }; 1873 1874 opp-256000000 { 1875 opp-hz = /bits/ 64 <256000000>; 1876 required-opps = <&rpmpd_opp_svs>; 1877 }; 1878 1879 opp-307200000 { 1880 opp-hz = /bits/ 64 <307200000>; 1881 required-opps = <&rpmpd_opp_svs_plus>; 1882 }; 1883 1884 opp-384000000 { 1885 opp-hz = /bits/ 64 <384000000>; 1886 required-opps = <&rpmpd_opp_nom>; 1887 }; 1888 }; 1889 }; 1890 1891 mdss_dsi0: dsi@5e94000 { 1892 compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1893 reg = <0x0 0x05e94000 0x0 0x400>; 1894 reg-names = "dsi_ctrl"; 1895 1896 interrupt-parent = <&mdss>; 1897 interrupts = <4>; 1898 1899 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1900 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1901 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1902 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1903 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1904 <&gcc GCC_DISP_HF_AXI_CLK>; 1905 clock-names = "byte", 1906 "byte_intf", 1907 "pixel", 1908 "core", 1909 "iface", 1910 "bus"; 1911 1912 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1913 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1914 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1915 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1916 1917 operating-points-v2 = <&dsi_opp_table>; 1918 power-domains = <&rpmpd QCM2290_VDDCX>; 1919 phys = <&mdss_dsi0_phy>; 1920 1921 #address-cells = <1>; 1922 #size-cells = <0>; 1923 1924 status = "disabled"; 1925 1926 dsi_opp_table: opp-table { 1927 compatible = "operating-points-v2"; 1928 1929 opp-19200000 { 1930 opp-hz = /bits/ 64 <19200000>; 1931 required-opps = <&rpmpd_opp_min_svs>; 1932 }; 1933 1934 opp-164000000 { 1935 opp-hz = /bits/ 64 <164000000>; 1936 required-opps = <&rpmpd_opp_low_svs>; 1937 }; 1938 1939 opp-187500000 { 1940 opp-hz = /bits/ 64 <187500000>; 1941 required-opps = <&rpmpd_opp_svs>; 1942 }; 1943 }; 1944 1945 ports { 1946 #address-cells = <1>; 1947 #size-cells = <0>; 1948 1949 port@0 { 1950 reg = <0>; 1951 1952 mdss_dsi0_in: endpoint { 1953 remote-endpoint = <&dpu_intf1_out>; 1954 }; 1955 }; 1956 1957 port@1 { 1958 reg = <1>; 1959 1960 mdss_dsi0_out: endpoint { 1961 }; 1962 }; 1963 }; 1964 }; 1965 1966 mdss_dsi0_phy: phy@5e94400 { 1967 compatible = "qcom,dsi-phy-14nm-2290"; 1968 reg = <0x0 0x05e94400 0x0 0x100>, 1969 <0x0 0x05e94500 0x0 0x300>, 1970 <0x0 0x05e94800 0x0 0x188>; 1971 reg-names = "dsi_phy", 1972 "dsi_phy_lane", 1973 "dsi_pll"; 1974 1975 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1976 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1977 clock-names = "iface", 1978 "ref"; 1979 1980 power-domains = <&rpmpd QCM2290_VDDMX>; 1981 required-opps = <&rpmpd_opp_nom>; 1982 1983 #clock-cells = <1>; 1984 #phy-cells = <0>; 1985 1986 status = "disabled"; 1987 }; 1988 }; 1989 1990 dispcc: clock-controller@5f00000 { 1991 compatible = "qcom,qcm2290-dispcc"; 1992 reg = <0x0 0x05f00000 0x0 0x20000>; 1993 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1994 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 1995 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1996 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 1997 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1998 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1999 clock-names = "bi_tcxo", 2000 "bi_tcxo_ao", 2001 "gcc_disp_gpll0_clk_src", 2002 "gcc_disp_gpll0_div_clk_src", 2003 "dsi0_phy_pll_out_byteclk", 2004 "dsi0_phy_pll_out_dsiclk"; 2005 #power-domain-cells = <1>; 2006 #clock-cells = <1>; 2007 #reset-cells = <1>; 2008 }; 2009 2010 remoteproc_mpss: remoteproc@6080000 { 2011 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; 2012 reg = <0x0 0x06080000 0x0 0x100>; 2013 2014 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 2015 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2016 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2017 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2018 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2019 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2020 interrupt-names = "wdog", 2021 "fatal", 2022 "ready", 2023 "handover", 2024 "stop-ack", 2025 "shutdown-ack"; 2026 2027 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2028 clock-names = "xo"; 2029 2030 power-domains = <&rpmpd QCM2290_VDDCX>; 2031 2032 memory-region = <&pil_modem_mem>; 2033 2034 qcom,smem-states = <&modem_smp2p_out 0>; 2035 qcom,smem-state-names = "stop"; 2036 2037 status = "disabled"; 2038 2039 glink-edge { 2040 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 2041 label = "mpss"; 2042 qcom,remote-pid = <1>; 2043 mboxes = <&apcs_glb 12>; 2044 }; 2045 }; 2046 2047 remoteproc_adsp: remoteproc@ab00000 { 2048 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; 2049 reg = <0x0 0x0ab00000 0x0 0x100>; 2050 2051 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2052 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2053 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2054 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2055 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2056 interrupt-names = "wdog", 2057 "fatal", 2058 "ready", 2059 "handover", 2060 "stop-ack"; 2061 2062 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2063 clock-names = "xo"; 2064 2065 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, 2066 <&rpmpd QCM2290_VDD_LPI_MX>; 2067 2068 memory-region = <&pil_adsp_mem>; 2069 2070 qcom,smem-states = <&adsp_smp2p_out 0>; 2071 qcom,smem-state-names = "stop"; 2072 2073 status = "disabled"; 2074 2075 glink-edge { 2076 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2077 label = "lpass"; 2078 qcom,remote-pid = <2>; 2079 mboxes = <&apcs_glb 8>; 2080 }; 2081 }; 2082 2083 apps_smmu: iommu@c600000 { 2084 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2085 reg = <0x0 0x0c600000 0x0 0x80000>; 2086 #iommu-cells = <2>; 2087 #global-interrupts = <1>; 2088 2089 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2128 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2154 }; 2155 2156 venus: video-codec@5a00000 { 2157 compatible = "qcom,qcm2290-venus"; 2158 reg = <0 0x5a00000 0 0xf0000>; 2159 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 2160 2161 power-domains = <&gcc GCC_VENUS_GDSC>, 2162 <&gcc GCC_VCODEC0_GDSC>, 2163 <&rpmpd QCM2290_VDDCX>; 2164 power-domain-names = "venus", 2165 "vcodec0", 2166 "cx"; 2167 operating-points-v2 = <&venus_opp_table>; 2168 2169 clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, 2170 <&gcc GCC_VIDEO_AHB_CLK>, 2171 <&gcc GCC_VENUS_CTL_AXI_CLK>, 2172 <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>, 2173 <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, 2174 <&gcc GCC_VCODEC0_AXI_CLK>; 2175 clock-names = "core", 2176 "iface", 2177 "bus", 2178 "throttle", 2179 "vcodec0_core", 2180 "vcodec0_bus"; 2181 2182 memory-region = <&pil_video_mem>; 2183 iommus = <&apps_smmu 0x860 0x0>, 2184 <&apps_smmu 0x880 0x0>, 2185 <&apps_smmu 0x861 0x04>, 2186 <&apps_smmu 0x863 0x0>, 2187 <&apps_smmu 0x804 0xe0>; 2188 2189 interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG 2190 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 2191 <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 2192 &config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG>; 2193 interconnect-names = "video-mem", 2194 "cpu-cfg"; 2195 2196 venus_opp_table: opp-table { 2197 compatible = "operating-points-v2"; 2198 2199 opp-133333333 { 2200 opp-hz = /bits/ 64 <133333333>; 2201 required-opps = <&rpmpd_opp_low_svs>; 2202 }; 2203 2204 opp-240000000 { 2205 opp-hz = /bits/ 64 <240000000>; 2206 required-opps = <&rpmpd_opp_svs>; 2207 }; 2208 }; 2209 }; 2210 2211 wifi: wifi@c800000 { 2212 compatible = "qcom,wcn3990-wifi"; 2213 reg = <0x0 0x0c800000 0x0 0x800000>; 2214 reg-names = "membase"; 2215 memory-region = <&wlan_msa_mem>; 2216 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2223 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2224 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2228 iommus = <&apps_smmu 0x1a0 0x1>; 2229 qcom,msa-fixed-perm; 2230 status = "disabled"; 2231 }; 2232 2233 watchdog@f017000 { 2234 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; 2235 reg = <0x0 0x0f017000 0x0 0x1000>; 2236 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 2237 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 2238 clocks = <&sleep_clk>; 2239 }; 2240 2241 apcs_glb: mailbox@f111000 { 2242 compatible = "qcom,qcm2290-apcs-hmss-global"; 2243 reg = <0x0 0x0f111000 0x0 0x1000>; 2244 #mbox-cells = <1>; 2245 }; 2246 2247 timer@f120000 { 2248 compatible = "arm,armv7-timer-mem"; 2249 reg = <0x0 0x0f120000 0x0 0x1000>; 2250 #address-cells = <1>; 2251 #size-cells = <1>; 2252 ranges = <0 0x0 0x0f121000 0x8000>; 2253 2254 frame@0 { 2255 reg = <0x0 0x1000>, 2256 <0x1000 0x1000>; 2257 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2258 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2259 frame-number = <0>; 2260 }; 2261 2262 frame@2000 { 2263 reg = <0x2000 0x1000>; 2264 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2265 frame-number = <1>; 2266 status = "disabled"; 2267 }; 2268 2269 frame@3000 { 2270 reg = <0x3000 0x1000>; 2271 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2272 frame-number = <2>; 2273 status = "disabled"; 2274 }; 2275 2276 frame@4000 { 2277 reg = <0x4000 0x1000>; 2278 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2279 frame-number = <3>; 2280 status = "disabled"; 2281 }; 2282 2283 frame@5000 { 2284 reg = <0x5000 0x1000>; 2285 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2286 frame-number = <4>; 2287 status = "disabled"; 2288 }; 2289 2290 frame@6000 { 2291 reg = <0x6000 0x1000>; 2292 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2293 frame-number = <5>; 2294 status = "disabled"; 2295 }; 2296 2297 frame@7000 { 2298 reg = <0x7000 0x1000>; 2299 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2300 frame-number = <6>; 2301 status = "disabled"; 2302 }; 2303 }; 2304 2305 intc: interrupt-controller@f200000 { 2306 compatible = "arm,gic-v3"; 2307 reg = <0x0 0x0f200000 0x0 0x10000>, 2308 <0x0 0x0f300000 0x0 0x100000>; 2309 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2310 #interrupt-cells = <3>; 2311 interrupt-controller; 2312 interrupt-parent = <&intc>; 2313 #redistributor-regions = <1>; 2314 redistributor-stride = <0x0 0x20000>; 2315 }; 2316 2317 cpufreq_hw: cpufreq@f521000 { 2318 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; 2319 reg = <0x0 0x0f521000 0x0 0x1000>; 2320 reg-names = "freq-domain0"; 2321 interrupts-extended = <&lmh_cluster 0>; 2322 interrupt-names = "dcvsh-irq-0"; 2323 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2324 clock-names = "xo", "alternate"; 2325 2326 #freq-domain-cells = <1>; 2327 #clock-cells = <1>; 2328 }; 2329 2330 lmh_cluster: lmh@f550800 { 2331 compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh"; 2332 reg = <0x0 0x0f550800 0x0 0x400>; 2333 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2334 cpus = <&cpu0>; 2335 qcom,lmh-temp-arm-millicelsius = <65000>; 2336 qcom,lmh-temp-low-millicelsius = <94500>; 2337 qcom,lmh-temp-high-millicelsius = <95000>; 2338 interrupt-controller; 2339 #interrupt-cells = <1>; 2340 }; 2341 }; 2342 2343 thermal-zones { 2344 mapss-thermal { 2345 thermal-sensors = <&tsens0 0>; 2346 2347 trips { 2348 mapss_alert0: trip-point0 { 2349 temperature = <90000>; 2350 hysteresis = <2000>; 2351 type = "passive"; 2352 }; 2353 2354 mapss_alert1: trip-point1 { 2355 temperature = <95000>; 2356 hysteresis = <2000>; 2357 type = "passive"; 2358 }; 2359 2360 mapss_crit: mapss-crit { 2361 temperature = <110000>; 2362 hysteresis = <1000>; 2363 type = "critical"; 2364 }; 2365 }; 2366 }; 2367 2368 video-thermal { 2369 thermal-sensors = <&tsens0 1>; 2370 2371 trips { 2372 video_alert0: trip-point0 { 2373 temperature = <90000>; 2374 hysteresis = <2000>; 2375 type = "passive"; 2376 }; 2377 2378 video_alert1: trip-point1 { 2379 temperature = <95000>; 2380 hysteresis = <2000>; 2381 type = "passive"; 2382 }; 2383 2384 video_crit: video-crit { 2385 temperature = <110000>; 2386 hysteresis = <1000>; 2387 type = "critical"; 2388 }; 2389 }; 2390 }; 2391 2392 wlan-thermal { 2393 thermal-sensors = <&tsens0 2>; 2394 2395 trips { 2396 wlan_alert0: trip-point0 { 2397 temperature = <90000>; 2398 hysteresis = <2000>; 2399 type = "passive"; 2400 }; 2401 2402 wlan_alert1: trip-point1 { 2403 temperature = <95000>; 2404 hysteresis = <2000>; 2405 type = "passive"; 2406 }; 2407 2408 wlan_crit: wlan-crit { 2409 temperature = <110000>; 2410 hysteresis = <1000>; 2411 type = "critical"; 2412 }; 2413 }; 2414 }; 2415 2416 cpuss0-thermal { 2417 thermal-sensors = <&tsens0 3>; 2418 2419 trips { 2420 cpuss0_alert0: trip-point0 { 2421 temperature = <90000>; 2422 hysteresis = <2000>; 2423 type = "passive"; 2424 }; 2425 2426 cpuss0_alert1: trip-point1 { 2427 temperature = <95000>; 2428 hysteresis = <2000>; 2429 type = "passive"; 2430 }; 2431 2432 cpuss0_crit: cpuss0-crit { 2433 temperature = <110000>; 2434 hysteresis = <1000>; 2435 type = "critical"; 2436 }; 2437 }; 2438 }; 2439 2440 cpuss1-thermal { 2441 thermal-sensors = <&tsens0 4>; 2442 2443 trips { 2444 cpuss1_alert0: trip-point0 { 2445 temperature = <90000>; 2446 hysteresis = <2000>; 2447 type = "passive"; 2448 }; 2449 2450 cpuss1_alert1: trip-point1 { 2451 temperature = <95000>; 2452 hysteresis = <2000>; 2453 type = "passive"; 2454 }; 2455 2456 cpuss1_crit: cpuss1-crit { 2457 temperature = <110000>; 2458 hysteresis = <1000>; 2459 type = "critical"; 2460 }; 2461 }; 2462 }; 2463 2464 mdm0-thermal { 2465 thermal-sensors = <&tsens0 5>; 2466 2467 trips { 2468 mdm0_alert0: trip-point0 { 2469 temperature = <90000>; 2470 hysteresis = <2000>; 2471 type = "passive"; 2472 }; 2473 2474 mdm0_alert1: trip-point1 { 2475 temperature = <95000>; 2476 hysteresis = <2000>; 2477 type = "passive"; 2478 }; 2479 2480 mdm0_crit: mdm0-crit { 2481 temperature = <110000>; 2482 hysteresis = <1000>; 2483 type = "critical"; 2484 }; 2485 }; 2486 }; 2487 2488 mdm1-thermal { 2489 thermal-sensors = <&tsens0 6>; 2490 2491 trips { 2492 mdm1_alert0: trip-point0 { 2493 temperature = <90000>; 2494 hysteresis = <2000>; 2495 type = "passive"; 2496 }; 2497 2498 mdm1_alert1: trip-point1 { 2499 temperature = <95000>; 2500 hysteresis = <2000>; 2501 type = "passive"; 2502 }; 2503 2504 mdm1_crit: mdm1-crit { 2505 temperature = <110000>; 2506 hysteresis = <1000>; 2507 type = "critical"; 2508 }; 2509 }; 2510 }; 2511 2512 gpu-thermal { 2513 thermal-sensors = <&tsens0 7>; 2514 2515 trips { 2516 gpu_alert0: trip-point0 { 2517 temperature = <90000>; 2518 hysteresis = <2000>; 2519 type = "passive"; 2520 }; 2521 2522 gpu_alert1: trip-point1 { 2523 temperature = <95000>; 2524 hysteresis = <2000>; 2525 type = "passive"; 2526 }; 2527 2528 gpu_crit: gpu-crit { 2529 temperature = <110000>; 2530 hysteresis = <1000>; 2531 type = "critical"; 2532 }; 2533 }; 2534 }; 2535 2536 hm-center-thermal { 2537 thermal-sensors = <&tsens0 8>; 2538 2539 trips { 2540 hm_center_alert0: trip-point0 { 2541 temperature = <90000>; 2542 hysteresis = <2000>; 2543 type = "passive"; 2544 }; 2545 2546 hm_center_alert1: trip-point1 { 2547 temperature = <95000>; 2548 hysteresis = <2000>; 2549 type = "passive"; 2550 }; 2551 2552 hm_center_crit: hm-center-crit { 2553 temperature = <110000>; 2554 hysteresis = <1000>; 2555 type = "critical"; 2556 }; 2557 }; 2558 }; 2559 2560 camera-thermal { 2561 thermal-sensors = <&tsens0 9>; 2562 2563 trips { 2564 camera_alert0: trip-point0 { 2565 temperature = <90000>; 2566 hysteresis = <2000>; 2567 type = "passive"; 2568 }; 2569 2570 camera_alert1: trip-point1 { 2571 temperature = <95000>; 2572 hysteresis = <2000>; 2573 type = "passive"; 2574 }; 2575 2576 camera_crit: camera-crit { 2577 temperature = <110000>; 2578 hysteresis = <1000>; 2579 type = "critical"; 2580 }; 2581 }; 2582 }; 2583 }; 2584 2585 timer { 2586 compatible = "arm,armv8-timer"; 2587 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2588 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2589 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2590 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2591 }; 2592}; 2593