1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2023, Linaro Ltd 4 * 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-qcm2290.h> 9#include <dt-bindings/clock/qcom,gcc-qcm2290.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/firmware/qcom,scm.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interconnect/qcom,qcm2290.h> 16#include <dt-bindings/interconnect/qcom,rpm-icc.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 clock-frequency = <32764>; 36 #clock-cells = <0>; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x0 0x0>; 48 clocks = <&cpufreq_hw 0>; 49 capacity-dmips-mhz = <1024>; 50 dynamic-power-coefficient = <100>; 51 enable-method = "psci"; 52 next-level-cache = <&L2_0>; 53 qcom,freq-domain = <&cpufreq_hw 0>; 54 power-domains = <&CPU_PD0>; 55 power-domain-names = "psci"; 56 L2_0: l2-cache { 57 compatible = "cache"; 58 cache-level = <2>; 59 cache-unified; 60 }; 61 }; 62 63 CPU1: cpu@1 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x0 0x1>; 67 clocks = <&cpufreq_hw 0>; 68 capacity-dmips-mhz = <1024>; 69 dynamic-power-coefficient = <100>; 70 enable-method = "psci"; 71 next-level-cache = <&L2_0>; 72 qcom,freq-domain = <&cpufreq_hw 0>; 73 power-domains = <&CPU_PD1>; 74 power-domain-names = "psci"; 75 }; 76 77 CPU2: cpu@2 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x0 0x2>; 81 clocks = <&cpufreq_hw 0>; 82 capacity-dmips-mhz = <1024>; 83 dynamic-power-coefficient = <100>; 84 enable-method = "psci"; 85 next-level-cache = <&L2_0>; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 power-domains = <&CPU_PD2>; 88 power-domain-names = "psci"; 89 }; 90 91 CPU3: cpu@3 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a53"; 94 reg = <0x0 0x3>; 95 clocks = <&cpufreq_hw 0>; 96 capacity-dmips-mhz = <1024>; 97 dynamic-power-coefficient = <100>; 98 enable-method = "psci"; 99 next-level-cache = <&L2_0>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 power-domains = <&CPU_PD3>; 102 power-domain-names = "psci"; 103 }; 104 105 cpu-map { 106 cluster0 { 107 core0 { 108 cpu = <&CPU0>; 109 }; 110 111 core1 { 112 cpu = <&CPU1>; 113 }; 114 115 core2 { 116 cpu = <&CPU2>; 117 }; 118 119 core3 { 120 cpu = <&CPU3>; 121 }; 122 }; 123 }; 124 125 domain-idle-states { 126 CLUSTER_SLEEP: cluster-sleep-0 { 127 compatible = "domain-idle-state"; 128 arm,psci-suspend-param = <0x41000043>; 129 entry-latency-us = <800>; 130 exit-latency-us = <2118>; 131 min-residency-us = <7376>; 132 }; 133 }; 134 135 idle-states { 136 entry-method = "psci"; 137 138 CPU_SLEEP: cpu-sleep-0 { 139 compatible = "arm,idle-state"; 140 idle-state-name = "power-collapse"; 141 arm,psci-suspend-param = <0x40000003>; 142 entry-latency-us = <290>; 143 exit-latency-us = <376>; 144 min-residency-us = <1182>; 145 local-timer-stop; 146 }; 147 }; 148 }; 149 150 firmware { 151 scm: scm { 152 compatible = "qcom,scm-qcm2290", "qcom,scm"; 153 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 154 clock-names = "core"; 155 #reset-cells = <1>; 156 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 157 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 158 }; 159 }; 160 161 memory@40000000 { 162 device_type = "memory"; 163 /* We expect the bootloader to fill in the size */ 164 reg = <0 0x40000000 0 0>; 165 }; 166 167 pmu { 168 compatible = "arm,cortex-a53-pmu"; 169 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 170 }; 171 172 psci { 173 compatible = "arm,psci-1.0"; 174 method = "smc"; 175 176 CPU_PD0: power-domain-cpu0 { 177 #power-domain-cells = <0>; 178 power-domains = <&CLUSTER_PD>; 179 domain-idle-states = <&CPU_SLEEP>; 180 }; 181 182 CPU_PD1: power-domain-cpu1 { 183 #power-domain-cells = <0>; 184 power-domains = <&CLUSTER_PD>; 185 domain-idle-states = <&CPU_SLEEP>; 186 }; 187 188 CPU_PD2: power-domain-cpu2 { 189 #power-domain-cells = <0>; 190 power-domains = <&CLUSTER_PD>; 191 domain-idle-states = <&CPU_SLEEP>; 192 }; 193 194 CPU_PD3: power-domain-cpu3 { 195 #power-domain-cells = <0>; 196 power-domains = <&CLUSTER_PD>; 197 domain-idle-states = <&CPU_SLEEP>; 198 }; 199 200 CLUSTER_PD: power-domain-cpu-cluster { 201 #power-domain-cells = <0>; 202 power-domains = <&mpm>; 203 domain-idle-states = <&CLUSTER_SLEEP>; 204 }; 205 }; 206 207 rpm: remoteproc { 208 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc"; 209 210 glink-edge { 211 compatible = "qcom,glink-rpm"; 212 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 213 qcom,rpm-msg-ram = <&rpm_msg_ram>; 214 mboxes = <&apcs_glb 0>; 215 216 rpm_requests: rpm-requests { 217 compatible = "qcom,rpm-qcm2290"; 218 qcom,glink-channels = "rpm_requests"; 219 220 rpmcc: clock-controller { 221 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; 222 clocks = <&xo_board>; 223 clock-names = "xo"; 224 #clock-cells = <1>; 225 }; 226 227 rpmpd: power-controller { 228 compatible = "qcom,qcm2290-rpmpd"; 229 #power-domain-cells = <1>; 230 operating-points-v2 = <&rpmpd_opp_table>; 231 232 rpmpd_opp_table: opp-table { 233 compatible = "operating-points-v2"; 234 235 rpmpd_opp_min_svs: opp1 { 236 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 237 }; 238 239 rpmpd_opp_low_svs: opp2 { 240 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 241 }; 242 243 rpmpd_opp_svs: opp3 { 244 opp-level = <RPM_SMD_LEVEL_SVS>; 245 }; 246 247 rpmpd_opp_svs_plus: opp4 { 248 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 249 }; 250 251 rpmpd_opp_nom: opp5 { 252 opp-level = <RPM_SMD_LEVEL_NOM>; 253 }; 254 255 rpmpd_opp_nom_plus: opp6 { 256 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 257 }; 258 259 rpmpd_opp_turbo: opp7 { 260 opp-level = <RPM_SMD_LEVEL_TURBO>; 261 }; 262 263 rpmpd_opp_turbo_plus: opp8 { 264 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 265 }; 266 }; 267 }; 268 }; 269 }; 270 271 mpm: interrupt-controller { 272 compatible = "qcom,mpm"; 273 qcom,rpm-msg-ram = <&apss_mpm>; 274 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 275 mboxes = <&apcs_glb 1>; 276 interrupt-controller; 277 #interrupt-cells = <2>; 278 #power-domain-cells = <0>; 279 interrupt-parent = <&intc>; 280 qcom,mpm-pin-count = <96>; 281 qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ 282 <5 296>, /* Soundwire master_irq */ 283 <12 422>, /* DWC3 ss_phy_irq */ 284 <24 79>, /* Soundwire wake_irq */ 285 <86 183>, /* MPM wake, SPMI */ 286 <90 260>; /* QUSB2_PHY DP+DM */ 287 }; 288 }; 289 290 reserved_memory: reserved-memory { 291 #address-cells = <2>; 292 #size-cells = <2>; 293 ranges; 294 295 hyp_mem: hyp@45700000 { 296 reg = <0x0 0x45700000 0x0 0x600000>; 297 no-map; 298 }; 299 300 xbl_aop_mem: xbl-aop@45e00000 { 301 reg = <0x0 0x45e00000 0x0 0x140000>; 302 no-map; 303 }; 304 305 sec_apps_mem: sec-apps@45fff000 { 306 reg = <0x0 0x45fff000 0x0 0x1000>; 307 no-map; 308 }; 309 310 smem_mem: smem@46000000 { 311 compatible = "qcom,smem"; 312 reg = <0x0 0x46000000 0x0 0x200000>; 313 no-map; 314 315 hwlocks = <&tcsr_mutex 3>; 316 qcom,rpm-msg-ram = <&rpm_msg_ram>; 317 }; 318 319 pil_modem_mem: modem@4ab00000 { 320 reg = <0x0 0x4ab00000 0x0 0x6900000>; 321 no-map; 322 }; 323 324 pil_video_mem: video@51400000 { 325 reg = <0x0 0x51400000 0x0 0x500000>; 326 no-map; 327 }; 328 329 wlan_msa_mem: wlan-msa@51900000 { 330 reg = <0x0 0x51900000 0x0 0x100000>; 331 no-map; 332 }; 333 334 pil_adsp_mem: adsp@51a00000 { 335 reg = <0x0 0x51a00000 0x0 0x1c00000>; 336 no-map; 337 }; 338 339 pil_ipa_fw_mem: ipa-fw@53600000 { 340 reg = <0x0 0x53600000 0x0 0x10000>; 341 no-map; 342 }; 343 344 pil_ipa_gsi_mem: ipa-gsi@53610000 { 345 reg = <0x0 0x53610000 0x0 0x5000>; 346 no-map; 347 }; 348 349 pil_gpu_mem: zap@53615000 { 350 compatible = "shared-dma-pool"; 351 reg = <0x0 0x53615000 0x0 0x2000>; 352 no-map; 353 }; 354 355 cont_splash_memory: framebuffer@5c000000 { 356 reg = <0x0 0x5c000000 0x0 0x00f00000>; 357 no-map; 358 }; 359 360 dfps_data_memory: dpfs-data@5cf00000 { 361 reg = <0x0 0x5cf00000 0x0 0x0100000>; 362 no-map; 363 }; 364 365 removed_mem: reserved@60000000 { 366 reg = <0x0 0x60000000 0x0 0x3900000>; 367 no-map; 368 }; 369 370 rmtfs_mem: memory@89b01000 { 371 compatible = "qcom,rmtfs-mem"; 372 reg = <0x0 0x89b01000 0x0 0x200000>; 373 no-map; 374 375 qcom,client-id = <1>; 376 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 377 }; 378 }; 379 380 smp2p-adsp { 381 compatible = "qcom,smp2p"; 382 qcom,smem = <443>, <429>; 383 384 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 385 386 mboxes = <&apcs_glb 10>; 387 388 qcom,local-pid = <0>; 389 qcom,remote-pid = <2>; 390 391 adsp_smp2p_out: master-kernel { 392 qcom,entry-name = "master-kernel"; 393 #qcom,smem-state-cells = <1>; 394 }; 395 396 adsp_smp2p_in: slave-kernel { 397 qcom,entry-name = "slave-kernel"; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 }; 401 }; 402 403 smp2p-mpss { 404 compatible = "qcom,smp2p"; 405 qcom,smem = <435>, <428>; 406 407 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 408 409 mboxes = <&apcs_glb 14>; 410 411 qcom,local-pid = <0>; 412 qcom,remote-pid = <1>; 413 414 modem_smp2p_out: master-kernel { 415 qcom,entry-name = "master-kernel"; 416 #qcom,smem-state-cells = <1>; 417 }; 418 419 modem_smp2p_in: slave-kernel { 420 qcom,entry-name = "slave-kernel"; 421 interrupt-controller; 422 #interrupt-cells = <2>; 423 }; 424 425 wlan_smp2p_in: wlan-wpss-to-ap { 426 qcom,entry-name = "wlan"; 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 }; 430 }; 431 432 soc: soc@0 { 433 compatible = "simple-bus"; 434 #address-cells = <2>; 435 #size-cells = <2>; 436 ranges = <0 0 0 0 0x10 0>; 437 dma-ranges = <0 0 0 0 0x10 0>; 438 439 tcsr_mutex: hwlock@340000 { 440 compatible = "qcom,tcsr-mutex"; 441 reg = <0x0 0x00340000 0x0 0x20000>; 442 #hwlock-cells = <1>; 443 }; 444 445 tcsr_regs: syscon@3c0000 { 446 compatible = "qcom,qcm2290-tcsr", "syscon"; 447 reg = <0x0 0x003c0000 0x0 0x40000>; 448 }; 449 450 tlmm: pinctrl@500000 { 451 compatible = "qcom,qcm2290-tlmm"; 452 reg = <0x0 0x00500000 0x0 0x300000>; 453 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 454 gpio-controller; 455 gpio-ranges = <&tlmm 0 0 127>; 456 wakeup-parent = <&mpm>; 457 #gpio-cells = <2>; 458 interrupt-controller; 459 #interrupt-cells = <2>; 460 461 qup_i2c0_default: qup-i2c0-default-state { 462 pins = "gpio0", "gpio1"; 463 function = "qup0"; 464 drive-strength = <2>; 465 bias-pull-up; 466 }; 467 468 qup_i2c1_default: qup-i2c1-default-state { 469 pins = "gpio4", "gpio5"; 470 function = "qup1"; 471 drive-strength = <2>; 472 bias-pull-up; 473 }; 474 475 qup_i2c2_default: qup-i2c2-default-state { 476 pins = "gpio6", "gpio7"; 477 function = "qup2"; 478 drive-strength = <2>; 479 bias-pull-up; 480 }; 481 482 qup_i2c3_default: qup-i2c3-default-state { 483 pins = "gpio8", "gpio9"; 484 function = "qup3"; 485 drive-strength = <2>; 486 bias-pull-up; 487 }; 488 489 qup_i2c4_default: qup-i2c4-default-state { 490 pins = "gpio12", "gpio13"; 491 function = "qup4"; 492 drive-strength = <2>; 493 bias-pull-up; 494 }; 495 496 qup_i2c5_default: qup-i2c5-default-state { 497 pins = "gpio14", "gpio15"; 498 function = "qup5"; 499 drive-strength = <2>; 500 bias-pull-up; 501 }; 502 503 qup_spi0_default: qup-spi0-default-state { 504 pins = "gpio0", "gpio1","gpio2", "gpio3"; 505 function = "qup0"; 506 drive-strength = <2>; 507 bias-pull-up; 508 }; 509 510 qup_spi1_default: qup-spi1-default-state { 511 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 512 function = "qup1"; 513 drive-strength = <2>; 514 bias-pull-up; 515 }; 516 517 qup_spi2_default: qup-spi2-default-state { 518 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 519 function = "qup2"; 520 drive-strength = <2>; 521 bias-pull-up; 522 }; 523 524 qup_spi3_default: qup-spi3-default-state { 525 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 526 function = "qup3"; 527 drive-strength = <2>; 528 bias-pull-up; 529 }; 530 531 qup_spi4_default: qup-spi4-default-state { 532 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 533 function = "qup4"; 534 drive-strength = <2>; 535 bias-pull-up; 536 }; 537 538 qup_spi5_default: qup-spi5-default-state { 539 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 540 function = "qup5"; 541 drive-strength = <2>; 542 bias-pull-up; 543 }; 544 545 qup_uart0_default: qup-uart0-default-state { 546 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 547 function = "qup0"; 548 drive-strength = <2>; 549 bias-disable; 550 }; 551 552 qup_uart4_default: qup-uart4-default-state { 553 pins = "gpio12", "gpio13"; 554 function = "qup4"; 555 drive-strength = <2>; 556 bias-disable; 557 }; 558 559 sdc1_state_on: sdc1-on-state { 560 clk-pins { 561 pins = "sdc1_clk"; 562 drive-strength = <16>; 563 bias-disable; 564 }; 565 566 cmd-pins { 567 pins = "sdc1_cmd"; 568 drive-strength = <10>; 569 bias-pull-up; 570 }; 571 572 data-pins { 573 pins = "sdc1_data"; 574 drive-strength = <10>; 575 bias-pull-up; 576 }; 577 578 rclk-pins { 579 pins = "sdc1_rclk"; 580 bias-pull-down; 581 }; 582 }; 583 584 sdc1_state_off: sdc1-off-state { 585 clk-pins { 586 pins = "sdc1_clk"; 587 drive-strength = <2>; 588 bias-disable; 589 }; 590 591 cmd-pins { 592 pins = "sdc1_cmd"; 593 drive-strength = <2>; 594 bias-pull-up; 595 }; 596 597 data-pins { 598 pins = "sdc1_data"; 599 drive-strength = <2>; 600 bias-pull-up; 601 }; 602 603 rclk-pins { 604 pins = "sdc1_rclk"; 605 bias-pull-down; 606 }; 607 }; 608 609 sdc2_state_on: sdc2-on-state { 610 clk-pins { 611 pins = "sdc2_clk"; 612 drive-strength = <16>; 613 bias-disable; 614 }; 615 616 cmd-pins { 617 pins = "sdc2_cmd"; 618 drive-strength = <10>; 619 bias-pull-up; 620 }; 621 622 data-pins { 623 pins = "sdc2_data"; 624 drive-strength = <10>; 625 bias-pull-up; 626 }; 627 }; 628 629 sdc2_state_off: sdc2-off-state { 630 clk-pins { 631 pins = "sdc2_clk"; 632 drive-strength = <2>; 633 bias-disable; 634 }; 635 636 cmd-pins { 637 pins = "sdc2_cmd"; 638 drive-strength = <2>; 639 bias-pull-up; 640 }; 641 642 data-pins { 643 pins = "sdc2_data"; 644 drive-strength = <2>; 645 bias-pull-up; 646 }; 647 }; 648 }; 649 650 gcc: clock-controller@1400000 { 651 compatible = "qcom,gcc-qcm2290"; 652 reg = <0x0 0x01400000 0x0 0x1f0000>; 653 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 654 clock-names = "bi_tcxo", "sleep_clk"; 655 #clock-cells = <1>; 656 #reset-cells = <1>; 657 #power-domain-cells = <1>; 658 }; 659 660 usb_hsphy: phy@1613000 { 661 compatible = "qcom,qcm2290-qusb2-phy"; 662 reg = <0x0 0x01613000 0x0 0x180>; 663 664 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 665 <&rpmcc RPM_SMD_XO_CLK_SRC>; 666 clock-names = "cfg_ahb", "ref"; 667 668 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 669 nvmem-cells = <&qusb2_hstx_trim>; 670 #phy-cells = <0>; 671 672 status = "disabled"; 673 }; 674 675 usb_qmpphy: phy@1615000 { 676 compatible = "qcom,qcm2290-qmp-usb3-phy"; 677 reg = <0x0 0x01615000 0x0 0x1000>; 678 679 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 680 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 681 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 682 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 683 clock-names = "cfg_ahb", 684 "ref", 685 "com_aux", 686 "pipe"; 687 688 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 689 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 690 reset-names = "phy", 691 "phy_phy"; 692 693 #clock-cells = <0>; 694 clock-output-names = "usb3_phy_pipe_clk_src"; 695 696 #phy-cells = <0>; 697 orientation-switch; 698 699 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 700 701 status = "disabled"; 702 703 ports { 704 #address-cells = <1>; 705 #size-cells = <0>; 706 707 port@0 { 708 reg = <0>; 709 710 usb_qmpphy_out: endpoint { 711 }; 712 }; 713 714 port@1 { 715 reg = <1>; 716 717 usb_qmpphy_usb_ss_in: endpoint { 718 remote-endpoint = <&usb_dwc3_ss>; 719 }; 720 }; 721 }; 722 }; 723 724 system_noc: interconnect@1880000 { 725 compatible = "qcom,qcm2290-snoc"; 726 reg = <0x0 0x01880000 0x0 0x60200>; 727 #interconnect-cells = <2>; 728 729 qup_virt: interconnect-qup { 730 compatible = "qcom,qcm2290-qup-virt"; 731 #interconnect-cells = <2>; 732 }; 733 734 mmnrt_virt: interconnect-mmnrt { 735 compatible = "qcom,qcm2290-mmnrt-virt"; 736 #interconnect-cells = <2>; 737 }; 738 739 mmrt_virt: interconnect-mmrt { 740 compatible = "qcom,qcm2290-mmrt-virt"; 741 #interconnect-cells = <2>; 742 }; 743 }; 744 745 config_noc: interconnect@1900000 { 746 compatible = "qcom,qcm2290-cnoc"; 747 reg = <0x0 0x01900000 0x0 0x8200>; 748 #interconnect-cells = <2>; 749 }; 750 751 qfprom@1b44000 { 752 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; 753 reg = <0x0 0x01b44000 0x0 0x3000>; 754 #address-cells = <1>; 755 #size-cells = <1>; 756 757 qusb2_hstx_trim: hstx-trim@25b { 758 reg = <0x25b 0x1>; 759 bits = <1 4>; 760 }; 761 }; 762 763 pmu@1b8e300 { 764 compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon"; 765 reg = <0x0 0x01b8e300 0x0 0x600>; 766 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 767 768 operating-points-v2 = <&cpu_bwmon_opp_table>; 769 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 770 &bimc SLAVE_EBI1 RPM_ACTIVE_TAG>; 771 772 cpu_bwmon_opp_table: opp-table { 773 compatible = "operating-points-v2"; 774 775 opp-0 { 776 opp-peak-kBps = <(200 * 4 * 1000)>; 777 }; 778 779 opp-1 { 780 opp-peak-kBps = <(300 * 4 * 1000)>; 781 }; 782 783 opp-2 { 784 opp-peak-kBps = <(451 * 4 * 1000)>; 785 }; 786 787 opp-3 { 788 opp-peak-kBps = <(547 * 4 * 1000)>; 789 }; 790 791 opp-4 { 792 opp-peak-kBps = <(681 * 4 * 1000)>; 793 }; 794 795 opp-5 { 796 opp-peak-kBps = <(768 * 4 * 1000)>; 797 }; 798 799 opp-6 { 800 opp-peak-kBps = <(1017 * 4 * 1000)>; 801 }; 802 803 opp-7 { 804 opp-peak-kBps = <(1353 * 4 * 1000)>; 805 }; 806 807 opp-8 { 808 opp-peak-kBps = <(1555 * 4 * 1000)>; 809 }; 810 811 opp-9 { 812 opp-peak-kBps = <(1804 * 4 * 1000)>; 813 }; 814 }; 815 }; 816 817 spmi_bus: spmi@1c40000 { 818 compatible = "qcom,spmi-pmic-arb"; 819 reg = <0x0 0x01c40000 0x0 0x1100>, 820 <0x0 0x01e00000 0x0 0x2000000>, 821 <0x0 0x03e00000 0x0 0x100000>, 822 <0x0 0x03f00000 0x0 0xa0000>, 823 <0x0 0x01c0a000 0x0 0x26000>; 824 reg-names = "core", 825 "chnls", 826 "obsrvr", 827 "intr", 828 "cnfg"; 829 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; 830 interrupt-names = "periph_irq"; 831 qcom,ee = <0>; 832 qcom,channel = <0>; 833 #address-cells = <2>; 834 #size-cells = <0>; 835 interrupt-controller; 836 #interrupt-cells = <4>; 837 }; 838 839 tsens0: thermal-sensor@4411000 { 840 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; 841 reg = <0x0 0x04411000 0x0 0x1ff>, 842 <0x0 0x04410000 0x0 0x8>; 843 #qcom,sensors = <10>; 844 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, 845 <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 846 interrupt-names = "uplow", "critical"; 847 #thermal-sensor-cells = <1>; 848 }; 849 850 rng: rng@4453000 { 851 compatible = "qcom,prng-ee"; 852 reg = <0x0 0x04453000 0x0 0x1000>; 853 clocks = <&rpmcc RPM_SMD_HWKM_CLK>; 854 clock-names = "core"; 855 }; 856 857 bimc: interconnect@4480000 { 858 compatible = "qcom,qcm2290-bimc"; 859 reg = <0x0 0x04480000 0x0 0x80000>; 860 #interconnect-cells = <2>; 861 }; 862 863 rpm_msg_ram: sram@45f0000 { 864 compatible = "qcom,rpm-msg-ram", "mmio-sram"; 865 reg = <0x0 0x045f0000 0x0 0x7000>; 866 #address-cells = <1>; 867 #size-cells = <1>; 868 ranges = <0 0x0 0x045f0000 0x7000>; 869 870 apss_mpm: sram@1b8 { 871 reg = <0x1b8 0x48>; 872 }; 873 }; 874 875 sram@4690000 { 876 compatible = "qcom,rpm-stats"; 877 reg = <0x0 0x04690000 0x0 0x10000>; 878 }; 879 880 sdhc_1: mmc@4744000 { 881 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 882 reg = <0x0 0x04744000 0x0 0x1000>, 883 <0x0 0x04745000 0x0 0x1000>, 884 <0x0 0x04748000 0x0 0x8000>; 885 reg-names = "hc", 886 "cqhci", 887 "ice"; 888 889 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 891 interrupt-names = "hc_irq", "pwr_irq"; 892 893 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 894 <&gcc GCC_SDCC1_APPS_CLK>, 895 <&rpmcc RPM_SMD_XO_CLK_SRC>, 896 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 897 clock-names = "iface", 898 "core", 899 "xo", 900 "ice"; 901 902 resets = <&gcc GCC_SDCC1_BCR>; 903 904 power-domains = <&rpmpd QCM2290_VDDCX>; 905 operating-points-v2 = <&sdhc1_opp_table>; 906 iommus = <&apps_smmu 0xc0 0x0>; 907 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 908 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 909 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 910 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; 911 interconnect-names = "sdhc-ddr", 912 "cpu-sdhc"; 913 914 qcom,dll-config = <0x000f642c>; 915 qcom,ddr-config = <0x80040868>; 916 bus-width = <8>; 917 918 status = "disabled"; 919 920 sdhc1_opp_table: opp-table { 921 compatible = "operating-points-v2"; 922 923 opp-100000000 { 924 opp-hz = /bits/ 64 <100000000>; 925 required-opps = <&rpmpd_opp_low_svs>; 926 opp-peak-kBps = <250000 133320>; 927 opp-avg-kBps = <102400 65000>; 928 }; 929 930 opp-192000000 { 931 opp-hz = /bits/ 64 <192000000>; 932 required-opps = <&rpmpd_opp_low_svs>; 933 opp-peak-kBps = <800000 300000>; 934 opp-avg-kBps = <204800 200000>; 935 }; 936 937 opp-384000000 { 938 opp-hz = /bits/ 64 <384000000>; 939 required-opps = <&rpmpd_opp_svs_plus>; 940 opp-peak-kBps = <800000 300000>; 941 opp-avg-kBps = <204800 200000>; 942 }; 943 }; 944 }; 945 946 sdhc_2: mmc@4784000 { 947 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 948 reg = <0x0 0x04784000 0x0 0x1000>; 949 reg-names = "hc"; 950 951 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 953 interrupt-names = "hc_irq", "pwr_irq"; 954 955 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 956 <&gcc GCC_SDCC2_APPS_CLK>, 957 <&rpmcc RPM_SMD_XO_CLK_SRC>; 958 clock-names = "iface", 959 "core", 960 "xo"; 961 962 resets = <&gcc GCC_SDCC2_BCR>; 963 964 power-domains = <&rpmpd QCM2290_VDDCX>; 965 operating-points-v2 = <&sdhc2_opp_table>; 966 iommus = <&apps_smmu 0xa0 0x0>; 967 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG 968 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 969 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 970 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; 971 interconnect-names = "sdhc-ddr", 972 "cpu-sdhc"; 973 974 qcom,dll-config = <0x0007642c>; 975 qcom,ddr-config = <0x80040868>; 976 bus-width = <4>; 977 978 status = "disabled"; 979 980 sdhc2_opp_table: opp-table { 981 compatible = "operating-points-v2"; 982 983 opp-100000000 { 984 opp-hz = /bits/ 64 <100000000>; 985 required-opps = <&rpmpd_opp_low_svs>; 986 opp-peak-kBps = <250000 133320>; 987 opp-avg-kBps = <261438 150000>; 988 }; 989 990 opp-202000000 { 991 opp-hz = /bits/ 64 <202000000>; 992 required-opps = <&rpmpd_opp_svs_plus>; 993 opp-peak-kBps = <800000 300000>; 994 opp-avg-kBps = <261438 300000>; 995 }; 996 }; 997 }; 998 999 gpi_dma0: dma-controller@4a00000 { 1000 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; 1001 reg = <0x0 0x04a00000 0x0 0x60000>; 1002 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1008 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1012 dma-channels = <10>; 1013 dma-channel-mask = <0x1f>; 1014 iommus = <&apps_smmu 0xf6 0x0>; 1015 #dma-cells = <3>; 1016 status = "disabled"; 1017 }; 1018 1019 qupv3_id_0: geniqup@4ac0000 { 1020 compatible = "qcom,geni-se-qup"; 1021 reg = <0x0 0x04ac0000 0x0 0x2000>; 1022 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1023 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1024 clock-names = "m-ahb", "s-ahb"; 1025 iommus = <&apps_smmu 0xe3 0x0>; 1026 #address-cells = <2>; 1027 #size-cells = <2>; 1028 ranges; 1029 status = "disabled"; 1030 1031 i2c0: i2c@4a80000 { 1032 compatible = "qcom,geni-i2c"; 1033 reg = <0x0 0x04a80000 0x0 0x4000>; 1034 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1036 clock-names = "se"; 1037 pinctrl-0 = <&qup_i2c0_default>; 1038 pinctrl-names = "default"; 1039 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1040 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1041 dma-names = "tx", "rx"; 1042 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1043 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1044 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1045 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1046 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1047 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1048 interconnect-names = "qup-core", 1049 "qup-config", 1050 "qup-memory"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 spi0: spi@4a80000 { 1057 compatible = "qcom,geni-spi"; 1058 reg = <0x0 0x04a80000 0x0 0x4000>; 1059 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1061 clock-names = "se"; 1062 pinctrl-0 = <&qup_spi0_default>; 1063 pinctrl-names = "default"; 1064 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1065 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1066 dma-names = "tx", "rx"; 1067 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1068 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1069 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1070 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1071 interconnect-names = "qup-core", 1072 "qup-config"; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 1078 uart0: serial@4a80000 { 1079 compatible = "qcom,geni-uart"; 1080 reg = <0x0 0x04a80000 0x0 0x4000>; 1081 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1083 clock-names = "se"; 1084 pinctrl-0 = <&qup_uart0_default>; 1085 pinctrl-names = "default"; 1086 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1087 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1088 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1089 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1090 interconnect-names = "qup-core", 1091 "qup-config"; 1092 status = "disabled"; 1093 }; 1094 1095 i2c1: i2c@4a84000 { 1096 compatible = "qcom,geni-i2c"; 1097 reg = <0x0 0x04a84000 0x0 0x4000>; 1098 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1100 clock-names = "se"; 1101 pinctrl-0 = <&qup_i2c1_default>; 1102 pinctrl-names = "default"; 1103 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1104 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1105 dma-names = "tx", "rx"; 1106 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1107 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1108 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1109 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1110 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1111 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1112 interconnect-names = "qup-core", 1113 "qup-config", 1114 "qup-memory"; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 status = "disabled"; 1118 }; 1119 1120 spi1: spi@4a84000 { 1121 compatible = "qcom,geni-spi"; 1122 reg = <0x0 0x04a84000 0x0 0x4000>; 1123 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1124 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1125 clock-names = "se"; 1126 pinctrl-0 = <&qup_spi1_default>; 1127 pinctrl-names = "default"; 1128 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1129 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1130 dma-names = "tx", "rx"; 1131 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1132 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1133 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1134 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1135 interconnect-names = "qup-core", 1136 "qup-config"; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 status = "disabled"; 1140 }; 1141 1142 i2c2: i2c@4a88000 { 1143 compatible = "qcom,geni-i2c"; 1144 reg = <0x0 0x04a88000 0x0 0x4000>; 1145 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1147 clock-names = "se"; 1148 pinctrl-0 = <&qup_i2c2_default>; 1149 pinctrl-names = "default"; 1150 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1151 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1152 dma-names = "tx", "rx"; 1153 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1154 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1155 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1156 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1157 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1158 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1159 interconnect-names = "qup-core", 1160 "qup-config", 1161 "qup-memory"; 1162 #address-cells = <1>; 1163 #size-cells = <0>; 1164 status = "disabled"; 1165 }; 1166 1167 spi2: spi@4a88000 { 1168 compatible = "qcom,geni-spi"; 1169 reg = <0x0 0x04a88000 0x0 0x4000>; 1170 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1172 clock-names = "se"; 1173 pinctrl-0 = <&qup_spi2_default>; 1174 pinctrl-names = "default"; 1175 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1176 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1177 dma-names = "tx", "rx"; 1178 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1179 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1180 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1181 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1182 interconnect-names = "qup-core", 1183 "qup-config"; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 status = "disabled"; 1187 }; 1188 1189 i2c3: i2c@4a8c000 { 1190 compatible = "qcom,geni-i2c"; 1191 reg = <0x0 0x04a8c000 0x0 0x4000>; 1192 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1194 clock-names = "se"; 1195 pinctrl-0 = <&qup_i2c3_default>; 1196 pinctrl-names = "default"; 1197 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1198 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1199 dma-names = "tx", "rx"; 1200 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1201 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1202 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1203 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1204 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1205 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1206 interconnect-names = "qup-core", 1207 "qup-config", 1208 "qup-memory"; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 status = "disabled"; 1212 }; 1213 1214 spi3: spi@4a8c000 { 1215 compatible = "qcom,geni-spi"; 1216 reg = <0x0 0x04a8c000 0x0 0x4000>; 1217 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1218 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1219 clock-names = "se"; 1220 pinctrl-0 = <&qup_spi3_default>; 1221 pinctrl-names = "default"; 1222 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1223 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1224 dma-names = "tx", "rx"; 1225 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1226 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1227 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1228 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1229 interconnect-names = "qup-core", 1230 "qup-config"; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 status = "disabled"; 1234 }; 1235 1236 i2c4: i2c@4a90000 { 1237 compatible = "qcom,geni-i2c"; 1238 reg = <0x0 0x04a90000 0x0 0x4000>; 1239 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1241 clock-names = "se"; 1242 pinctrl-0 = <&qup_i2c4_default>; 1243 pinctrl-names = "default"; 1244 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1245 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1246 dma-names = "tx", "rx"; 1247 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1248 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1249 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1250 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1251 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1252 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1253 interconnect-names = "qup-core", 1254 "qup-config", 1255 "qup-memory"; 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 status = "disabled"; 1259 }; 1260 1261 spi4: spi@4a90000 { 1262 compatible = "qcom,geni-spi"; 1263 reg = <0x0 0x04a90000 0x0 0x4000>; 1264 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1265 clock-names = "se"; 1266 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&qup_spi4_default>; 1269 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1270 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1271 dma-names = "tx", "rx"; 1272 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1273 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1274 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1275 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1276 interconnect-names = "qup-core", 1277 "qup-config"; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 status = "disabled"; 1281 }; 1282 1283 uart4: serial@4a90000 { 1284 compatible = "qcom,geni-uart"; 1285 reg = <0x0 0x04a90000 0x0 0x4000>; 1286 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1288 clock-names = "se"; 1289 pinctrl-0 = <&qup_uart4_default>; 1290 pinctrl-names = "default"; 1291 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1292 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1293 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1294 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1295 interconnect-names = "qup-core", 1296 "qup-config"; 1297 status = "disabled"; 1298 }; 1299 1300 i2c5: i2c@4a94000 { 1301 compatible = "qcom,geni-i2c"; 1302 reg = <0x0 0x04a94000 0x0 0x4000>; 1303 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1305 clock-names = "se"; 1306 pinctrl-0 = <&qup_i2c5_default>; 1307 pinctrl-names = "default"; 1308 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1309 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1310 dma-names = "tx", "rx"; 1311 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1312 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1313 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1314 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1315 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1316 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1317 interconnect-names = "qup-core", 1318 "qup-config", 1319 "qup-memory"; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 spi5: spi@4a94000 { 1326 compatible = "qcom,geni-spi"; 1327 reg = <0x0 0x04a94000 0x0 0x4000>; 1328 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1329 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1330 clock-names = "se"; 1331 pinctrl-0 = <&qup_spi5_default>; 1332 pinctrl-names = "default"; 1333 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1334 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1335 dma-names = "tx", "rx"; 1336 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1337 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1338 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1339 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>; 1340 interconnect-names = "qup-core", 1341 "qup-config"; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 status = "disabled"; 1345 }; 1346 }; 1347 1348 usb: usb@4ef8800 { 1349 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; 1350 reg = <0x0 0x04ef8800 0x0 0x400>; 1351 interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1352 <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; 1353 interrupt-names = "hs_phy_irq", 1354 "ss_phy_irq"; 1355 1356 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1357 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1358 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1359 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1360 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1361 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1362 clock-names = "cfg_noc", 1363 "core", 1364 "iface", 1365 "sleep", 1366 "mock_utmi", 1367 "xo"; 1368 1369 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1370 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1371 assigned-clock-rates = <19200000>, <133333333>; 1372 1373 resets = <&gcc GCC_USB30_PRIM_BCR>; 1374 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1375 /* TODO: USB<->IPA path */ 1376 interconnects = <&system_noc MASTER_USB3_0 RPM_ALWAYS_TAG 1377 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1378 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1379 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; 1380 interconnect-names = "usb-ddr", 1381 "apps-usb"; 1382 wakeup-source; 1383 1384 #address-cells = <2>; 1385 #size-cells = <2>; 1386 ranges; 1387 1388 status = "disabled"; 1389 1390 usb_dwc3: usb@4e00000 { 1391 compatible = "snps,dwc3"; 1392 reg = <0x0 0x04e00000 0x0 0xcd00>; 1393 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1394 phys = <&usb_hsphy>, <&usb_qmpphy>; 1395 phy-names = "usb2-phy", "usb3-phy"; 1396 iommus = <&apps_smmu 0x120 0x0>; 1397 snps,dis_u2_susphy_quirk; 1398 snps,dis_enblslpm_quirk; 1399 snps,has-lpm-erratum; 1400 snps,hird-threshold = /bits/ 8 <0x10>; 1401 snps,usb3_lpm_capable; 1402 maximum-speed = "super-speed"; 1403 dr_mode = "otg"; 1404 usb-role-switch; 1405 1406 ports { 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 1410 port@0 { 1411 reg = <0>; 1412 1413 usb_dwc3_hs: endpoint { 1414 }; 1415 }; 1416 1417 port@1 { 1418 reg = <1>; 1419 1420 usb_dwc3_ss: endpoint { 1421 remote-endpoint = <&usb_qmpphy_usb_ss_in>; 1422 }; 1423 }; 1424 }; 1425 }; 1426 }; 1427 1428 mdss: display-subsystem@5e00000 { 1429 compatible = "qcom,qcm2290-mdss"; 1430 reg = <0x0 0x05e00000 0x0 0x1000>; 1431 reg-names = "mdss"; 1432 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1433 interrupt-controller; 1434 #interrupt-cells = <1>; 1435 1436 clocks = <&gcc GCC_DISP_AHB_CLK>, 1437 <&gcc GCC_DISP_HF_AXI_CLK>, 1438 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1439 clock-names = "iface", 1440 "bus", 1441 "core"; 1442 1443 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 1444 1445 power-domains = <&dispcc MDSS_GDSC>; 1446 1447 iommus = <&apps_smmu 0x420 0x2>, 1448 <&apps_smmu 0x421 0x0>; 1449 interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG 1450 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1451 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1452 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; 1453 interconnect-names = "mdp0-mem", 1454 "cpu-cfg"; 1455 1456 #address-cells = <2>; 1457 #size-cells = <2>; 1458 ranges; 1459 1460 status = "disabled"; 1461 1462 mdp: display-controller@5e01000 { 1463 compatible = "qcom,qcm2290-dpu"; 1464 reg = <0x0 0x05e01000 0x0 0x8f000>, 1465 <0x0 0x05eb0000 0x0 0x2008>; 1466 reg-names = "mdp", 1467 "vbif"; 1468 1469 interrupt-parent = <&mdss>; 1470 interrupts = <0>; 1471 1472 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1473 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1474 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1475 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1476 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1477 clock-names = "bus", 1478 "iface", 1479 "core", 1480 "lut", 1481 "vsync"; 1482 1483 operating-points-v2 = <&mdp_opp_table>; 1484 power-domains = <&rpmpd QCM2290_VDDCX>; 1485 1486 ports { 1487 #address-cells = <1>; 1488 #size-cells = <0>; 1489 1490 port@0 { 1491 reg = <0>; 1492 dpu_intf1_out: endpoint { 1493 remote-endpoint = <&mdss_dsi0_in>; 1494 }; 1495 }; 1496 }; 1497 1498 mdp_opp_table: opp-table { 1499 compatible = "operating-points-v2"; 1500 1501 opp-19200000 { 1502 opp-hz = /bits/ 64 <19200000>; 1503 required-opps = <&rpmpd_opp_min_svs>; 1504 }; 1505 1506 opp-192000000 { 1507 opp-hz = /bits/ 64 <192000000>; 1508 required-opps = <&rpmpd_opp_low_svs>; 1509 }; 1510 1511 opp-256000000 { 1512 opp-hz = /bits/ 64 <256000000>; 1513 required-opps = <&rpmpd_opp_svs>; 1514 }; 1515 1516 opp-307200000 { 1517 opp-hz = /bits/ 64 <307200000>; 1518 required-opps = <&rpmpd_opp_svs_plus>; 1519 }; 1520 1521 opp-384000000 { 1522 opp-hz = /bits/ 64 <384000000>; 1523 required-opps = <&rpmpd_opp_nom>; 1524 }; 1525 }; 1526 }; 1527 1528 mdss_dsi0: dsi@5e94000 { 1529 compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1530 reg = <0x0 0x05e94000 0x0 0x400>; 1531 reg-names = "dsi_ctrl"; 1532 1533 interrupt-parent = <&mdss>; 1534 interrupts = <4>; 1535 1536 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1537 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1538 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1539 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1540 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1541 <&gcc GCC_DISP_HF_AXI_CLK>; 1542 clock-names = "byte", 1543 "byte_intf", 1544 "pixel", 1545 "core", 1546 "iface", 1547 "bus"; 1548 1549 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1550 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1551 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1552 <&mdss_dsi0_phy 1>; 1553 1554 operating-points-v2 = <&dsi_opp_table>; 1555 power-domains = <&rpmpd QCM2290_VDDCX>; 1556 phys = <&mdss_dsi0_phy>; 1557 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 1561 status = "disabled"; 1562 1563 dsi_opp_table: opp-table { 1564 compatible = "operating-points-v2"; 1565 1566 opp-19200000 { 1567 opp-hz = /bits/ 64 <19200000>; 1568 required-opps = <&rpmpd_opp_min_svs>; 1569 }; 1570 1571 opp-164000000 { 1572 opp-hz = /bits/ 64 <164000000>; 1573 required-opps = <&rpmpd_opp_low_svs>; 1574 }; 1575 1576 opp-187500000 { 1577 opp-hz = /bits/ 64 <187500000>; 1578 required-opps = <&rpmpd_opp_svs>; 1579 }; 1580 }; 1581 1582 ports { 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 1586 port@0 { 1587 reg = <0>; 1588 1589 mdss_dsi0_in: endpoint { 1590 remote-endpoint = <&dpu_intf1_out>; 1591 }; 1592 }; 1593 1594 port@1 { 1595 reg = <1>; 1596 1597 mdss_dsi0_out: endpoint { 1598 }; 1599 }; 1600 }; 1601 }; 1602 1603 mdss_dsi0_phy: phy@5e94400 { 1604 compatible = "qcom,dsi-phy-14nm-2290"; 1605 reg = <0x0 0x05e94400 0x0 0x100>, 1606 <0x0 0x05e94500 0x0 0x300>, 1607 <0x0 0x05e94800 0x0 0x188>; 1608 reg-names = "dsi_phy", 1609 "dsi_phy_lane", 1610 "dsi_pll"; 1611 1612 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1613 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1614 clock-names = "iface", 1615 "ref"; 1616 1617 power-domains = <&rpmpd QCM2290_VDDMX>; 1618 required-opps = <&rpmpd_opp_nom>; 1619 1620 #clock-cells = <1>; 1621 #phy-cells = <0>; 1622 1623 status = "disabled"; 1624 }; 1625 }; 1626 1627 dispcc: clock-controller@5f00000 { 1628 compatible = "qcom,qcm2290-dispcc"; 1629 reg = <0x0 0x05f00000 0x0 0x20000>; 1630 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1631 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 1632 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1633 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 1634 <&mdss_dsi0_phy 0>, 1635 <&mdss_dsi0_phy 1>; 1636 clock-names = "bi_tcxo", 1637 "bi_tcxo_ao", 1638 "gcc_disp_gpll0_clk_src", 1639 "gcc_disp_gpll0_div_clk_src", 1640 "dsi0_phy_pll_out_byteclk", 1641 "dsi0_phy_pll_out_dsiclk"; 1642 #power-domain-cells = <1>; 1643 #clock-cells = <1>; 1644 #reset-cells = <1>; 1645 }; 1646 1647 remoteproc_mpss: remoteproc@6080000 { 1648 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; 1649 reg = <0x0 0x06080000 0x0 0x100>; 1650 1651 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 1652 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1653 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1654 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1655 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1656 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1657 interrupt-names = "wdog", 1658 "fatal", 1659 "ready", 1660 "handover", 1661 "stop-ack", 1662 "shutdown-ack"; 1663 1664 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1665 clock-names = "xo"; 1666 1667 power-domains = <&rpmpd QCM2290_VDDCX>; 1668 1669 memory-region = <&pil_modem_mem>; 1670 1671 qcom,smem-states = <&modem_smp2p_out 0>; 1672 qcom,smem-state-names = "stop"; 1673 1674 status = "disabled"; 1675 1676 glink-edge { 1677 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 1678 label = "mpss"; 1679 qcom,remote-pid = <1>; 1680 mboxes = <&apcs_glb 12>; 1681 }; 1682 }; 1683 1684 remoteproc_adsp: remoteproc@ab00000 { 1685 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; 1686 reg = <0x0 0x0ab00000 0x0 0x100>; 1687 1688 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 1689 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1690 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1691 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1692 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1693 interrupt-names = "wdog", 1694 "fatal", 1695 "ready", 1696 "handover", 1697 "stop-ack"; 1698 1699 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1700 clock-names = "xo"; 1701 1702 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, 1703 <&rpmpd QCM2290_VDD_LPI_MX>; 1704 1705 memory-region = <&pil_adsp_mem>; 1706 1707 qcom,smem-states = <&adsp_smp2p_out 0>; 1708 qcom,smem-state-names = "stop"; 1709 1710 status = "disabled"; 1711 1712 glink-edge { 1713 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 1714 label = "lpass"; 1715 qcom,remote-pid = <2>; 1716 mboxes = <&apcs_glb 8>; 1717 }; 1718 }; 1719 1720 apps_smmu: iommu@c600000 { 1721 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1722 reg = <0x0 0x0c600000 0x0 0x80000>; 1723 #iommu-cells = <2>; 1724 #global-interrupts = <1>; 1725 1726 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1733 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1734 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1738 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1739 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1740 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1741 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1743 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1745 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1746 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1747 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1748 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1750 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1751 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1752 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1775 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1779 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1780 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1781 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1782 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1791 }; 1792 1793 wifi: wifi@c800000 { 1794 compatible = "qcom,wcn3990-wifi"; 1795 reg = <0x0 0x0c800000 0x0 0x800000>; 1796 reg-names = "membase"; 1797 memory-region = <&wlan_msa_mem>; 1798 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1810 iommus = <&apps_smmu 0x1a0 0x1>; 1811 qcom,msa-fixed-perm; 1812 status = "disabled"; 1813 }; 1814 1815 watchdog@f017000 { 1816 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; 1817 reg = <0x0 0x0f017000 0x0 0x1000>; 1818 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 1819 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1820 clocks = <&sleep_clk>; 1821 }; 1822 1823 apcs_glb: mailbox@f111000 { 1824 compatible = "qcom,qcm2290-apcs-hmss-global"; 1825 reg = <0x0 0x0f111000 0x0 0x1000>; 1826 #mbox-cells = <1>; 1827 }; 1828 1829 timer@f120000 { 1830 compatible = "arm,armv7-timer-mem"; 1831 reg = <0x0 0x0f120000 0x0 0x1000>; 1832 #address-cells = <1>; 1833 #size-cells = <1>; 1834 ranges = <0 0x0 0x0f121000 0x8000>; 1835 1836 frame@0 { 1837 reg = <0x0 0x1000>, 1838 <0x1000 0x1000>; 1839 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1841 frame-number = <0>; 1842 }; 1843 1844 frame@2000 { 1845 reg = <0x2000 0x1000>; 1846 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1847 frame-number = <1>; 1848 status = "disabled"; 1849 }; 1850 1851 frame@3000 { 1852 reg = <0x3000 0x1000>; 1853 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1854 frame-number = <2>; 1855 status = "disabled"; 1856 }; 1857 1858 frame@4000 { 1859 reg = <0x4000 0x1000>; 1860 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1861 frame-number = <3>; 1862 status = "disabled"; 1863 }; 1864 1865 frame@5000 { 1866 reg = <0x5000 0x1000>; 1867 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1868 frame-number = <4>; 1869 status = "disabled"; 1870 }; 1871 1872 frame@6000 { 1873 reg = <0x6000 0x1000>; 1874 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1875 frame-number = <5>; 1876 status = "disabled"; 1877 }; 1878 1879 frame@7000 { 1880 reg = <0x7000 0x1000>; 1881 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1882 frame-number = <6>; 1883 status = "disabled"; 1884 }; 1885 }; 1886 1887 intc: interrupt-controller@f200000 { 1888 compatible = "arm,gic-v3"; 1889 reg = <0x0 0x0f200000 0x0 0x10000>, 1890 <0x0 0x0f300000 0x0 0x100000>; 1891 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1892 #interrupt-cells = <3>; 1893 interrupt-controller; 1894 interrupt-parent = <&intc>; 1895 #redistributor-regions = <1>; 1896 redistributor-stride = <0x0 0x20000>; 1897 }; 1898 1899 cpufreq_hw: cpufreq@f521000 { 1900 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; 1901 reg = <0x0 0x0f521000 0x0 0x1000>; 1902 reg-names = "freq-domain0"; 1903 interrupts-extended = <&lmh_cluster 0>; 1904 interrupt-names = "dcvsh-irq-0"; 1905 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 1906 clock-names = "xo", "alternate"; 1907 1908 #freq-domain-cells = <1>; 1909 #clock-cells = <1>; 1910 }; 1911 1912 lmh_cluster: lmh@f550800 { 1913 compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh"; 1914 reg = <0x0 0x0f550800 0x0 0x400>; 1915 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1916 cpus = <&CPU0>; 1917 qcom,lmh-temp-arm-millicelsius = <65000>; 1918 qcom,lmh-temp-low-millicelsius = <94500>; 1919 qcom,lmh-temp-high-millicelsius = <95000>; 1920 interrupt-controller; 1921 #interrupt-cells = <1>; 1922 }; 1923 }; 1924 1925 thermal-zones { 1926 mapss-thermal { 1927 polling-delay-passive = <0>; 1928 polling-delay = <0>; 1929 1930 thermal-sensors = <&tsens0 0>; 1931 1932 trips { 1933 mapss_alert0: trip-point0 { 1934 temperature = <90000>; 1935 hysteresis = <2000>; 1936 type = "passive"; 1937 }; 1938 1939 mapss_alert1: trip-point1 { 1940 temperature = <95000>; 1941 hysteresis = <2000>; 1942 type = "passive"; 1943 }; 1944 1945 mapss_crit: mapss-crit { 1946 temperature = <110000>; 1947 hysteresis = <1000>; 1948 type = "critical"; 1949 }; 1950 }; 1951 }; 1952 1953 video-thermal { 1954 polling-delay-passive = <0>; 1955 polling-delay = <0>; 1956 1957 thermal-sensors = <&tsens0 1>; 1958 1959 trips { 1960 video_alert0: trip-point0 { 1961 temperature = <90000>; 1962 hysteresis = <2000>; 1963 type = "passive"; 1964 }; 1965 1966 video_alert1: trip-point1 { 1967 temperature = <95000>; 1968 hysteresis = <2000>; 1969 type = "passive"; 1970 }; 1971 1972 video_crit: video-crit { 1973 temperature = <110000>; 1974 hysteresis = <1000>; 1975 type = "critical"; 1976 }; 1977 }; 1978 }; 1979 1980 wlan-thermal { 1981 polling-delay-passive = <0>; 1982 polling-delay = <0>; 1983 1984 thermal-sensors = <&tsens0 2>; 1985 1986 trips { 1987 wlan_alert0: trip-point0 { 1988 temperature = <90000>; 1989 hysteresis = <2000>; 1990 type = "passive"; 1991 }; 1992 1993 wlan_alert1: trip-point1 { 1994 temperature = <95000>; 1995 hysteresis = <2000>; 1996 type = "passive"; 1997 }; 1998 1999 wlan_crit: wlan-crit { 2000 temperature = <110000>; 2001 hysteresis = <1000>; 2002 type = "critical"; 2003 }; 2004 }; 2005 }; 2006 2007 cpuss0-thermal { 2008 polling-delay-passive = <0>; 2009 polling-delay = <0>; 2010 2011 thermal-sensors = <&tsens0 3>; 2012 2013 trips { 2014 cpuss0_alert0: trip-point0 { 2015 temperature = <90000>; 2016 hysteresis = <2000>; 2017 type = "passive"; 2018 }; 2019 2020 cpuss0_alert1: trip-point1 { 2021 temperature = <95000>; 2022 hysteresis = <2000>; 2023 type = "passive"; 2024 }; 2025 2026 cpuss0_crit: cpuss0-crit { 2027 temperature = <110000>; 2028 hysteresis = <1000>; 2029 type = "critical"; 2030 }; 2031 }; 2032 }; 2033 2034 cpuss1-thermal { 2035 polling-delay-passive = <0>; 2036 polling-delay = <0>; 2037 2038 thermal-sensors = <&tsens0 4>; 2039 2040 trips { 2041 cpuss1_alert0: trip-point0 { 2042 temperature = <90000>; 2043 hysteresis = <2000>; 2044 type = "passive"; 2045 }; 2046 2047 cpuss1_alert1: trip-point1 { 2048 temperature = <95000>; 2049 hysteresis = <2000>; 2050 type = "passive"; 2051 }; 2052 2053 cpuss1_crit: cpuss1-crit { 2054 temperature = <110000>; 2055 hysteresis = <1000>; 2056 type = "critical"; 2057 }; 2058 }; 2059 }; 2060 2061 mdm0-thermal { 2062 polling-delay-passive = <0>; 2063 polling-delay = <0>; 2064 2065 thermal-sensors = <&tsens0 5>; 2066 2067 trips { 2068 mdm0_alert0: trip-point0 { 2069 temperature = <90000>; 2070 hysteresis = <2000>; 2071 type = "passive"; 2072 }; 2073 2074 mdm0_alert1: trip-point1 { 2075 temperature = <95000>; 2076 hysteresis = <2000>; 2077 type = "passive"; 2078 }; 2079 2080 mdm0_crit: mdm0-crit { 2081 temperature = <110000>; 2082 hysteresis = <1000>; 2083 type = "critical"; 2084 }; 2085 }; 2086 }; 2087 2088 mdm1-thermal { 2089 polling-delay-passive = <0>; 2090 polling-delay = <0>; 2091 2092 thermal-sensors = <&tsens0 6>; 2093 2094 trips { 2095 mdm1_alert0: trip-point0 { 2096 temperature = <90000>; 2097 hysteresis = <2000>; 2098 type = "passive"; 2099 }; 2100 2101 mdm1_alert1: trip-point1 { 2102 temperature = <95000>; 2103 hysteresis = <2000>; 2104 type = "passive"; 2105 }; 2106 2107 mdm1_crit: mdm1-crit { 2108 temperature = <110000>; 2109 hysteresis = <1000>; 2110 type = "critical"; 2111 }; 2112 }; 2113 }; 2114 2115 gpu-thermal { 2116 polling-delay-passive = <0>; 2117 polling-delay = <0>; 2118 2119 thermal-sensors = <&tsens0 7>; 2120 2121 trips { 2122 gpu_alert0: trip-point0 { 2123 temperature = <90000>; 2124 hysteresis = <2000>; 2125 type = "passive"; 2126 }; 2127 2128 gpu_alert1: trip-point1 { 2129 temperature = <95000>; 2130 hysteresis = <2000>; 2131 type = "passive"; 2132 }; 2133 2134 gpu_crit: gpu-crit { 2135 temperature = <110000>; 2136 hysteresis = <1000>; 2137 type = "critical"; 2138 }; 2139 }; 2140 }; 2141 2142 hm-center-thermal { 2143 polling-delay-passive = <0>; 2144 polling-delay = <0>; 2145 2146 thermal-sensors = <&tsens0 8>; 2147 2148 trips { 2149 hm_center_alert0: trip-point0 { 2150 temperature = <90000>; 2151 hysteresis = <2000>; 2152 type = "passive"; 2153 }; 2154 2155 hm_center_alert1: trip-point1 { 2156 temperature = <95000>; 2157 hysteresis = <2000>; 2158 type = "passive"; 2159 }; 2160 2161 hm_center_crit: hm-center-crit { 2162 temperature = <110000>; 2163 hysteresis = <1000>; 2164 type = "critical"; 2165 }; 2166 }; 2167 }; 2168 2169 camera-thermal { 2170 polling-delay-passive = <0>; 2171 polling-delay = <0>; 2172 2173 thermal-sensors = <&tsens0 9>; 2174 2175 trips { 2176 camera_alert0: trip-point0 { 2177 temperature = <90000>; 2178 hysteresis = <2000>; 2179 type = "passive"; 2180 }; 2181 2182 camera_alert1: trip-point1 { 2183 temperature = <95000>; 2184 hysteresis = <2000>; 2185 type = "passive"; 2186 }; 2187 2188 camera_crit: camera-crit { 2189 temperature = <110000>; 2190 hysteresis = <1000>; 2191 type = "critical"; 2192 }; 2193 }; 2194 }; 2195 }; 2196 2197 timer { 2198 compatible = "arm,armv8-timer"; 2199 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2200 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2201 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2202 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2203 }; 2204}; 2205