1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8998.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/firmware/qcom,scm.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 qcom,msm-id = <292 0x0>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 memory@80000000 { 24 device_type = "memory"; 25 /* We expect the bootloader to fill in the reg */ 26 reg = <0x0 0x80000000 0x0 0x0>; 27 }; 28 29 reserved-memory { 30 #address-cells = <2>; 31 #size-cells = <2>; 32 ranges; 33 34 hyp_mem: memory@85800000 { 35 reg = <0x0 0x85800000 0x0 0x600000>; 36 no-map; 37 }; 38 39 xbl_mem: memory@85e00000 { 40 reg = <0x0 0x85e00000 0x0 0x100000>; 41 no-map; 42 }; 43 44 smem_mem: smem-mem@86000000 { 45 reg = <0x0 0x86000000 0x0 0x200000>; 46 no-map; 47 }; 48 49 tz_mem: memory@86200000 { 50 reg = <0x0 0x86200000 0x0 0x2d00000>; 51 no-map; 52 }; 53 54 rmtfs_mem: memory@88f00000 { 55 compatible = "qcom,rmtfs-mem"; 56 reg = <0x0 0x88f00000 0x0 0x200000>; 57 no-map; 58 59 qcom,client-id = <1>; 60 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 61 }; 62 63 spss_mem: memory@8ab00000 { 64 reg = <0x0 0x8ab00000 0x0 0x700000>; 65 no-map; 66 }; 67 68 adsp_mem: memory@8b200000 { 69 reg = <0x0 0x8b200000 0x0 0x1a00000>; 70 no-map; 71 }; 72 73 mpss_mem: memory@8cc00000 { 74 reg = <0x0 0x8cc00000 0x0 0x7000000>; 75 no-map; 76 }; 77 78 venus_mem: memory@93c00000 { 79 reg = <0x0 0x93c00000 0x0 0x500000>; 80 no-map; 81 }; 82 83 mba_mem: memory@94100000 { 84 reg = <0x0 0x94100000 0x0 0x200000>; 85 no-map; 86 }; 87 88 slpi_mem: memory@94300000 { 89 reg = <0x0 0x94300000 0x0 0xf00000>; 90 no-map; 91 }; 92 93 ipa_fw_mem: memory@95200000 { 94 reg = <0x0 0x95200000 0x0 0x10000>; 95 no-map; 96 }; 97 98 ipa_gsi_mem: memory@95210000 { 99 reg = <0x0 0x95210000 0x0 0x5000>; 100 no-map; 101 }; 102 103 gpu_mem: memory@95600000 { 104 reg = <0x0 0x95600000 0x0 0x100000>; 105 no-map; 106 }; 107 108 wlan_msa_mem: memory@95700000 { 109 reg = <0x0 0x95700000 0x0 0x100000>; 110 no-map; 111 }; 112 113 mdata_mem: mpss-metadata { 114 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 115 size = <0x0 0x4000>; 116 no-map; 117 }; 118 }; 119 120 clocks { 121 xo: xo-board { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <19200000>; 125 clock-output-names = "xo_board"; 126 }; 127 128 sleep_clk: sleep-clk { 129 compatible = "fixed-clock"; 130 #clock-cells = <0>; 131 clock-frequency = <32764>; 132 }; 133 }; 134 135 cpus { 136 #address-cells = <2>; 137 #size-cells = <0>; 138 139 CPU0: cpu@0 { 140 device_type = "cpu"; 141 compatible = "qcom,kryo280"; 142 reg = <0x0 0x0>; 143 enable-method = "psci"; 144 capacity-dmips-mhz = <1024>; 145 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 146 next-level-cache = <&L2_0>; 147 L2_0: l2-cache { 148 compatible = "cache"; 149 cache-level = <2>; 150 cache-unified; 151 }; 152 }; 153 154 CPU1: cpu@1 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo280"; 157 reg = <0x0 0x1>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1024>; 160 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 161 next-level-cache = <&L2_0>; 162 }; 163 164 CPU2: cpu@2 { 165 device_type = "cpu"; 166 compatible = "qcom,kryo280"; 167 reg = <0x0 0x2>; 168 enable-method = "psci"; 169 capacity-dmips-mhz = <1024>; 170 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 171 next-level-cache = <&L2_0>; 172 }; 173 174 CPU3: cpu@3 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo280"; 177 reg = <0x0 0x3>; 178 enable-method = "psci"; 179 capacity-dmips-mhz = <1024>; 180 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 181 next-level-cache = <&L2_0>; 182 }; 183 184 CPU4: cpu@100 { 185 device_type = "cpu"; 186 compatible = "qcom,kryo280"; 187 reg = <0x0 0x100>; 188 enable-method = "psci"; 189 capacity-dmips-mhz = <1536>; 190 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 191 next-level-cache = <&L2_1>; 192 L2_1: l2-cache { 193 compatible = "cache"; 194 cache-level = <2>; 195 cache-unified; 196 }; 197 }; 198 199 CPU5: cpu@101 { 200 device_type = "cpu"; 201 compatible = "qcom,kryo280"; 202 reg = <0x0 0x101>; 203 enable-method = "psci"; 204 capacity-dmips-mhz = <1536>; 205 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 206 next-level-cache = <&L2_1>; 207 }; 208 209 CPU6: cpu@102 { 210 device_type = "cpu"; 211 compatible = "qcom,kryo280"; 212 reg = <0x0 0x102>; 213 enable-method = "psci"; 214 capacity-dmips-mhz = <1536>; 215 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 216 next-level-cache = <&L2_1>; 217 }; 218 219 CPU7: cpu@103 { 220 device_type = "cpu"; 221 compatible = "qcom,kryo280"; 222 reg = <0x0 0x103>; 223 enable-method = "psci"; 224 capacity-dmips-mhz = <1536>; 225 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 226 next-level-cache = <&L2_1>; 227 }; 228 229 cpu-map { 230 cluster0 { 231 core0 { 232 cpu = <&CPU0>; 233 }; 234 235 core1 { 236 cpu = <&CPU1>; 237 }; 238 239 core2 { 240 cpu = <&CPU2>; 241 }; 242 243 core3 { 244 cpu = <&CPU3>; 245 }; 246 }; 247 248 cluster1 { 249 core0 { 250 cpu = <&CPU4>; 251 }; 252 253 core1 { 254 cpu = <&CPU5>; 255 }; 256 257 core2 { 258 cpu = <&CPU6>; 259 }; 260 261 core3 { 262 cpu = <&CPU7>; 263 }; 264 }; 265 }; 266 267 idle-states { 268 entry-method = "psci"; 269 270 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 271 compatible = "arm,idle-state"; 272 idle-state-name = "little-retention"; 273 /* CPU Retention (C2D), L2 Active */ 274 arm,psci-suspend-param = <0x00000002>; 275 entry-latency-us = <81>; 276 exit-latency-us = <86>; 277 min-residency-us = <504>; 278 }; 279 280 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 281 compatible = "arm,idle-state"; 282 idle-state-name = "little-power-collapse"; 283 /* CPU + L2 Power Collapse (C3, D4) */ 284 arm,psci-suspend-param = <0x40000003>; 285 entry-latency-us = <814>; 286 exit-latency-us = <4562>; 287 min-residency-us = <9183>; 288 local-timer-stop; 289 }; 290 291 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "big-retention"; 294 /* CPU Retention (C2D), L2 Active */ 295 arm,psci-suspend-param = <0x00000002>; 296 entry-latency-us = <79>; 297 exit-latency-us = <82>; 298 min-residency-us = <1302>; 299 }; 300 301 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "big-power-collapse"; 304 /* CPU + L2 Power Collapse (C3, D4) */ 305 arm,psci-suspend-param = <0x40000003>; 306 entry-latency-us = <724>; 307 exit-latency-us = <2027>; 308 min-residency-us = <9419>; 309 local-timer-stop; 310 }; 311 }; 312 }; 313 314 firmware { 315 scm { 316 compatible = "qcom,scm-msm8998", "qcom,scm"; 317 }; 318 }; 319 320 dsi_opp_table: opp-table-dsi { 321 compatible = "operating-points-v2"; 322 323 opp-131250000 { 324 opp-hz = /bits/ 64 <131250000>; 325 required-opps = <&rpmpd_opp_low_svs>; 326 }; 327 328 opp-210000000 { 329 opp-hz = /bits/ 64 <210000000>; 330 required-opps = <&rpmpd_opp_svs>; 331 }; 332 333 opp-312500000 { 334 opp-hz = /bits/ 64 <312500000>; 335 required-opps = <&rpmpd_opp_nom>; 336 }; 337 }; 338 339 psci { 340 compatible = "arm,psci-1.0"; 341 method = "smc"; 342 }; 343 344 rpm: remoteproc { 345 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; 346 347 glink-edge { 348 compatible = "qcom,glink-rpm"; 349 350 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 351 qcom,rpm-msg-ram = <&rpm_msg_ram>; 352 mboxes = <&apcs_glb 0>; 353 354 rpm_requests: rpm-requests { 355 compatible = "qcom,rpm-msm8998"; 356 qcom,glink-channels = "rpm_requests"; 357 358 rpmcc: clock-controller { 359 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 360 clocks = <&xo>; 361 clock-names = "xo"; 362 #clock-cells = <1>; 363 }; 364 365 rpmpd: power-controller { 366 compatible = "qcom,msm8998-rpmpd"; 367 #power-domain-cells = <1>; 368 operating-points-v2 = <&rpmpd_opp_table>; 369 370 rpmpd_opp_table: opp-table { 371 compatible = "operating-points-v2"; 372 373 rpmpd_opp_ret: opp1 { 374 opp-level = <RPM_SMD_LEVEL_RETENTION>; 375 }; 376 377 rpmpd_opp_ret_plus: opp2 { 378 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 379 }; 380 381 rpmpd_opp_min_svs: opp3 { 382 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 383 }; 384 385 rpmpd_opp_low_svs: opp4 { 386 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 387 }; 388 389 rpmpd_opp_svs: opp5 { 390 opp-level = <RPM_SMD_LEVEL_SVS>; 391 }; 392 393 rpmpd_opp_svs_plus: opp6 { 394 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 395 }; 396 397 rpmpd_opp_nom: opp7 { 398 opp-level = <RPM_SMD_LEVEL_NOM>; 399 }; 400 401 rpmpd_opp_nom_plus: opp8 { 402 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 403 }; 404 405 rpmpd_opp_turbo: opp9 { 406 opp-level = <RPM_SMD_LEVEL_TURBO>; 407 }; 408 409 rpmpd_opp_turbo_plus: opp10 { 410 opp-level = <RPM_SMD_LEVEL_BINNING>; 411 }; 412 }; 413 }; 414 }; 415 }; 416 }; 417 418 smem { 419 compatible = "qcom,smem"; 420 memory-region = <&smem_mem>; 421 hwlocks = <&tcsr_mutex 3>; 422 }; 423 424 smp2p-lpass { 425 compatible = "qcom,smp2p"; 426 qcom,smem = <443>, <429>; 427 428 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 429 430 mboxes = <&apcs_glb 10>; 431 432 qcom,local-pid = <0>; 433 qcom,remote-pid = <2>; 434 435 adsp_smp2p_out: master-kernel { 436 qcom,entry-name = "master-kernel"; 437 #qcom,smem-state-cells = <1>; 438 }; 439 440 adsp_smp2p_in: slave-kernel { 441 qcom,entry-name = "slave-kernel"; 442 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 }; 446 }; 447 448 smp2p-mpss { 449 compatible = "qcom,smp2p"; 450 qcom,smem = <435>, <428>; 451 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 452 mboxes = <&apcs_glb 14>; 453 qcom,local-pid = <0>; 454 qcom,remote-pid = <1>; 455 456 modem_smp2p_out: master-kernel { 457 qcom,entry-name = "master-kernel"; 458 #qcom,smem-state-cells = <1>; 459 }; 460 461 modem_smp2p_in: slave-kernel { 462 qcom,entry-name = "slave-kernel"; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 }; 466 }; 467 468 smp2p-slpi { 469 compatible = "qcom,smp2p"; 470 qcom,smem = <481>, <430>; 471 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 472 mboxes = <&apcs_glb 26>; 473 qcom,local-pid = <0>; 474 qcom,remote-pid = <3>; 475 476 slpi_smp2p_out: master-kernel { 477 qcom,entry-name = "master-kernel"; 478 #qcom,smem-state-cells = <1>; 479 }; 480 481 slpi_smp2p_in: slave-kernel { 482 qcom,entry-name = "slave-kernel"; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 }; 486 }; 487 488 thermal-zones { 489 cpu0-thermal { 490 polling-delay-passive = <250>; 491 polling-delay = <1000>; 492 493 thermal-sensors = <&tsens0 1>; 494 495 trips { 496 cpu0_alert0: trip-point0 { 497 temperature = <75000>; 498 hysteresis = <2000>; 499 type = "passive"; 500 }; 501 502 cpu0_crit: cpu-crit { 503 temperature = <110000>; 504 hysteresis = <2000>; 505 type = "critical"; 506 }; 507 }; 508 }; 509 510 cpu1-thermal { 511 polling-delay-passive = <250>; 512 polling-delay = <1000>; 513 514 thermal-sensors = <&tsens0 2>; 515 516 trips { 517 cpu1_alert0: trip-point0 { 518 temperature = <75000>; 519 hysteresis = <2000>; 520 type = "passive"; 521 }; 522 523 cpu1_crit: cpu-crit { 524 temperature = <110000>; 525 hysteresis = <2000>; 526 type = "critical"; 527 }; 528 }; 529 }; 530 531 cpu2-thermal { 532 polling-delay-passive = <250>; 533 polling-delay = <1000>; 534 535 thermal-sensors = <&tsens0 3>; 536 537 trips { 538 cpu2_alert0: trip-point0 { 539 temperature = <75000>; 540 hysteresis = <2000>; 541 type = "passive"; 542 }; 543 544 cpu2_crit: cpu-crit { 545 temperature = <110000>; 546 hysteresis = <2000>; 547 type = "critical"; 548 }; 549 }; 550 }; 551 552 cpu3-thermal { 553 polling-delay-passive = <250>; 554 polling-delay = <1000>; 555 556 thermal-sensors = <&tsens0 4>; 557 558 trips { 559 cpu3_alert0: trip-point0 { 560 temperature = <75000>; 561 hysteresis = <2000>; 562 type = "passive"; 563 }; 564 565 cpu3_crit: cpu-crit { 566 temperature = <110000>; 567 hysteresis = <2000>; 568 type = "critical"; 569 }; 570 }; 571 }; 572 573 cpu4-thermal { 574 polling-delay-passive = <250>; 575 polling-delay = <1000>; 576 577 thermal-sensors = <&tsens0 7>; 578 579 trips { 580 cpu4_alert0: trip-point0 { 581 temperature = <75000>; 582 hysteresis = <2000>; 583 type = "passive"; 584 }; 585 586 cpu4_crit: cpu-crit { 587 temperature = <110000>; 588 hysteresis = <2000>; 589 type = "critical"; 590 }; 591 }; 592 }; 593 594 cpu5-thermal { 595 polling-delay-passive = <250>; 596 polling-delay = <1000>; 597 598 thermal-sensors = <&tsens0 8>; 599 600 trips { 601 cpu5_alert0: trip-point0 { 602 temperature = <75000>; 603 hysteresis = <2000>; 604 type = "passive"; 605 }; 606 607 cpu5_crit: cpu-crit { 608 temperature = <110000>; 609 hysteresis = <2000>; 610 type = "critical"; 611 }; 612 }; 613 }; 614 615 cpu6-thermal { 616 polling-delay-passive = <250>; 617 polling-delay = <1000>; 618 619 thermal-sensors = <&tsens0 9>; 620 621 trips { 622 cpu6_alert0: trip-point0 { 623 temperature = <75000>; 624 hysteresis = <2000>; 625 type = "passive"; 626 }; 627 628 cpu6_crit: cpu-crit { 629 temperature = <110000>; 630 hysteresis = <2000>; 631 type = "critical"; 632 }; 633 }; 634 }; 635 636 cpu7-thermal { 637 polling-delay-passive = <250>; 638 polling-delay = <1000>; 639 640 thermal-sensors = <&tsens0 10>; 641 642 trips { 643 cpu7_alert0: trip-point0 { 644 temperature = <75000>; 645 hysteresis = <2000>; 646 type = "passive"; 647 }; 648 649 cpu7_crit: cpu-crit { 650 temperature = <110000>; 651 hysteresis = <2000>; 652 type = "critical"; 653 }; 654 }; 655 }; 656 657 gpu-bottom-thermal { 658 polling-delay-passive = <250>; 659 polling-delay = <1000>; 660 661 thermal-sensors = <&tsens0 12>; 662 663 trips { 664 gpu1_alert0: trip-point0 { 665 temperature = <90000>; 666 hysteresis = <2000>; 667 type = "hot"; 668 }; 669 }; 670 }; 671 672 gpu-top-thermal { 673 polling-delay-passive = <250>; 674 polling-delay = <1000>; 675 676 thermal-sensors = <&tsens0 13>; 677 678 trips { 679 gpu2_alert0: trip-point0 { 680 temperature = <90000>; 681 hysteresis = <2000>; 682 type = "hot"; 683 }; 684 }; 685 }; 686 687 clust0-mhm-thermal { 688 polling-delay-passive = <250>; 689 polling-delay = <1000>; 690 691 thermal-sensors = <&tsens0 5>; 692 693 trips { 694 cluster0_mhm_alert0: trip-point0 { 695 temperature = <90000>; 696 hysteresis = <2000>; 697 type = "hot"; 698 }; 699 }; 700 }; 701 702 clust1-mhm-thermal { 703 polling-delay-passive = <250>; 704 polling-delay = <1000>; 705 706 thermal-sensors = <&tsens0 6>; 707 708 trips { 709 cluster1_mhm_alert0: trip-point0 { 710 temperature = <90000>; 711 hysteresis = <2000>; 712 type = "hot"; 713 }; 714 }; 715 }; 716 717 cluster1-l2-thermal { 718 polling-delay-passive = <250>; 719 polling-delay = <1000>; 720 721 thermal-sensors = <&tsens0 11>; 722 723 trips { 724 cluster1_l2_alert0: trip-point0 { 725 temperature = <90000>; 726 hysteresis = <2000>; 727 type = "hot"; 728 }; 729 }; 730 }; 731 732 modem-thermal { 733 polling-delay-passive = <250>; 734 polling-delay = <1000>; 735 736 thermal-sensors = <&tsens1 1>; 737 738 trips { 739 modem_alert0: trip-point0 { 740 temperature = <90000>; 741 hysteresis = <2000>; 742 type = "hot"; 743 }; 744 }; 745 }; 746 747 mem-thermal { 748 polling-delay-passive = <250>; 749 polling-delay = <1000>; 750 751 thermal-sensors = <&tsens1 2>; 752 753 trips { 754 mem_alert0: trip-point0 { 755 temperature = <90000>; 756 hysteresis = <2000>; 757 type = "hot"; 758 }; 759 }; 760 }; 761 762 wlan-thermal { 763 polling-delay-passive = <250>; 764 polling-delay = <1000>; 765 766 thermal-sensors = <&tsens1 3>; 767 768 trips { 769 wlan_alert0: trip-point0 { 770 temperature = <90000>; 771 hysteresis = <2000>; 772 type = "hot"; 773 }; 774 }; 775 }; 776 777 q6-dsp-thermal { 778 polling-delay-passive = <250>; 779 polling-delay = <1000>; 780 781 thermal-sensors = <&tsens1 4>; 782 783 trips { 784 q6_dsp_alert0: trip-point0 { 785 temperature = <90000>; 786 hysteresis = <2000>; 787 type = "hot"; 788 }; 789 }; 790 }; 791 792 camera-thermal { 793 polling-delay-passive = <250>; 794 polling-delay = <1000>; 795 796 thermal-sensors = <&tsens1 5>; 797 798 trips { 799 camera_alert0: trip-point0 { 800 temperature = <90000>; 801 hysteresis = <2000>; 802 type = "hot"; 803 }; 804 }; 805 }; 806 807 multimedia-thermal { 808 polling-delay-passive = <250>; 809 polling-delay = <1000>; 810 811 thermal-sensors = <&tsens1 6>; 812 813 trips { 814 multimedia_alert0: trip-point0 { 815 temperature = <90000>; 816 hysteresis = <2000>; 817 type = "hot"; 818 }; 819 }; 820 }; 821 }; 822 823 timer { 824 compatible = "arm,armv8-timer"; 825 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 826 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 827 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 828 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 829 }; 830 831 soc: soc@0 { 832 #address-cells = <1>; 833 #size-cells = <1>; 834 ranges = <0 0 0 0xffffffff>; 835 compatible = "simple-bus"; 836 837 gcc: clock-controller@100000 { 838 compatible = "qcom,gcc-msm8998"; 839 #clock-cells = <1>; 840 #reset-cells = <1>; 841 #power-domain-cells = <1>; 842 reg = <0x00100000 0xb0000>; 843 844 clock-names = "xo", "sleep_clk"; 845 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 846 847 /* 848 * The hypervisor typically configures the memory region where these clocks 849 * reside as read-only for the HLOS. If the HLOS tried to enable or disable 850 * these clocks on a device with such configuration (e.g. because they are 851 * enabled but unused during boot-up), the device will most likely decide 852 * to reboot. 853 * In light of that, we are conservative here and we list all such clocks 854 * as protected. The board dts (or a user-supplied dts) can override the 855 * list of protected clocks if it differs from the norm, and it is in fact 856 * desired for the HLOS to manage these clocks 857 */ 858 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>, 859 <SSC_XO>, 860 <SSC_CNOC_AHBS_CLK>; 861 }; 862 863 rpm_msg_ram: sram@778000 { 864 compatible = "qcom,rpm-msg-ram"; 865 reg = <0x00778000 0x7000>; 866 }; 867 868 qfprom: qfprom@784000 { 869 compatible = "qcom,msm8998-qfprom", "qcom,qfprom"; 870 reg = <0x00784000 0x621c>; 871 #address-cells = <1>; 872 #size-cells = <1>; 873 874 qusb2_hstx_trim: hstx-trim@23a { 875 reg = <0x23a 0x1>; 876 bits = <0 4>; 877 }; 878 }; 879 880 tsens0: thermal@10ab000 { 881 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 882 reg = <0x010ab000 0x1000>, /* TM */ 883 <0x010aa000 0x1000>; /* SROT */ 884 #qcom,sensors = <14>; 885 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 887 interrupt-names = "uplow", "critical"; 888 #thermal-sensor-cells = <1>; 889 }; 890 891 tsens1: thermal@10ae000 { 892 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 893 reg = <0x010ae000 0x1000>, /* TM */ 894 <0x010ad000 0x1000>; /* SROT */ 895 #qcom,sensors = <8>; 896 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 898 interrupt-names = "uplow", "critical"; 899 #thermal-sensor-cells = <1>; 900 }; 901 902 anoc1_smmu: iommu@1680000 { 903 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 904 reg = <0x01680000 0x10000>; 905 #iommu-cells = <1>; 906 907 #global-interrupts = <0>; 908 interrupts = 909 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 910 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 911 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 912 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 913 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 914 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 915 }; 916 917 anoc2_smmu: iommu@16c0000 { 918 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 919 reg = <0x016c0000 0x40000>; 920 #iommu-cells = <1>; 921 922 #global-interrupts = <0>; 923 interrupts = 924 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 925 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 926 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 927 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 928 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 929 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 930 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 931 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 932 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 933 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 934 }; 935 936 pcie0: pcie@1c00000 { 937 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; 938 reg = <0x01c00000 0x2000>, 939 <0x1b000000 0xf1d>, 940 <0x1b000f20 0xa8>, 941 <0x1b100000 0x100000>; 942 reg-names = "parf", "dbi", "elbi", "config"; 943 device_type = "pci"; 944 linux,pci-domain = <0>; 945 bus-range = <0x00 0xff>; 946 #address-cells = <3>; 947 #size-cells = <2>; 948 num-lanes = <1>; 949 phys = <&pcie_phy>; 950 phy-names = "pciephy"; 951 status = "disabled"; 952 953 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, 954 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 955 956 #interrupt-cells = <1>; 957 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 958 interrupt-names = "msi"; 959 interrupt-map-mask = <0 0 0 0x7>; 960 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, 961 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, 962 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, 963 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; 964 965 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 966 <&gcc GCC_PCIE_0_AUX_CLK>, 967 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 968 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 969 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 970 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave"; 971 972 power-domains = <&gcc PCIE_0_GDSC>; 973 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 974 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 975 }; 976 977 pcie_phy: phy@1c06000 { 978 compatible = "qcom,msm8998-qmp-pcie-phy"; 979 reg = <0x01c06000 0x1000>; 980 status = "disabled"; 981 982 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 983 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 984 <&gcc GCC_PCIE_CLKREF_CLK>, 985 <&gcc GCC_PCIE_0_PIPE_CLK>; 986 clock-names = "aux", 987 "cfg_ahb", 988 "ref", 989 "pipe"; 990 991 clock-output-names = "pcie_0_pipe_clk_src"; 992 #clock-cells = <0>; 993 994 #phy-cells = <0>; 995 996 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 997 reset-names = "phy", "common"; 998 999 vdda-phy-supply = <&vreg_l1a_0p875>; 1000 vdda-pll-supply = <&vreg_l2a_1p2>; 1001 }; 1002 1003 ufshc: ufshc@1da4000 { 1004 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1005 reg = <0x01da4000 0x2500>; 1006 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1007 phys = <&ufsphy>; 1008 phy-names = "ufsphy"; 1009 lanes-per-direction = <2>; 1010 power-domains = <&gcc UFS_GDSC>; 1011 status = "disabled"; 1012 #reset-cells = <1>; 1013 1014 clock-names = 1015 "core_clk", 1016 "bus_aggr_clk", 1017 "iface_clk", 1018 "core_clk_unipro", 1019 "ref_clk", 1020 "tx_lane0_sync_clk", 1021 "rx_lane0_sync_clk", 1022 "rx_lane1_sync_clk"; 1023 clocks = 1024 <&gcc GCC_UFS_AXI_CLK>, 1025 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1026 <&gcc GCC_UFS_AHB_CLK>, 1027 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1028 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1029 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1030 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1031 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1032 freq-table-hz = 1033 <50000000 200000000>, 1034 <0 0>, 1035 <0 0>, 1036 <37500000 150000000>, 1037 <0 0>, 1038 <0 0>, 1039 <0 0>, 1040 <0 0>; 1041 1042 resets = <&gcc GCC_UFS_BCR>; 1043 reset-names = "rst"; 1044 }; 1045 1046 ufsphy: phy@1da7000 { 1047 compatible = "qcom,msm8998-qmp-ufs-phy"; 1048 reg = <0x01da7000 0x1000>; 1049 1050 clocks = <&rpmcc RPM_SMD_LN_BB_CLK1>, 1051 <&gcc GCC_UFS_PHY_AUX_CLK>, 1052 <&gcc GCC_UFS_CLKREF_CLK>; 1053 clock-names = "ref", 1054 "ref_aux", 1055 "qref"; 1056 1057 reset-names = "ufsphy"; 1058 resets = <&ufshc 0>; 1059 1060 #phy-cells = <0>; 1061 status = "disabled"; 1062 }; 1063 1064 tcsr_mutex: hwlock@1f40000 { 1065 compatible = "qcom,tcsr-mutex"; 1066 reg = <0x01f40000 0x20000>; 1067 #hwlock-cells = <1>; 1068 }; 1069 1070 tcsr_regs_1: syscon@1f60000 { 1071 compatible = "qcom,msm8998-tcsr", "syscon"; 1072 reg = <0x01f60000 0x20000>; 1073 }; 1074 1075 tcsr_regs_2: syscon@1fc0000 { 1076 compatible = "qcom,msm8998-tcsr", "syscon"; 1077 reg = <0x01fc0000 0x26000>; 1078 }; 1079 1080 tlmm: pinctrl@3400000 { 1081 compatible = "qcom,msm8998-pinctrl"; 1082 reg = <0x03400000 0xc00000>; 1083 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1084 gpio-ranges = <&tlmm 0 0 150>; 1085 gpio-controller; 1086 #gpio-cells = <2>; 1087 interrupt-controller; 1088 #interrupt-cells = <2>; 1089 1090 sdc2_on: sdc2-on-state { 1091 clk-pins { 1092 pins = "sdc2_clk"; 1093 drive-strength = <16>; 1094 bias-disable; 1095 }; 1096 1097 cmd-pins { 1098 pins = "sdc2_cmd"; 1099 drive-strength = <10>; 1100 bias-pull-up; 1101 }; 1102 1103 data-pins { 1104 pins = "sdc2_data"; 1105 drive-strength = <10>; 1106 bias-pull-up; 1107 }; 1108 }; 1109 1110 sdc2_off: sdc2-off-state { 1111 clk-pins { 1112 pins = "sdc2_clk"; 1113 drive-strength = <2>; 1114 bias-disable; 1115 }; 1116 1117 cmd-pins { 1118 pins = "sdc2_cmd"; 1119 drive-strength = <2>; 1120 bias-pull-up; 1121 }; 1122 1123 data-pins { 1124 pins = "sdc2_data"; 1125 drive-strength = <2>; 1126 bias-pull-up; 1127 }; 1128 }; 1129 1130 sdc2_cd: sdc2-cd-state { 1131 pins = "gpio95"; 1132 function = "gpio"; 1133 bias-pull-up; 1134 drive-strength = <2>; 1135 }; 1136 1137 blsp1_uart3_on: blsp1-uart3-on-state { 1138 tx-pins { 1139 pins = "gpio45"; 1140 function = "blsp_uart3_a"; 1141 drive-strength = <2>; 1142 bias-disable; 1143 }; 1144 1145 rx-pins { 1146 pins = "gpio46"; 1147 function = "blsp_uart3_a"; 1148 drive-strength = <2>; 1149 bias-disable; 1150 }; 1151 1152 cts-pins { 1153 pins = "gpio47"; 1154 function = "blsp_uart3_a"; 1155 drive-strength = <2>; 1156 bias-disable; 1157 }; 1158 1159 rfr-pins { 1160 pins = "gpio48"; 1161 function = "blsp_uart3_a"; 1162 drive-strength = <2>; 1163 bias-disable; 1164 }; 1165 }; 1166 1167 blsp1_i2c1_default: blsp1-i2c1-default-state { 1168 pins = "gpio2", "gpio3"; 1169 function = "blsp_i2c1"; 1170 drive-strength = <2>; 1171 bias-disable; 1172 }; 1173 1174 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state { 1175 pins = "gpio2", "gpio3"; 1176 function = "blsp_i2c1"; 1177 drive-strength = <2>; 1178 bias-pull-up; 1179 }; 1180 1181 blsp1_i2c2_default: blsp1-i2c2-default-state { 1182 pins = "gpio32", "gpio33"; 1183 function = "blsp_i2c2"; 1184 drive-strength = <2>; 1185 bias-disable; 1186 }; 1187 1188 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state { 1189 pins = "gpio32", "gpio33"; 1190 function = "blsp_i2c2"; 1191 drive-strength = <2>; 1192 bias-pull-up; 1193 }; 1194 1195 blsp1_i2c3_default: blsp1-i2c3-default-state { 1196 pins = "gpio47", "gpio48"; 1197 function = "blsp_i2c3"; 1198 drive-strength = <2>; 1199 bias-disable; 1200 }; 1201 1202 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1203 pins = "gpio47", "gpio48"; 1204 function = "blsp_i2c3"; 1205 drive-strength = <2>; 1206 bias-pull-up; 1207 }; 1208 1209 blsp1_i2c4_default: blsp1-i2c4-default-state { 1210 pins = "gpio10", "gpio11"; 1211 function = "blsp_i2c4"; 1212 drive-strength = <2>; 1213 bias-disable; 1214 }; 1215 1216 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 1217 pins = "gpio10", "gpio11"; 1218 function = "blsp_i2c4"; 1219 drive-strength = <2>; 1220 bias-pull-up; 1221 }; 1222 1223 blsp1_i2c5_default: blsp1-i2c5-default-state { 1224 pins = "gpio87", "gpio88"; 1225 function = "blsp_i2c5"; 1226 drive-strength = <2>; 1227 bias-disable; 1228 }; 1229 1230 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state { 1231 pins = "gpio87", "gpio88"; 1232 function = "blsp_i2c5"; 1233 drive-strength = <2>; 1234 bias-pull-up; 1235 }; 1236 1237 blsp1_i2c6_default: blsp1-i2c6-default-state { 1238 pins = "gpio43", "gpio44"; 1239 function = "blsp_i2c6"; 1240 drive-strength = <2>; 1241 bias-disable; 1242 }; 1243 1244 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1245 pins = "gpio43", "gpio44"; 1246 function = "blsp_i2c6"; 1247 drive-strength = <2>; 1248 bias-pull-up; 1249 }; 1250 1251 blsp1_spi_b_default: blsp1-spi-b-default-state { 1252 pins = "gpio23", "gpio28"; 1253 function = "blsp1_spi_b"; 1254 drive-strength = <6>; 1255 bias-disable; 1256 }; 1257 1258 blsp1_spi1_default: blsp1-spi1-default-state { 1259 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1260 function = "blsp_spi1"; 1261 drive-strength = <6>; 1262 bias-disable; 1263 }; 1264 1265 blsp1_spi2_default: blsp1-spi2-default-state { 1266 pins = "gpio31", "gpio34", "gpio32", "gpio33"; 1267 function = "blsp_spi2"; 1268 drive-strength = <6>; 1269 bias-disable; 1270 }; 1271 1272 blsp1_spi3_default: blsp1-spi3-default-state { 1273 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 1274 function = "blsp_spi2"; 1275 drive-strength = <6>; 1276 bias-disable; 1277 }; 1278 1279 blsp1_spi4_default: blsp1-spi4-default-state { 1280 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 1281 function = "blsp_spi4"; 1282 drive-strength = <6>; 1283 bias-disable; 1284 }; 1285 1286 blsp1_spi5_default: blsp1-spi5-default-state { 1287 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1288 function = "blsp_spi5"; 1289 drive-strength = <6>; 1290 bias-disable; 1291 }; 1292 1293 blsp1_spi6_default: blsp1-spi6-default-state { 1294 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1295 function = "blsp_spi6"; 1296 drive-strength = <6>; 1297 bias-disable; 1298 }; 1299 1300 1301 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1302 blsp2_i2c1_default: blsp2-i2c1-default-state { 1303 pins = "gpio55", "gpio56"; 1304 function = "blsp_i2c7"; 1305 drive-strength = <2>; 1306 bias-disable; 1307 }; 1308 1309 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1310 pins = "gpio55", "gpio56"; 1311 function = "blsp_i2c7"; 1312 drive-strength = <2>; 1313 bias-pull-up; 1314 }; 1315 1316 blsp2_i2c2_default: blsp2-i2c2-default-state { 1317 pins = "gpio6", "gpio7"; 1318 function = "blsp_i2c8"; 1319 drive-strength = <2>; 1320 bias-disable; 1321 }; 1322 1323 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1324 pins = "gpio6", "gpio7"; 1325 function = "blsp_i2c8"; 1326 drive-strength = <2>; 1327 bias-pull-up; 1328 }; 1329 1330 blsp2_i2c3_default: blsp2-i2c3-default-state { 1331 pins = "gpio51", "gpio52"; 1332 function = "blsp_i2c9"; 1333 drive-strength = <2>; 1334 bias-disable; 1335 }; 1336 1337 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1338 pins = "gpio51", "gpio52"; 1339 function = "blsp_i2c9"; 1340 drive-strength = <2>; 1341 bias-pull-up; 1342 }; 1343 1344 blsp2_i2c4_default: blsp2-i2c4-default-state { 1345 pins = "gpio67", "gpio68"; 1346 function = "blsp_i2c10"; 1347 drive-strength = <2>; 1348 bias-disable; 1349 }; 1350 1351 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 1352 pins = "gpio67", "gpio68"; 1353 function = "blsp_i2c10"; 1354 drive-strength = <2>; 1355 bias-pull-up; 1356 }; 1357 1358 blsp2_i2c5_default: blsp2-i2c5-default-state { 1359 pins = "gpio60", "gpio61"; 1360 function = "blsp_i2c11"; 1361 drive-strength = <2>; 1362 bias-disable; 1363 }; 1364 1365 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1366 pins = "gpio60", "gpio61"; 1367 function = "blsp_i2c11"; 1368 drive-strength = <2>; 1369 bias-pull-up; 1370 }; 1371 1372 blsp2_i2c6_default: blsp2-i2c6-default-state { 1373 pins = "gpio83", "gpio84"; 1374 function = "blsp_i2c12"; 1375 drive-strength = <2>; 1376 bias-disable; 1377 }; 1378 1379 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1380 pins = "gpio83", "gpio84"; 1381 function = "blsp_i2c12"; 1382 drive-strength = <2>; 1383 bias-pull-up; 1384 }; 1385 1386 blsp2_spi1_default: blsp2-spi1-default-state { 1387 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1388 function = "blsp_spi7"; 1389 drive-strength = <6>; 1390 bias-disable; 1391 }; 1392 1393 blsp2_spi2_default: blsp2-spi2-default-state { 1394 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 1395 function = "blsp_spi8"; 1396 drive-strength = <6>; 1397 bias-disable; 1398 }; 1399 1400 blsp2_spi3_default: blsp2-spi3-default-state { 1401 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1402 function = "blsp_spi9"; 1403 drive-strength = <6>; 1404 bias-disable; 1405 }; 1406 1407 blsp2_spi4_default: blsp2-spi4-default-state { 1408 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 1409 function = "blsp_spi10"; 1410 drive-strength = <6>; 1411 bias-disable; 1412 }; 1413 1414 blsp2_spi5_default: blsp2-spi5-default-state { 1415 pins = "gpio58", "gpio59", "gpio60", "gpio61"; 1416 function = "blsp_spi11"; 1417 drive-strength = <6>; 1418 bias-disable; 1419 }; 1420 1421 blsp2_spi6_default: blsp2-spi6-default-state { 1422 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 1423 function = "blsp_spi12"; 1424 drive-strength = <6>; 1425 bias-disable; 1426 }; 1427 }; 1428 1429 remoteproc_mss: remoteproc@4080000 { 1430 compatible = "qcom,msm8998-mss-pil"; 1431 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1432 reg-names = "qdsp6", "rmb"; 1433 1434 interrupts-extended = 1435 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1436 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1437 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1438 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1439 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1440 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1441 interrupt-names = "wdog", "fatal", "ready", 1442 "handover", "stop-ack", 1443 "shutdown-ack"; 1444 1445 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1446 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1447 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1448 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1449 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1450 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1451 <&rpmcc RPM_SMD_QDSS_CLK>, 1452 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1453 clock-names = "iface", "bus", "mem", "gpll0_mss", 1454 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1455 1456 qcom,smem-states = <&modem_smp2p_out 0>; 1457 qcom,smem-state-names = "stop"; 1458 1459 resets = <&gcc GCC_MSS_RESTART>; 1460 reset-names = "mss_restart"; 1461 1462 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1463 1464 power-domains = <&rpmpd MSM8998_VDDCX>, 1465 <&rpmpd MSM8998_VDDMX>; 1466 power-domain-names = "cx", "mx"; 1467 1468 status = "disabled"; 1469 1470 mba { 1471 memory-region = <&mba_mem>; 1472 }; 1473 1474 mpss { 1475 memory-region = <&mpss_mem>; 1476 }; 1477 1478 metadata { 1479 memory-region = <&mdata_mem>; 1480 }; 1481 1482 glink-edge { 1483 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1484 label = "modem"; 1485 qcom,remote-pid = <1>; 1486 mboxes = <&apcs_glb 15>; 1487 }; 1488 }; 1489 1490 adreno_gpu: gpu@5000000 { 1491 compatible = "qcom,adreno-540.1", "qcom,adreno"; 1492 reg = <0x05000000 0x40000>; 1493 reg-names = "kgsl_3d0_reg_memory"; 1494 1495 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1496 <&gpucc RBBMTIMER_CLK>, 1497 <&gcc GCC_BIMC_GFX_CLK>, 1498 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1499 <&gpucc RBCPR_CLK>, 1500 <&gpucc GFX3D_CLK>; 1501 clock-names = "iface", 1502 "rbbmtimer", 1503 "mem", 1504 "mem_iface", 1505 "rbcpr", 1506 "core"; 1507 1508 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1509 iommus = <&adreno_smmu 0>; 1510 operating-points-v2 = <&gpu_opp_table>; 1511 power-domains = <&rpmpd MSM8998_VDDMX>; 1512 status = "disabled"; 1513 1514 gpu_opp_table: opp-table { 1515 compatible = "operating-points-v2"; 1516 opp-710000097 { 1517 opp-hz = /bits/ 64 <710000097>; 1518 opp-level = <RPM_SMD_LEVEL_TURBO>; 1519 opp-supported-hw = <0xff>; 1520 }; 1521 1522 opp-670000048 { 1523 opp-hz = /bits/ 64 <670000048>; 1524 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1525 opp-supported-hw = <0xff>; 1526 }; 1527 1528 opp-596000097 { 1529 opp-hz = /bits/ 64 <596000097>; 1530 opp-level = <RPM_SMD_LEVEL_NOM>; 1531 opp-supported-hw = <0xff>; 1532 }; 1533 1534 opp-515000097 { 1535 opp-hz = /bits/ 64 <515000097>; 1536 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1537 opp-supported-hw = <0xff>; 1538 }; 1539 1540 opp-414000000 { 1541 opp-hz = /bits/ 64 <414000000>; 1542 opp-level = <RPM_SMD_LEVEL_SVS>; 1543 opp-supported-hw = <0xff>; 1544 }; 1545 1546 opp-342000000 { 1547 opp-hz = /bits/ 64 <342000000>; 1548 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1549 opp-supported-hw = <0xff>; 1550 }; 1551 1552 opp-257000000 { 1553 opp-hz = /bits/ 64 <257000000>; 1554 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1555 opp-supported-hw = <0xff>; 1556 }; 1557 }; 1558 }; 1559 1560 adreno_smmu: iommu@5040000 { 1561 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1562 reg = <0x05040000 0x10000>; 1563 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1564 <&gcc GCC_BIMC_GFX_CLK>, 1565 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1566 clock-names = "iface", "mem", "mem_iface"; 1567 1568 #global-interrupts = <0>; 1569 #iommu-cells = <1>; 1570 interrupts = 1571 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1574 /* 1575 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the 1576 * GPU-CX for SMMU but we need both of them up for Adreno. 1577 * Contemporarily, we also need to manage the VDDMX rpmpd 1578 * domain in the Adreno driver. 1579 * Enable GPU CX/GX GDSCs here so that we can manage the 1580 * SoC VDDMX RPM Power Domain in the Adreno driver. 1581 */ 1582 power-domains = <&gpucc GPU_GX_GDSC>; 1583 status = "disabled"; 1584 }; 1585 1586 gpucc: clock-controller@5065000 { 1587 compatible = "qcom,msm8998-gpucc"; 1588 #clock-cells = <1>; 1589 #reset-cells = <1>; 1590 #power-domain-cells = <1>; 1591 reg = <0x05065000 0x9000>; 1592 1593 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1594 <&gcc GCC_GPU_GPLL0_CLK>; 1595 clock-names = "xo", 1596 "gpll0"; 1597 }; 1598 1599 remoteproc_slpi: remoteproc@5800000 { 1600 compatible = "qcom,msm8998-slpi-pas"; 1601 reg = <0x05800000 0x4040>; 1602 1603 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1604 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1605 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1606 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1607 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1608 interrupt-names = "wdog", "fatal", "ready", 1609 "handover", "stop-ack"; 1610 1611 px-supply = <&vreg_lvs2a_1p8>; 1612 1613 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1614 clock-names = "xo"; 1615 1616 memory-region = <&slpi_mem>; 1617 1618 qcom,smem-states = <&slpi_smp2p_out 0>; 1619 qcom,smem-state-names = "stop"; 1620 1621 power-domains = <&rpmpd MSM8998_SSCCX>; 1622 power-domain-names = "ssc_cx"; 1623 1624 status = "disabled"; 1625 1626 glink-edge { 1627 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1628 label = "dsps"; 1629 qcom,remote-pid = <3>; 1630 mboxes = <&apcs_glb 27>; 1631 }; 1632 }; 1633 1634 stm: stm@6002000 { 1635 compatible = "arm,coresight-stm", "arm,primecell"; 1636 reg = <0x06002000 0x1000>, 1637 <0x16280000 0x180000>; 1638 reg-names = "stm-base", "stm-stimulus-base"; 1639 status = "disabled"; 1640 1641 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1642 clock-names = "apb_pclk", "atclk"; 1643 1644 out-ports { 1645 port { 1646 stm_out: endpoint { 1647 remote-endpoint = <&funnel0_in7>; 1648 }; 1649 }; 1650 }; 1651 }; 1652 1653 funnel1: funnel@6041000 { 1654 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1655 reg = <0x06041000 0x1000>; 1656 status = "disabled"; 1657 1658 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1659 clock-names = "apb_pclk", "atclk"; 1660 1661 out-ports { 1662 port { 1663 funnel0_out: endpoint { 1664 remote-endpoint = 1665 <&merge_funnel_in0>; 1666 }; 1667 }; 1668 }; 1669 1670 in-ports { 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 1674 port@7 { 1675 reg = <7>; 1676 funnel0_in7: endpoint { 1677 remote-endpoint = <&stm_out>; 1678 }; 1679 }; 1680 }; 1681 }; 1682 1683 funnel2: funnel@6042000 { 1684 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1685 reg = <0x06042000 0x1000>; 1686 status = "disabled"; 1687 1688 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1689 clock-names = "apb_pclk", "atclk"; 1690 1691 out-ports { 1692 port { 1693 funnel1_out: endpoint { 1694 remote-endpoint = 1695 <&merge_funnel_in1>; 1696 }; 1697 }; 1698 }; 1699 1700 in-ports { 1701 #address-cells = <1>; 1702 #size-cells = <0>; 1703 1704 port@6 { 1705 reg = <6>; 1706 funnel1_in6: endpoint { 1707 remote-endpoint = 1708 <&apss_merge_funnel_out>; 1709 }; 1710 }; 1711 }; 1712 }; 1713 1714 funnel3: funnel@6045000 { 1715 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1716 reg = <0x06045000 0x1000>; 1717 status = "disabled"; 1718 1719 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1720 clock-names = "apb_pclk", "atclk"; 1721 1722 out-ports { 1723 port { 1724 merge_funnel_out: endpoint { 1725 remote-endpoint = 1726 <&etf_in>; 1727 }; 1728 }; 1729 }; 1730 1731 in-ports { 1732 #address-cells = <1>; 1733 #size-cells = <0>; 1734 1735 port@0 { 1736 reg = <0>; 1737 merge_funnel_in0: endpoint { 1738 remote-endpoint = 1739 <&funnel0_out>; 1740 }; 1741 }; 1742 1743 port@1 { 1744 reg = <1>; 1745 merge_funnel_in1: endpoint { 1746 remote-endpoint = 1747 <&funnel1_out>; 1748 }; 1749 }; 1750 }; 1751 }; 1752 1753 replicator1: replicator@6046000 { 1754 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1755 reg = <0x06046000 0x1000>; 1756 status = "disabled"; 1757 1758 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1759 clock-names = "apb_pclk", "atclk"; 1760 1761 out-ports { 1762 port { 1763 replicator_out: endpoint { 1764 remote-endpoint = <&etr_in>; 1765 }; 1766 }; 1767 }; 1768 1769 in-ports { 1770 port { 1771 replicator_in: endpoint { 1772 remote-endpoint = <&etf_out>; 1773 }; 1774 }; 1775 }; 1776 }; 1777 1778 etf: etf@6047000 { 1779 compatible = "arm,coresight-tmc", "arm,primecell"; 1780 reg = <0x06047000 0x1000>; 1781 status = "disabled"; 1782 1783 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1784 clock-names = "apb_pclk", "atclk"; 1785 1786 out-ports { 1787 port { 1788 etf_out: endpoint { 1789 remote-endpoint = 1790 <&replicator_in>; 1791 }; 1792 }; 1793 }; 1794 1795 in-ports { 1796 port { 1797 etf_in: endpoint { 1798 remote-endpoint = 1799 <&merge_funnel_out>; 1800 }; 1801 }; 1802 }; 1803 }; 1804 1805 etr: etr@6048000 { 1806 compatible = "arm,coresight-tmc", "arm,primecell"; 1807 reg = <0x06048000 0x1000>; 1808 status = "disabled"; 1809 1810 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1811 clock-names = "apb_pclk", "atclk"; 1812 arm,scatter-gather; 1813 1814 in-ports { 1815 port { 1816 etr_in: endpoint { 1817 remote-endpoint = 1818 <&replicator_out>; 1819 }; 1820 }; 1821 }; 1822 }; 1823 1824 etm1: etm@7840000 { 1825 compatible = "arm,coresight-etm4x", "arm,primecell"; 1826 reg = <0x07840000 0x1000>; 1827 status = "disabled"; 1828 1829 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1830 clock-names = "apb_pclk", "atclk"; 1831 1832 cpu = <&CPU0>; 1833 1834 out-ports { 1835 port { 1836 etm0_out: endpoint { 1837 remote-endpoint = 1838 <&apss_funnel_in0>; 1839 }; 1840 }; 1841 }; 1842 }; 1843 1844 etm2: etm@7940000 { 1845 compatible = "arm,coresight-etm4x", "arm,primecell"; 1846 reg = <0x07940000 0x1000>; 1847 status = "disabled"; 1848 1849 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1850 clock-names = "apb_pclk", "atclk"; 1851 1852 cpu = <&CPU1>; 1853 1854 out-ports { 1855 port { 1856 etm1_out: endpoint { 1857 remote-endpoint = 1858 <&apss_funnel_in1>; 1859 }; 1860 }; 1861 }; 1862 }; 1863 1864 etm3: etm@7a40000 { 1865 compatible = "arm,coresight-etm4x", "arm,primecell"; 1866 reg = <0x07a40000 0x1000>; 1867 status = "disabled"; 1868 1869 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1870 clock-names = "apb_pclk", "atclk"; 1871 1872 cpu = <&CPU2>; 1873 1874 out-ports { 1875 port { 1876 etm2_out: endpoint { 1877 remote-endpoint = 1878 <&apss_funnel_in2>; 1879 }; 1880 }; 1881 }; 1882 }; 1883 1884 etm4: etm@7b40000 { 1885 compatible = "arm,coresight-etm4x", "arm,primecell"; 1886 reg = <0x07b40000 0x1000>; 1887 status = "disabled"; 1888 1889 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1890 clock-names = "apb_pclk", "atclk"; 1891 1892 cpu = <&CPU3>; 1893 1894 out-ports { 1895 port { 1896 etm3_out: endpoint { 1897 remote-endpoint = 1898 <&apss_funnel_in3>; 1899 }; 1900 }; 1901 }; 1902 }; 1903 1904 funnel4: funnel@7b60000 { /* APSS Funnel */ 1905 compatible = "arm,coresight-etm4x", "arm,primecell"; 1906 reg = <0x07b60000 0x1000>; 1907 status = "disabled"; 1908 1909 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1910 clock-names = "apb_pclk", "atclk"; 1911 1912 out-ports { 1913 port { 1914 apss_funnel_out: endpoint { 1915 remote-endpoint = 1916 <&apss_merge_funnel_in>; 1917 }; 1918 }; 1919 }; 1920 1921 in-ports { 1922 #address-cells = <1>; 1923 #size-cells = <0>; 1924 1925 port@0 { 1926 reg = <0>; 1927 apss_funnel_in0: endpoint { 1928 remote-endpoint = 1929 <&etm0_out>; 1930 }; 1931 }; 1932 1933 port@1 { 1934 reg = <1>; 1935 apss_funnel_in1: endpoint { 1936 remote-endpoint = 1937 <&etm1_out>; 1938 }; 1939 }; 1940 1941 port@2 { 1942 reg = <2>; 1943 apss_funnel_in2: endpoint { 1944 remote-endpoint = 1945 <&etm2_out>; 1946 }; 1947 }; 1948 1949 port@3 { 1950 reg = <3>; 1951 apss_funnel_in3: endpoint { 1952 remote-endpoint = 1953 <&etm3_out>; 1954 }; 1955 }; 1956 1957 port@4 { 1958 reg = <4>; 1959 apss_funnel_in4: endpoint { 1960 remote-endpoint = 1961 <&etm4_out>; 1962 }; 1963 }; 1964 1965 port@5 { 1966 reg = <5>; 1967 apss_funnel_in5: endpoint { 1968 remote-endpoint = 1969 <&etm5_out>; 1970 }; 1971 }; 1972 1973 port@6 { 1974 reg = <6>; 1975 apss_funnel_in6: endpoint { 1976 remote-endpoint = 1977 <&etm6_out>; 1978 }; 1979 }; 1980 1981 port@7 { 1982 reg = <7>; 1983 apss_funnel_in7: endpoint { 1984 remote-endpoint = 1985 <&etm7_out>; 1986 }; 1987 }; 1988 }; 1989 }; 1990 1991 funnel5: funnel@7b70000 { 1992 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1993 reg = <0x07b70000 0x1000>; 1994 status = "disabled"; 1995 1996 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1997 clock-names = "apb_pclk", "atclk"; 1998 1999 out-ports { 2000 port { 2001 apss_merge_funnel_out: endpoint { 2002 remote-endpoint = 2003 <&funnel1_in6>; 2004 }; 2005 }; 2006 }; 2007 2008 in-ports { 2009 port { 2010 apss_merge_funnel_in: endpoint { 2011 remote-endpoint = 2012 <&apss_funnel_out>; 2013 }; 2014 }; 2015 }; 2016 }; 2017 2018 etm5: etm@7c40000 { 2019 compatible = "arm,coresight-etm4x", "arm,primecell"; 2020 reg = <0x07c40000 0x1000>; 2021 status = "disabled"; 2022 2023 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2024 clock-names = "apb_pclk", "atclk"; 2025 2026 cpu = <&CPU4>; 2027 2028 out-ports { 2029 port { 2030 etm4_out: endpoint { 2031 remote-endpoint = <&apss_funnel_in4>; 2032 }; 2033 }; 2034 }; 2035 }; 2036 2037 etm6: etm@7d40000 { 2038 compatible = "arm,coresight-etm4x", "arm,primecell"; 2039 reg = <0x07d40000 0x1000>; 2040 status = "disabled"; 2041 2042 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2043 clock-names = "apb_pclk", "atclk"; 2044 2045 cpu = <&CPU5>; 2046 2047 out-ports { 2048 port { 2049 etm5_out: endpoint { 2050 remote-endpoint = <&apss_funnel_in5>; 2051 }; 2052 }; 2053 }; 2054 }; 2055 2056 etm7: etm@7e40000 { 2057 compatible = "arm,coresight-etm4x", "arm,primecell"; 2058 reg = <0x07e40000 0x1000>; 2059 status = "disabled"; 2060 2061 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2062 clock-names = "apb_pclk", "atclk"; 2063 2064 cpu = <&CPU6>; 2065 2066 out-ports { 2067 port { 2068 etm6_out: endpoint { 2069 remote-endpoint = <&apss_funnel_in6>; 2070 }; 2071 }; 2072 }; 2073 }; 2074 2075 etm8: etm@7f40000 { 2076 compatible = "arm,coresight-etm4x", "arm,primecell"; 2077 reg = <0x07f40000 0x1000>; 2078 status = "disabled"; 2079 2080 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2081 clock-names = "apb_pclk", "atclk"; 2082 2083 cpu = <&CPU7>; 2084 2085 out-ports { 2086 port { 2087 etm7_out: endpoint { 2088 remote-endpoint = <&apss_funnel_in7>; 2089 }; 2090 }; 2091 }; 2092 }; 2093 2094 sram@290000 { 2095 compatible = "qcom,rpm-stats"; 2096 reg = <0x00290000 0x10000>; 2097 }; 2098 2099 spmi_bus: spmi@800f000 { 2100 compatible = "qcom,spmi-pmic-arb"; 2101 reg = <0x0800f000 0x1000>, 2102 <0x08400000 0x1000000>, 2103 <0x09400000 0x1000000>, 2104 <0x0a400000 0x220000>, 2105 <0x0800a000 0x3000>; 2106 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2107 interrupt-names = "periph_irq"; 2108 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 2109 qcom,ee = <0>; 2110 qcom,channel = <0>; 2111 #address-cells = <2>; 2112 #size-cells = <0>; 2113 interrupt-controller; 2114 #interrupt-cells = <4>; 2115 }; 2116 2117 usb3: usb@a8f8800 { 2118 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 2119 reg = <0x0a8f8800 0x400>; 2120 status = "disabled"; 2121 #address-cells = <1>; 2122 #size-cells = <1>; 2123 ranges; 2124 2125 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 2126 <&gcc GCC_USB30_MASTER_CLK>, 2127 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 2128 <&gcc GCC_USB30_SLEEP_CLK>, 2129 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2130 clock-names = "cfg_noc", 2131 "core", 2132 "iface", 2133 "sleep", 2134 "mock_utmi"; 2135 2136 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2137 <&gcc GCC_USB30_MASTER_CLK>; 2138 assigned-clock-rates = <19200000>, <120000000>; 2139 2140 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2143 interrupt-names = "pwr_event", 2144 "qusb2_phy", 2145 "ss_phy_irq"; 2146 2147 power-domains = <&gcc USB_30_GDSC>; 2148 2149 resets = <&gcc GCC_USB_30_BCR>; 2150 2151 usb3_dwc3: usb@a800000 { 2152 compatible = "snps,dwc3"; 2153 reg = <0x0a800000 0xcd00>; 2154 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2155 snps,dis_u2_susphy_quirk; 2156 snps,dis_enblslpm_quirk; 2157 phys = <&qusb2phy>, <&usb3phy>; 2158 phy-names = "usb2-phy", "usb3-phy"; 2159 snps,has-lpm-erratum; 2160 snps,hird-threshold = /bits/ 8 <0x10>; 2161 }; 2162 }; 2163 2164 usb3phy: phy@c010000 { 2165 compatible = "qcom,msm8998-qmp-usb3-phy"; 2166 reg = <0x0c010000 0x1000>; 2167 2168 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2169 <&gcc GCC_USB3_CLKREF_CLK>, 2170 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2171 <&gcc GCC_USB3_PHY_PIPE_CLK>; 2172 clock-names = "aux", 2173 "ref", 2174 "cfg_ahb", 2175 "pipe"; 2176 clock-output-names = "usb3_phy_pipe_clk_src"; 2177 #clock-cells = <0>; 2178 #phy-cells = <0>; 2179 2180 resets = <&gcc GCC_USB3_PHY_BCR>, 2181 <&gcc GCC_USB3PHY_PHY_BCR>; 2182 reset-names = "phy", 2183 "phy_phy"; 2184 2185 qcom,tcsr-reg = <&tcsr_regs_2 0xb244>; 2186 2187 status = "disabled"; 2188 }; 2189 2190 qusb2phy: phy@c012000 { 2191 compatible = "qcom,msm8998-qusb2-phy"; 2192 reg = <0x0c012000 0x2a8>; 2193 status = "disabled"; 2194 #phy-cells = <0>; 2195 2196 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2197 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2198 clock-names = "cfg_ahb", "ref"; 2199 2200 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2201 2202 nvmem-cells = <&qusb2_hstx_trim>; 2203 }; 2204 2205 sdhc2: mmc@c0a4900 { 2206 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; 2207 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 2208 reg-names = "hc", "core"; 2209 2210 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2211 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2212 interrupt-names = "hc_irq", "pwr_irq"; 2213 2214 clock-names = "iface", "core", "xo"; 2215 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2216 <&gcc GCC_SDCC2_APPS_CLK>, 2217 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2218 bus-width = <4>; 2219 status = "disabled"; 2220 }; 2221 2222 blsp1_dma: dma-controller@c144000 { 2223 compatible = "qcom,bam-v1.7.0"; 2224 reg = <0x0c144000 0x25000>; 2225 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2226 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2227 clock-names = "bam_clk"; 2228 #dma-cells = <1>; 2229 qcom,ee = <0>; 2230 qcom,controlled-remotely; 2231 num-channels = <18>; 2232 qcom,num-ees = <4>; 2233 }; 2234 2235 blsp1_uart3: serial@c171000 { 2236 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2237 reg = <0x0c171000 0x1000>; 2238 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 2239 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 2240 <&gcc GCC_BLSP1_AHB_CLK>; 2241 clock-names = "core", "iface"; 2242 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 2243 dma-names = "tx", "rx"; 2244 pinctrl-names = "default"; 2245 pinctrl-0 = <&blsp1_uart3_on>; 2246 status = "disabled"; 2247 }; 2248 2249 blsp1_i2c1: i2c@c175000 { 2250 compatible = "qcom,i2c-qup-v2.2.1"; 2251 reg = <0x0c175000 0x600>; 2252 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2253 2254 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2255 <&gcc GCC_BLSP1_AHB_CLK>; 2256 clock-names = "core", "iface"; 2257 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2258 dma-names = "tx", "rx"; 2259 pinctrl-names = "default", "sleep"; 2260 pinctrl-0 = <&blsp1_i2c1_default>; 2261 pinctrl-1 = <&blsp1_i2c1_sleep>; 2262 clock-frequency = <400000>; 2263 2264 status = "disabled"; 2265 #address-cells = <1>; 2266 #size-cells = <0>; 2267 }; 2268 2269 blsp1_i2c2: i2c@c176000 { 2270 compatible = "qcom,i2c-qup-v2.2.1"; 2271 reg = <0x0c176000 0x600>; 2272 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2273 2274 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2275 <&gcc GCC_BLSP1_AHB_CLK>; 2276 clock-names = "core", "iface"; 2277 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2278 dma-names = "tx", "rx"; 2279 pinctrl-names = "default", "sleep"; 2280 pinctrl-0 = <&blsp1_i2c2_default>; 2281 pinctrl-1 = <&blsp1_i2c2_sleep>; 2282 clock-frequency = <400000>; 2283 2284 status = "disabled"; 2285 #address-cells = <1>; 2286 #size-cells = <0>; 2287 }; 2288 2289 blsp1_i2c3: i2c@c177000 { 2290 compatible = "qcom,i2c-qup-v2.2.1"; 2291 reg = <0x0c177000 0x600>; 2292 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2293 2294 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2295 <&gcc GCC_BLSP1_AHB_CLK>; 2296 clock-names = "core", "iface"; 2297 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2298 dma-names = "tx", "rx"; 2299 pinctrl-names = "default", "sleep"; 2300 pinctrl-0 = <&blsp1_i2c3_default>; 2301 pinctrl-1 = <&blsp1_i2c3_sleep>; 2302 clock-frequency = <400000>; 2303 2304 status = "disabled"; 2305 #address-cells = <1>; 2306 #size-cells = <0>; 2307 }; 2308 2309 blsp1_i2c4: i2c@c178000 { 2310 compatible = "qcom,i2c-qup-v2.2.1"; 2311 reg = <0x0c178000 0x600>; 2312 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2313 2314 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2315 <&gcc GCC_BLSP1_AHB_CLK>; 2316 clock-names = "core", "iface"; 2317 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2318 dma-names = "tx", "rx"; 2319 pinctrl-names = "default", "sleep"; 2320 pinctrl-0 = <&blsp1_i2c4_default>; 2321 pinctrl-1 = <&blsp1_i2c4_sleep>; 2322 clock-frequency = <400000>; 2323 2324 status = "disabled"; 2325 #address-cells = <1>; 2326 #size-cells = <0>; 2327 }; 2328 2329 blsp1_i2c5: i2c@c179000 { 2330 compatible = "qcom,i2c-qup-v2.2.1"; 2331 reg = <0x0c179000 0x600>; 2332 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2333 2334 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2335 <&gcc GCC_BLSP1_AHB_CLK>; 2336 clock-names = "core", "iface"; 2337 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2338 dma-names = "tx", "rx"; 2339 pinctrl-names = "default", "sleep"; 2340 pinctrl-0 = <&blsp1_i2c5_default>; 2341 pinctrl-1 = <&blsp1_i2c5_sleep>; 2342 clock-frequency = <400000>; 2343 2344 status = "disabled"; 2345 #address-cells = <1>; 2346 #size-cells = <0>; 2347 }; 2348 2349 blsp1_i2c6: i2c@c17a000 { 2350 compatible = "qcom,i2c-qup-v2.2.1"; 2351 reg = <0x0c17a000 0x600>; 2352 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2353 2354 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2355 <&gcc GCC_BLSP1_AHB_CLK>; 2356 clock-names = "core", "iface"; 2357 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2358 dma-names = "tx", "rx"; 2359 pinctrl-names = "default", "sleep"; 2360 pinctrl-0 = <&blsp1_i2c6_default>; 2361 pinctrl-1 = <&blsp1_i2c6_sleep>; 2362 clock-frequency = <400000>; 2363 2364 status = "disabled"; 2365 #address-cells = <1>; 2366 #size-cells = <0>; 2367 }; 2368 2369 blsp1_spi1: spi@c175000 { 2370 compatible = "qcom,spi-qup-v2.2.1"; 2371 reg = <0x0c175000 0x600>; 2372 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2373 2374 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2375 <&gcc GCC_BLSP1_AHB_CLK>; 2376 clock-names = "core", "iface"; 2377 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2378 dma-names = "tx", "rx"; 2379 pinctrl-names = "default"; 2380 pinctrl-0 = <&blsp1_spi1_default>; 2381 2382 status = "disabled"; 2383 #address-cells = <1>; 2384 #size-cells = <0>; 2385 }; 2386 2387 blsp1_spi2: spi@c176000 { 2388 compatible = "qcom,spi-qup-v2.2.1"; 2389 reg = <0x0c176000 0x600>; 2390 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2391 2392 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 2393 <&gcc GCC_BLSP1_AHB_CLK>; 2394 clock-names = "core", "iface"; 2395 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2396 dma-names = "tx", "rx"; 2397 pinctrl-names = "default"; 2398 pinctrl-0 = <&blsp1_spi2_default>; 2399 2400 status = "disabled"; 2401 #address-cells = <1>; 2402 #size-cells = <0>; 2403 }; 2404 2405 blsp1_spi3: spi@c177000 { 2406 compatible = "qcom,spi-qup-v2.2.1"; 2407 reg = <0x0c177000 0x600>; 2408 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2409 2410 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 2411 <&gcc GCC_BLSP1_AHB_CLK>; 2412 clock-names = "core", "iface"; 2413 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2414 dma-names = "tx", "rx"; 2415 pinctrl-names = "default"; 2416 pinctrl-0 = <&blsp1_spi3_default>; 2417 2418 status = "disabled"; 2419 #address-cells = <1>; 2420 #size-cells = <0>; 2421 }; 2422 2423 blsp1_spi4: spi@c178000 { 2424 compatible = "qcom,spi-qup-v2.2.1"; 2425 reg = <0x0c178000 0x600>; 2426 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2427 2428 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 2429 <&gcc GCC_BLSP1_AHB_CLK>; 2430 clock-names = "core", "iface"; 2431 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2432 dma-names = "tx", "rx"; 2433 pinctrl-names = "default"; 2434 pinctrl-0 = <&blsp1_spi4_default>; 2435 2436 status = "disabled"; 2437 #address-cells = <1>; 2438 #size-cells = <0>; 2439 }; 2440 2441 blsp1_spi5: spi@c179000 { 2442 compatible = "qcom,spi-qup-v2.2.1"; 2443 reg = <0x0c179000 0x600>; 2444 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2445 2446 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 2447 <&gcc GCC_BLSP1_AHB_CLK>; 2448 clock-names = "core", "iface"; 2449 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2450 dma-names = "tx", "rx"; 2451 pinctrl-names = "default"; 2452 pinctrl-0 = <&blsp1_spi5_default>; 2453 2454 status = "disabled"; 2455 #address-cells = <1>; 2456 #size-cells = <0>; 2457 }; 2458 2459 blsp1_spi6: spi@c17a000 { 2460 compatible = "qcom,spi-qup-v2.2.1"; 2461 reg = <0x0c17a000 0x600>; 2462 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2463 2464 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 2465 <&gcc GCC_BLSP1_AHB_CLK>; 2466 clock-names = "core", "iface"; 2467 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2468 dma-names = "tx", "rx"; 2469 pinctrl-names = "default"; 2470 pinctrl-0 = <&blsp1_spi6_default>; 2471 2472 status = "disabled"; 2473 #address-cells = <1>; 2474 #size-cells = <0>; 2475 }; 2476 2477 blsp2_dma: dma-controller@c184000 { 2478 compatible = "qcom,bam-v1.7.0"; 2479 reg = <0x0c184000 0x25000>; 2480 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2481 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2482 clock-names = "bam_clk"; 2483 #dma-cells = <1>; 2484 qcom,ee = <0>; 2485 qcom,controlled-remotely; 2486 num-channels = <18>; 2487 qcom,num-ees = <4>; 2488 }; 2489 2490 blsp2_uart1: serial@c1b0000 { 2491 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2492 reg = <0x0c1b0000 0x1000>; 2493 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2494 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2495 <&gcc GCC_BLSP2_AHB_CLK>; 2496 clock-names = "core", "iface"; 2497 status = "disabled"; 2498 }; 2499 2500 blsp2_i2c1: i2c@c1b5000 { 2501 compatible = "qcom,i2c-qup-v2.2.1"; 2502 reg = <0x0c1b5000 0x600>; 2503 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2504 2505 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2506 <&gcc GCC_BLSP2_AHB_CLK>; 2507 clock-names = "core", "iface"; 2508 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2509 dma-names = "tx", "rx"; 2510 pinctrl-names = "default", "sleep"; 2511 pinctrl-0 = <&blsp2_i2c1_default>; 2512 pinctrl-1 = <&blsp2_i2c1_sleep>; 2513 clock-frequency = <400000>; 2514 2515 status = "disabled"; 2516 #address-cells = <1>; 2517 #size-cells = <0>; 2518 }; 2519 2520 blsp2_i2c2: i2c@c1b6000 { 2521 compatible = "qcom,i2c-qup-v2.2.1"; 2522 reg = <0x0c1b6000 0x600>; 2523 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2524 2525 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2526 <&gcc GCC_BLSP2_AHB_CLK>; 2527 clock-names = "core", "iface"; 2528 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2529 dma-names = "tx", "rx"; 2530 pinctrl-names = "default", "sleep"; 2531 pinctrl-0 = <&blsp2_i2c2_default>; 2532 pinctrl-1 = <&blsp2_i2c2_sleep>; 2533 clock-frequency = <400000>; 2534 2535 status = "disabled"; 2536 #address-cells = <1>; 2537 #size-cells = <0>; 2538 }; 2539 2540 blsp2_i2c3: i2c@c1b7000 { 2541 compatible = "qcom,i2c-qup-v2.2.1"; 2542 reg = <0x0c1b7000 0x600>; 2543 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2544 2545 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 2546 <&gcc GCC_BLSP2_AHB_CLK>; 2547 clock-names = "core", "iface"; 2548 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2549 dma-names = "tx", "rx"; 2550 pinctrl-names = "default", "sleep"; 2551 pinctrl-0 = <&blsp2_i2c3_default>; 2552 pinctrl-1 = <&blsp2_i2c3_sleep>; 2553 clock-frequency = <400000>; 2554 2555 status = "disabled"; 2556 #address-cells = <1>; 2557 #size-cells = <0>; 2558 }; 2559 2560 blsp2_i2c4: i2c@c1b8000 { 2561 compatible = "qcom,i2c-qup-v2.2.1"; 2562 reg = <0x0c1b8000 0x600>; 2563 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2564 2565 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 2566 <&gcc GCC_BLSP2_AHB_CLK>; 2567 clock-names = "core", "iface"; 2568 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2569 dma-names = "tx", "rx"; 2570 pinctrl-names = "default", "sleep"; 2571 pinctrl-0 = <&blsp2_i2c4_default>; 2572 pinctrl-1 = <&blsp2_i2c4_sleep>; 2573 clock-frequency = <400000>; 2574 2575 status = "disabled"; 2576 #address-cells = <1>; 2577 #size-cells = <0>; 2578 }; 2579 2580 blsp2_i2c5: i2c@c1b9000 { 2581 compatible = "qcom,i2c-qup-v2.2.1"; 2582 reg = <0x0c1b9000 0x600>; 2583 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2584 2585 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 2586 <&gcc GCC_BLSP2_AHB_CLK>; 2587 clock-names = "core", "iface"; 2588 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2589 dma-names = "tx", "rx"; 2590 pinctrl-names = "default", "sleep"; 2591 pinctrl-0 = <&blsp2_i2c5_default>; 2592 pinctrl-1 = <&blsp2_i2c5_sleep>; 2593 clock-frequency = <400000>; 2594 2595 status = "disabled"; 2596 #address-cells = <1>; 2597 #size-cells = <0>; 2598 }; 2599 2600 blsp2_i2c6: i2c@c1ba000 { 2601 compatible = "qcom,i2c-qup-v2.2.1"; 2602 reg = <0x0c1ba000 0x600>; 2603 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2604 2605 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 2606 <&gcc GCC_BLSP2_AHB_CLK>; 2607 clock-names = "core", "iface"; 2608 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2609 dma-names = "tx", "rx"; 2610 pinctrl-names = "default", "sleep"; 2611 pinctrl-0 = <&blsp2_i2c6_default>; 2612 pinctrl-1 = <&blsp2_i2c6_sleep>; 2613 clock-frequency = <400000>; 2614 2615 status = "disabled"; 2616 #address-cells = <1>; 2617 #size-cells = <0>; 2618 }; 2619 2620 blsp2_spi1: spi@c1b5000 { 2621 compatible = "qcom,spi-qup-v2.2.1"; 2622 reg = <0x0c1b5000 0x600>; 2623 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2624 2625 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, 2626 <&gcc GCC_BLSP2_AHB_CLK>; 2627 clock-names = "core", "iface"; 2628 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2629 dma-names = "tx", "rx"; 2630 pinctrl-names = "default"; 2631 pinctrl-0 = <&blsp2_spi1_default>; 2632 2633 status = "disabled"; 2634 #address-cells = <1>; 2635 #size-cells = <0>; 2636 }; 2637 2638 blsp2_spi2: spi@c1b6000 { 2639 compatible = "qcom,spi-qup-v2.2.1"; 2640 reg = <0x0c1b6000 0x600>; 2641 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2642 2643 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, 2644 <&gcc GCC_BLSP2_AHB_CLK>; 2645 clock-names = "core", "iface"; 2646 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2647 dma-names = "tx", "rx"; 2648 pinctrl-names = "default"; 2649 pinctrl-0 = <&blsp2_spi2_default>; 2650 2651 status = "disabled"; 2652 #address-cells = <1>; 2653 #size-cells = <0>; 2654 }; 2655 2656 blsp2_spi3: spi@c1b7000 { 2657 compatible = "qcom,spi-qup-v2.2.1"; 2658 reg = <0x0c1b7000 0x600>; 2659 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2660 2661 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, 2662 <&gcc GCC_BLSP2_AHB_CLK>; 2663 clock-names = "core", "iface"; 2664 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2665 dma-names = "tx", "rx"; 2666 pinctrl-names = "default"; 2667 pinctrl-0 = <&blsp2_spi3_default>; 2668 2669 status = "disabled"; 2670 #address-cells = <1>; 2671 #size-cells = <0>; 2672 }; 2673 2674 blsp2_spi4: spi@c1b8000 { 2675 compatible = "qcom,spi-qup-v2.2.1"; 2676 reg = <0x0c1b8000 0x600>; 2677 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2678 2679 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, 2680 <&gcc GCC_BLSP2_AHB_CLK>; 2681 clock-names = "core", "iface"; 2682 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2683 dma-names = "tx", "rx"; 2684 pinctrl-names = "default"; 2685 pinctrl-0 = <&blsp2_spi4_default>; 2686 2687 status = "disabled"; 2688 #address-cells = <1>; 2689 #size-cells = <0>; 2690 }; 2691 2692 blsp2_spi5: spi@c1b9000 { 2693 compatible = "qcom,spi-qup-v2.2.1"; 2694 reg = <0x0c1b9000 0x600>; 2695 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2696 2697 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, 2698 <&gcc GCC_BLSP2_AHB_CLK>; 2699 clock-names = "core", "iface"; 2700 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2701 dma-names = "tx", "rx"; 2702 pinctrl-names = "default"; 2703 pinctrl-0 = <&blsp2_spi5_default>; 2704 2705 status = "disabled"; 2706 #address-cells = <1>; 2707 #size-cells = <0>; 2708 }; 2709 2710 blsp2_spi6: spi@c1ba000 { 2711 compatible = "qcom,spi-qup-v2.2.1"; 2712 reg = <0x0c1ba000 0x600>; 2713 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2714 2715 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 2716 <&gcc GCC_BLSP2_AHB_CLK>; 2717 clock-names = "core", "iface"; 2718 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2719 dma-names = "tx", "rx"; 2720 pinctrl-names = "default"; 2721 pinctrl-0 = <&blsp2_spi6_default>; 2722 2723 status = "disabled"; 2724 #address-cells = <1>; 2725 #size-cells = <0>; 2726 }; 2727 2728 mmcc: clock-controller@c8c0000 { 2729 compatible = "qcom,mmcc-msm8998"; 2730 #clock-cells = <1>; 2731 #reset-cells = <1>; 2732 #power-domain-cells = <1>; 2733 reg = <0xc8c0000 0x40000>; 2734 2735 clock-names = "xo", 2736 "gpll0", 2737 "dsi0dsi", 2738 "dsi0byte", 2739 "dsi1dsi", 2740 "dsi1byte", 2741 "hdmipll", 2742 "dplink", 2743 "dpvco", 2744 "gpll0_div"; 2745 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2746 <&gcc GCC_MMSS_GPLL0_CLK>, 2747 <&mdss_dsi0_phy 1>, 2748 <&mdss_dsi0_phy 0>, 2749 <&mdss_dsi1_phy 1>, 2750 <&mdss_dsi1_phy 0>, 2751 <0>, 2752 <0>, 2753 <0>, 2754 <&gcc GCC_MMSS_GPLL0_DIV_CLK>; 2755 }; 2756 2757 mdss: display-subsystem@c900000 { 2758 compatible = "qcom,msm8998-mdss"; 2759 reg = <0x0c900000 0x1000>; 2760 reg-names = "mdss"; 2761 2762 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2763 interrupt-controller; 2764 #interrupt-cells = <1>; 2765 2766 clocks = <&mmcc MDSS_AHB_CLK>, 2767 <&mmcc MDSS_AXI_CLK>, 2768 <&mmcc MDSS_MDP_CLK>; 2769 clock-names = "iface", 2770 "bus", 2771 "core"; 2772 2773 power-domains = <&mmcc MDSS_GDSC>; 2774 iommus = <&mmss_smmu 0>; 2775 2776 #address-cells = <1>; 2777 #size-cells = <1>; 2778 ranges; 2779 2780 status = "disabled"; 2781 2782 mdss_mdp: display-controller@c901000 { 2783 compatible = "qcom,msm8998-dpu"; 2784 reg = <0x0c901000 0x8f000>, 2785 <0x0c9a8e00 0xf0>, 2786 <0x0c9b0000 0x2008>, 2787 <0x0c9b8000 0x1040>; 2788 reg-names = "mdp", 2789 "regdma", 2790 "vbif", 2791 "vbif_nrt"; 2792 2793 interrupt-parent = <&mdss>; 2794 interrupts = <0>; 2795 2796 clocks = <&mmcc MDSS_AHB_CLK>, 2797 <&mmcc MDSS_AXI_CLK>, 2798 <&mmcc MNOC_AHB_CLK>, 2799 <&mmcc MDSS_MDP_CLK>, 2800 <&mmcc MDSS_VSYNC_CLK>; 2801 clock-names = "iface", 2802 "bus", 2803 "mnoc", 2804 "core", 2805 "vsync"; 2806 2807 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>; 2808 assigned-clock-rates = <19200000>; 2809 2810 operating-points-v2 = <&mdp_opp_table>; 2811 power-domains = <&rpmpd MSM8998_VDDMX>; 2812 2813 mdp_opp_table: opp-table { 2814 compatible = "operating-points-v2"; 2815 2816 opp-171430000 { 2817 opp-hz = /bits/ 64 <171430000>; 2818 required-opps = <&rpmpd_opp_low_svs>; 2819 }; 2820 2821 opp-275000000 { 2822 opp-hz = /bits/ 64 <275000000>; 2823 required-opps = <&rpmpd_opp_svs>; 2824 }; 2825 2826 opp-330000000 { 2827 opp-hz = /bits/ 64 <330000000>; 2828 required-opps = <&rpmpd_opp_nom>; 2829 }; 2830 2831 opp-412500000 { 2832 opp-hz = /bits/ 64 <412500000>; 2833 required-opps = <&rpmpd_opp_turbo>; 2834 }; 2835 }; 2836 2837 ports { 2838 #address-cells = <1>; 2839 #size-cells = <0>; 2840 2841 port@0 { 2842 reg = <0>; 2843 2844 dpu_intf1_out: endpoint { 2845 remote-endpoint = <&mdss_dsi0_in>; 2846 }; 2847 }; 2848 2849 port@1 { 2850 reg = <1>; 2851 2852 dpu_intf2_out: endpoint { 2853 remote-endpoint = <&mdss_dsi1_in>; 2854 }; 2855 }; 2856 }; 2857 }; 2858 2859 mdss_dsi0: dsi@c994000 { 2860 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2861 reg = <0x0c994000 0x400>; 2862 reg-names = "dsi_ctrl"; 2863 2864 interrupt-parent = <&mdss>; 2865 interrupts = <4>; 2866 2867 clocks = <&mmcc MDSS_BYTE0_CLK>, 2868 <&mmcc MDSS_BYTE0_INTF_CLK>, 2869 <&mmcc MDSS_PCLK0_CLK>, 2870 <&mmcc MDSS_ESC0_CLK>, 2871 <&mmcc MDSS_AHB_CLK>, 2872 <&mmcc MDSS_AXI_CLK>; 2873 clock-names = "byte", 2874 "byte_intf", 2875 "pixel", 2876 "core", 2877 "iface", 2878 "bus"; 2879 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 2880 <&mmcc PCLK0_CLK_SRC>; 2881 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2882 <&mdss_dsi0_phy 1>; 2883 2884 operating-points-v2 = <&dsi_opp_table>; 2885 power-domains = <&rpmpd MSM8998_VDDCX>; 2886 2887 phys = <&mdss_dsi0_phy>; 2888 phy-names = "dsi"; 2889 2890 #address-cells = <1>; 2891 #size-cells = <0>; 2892 2893 status = "disabled"; 2894 2895 ports { 2896 #address-cells = <1>; 2897 #size-cells = <0>; 2898 2899 port@0 { 2900 reg = <0>; 2901 2902 mdss_dsi0_in: endpoint { 2903 remote-endpoint = <&dpu_intf1_out>; 2904 }; 2905 }; 2906 2907 port@1 { 2908 reg = <1>; 2909 2910 mdss_dsi0_out: endpoint { 2911 }; 2912 }; 2913 }; 2914 }; 2915 2916 mdss_dsi0_phy: phy@c994400 { 2917 compatible = "qcom,dsi-phy-10nm-8998"; 2918 reg = <0x0c994400 0x200>, 2919 <0x0c994600 0x280>, 2920 <0x0c994a00 0x1e0>; 2921 reg-names = "dsi_phy", 2922 "dsi_phy_lane", 2923 "dsi_pll"; 2924 2925 clocks = <&mmcc MDSS_AHB_CLK>, 2926 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2927 clock-names = "iface", "ref"; 2928 2929 #clock-cells = <1>; 2930 #phy-cells = <0>; 2931 2932 status = "disabled"; 2933 }; 2934 2935 mdss_dsi1: dsi@c996000 { 2936 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2937 reg = <0x0c996000 0x400>; 2938 reg-names = "dsi_ctrl"; 2939 2940 interrupt-parent = <&mdss>; 2941 interrupts = <5>; 2942 2943 clocks = <&mmcc MDSS_BYTE1_CLK>, 2944 <&mmcc MDSS_BYTE1_INTF_CLK>, 2945 <&mmcc MDSS_PCLK1_CLK>, 2946 <&mmcc MDSS_ESC1_CLK>, 2947 <&mmcc MDSS_AHB_CLK>, 2948 <&mmcc MDSS_AXI_CLK>; 2949 clock-names = "byte", 2950 "byte_intf", 2951 "pixel", 2952 "core", 2953 "iface", 2954 "bus"; 2955 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, 2956 <&mmcc PCLK1_CLK_SRC>; 2957 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2958 <&mdss_dsi1_phy 1>; 2959 2960 operating-points-v2 = <&dsi_opp_table>; 2961 power-domains = <&rpmpd MSM8998_VDDCX>; 2962 2963 phys = <&mdss_dsi1_phy>; 2964 phy-names = "dsi"; 2965 2966 #address-cells = <1>; 2967 #size-cells = <0>; 2968 2969 status = "disabled"; 2970 2971 ports { 2972 #address-cells = <1>; 2973 #size-cells = <0>; 2974 2975 port@0 { 2976 reg = <0>; 2977 2978 mdss_dsi1_in: endpoint { 2979 remote-endpoint = <&dpu_intf2_out>; 2980 }; 2981 }; 2982 2983 port@1 { 2984 reg = <1>; 2985 2986 mdss_dsi1_out: endpoint { 2987 }; 2988 }; 2989 }; 2990 }; 2991 2992 mdss_dsi1_phy: phy@c996400 { 2993 compatible = "qcom,dsi-phy-10nm-8998"; 2994 reg = <0x0c996400 0x200>, 2995 <0x0c996600 0x280>, 2996 <0x0c996a00 0x10e>; 2997 reg-names = "dsi_phy", 2998 "dsi_phy_lane", 2999 "dsi_pll"; 3000 3001 clocks = <&mmcc MDSS_AHB_CLK>, 3002 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3003 clock-names = "iface", 3004 "ref"; 3005 3006 #clock-cells = <1>; 3007 #phy-cells = <0>; 3008 3009 status = "disabled"; 3010 }; 3011 }; 3012 3013 mmss_smmu: iommu@cd00000 { 3014 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 3015 reg = <0x0cd00000 0x40000>; 3016 #iommu-cells = <1>; 3017 3018 clocks = <&mmcc MNOC_AHB_CLK>, 3019 <&mmcc BIMC_SMMU_AHB_CLK>, 3020 <&mmcc BIMC_SMMU_AXI_CLK>; 3021 clock-names = "iface-mm", 3022 "iface-smmu", 3023 "bus-smmu"; 3024 3025 #global-interrupts = <0>; 3026 interrupts = 3027 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 3028 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 3029 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 3030 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 3031 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 3032 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 3033 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 3034 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 3035 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 3036 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 3037 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 3038 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 3039 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 3040 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 3041 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 3042 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 3043 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 3044 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3045 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 3046 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3047 3048 power-domains = <&mmcc BIMC_SMMU_GDSC>; 3049 }; 3050 3051 remoteproc_adsp: remoteproc@17300000 { 3052 compatible = "qcom,msm8998-adsp-pas"; 3053 reg = <0x17300000 0x4040>; 3054 3055 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3056 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3057 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3058 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3059 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3060 interrupt-names = "wdog", "fatal", "ready", 3061 "handover", "stop-ack"; 3062 3063 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3064 clock-names = "xo"; 3065 3066 memory-region = <&adsp_mem>; 3067 3068 qcom,smem-states = <&adsp_smp2p_out 0>; 3069 qcom,smem-state-names = "stop"; 3070 3071 power-domains = <&rpmpd MSM8998_VDDCX>; 3072 power-domain-names = "cx"; 3073 3074 status = "disabled"; 3075 3076 glink-edge { 3077 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 3078 label = "lpass"; 3079 qcom,remote-pid = <2>; 3080 mboxes = <&apcs_glb 9>; 3081 }; 3082 }; 3083 3084 apcs_glb: mailbox@17911000 { 3085 compatible = "qcom,msm8998-apcs-hmss-global", 3086 "qcom,msm8994-apcs-kpss-global"; 3087 reg = <0x17911000 0x1000>; 3088 3089 #mbox-cells = <1>; 3090 }; 3091 3092 timer@17920000 { 3093 #address-cells = <1>; 3094 #size-cells = <1>; 3095 ranges; 3096 compatible = "arm,armv7-timer-mem"; 3097 reg = <0x17920000 0x1000>; 3098 3099 frame@17921000 { 3100 frame-number = <0>; 3101 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 3103 reg = <0x17921000 0x1000>, 3104 <0x17922000 0x1000>; 3105 }; 3106 3107 frame@17923000 { 3108 frame-number = <1>; 3109 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3110 reg = <0x17923000 0x1000>; 3111 status = "disabled"; 3112 }; 3113 3114 frame@17924000 { 3115 frame-number = <2>; 3116 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3117 reg = <0x17924000 0x1000>; 3118 status = "disabled"; 3119 }; 3120 3121 frame@17925000 { 3122 frame-number = <3>; 3123 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3124 reg = <0x17925000 0x1000>; 3125 status = "disabled"; 3126 }; 3127 3128 frame@17926000 { 3129 frame-number = <4>; 3130 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3131 reg = <0x17926000 0x1000>; 3132 status = "disabled"; 3133 }; 3134 3135 frame@17927000 { 3136 frame-number = <5>; 3137 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3138 reg = <0x17927000 0x1000>; 3139 status = "disabled"; 3140 }; 3141 3142 frame@17928000 { 3143 frame-number = <6>; 3144 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3145 reg = <0x17928000 0x1000>; 3146 status = "disabled"; 3147 }; 3148 }; 3149 3150 intc: interrupt-controller@17a00000 { 3151 compatible = "arm,gic-v3"; 3152 reg = <0x17a00000 0x10000>, /* GICD */ 3153 <0x17b00000 0x100000>; /* GICR * 8 */ 3154 #interrupt-cells = <3>; 3155 #address-cells = <1>; 3156 #size-cells = <1>; 3157 ranges; 3158 interrupt-controller; 3159 #redistributor-regions = <1>; 3160 redistributor-stride = <0x0 0x20000>; 3161 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3162 }; 3163 3164 wifi: wifi@18800000 { 3165 compatible = "qcom,wcn3990-wifi"; 3166 status = "disabled"; 3167 reg = <0x18800000 0x800000>; 3168 reg-names = "membase"; 3169 memory-region = <&wlan_msa_mem>; 3170 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 3171 clock-names = "cxo_ref_clk_pin"; 3172 interrupts = 3173 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3185 iommus = <&anoc2_smmu 0x1900>, 3186 <&anoc2_smmu 0x1901>; 3187 qcom,snoc-host-cap-8bit-quirk; 3188 }; 3189 }; 3190}; 3191