xref: /linux/arch/arm64/boot/dts/qcom/msm8998.dtsi (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0) 
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8998.h>
6#include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/firmware/qcom,scm.h>
10#include <dt-bindings/power/qcom-rpmpd.h>
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14	interrupt-parent = <&intc>;
15
16	qcom,msm-id = <292 0x0>;
17
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	chosen { };
22
23	memory@80000000 {
24		device_type = "memory";
25		/* We expect the bootloader to fill in the reg */
26		reg = <0x0 0x80000000 0x0 0x0>;
27	};
28
29	reserved-memory {
30		#address-cells = <2>;
31		#size-cells = <2>;
32		ranges;
33
34		hyp_mem: memory@85800000 {
35			reg = <0x0 0x85800000 0x0 0x600000>;
36			no-map;
37		};
38
39		xbl_mem: memory@85e00000 {
40			reg = <0x0 0x85e00000 0x0 0x100000>;
41			no-map;
42		};
43
44		smem_mem: smem-mem@86000000 {
45			reg = <0x0 0x86000000 0x0 0x200000>;
46			no-map;
47		};
48
49		tz_mem: memory@86200000 {
50			reg = <0x0 0x86200000 0x0 0x2d00000>;
51			no-map;
52		};
53
54		rmtfs_mem: memory@88f00000 {
55			compatible = "qcom,rmtfs-mem";
56			reg = <0x0 0x88f00000 0x0 0x200000>;
57			no-map;
58
59			qcom,client-id = <1>;
60			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
61		};
62
63		spss_mem: memory@8ab00000 {
64			reg = <0x0 0x8ab00000 0x0 0x700000>;
65			no-map;
66		};
67
68		adsp_mem: memory@8b200000 {
69			reg = <0x0 0x8b200000 0x0 0x1a00000>;
70			no-map;
71		};
72
73		mpss_mem: memory@8cc00000 {
74			reg = <0x0 0x8cc00000 0x0 0x7000000>;
75			no-map;
76		};
77
78		venus_mem: memory@93c00000 {
79			reg = <0x0 0x93c00000 0x0 0x500000>;
80			no-map;
81		};
82
83		mba_mem: memory@94100000 {
84			reg = <0x0 0x94100000 0x0 0x200000>;
85			no-map;
86		};
87
88		slpi_mem: memory@94300000 {
89			reg = <0x0 0x94300000 0x0 0xf00000>;
90			no-map;
91		};
92
93		ipa_fw_mem: memory@95200000 {
94			reg = <0x0 0x95200000 0x0 0x10000>;
95			no-map;
96		};
97
98		ipa_gsi_mem: memory@95210000 {
99			reg = <0x0 0x95210000 0x0 0x5000>;
100			no-map;
101		};
102
103		gpu_mem: memory@95600000 {
104			reg = <0x0 0x95600000 0x0 0x100000>;
105			no-map;
106		};
107
108		wlan_msa_mem: memory@95700000 {
109			reg = <0x0 0x95700000 0x0 0x100000>;
110			no-map;
111		};
112
113		mdata_mem: mpss-metadata {
114			alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
115			size = <0x0 0x4000>;
116			no-map;
117		};
118	};
119
120	clocks {
121		xo: xo-board {
122			compatible = "fixed-clock";
123			#clock-cells = <0>;
124			clock-frequency = <19200000>;
125			clock-output-names = "xo_board";
126		};
127
128		sleep_clk: sleep-clk {
129			compatible = "fixed-clock";
130			#clock-cells = <0>;
131			clock-frequency = <32764>;
132		};
133	};
134
135	cpus {
136		#address-cells = <2>;
137		#size-cells = <0>;
138
139		CPU0: cpu@0 {
140			device_type = "cpu";
141			compatible = "qcom,kryo280";
142			reg = <0x0 0x0>;
143			enable-method = "psci";
144			capacity-dmips-mhz = <1024>;
145			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146			next-level-cache = <&L2_0>;
147			L2_0: l2-cache {
148				compatible = "cache";
149				cache-level = <2>;
150				cache-unified;
151			};
152		};
153
154		CPU1: cpu@1 {
155			device_type = "cpu";
156			compatible = "qcom,kryo280";
157			reg = <0x0 0x1>;
158			enable-method = "psci";
159			capacity-dmips-mhz = <1024>;
160			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161			next-level-cache = <&L2_0>;
162		};
163
164		CPU2: cpu@2 {
165			device_type = "cpu";
166			compatible = "qcom,kryo280";
167			reg = <0x0 0x2>;
168			enable-method = "psci";
169			capacity-dmips-mhz = <1024>;
170			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171			next-level-cache = <&L2_0>;
172		};
173
174		CPU3: cpu@3 {
175			device_type = "cpu";
176			compatible = "qcom,kryo280";
177			reg = <0x0 0x3>;
178			enable-method = "psci";
179			capacity-dmips-mhz = <1024>;
180			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181			next-level-cache = <&L2_0>;
182		};
183
184		CPU4: cpu@100 {
185			device_type = "cpu";
186			compatible = "qcom,kryo280";
187			reg = <0x0 0x100>;
188			enable-method = "psci";
189			capacity-dmips-mhz = <1536>;
190			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191			next-level-cache = <&L2_1>;
192			L2_1: l2-cache {
193				compatible = "cache";
194				cache-level = <2>;
195				cache-unified;
196			};
197		};
198
199		CPU5: cpu@101 {
200			device_type = "cpu";
201			compatible = "qcom,kryo280";
202			reg = <0x0 0x101>;
203			enable-method = "psci";
204			capacity-dmips-mhz = <1536>;
205			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206			next-level-cache = <&L2_1>;
207		};
208
209		CPU6: cpu@102 {
210			device_type = "cpu";
211			compatible = "qcom,kryo280";
212			reg = <0x0 0x102>;
213			enable-method = "psci";
214			capacity-dmips-mhz = <1536>;
215			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216			next-level-cache = <&L2_1>;
217		};
218
219		CPU7: cpu@103 {
220			device_type = "cpu";
221			compatible = "qcom,kryo280";
222			reg = <0x0 0x103>;
223			enable-method = "psci";
224			capacity-dmips-mhz = <1536>;
225			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226			next-level-cache = <&L2_1>;
227		};
228
229		cpu-map {
230			cluster0 {
231				core0 {
232					cpu = <&CPU0>;
233				};
234
235				core1 {
236					cpu = <&CPU1>;
237				};
238
239				core2 {
240					cpu = <&CPU2>;
241				};
242
243				core3 {
244					cpu = <&CPU3>;
245				};
246			};
247
248			cluster1 {
249				core0 {
250					cpu = <&CPU4>;
251				};
252
253				core1 {
254					cpu = <&CPU5>;
255				};
256
257				core2 {
258					cpu = <&CPU6>;
259				};
260
261				core3 {
262					cpu = <&CPU7>;
263				};
264			};
265		};
266
267		idle-states {
268			entry-method = "psci";
269
270			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271				compatible = "arm,idle-state";
272				idle-state-name = "little-retention";
273				/* CPU Retention (C2D), L2 Active */
274				arm,psci-suspend-param = <0x00000002>;
275				entry-latency-us = <81>;
276				exit-latency-us = <86>;
277				min-residency-us = <504>;
278			};
279
280			LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281				compatible = "arm,idle-state";
282				idle-state-name = "little-power-collapse";
283				/* CPU + L2 Power Collapse (C3, D4) */
284				arm,psci-suspend-param = <0x40000003>;
285				entry-latency-us = <814>;
286				exit-latency-us = <4562>;
287				min-residency-us = <9183>;
288				local-timer-stop;
289			};
290
291			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292				compatible = "arm,idle-state";
293				idle-state-name = "big-retention";
294				/* CPU Retention (C2D), L2 Active */
295				arm,psci-suspend-param = <0x00000002>;
296				entry-latency-us = <79>;
297				exit-latency-us = <82>;
298				min-residency-us = <1302>;
299			};
300
301			BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302				compatible = "arm,idle-state";
303				idle-state-name = "big-power-collapse";
304				/* CPU + L2 Power Collapse (C3, D4) */
305				arm,psci-suspend-param = <0x40000003>;
306				entry-latency-us = <724>;
307				exit-latency-us = <2027>;
308				min-residency-us = <9419>;
309				local-timer-stop;
310			};
311		};
312	};
313
314	firmware {
315		scm {
316			compatible = "qcom,scm-msm8998", "qcom,scm";
317		};
318	};
319
320	dsi_opp_table: opp-table-dsi {
321		compatible = "operating-points-v2";
322
323		opp-131250000 {
324			opp-hz = /bits/ 64 <131250000>;
325			required-opps = <&rpmpd_opp_low_svs>;
326		};
327
328		opp-210000000 {
329			opp-hz = /bits/ 64 <210000000>;
330			required-opps = <&rpmpd_opp_svs>;
331		};
332
333		opp-312500000 {
334			opp-hz = /bits/ 64 <312500000>;
335			required-opps = <&rpmpd_opp_nom>;
336		};
337	};
338
339	psci {
340		compatible = "arm,psci-1.0";
341		method = "smc";
342	};
343
344	rpm: remoteproc {
345		compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
346
347		glink-edge {
348			compatible = "qcom,glink-rpm";
349
350			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
351			qcom,rpm-msg-ram = <&rpm_msg_ram>;
352			mboxes = <&apcs_glb 0>;
353
354			rpm_requests: rpm-requests {
355				compatible = "qcom,rpm-msm8998", "qcom,glink-smd-rpm";
356				qcom,glink-channels = "rpm_requests";
357
358				rpmcc: clock-controller {
359					compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
360					clocks = <&xo>;
361					clock-names = "xo";
362					#clock-cells = <1>;
363				};
364
365				rpmpd: power-controller {
366					compatible = "qcom,msm8998-rpmpd";
367					#power-domain-cells = <1>;
368					operating-points-v2 = <&rpmpd_opp_table>;
369
370					rpmpd_opp_table: opp-table {
371						compatible = "operating-points-v2";
372
373						rpmpd_opp_ret: opp1 {
374							opp-level = <RPM_SMD_LEVEL_RETENTION>;
375						};
376
377						rpmpd_opp_ret_plus: opp2 {
378							opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
379						};
380
381						rpmpd_opp_min_svs: opp3 {
382							opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
383						};
384
385						rpmpd_opp_low_svs: opp4 {
386							opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
387						};
388
389						rpmpd_opp_svs: opp5 {
390							opp-level = <RPM_SMD_LEVEL_SVS>;
391						};
392
393						rpmpd_opp_svs_plus: opp6 {
394							opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
395						};
396
397						rpmpd_opp_nom: opp7 {
398							opp-level = <RPM_SMD_LEVEL_NOM>;
399						};
400
401						rpmpd_opp_nom_plus: opp8 {
402							opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
403						};
404
405						rpmpd_opp_turbo: opp9 {
406							opp-level = <RPM_SMD_LEVEL_TURBO>;
407						};
408
409						rpmpd_opp_turbo_plus: opp10 {
410							opp-level = <RPM_SMD_LEVEL_BINNING>;
411						};
412					};
413				};
414			};
415		};
416	};
417
418	smem {
419		compatible = "qcom,smem";
420		memory-region = <&smem_mem>;
421		hwlocks = <&tcsr_mutex 3>;
422	};
423
424	smp2p-lpass {
425		compatible = "qcom,smp2p";
426		qcom,smem = <443>, <429>;
427
428		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429
430		mboxes = <&apcs_glb 10>;
431
432		qcom,local-pid = <0>;
433		qcom,remote-pid = <2>;
434
435		adsp_smp2p_out: master-kernel {
436			qcom,entry-name = "master-kernel";
437			#qcom,smem-state-cells = <1>;
438		};
439
440		adsp_smp2p_in: slave-kernel {
441			qcom,entry-name = "slave-kernel";
442
443			interrupt-controller;
444			#interrupt-cells = <2>;
445		};
446	};
447
448	smp2p-mpss {
449		compatible = "qcom,smp2p";
450		qcom,smem = <435>, <428>;
451		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452		mboxes = <&apcs_glb 14>;
453		qcom,local-pid = <0>;
454		qcom,remote-pid = <1>;
455
456		modem_smp2p_out: master-kernel {
457			qcom,entry-name = "master-kernel";
458			#qcom,smem-state-cells = <1>;
459		};
460
461		modem_smp2p_in: slave-kernel {
462			qcom,entry-name = "slave-kernel";
463			interrupt-controller;
464			#interrupt-cells = <2>;
465		};
466	};
467
468	smp2p-slpi {
469		compatible = "qcom,smp2p";
470		qcom,smem = <481>, <430>;
471		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472		mboxes = <&apcs_glb 26>;
473		qcom,local-pid = <0>;
474		qcom,remote-pid = <3>;
475
476		slpi_smp2p_out: master-kernel {
477			qcom,entry-name = "master-kernel";
478			#qcom,smem-state-cells = <1>;
479		};
480
481		slpi_smp2p_in: slave-kernel {
482			qcom,entry-name = "slave-kernel";
483			interrupt-controller;
484			#interrupt-cells = <2>;
485		};
486	};
487
488	thermal-zones {
489		cpu0-thermal {
490			polling-delay-passive = <250>;
491
492			thermal-sensors = <&tsens0 1>;
493
494			trips {
495				cpu0_alert0: trip-point0 {
496					temperature = <75000>;
497					hysteresis = <2000>;
498					type = "passive";
499				};
500
501				cpu0_crit: cpu-crit {
502					temperature = <110000>;
503					hysteresis = <2000>;
504					type = "critical";
505				};
506			};
507		};
508
509		cpu1-thermal {
510			polling-delay-passive = <250>;
511
512			thermal-sensors = <&tsens0 2>;
513
514			trips {
515				cpu1_alert0: trip-point0 {
516					temperature = <75000>;
517					hysteresis = <2000>;
518					type = "passive";
519				};
520
521				cpu1_crit: cpu-crit {
522					temperature = <110000>;
523					hysteresis = <2000>;
524					type = "critical";
525				};
526			};
527		};
528
529		cpu2-thermal {
530			polling-delay-passive = <250>;
531
532			thermal-sensors = <&tsens0 3>;
533
534			trips {
535				cpu2_alert0: trip-point0 {
536					temperature = <75000>;
537					hysteresis = <2000>;
538					type = "passive";
539				};
540
541				cpu2_crit: cpu-crit {
542					temperature = <110000>;
543					hysteresis = <2000>;
544					type = "critical";
545				};
546			};
547		};
548
549		cpu3-thermal {
550			polling-delay-passive = <250>;
551
552			thermal-sensors = <&tsens0 4>;
553
554			trips {
555				cpu3_alert0: trip-point0 {
556					temperature = <75000>;
557					hysteresis = <2000>;
558					type = "passive";
559				};
560
561				cpu3_crit: cpu-crit {
562					temperature = <110000>;
563					hysteresis = <2000>;
564					type = "critical";
565				};
566			};
567		};
568
569		cpu4-thermal {
570			polling-delay-passive = <250>;
571
572			thermal-sensors = <&tsens0 7>;
573
574			trips {
575				cpu4_alert0: trip-point0 {
576					temperature = <75000>;
577					hysteresis = <2000>;
578					type = "passive";
579				};
580
581				cpu4_crit: cpu-crit {
582					temperature = <110000>;
583					hysteresis = <2000>;
584					type = "critical";
585				};
586			};
587		};
588
589		cpu5-thermal {
590			polling-delay-passive = <250>;
591
592			thermal-sensors = <&tsens0 8>;
593
594			trips {
595				cpu5_alert0: trip-point0 {
596					temperature = <75000>;
597					hysteresis = <2000>;
598					type = "passive";
599				};
600
601				cpu5_crit: cpu-crit {
602					temperature = <110000>;
603					hysteresis = <2000>;
604					type = "critical";
605				};
606			};
607		};
608
609		cpu6-thermal {
610			polling-delay-passive = <250>;
611
612			thermal-sensors = <&tsens0 9>;
613
614			trips {
615				cpu6_alert0: trip-point0 {
616					temperature = <75000>;
617					hysteresis = <2000>;
618					type = "passive";
619				};
620
621				cpu6_crit: cpu-crit {
622					temperature = <110000>;
623					hysteresis = <2000>;
624					type = "critical";
625				};
626			};
627		};
628
629		cpu7-thermal {
630			polling-delay-passive = <250>;
631
632			thermal-sensors = <&tsens0 10>;
633
634			trips {
635				cpu7_alert0: trip-point0 {
636					temperature = <75000>;
637					hysteresis = <2000>;
638					type = "passive";
639				};
640
641				cpu7_crit: cpu-crit {
642					temperature = <110000>;
643					hysteresis = <2000>;
644					type = "critical";
645				};
646			};
647		};
648
649		gpu-bottom-thermal {
650			polling-delay-passive = <250>;
651
652			thermal-sensors = <&tsens0 12>;
653
654			trips {
655				gpu1_alert0: trip-point0 {
656					temperature = <90000>;
657					hysteresis = <2000>;
658					type = "hot";
659				};
660			};
661		};
662
663		gpu-top-thermal {
664			polling-delay-passive = <250>;
665
666			thermal-sensors = <&tsens0 13>;
667
668			trips {
669				gpu2_alert0: trip-point0 {
670					temperature = <90000>;
671					hysteresis = <2000>;
672					type = "hot";
673				};
674			};
675		};
676
677		clust0-mhm-thermal {
678			polling-delay-passive = <250>;
679
680			thermal-sensors = <&tsens0 5>;
681
682			trips {
683				cluster0_mhm_alert0: trip-point0 {
684					temperature = <90000>;
685					hysteresis = <2000>;
686					type = "hot";
687				};
688			};
689		};
690
691		clust1-mhm-thermal {
692			polling-delay-passive = <250>;
693
694			thermal-sensors = <&tsens0 6>;
695
696			trips {
697				cluster1_mhm_alert0: trip-point0 {
698					temperature = <90000>;
699					hysteresis = <2000>;
700					type = "hot";
701				};
702			};
703		};
704
705		cluster1-l2-thermal {
706			polling-delay-passive = <250>;
707
708			thermal-sensors = <&tsens0 11>;
709
710			trips {
711				cluster1_l2_alert0: trip-point0 {
712					temperature = <90000>;
713					hysteresis = <2000>;
714					type = "hot";
715				};
716			};
717		};
718
719		modem-thermal {
720			polling-delay-passive = <250>;
721
722			thermal-sensors = <&tsens1 1>;
723
724			trips {
725				modem_alert0: trip-point0 {
726					temperature = <90000>;
727					hysteresis = <2000>;
728					type = "hot";
729				};
730			};
731		};
732
733		mem-thermal {
734			polling-delay-passive = <250>;
735
736			thermal-sensors = <&tsens1 2>;
737
738			trips {
739				mem_alert0: trip-point0 {
740					temperature = <90000>;
741					hysteresis = <2000>;
742					type = "hot";
743				};
744			};
745		};
746
747		wlan-thermal {
748			polling-delay-passive = <250>;
749
750			thermal-sensors = <&tsens1 3>;
751
752			trips {
753				wlan_alert0: trip-point0 {
754					temperature = <90000>;
755					hysteresis = <2000>;
756					type = "hot";
757				};
758			};
759		};
760
761		q6-dsp-thermal {
762			polling-delay-passive = <250>;
763
764			thermal-sensors = <&tsens1 4>;
765
766			trips {
767				q6_dsp_alert0: trip-point0 {
768					temperature = <90000>;
769					hysteresis = <2000>;
770					type = "hot";
771				};
772			};
773		};
774
775		camera-thermal {
776			polling-delay-passive = <250>;
777
778			thermal-sensors = <&tsens1 5>;
779
780			trips {
781				camera_alert0: trip-point0 {
782					temperature = <90000>;
783					hysteresis = <2000>;
784					type = "hot";
785				};
786			};
787		};
788
789		multimedia-thermal {
790			polling-delay-passive = <250>;
791
792			thermal-sensors = <&tsens1 6>;
793
794			trips {
795				multimedia_alert0: trip-point0 {
796					temperature = <90000>;
797					hysteresis = <2000>;
798					type = "hot";
799				};
800			};
801		};
802	};
803
804	timer {
805		compatible = "arm,armv8-timer";
806		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810	};
811
812	soc: soc@0 {
813		#address-cells = <1>;
814		#size-cells = <1>;
815		ranges = <0 0 0 0xffffffff>;
816		compatible = "simple-bus";
817
818		gcc: clock-controller@100000 {
819			compatible = "qcom,gcc-msm8998";
820			#clock-cells = <1>;
821			#reset-cells = <1>;
822			#power-domain-cells = <1>;
823			reg = <0x00100000 0xb0000>;
824
825			clock-names = "xo", "sleep_clk";
826			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
827
828			/*
829			 * The hypervisor typically configures the memory region where these clocks
830			 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
831			 * these clocks on a device with such configuration (e.g. because they are
832			 * enabled but unused during boot-up), the device will most likely decide
833			 * to reboot.
834			 * In light of that, we are conservative here and we list all such clocks
835			 * as protected. The board dts (or a user-supplied dts) can override the
836			 * list of protected clocks if it differs from the norm, and it is in fact
837			 * desired for the HLOS to manage these clocks
838			 */
839			protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
840					   <SSC_XO>,
841					   <SSC_CNOC_AHBS_CLK>;
842		};
843
844		rpm_msg_ram: sram@778000 {
845			compatible = "qcom,rpm-msg-ram";
846			reg = <0x00778000 0x7000>;
847		};
848
849		qfprom: qfprom@784000 {
850			compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
851			reg = <0x00784000 0x621c>;
852			#address-cells = <1>;
853			#size-cells = <1>;
854
855			qusb2_hstx_trim: hstx-trim@23a {
856				reg = <0x23a 0x1>;
857				bits = <0 4>;
858			};
859		};
860
861		tsens0: thermal@10ab000 {
862			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863			reg = <0x010ab000 0x1000>, /* TM */
864			      <0x010aa000 0x1000>; /* SROT */
865			#qcom,sensors = <14>;
866			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
867				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
868			interrupt-names = "uplow", "critical";
869			#thermal-sensor-cells = <1>;
870		};
871
872		tsens1: thermal@10ae000 {
873			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874			reg = <0x010ae000 0x1000>, /* TM */
875			      <0x010ad000 0x1000>; /* SROT */
876			#qcom,sensors = <8>;
877			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
878				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
879			interrupt-names = "uplow", "critical";
880			#thermal-sensor-cells = <1>;
881		};
882
883		anoc1_smmu: iommu@1680000 {
884			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885			reg = <0x01680000 0x10000>;
886			#iommu-cells = <1>;
887
888			#global-interrupts = <0>;
889			interrupts =
890				<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891				<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892				<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893				<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894				<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895				<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896		};
897
898		anoc2_smmu: iommu@16c0000 {
899			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
900			reg = <0x016c0000 0x40000>;
901			#iommu-cells = <1>;
902
903			#global-interrupts = <0>;
904			interrupts =
905				<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
906				<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
907				<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
908				<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
909				<GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
910				<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
911				<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
912				<GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
913				<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
914				<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
915		};
916
917		pcie0: pcie@1c00000 {
918			compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
919			reg = <0x01c00000 0x2000>,
920			      <0x1b000000 0xf1d>,
921			      <0x1b000f20 0xa8>,
922			      <0x1b100000 0x100000>;
923			reg-names = "parf", "dbi", "elbi", "config";
924			device_type = "pci";
925			linux,pci-domain = <0>;
926			bus-range = <0x00 0xff>;
927			#address-cells = <3>;
928			#size-cells = <2>;
929			num-lanes = <1>;
930			phys = <&pcie_phy>;
931			phy-names = "pciephy";
932			status = "disabled";
933
934			ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
935				 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936
937			#interrupt-cells = <1>;
938			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939			interrupt-names = "msi";
940			interrupt-map-mask = <0 0 0 0x7>;
941			interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942					<0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943					<0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944					<0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
945
946			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947				 <&gcc GCC_PCIE_0_AUX_CLK>,
948				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
949				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
951			clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
952
953			power-domains = <&gcc PCIE_0_GDSC>;
954			iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955			perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956
957			pcie@0 {
958				device_type = "pci";
959				reg = <0x0 0x0 0x0 0x0 0x0>;
960				bus-range = <0x01 0xff>;
961
962				#address-cells = <3>;
963				#size-cells = <2>;
964				ranges;
965			};
966		};
967
968		pcie_phy: phy@1c06000 {
969			compatible = "qcom,msm8998-qmp-pcie-phy";
970			reg = <0x01c06000 0x1000>;
971			status = "disabled";
972
973			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975				 <&gcc GCC_PCIE_CLKREF_CLK>,
976				 <&gcc GCC_PCIE_0_PIPE_CLK>;
977			clock-names = "aux",
978				      "cfg_ahb",
979				      "ref",
980				      "pipe";
981
982			clock-output-names = "pcie_0_pipe_clk_src";
983			#clock-cells = <0>;
984
985			#phy-cells = <0>;
986
987			resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988			reset-names = "phy", "common";
989
990			vdda-phy-supply = <&vreg_l1a_0p875>;
991			vdda-pll-supply = <&vreg_l2a_1p2>;
992		};
993
994		ufshc: ufshc@1da4000 {
995			compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996			reg = <0x01da4000 0x2500>;
997			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998			phys = <&ufsphy>;
999			phy-names = "ufsphy";
1000			lanes-per-direction = <2>;
1001			power-domains = <&gcc UFS_GDSC>;
1002			status = "disabled";
1003			#reset-cells = <1>;
1004
1005			clock-names =
1006				"core_clk",
1007				"bus_aggr_clk",
1008				"iface_clk",
1009				"core_clk_unipro",
1010				"ref_clk",
1011				"tx_lane0_sync_clk",
1012				"rx_lane0_sync_clk",
1013				"rx_lane1_sync_clk";
1014			clocks =
1015				<&gcc GCC_UFS_AXI_CLK>,
1016				<&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017				<&gcc GCC_UFS_AHB_CLK>,
1018				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019				<&rpmcc RPM_SMD_LN_BB_CLK1>,
1020				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022				<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023			freq-table-hz =
1024				<50000000 200000000>,
1025				<0 0>,
1026				<0 0>,
1027				<37500000 150000000>,
1028				<0 0>,
1029				<0 0>,
1030				<0 0>,
1031				<0 0>;
1032
1033			resets = <&gcc GCC_UFS_BCR>;
1034			reset-names = "rst";
1035		};
1036
1037		ufsphy: phy@1da7000 {
1038			compatible = "qcom,msm8998-qmp-ufs-phy";
1039			reg = <0x01da7000 0x1000>;
1040
1041			clocks = <&rpmcc RPM_SMD_LN_BB_CLK1>,
1042				 <&gcc GCC_UFS_PHY_AUX_CLK>,
1043				 <&gcc GCC_UFS_CLKREF_CLK>;
1044			clock-names = "ref",
1045				      "ref_aux",
1046				      "qref";
1047
1048			reset-names = "ufsphy";
1049			resets = <&ufshc 0>;
1050
1051			#phy-cells = <0>;
1052			status = "disabled";
1053		};
1054
1055		tcsr_mutex: hwlock@1f40000 {
1056			compatible = "qcom,tcsr-mutex";
1057			reg = <0x01f40000 0x20000>;
1058			#hwlock-cells = <1>;
1059		};
1060
1061		tcsr_regs_1: syscon@1f60000 {
1062			compatible = "qcom,msm8998-tcsr", "syscon";
1063			reg = <0x01f60000 0x20000>;
1064		};
1065
1066		tcsr_regs_2: syscon@1fc0000 {
1067			compatible = "qcom,msm8998-tcsr", "syscon";
1068			reg = <0x01fc0000 0x26000>;
1069		};
1070
1071		tlmm: pinctrl@3400000 {
1072			compatible = "qcom,msm8998-pinctrl";
1073			reg = <0x03400000 0xc00000>;
1074			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075			gpio-ranges = <&tlmm 0 0 150>;
1076			gpio-controller;
1077			#gpio-cells = <2>;
1078			interrupt-controller;
1079			#interrupt-cells = <2>;
1080
1081			sdc2_on: sdc2-on-state {
1082				clk-pins {
1083					pins = "sdc2_clk";
1084					drive-strength = <16>;
1085					bias-disable;
1086				};
1087
1088				cmd-pins {
1089					pins = "sdc2_cmd";
1090					drive-strength = <10>;
1091					bias-pull-up;
1092				};
1093
1094				data-pins {
1095					pins = "sdc2_data";
1096					drive-strength = <10>;
1097					bias-pull-up;
1098				};
1099			};
1100
1101			sdc2_off: sdc2-off-state {
1102				clk-pins {
1103					pins = "sdc2_clk";
1104					drive-strength = <2>;
1105					bias-disable;
1106				};
1107
1108				cmd-pins {
1109					pins = "sdc2_cmd";
1110					drive-strength = <2>;
1111					bias-pull-up;
1112				};
1113
1114				data-pins {
1115					pins = "sdc2_data";
1116					drive-strength = <2>;
1117					bias-pull-up;
1118				};
1119			};
1120
1121			sdc2_cd: sdc2-cd-state {
1122				pins = "gpio95";
1123				function = "gpio";
1124				bias-pull-up;
1125				drive-strength = <2>;
1126			};
1127
1128			blsp1_uart3_on: blsp1-uart3-on-state {
1129				tx-pins {
1130					pins = "gpio45";
1131					function = "blsp_uart3_a";
1132					drive-strength = <2>;
1133					bias-disable;
1134				};
1135
1136				rx-pins {
1137					pins = "gpio46";
1138					function = "blsp_uart3_a";
1139					drive-strength = <2>;
1140					bias-disable;
1141				};
1142
1143				cts-pins {
1144					pins = "gpio47";
1145					function = "blsp_uart3_a";
1146					drive-strength = <2>;
1147					bias-disable;
1148				};
1149
1150				rfr-pins {
1151					pins = "gpio48";
1152					function = "blsp_uart3_a";
1153					drive-strength = <2>;
1154					bias-disable;
1155				};
1156			};
1157
1158			blsp1_i2c1_default: blsp1-i2c1-default-state {
1159				pins = "gpio2", "gpio3";
1160				function = "blsp_i2c1";
1161				drive-strength = <2>;
1162				bias-disable;
1163			};
1164
1165			blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1166				pins = "gpio2", "gpio3";
1167				function = "blsp_i2c1";
1168				drive-strength = <2>;
1169				bias-pull-up;
1170			};
1171
1172			blsp1_i2c2_default: blsp1-i2c2-default-state {
1173				pins = "gpio32", "gpio33";
1174				function = "blsp_i2c2";
1175				drive-strength = <2>;
1176				bias-disable;
1177			};
1178
1179			blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1180				pins = "gpio32", "gpio33";
1181				function = "blsp_i2c2";
1182				drive-strength = <2>;
1183				bias-pull-up;
1184			};
1185
1186			blsp1_i2c3_default: blsp1-i2c3-default-state {
1187				pins = "gpio47", "gpio48";
1188				function = "blsp_i2c3";
1189				drive-strength = <2>;
1190				bias-disable;
1191			};
1192
1193			blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1194				pins = "gpio47", "gpio48";
1195				function = "blsp_i2c3";
1196				drive-strength = <2>;
1197				bias-pull-up;
1198			};
1199
1200			blsp1_i2c4_default: blsp1-i2c4-default-state {
1201				pins = "gpio10", "gpio11";
1202				function = "blsp_i2c4";
1203				drive-strength = <2>;
1204				bias-disable;
1205			};
1206
1207			blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1208				pins = "gpio10", "gpio11";
1209				function = "blsp_i2c4";
1210				drive-strength = <2>;
1211				bias-pull-up;
1212			};
1213
1214			blsp1_i2c5_default: blsp1-i2c5-default-state {
1215				pins = "gpio87", "gpio88";
1216				function = "blsp_i2c5";
1217				drive-strength = <2>;
1218				bias-disable;
1219			};
1220
1221			blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1222				pins = "gpio87", "gpio88";
1223				function = "blsp_i2c5";
1224				drive-strength = <2>;
1225				bias-pull-up;
1226			};
1227
1228			blsp1_i2c6_default: blsp1-i2c6-default-state {
1229				pins = "gpio43", "gpio44";
1230				function = "blsp_i2c6";
1231				drive-strength = <2>;
1232				bias-disable;
1233			};
1234
1235			blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1236				pins = "gpio43", "gpio44";
1237				function = "blsp_i2c6";
1238				drive-strength = <2>;
1239				bias-pull-up;
1240			};
1241
1242			blsp1_spi_b_default: blsp1-spi-b-default-state {
1243				pins = "gpio23", "gpio28";
1244				function = "blsp1_spi_b";
1245				drive-strength = <6>;
1246				bias-disable;
1247			};
1248
1249			blsp1_spi1_default: blsp1-spi1-default-state {
1250				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1251				function = "blsp_spi1";
1252				drive-strength = <6>;
1253				bias-disable;
1254			};
1255
1256			blsp1_spi2_default: blsp1-spi2-default-state {
1257				pins = "gpio31", "gpio34", "gpio32", "gpio33";
1258				function = "blsp_spi2";
1259				drive-strength = <6>;
1260				bias-disable;
1261			};
1262
1263			blsp1_spi3_default: blsp1-spi3-default-state {
1264				pins = "gpio45", "gpio46", "gpio47", "gpio48";
1265				function = "blsp_spi2";
1266				drive-strength = <6>;
1267				bias-disable;
1268			};
1269
1270			blsp1_spi4_default: blsp1-spi4-default-state {
1271				pins = "gpio8", "gpio9", "gpio10", "gpio11";
1272				function = "blsp_spi4";
1273				drive-strength = <6>;
1274				bias-disable;
1275			};
1276
1277			blsp1_spi5_default: blsp1-spi5-default-state {
1278				pins = "gpio85", "gpio86", "gpio87", "gpio88";
1279				function = "blsp_spi5";
1280				drive-strength = <6>;
1281				bias-disable;
1282			};
1283
1284			blsp1_spi6_default: blsp1-spi6-default-state {
1285				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1286				function = "blsp_spi6";
1287				drive-strength = <6>;
1288				bias-disable;
1289			};
1290
1291
1292			/* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1293			blsp2_i2c1_default: blsp2-i2c1-default-state {
1294				pins = "gpio55", "gpio56";
1295				function = "blsp_i2c7";
1296				drive-strength = <2>;
1297				bias-disable;
1298			};
1299
1300			blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1301				pins = "gpio55", "gpio56";
1302				function = "blsp_i2c7";
1303				drive-strength = <2>;
1304				bias-pull-up;
1305			};
1306
1307			blsp2_i2c2_default: blsp2-i2c2-default-state {
1308				pins = "gpio6", "gpio7";
1309				function = "blsp_i2c8";
1310				drive-strength = <2>;
1311				bias-disable;
1312			};
1313
1314			blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1315				pins = "gpio6", "gpio7";
1316				function = "blsp_i2c8";
1317				drive-strength = <2>;
1318				bias-pull-up;
1319			};
1320
1321			blsp2_i2c3_default: blsp2-i2c3-default-state {
1322				pins = "gpio51", "gpio52";
1323				function = "blsp_i2c9";
1324				drive-strength = <2>;
1325				bias-disable;
1326			};
1327
1328			blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1329				pins = "gpio51", "gpio52";
1330				function = "blsp_i2c9";
1331				drive-strength = <2>;
1332				bias-pull-up;
1333			};
1334
1335			blsp2_i2c4_default: blsp2-i2c4-default-state {
1336				pins = "gpio67", "gpio68";
1337				function = "blsp_i2c10";
1338				drive-strength = <2>;
1339				bias-disable;
1340			};
1341
1342			blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1343				pins = "gpio67", "gpio68";
1344				function = "blsp_i2c10";
1345				drive-strength = <2>;
1346				bias-pull-up;
1347			};
1348
1349			blsp2_i2c5_default: blsp2-i2c5-default-state {
1350				pins = "gpio60", "gpio61";
1351				function = "blsp_i2c11";
1352				drive-strength = <2>;
1353				bias-disable;
1354			};
1355
1356			blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1357				pins = "gpio60", "gpio61";
1358				function = "blsp_i2c11";
1359				drive-strength = <2>;
1360				bias-pull-up;
1361			};
1362
1363			blsp2_i2c6_default: blsp2-i2c6-default-state {
1364				pins = "gpio83", "gpio84";
1365				function = "blsp_i2c12";
1366				drive-strength = <2>;
1367				bias-disable;
1368			};
1369
1370			blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1371				pins = "gpio83", "gpio84";
1372				function = "blsp_i2c12";
1373				drive-strength = <2>;
1374				bias-pull-up;
1375			};
1376
1377			blsp2_spi1_default: blsp2-spi1-default-state {
1378				pins = "gpio53", "gpio54", "gpio55", "gpio56";
1379				function = "blsp_spi7";
1380				drive-strength = <6>;
1381				bias-disable;
1382			};
1383
1384			blsp2_spi2_default: blsp2-spi2-default-state {
1385				pins = "gpio4", "gpio5", "gpio6", "gpio7";
1386				function = "blsp_spi8";
1387				drive-strength = <6>;
1388				bias-disable;
1389			};
1390
1391			blsp2_spi3_default: blsp2-spi3-default-state {
1392				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1393				function = "blsp_spi9";
1394				drive-strength = <6>;
1395				bias-disable;
1396			};
1397
1398			blsp2_spi4_default: blsp2-spi4-default-state {
1399				pins = "gpio65", "gpio66", "gpio67", "gpio68";
1400				function = "blsp_spi10";
1401				drive-strength = <6>;
1402				bias-disable;
1403			};
1404
1405			blsp2_spi5_default: blsp2-spi5-default-state {
1406				pins = "gpio58", "gpio59", "gpio60", "gpio61";
1407				function = "blsp_spi11";
1408				drive-strength = <6>;
1409				bias-disable;
1410			};
1411
1412			blsp2_spi6_default: blsp2-spi6-default-state {
1413				pins = "gpio81", "gpio82", "gpio83", "gpio84";
1414				function = "blsp_spi12";
1415				drive-strength = <6>;
1416				bias-disable;
1417			};
1418		};
1419
1420		remoteproc_mss: remoteproc@4080000 {
1421			compatible = "qcom,msm8998-mss-pil";
1422			reg = <0x04080000 0x100>, <0x04180000 0x20>;
1423			reg-names = "qdsp6", "rmb";
1424
1425			interrupts-extended =
1426				<&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1427				<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1428				<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1429				<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1430				<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1431				<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1432			interrupt-names = "wdog", "fatal", "ready",
1433					  "handover", "stop-ack",
1434					  "shutdown-ack";
1435
1436			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1437				 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1438				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1439				 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1440				 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1441				 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1442				 <&rpmcc RPM_SMD_QDSS_CLK>,
1443				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1444			clock-names = "iface", "bus", "mem", "gpll0_mss",
1445				      "snoc_axi", "mnoc_axi", "qdss", "xo";
1446
1447			qcom,smem-states = <&modem_smp2p_out 0>;
1448			qcom,smem-state-names = "stop";
1449
1450			resets = <&gcc GCC_MSS_RESTART>;
1451			reset-names = "mss_restart";
1452
1453			qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1454
1455			power-domains = <&rpmpd MSM8998_VDDCX>,
1456					<&rpmpd MSM8998_VDDMX>;
1457			power-domain-names = "cx", "mx";
1458
1459			status = "disabled";
1460
1461			mba {
1462				memory-region = <&mba_mem>;
1463			};
1464
1465			mpss {
1466				memory-region = <&mpss_mem>;
1467			};
1468
1469			metadata {
1470				memory-region = <&mdata_mem>;
1471			};
1472
1473			glink-edge {
1474				interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1475				label = "modem";
1476				qcom,remote-pid = <1>;
1477				mboxes = <&apcs_glb 15>;
1478			};
1479		};
1480
1481		adreno_gpu: gpu@5000000 {
1482			compatible = "qcom,adreno-540.1", "qcom,adreno";
1483			reg = <0x05000000 0x40000>;
1484			reg-names = "kgsl_3d0_reg_memory";
1485
1486			clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1487				<&gpucc RBBMTIMER_CLK>,
1488				<&gcc GCC_BIMC_GFX_CLK>,
1489				<&gcc GCC_GPU_BIMC_GFX_CLK>,
1490				<&gpucc RBCPR_CLK>,
1491				<&gpucc GFX3D_CLK>;
1492			clock-names = "iface",
1493				"rbbmtimer",
1494				"mem",
1495				"mem_iface",
1496				"rbcpr",
1497				"core";
1498
1499			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1500			iommus = <&adreno_smmu 0>;
1501			operating-points-v2 = <&gpu_opp_table>;
1502			power-domains = <&rpmpd MSM8998_VDDMX>;
1503			status = "disabled";
1504
1505			gpu_opp_table: opp-table {
1506				compatible = "operating-points-v2";
1507				opp-710000097 {
1508					opp-hz = /bits/ 64 <710000097>;
1509					opp-level = <RPM_SMD_LEVEL_TURBO>;
1510					opp-supported-hw = <0xff>;
1511				};
1512
1513				opp-670000048 {
1514					opp-hz = /bits/ 64 <670000048>;
1515					opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1516					opp-supported-hw = <0xff>;
1517				};
1518
1519				opp-596000097 {
1520					opp-hz = /bits/ 64 <596000097>;
1521					opp-level = <RPM_SMD_LEVEL_NOM>;
1522					opp-supported-hw = <0xff>;
1523				};
1524
1525				opp-515000097 {
1526					opp-hz = /bits/ 64 <515000097>;
1527					opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1528					opp-supported-hw = <0xff>;
1529				};
1530
1531				opp-414000000 {
1532					opp-hz = /bits/ 64 <414000000>;
1533					opp-level = <RPM_SMD_LEVEL_SVS>;
1534					opp-supported-hw = <0xff>;
1535				};
1536
1537				opp-342000000 {
1538					opp-hz = /bits/ 64 <342000000>;
1539					opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1540					opp-supported-hw = <0xff>;
1541				};
1542
1543				opp-257000000 {
1544					opp-hz = /bits/ 64 <257000000>;
1545					opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1546					opp-supported-hw = <0xff>;
1547				};
1548			};
1549		};
1550
1551		adreno_smmu: iommu@5040000 {
1552			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1553			reg = <0x05040000 0x10000>;
1554			clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1555				 <&gcc GCC_BIMC_GFX_CLK>,
1556				 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1557			clock-names = "iface", "mem", "mem_iface";
1558
1559			#global-interrupts = <0>;
1560			#iommu-cells = <1>;
1561			interrupts =
1562				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1563				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1564				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1565			/*
1566			 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1567			 * GPU-CX for SMMU but we need both of them up for Adreno.
1568			 * Contemporarily, we also need to manage the VDDMX rpmpd
1569			 * domain in the Adreno driver.
1570			 * Enable GPU CX/GX GDSCs here so that we can manage the
1571			 * SoC VDDMX RPM Power Domain in the Adreno driver.
1572			 */
1573			power-domains = <&gpucc GPU_GX_GDSC>;
1574		};
1575
1576		gpucc: clock-controller@5065000 {
1577			compatible = "qcom,msm8998-gpucc";
1578			#clock-cells = <1>;
1579			#reset-cells = <1>;
1580			#power-domain-cells = <1>;
1581			reg = <0x05065000 0x9000>;
1582
1583			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1584				 <&gcc GCC_GPU_GPLL0_CLK>;
1585			clock-names = "xo",
1586				      "gpll0";
1587		};
1588
1589		lpass_q6_smmu: iommu@5100000 {
1590			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1591			reg = <0x05100000 0x40000>;
1592			clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
1593			clock-names = "bus";
1594
1595			#global-interrupts = <0>;
1596			#iommu-cells = <1>;
1597			interrupts =
1598				<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1599				<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1600				<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1601				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1602				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1603				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1604				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1605				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1606				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1607				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1608				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1609				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1610				<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1611
1612			power-domains = <&gcc LPASS_ADSP_GDSC>;
1613			status = "disabled";
1614		};
1615
1616		remoteproc_slpi: remoteproc@5800000 {
1617			compatible = "qcom,msm8998-slpi-pas";
1618			reg = <0x05800000 0x4040>;
1619
1620			interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1621					      <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1622					      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1623					      <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1624					      <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1625			interrupt-names = "wdog", "fatal", "ready",
1626					  "handover", "stop-ack";
1627
1628			px-supply = <&vreg_lvs2a_1p8>;
1629
1630			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1631			clock-names = "xo";
1632
1633			memory-region = <&slpi_mem>;
1634
1635			qcom,smem-states = <&slpi_smp2p_out 0>;
1636			qcom,smem-state-names = "stop";
1637
1638			power-domains = <&rpmpd MSM8998_SSCCX>;
1639			power-domain-names = "ssc_cx";
1640
1641			status = "disabled";
1642
1643			glink-edge {
1644				interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1645				label = "dsps";
1646				qcom,remote-pid = <3>;
1647				mboxes = <&apcs_glb 27>;
1648			};
1649		};
1650
1651		stm: stm@6002000 {
1652			compatible = "arm,coresight-stm", "arm,primecell";
1653			reg = <0x06002000 0x1000>,
1654			      <0x16280000 0x180000>;
1655			reg-names = "stm-base", "stm-stimulus-base";
1656			status = "disabled";
1657
1658			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1659			clock-names = "apb_pclk", "atclk";
1660
1661			out-ports {
1662				port {
1663					stm_out: endpoint {
1664						remote-endpoint = <&funnel0_in7>;
1665					};
1666				};
1667			};
1668		};
1669
1670		funnel1: funnel@6041000 {
1671			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672			reg = <0x06041000 0x1000>;
1673			status = "disabled";
1674
1675			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1676			clock-names = "apb_pclk", "atclk";
1677
1678			out-ports {
1679				port {
1680					funnel0_out: endpoint {
1681						remote-endpoint =
1682						  <&merge_funnel_in0>;
1683					};
1684				};
1685			};
1686
1687			in-ports {
1688				#address-cells = <1>;
1689				#size-cells = <0>;
1690
1691				port@7 {
1692					reg = <7>;
1693					funnel0_in7: endpoint {
1694						remote-endpoint = <&stm_out>;
1695					};
1696				};
1697			};
1698		};
1699
1700		funnel2: funnel@6042000 {
1701			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1702			reg = <0x06042000 0x1000>;
1703			status = "disabled";
1704
1705			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1706			clock-names = "apb_pclk", "atclk";
1707
1708			out-ports {
1709				port {
1710					funnel1_out: endpoint {
1711						remote-endpoint =
1712						  <&merge_funnel_in1>;
1713					};
1714				};
1715			};
1716
1717			in-ports {
1718				#address-cells = <1>;
1719				#size-cells = <0>;
1720
1721				port@6 {
1722					reg = <6>;
1723					funnel1_in6: endpoint {
1724						remote-endpoint =
1725						  <&apss_merge_funnel_out>;
1726					};
1727				};
1728			};
1729		};
1730
1731		funnel3: funnel@6045000 {
1732			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1733			reg = <0x06045000 0x1000>;
1734			status = "disabled";
1735
1736			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1737			clock-names = "apb_pclk", "atclk";
1738
1739			out-ports {
1740				port {
1741					merge_funnel_out: endpoint {
1742						remote-endpoint =
1743						  <&etf_in>;
1744					};
1745				};
1746			};
1747
1748			in-ports {
1749				#address-cells = <1>;
1750				#size-cells = <0>;
1751
1752				port@0 {
1753					reg = <0>;
1754					merge_funnel_in0: endpoint {
1755						remote-endpoint =
1756						  <&funnel0_out>;
1757					};
1758				};
1759
1760				port@1 {
1761					reg = <1>;
1762					merge_funnel_in1: endpoint {
1763						remote-endpoint =
1764						  <&funnel1_out>;
1765					};
1766				};
1767			};
1768		};
1769
1770		replicator1: replicator@6046000 {
1771			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1772			reg = <0x06046000 0x1000>;
1773			status = "disabled";
1774
1775			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1776			clock-names = "apb_pclk", "atclk";
1777
1778			out-ports {
1779				port {
1780					replicator_out: endpoint {
1781						remote-endpoint = <&etr_in>;
1782					};
1783				};
1784			};
1785
1786			in-ports {
1787				port {
1788					replicator_in: endpoint {
1789						remote-endpoint = <&etf_out>;
1790					};
1791				};
1792			};
1793		};
1794
1795		etf: etf@6047000 {
1796			compatible = "arm,coresight-tmc", "arm,primecell";
1797			reg = <0x06047000 0x1000>;
1798			status = "disabled";
1799
1800			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801			clock-names = "apb_pclk", "atclk";
1802
1803			out-ports {
1804				port {
1805					etf_out: endpoint {
1806						remote-endpoint =
1807						  <&replicator_in>;
1808					};
1809				};
1810			};
1811
1812			in-ports {
1813				port {
1814					etf_in: endpoint {
1815						remote-endpoint =
1816						  <&merge_funnel_out>;
1817					};
1818				};
1819			};
1820		};
1821
1822		etr: etr@6048000 {
1823			compatible = "arm,coresight-tmc", "arm,primecell";
1824			reg = <0x06048000 0x1000>;
1825			status = "disabled";
1826
1827			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1828			clock-names = "apb_pclk", "atclk";
1829			arm,scatter-gather;
1830
1831			in-ports {
1832				port {
1833					etr_in: endpoint {
1834						remote-endpoint =
1835						  <&replicator_out>;
1836					};
1837				};
1838			};
1839		};
1840
1841		etm1: etm@7840000 {
1842			compatible = "arm,coresight-etm4x", "arm,primecell";
1843			reg = <0x07840000 0x1000>;
1844			status = "disabled";
1845
1846			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1847			clock-names = "apb_pclk", "atclk";
1848
1849			cpu = <&CPU0>;
1850
1851			out-ports {
1852				port {
1853					etm0_out: endpoint {
1854						remote-endpoint =
1855						  <&apss_funnel_in0>;
1856					};
1857				};
1858			};
1859		};
1860
1861		etm2: etm@7940000 {
1862			compatible = "arm,coresight-etm4x", "arm,primecell";
1863			reg = <0x07940000 0x1000>;
1864			status = "disabled";
1865
1866			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1867			clock-names = "apb_pclk", "atclk";
1868
1869			cpu = <&CPU1>;
1870
1871			out-ports {
1872				port {
1873					etm1_out: endpoint {
1874						remote-endpoint =
1875						  <&apss_funnel_in1>;
1876					};
1877				};
1878			};
1879		};
1880
1881		etm3: etm@7a40000 {
1882			compatible = "arm,coresight-etm4x", "arm,primecell";
1883			reg = <0x07a40000 0x1000>;
1884			status = "disabled";
1885
1886			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1887			clock-names = "apb_pclk", "atclk";
1888
1889			cpu = <&CPU2>;
1890
1891			out-ports {
1892				port {
1893					etm2_out: endpoint {
1894						remote-endpoint =
1895						  <&apss_funnel_in2>;
1896					};
1897				};
1898			};
1899		};
1900
1901		etm4: etm@7b40000 {
1902			compatible = "arm,coresight-etm4x", "arm,primecell";
1903			reg = <0x07b40000 0x1000>;
1904			status = "disabled";
1905
1906			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1907			clock-names = "apb_pclk", "atclk";
1908
1909			cpu = <&CPU3>;
1910
1911			out-ports {
1912				port {
1913					etm3_out: endpoint {
1914						remote-endpoint =
1915						  <&apss_funnel_in3>;
1916					};
1917				};
1918			};
1919		};
1920
1921		funnel4: funnel@7b60000 { /* APSS Funnel */
1922			compatible = "arm,coresight-etm4x", "arm,primecell";
1923			reg = <0x07b60000 0x1000>;
1924			status = "disabled";
1925
1926			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1927			clock-names = "apb_pclk", "atclk";
1928
1929			out-ports {
1930				port {
1931					apss_funnel_out: endpoint {
1932						remote-endpoint =
1933						  <&apss_merge_funnel_in>;
1934					};
1935				};
1936			};
1937
1938			in-ports {
1939				#address-cells = <1>;
1940				#size-cells = <0>;
1941
1942				port@0 {
1943					reg = <0>;
1944					apss_funnel_in0: endpoint {
1945						remote-endpoint =
1946						  <&etm0_out>;
1947					};
1948				};
1949
1950				port@1 {
1951					reg = <1>;
1952					apss_funnel_in1: endpoint {
1953						remote-endpoint =
1954						  <&etm1_out>;
1955					};
1956				};
1957
1958				port@2 {
1959					reg = <2>;
1960					apss_funnel_in2: endpoint {
1961						remote-endpoint =
1962						  <&etm2_out>;
1963					};
1964				};
1965
1966				port@3 {
1967					reg = <3>;
1968					apss_funnel_in3: endpoint {
1969						remote-endpoint =
1970						  <&etm3_out>;
1971					};
1972				};
1973
1974				port@4 {
1975					reg = <4>;
1976					apss_funnel_in4: endpoint {
1977						remote-endpoint =
1978						  <&etm4_out>;
1979					};
1980				};
1981
1982				port@5 {
1983					reg = <5>;
1984					apss_funnel_in5: endpoint {
1985						remote-endpoint =
1986						  <&etm5_out>;
1987					};
1988				};
1989
1990				port@6 {
1991					reg = <6>;
1992					apss_funnel_in6: endpoint {
1993						remote-endpoint =
1994						  <&etm6_out>;
1995					};
1996				};
1997
1998				port@7 {
1999					reg = <7>;
2000					apss_funnel_in7: endpoint {
2001						remote-endpoint =
2002						  <&etm7_out>;
2003					};
2004				};
2005			};
2006		};
2007
2008		funnel5: funnel@7b70000 {
2009			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2010			reg = <0x07b70000 0x1000>;
2011			status = "disabled";
2012
2013			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014			clock-names = "apb_pclk", "atclk";
2015
2016			out-ports {
2017				port {
2018					apss_merge_funnel_out: endpoint {
2019						remote-endpoint =
2020						  <&funnel1_in6>;
2021					};
2022				};
2023			};
2024
2025			in-ports {
2026				port {
2027					apss_merge_funnel_in: endpoint {
2028						remote-endpoint =
2029						  <&apss_funnel_out>;
2030					};
2031				};
2032			};
2033		};
2034
2035		etm5: etm@7c40000 {
2036			compatible = "arm,coresight-etm4x", "arm,primecell";
2037			reg = <0x07c40000 0x1000>;
2038			status = "disabled";
2039
2040			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2041			clock-names = "apb_pclk", "atclk";
2042
2043			cpu = <&CPU4>;
2044
2045			out-ports {
2046				port {
2047					etm4_out: endpoint {
2048						remote-endpoint = <&apss_funnel_in4>;
2049					};
2050				};
2051			};
2052		};
2053
2054		etm6: etm@7d40000 {
2055			compatible = "arm,coresight-etm4x", "arm,primecell";
2056			reg = <0x07d40000 0x1000>;
2057			status = "disabled";
2058
2059			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2060			clock-names = "apb_pclk", "atclk";
2061
2062			cpu = <&CPU5>;
2063
2064			out-ports {
2065				port {
2066					etm5_out: endpoint {
2067						remote-endpoint = <&apss_funnel_in5>;
2068					};
2069				};
2070			};
2071		};
2072
2073		etm7: etm@7e40000 {
2074			compatible = "arm,coresight-etm4x", "arm,primecell";
2075			reg = <0x07e40000 0x1000>;
2076			status = "disabled";
2077
2078			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2079			clock-names = "apb_pclk", "atclk";
2080
2081			cpu = <&CPU6>;
2082
2083			out-ports {
2084				port {
2085					etm6_out: endpoint {
2086						remote-endpoint = <&apss_funnel_in6>;
2087					};
2088				};
2089			};
2090		};
2091
2092		etm8: etm@7f40000 {
2093			compatible = "arm,coresight-etm4x", "arm,primecell";
2094			reg = <0x07f40000 0x1000>;
2095			status = "disabled";
2096
2097			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2098			clock-names = "apb_pclk", "atclk";
2099
2100			cpu = <&CPU7>;
2101
2102			out-ports {
2103				port {
2104					etm7_out: endpoint {
2105						remote-endpoint = <&apss_funnel_in7>;
2106					};
2107				};
2108			};
2109		};
2110
2111		sram@290000 {
2112			compatible = "qcom,rpm-stats";
2113			reg = <0x00290000 0x10000>;
2114		};
2115
2116		spmi_bus: spmi@800f000 {
2117			compatible = "qcom,spmi-pmic-arb";
2118			reg = <0x0800f000 0x1000>,
2119			      <0x08400000 0x1000000>,
2120			      <0x09400000 0x1000000>,
2121			      <0x0a400000 0x220000>,
2122			      <0x0800a000 0x3000>;
2123			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2124			interrupt-names = "periph_irq";
2125			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2126			qcom,ee = <0>;
2127			qcom,channel = <0>;
2128			#address-cells = <2>;
2129			#size-cells = <0>;
2130			interrupt-controller;
2131			#interrupt-cells = <4>;
2132		};
2133
2134		usb3: usb@a8f8800 {
2135			compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2136			reg = <0x0a8f8800 0x400>;
2137			status = "disabled";
2138			#address-cells = <1>;
2139			#size-cells = <1>;
2140			ranges;
2141
2142			clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2143				 <&gcc GCC_USB30_MASTER_CLK>,
2144				 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2145				 <&gcc GCC_USB30_SLEEP_CLK>,
2146				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2147			clock-names = "cfg_noc",
2148				      "core",
2149				      "iface",
2150				      "sleep",
2151				      "mock_utmi";
2152
2153			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2154					  <&gcc GCC_USB30_MASTER_CLK>;
2155			assigned-clock-rates = <19200000>, <120000000>;
2156
2157			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
2158				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2159				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2160			interrupt-names = "pwr_event",
2161					  "qusb2_phy",
2162					  "ss_phy_irq";
2163
2164			power-domains = <&gcc USB_30_GDSC>;
2165
2166			resets = <&gcc GCC_USB_30_BCR>;
2167
2168			usb3_dwc3: usb@a800000 {
2169				compatible = "snps,dwc3";
2170				reg = <0x0a800000 0xcd00>;
2171				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2172				snps,dis_u2_susphy_quirk;
2173				snps,dis_enblslpm_quirk;
2174				snps,parkmode-disable-ss-quirk;
2175				phys = <&qusb2phy>, <&usb3phy>;
2176				phy-names = "usb2-phy", "usb3-phy";
2177				snps,has-lpm-erratum;
2178				snps,hird-threshold = /bits/ 8 <0x10>;
2179			};
2180		};
2181
2182		usb3phy: phy@c010000 {
2183			compatible = "qcom,msm8998-qmp-usb3-phy";
2184			reg = <0x0c010000 0x1000>;
2185
2186			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2187				 <&gcc GCC_USB3_CLKREF_CLK>,
2188				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2189				 <&gcc GCC_USB3_PHY_PIPE_CLK>;
2190			clock-names = "aux",
2191				      "ref",
2192				      "cfg_ahb",
2193				      "pipe";
2194			clock-output-names = "usb3_phy_pipe_clk_src";
2195			#clock-cells = <0>;
2196			#phy-cells = <0>;
2197
2198			resets = <&gcc GCC_USB3_PHY_BCR>,
2199				 <&gcc GCC_USB3PHY_PHY_BCR>;
2200			reset-names = "phy",
2201				      "phy_phy";
2202
2203			qcom,tcsr-reg = <&tcsr_regs_2 0xb244>;
2204
2205			status = "disabled";
2206		};
2207
2208		qusb2phy: phy@c012000 {
2209			compatible = "qcom,msm8998-qusb2-phy";
2210			reg = <0x0c012000 0x2a8>;
2211			status = "disabled";
2212			#phy-cells = <0>;
2213
2214			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2215				 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2216			clock-names = "cfg_ahb", "ref";
2217
2218			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2219
2220			nvmem-cells = <&qusb2_hstx_trim>;
2221		};
2222
2223		sdhc2: mmc@c0a4900 {
2224			compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2225			reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2226			reg-names = "hc", "core";
2227
2228			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2229				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2230			interrupt-names = "hc_irq", "pwr_irq";
2231
2232			clock-names = "iface", "core", "xo";
2233			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2234				 <&gcc GCC_SDCC2_APPS_CLK>,
2235				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2236			bus-width = <4>;
2237			status = "disabled";
2238		};
2239
2240		blsp1_dma: dma-controller@c144000 {
2241			compatible = "qcom,bam-v1.7.0";
2242			reg = <0x0c144000 0x25000>;
2243			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2244			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2245			clock-names = "bam_clk";
2246			#dma-cells = <1>;
2247			qcom,ee = <0>;
2248			qcom,controlled-remotely;
2249			num-channels = <18>;
2250			qcom,num-ees = <4>;
2251		};
2252
2253		blsp1_uart3: serial@c171000 {
2254			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2255			reg = <0x0c171000 0x1000>;
2256			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2257			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2258				 <&gcc GCC_BLSP1_AHB_CLK>;
2259			clock-names = "core", "iface";
2260			dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2261			dma-names = "tx", "rx";
2262			pinctrl-names = "default";
2263			pinctrl-0 = <&blsp1_uart3_on>;
2264			status = "disabled";
2265		};
2266
2267		blsp1_i2c1: i2c@c175000 {
2268			compatible = "qcom,i2c-qup-v2.2.1";
2269			reg = <0x0c175000 0x600>;
2270			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2271
2272			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2273				 <&gcc GCC_BLSP1_AHB_CLK>;
2274			clock-names = "core", "iface";
2275			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2276			dma-names = "tx", "rx";
2277			pinctrl-names = "default", "sleep";
2278			pinctrl-0 = <&blsp1_i2c1_default>;
2279			pinctrl-1 = <&blsp1_i2c1_sleep>;
2280			clock-frequency = <400000>;
2281
2282			status = "disabled";
2283			#address-cells = <1>;
2284			#size-cells = <0>;
2285		};
2286
2287		blsp1_i2c2: i2c@c176000 {
2288			compatible = "qcom,i2c-qup-v2.2.1";
2289			reg = <0x0c176000 0x600>;
2290			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2291
2292			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2293				 <&gcc GCC_BLSP1_AHB_CLK>;
2294			clock-names = "core", "iface";
2295			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2296			dma-names = "tx", "rx";
2297			pinctrl-names = "default", "sleep";
2298			pinctrl-0 = <&blsp1_i2c2_default>;
2299			pinctrl-1 = <&blsp1_i2c2_sleep>;
2300			clock-frequency = <400000>;
2301
2302			status = "disabled";
2303			#address-cells = <1>;
2304			#size-cells = <0>;
2305		};
2306
2307		blsp1_i2c3: i2c@c177000 {
2308			compatible = "qcom,i2c-qup-v2.2.1";
2309			reg = <0x0c177000 0x600>;
2310			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2311
2312			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2313				 <&gcc GCC_BLSP1_AHB_CLK>;
2314			clock-names = "core", "iface";
2315			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2316			dma-names = "tx", "rx";
2317			pinctrl-names = "default", "sleep";
2318			pinctrl-0 = <&blsp1_i2c3_default>;
2319			pinctrl-1 = <&blsp1_i2c3_sleep>;
2320			clock-frequency = <400000>;
2321
2322			status = "disabled";
2323			#address-cells = <1>;
2324			#size-cells = <0>;
2325		};
2326
2327		blsp1_i2c4: i2c@c178000 {
2328			compatible = "qcom,i2c-qup-v2.2.1";
2329			reg = <0x0c178000 0x600>;
2330			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2331
2332			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2333				 <&gcc GCC_BLSP1_AHB_CLK>;
2334			clock-names = "core", "iface";
2335			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2336			dma-names = "tx", "rx";
2337			pinctrl-names = "default", "sleep";
2338			pinctrl-0 = <&blsp1_i2c4_default>;
2339			pinctrl-1 = <&blsp1_i2c4_sleep>;
2340			clock-frequency = <400000>;
2341
2342			status = "disabled";
2343			#address-cells = <1>;
2344			#size-cells = <0>;
2345		};
2346
2347		blsp1_i2c5: i2c@c179000 {
2348			compatible = "qcom,i2c-qup-v2.2.1";
2349			reg = <0x0c179000 0x600>;
2350			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2351
2352			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2353				 <&gcc GCC_BLSP1_AHB_CLK>;
2354			clock-names = "core", "iface";
2355			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2356			dma-names = "tx", "rx";
2357			pinctrl-names = "default", "sleep";
2358			pinctrl-0 = <&blsp1_i2c5_default>;
2359			pinctrl-1 = <&blsp1_i2c5_sleep>;
2360			clock-frequency = <400000>;
2361
2362			status = "disabled";
2363			#address-cells = <1>;
2364			#size-cells = <0>;
2365		};
2366
2367		blsp1_i2c6: i2c@c17a000 {
2368			compatible = "qcom,i2c-qup-v2.2.1";
2369			reg = <0x0c17a000 0x600>;
2370			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2371
2372			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2373				 <&gcc GCC_BLSP1_AHB_CLK>;
2374			clock-names = "core", "iface";
2375			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2376			dma-names = "tx", "rx";
2377			pinctrl-names = "default", "sleep";
2378			pinctrl-0 = <&blsp1_i2c6_default>;
2379			pinctrl-1 = <&blsp1_i2c6_sleep>;
2380			clock-frequency = <400000>;
2381
2382			status = "disabled";
2383			#address-cells = <1>;
2384			#size-cells = <0>;
2385		};
2386
2387		blsp1_spi1: spi@c175000 {
2388			compatible = "qcom,spi-qup-v2.2.1";
2389			reg = <0x0c175000 0x600>;
2390			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2391
2392			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2393				 <&gcc GCC_BLSP1_AHB_CLK>;
2394			clock-names = "core", "iface";
2395			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2396			dma-names = "tx", "rx";
2397			pinctrl-names = "default";
2398			pinctrl-0 = <&blsp1_spi1_default>;
2399
2400			status = "disabled";
2401			#address-cells = <1>;
2402			#size-cells = <0>;
2403		};
2404
2405		blsp1_spi2: spi@c176000 {
2406			compatible = "qcom,spi-qup-v2.2.1";
2407			reg = <0x0c176000 0x600>;
2408			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2409
2410			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2411				 <&gcc GCC_BLSP1_AHB_CLK>;
2412			clock-names = "core", "iface";
2413			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2414			dma-names = "tx", "rx";
2415			pinctrl-names = "default";
2416			pinctrl-0 = <&blsp1_spi2_default>;
2417
2418			status = "disabled";
2419			#address-cells = <1>;
2420			#size-cells = <0>;
2421		};
2422
2423		blsp1_spi3: spi@c177000 {
2424			compatible = "qcom,spi-qup-v2.2.1";
2425			reg = <0x0c177000 0x600>;
2426			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2427
2428			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2429				 <&gcc GCC_BLSP1_AHB_CLK>;
2430			clock-names = "core", "iface";
2431			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2432			dma-names = "tx", "rx";
2433			pinctrl-names = "default";
2434			pinctrl-0 = <&blsp1_spi3_default>;
2435
2436			status = "disabled";
2437			#address-cells = <1>;
2438			#size-cells = <0>;
2439		};
2440
2441		blsp1_spi4: spi@c178000 {
2442			compatible = "qcom,spi-qup-v2.2.1";
2443			reg = <0x0c178000 0x600>;
2444			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2445
2446			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2447				 <&gcc GCC_BLSP1_AHB_CLK>;
2448			clock-names = "core", "iface";
2449			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2450			dma-names = "tx", "rx";
2451			pinctrl-names = "default";
2452			pinctrl-0 = <&blsp1_spi4_default>;
2453
2454			status = "disabled";
2455			#address-cells = <1>;
2456			#size-cells = <0>;
2457		};
2458
2459		blsp1_spi5: spi@c179000 {
2460			compatible = "qcom,spi-qup-v2.2.1";
2461			reg = <0x0c179000 0x600>;
2462			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2463
2464			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2465				 <&gcc GCC_BLSP1_AHB_CLK>;
2466			clock-names = "core", "iface";
2467			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2468			dma-names = "tx", "rx";
2469			pinctrl-names = "default";
2470			pinctrl-0 = <&blsp1_spi5_default>;
2471
2472			status = "disabled";
2473			#address-cells = <1>;
2474			#size-cells = <0>;
2475		};
2476
2477		blsp1_spi6: spi@c17a000 {
2478			compatible = "qcom,spi-qup-v2.2.1";
2479			reg = <0x0c17a000 0x600>;
2480			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2481
2482			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2483				 <&gcc GCC_BLSP1_AHB_CLK>;
2484			clock-names = "core", "iface";
2485			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2486			dma-names = "tx", "rx";
2487			pinctrl-names = "default";
2488			pinctrl-0 = <&blsp1_spi6_default>;
2489
2490			status = "disabled";
2491			#address-cells = <1>;
2492			#size-cells = <0>;
2493		};
2494
2495		blsp2_dma: dma-controller@c184000 {
2496			compatible = "qcom,bam-v1.7.0";
2497			reg = <0x0c184000 0x25000>;
2498			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2499			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2500			clock-names = "bam_clk";
2501			#dma-cells = <1>;
2502			qcom,ee = <0>;
2503			qcom,controlled-remotely;
2504			num-channels = <18>;
2505			qcom,num-ees = <4>;
2506		};
2507
2508		blsp2_uart1: serial@c1b0000 {
2509			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2510			reg = <0x0c1b0000 0x1000>;
2511			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2512			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2513				 <&gcc GCC_BLSP2_AHB_CLK>;
2514			clock-names = "core", "iface";
2515			status = "disabled";
2516		};
2517
2518		blsp2_i2c1: i2c@c1b5000 {
2519			compatible = "qcom,i2c-qup-v2.2.1";
2520			reg = <0x0c1b5000 0x600>;
2521			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2522
2523			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2524				 <&gcc GCC_BLSP2_AHB_CLK>;
2525			clock-names = "core", "iface";
2526			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2527			dma-names = "tx", "rx";
2528			pinctrl-names = "default", "sleep";
2529			pinctrl-0 = <&blsp2_i2c1_default>;
2530			pinctrl-1 = <&blsp2_i2c1_sleep>;
2531			clock-frequency = <400000>;
2532
2533			status = "disabled";
2534			#address-cells = <1>;
2535			#size-cells = <0>;
2536		};
2537
2538		blsp2_i2c2: i2c@c1b6000 {
2539			compatible = "qcom,i2c-qup-v2.2.1";
2540			reg = <0x0c1b6000 0x600>;
2541			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2542
2543			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2544				 <&gcc GCC_BLSP2_AHB_CLK>;
2545			clock-names = "core", "iface";
2546			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2547			dma-names = "tx", "rx";
2548			pinctrl-names = "default", "sleep";
2549			pinctrl-0 = <&blsp2_i2c2_default>;
2550			pinctrl-1 = <&blsp2_i2c2_sleep>;
2551			clock-frequency = <400000>;
2552
2553			status = "disabled";
2554			#address-cells = <1>;
2555			#size-cells = <0>;
2556		};
2557
2558		blsp2_i2c3: i2c@c1b7000 {
2559			compatible = "qcom,i2c-qup-v2.2.1";
2560			reg = <0x0c1b7000 0x600>;
2561			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2562
2563			clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2564				 <&gcc GCC_BLSP2_AHB_CLK>;
2565			clock-names = "core", "iface";
2566			dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2567			dma-names = "tx", "rx";
2568			pinctrl-names = "default", "sleep";
2569			pinctrl-0 = <&blsp2_i2c3_default>;
2570			pinctrl-1 = <&blsp2_i2c3_sleep>;
2571			clock-frequency = <400000>;
2572
2573			status = "disabled";
2574			#address-cells = <1>;
2575			#size-cells = <0>;
2576		};
2577
2578		blsp2_i2c4: i2c@c1b8000 {
2579			compatible = "qcom,i2c-qup-v2.2.1";
2580			reg = <0x0c1b8000 0x600>;
2581			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2582
2583			clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2584				 <&gcc GCC_BLSP2_AHB_CLK>;
2585			clock-names = "core", "iface";
2586			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2587			dma-names = "tx", "rx";
2588			pinctrl-names = "default", "sleep";
2589			pinctrl-0 = <&blsp2_i2c4_default>;
2590			pinctrl-1 = <&blsp2_i2c4_sleep>;
2591			clock-frequency = <400000>;
2592
2593			status = "disabled";
2594			#address-cells = <1>;
2595			#size-cells = <0>;
2596		};
2597
2598		blsp2_i2c5: i2c@c1b9000 {
2599			compatible = "qcom,i2c-qup-v2.2.1";
2600			reg = <0x0c1b9000 0x600>;
2601			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2602
2603			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2604				 <&gcc GCC_BLSP2_AHB_CLK>;
2605			clock-names = "core", "iface";
2606			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2607			dma-names = "tx", "rx";
2608			pinctrl-names = "default", "sleep";
2609			pinctrl-0 = <&blsp2_i2c5_default>;
2610			pinctrl-1 = <&blsp2_i2c5_sleep>;
2611			clock-frequency = <400000>;
2612
2613			status = "disabled";
2614			#address-cells = <1>;
2615			#size-cells = <0>;
2616		};
2617
2618		blsp2_i2c6: i2c@c1ba000 {
2619			compatible = "qcom,i2c-qup-v2.2.1";
2620			reg = <0x0c1ba000 0x600>;
2621			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2622
2623			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2624				 <&gcc GCC_BLSP2_AHB_CLK>;
2625			clock-names = "core", "iface";
2626			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2627			dma-names = "tx", "rx";
2628			pinctrl-names = "default", "sleep";
2629			pinctrl-0 = <&blsp2_i2c6_default>;
2630			pinctrl-1 = <&blsp2_i2c6_sleep>;
2631			clock-frequency = <400000>;
2632
2633			status = "disabled";
2634			#address-cells = <1>;
2635			#size-cells = <0>;
2636		};
2637
2638		blsp2_spi1: spi@c1b5000 {
2639			compatible = "qcom,spi-qup-v2.2.1";
2640			reg = <0x0c1b5000 0x600>;
2641			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2642
2643			clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
2644				 <&gcc GCC_BLSP2_AHB_CLK>;
2645			clock-names = "core", "iface";
2646			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2647			dma-names = "tx", "rx";
2648			pinctrl-names = "default";
2649			pinctrl-0 = <&blsp2_spi1_default>;
2650
2651			status = "disabled";
2652			#address-cells = <1>;
2653			#size-cells = <0>;
2654		};
2655
2656		blsp2_spi2: spi@c1b6000 {
2657			compatible = "qcom,spi-qup-v2.2.1";
2658			reg = <0x0c1b6000 0x600>;
2659			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2660
2661			clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
2662				 <&gcc GCC_BLSP2_AHB_CLK>;
2663			clock-names = "core", "iface";
2664			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2665			dma-names = "tx", "rx";
2666			pinctrl-names = "default";
2667			pinctrl-0 = <&blsp2_spi2_default>;
2668
2669			status = "disabled";
2670			#address-cells = <1>;
2671			#size-cells = <0>;
2672		};
2673
2674		blsp2_spi3: spi@c1b7000 {
2675			compatible = "qcom,spi-qup-v2.2.1";
2676			reg = <0x0c1b7000 0x600>;
2677			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2678
2679			clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
2680				 <&gcc GCC_BLSP2_AHB_CLK>;
2681			clock-names = "core", "iface";
2682			dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2683			dma-names = "tx", "rx";
2684			pinctrl-names = "default";
2685			pinctrl-0 = <&blsp2_spi3_default>;
2686
2687			status = "disabled";
2688			#address-cells = <1>;
2689			#size-cells = <0>;
2690		};
2691
2692		blsp2_spi4: spi@c1b8000 {
2693			compatible = "qcom,spi-qup-v2.2.1";
2694			reg = <0x0c1b8000 0x600>;
2695			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2696
2697			clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
2698				 <&gcc GCC_BLSP2_AHB_CLK>;
2699			clock-names = "core", "iface";
2700			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2701			dma-names = "tx", "rx";
2702			pinctrl-names = "default";
2703			pinctrl-0 = <&blsp2_spi4_default>;
2704
2705			status = "disabled";
2706			#address-cells = <1>;
2707			#size-cells = <0>;
2708		};
2709
2710		blsp2_spi5: spi@c1b9000 {
2711			compatible = "qcom,spi-qup-v2.2.1";
2712			reg = <0x0c1b9000 0x600>;
2713			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2714
2715			clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
2716				 <&gcc GCC_BLSP2_AHB_CLK>;
2717			clock-names = "core", "iface";
2718			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2719			dma-names = "tx", "rx";
2720			pinctrl-names = "default";
2721			pinctrl-0 = <&blsp2_spi5_default>;
2722
2723			status = "disabled";
2724			#address-cells = <1>;
2725			#size-cells = <0>;
2726		};
2727
2728		blsp2_spi6: spi@c1ba000 {
2729			compatible = "qcom,spi-qup-v2.2.1";
2730			reg = <0x0c1ba000 0x600>;
2731			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2732
2733			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2734				 <&gcc GCC_BLSP2_AHB_CLK>;
2735			clock-names = "core", "iface";
2736			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2737			dma-names = "tx", "rx";
2738			pinctrl-names = "default";
2739			pinctrl-0 = <&blsp2_spi6_default>;
2740
2741			status = "disabled";
2742			#address-cells = <1>;
2743			#size-cells = <0>;
2744		};
2745
2746		mmcc: clock-controller@c8c0000 {
2747			compatible = "qcom,mmcc-msm8998";
2748			#clock-cells = <1>;
2749			#reset-cells = <1>;
2750			#power-domain-cells = <1>;
2751			reg = <0xc8c0000 0x40000>;
2752
2753			clock-names = "xo",
2754				      "gpll0",
2755				      "dsi0dsi",
2756				      "dsi0byte",
2757				      "dsi1dsi",
2758				      "dsi1byte",
2759				      "hdmipll",
2760				      "dplink",
2761				      "dpvco",
2762				      "gpll0_div";
2763			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2764				 <&gcc GCC_MMSS_GPLL0_CLK>,
2765				 <&mdss_dsi0_phy 1>,
2766				 <&mdss_dsi0_phy 0>,
2767				 <&mdss_dsi1_phy 1>,
2768				 <&mdss_dsi1_phy 0>,
2769				 <0>,
2770				 <0>,
2771				 <0>,
2772				 <&gcc GCC_MMSS_GPLL0_DIV_CLK>;
2773		};
2774
2775		mdss: display-subsystem@c900000 {
2776			compatible = "qcom,msm8998-mdss";
2777			reg = <0x0c900000 0x1000>;
2778			reg-names = "mdss";
2779
2780			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2781			interrupt-controller;
2782			#interrupt-cells = <1>;
2783
2784			clocks = <&mmcc MDSS_AHB_CLK>,
2785				 <&mmcc MDSS_AXI_CLK>,
2786				 <&mmcc MDSS_MDP_CLK>;
2787			clock-names = "iface",
2788				      "bus",
2789				      "core";
2790
2791			power-domains = <&mmcc MDSS_GDSC>;
2792			iommus = <&mmss_smmu 0>;
2793
2794			#address-cells = <1>;
2795			#size-cells = <1>;
2796			ranges;
2797
2798			status = "disabled";
2799
2800			mdss_mdp: display-controller@c901000 {
2801				compatible = "qcom,msm8998-dpu";
2802				reg = <0x0c901000 0x8f000>,
2803				      <0x0c9a8e00 0xf0>,
2804				      <0x0c9b0000 0x2008>,
2805				      <0x0c9b8000 0x1040>;
2806				reg-names = "mdp",
2807					    "regdma",
2808					    "vbif",
2809					    "vbif_nrt";
2810
2811				interrupt-parent = <&mdss>;
2812				interrupts = <0>;
2813
2814				clocks = <&mmcc MDSS_AHB_CLK>,
2815					 <&mmcc MDSS_AXI_CLK>,
2816					 <&mmcc MNOC_AHB_CLK>,
2817					 <&mmcc MDSS_MDP_CLK>,
2818					 <&mmcc MDSS_VSYNC_CLK>;
2819				clock-names = "iface",
2820					      "bus",
2821					      "mnoc",
2822					      "core",
2823					      "vsync";
2824
2825				assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2826				assigned-clock-rates = <19200000>;
2827
2828				operating-points-v2 = <&mdp_opp_table>;
2829				power-domains = <&rpmpd MSM8998_VDDMX>;
2830
2831				mdp_opp_table: opp-table {
2832					compatible = "operating-points-v2";
2833
2834					opp-171430000 {
2835						opp-hz = /bits/ 64 <171430000>;
2836						required-opps = <&rpmpd_opp_low_svs>;
2837					};
2838
2839					opp-275000000 {
2840						opp-hz = /bits/ 64 <275000000>;
2841						required-opps = <&rpmpd_opp_svs>;
2842					};
2843
2844					opp-330000000 {
2845						opp-hz = /bits/ 64 <330000000>;
2846						required-opps = <&rpmpd_opp_nom>;
2847					};
2848
2849					opp-412500000 {
2850						opp-hz = /bits/ 64 <412500000>;
2851						required-opps = <&rpmpd_opp_turbo>;
2852					};
2853				};
2854
2855				ports {
2856					#address-cells = <1>;
2857					#size-cells = <0>;
2858
2859					port@0 {
2860						reg = <0>;
2861
2862						dpu_intf1_out: endpoint {
2863							remote-endpoint = <&mdss_dsi0_in>;
2864						};
2865					};
2866
2867					port@1 {
2868						reg = <1>;
2869
2870						dpu_intf2_out: endpoint {
2871							remote-endpoint = <&mdss_dsi1_in>;
2872						};
2873					};
2874				};
2875			};
2876
2877			mdss_dsi0: dsi@c994000 {
2878				compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2879				reg = <0x0c994000 0x400>;
2880				reg-names = "dsi_ctrl";
2881
2882				interrupt-parent = <&mdss>;
2883				interrupts = <4>;
2884
2885				clocks = <&mmcc MDSS_BYTE0_CLK>,
2886					 <&mmcc MDSS_BYTE0_INTF_CLK>,
2887					 <&mmcc MDSS_PCLK0_CLK>,
2888					 <&mmcc MDSS_ESC0_CLK>,
2889					 <&mmcc MDSS_AHB_CLK>,
2890					 <&mmcc MDSS_AXI_CLK>;
2891				clock-names = "byte",
2892					      "byte_intf",
2893					      "pixel",
2894					      "core",
2895					      "iface",
2896					      "bus";
2897				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2898						  <&mmcc PCLK0_CLK_SRC>;
2899				assigned-clock-parents = <&mdss_dsi0_phy 0>,
2900							 <&mdss_dsi0_phy 1>;
2901
2902				operating-points-v2 = <&dsi_opp_table>;
2903				power-domains = <&rpmpd MSM8998_VDDCX>;
2904
2905				phys = <&mdss_dsi0_phy>;
2906				phy-names = "dsi";
2907
2908				#address-cells = <1>;
2909				#size-cells = <0>;
2910
2911				status = "disabled";
2912
2913				ports {
2914					#address-cells = <1>;
2915					#size-cells = <0>;
2916
2917					port@0 {
2918						reg = <0>;
2919
2920						mdss_dsi0_in: endpoint {
2921							remote-endpoint = <&dpu_intf1_out>;
2922						};
2923					};
2924
2925					port@1 {
2926						reg = <1>;
2927
2928						mdss_dsi0_out: endpoint {
2929						};
2930					};
2931				};
2932			};
2933
2934			mdss_dsi0_phy: phy@c994400 {
2935				compatible = "qcom,dsi-phy-10nm-8998";
2936				reg = <0x0c994400 0x200>,
2937				      <0x0c994600 0x280>,
2938				      <0x0c994a00 0x1e0>;
2939				reg-names = "dsi_phy",
2940					    "dsi_phy_lane",
2941					    "dsi_pll";
2942
2943				clocks = <&mmcc MDSS_AHB_CLK>,
2944					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2945				clock-names = "iface", "ref";
2946
2947				#clock-cells = <1>;
2948				#phy-cells = <0>;
2949
2950				status = "disabled";
2951			};
2952
2953			mdss_dsi1: dsi@c996000 {
2954				compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2955				reg = <0x0c996000 0x400>;
2956				reg-names = "dsi_ctrl";
2957
2958				interrupt-parent = <&mdss>;
2959				interrupts = <5>;
2960
2961				clocks = <&mmcc MDSS_BYTE1_CLK>,
2962					 <&mmcc MDSS_BYTE1_INTF_CLK>,
2963					 <&mmcc MDSS_PCLK1_CLK>,
2964					 <&mmcc MDSS_ESC1_CLK>,
2965					 <&mmcc MDSS_AHB_CLK>,
2966					 <&mmcc MDSS_AXI_CLK>;
2967				clock-names = "byte",
2968					      "byte_intf",
2969					      "pixel",
2970					      "core",
2971					      "iface",
2972					      "bus";
2973				assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2974						  <&mmcc PCLK1_CLK_SRC>;
2975				assigned-clock-parents = <&mdss_dsi1_phy 0>,
2976							 <&mdss_dsi1_phy 1>;
2977
2978				operating-points-v2 = <&dsi_opp_table>;
2979				power-domains = <&rpmpd MSM8998_VDDCX>;
2980
2981				phys = <&mdss_dsi1_phy>;
2982				phy-names = "dsi";
2983
2984				#address-cells = <1>;
2985				#size-cells = <0>;
2986
2987				status = "disabled";
2988
2989				ports {
2990					#address-cells = <1>;
2991					#size-cells = <0>;
2992
2993					port@0 {
2994						reg = <0>;
2995
2996						mdss_dsi1_in: endpoint {
2997							remote-endpoint = <&dpu_intf2_out>;
2998						};
2999					};
3000
3001					port@1 {
3002						reg = <1>;
3003
3004						mdss_dsi1_out: endpoint {
3005						};
3006					};
3007				};
3008			};
3009
3010			mdss_dsi1_phy: phy@c996400 {
3011				compatible = "qcom,dsi-phy-10nm-8998";
3012				reg = <0x0c996400 0x200>,
3013				      <0x0c996600 0x280>,
3014				      <0x0c996a00 0x10e>;
3015				reg-names = "dsi_phy",
3016					    "dsi_phy_lane",
3017					    "dsi_pll";
3018
3019				clocks = <&mmcc MDSS_AHB_CLK>,
3020					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3021				clock-names = "iface",
3022					      "ref";
3023
3024				#clock-cells = <1>;
3025				#phy-cells = <0>;
3026
3027				status = "disabled";
3028			};
3029		};
3030
3031		venus: video-codec@cc00000 {
3032			compatible = "qcom,msm8998-venus";
3033			reg = <0x0cc00000 0xff000>;
3034			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
3035			power-domains = <&mmcc VIDEO_TOP_GDSC>;
3036			clocks = <&mmcc VIDEO_CORE_CLK>,
3037				 <&mmcc VIDEO_AHB_CLK>,
3038				 <&mmcc VIDEO_AXI_CLK>,
3039				 <&mmcc VIDEO_MAXI_CLK>;
3040			clock-names = "core", "iface", "bus", "mbus";
3041			iommus = <&mmss_smmu 0x400>,
3042				 <&mmss_smmu 0x401>,
3043				 <&mmss_smmu 0x40a>,
3044				 <&mmss_smmu 0x407>,
3045				 <&mmss_smmu 0x40e>,
3046				 <&mmss_smmu 0x40f>,
3047				 <&mmss_smmu 0x408>,
3048				 <&mmss_smmu 0x409>,
3049				 <&mmss_smmu 0x40b>,
3050				 <&mmss_smmu 0x40c>,
3051				 <&mmss_smmu 0x40d>,
3052				 <&mmss_smmu 0x410>,
3053				 <&mmss_smmu 0x421>,
3054				 <&mmss_smmu 0x428>,
3055				 <&mmss_smmu 0x429>,
3056				 <&mmss_smmu 0x42b>,
3057				 <&mmss_smmu 0x42c>,
3058				 <&mmss_smmu 0x42d>,
3059				 <&mmss_smmu 0x411>,
3060				 <&mmss_smmu 0x431>;
3061			memory-region = <&venus_mem>;
3062			status = "disabled";
3063
3064			video-decoder {
3065				compatible = "venus-decoder";
3066				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
3067				clock-names = "core";
3068				power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>;
3069			};
3070
3071			video-encoder {
3072				compatible = "venus-encoder";
3073				clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
3074				clock-names = "core";
3075				power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>;
3076			};
3077		};
3078
3079		mmss_smmu: iommu@cd00000 {
3080			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3081			reg = <0x0cd00000 0x40000>;
3082			#iommu-cells = <1>;
3083
3084			clocks = <&mmcc MNOC_AHB_CLK>,
3085				 <&mmcc BIMC_SMMU_AHB_CLK>,
3086				 <&mmcc BIMC_SMMU_AXI_CLK>;
3087			clock-names = "iface-mm",
3088				      "iface-smmu",
3089				      "bus-smmu";
3090
3091			#global-interrupts = <0>;
3092			interrupts =
3093				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3094				<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3095				<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3096				<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3097				<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3098				<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3099				<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3100				<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
3101				<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3102				<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3103				<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3104				<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
3105				<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3106				<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3107				<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3108				<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3109				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
3110				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3111				<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3112				<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3113
3114			power-domains = <&mmcc BIMC_SMMU_GDSC>;
3115		};
3116
3117		remoteproc_adsp: remoteproc@17300000 {
3118			compatible = "qcom,msm8998-adsp-pas";
3119			reg = <0x17300000 0x4040>;
3120
3121			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3122					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3123					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3124					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3125					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3126			interrupt-names = "wdog", "fatal", "ready",
3127					  "handover", "stop-ack";
3128
3129			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3130			clock-names = "xo";
3131
3132			memory-region = <&adsp_mem>;
3133
3134			qcom,smem-states = <&adsp_smp2p_out 0>;
3135			qcom,smem-state-names = "stop";
3136
3137			power-domains = <&rpmpd MSM8998_VDDCX>;
3138			power-domain-names = "cx";
3139
3140			status = "disabled";
3141
3142			glink-edge {
3143				interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3144				label = "lpass";
3145				qcom,remote-pid = <2>;
3146				mboxes = <&apcs_glb 9>;
3147			};
3148		};
3149
3150		apcs_glb: mailbox@17911000 {
3151			compatible = "qcom,msm8998-apcs-hmss-global",
3152				     "qcom,msm8994-apcs-kpss-global";
3153			reg = <0x17911000 0x1000>;
3154
3155			#mbox-cells = <1>;
3156		};
3157
3158		timer@17920000 {
3159			#address-cells = <1>;
3160			#size-cells = <1>;
3161			ranges;
3162			compatible = "arm,armv7-timer-mem";
3163			reg = <0x17920000 0x1000>;
3164
3165			frame@17921000 {
3166				frame-number = <0>;
3167				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3168					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3169				reg = <0x17921000 0x1000>,
3170				      <0x17922000 0x1000>;
3171			};
3172
3173			frame@17923000 {
3174				frame-number = <1>;
3175				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3176				reg = <0x17923000 0x1000>;
3177				status = "disabled";
3178			};
3179
3180			frame@17924000 {
3181				frame-number = <2>;
3182				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3183				reg = <0x17924000 0x1000>;
3184				status = "disabled";
3185			};
3186
3187			frame@17925000 {
3188				frame-number = <3>;
3189				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3190				reg = <0x17925000 0x1000>;
3191				status = "disabled";
3192			};
3193
3194			frame@17926000 {
3195				frame-number = <4>;
3196				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3197				reg = <0x17926000 0x1000>;
3198				status = "disabled";
3199			};
3200
3201			frame@17927000 {
3202				frame-number = <5>;
3203				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3204				reg = <0x17927000 0x1000>;
3205				status = "disabled";
3206			};
3207
3208			frame@17928000 {
3209				frame-number = <6>;
3210				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3211				reg = <0x17928000 0x1000>;
3212				status = "disabled";
3213			};
3214		};
3215
3216		intc: interrupt-controller@17a00000 {
3217			compatible = "arm,gic-v3";
3218			reg = <0x17a00000 0x10000>,       /* GICD */
3219			      <0x17b00000 0x100000>;      /* GICR * 8 */
3220			#interrupt-cells = <3>;
3221			#address-cells = <1>;
3222			#size-cells = <1>;
3223			ranges;
3224			interrupt-controller;
3225			#redistributor-regions = <1>;
3226			redistributor-stride = <0x0 0x20000>;
3227			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3228		};
3229
3230		wifi: wifi@18800000 {
3231			compatible = "qcom,wcn3990-wifi";
3232			status = "disabled";
3233			reg = <0x18800000 0x800000>;
3234			reg-names = "membase";
3235			memory-region = <&wlan_msa_mem>;
3236			clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3237			clock-names = "cxo_ref_clk_pin";
3238			interrupts =
3239				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3240				<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3241				<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3242				<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3243				<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3244				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3245				<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3246				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3247				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3248				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3249				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3250				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3251			iommus = <&anoc2_smmu 0x1900>,
3252				 <&anoc2_smmu 0x1901>;
3253			qcom,snoc-host-cap-8bit-quirk;
3254			qcom,no-msa-ready-indicator;
3255		};
3256	};
3257};
3258