xref: /linux/arch/arm64/boot/dts/qcom/msm8998.dtsi (revision a3a02a52bcfcbcc4a637d4b68bf1bc391c9fad02) 
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8998.h>
6#include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/firmware/qcom,scm.h>
10#include <dt-bindings/power/qcom-rpmpd.h>
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14	interrupt-parent = <&intc>;
15
16	qcom,msm-id = <292 0x0>;
17
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	chosen { };
22
23	memory@80000000 {
24		device_type = "memory";
25		/* We expect the bootloader to fill in the reg */
26		reg = <0x0 0x80000000 0x0 0x0>;
27	};
28
29	reserved-memory {
30		#address-cells = <2>;
31		#size-cells = <2>;
32		ranges;
33
34		hyp_mem: memory@85800000 {
35			reg = <0x0 0x85800000 0x0 0x600000>;
36			no-map;
37		};
38
39		xbl_mem: memory@85e00000 {
40			reg = <0x0 0x85e00000 0x0 0x100000>;
41			no-map;
42		};
43
44		smem_mem: smem-mem@86000000 {
45			reg = <0x0 0x86000000 0x0 0x200000>;
46			no-map;
47		};
48
49		tz_mem: memory@86200000 {
50			reg = <0x0 0x86200000 0x0 0x2d00000>;
51			no-map;
52		};
53
54		rmtfs_mem: memory@88f00000 {
55			compatible = "qcom,rmtfs-mem";
56			reg = <0x0 0x88f00000 0x0 0x200000>;
57			no-map;
58
59			qcom,client-id = <1>;
60			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
61		};
62
63		spss_mem: memory@8ab00000 {
64			reg = <0x0 0x8ab00000 0x0 0x700000>;
65			no-map;
66		};
67
68		adsp_mem: memory@8b200000 {
69			reg = <0x0 0x8b200000 0x0 0x1a00000>;
70			no-map;
71		};
72
73		mpss_mem: memory@8cc00000 {
74			reg = <0x0 0x8cc00000 0x0 0x7000000>;
75			no-map;
76		};
77
78		venus_mem: memory@93c00000 {
79			reg = <0x0 0x93c00000 0x0 0x500000>;
80			no-map;
81		};
82
83		mba_mem: memory@94100000 {
84			reg = <0x0 0x94100000 0x0 0x200000>;
85			no-map;
86		};
87
88		slpi_mem: memory@94300000 {
89			reg = <0x0 0x94300000 0x0 0xf00000>;
90			no-map;
91		};
92
93		ipa_fw_mem: memory@95200000 {
94			reg = <0x0 0x95200000 0x0 0x10000>;
95			no-map;
96		};
97
98		ipa_gsi_mem: memory@95210000 {
99			reg = <0x0 0x95210000 0x0 0x5000>;
100			no-map;
101		};
102
103		gpu_mem: memory@95600000 {
104			reg = <0x0 0x95600000 0x0 0x100000>;
105			no-map;
106		};
107
108		wlan_msa_mem: memory@95700000 {
109			reg = <0x0 0x95700000 0x0 0x100000>;
110			no-map;
111		};
112
113		mdata_mem: mpss-metadata {
114			alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
115			size = <0x0 0x4000>;
116			no-map;
117		};
118	};
119
120	clocks {
121		xo: xo-board {
122			compatible = "fixed-clock";
123			#clock-cells = <0>;
124			clock-frequency = <19200000>;
125			clock-output-names = "xo_board";
126		};
127
128		sleep_clk: sleep-clk {
129			compatible = "fixed-clock";
130			#clock-cells = <0>;
131			clock-frequency = <32764>;
132		};
133	};
134
135	cpus {
136		#address-cells = <2>;
137		#size-cells = <0>;
138
139		CPU0: cpu@0 {
140			device_type = "cpu";
141			compatible = "qcom,kryo280";
142			reg = <0x0 0x0>;
143			enable-method = "psci";
144			capacity-dmips-mhz = <1024>;
145			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146			next-level-cache = <&L2_0>;
147			L2_0: l2-cache {
148				compatible = "cache";
149				cache-level = <2>;
150				cache-unified;
151			};
152		};
153
154		CPU1: cpu@1 {
155			device_type = "cpu";
156			compatible = "qcom,kryo280";
157			reg = <0x0 0x1>;
158			enable-method = "psci";
159			capacity-dmips-mhz = <1024>;
160			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161			next-level-cache = <&L2_0>;
162		};
163
164		CPU2: cpu@2 {
165			device_type = "cpu";
166			compatible = "qcom,kryo280";
167			reg = <0x0 0x2>;
168			enable-method = "psci";
169			capacity-dmips-mhz = <1024>;
170			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171			next-level-cache = <&L2_0>;
172		};
173
174		CPU3: cpu@3 {
175			device_type = "cpu";
176			compatible = "qcom,kryo280";
177			reg = <0x0 0x3>;
178			enable-method = "psci";
179			capacity-dmips-mhz = <1024>;
180			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181			next-level-cache = <&L2_0>;
182		};
183
184		CPU4: cpu@100 {
185			device_type = "cpu";
186			compatible = "qcom,kryo280";
187			reg = <0x0 0x100>;
188			enable-method = "psci";
189			capacity-dmips-mhz = <1536>;
190			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191			next-level-cache = <&L2_1>;
192			L2_1: l2-cache {
193				compatible = "cache";
194				cache-level = <2>;
195				cache-unified;
196			};
197		};
198
199		CPU5: cpu@101 {
200			device_type = "cpu";
201			compatible = "qcom,kryo280";
202			reg = <0x0 0x101>;
203			enable-method = "psci";
204			capacity-dmips-mhz = <1536>;
205			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206			next-level-cache = <&L2_1>;
207		};
208
209		CPU6: cpu@102 {
210			device_type = "cpu";
211			compatible = "qcom,kryo280";
212			reg = <0x0 0x102>;
213			enable-method = "psci";
214			capacity-dmips-mhz = <1536>;
215			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216			next-level-cache = <&L2_1>;
217		};
218
219		CPU7: cpu@103 {
220			device_type = "cpu";
221			compatible = "qcom,kryo280";
222			reg = <0x0 0x103>;
223			enable-method = "psci";
224			capacity-dmips-mhz = <1536>;
225			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226			next-level-cache = <&L2_1>;
227		};
228
229		cpu-map {
230			cluster0 {
231				core0 {
232					cpu = <&CPU0>;
233				};
234
235				core1 {
236					cpu = <&CPU1>;
237				};
238
239				core2 {
240					cpu = <&CPU2>;
241				};
242
243				core3 {
244					cpu = <&CPU3>;
245				};
246			};
247
248			cluster1 {
249				core0 {
250					cpu = <&CPU4>;
251				};
252
253				core1 {
254					cpu = <&CPU5>;
255				};
256
257				core2 {
258					cpu = <&CPU6>;
259				};
260
261				core3 {
262					cpu = <&CPU7>;
263				};
264			};
265		};
266
267		idle-states {
268			entry-method = "psci";
269
270			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271				compatible = "arm,idle-state";
272				idle-state-name = "little-retention";
273				/* CPU Retention (C2D), L2 Active */
274				arm,psci-suspend-param = <0x00000002>;
275				entry-latency-us = <81>;
276				exit-latency-us = <86>;
277				min-residency-us = <504>;
278			};
279
280			LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281				compatible = "arm,idle-state";
282				idle-state-name = "little-power-collapse";
283				/* CPU + L2 Power Collapse (C3, D4) */
284				arm,psci-suspend-param = <0x40000003>;
285				entry-latency-us = <814>;
286				exit-latency-us = <4562>;
287				min-residency-us = <9183>;
288				local-timer-stop;
289			};
290
291			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292				compatible = "arm,idle-state";
293				idle-state-name = "big-retention";
294				/* CPU Retention (C2D), L2 Active */
295				arm,psci-suspend-param = <0x00000002>;
296				entry-latency-us = <79>;
297				exit-latency-us = <82>;
298				min-residency-us = <1302>;
299			};
300
301			BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302				compatible = "arm,idle-state";
303				idle-state-name = "big-power-collapse";
304				/* CPU + L2 Power Collapse (C3, D4) */
305				arm,psci-suspend-param = <0x40000003>;
306				entry-latency-us = <724>;
307				exit-latency-us = <2027>;
308				min-residency-us = <9419>;
309				local-timer-stop;
310			};
311		};
312	};
313
314	firmware {
315		scm {
316			compatible = "qcom,scm-msm8998", "qcom,scm";
317		};
318	};
319
320	dsi_opp_table: opp-table-dsi {
321		compatible = "operating-points-v2";
322
323		opp-131250000 {
324			opp-hz = /bits/ 64 <131250000>;
325			required-opps = <&rpmpd_opp_low_svs>;
326		};
327
328		opp-210000000 {
329			opp-hz = /bits/ 64 <210000000>;
330			required-opps = <&rpmpd_opp_svs>;
331		};
332
333		opp-312500000 {
334			opp-hz = /bits/ 64 <312500000>;
335			required-opps = <&rpmpd_opp_nom>;
336		};
337	};
338
339	psci {
340		compatible = "arm,psci-1.0";
341		method = "smc";
342	};
343
344	rpm: remoteproc {
345		compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
346
347		glink-edge {
348			compatible = "qcom,glink-rpm";
349
350			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
351			qcom,rpm-msg-ram = <&rpm_msg_ram>;
352			mboxes = <&apcs_glb 0>;
353
354			rpm_requests: rpm-requests {
355				compatible = "qcom,rpm-msm8998";
356				qcom,glink-channels = "rpm_requests";
357
358				rpmcc: clock-controller {
359					compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
360					clocks = <&xo>;
361					clock-names = "xo";
362					#clock-cells = <1>;
363				};
364
365				rpmpd: power-controller {
366					compatible = "qcom,msm8998-rpmpd";
367					#power-domain-cells = <1>;
368					operating-points-v2 = <&rpmpd_opp_table>;
369
370					rpmpd_opp_table: opp-table {
371						compatible = "operating-points-v2";
372
373						rpmpd_opp_ret: opp1 {
374							opp-level = <RPM_SMD_LEVEL_RETENTION>;
375						};
376
377						rpmpd_opp_ret_plus: opp2 {
378							opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
379						};
380
381						rpmpd_opp_min_svs: opp3 {
382							opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
383						};
384
385						rpmpd_opp_low_svs: opp4 {
386							opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
387						};
388
389						rpmpd_opp_svs: opp5 {
390							opp-level = <RPM_SMD_LEVEL_SVS>;
391						};
392
393						rpmpd_opp_svs_plus: opp6 {
394							opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
395						};
396
397						rpmpd_opp_nom: opp7 {
398							opp-level = <RPM_SMD_LEVEL_NOM>;
399						};
400
401						rpmpd_opp_nom_plus: opp8 {
402							opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
403						};
404
405						rpmpd_opp_turbo: opp9 {
406							opp-level = <RPM_SMD_LEVEL_TURBO>;
407						};
408
409						rpmpd_opp_turbo_plus: opp10 {
410							opp-level = <RPM_SMD_LEVEL_BINNING>;
411						};
412					};
413				};
414			};
415		};
416	};
417
418	smem {
419		compatible = "qcom,smem";
420		memory-region = <&smem_mem>;
421		hwlocks = <&tcsr_mutex 3>;
422	};
423
424	smp2p-lpass {
425		compatible = "qcom,smp2p";
426		qcom,smem = <443>, <429>;
427
428		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429
430		mboxes = <&apcs_glb 10>;
431
432		qcom,local-pid = <0>;
433		qcom,remote-pid = <2>;
434
435		adsp_smp2p_out: master-kernel {
436			qcom,entry-name = "master-kernel";
437			#qcom,smem-state-cells = <1>;
438		};
439
440		adsp_smp2p_in: slave-kernel {
441			qcom,entry-name = "slave-kernel";
442
443			interrupt-controller;
444			#interrupt-cells = <2>;
445		};
446	};
447
448	smp2p-mpss {
449		compatible = "qcom,smp2p";
450		qcom,smem = <435>, <428>;
451		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452		mboxes = <&apcs_glb 14>;
453		qcom,local-pid = <0>;
454		qcom,remote-pid = <1>;
455
456		modem_smp2p_out: master-kernel {
457			qcom,entry-name = "master-kernel";
458			#qcom,smem-state-cells = <1>;
459		};
460
461		modem_smp2p_in: slave-kernel {
462			qcom,entry-name = "slave-kernel";
463			interrupt-controller;
464			#interrupt-cells = <2>;
465		};
466	};
467
468	smp2p-slpi {
469		compatible = "qcom,smp2p";
470		qcom,smem = <481>, <430>;
471		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472		mboxes = <&apcs_glb 26>;
473		qcom,local-pid = <0>;
474		qcom,remote-pid = <3>;
475
476		slpi_smp2p_out: master-kernel {
477			qcom,entry-name = "master-kernel";
478			#qcom,smem-state-cells = <1>;
479		};
480
481		slpi_smp2p_in: slave-kernel {
482			qcom,entry-name = "slave-kernel";
483			interrupt-controller;
484			#interrupt-cells = <2>;
485		};
486	};
487
488	thermal-zones {
489		cpu0-thermal {
490			polling-delay-passive = <250>;
491
492			thermal-sensors = <&tsens0 1>;
493
494			trips {
495				cpu0_alert0: trip-point0 {
496					temperature = <75000>;
497					hysteresis = <2000>;
498					type = "passive";
499				};
500
501				cpu0_crit: cpu-crit {
502					temperature = <110000>;
503					hysteresis = <2000>;
504					type = "critical";
505				};
506			};
507		};
508
509		cpu1-thermal {
510			polling-delay-passive = <250>;
511
512			thermal-sensors = <&tsens0 2>;
513
514			trips {
515				cpu1_alert0: trip-point0 {
516					temperature = <75000>;
517					hysteresis = <2000>;
518					type = "passive";
519				};
520
521				cpu1_crit: cpu-crit {
522					temperature = <110000>;
523					hysteresis = <2000>;
524					type = "critical";
525				};
526			};
527		};
528
529		cpu2-thermal {
530			polling-delay-passive = <250>;
531
532			thermal-sensors = <&tsens0 3>;
533
534			trips {
535				cpu2_alert0: trip-point0 {
536					temperature = <75000>;
537					hysteresis = <2000>;
538					type = "passive";
539				};
540
541				cpu2_crit: cpu-crit {
542					temperature = <110000>;
543					hysteresis = <2000>;
544					type = "critical";
545				};
546			};
547		};
548
549		cpu3-thermal {
550			polling-delay-passive = <250>;
551
552			thermal-sensors = <&tsens0 4>;
553
554			trips {
555				cpu3_alert0: trip-point0 {
556					temperature = <75000>;
557					hysteresis = <2000>;
558					type = "passive";
559				};
560
561				cpu3_crit: cpu-crit {
562					temperature = <110000>;
563					hysteresis = <2000>;
564					type = "critical";
565				};
566			};
567		};
568
569		cpu4-thermal {
570			polling-delay-passive = <250>;
571
572			thermal-sensors = <&tsens0 7>;
573
574			trips {
575				cpu4_alert0: trip-point0 {
576					temperature = <75000>;
577					hysteresis = <2000>;
578					type = "passive";
579				};
580
581				cpu4_crit: cpu-crit {
582					temperature = <110000>;
583					hysteresis = <2000>;
584					type = "critical";
585				};
586			};
587		};
588
589		cpu5-thermal {
590			polling-delay-passive = <250>;
591
592			thermal-sensors = <&tsens0 8>;
593
594			trips {
595				cpu5_alert0: trip-point0 {
596					temperature = <75000>;
597					hysteresis = <2000>;
598					type = "passive";
599				};
600
601				cpu5_crit: cpu-crit {
602					temperature = <110000>;
603					hysteresis = <2000>;
604					type = "critical";
605				};
606			};
607		};
608
609		cpu6-thermal {
610			polling-delay-passive = <250>;
611
612			thermal-sensors = <&tsens0 9>;
613
614			trips {
615				cpu6_alert0: trip-point0 {
616					temperature = <75000>;
617					hysteresis = <2000>;
618					type = "passive";
619				};
620
621				cpu6_crit: cpu-crit {
622					temperature = <110000>;
623					hysteresis = <2000>;
624					type = "critical";
625				};
626			};
627		};
628
629		cpu7-thermal {
630			polling-delay-passive = <250>;
631
632			thermal-sensors = <&tsens0 10>;
633
634			trips {
635				cpu7_alert0: trip-point0 {
636					temperature = <75000>;
637					hysteresis = <2000>;
638					type = "passive";
639				};
640
641				cpu7_crit: cpu-crit {
642					temperature = <110000>;
643					hysteresis = <2000>;
644					type = "critical";
645				};
646			};
647		};
648
649		gpu-bottom-thermal {
650			polling-delay-passive = <250>;
651
652			thermal-sensors = <&tsens0 12>;
653
654			trips {
655				gpu1_alert0: trip-point0 {
656					temperature = <90000>;
657					hysteresis = <2000>;
658					type = "hot";
659				};
660			};
661		};
662
663		gpu-top-thermal {
664			polling-delay-passive = <250>;
665
666			thermal-sensors = <&tsens0 13>;
667
668			trips {
669				gpu2_alert0: trip-point0 {
670					temperature = <90000>;
671					hysteresis = <2000>;
672					type = "hot";
673				};
674			};
675		};
676
677		clust0-mhm-thermal {
678			polling-delay-passive = <250>;
679
680			thermal-sensors = <&tsens0 5>;
681
682			trips {
683				cluster0_mhm_alert0: trip-point0 {
684					temperature = <90000>;
685					hysteresis = <2000>;
686					type = "hot";
687				};
688			};
689		};
690
691		clust1-mhm-thermal {
692			polling-delay-passive = <250>;
693
694			thermal-sensors = <&tsens0 6>;
695
696			trips {
697				cluster1_mhm_alert0: trip-point0 {
698					temperature = <90000>;
699					hysteresis = <2000>;
700					type = "hot";
701				};
702			};
703		};
704
705		cluster1-l2-thermal {
706			polling-delay-passive = <250>;
707
708			thermal-sensors = <&tsens0 11>;
709
710			trips {
711				cluster1_l2_alert0: trip-point0 {
712					temperature = <90000>;
713					hysteresis = <2000>;
714					type = "hot";
715				};
716			};
717		};
718
719		modem-thermal {
720			polling-delay-passive = <250>;
721
722			thermal-sensors = <&tsens1 1>;
723
724			trips {
725				modem_alert0: trip-point0 {
726					temperature = <90000>;
727					hysteresis = <2000>;
728					type = "hot";
729				};
730			};
731		};
732
733		mem-thermal {
734			polling-delay-passive = <250>;
735
736			thermal-sensors = <&tsens1 2>;
737
738			trips {
739				mem_alert0: trip-point0 {
740					temperature = <90000>;
741					hysteresis = <2000>;
742					type = "hot";
743				};
744			};
745		};
746
747		wlan-thermal {
748			polling-delay-passive = <250>;
749
750			thermal-sensors = <&tsens1 3>;
751
752			trips {
753				wlan_alert0: trip-point0 {
754					temperature = <90000>;
755					hysteresis = <2000>;
756					type = "hot";
757				};
758			};
759		};
760
761		q6-dsp-thermal {
762			polling-delay-passive = <250>;
763
764			thermal-sensors = <&tsens1 4>;
765
766			trips {
767				q6_dsp_alert0: trip-point0 {
768					temperature = <90000>;
769					hysteresis = <2000>;
770					type = "hot";
771				};
772			};
773		};
774
775		camera-thermal {
776			polling-delay-passive = <250>;
777
778			thermal-sensors = <&tsens1 5>;
779
780			trips {
781				camera_alert0: trip-point0 {
782					temperature = <90000>;
783					hysteresis = <2000>;
784					type = "hot";
785				};
786			};
787		};
788
789		multimedia-thermal {
790			polling-delay-passive = <250>;
791
792			thermal-sensors = <&tsens1 6>;
793
794			trips {
795				multimedia_alert0: trip-point0 {
796					temperature = <90000>;
797					hysteresis = <2000>;
798					type = "hot";
799				};
800			};
801		};
802	};
803
804	timer {
805		compatible = "arm,armv8-timer";
806		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
807			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
808			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
809			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
810	};
811
812	soc: soc@0 {
813		#address-cells = <1>;
814		#size-cells = <1>;
815		ranges = <0 0 0 0xffffffff>;
816		compatible = "simple-bus";
817
818		gcc: clock-controller@100000 {
819			compatible = "qcom,gcc-msm8998";
820			#clock-cells = <1>;
821			#reset-cells = <1>;
822			#power-domain-cells = <1>;
823			reg = <0x00100000 0xb0000>;
824
825			clock-names = "xo", "sleep_clk";
826			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
827
828			/*
829			 * The hypervisor typically configures the memory region where these clocks
830			 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
831			 * these clocks on a device with such configuration (e.g. because they are
832			 * enabled but unused during boot-up), the device will most likely decide
833			 * to reboot.
834			 * In light of that, we are conservative here and we list all such clocks
835			 * as protected. The board dts (or a user-supplied dts) can override the
836			 * list of protected clocks if it differs from the norm, and it is in fact
837			 * desired for the HLOS to manage these clocks
838			 */
839			protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
840					   <SSC_XO>,
841					   <SSC_CNOC_AHBS_CLK>;
842		};
843
844		rpm_msg_ram: sram@778000 {
845			compatible = "qcom,rpm-msg-ram";
846			reg = <0x00778000 0x7000>;
847		};
848
849		qfprom: qfprom@784000 {
850			compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
851			reg = <0x00784000 0x621c>;
852			#address-cells = <1>;
853			#size-cells = <1>;
854
855			qusb2_hstx_trim: hstx-trim@23a {
856				reg = <0x23a 0x1>;
857				bits = <0 4>;
858			};
859		};
860
861		tsens0: thermal@10ab000 {
862			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
863			reg = <0x010ab000 0x1000>, /* TM */
864			      <0x010aa000 0x1000>; /* SROT */
865			#qcom,sensors = <14>;
866			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
867				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
868			interrupt-names = "uplow", "critical";
869			#thermal-sensor-cells = <1>;
870		};
871
872		tsens1: thermal@10ae000 {
873			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
874			reg = <0x010ae000 0x1000>, /* TM */
875			      <0x010ad000 0x1000>; /* SROT */
876			#qcom,sensors = <8>;
877			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
878				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
879			interrupt-names = "uplow", "critical";
880			#thermal-sensor-cells = <1>;
881		};
882
883		anoc1_smmu: iommu@1680000 {
884			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
885			reg = <0x01680000 0x10000>;
886			#iommu-cells = <1>;
887
888			#global-interrupts = <0>;
889			interrupts =
890				<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
891				<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
892				<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
893				<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
894				<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
895				<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
896		};
897
898		anoc2_smmu: iommu@16c0000 {
899			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
900			reg = <0x016c0000 0x40000>;
901			#iommu-cells = <1>;
902
903			#global-interrupts = <0>;
904			interrupts =
905				<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
906				<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
907				<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
908				<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
909				<GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
910				<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
911				<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
912				<GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
913				<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
914				<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
915		};
916
917		pcie0: pcie@1c00000 {
918			compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
919			reg = <0x01c00000 0x2000>,
920			      <0x1b000000 0xf1d>,
921			      <0x1b000f20 0xa8>,
922			      <0x1b100000 0x100000>;
923			reg-names = "parf", "dbi", "elbi", "config";
924			device_type = "pci";
925			linux,pci-domain = <0>;
926			bus-range = <0x00 0xff>;
927			#address-cells = <3>;
928			#size-cells = <2>;
929			num-lanes = <1>;
930			phys = <&pcie_phy>;
931			phy-names = "pciephy";
932			status = "disabled";
933
934			ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
935				 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
936
937			#interrupt-cells = <1>;
938			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
939			interrupt-names = "msi";
940			interrupt-map-mask = <0 0 0 0x7>;
941			interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
942					<0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
943					<0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
944					<0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
945
946			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
947				 <&gcc GCC_PCIE_0_AUX_CLK>,
948				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
949				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
950				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
951			clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
952
953			power-domains = <&gcc PCIE_0_GDSC>;
954			iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
955			perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
956
957			pcie@0 {
958				device_type = "pci";
959				reg = <0x0 0x0 0x0 0x0 0x0>;
960				bus-range = <0x01 0xff>;
961
962				#address-cells = <3>;
963				#size-cells = <2>;
964				ranges;
965			};
966		};
967
968		pcie_phy: phy@1c06000 {
969			compatible = "qcom,msm8998-qmp-pcie-phy";
970			reg = <0x01c06000 0x1000>;
971			status = "disabled";
972
973			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
974				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
975				 <&gcc GCC_PCIE_CLKREF_CLK>,
976				 <&gcc GCC_PCIE_0_PIPE_CLK>;
977			clock-names = "aux",
978				      "cfg_ahb",
979				      "ref",
980				      "pipe";
981
982			clock-output-names = "pcie_0_pipe_clk_src";
983			#clock-cells = <0>;
984
985			#phy-cells = <0>;
986
987			resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
988			reset-names = "phy", "common";
989
990			vdda-phy-supply = <&vreg_l1a_0p875>;
991			vdda-pll-supply = <&vreg_l2a_1p2>;
992		};
993
994		ufshc: ufshc@1da4000 {
995			compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
996			reg = <0x01da4000 0x2500>;
997			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
998			phys = <&ufsphy>;
999			phy-names = "ufsphy";
1000			lanes-per-direction = <2>;
1001			power-domains = <&gcc UFS_GDSC>;
1002			status = "disabled";
1003			#reset-cells = <1>;
1004
1005			clock-names =
1006				"core_clk",
1007				"bus_aggr_clk",
1008				"iface_clk",
1009				"core_clk_unipro",
1010				"ref_clk",
1011				"tx_lane0_sync_clk",
1012				"rx_lane0_sync_clk",
1013				"rx_lane1_sync_clk";
1014			clocks =
1015				<&gcc GCC_UFS_AXI_CLK>,
1016				<&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1017				<&gcc GCC_UFS_AHB_CLK>,
1018				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1019				<&rpmcc RPM_SMD_LN_BB_CLK1>,
1020				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1021				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1022				<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1023			freq-table-hz =
1024				<50000000 200000000>,
1025				<0 0>,
1026				<0 0>,
1027				<37500000 150000000>,
1028				<0 0>,
1029				<0 0>,
1030				<0 0>,
1031				<0 0>;
1032
1033			resets = <&gcc GCC_UFS_BCR>;
1034			reset-names = "rst";
1035		};
1036
1037		ufsphy: phy@1da7000 {
1038			compatible = "qcom,msm8998-qmp-ufs-phy";
1039			reg = <0x01da7000 0x1000>;
1040
1041			clocks = <&rpmcc RPM_SMD_LN_BB_CLK1>,
1042				 <&gcc GCC_UFS_PHY_AUX_CLK>,
1043				 <&gcc GCC_UFS_CLKREF_CLK>;
1044			clock-names = "ref",
1045				      "ref_aux",
1046				      "qref";
1047
1048			reset-names = "ufsphy";
1049			resets = <&ufshc 0>;
1050
1051			#phy-cells = <0>;
1052			status = "disabled";
1053		};
1054
1055		tcsr_mutex: hwlock@1f40000 {
1056			compatible = "qcom,tcsr-mutex";
1057			reg = <0x01f40000 0x20000>;
1058			#hwlock-cells = <1>;
1059		};
1060
1061		tcsr_regs_1: syscon@1f60000 {
1062			compatible = "qcom,msm8998-tcsr", "syscon";
1063			reg = <0x01f60000 0x20000>;
1064		};
1065
1066		tcsr_regs_2: syscon@1fc0000 {
1067			compatible = "qcom,msm8998-tcsr", "syscon";
1068			reg = <0x01fc0000 0x26000>;
1069		};
1070
1071		tlmm: pinctrl@3400000 {
1072			compatible = "qcom,msm8998-pinctrl";
1073			reg = <0x03400000 0xc00000>;
1074			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1075			gpio-ranges = <&tlmm 0 0 150>;
1076			gpio-controller;
1077			#gpio-cells = <2>;
1078			interrupt-controller;
1079			#interrupt-cells = <2>;
1080
1081			sdc2_on: sdc2-on-state {
1082				clk-pins {
1083					pins = "sdc2_clk";
1084					drive-strength = <16>;
1085					bias-disable;
1086				};
1087
1088				cmd-pins {
1089					pins = "sdc2_cmd";
1090					drive-strength = <10>;
1091					bias-pull-up;
1092				};
1093
1094				data-pins {
1095					pins = "sdc2_data";
1096					drive-strength = <10>;
1097					bias-pull-up;
1098				};
1099			};
1100
1101			sdc2_off: sdc2-off-state {
1102				clk-pins {
1103					pins = "sdc2_clk";
1104					drive-strength = <2>;
1105					bias-disable;
1106				};
1107
1108				cmd-pins {
1109					pins = "sdc2_cmd";
1110					drive-strength = <2>;
1111					bias-pull-up;
1112				};
1113
1114				data-pins {
1115					pins = "sdc2_data";
1116					drive-strength = <2>;
1117					bias-pull-up;
1118				};
1119			};
1120
1121			sdc2_cd: sdc2-cd-state {
1122				pins = "gpio95";
1123				function = "gpio";
1124				bias-pull-up;
1125				drive-strength = <2>;
1126			};
1127
1128			blsp1_uart3_on: blsp1-uart3-on-state {
1129				tx-pins {
1130					pins = "gpio45";
1131					function = "blsp_uart3_a";
1132					drive-strength = <2>;
1133					bias-disable;
1134				};
1135
1136				rx-pins {
1137					pins = "gpio46";
1138					function = "blsp_uart3_a";
1139					drive-strength = <2>;
1140					bias-disable;
1141				};
1142
1143				cts-pins {
1144					pins = "gpio47";
1145					function = "blsp_uart3_a";
1146					drive-strength = <2>;
1147					bias-disable;
1148				};
1149
1150				rfr-pins {
1151					pins = "gpio48";
1152					function = "blsp_uart3_a";
1153					drive-strength = <2>;
1154					bias-disable;
1155				};
1156			};
1157
1158			blsp1_i2c1_default: blsp1-i2c1-default-state {
1159				pins = "gpio2", "gpio3";
1160				function = "blsp_i2c1";
1161				drive-strength = <2>;
1162				bias-disable;
1163			};
1164
1165			blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1166				pins = "gpio2", "gpio3";
1167				function = "blsp_i2c1";
1168				drive-strength = <2>;
1169				bias-pull-up;
1170			};
1171
1172			blsp1_i2c2_default: blsp1-i2c2-default-state {
1173				pins = "gpio32", "gpio33";
1174				function = "blsp_i2c2";
1175				drive-strength = <2>;
1176				bias-disable;
1177			};
1178
1179			blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1180				pins = "gpio32", "gpio33";
1181				function = "blsp_i2c2";
1182				drive-strength = <2>;
1183				bias-pull-up;
1184			};
1185
1186			blsp1_i2c3_default: blsp1-i2c3-default-state {
1187				pins = "gpio47", "gpio48";
1188				function = "blsp_i2c3";
1189				drive-strength = <2>;
1190				bias-disable;
1191			};
1192
1193			blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1194				pins = "gpio47", "gpio48";
1195				function = "blsp_i2c3";
1196				drive-strength = <2>;
1197				bias-pull-up;
1198			};
1199
1200			blsp1_i2c4_default: blsp1-i2c4-default-state {
1201				pins = "gpio10", "gpio11";
1202				function = "blsp_i2c4";
1203				drive-strength = <2>;
1204				bias-disable;
1205			};
1206
1207			blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1208				pins = "gpio10", "gpio11";
1209				function = "blsp_i2c4";
1210				drive-strength = <2>;
1211				bias-pull-up;
1212			};
1213
1214			blsp1_i2c5_default: blsp1-i2c5-default-state {
1215				pins = "gpio87", "gpio88";
1216				function = "blsp_i2c5";
1217				drive-strength = <2>;
1218				bias-disable;
1219			};
1220
1221			blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1222				pins = "gpio87", "gpio88";
1223				function = "blsp_i2c5";
1224				drive-strength = <2>;
1225				bias-pull-up;
1226			};
1227
1228			blsp1_i2c6_default: blsp1-i2c6-default-state {
1229				pins = "gpio43", "gpio44";
1230				function = "blsp_i2c6";
1231				drive-strength = <2>;
1232				bias-disable;
1233			};
1234
1235			blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1236				pins = "gpio43", "gpio44";
1237				function = "blsp_i2c6";
1238				drive-strength = <2>;
1239				bias-pull-up;
1240			};
1241
1242			blsp1_spi_b_default: blsp1-spi-b-default-state {
1243				pins = "gpio23", "gpio28";
1244				function = "blsp1_spi_b";
1245				drive-strength = <6>;
1246				bias-disable;
1247			};
1248
1249			blsp1_spi1_default: blsp1-spi1-default-state {
1250				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1251				function = "blsp_spi1";
1252				drive-strength = <6>;
1253				bias-disable;
1254			};
1255
1256			blsp1_spi2_default: blsp1-spi2-default-state {
1257				pins = "gpio31", "gpio34", "gpio32", "gpio33";
1258				function = "blsp_spi2";
1259				drive-strength = <6>;
1260				bias-disable;
1261			};
1262
1263			blsp1_spi3_default: blsp1-spi3-default-state {
1264				pins = "gpio45", "gpio46", "gpio47", "gpio48";
1265				function = "blsp_spi2";
1266				drive-strength = <6>;
1267				bias-disable;
1268			};
1269
1270			blsp1_spi4_default: blsp1-spi4-default-state {
1271				pins = "gpio8", "gpio9", "gpio10", "gpio11";
1272				function = "blsp_spi4";
1273				drive-strength = <6>;
1274				bias-disable;
1275			};
1276
1277			blsp1_spi5_default: blsp1-spi5-default-state {
1278				pins = "gpio85", "gpio86", "gpio87", "gpio88";
1279				function = "blsp_spi5";
1280				drive-strength = <6>;
1281				bias-disable;
1282			};
1283
1284			blsp1_spi6_default: blsp1-spi6-default-state {
1285				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1286				function = "blsp_spi6";
1287				drive-strength = <6>;
1288				bias-disable;
1289			};
1290
1291
1292			/* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1293			blsp2_i2c1_default: blsp2-i2c1-default-state {
1294				pins = "gpio55", "gpio56";
1295				function = "blsp_i2c7";
1296				drive-strength = <2>;
1297				bias-disable;
1298			};
1299
1300			blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1301				pins = "gpio55", "gpio56";
1302				function = "blsp_i2c7";
1303				drive-strength = <2>;
1304				bias-pull-up;
1305			};
1306
1307			blsp2_i2c2_default: blsp2-i2c2-default-state {
1308				pins = "gpio6", "gpio7";
1309				function = "blsp_i2c8";
1310				drive-strength = <2>;
1311				bias-disable;
1312			};
1313
1314			blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1315				pins = "gpio6", "gpio7";
1316				function = "blsp_i2c8";
1317				drive-strength = <2>;
1318				bias-pull-up;
1319			};
1320
1321			blsp2_i2c3_default: blsp2-i2c3-default-state {
1322				pins = "gpio51", "gpio52";
1323				function = "blsp_i2c9";
1324				drive-strength = <2>;
1325				bias-disable;
1326			};
1327
1328			blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1329				pins = "gpio51", "gpio52";
1330				function = "blsp_i2c9";
1331				drive-strength = <2>;
1332				bias-pull-up;
1333			};
1334
1335			blsp2_i2c4_default: blsp2-i2c4-default-state {
1336				pins = "gpio67", "gpio68";
1337				function = "blsp_i2c10";
1338				drive-strength = <2>;
1339				bias-disable;
1340			};
1341
1342			blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1343				pins = "gpio67", "gpio68";
1344				function = "blsp_i2c10";
1345				drive-strength = <2>;
1346				bias-pull-up;
1347			};
1348
1349			blsp2_i2c5_default: blsp2-i2c5-default-state {
1350				pins = "gpio60", "gpio61";
1351				function = "blsp_i2c11";
1352				drive-strength = <2>;
1353				bias-disable;
1354			};
1355
1356			blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1357				pins = "gpio60", "gpio61";
1358				function = "blsp_i2c11";
1359				drive-strength = <2>;
1360				bias-pull-up;
1361			};
1362
1363			blsp2_i2c6_default: blsp2-i2c6-default-state {
1364				pins = "gpio83", "gpio84";
1365				function = "blsp_i2c12";
1366				drive-strength = <2>;
1367				bias-disable;
1368			};
1369
1370			blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1371				pins = "gpio83", "gpio84";
1372				function = "blsp_i2c12";
1373				drive-strength = <2>;
1374				bias-pull-up;
1375			};
1376
1377			blsp2_spi1_default: blsp2-spi1-default-state {
1378				pins = "gpio53", "gpio54", "gpio55", "gpio56";
1379				function = "blsp_spi7";
1380				drive-strength = <6>;
1381				bias-disable;
1382			};
1383
1384			blsp2_spi2_default: blsp2-spi2-default-state {
1385				pins = "gpio4", "gpio5", "gpio6", "gpio7";
1386				function = "blsp_spi8";
1387				drive-strength = <6>;
1388				bias-disable;
1389			};
1390
1391			blsp2_spi3_default: blsp2-spi3-default-state {
1392				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1393				function = "blsp_spi9";
1394				drive-strength = <6>;
1395				bias-disable;
1396			};
1397
1398			blsp2_spi4_default: blsp2-spi4-default-state {
1399				pins = "gpio65", "gpio66", "gpio67", "gpio68";
1400				function = "blsp_spi10";
1401				drive-strength = <6>;
1402				bias-disable;
1403			};
1404
1405			blsp2_spi5_default: blsp2-spi5-default-state {
1406				pins = "gpio58", "gpio59", "gpio60", "gpio61";
1407				function = "blsp_spi11";
1408				drive-strength = <6>;
1409				bias-disable;
1410			};
1411
1412			blsp2_spi6_default: blsp2-spi6-default-state {
1413				pins = "gpio81", "gpio82", "gpio83", "gpio84";
1414				function = "blsp_spi12";
1415				drive-strength = <6>;
1416				bias-disable;
1417			};
1418		};
1419
1420		remoteproc_mss: remoteproc@4080000 {
1421			compatible = "qcom,msm8998-mss-pil";
1422			reg = <0x04080000 0x100>, <0x04180000 0x20>;
1423			reg-names = "qdsp6", "rmb";
1424
1425			interrupts-extended =
1426				<&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1427				<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1428				<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1429				<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1430				<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1431				<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1432			interrupt-names = "wdog", "fatal", "ready",
1433					  "handover", "stop-ack",
1434					  "shutdown-ack";
1435
1436			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1437				 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1438				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1439				 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1440				 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1441				 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1442				 <&rpmcc RPM_SMD_QDSS_CLK>,
1443				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1444			clock-names = "iface", "bus", "mem", "gpll0_mss",
1445				      "snoc_axi", "mnoc_axi", "qdss", "xo";
1446
1447			qcom,smem-states = <&modem_smp2p_out 0>;
1448			qcom,smem-state-names = "stop";
1449
1450			resets = <&gcc GCC_MSS_RESTART>;
1451			reset-names = "mss_restart";
1452
1453			qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1454
1455			power-domains = <&rpmpd MSM8998_VDDCX>,
1456					<&rpmpd MSM8998_VDDMX>;
1457			power-domain-names = "cx", "mx";
1458
1459			status = "disabled";
1460
1461			mba {
1462				memory-region = <&mba_mem>;
1463			};
1464
1465			mpss {
1466				memory-region = <&mpss_mem>;
1467			};
1468
1469			metadata {
1470				memory-region = <&mdata_mem>;
1471			};
1472
1473			glink-edge {
1474				interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1475				label = "modem";
1476				qcom,remote-pid = <1>;
1477				mboxes = <&apcs_glb 15>;
1478			};
1479		};
1480
1481		adreno_gpu: gpu@5000000 {
1482			compatible = "qcom,adreno-540.1", "qcom,adreno";
1483			reg = <0x05000000 0x40000>;
1484			reg-names = "kgsl_3d0_reg_memory";
1485
1486			clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1487				<&gpucc RBBMTIMER_CLK>,
1488				<&gcc GCC_BIMC_GFX_CLK>,
1489				<&gcc GCC_GPU_BIMC_GFX_CLK>,
1490				<&gpucc RBCPR_CLK>,
1491				<&gpucc GFX3D_CLK>;
1492			clock-names = "iface",
1493				"rbbmtimer",
1494				"mem",
1495				"mem_iface",
1496				"rbcpr",
1497				"core";
1498
1499			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1500			iommus = <&adreno_smmu 0>;
1501			operating-points-v2 = <&gpu_opp_table>;
1502			power-domains = <&rpmpd MSM8998_VDDMX>;
1503			status = "disabled";
1504
1505			gpu_opp_table: opp-table {
1506				compatible = "operating-points-v2";
1507				opp-710000097 {
1508					opp-hz = /bits/ 64 <710000097>;
1509					opp-level = <RPM_SMD_LEVEL_TURBO>;
1510					opp-supported-hw = <0xff>;
1511				};
1512
1513				opp-670000048 {
1514					opp-hz = /bits/ 64 <670000048>;
1515					opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1516					opp-supported-hw = <0xff>;
1517				};
1518
1519				opp-596000097 {
1520					opp-hz = /bits/ 64 <596000097>;
1521					opp-level = <RPM_SMD_LEVEL_NOM>;
1522					opp-supported-hw = <0xff>;
1523				};
1524
1525				opp-515000097 {
1526					opp-hz = /bits/ 64 <515000097>;
1527					opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1528					opp-supported-hw = <0xff>;
1529				};
1530
1531				opp-414000000 {
1532					opp-hz = /bits/ 64 <414000000>;
1533					opp-level = <RPM_SMD_LEVEL_SVS>;
1534					opp-supported-hw = <0xff>;
1535				};
1536
1537				opp-342000000 {
1538					opp-hz = /bits/ 64 <342000000>;
1539					opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1540					opp-supported-hw = <0xff>;
1541				};
1542
1543				opp-257000000 {
1544					opp-hz = /bits/ 64 <257000000>;
1545					opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1546					opp-supported-hw = <0xff>;
1547				};
1548			};
1549		};
1550
1551		adreno_smmu: iommu@5040000 {
1552			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1553			reg = <0x05040000 0x10000>;
1554			clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1555				 <&gcc GCC_BIMC_GFX_CLK>,
1556				 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1557			clock-names = "iface", "mem", "mem_iface";
1558
1559			#global-interrupts = <0>;
1560			#iommu-cells = <1>;
1561			interrupts =
1562				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1563				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1564				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1565			/*
1566			 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1567			 * GPU-CX for SMMU but we need both of them up for Adreno.
1568			 * Contemporarily, we also need to manage the VDDMX rpmpd
1569			 * domain in the Adreno driver.
1570			 * Enable GPU CX/GX GDSCs here so that we can manage the
1571			 * SoC VDDMX RPM Power Domain in the Adreno driver.
1572			 */
1573			power-domains = <&gpucc GPU_GX_GDSC>;
1574		};
1575
1576		gpucc: clock-controller@5065000 {
1577			compatible = "qcom,msm8998-gpucc";
1578			#clock-cells = <1>;
1579			#reset-cells = <1>;
1580			#power-domain-cells = <1>;
1581			reg = <0x05065000 0x9000>;
1582
1583			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1584				 <&gcc GCC_GPU_GPLL0_CLK>;
1585			clock-names = "xo",
1586				      "gpll0";
1587		};
1588
1589		remoteproc_slpi: remoteproc@5800000 {
1590			compatible = "qcom,msm8998-slpi-pas";
1591			reg = <0x05800000 0x4040>;
1592
1593			interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1594					      <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1595					      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1596					      <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1597					      <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1598			interrupt-names = "wdog", "fatal", "ready",
1599					  "handover", "stop-ack";
1600
1601			px-supply = <&vreg_lvs2a_1p8>;
1602
1603			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1604			clock-names = "xo";
1605
1606			memory-region = <&slpi_mem>;
1607
1608			qcom,smem-states = <&slpi_smp2p_out 0>;
1609			qcom,smem-state-names = "stop";
1610
1611			power-domains = <&rpmpd MSM8998_SSCCX>;
1612			power-domain-names = "ssc_cx";
1613
1614			status = "disabled";
1615
1616			glink-edge {
1617				interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1618				label = "dsps";
1619				qcom,remote-pid = <3>;
1620				mboxes = <&apcs_glb 27>;
1621			};
1622		};
1623
1624		stm: stm@6002000 {
1625			compatible = "arm,coresight-stm", "arm,primecell";
1626			reg = <0x06002000 0x1000>,
1627			      <0x16280000 0x180000>;
1628			reg-names = "stm-base", "stm-stimulus-base";
1629			status = "disabled";
1630
1631			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1632			clock-names = "apb_pclk", "atclk";
1633
1634			out-ports {
1635				port {
1636					stm_out: endpoint {
1637						remote-endpoint = <&funnel0_in7>;
1638					};
1639				};
1640			};
1641		};
1642
1643		funnel1: funnel@6041000 {
1644			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1645			reg = <0x06041000 0x1000>;
1646			status = "disabled";
1647
1648			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1649			clock-names = "apb_pclk", "atclk";
1650
1651			out-ports {
1652				port {
1653					funnel0_out: endpoint {
1654						remote-endpoint =
1655						  <&merge_funnel_in0>;
1656					};
1657				};
1658			};
1659
1660			in-ports {
1661				#address-cells = <1>;
1662				#size-cells = <0>;
1663
1664				port@7 {
1665					reg = <7>;
1666					funnel0_in7: endpoint {
1667						remote-endpoint = <&stm_out>;
1668					};
1669				};
1670			};
1671		};
1672
1673		funnel2: funnel@6042000 {
1674			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1675			reg = <0x06042000 0x1000>;
1676			status = "disabled";
1677
1678			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1679			clock-names = "apb_pclk", "atclk";
1680
1681			out-ports {
1682				port {
1683					funnel1_out: endpoint {
1684						remote-endpoint =
1685						  <&merge_funnel_in1>;
1686					};
1687				};
1688			};
1689
1690			in-ports {
1691				#address-cells = <1>;
1692				#size-cells = <0>;
1693
1694				port@6 {
1695					reg = <6>;
1696					funnel1_in6: endpoint {
1697						remote-endpoint =
1698						  <&apss_merge_funnel_out>;
1699					};
1700				};
1701			};
1702		};
1703
1704		funnel3: funnel@6045000 {
1705			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1706			reg = <0x06045000 0x1000>;
1707			status = "disabled";
1708
1709			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1710			clock-names = "apb_pclk", "atclk";
1711
1712			out-ports {
1713				port {
1714					merge_funnel_out: endpoint {
1715						remote-endpoint =
1716						  <&etf_in>;
1717					};
1718				};
1719			};
1720
1721			in-ports {
1722				#address-cells = <1>;
1723				#size-cells = <0>;
1724
1725				port@0 {
1726					reg = <0>;
1727					merge_funnel_in0: endpoint {
1728						remote-endpoint =
1729						  <&funnel0_out>;
1730					};
1731				};
1732
1733				port@1 {
1734					reg = <1>;
1735					merge_funnel_in1: endpoint {
1736						remote-endpoint =
1737						  <&funnel1_out>;
1738					};
1739				};
1740			};
1741		};
1742
1743		replicator1: replicator@6046000 {
1744			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1745			reg = <0x06046000 0x1000>;
1746			status = "disabled";
1747
1748			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1749			clock-names = "apb_pclk", "atclk";
1750
1751			out-ports {
1752				port {
1753					replicator_out: endpoint {
1754						remote-endpoint = <&etr_in>;
1755					};
1756				};
1757			};
1758
1759			in-ports {
1760				port {
1761					replicator_in: endpoint {
1762						remote-endpoint = <&etf_out>;
1763					};
1764				};
1765			};
1766		};
1767
1768		etf: etf@6047000 {
1769			compatible = "arm,coresight-tmc", "arm,primecell";
1770			reg = <0x06047000 0x1000>;
1771			status = "disabled";
1772
1773			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1774			clock-names = "apb_pclk", "atclk";
1775
1776			out-ports {
1777				port {
1778					etf_out: endpoint {
1779						remote-endpoint =
1780						  <&replicator_in>;
1781					};
1782				};
1783			};
1784
1785			in-ports {
1786				port {
1787					etf_in: endpoint {
1788						remote-endpoint =
1789						  <&merge_funnel_out>;
1790					};
1791				};
1792			};
1793		};
1794
1795		etr: etr@6048000 {
1796			compatible = "arm,coresight-tmc", "arm,primecell";
1797			reg = <0x06048000 0x1000>;
1798			status = "disabled";
1799
1800			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1801			clock-names = "apb_pclk", "atclk";
1802			arm,scatter-gather;
1803
1804			in-ports {
1805				port {
1806					etr_in: endpoint {
1807						remote-endpoint =
1808						  <&replicator_out>;
1809					};
1810				};
1811			};
1812		};
1813
1814		etm1: etm@7840000 {
1815			compatible = "arm,coresight-etm4x", "arm,primecell";
1816			reg = <0x07840000 0x1000>;
1817			status = "disabled";
1818
1819			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1820			clock-names = "apb_pclk", "atclk";
1821
1822			cpu = <&CPU0>;
1823
1824			out-ports {
1825				port {
1826					etm0_out: endpoint {
1827						remote-endpoint =
1828						  <&apss_funnel_in0>;
1829					};
1830				};
1831			};
1832		};
1833
1834		etm2: etm@7940000 {
1835			compatible = "arm,coresight-etm4x", "arm,primecell";
1836			reg = <0x07940000 0x1000>;
1837			status = "disabled";
1838
1839			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1840			clock-names = "apb_pclk", "atclk";
1841
1842			cpu = <&CPU1>;
1843
1844			out-ports {
1845				port {
1846					etm1_out: endpoint {
1847						remote-endpoint =
1848						  <&apss_funnel_in1>;
1849					};
1850				};
1851			};
1852		};
1853
1854		etm3: etm@7a40000 {
1855			compatible = "arm,coresight-etm4x", "arm,primecell";
1856			reg = <0x07a40000 0x1000>;
1857			status = "disabled";
1858
1859			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1860			clock-names = "apb_pclk", "atclk";
1861
1862			cpu = <&CPU2>;
1863
1864			out-ports {
1865				port {
1866					etm2_out: endpoint {
1867						remote-endpoint =
1868						  <&apss_funnel_in2>;
1869					};
1870				};
1871			};
1872		};
1873
1874		etm4: etm@7b40000 {
1875			compatible = "arm,coresight-etm4x", "arm,primecell";
1876			reg = <0x07b40000 0x1000>;
1877			status = "disabled";
1878
1879			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1880			clock-names = "apb_pclk", "atclk";
1881
1882			cpu = <&CPU3>;
1883
1884			out-ports {
1885				port {
1886					etm3_out: endpoint {
1887						remote-endpoint =
1888						  <&apss_funnel_in3>;
1889					};
1890				};
1891			};
1892		};
1893
1894		funnel4: funnel@7b60000 { /* APSS Funnel */
1895			compatible = "arm,coresight-etm4x", "arm,primecell";
1896			reg = <0x07b60000 0x1000>;
1897			status = "disabled";
1898
1899			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1900			clock-names = "apb_pclk", "atclk";
1901
1902			out-ports {
1903				port {
1904					apss_funnel_out: endpoint {
1905						remote-endpoint =
1906						  <&apss_merge_funnel_in>;
1907					};
1908				};
1909			};
1910
1911			in-ports {
1912				#address-cells = <1>;
1913				#size-cells = <0>;
1914
1915				port@0 {
1916					reg = <0>;
1917					apss_funnel_in0: endpoint {
1918						remote-endpoint =
1919						  <&etm0_out>;
1920					};
1921				};
1922
1923				port@1 {
1924					reg = <1>;
1925					apss_funnel_in1: endpoint {
1926						remote-endpoint =
1927						  <&etm1_out>;
1928					};
1929				};
1930
1931				port@2 {
1932					reg = <2>;
1933					apss_funnel_in2: endpoint {
1934						remote-endpoint =
1935						  <&etm2_out>;
1936					};
1937				};
1938
1939				port@3 {
1940					reg = <3>;
1941					apss_funnel_in3: endpoint {
1942						remote-endpoint =
1943						  <&etm3_out>;
1944					};
1945				};
1946
1947				port@4 {
1948					reg = <4>;
1949					apss_funnel_in4: endpoint {
1950						remote-endpoint =
1951						  <&etm4_out>;
1952					};
1953				};
1954
1955				port@5 {
1956					reg = <5>;
1957					apss_funnel_in5: endpoint {
1958						remote-endpoint =
1959						  <&etm5_out>;
1960					};
1961				};
1962
1963				port@6 {
1964					reg = <6>;
1965					apss_funnel_in6: endpoint {
1966						remote-endpoint =
1967						  <&etm6_out>;
1968					};
1969				};
1970
1971				port@7 {
1972					reg = <7>;
1973					apss_funnel_in7: endpoint {
1974						remote-endpoint =
1975						  <&etm7_out>;
1976					};
1977				};
1978			};
1979		};
1980
1981		funnel5: funnel@7b70000 {
1982			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1983			reg = <0x07b70000 0x1000>;
1984			status = "disabled";
1985
1986			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1987			clock-names = "apb_pclk", "atclk";
1988
1989			out-ports {
1990				port {
1991					apss_merge_funnel_out: endpoint {
1992						remote-endpoint =
1993						  <&funnel1_in6>;
1994					};
1995				};
1996			};
1997
1998			in-ports {
1999				port {
2000					apss_merge_funnel_in: endpoint {
2001						remote-endpoint =
2002						  <&apss_funnel_out>;
2003					};
2004				};
2005			};
2006		};
2007
2008		etm5: etm@7c40000 {
2009			compatible = "arm,coresight-etm4x", "arm,primecell";
2010			reg = <0x07c40000 0x1000>;
2011			status = "disabled";
2012
2013			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2014			clock-names = "apb_pclk", "atclk";
2015
2016			cpu = <&CPU4>;
2017
2018			out-ports {
2019				port {
2020					etm4_out: endpoint {
2021						remote-endpoint = <&apss_funnel_in4>;
2022					};
2023				};
2024			};
2025		};
2026
2027		etm6: etm@7d40000 {
2028			compatible = "arm,coresight-etm4x", "arm,primecell";
2029			reg = <0x07d40000 0x1000>;
2030			status = "disabled";
2031
2032			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2033			clock-names = "apb_pclk", "atclk";
2034
2035			cpu = <&CPU5>;
2036
2037			out-ports {
2038				port {
2039					etm5_out: endpoint {
2040						remote-endpoint = <&apss_funnel_in5>;
2041					};
2042				};
2043			};
2044		};
2045
2046		etm7: etm@7e40000 {
2047			compatible = "arm,coresight-etm4x", "arm,primecell";
2048			reg = <0x07e40000 0x1000>;
2049			status = "disabled";
2050
2051			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2052			clock-names = "apb_pclk", "atclk";
2053
2054			cpu = <&CPU6>;
2055
2056			out-ports {
2057				port {
2058					etm6_out: endpoint {
2059						remote-endpoint = <&apss_funnel_in6>;
2060					};
2061				};
2062			};
2063		};
2064
2065		etm8: etm@7f40000 {
2066			compatible = "arm,coresight-etm4x", "arm,primecell";
2067			reg = <0x07f40000 0x1000>;
2068			status = "disabled";
2069
2070			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2071			clock-names = "apb_pclk", "atclk";
2072
2073			cpu = <&CPU7>;
2074
2075			out-ports {
2076				port {
2077					etm7_out: endpoint {
2078						remote-endpoint = <&apss_funnel_in7>;
2079					};
2080				};
2081			};
2082		};
2083
2084		sram@290000 {
2085			compatible = "qcom,rpm-stats";
2086			reg = <0x00290000 0x10000>;
2087		};
2088
2089		spmi_bus: spmi@800f000 {
2090			compatible = "qcom,spmi-pmic-arb";
2091			reg = <0x0800f000 0x1000>,
2092			      <0x08400000 0x1000000>,
2093			      <0x09400000 0x1000000>,
2094			      <0x0a400000 0x220000>,
2095			      <0x0800a000 0x3000>;
2096			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2097			interrupt-names = "periph_irq";
2098			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2099			qcom,ee = <0>;
2100			qcom,channel = <0>;
2101			#address-cells = <2>;
2102			#size-cells = <0>;
2103			interrupt-controller;
2104			#interrupt-cells = <4>;
2105		};
2106
2107		usb3: usb@a8f8800 {
2108			compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2109			reg = <0x0a8f8800 0x400>;
2110			status = "disabled";
2111			#address-cells = <1>;
2112			#size-cells = <1>;
2113			ranges;
2114
2115			clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2116				 <&gcc GCC_USB30_MASTER_CLK>,
2117				 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2118				 <&gcc GCC_USB30_SLEEP_CLK>,
2119				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2120			clock-names = "cfg_noc",
2121				      "core",
2122				      "iface",
2123				      "sleep",
2124				      "mock_utmi";
2125
2126			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2127					  <&gcc GCC_USB30_MASTER_CLK>;
2128			assigned-clock-rates = <19200000>, <120000000>;
2129
2130			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
2131				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2132				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2133			interrupt-names = "pwr_event",
2134					  "qusb2_phy",
2135					  "ss_phy_irq";
2136
2137			power-domains = <&gcc USB_30_GDSC>;
2138
2139			resets = <&gcc GCC_USB_30_BCR>;
2140
2141			usb3_dwc3: usb@a800000 {
2142				compatible = "snps,dwc3";
2143				reg = <0x0a800000 0xcd00>;
2144				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2145				snps,dis_u2_susphy_quirk;
2146				snps,dis_enblslpm_quirk;
2147				snps,parkmode-disable-ss-quirk;
2148				phys = <&qusb2phy>, <&usb3phy>;
2149				phy-names = "usb2-phy", "usb3-phy";
2150				snps,has-lpm-erratum;
2151				snps,hird-threshold = /bits/ 8 <0x10>;
2152			};
2153		};
2154
2155		usb3phy: phy@c010000 {
2156			compatible = "qcom,msm8998-qmp-usb3-phy";
2157			reg = <0x0c010000 0x1000>;
2158
2159			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2160				 <&gcc GCC_USB3_CLKREF_CLK>,
2161				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2162				 <&gcc GCC_USB3_PHY_PIPE_CLK>;
2163			clock-names = "aux",
2164				      "ref",
2165				      "cfg_ahb",
2166				      "pipe";
2167			clock-output-names = "usb3_phy_pipe_clk_src";
2168			#clock-cells = <0>;
2169			#phy-cells = <0>;
2170
2171			resets = <&gcc GCC_USB3_PHY_BCR>,
2172				 <&gcc GCC_USB3PHY_PHY_BCR>;
2173			reset-names = "phy",
2174				      "phy_phy";
2175
2176			qcom,tcsr-reg = <&tcsr_regs_2 0xb244>;
2177
2178			status = "disabled";
2179		};
2180
2181		qusb2phy: phy@c012000 {
2182			compatible = "qcom,msm8998-qusb2-phy";
2183			reg = <0x0c012000 0x2a8>;
2184			status = "disabled";
2185			#phy-cells = <0>;
2186
2187			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2188				 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2189			clock-names = "cfg_ahb", "ref";
2190
2191			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2192
2193			nvmem-cells = <&qusb2_hstx_trim>;
2194		};
2195
2196		sdhc2: mmc@c0a4900 {
2197			compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2198			reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2199			reg-names = "hc", "core";
2200
2201			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2202				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2203			interrupt-names = "hc_irq", "pwr_irq";
2204
2205			clock-names = "iface", "core", "xo";
2206			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2207				 <&gcc GCC_SDCC2_APPS_CLK>,
2208				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2209			bus-width = <4>;
2210			status = "disabled";
2211		};
2212
2213		blsp1_dma: dma-controller@c144000 {
2214			compatible = "qcom,bam-v1.7.0";
2215			reg = <0x0c144000 0x25000>;
2216			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2217			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2218			clock-names = "bam_clk";
2219			#dma-cells = <1>;
2220			qcom,ee = <0>;
2221			qcom,controlled-remotely;
2222			num-channels = <18>;
2223			qcom,num-ees = <4>;
2224		};
2225
2226		blsp1_uart3: serial@c171000 {
2227			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2228			reg = <0x0c171000 0x1000>;
2229			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2230			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2231				 <&gcc GCC_BLSP1_AHB_CLK>;
2232			clock-names = "core", "iface";
2233			dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2234			dma-names = "tx", "rx";
2235			pinctrl-names = "default";
2236			pinctrl-0 = <&blsp1_uart3_on>;
2237			status = "disabled";
2238		};
2239
2240		blsp1_i2c1: i2c@c175000 {
2241			compatible = "qcom,i2c-qup-v2.2.1";
2242			reg = <0x0c175000 0x600>;
2243			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2244
2245			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2246				 <&gcc GCC_BLSP1_AHB_CLK>;
2247			clock-names = "core", "iface";
2248			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2249			dma-names = "tx", "rx";
2250			pinctrl-names = "default", "sleep";
2251			pinctrl-0 = <&blsp1_i2c1_default>;
2252			pinctrl-1 = <&blsp1_i2c1_sleep>;
2253			clock-frequency = <400000>;
2254
2255			status = "disabled";
2256			#address-cells = <1>;
2257			#size-cells = <0>;
2258		};
2259
2260		blsp1_i2c2: i2c@c176000 {
2261			compatible = "qcom,i2c-qup-v2.2.1";
2262			reg = <0x0c176000 0x600>;
2263			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2264
2265			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2266				 <&gcc GCC_BLSP1_AHB_CLK>;
2267			clock-names = "core", "iface";
2268			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2269			dma-names = "tx", "rx";
2270			pinctrl-names = "default", "sleep";
2271			pinctrl-0 = <&blsp1_i2c2_default>;
2272			pinctrl-1 = <&blsp1_i2c2_sleep>;
2273			clock-frequency = <400000>;
2274
2275			status = "disabled";
2276			#address-cells = <1>;
2277			#size-cells = <0>;
2278		};
2279
2280		blsp1_i2c3: i2c@c177000 {
2281			compatible = "qcom,i2c-qup-v2.2.1";
2282			reg = <0x0c177000 0x600>;
2283			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2284
2285			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2286				 <&gcc GCC_BLSP1_AHB_CLK>;
2287			clock-names = "core", "iface";
2288			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2289			dma-names = "tx", "rx";
2290			pinctrl-names = "default", "sleep";
2291			pinctrl-0 = <&blsp1_i2c3_default>;
2292			pinctrl-1 = <&blsp1_i2c3_sleep>;
2293			clock-frequency = <400000>;
2294
2295			status = "disabled";
2296			#address-cells = <1>;
2297			#size-cells = <0>;
2298		};
2299
2300		blsp1_i2c4: i2c@c178000 {
2301			compatible = "qcom,i2c-qup-v2.2.1";
2302			reg = <0x0c178000 0x600>;
2303			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2304
2305			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2306				 <&gcc GCC_BLSP1_AHB_CLK>;
2307			clock-names = "core", "iface";
2308			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2309			dma-names = "tx", "rx";
2310			pinctrl-names = "default", "sleep";
2311			pinctrl-0 = <&blsp1_i2c4_default>;
2312			pinctrl-1 = <&blsp1_i2c4_sleep>;
2313			clock-frequency = <400000>;
2314
2315			status = "disabled";
2316			#address-cells = <1>;
2317			#size-cells = <0>;
2318		};
2319
2320		blsp1_i2c5: i2c@c179000 {
2321			compatible = "qcom,i2c-qup-v2.2.1";
2322			reg = <0x0c179000 0x600>;
2323			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2324
2325			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2326				 <&gcc GCC_BLSP1_AHB_CLK>;
2327			clock-names = "core", "iface";
2328			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2329			dma-names = "tx", "rx";
2330			pinctrl-names = "default", "sleep";
2331			pinctrl-0 = <&blsp1_i2c5_default>;
2332			pinctrl-1 = <&blsp1_i2c5_sleep>;
2333			clock-frequency = <400000>;
2334
2335			status = "disabled";
2336			#address-cells = <1>;
2337			#size-cells = <0>;
2338		};
2339
2340		blsp1_i2c6: i2c@c17a000 {
2341			compatible = "qcom,i2c-qup-v2.2.1";
2342			reg = <0x0c17a000 0x600>;
2343			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2344
2345			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2346				 <&gcc GCC_BLSP1_AHB_CLK>;
2347			clock-names = "core", "iface";
2348			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2349			dma-names = "tx", "rx";
2350			pinctrl-names = "default", "sleep";
2351			pinctrl-0 = <&blsp1_i2c6_default>;
2352			pinctrl-1 = <&blsp1_i2c6_sleep>;
2353			clock-frequency = <400000>;
2354
2355			status = "disabled";
2356			#address-cells = <1>;
2357			#size-cells = <0>;
2358		};
2359
2360		blsp1_spi1: spi@c175000 {
2361			compatible = "qcom,spi-qup-v2.2.1";
2362			reg = <0x0c175000 0x600>;
2363			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2364
2365			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2366				 <&gcc GCC_BLSP1_AHB_CLK>;
2367			clock-names = "core", "iface";
2368			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2369			dma-names = "tx", "rx";
2370			pinctrl-names = "default";
2371			pinctrl-0 = <&blsp1_spi1_default>;
2372
2373			status = "disabled";
2374			#address-cells = <1>;
2375			#size-cells = <0>;
2376		};
2377
2378		blsp1_spi2: spi@c176000 {
2379			compatible = "qcom,spi-qup-v2.2.1";
2380			reg = <0x0c176000 0x600>;
2381			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2382
2383			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2384				 <&gcc GCC_BLSP1_AHB_CLK>;
2385			clock-names = "core", "iface";
2386			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2387			dma-names = "tx", "rx";
2388			pinctrl-names = "default";
2389			pinctrl-0 = <&blsp1_spi2_default>;
2390
2391			status = "disabled";
2392			#address-cells = <1>;
2393			#size-cells = <0>;
2394		};
2395
2396		blsp1_spi3: spi@c177000 {
2397			compatible = "qcom,spi-qup-v2.2.1";
2398			reg = <0x0c177000 0x600>;
2399			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2400
2401			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2402				 <&gcc GCC_BLSP1_AHB_CLK>;
2403			clock-names = "core", "iface";
2404			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2405			dma-names = "tx", "rx";
2406			pinctrl-names = "default";
2407			pinctrl-0 = <&blsp1_spi3_default>;
2408
2409			status = "disabled";
2410			#address-cells = <1>;
2411			#size-cells = <0>;
2412		};
2413
2414		blsp1_spi4: spi@c178000 {
2415			compatible = "qcom,spi-qup-v2.2.1";
2416			reg = <0x0c178000 0x600>;
2417			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2418
2419			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2420				 <&gcc GCC_BLSP1_AHB_CLK>;
2421			clock-names = "core", "iface";
2422			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2423			dma-names = "tx", "rx";
2424			pinctrl-names = "default";
2425			pinctrl-0 = <&blsp1_spi4_default>;
2426
2427			status = "disabled";
2428			#address-cells = <1>;
2429			#size-cells = <0>;
2430		};
2431
2432		blsp1_spi5: spi@c179000 {
2433			compatible = "qcom,spi-qup-v2.2.1";
2434			reg = <0x0c179000 0x600>;
2435			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2436
2437			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2438				 <&gcc GCC_BLSP1_AHB_CLK>;
2439			clock-names = "core", "iface";
2440			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2441			dma-names = "tx", "rx";
2442			pinctrl-names = "default";
2443			pinctrl-0 = <&blsp1_spi5_default>;
2444
2445			status = "disabled";
2446			#address-cells = <1>;
2447			#size-cells = <0>;
2448		};
2449
2450		blsp1_spi6: spi@c17a000 {
2451			compatible = "qcom,spi-qup-v2.2.1";
2452			reg = <0x0c17a000 0x600>;
2453			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2454
2455			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2456				 <&gcc GCC_BLSP1_AHB_CLK>;
2457			clock-names = "core", "iface";
2458			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2459			dma-names = "tx", "rx";
2460			pinctrl-names = "default";
2461			pinctrl-0 = <&blsp1_spi6_default>;
2462
2463			status = "disabled";
2464			#address-cells = <1>;
2465			#size-cells = <0>;
2466		};
2467
2468		blsp2_dma: dma-controller@c184000 {
2469			compatible = "qcom,bam-v1.7.0";
2470			reg = <0x0c184000 0x25000>;
2471			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2472			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2473			clock-names = "bam_clk";
2474			#dma-cells = <1>;
2475			qcom,ee = <0>;
2476			qcom,controlled-remotely;
2477			num-channels = <18>;
2478			qcom,num-ees = <4>;
2479		};
2480
2481		blsp2_uart1: serial@c1b0000 {
2482			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2483			reg = <0x0c1b0000 0x1000>;
2484			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2485			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2486				 <&gcc GCC_BLSP2_AHB_CLK>;
2487			clock-names = "core", "iface";
2488			status = "disabled";
2489		};
2490
2491		blsp2_i2c1: i2c@c1b5000 {
2492			compatible = "qcom,i2c-qup-v2.2.1";
2493			reg = <0x0c1b5000 0x600>;
2494			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2495
2496			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2497				 <&gcc GCC_BLSP2_AHB_CLK>;
2498			clock-names = "core", "iface";
2499			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2500			dma-names = "tx", "rx";
2501			pinctrl-names = "default", "sleep";
2502			pinctrl-0 = <&blsp2_i2c1_default>;
2503			pinctrl-1 = <&blsp2_i2c1_sleep>;
2504			clock-frequency = <400000>;
2505
2506			status = "disabled";
2507			#address-cells = <1>;
2508			#size-cells = <0>;
2509		};
2510
2511		blsp2_i2c2: i2c@c1b6000 {
2512			compatible = "qcom,i2c-qup-v2.2.1";
2513			reg = <0x0c1b6000 0x600>;
2514			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2515
2516			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2517				 <&gcc GCC_BLSP2_AHB_CLK>;
2518			clock-names = "core", "iface";
2519			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2520			dma-names = "tx", "rx";
2521			pinctrl-names = "default", "sleep";
2522			pinctrl-0 = <&blsp2_i2c2_default>;
2523			pinctrl-1 = <&blsp2_i2c2_sleep>;
2524			clock-frequency = <400000>;
2525
2526			status = "disabled";
2527			#address-cells = <1>;
2528			#size-cells = <0>;
2529		};
2530
2531		blsp2_i2c3: i2c@c1b7000 {
2532			compatible = "qcom,i2c-qup-v2.2.1";
2533			reg = <0x0c1b7000 0x600>;
2534			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2535
2536			clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2537				 <&gcc GCC_BLSP2_AHB_CLK>;
2538			clock-names = "core", "iface";
2539			dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2540			dma-names = "tx", "rx";
2541			pinctrl-names = "default", "sleep";
2542			pinctrl-0 = <&blsp2_i2c3_default>;
2543			pinctrl-1 = <&blsp2_i2c3_sleep>;
2544			clock-frequency = <400000>;
2545
2546			status = "disabled";
2547			#address-cells = <1>;
2548			#size-cells = <0>;
2549		};
2550
2551		blsp2_i2c4: i2c@c1b8000 {
2552			compatible = "qcom,i2c-qup-v2.2.1";
2553			reg = <0x0c1b8000 0x600>;
2554			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2555
2556			clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2557				 <&gcc GCC_BLSP2_AHB_CLK>;
2558			clock-names = "core", "iface";
2559			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2560			dma-names = "tx", "rx";
2561			pinctrl-names = "default", "sleep";
2562			pinctrl-0 = <&blsp2_i2c4_default>;
2563			pinctrl-1 = <&blsp2_i2c4_sleep>;
2564			clock-frequency = <400000>;
2565
2566			status = "disabled";
2567			#address-cells = <1>;
2568			#size-cells = <0>;
2569		};
2570
2571		blsp2_i2c5: i2c@c1b9000 {
2572			compatible = "qcom,i2c-qup-v2.2.1";
2573			reg = <0x0c1b9000 0x600>;
2574			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2575
2576			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2577				 <&gcc GCC_BLSP2_AHB_CLK>;
2578			clock-names = "core", "iface";
2579			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2580			dma-names = "tx", "rx";
2581			pinctrl-names = "default", "sleep";
2582			pinctrl-0 = <&blsp2_i2c5_default>;
2583			pinctrl-1 = <&blsp2_i2c5_sleep>;
2584			clock-frequency = <400000>;
2585
2586			status = "disabled";
2587			#address-cells = <1>;
2588			#size-cells = <0>;
2589		};
2590
2591		blsp2_i2c6: i2c@c1ba000 {
2592			compatible = "qcom,i2c-qup-v2.2.1";
2593			reg = <0x0c1ba000 0x600>;
2594			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2595
2596			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2597				 <&gcc GCC_BLSP2_AHB_CLK>;
2598			clock-names = "core", "iface";
2599			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2600			dma-names = "tx", "rx";
2601			pinctrl-names = "default", "sleep";
2602			pinctrl-0 = <&blsp2_i2c6_default>;
2603			pinctrl-1 = <&blsp2_i2c6_sleep>;
2604			clock-frequency = <400000>;
2605
2606			status = "disabled";
2607			#address-cells = <1>;
2608			#size-cells = <0>;
2609		};
2610
2611		blsp2_spi1: spi@c1b5000 {
2612			compatible = "qcom,spi-qup-v2.2.1";
2613			reg = <0x0c1b5000 0x600>;
2614			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2615
2616			clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
2617				 <&gcc GCC_BLSP2_AHB_CLK>;
2618			clock-names = "core", "iface";
2619			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2620			dma-names = "tx", "rx";
2621			pinctrl-names = "default";
2622			pinctrl-0 = <&blsp2_spi1_default>;
2623
2624			status = "disabled";
2625			#address-cells = <1>;
2626			#size-cells = <0>;
2627		};
2628
2629		blsp2_spi2: spi@c1b6000 {
2630			compatible = "qcom,spi-qup-v2.2.1";
2631			reg = <0x0c1b6000 0x600>;
2632			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2633
2634			clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
2635				 <&gcc GCC_BLSP2_AHB_CLK>;
2636			clock-names = "core", "iface";
2637			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2638			dma-names = "tx", "rx";
2639			pinctrl-names = "default";
2640			pinctrl-0 = <&blsp2_spi2_default>;
2641
2642			status = "disabled";
2643			#address-cells = <1>;
2644			#size-cells = <0>;
2645		};
2646
2647		blsp2_spi3: spi@c1b7000 {
2648			compatible = "qcom,spi-qup-v2.2.1";
2649			reg = <0x0c1b7000 0x600>;
2650			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2651
2652			clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
2653				 <&gcc GCC_BLSP2_AHB_CLK>;
2654			clock-names = "core", "iface";
2655			dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2656			dma-names = "tx", "rx";
2657			pinctrl-names = "default";
2658			pinctrl-0 = <&blsp2_spi3_default>;
2659
2660			status = "disabled";
2661			#address-cells = <1>;
2662			#size-cells = <0>;
2663		};
2664
2665		blsp2_spi4: spi@c1b8000 {
2666			compatible = "qcom,spi-qup-v2.2.1";
2667			reg = <0x0c1b8000 0x600>;
2668			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2669
2670			clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
2671				 <&gcc GCC_BLSP2_AHB_CLK>;
2672			clock-names = "core", "iface";
2673			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2674			dma-names = "tx", "rx";
2675			pinctrl-names = "default";
2676			pinctrl-0 = <&blsp2_spi4_default>;
2677
2678			status = "disabled";
2679			#address-cells = <1>;
2680			#size-cells = <0>;
2681		};
2682
2683		blsp2_spi5: spi@c1b9000 {
2684			compatible = "qcom,spi-qup-v2.2.1";
2685			reg = <0x0c1b9000 0x600>;
2686			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2687
2688			clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
2689				 <&gcc GCC_BLSP2_AHB_CLK>;
2690			clock-names = "core", "iface";
2691			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2692			dma-names = "tx", "rx";
2693			pinctrl-names = "default";
2694			pinctrl-0 = <&blsp2_spi5_default>;
2695
2696			status = "disabled";
2697			#address-cells = <1>;
2698			#size-cells = <0>;
2699		};
2700
2701		blsp2_spi6: spi@c1ba000 {
2702			compatible = "qcom,spi-qup-v2.2.1";
2703			reg = <0x0c1ba000 0x600>;
2704			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2705
2706			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2707				 <&gcc GCC_BLSP2_AHB_CLK>;
2708			clock-names = "core", "iface";
2709			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2710			dma-names = "tx", "rx";
2711			pinctrl-names = "default";
2712			pinctrl-0 = <&blsp2_spi6_default>;
2713
2714			status = "disabled";
2715			#address-cells = <1>;
2716			#size-cells = <0>;
2717		};
2718
2719		mmcc: clock-controller@c8c0000 {
2720			compatible = "qcom,mmcc-msm8998";
2721			#clock-cells = <1>;
2722			#reset-cells = <1>;
2723			#power-domain-cells = <1>;
2724			reg = <0xc8c0000 0x40000>;
2725
2726			clock-names = "xo",
2727				      "gpll0",
2728				      "dsi0dsi",
2729				      "dsi0byte",
2730				      "dsi1dsi",
2731				      "dsi1byte",
2732				      "hdmipll",
2733				      "dplink",
2734				      "dpvco",
2735				      "gpll0_div";
2736			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2737				 <&gcc GCC_MMSS_GPLL0_CLK>,
2738				 <&mdss_dsi0_phy 1>,
2739				 <&mdss_dsi0_phy 0>,
2740				 <&mdss_dsi1_phy 1>,
2741				 <&mdss_dsi1_phy 0>,
2742				 <0>,
2743				 <0>,
2744				 <0>,
2745				 <&gcc GCC_MMSS_GPLL0_DIV_CLK>;
2746		};
2747
2748		mdss: display-subsystem@c900000 {
2749			compatible = "qcom,msm8998-mdss";
2750			reg = <0x0c900000 0x1000>;
2751			reg-names = "mdss";
2752
2753			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2754			interrupt-controller;
2755			#interrupt-cells = <1>;
2756
2757			clocks = <&mmcc MDSS_AHB_CLK>,
2758				 <&mmcc MDSS_AXI_CLK>,
2759				 <&mmcc MDSS_MDP_CLK>;
2760			clock-names = "iface",
2761				      "bus",
2762				      "core";
2763
2764			power-domains = <&mmcc MDSS_GDSC>;
2765			iommus = <&mmss_smmu 0>;
2766
2767			#address-cells = <1>;
2768			#size-cells = <1>;
2769			ranges;
2770
2771			status = "disabled";
2772
2773			mdss_mdp: display-controller@c901000 {
2774				compatible = "qcom,msm8998-dpu";
2775				reg = <0x0c901000 0x8f000>,
2776				      <0x0c9a8e00 0xf0>,
2777				      <0x0c9b0000 0x2008>,
2778				      <0x0c9b8000 0x1040>;
2779				reg-names = "mdp",
2780					    "regdma",
2781					    "vbif",
2782					    "vbif_nrt";
2783
2784				interrupt-parent = <&mdss>;
2785				interrupts = <0>;
2786
2787				clocks = <&mmcc MDSS_AHB_CLK>,
2788					 <&mmcc MDSS_AXI_CLK>,
2789					 <&mmcc MNOC_AHB_CLK>,
2790					 <&mmcc MDSS_MDP_CLK>,
2791					 <&mmcc MDSS_VSYNC_CLK>;
2792				clock-names = "iface",
2793					      "bus",
2794					      "mnoc",
2795					      "core",
2796					      "vsync";
2797
2798				assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2799				assigned-clock-rates = <19200000>;
2800
2801				operating-points-v2 = <&mdp_opp_table>;
2802				power-domains = <&rpmpd MSM8998_VDDMX>;
2803
2804				mdp_opp_table: opp-table {
2805					compatible = "operating-points-v2";
2806
2807					opp-171430000 {
2808						opp-hz = /bits/ 64 <171430000>;
2809						required-opps = <&rpmpd_opp_low_svs>;
2810					};
2811
2812					opp-275000000 {
2813						opp-hz = /bits/ 64 <275000000>;
2814						required-opps = <&rpmpd_opp_svs>;
2815					};
2816
2817					opp-330000000 {
2818						opp-hz = /bits/ 64 <330000000>;
2819						required-opps = <&rpmpd_opp_nom>;
2820					};
2821
2822					opp-412500000 {
2823						opp-hz = /bits/ 64 <412500000>;
2824						required-opps = <&rpmpd_opp_turbo>;
2825					};
2826				};
2827
2828				ports {
2829					#address-cells = <1>;
2830					#size-cells = <0>;
2831
2832					port@0 {
2833						reg = <0>;
2834
2835						dpu_intf1_out: endpoint {
2836							remote-endpoint = <&mdss_dsi0_in>;
2837						};
2838					};
2839
2840					port@1 {
2841						reg = <1>;
2842
2843						dpu_intf2_out: endpoint {
2844							remote-endpoint = <&mdss_dsi1_in>;
2845						};
2846					};
2847				};
2848			};
2849
2850			mdss_dsi0: dsi@c994000 {
2851				compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2852				reg = <0x0c994000 0x400>;
2853				reg-names = "dsi_ctrl";
2854
2855				interrupt-parent = <&mdss>;
2856				interrupts = <4>;
2857
2858				clocks = <&mmcc MDSS_BYTE0_CLK>,
2859					 <&mmcc MDSS_BYTE0_INTF_CLK>,
2860					 <&mmcc MDSS_PCLK0_CLK>,
2861					 <&mmcc MDSS_ESC0_CLK>,
2862					 <&mmcc MDSS_AHB_CLK>,
2863					 <&mmcc MDSS_AXI_CLK>;
2864				clock-names = "byte",
2865					      "byte_intf",
2866					      "pixel",
2867					      "core",
2868					      "iface",
2869					      "bus";
2870				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2871						  <&mmcc PCLK0_CLK_SRC>;
2872				assigned-clock-parents = <&mdss_dsi0_phy 0>,
2873							 <&mdss_dsi0_phy 1>;
2874
2875				operating-points-v2 = <&dsi_opp_table>;
2876				power-domains = <&rpmpd MSM8998_VDDCX>;
2877
2878				phys = <&mdss_dsi0_phy>;
2879				phy-names = "dsi";
2880
2881				#address-cells = <1>;
2882				#size-cells = <0>;
2883
2884				status = "disabled";
2885
2886				ports {
2887					#address-cells = <1>;
2888					#size-cells = <0>;
2889
2890					port@0 {
2891						reg = <0>;
2892
2893						mdss_dsi0_in: endpoint {
2894							remote-endpoint = <&dpu_intf1_out>;
2895						};
2896					};
2897
2898					port@1 {
2899						reg = <1>;
2900
2901						mdss_dsi0_out: endpoint {
2902						};
2903					};
2904				};
2905			};
2906
2907			mdss_dsi0_phy: phy@c994400 {
2908				compatible = "qcom,dsi-phy-10nm-8998";
2909				reg = <0x0c994400 0x200>,
2910				      <0x0c994600 0x280>,
2911				      <0x0c994a00 0x1e0>;
2912				reg-names = "dsi_phy",
2913					    "dsi_phy_lane",
2914					    "dsi_pll";
2915
2916				clocks = <&mmcc MDSS_AHB_CLK>,
2917					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2918				clock-names = "iface", "ref";
2919
2920				#clock-cells = <1>;
2921				#phy-cells = <0>;
2922
2923				status = "disabled";
2924			};
2925
2926			mdss_dsi1: dsi@c996000 {
2927				compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2928				reg = <0x0c996000 0x400>;
2929				reg-names = "dsi_ctrl";
2930
2931				interrupt-parent = <&mdss>;
2932				interrupts = <5>;
2933
2934				clocks = <&mmcc MDSS_BYTE1_CLK>,
2935					 <&mmcc MDSS_BYTE1_INTF_CLK>,
2936					 <&mmcc MDSS_PCLK1_CLK>,
2937					 <&mmcc MDSS_ESC1_CLK>,
2938					 <&mmcc MDSS_AHB_CLK>,
2939					 <&mmcc MDSS_AXI_CLK>;
2940				clock-names = "byte",
2941					      "byte_intf",
2942					      "pixel",
2943					      "core",
2944					      "iface",
2945					      "bus";
2946				assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2947						  <&mmcc PCLK1_CLK_SRC>;
2948				assigned-clock-parents = <&mdss_dsi1_phy 0>,
2949							 <&mdss_dsi1_phy 1>;
2950
2951				operating-points-v2 = <&dsi_opp_table>;
2952				power-domains = <&rpmpd MSM8998_VDDCX>;
2953
2954				phys = <&mdss_dsi1_phy>;
2955				phy-names = "dsi";
2956
2957				#address-cells = <1>;
2958				#size-cells = <0>;
2959
2960				status = "disabled";
2961
2962				ports {
2963					#address-cells = <1>;
2964					#size-cells = <0>;
2965
2966					port@0 {
2967						reg = <0>;
2968
2969						mdss_dsi1_in: endpoint {
2970							remote-endpoint = <&dpu_intf2_out>;
2971						};
2972					};
2973
2974					port@1 {
2975						reg = <1>;
2976
2977						mdss_dsi1_out: endpoint {
2978						};
2979					};
2980				};
2981			};
2982
2983			mdss_dsi1_phy: phy@c996400 {
2984				compatible = "qcom,dsi-phy-10nm-8998";
2985				reg = <0x0c996400 0x200>,
2986				      <0x0c996600 0x280>,
2987				      <0x0c996a00 0x10e>;
2988				reg-names = "dsi_phy",
2989					    "dsi_phy_lane",
2990					    "dsi_pll";
2991
2992				clocks = <&mmcc MDSS_AHB_CLK>,
2993					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2994				clock-names = "iface",
2995					      "ref";
2996
2997				#clock-cells = <1>;
2998				#phy-cells = <0>;
2999
3000				status = "disabled";
3001			};
3002		};
3003
3004		venus: video-codec@cc00000 {
3005			compatible = "qcom,msm8998-venus";
3006			reg = <0x0cc00000 0xff000>;
3007			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
3008			power-domains = <&mmcc VIDEO_TOP_GDSC>;
3009			clocks = <&mmcc VIDEO_CORE_CLK>,
3010				 <&mmcc VIDEO_AHB_CLK>,
3011				 <&mmcc VIDEO_AXI_CLK>,
3012				 <&mmcc VIDEO_MAXI_CLK>;
3013			clock-names = "core", "iface", "bus", "mbus";
3014			iommus = <&mmss_smmu 0x400>,
3015				 <&mmss_smmu 0x401>,
3016				 <&mmss_smmu 0x40a>,
3017				 <&mmss_smmu 0x407>,
3018				 <&mmss_smmu 0x40e>,
3019				 <&mmss_smmu 0x40f>,
3020				 <&mmss_smmu 0x408>,
3021				 <&mmss_smmu 0x409>,
3022				 <&mmss_smmu 0x40b>,
3023				 <&mmss_smmu 0x40c>,
3024				 <&mmss_smmu 0x40d>,
3025				 <&mmss_smmu 0x410>,
3026				 <&mmss_smmu 0x421>,
3027				 <&mmss_smmu 0x428>,
3028				 <&mmss_smmu 0x429>,
3029				 <&mmss_smmu 0x42b>,
3030				 <&mmss_smmu 0x42c>,
3031				 <&mmss_smmu 0x42d>,
3032				 <&mmss_smmu 0x411>,
3033				 <&mmss_smmu 0x431>;
3034			memory-region = <&venus_mem>;
3035			status = "disabled";
3036
3037			video-decoder {
3038				compatible = "venus-decoder";
3039				clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
3040				clock-names = "core";
3041				power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>;
3042			};
3043
3044			video-encoder {
3045				compatible = "venus-encoder";
3046				clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
3047				clock-names = "core";
3048				power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>;
3049			};
3050		};
3051
3052		mmss_smmu: iommu@cd00000 {
3053			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3054			reg = <0x0cd00000 0x40000>;
3055			#iommu-cells = <1>;
3056
3057			clocks = <&mmcc MNOC_AHB_CLK>,
3058				 <&mmcc BIMC_SMMU_AHB_CLK>,
3059				 <&mmcc BIMC_SMMU_AXI_CLK>;
3060			clock-names = "iface-mm",
3061				      "iface-smmu",
3062				      "bus-smmu";
3063
3064			#global-interrupts = <0>;
3065			interrupts =
3066				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3067				<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3068				<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3069				<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3070				<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3071				<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3072				<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3073				<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
3074				<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3075				<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3076				<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3077				<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
3078				<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3079				<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3080				<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3081				<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3082				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
3083				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3084				<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3085				<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3086
3087			power-domains = <&mmcc BIMC_SMMU_GDSC>;
3088		};
3089
3090		remoteproc_adsp: remoteproc@17300000 {
3091			compatible = "qcom,msm8998-adsp-pas";
3092			reg = <0x17300000 0x4040>;
3093
3094			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3095					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3096					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3097					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3098					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3099			interrupt-names = "wdog", "fatal", "ready",
3100					  "handover", "stop-ack";
3101
3102			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3103			clock-names = "xo";
3104
3105			memory-region = <&adsp_mem>;
3106
3107			qcom,smem-states = <&adsp_smp2p_out 0>;
3108			qcom,smem-state-names = "stop";
3109
3110			power-domains = <&rpmpd MSM8998_VDDCX>;
3111			power-domain-names = "cx";
3112
3113			status = "disabled";
3114
3115			glink-edge {
3116				interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3117				label = "lpass";
3118				qcom,remote-pid = <2>;
3119				mboxes = <&apcs_glb 9>;
3120			};
3121		};
3122
3123		apcs_glb: mailbox@17911000 {
3124			compatible = "qcom,msm8998-apcs-hmss-global",
3125				     "qcom,msm8994-apcs-kpss-global";
3126			reg = <0x17911000 0x1000>;
3127
3128			#mbox-cells = <1>;
3129		};
3130
3131		timer@17920000 {
3132			#address-cells = <1>;
3133			#size-cells = <1>;
3134			ranges;
3135			compatible = "arm,armv7-timer-mem";
3136			reg = <0x17920000 0x1000>;
3137
3138			frame@17921000 {
3139				frame-number = <0>;
3140				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3141					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3142				reg = <0x17921000 0x1000>,
3143				      <0x17922000 0x1000>;
3144			};
3145
3146			frame@17923000 {
3147				frame-number = <1>;
3148				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3149				reg = <0x17923000 0x1000>;
3150				status = "disabled";
3151			};
3152
3153			frame@17924000 {
3154				frame-number = <2>;
3155				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3156				reg = <0x17924000 0x1000>;
3157				status = "disabled";
3158			};
3159
3160			frame@17925000 {
3161				frame-number = <3>;
3162				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3163				reg = <0x17925000 0x1000>;
3164				status = "disabled";
3165			};
3166
3167			frame@17926000 {
3168				frame-number = <4>;
3169				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3170				reg = <0x17926000 0x1000>;
3171				status = "disabled";
3172			};
3173
3174			frame@17927000 {
3175				frame-number = <5>;
3176				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3177				reg = <0x17927000 0x1000>;
3178				status = "disabled";
3179			};
3180
3181			frame@17928000 {
3182				frame-number = <6>;
3183				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3184				reg = <0x17928000 0x1000>;
3185				status = "disabled";
3186			};
3187		};
3188
3189		intc: interrupt-controller@17a00000 {
3190			compatible = "arm,gic-v3";
3191			reg = <0x17a00000 0x10000>,       /* GICD */
3192			      <0x17b00000 0x100000>;      /* GICR * 8 */
3193			#interrupt-cells = <3>;
3194			#address-cells = <1>;
3195			#size-cells = <1>;
3196			ranges;
3197			interrupt-controller;
3198			#redistributor-regions = <1>;
3199			redistributor-stride = <0x0 0x20000>;
3200			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3201		};
3202
3203		wifi: wifi@18800000 {
3204			compatible = "qcom,wcn3990-wifi";
3205			status = "disabled";
3206			reg = <0x18800000 0x800000>;
3207			reg-names = "membase";
3208			memory-region = <&wlan_msa_mem>;
3209			clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3210			clock-names = "cxo_ref_clk_pin";
3211			interrupts =
3212				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3213				<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3214				<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3215				<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3216				<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3217				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3218				<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3219				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3220				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3221				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3222				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3223				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3224			iommus = <&anoc2_smmu 0x1900>,
3225				 <&anoc2_smmu 0x1901>;
3226			qcom,snoc-host-cap-8bit-quirk;
3227			qcom,no-msa-ready-indicator;
3228		};
3229	};
3230};
3231