xref: /linux/arch/arm64/boot/dts/qcom/msm8998.dtsi (revision 906fd46a65383cd639e5eec72a047efc33045d86) 
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-msm8998.h>
6#include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8#include <dt-bindings/clock/qcom,rpmcc.h>
9#include <dt-bindings/firmware/qcom,scm.h>
10#include <dt-bindings/power/qcom-rpmpd.h>
11#include <dt-bindings/gpio/gpio.h>
12
13/ {
14	interrupt-parent = <&intc>;
15
16	qcom,msm-id = <292 0x0>;
17
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	chosen { };
22
23	memory@80000000 {
24		device_type = "memory";
25		/* We expect the bootloader to fill in the reg */
26		reg = <0x0 0x80000000 0x0 0x0>;
27	};
28
29	reserved-memory {
30		#address-cells = <2>;
31		#size-cells = <2>;
32		ranges;
33
34		hyp_mem: memory@85800000 {
35			reg = <0x0 0x85800000 0x0 0x600000>;
36			no-map;
37		};
38
39		xbl_mem: memory@85e00000 {
40			reg = <0x0 0x85e00000 0x0 0x100000>;
41			no-map;
42		};
43
44		smem_mem: smem-mem@86000000 {
45			reg = <0x0 0x86000000 0x0 0x200000>;
46			no-map;
47		};
48
49		tz_mem: memory@86200000 {
50			reg = <0x0 0x86200000 0x0 0x2d00000>;
51			no-map;
52		};
53
54		rmtfs_mem: memory@88f00000 {
55			compatible = "qcom,rmtfs-mem";
56			reg = <0x0 0x88f00000 0x0 0x200000>;
57			no-map;
58
59			qcom,client-id = <1>;
60			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
61		};
62
63		spss_mem: memory@8ab00000 {
64			reg = <0x0 0x8ab00000 0x0 0x700000>;
65			no-map;
66		};
67
68		adsp_mem: memory@8b200000 {
69			reg = <0x0 0x8b200000 0x0 0x1a00000>;
70			no-map;
71		};
72
73		mpss_mem: memory@8cc00000 {
74			reg = <0x0 0x8cc00000 0x0 0x7000000>;
75			no-map;
76		};
77
78		venus_mem: memory@93c00000 {
79			reg = <0x0 0x93c00000 0x0 0x500000>;
80			no-map;
81		};
82
83		mba_mem: memory@94100000 {
84			reg = <0x0 0x94100000 0x0 0x200000>;
85			no-map;
86		};
87
88		slpi_mem: memory@94300000 {
89			reg = <0x0 0x94300000 0x0 0xf00000>;
90			no-map;
91		};
92
93		ipa_fw_mem: memory@95200000 {
94			reg = <0x0 0x95200000 0x0 0x10000>;
95			no-map;
96		};
97
98		ipa_gsi_mem: memory@95210000 {
99			reg = <0x0 0x95210000 0x0 0x5000>;
100			no-map;
101		};
102
103		gpu_mem: memory@95600000 {
104			reg = <0x0 0x95600000 0x0 0x100000>;
105			no-map;
106		};
107
108		wlan_msa_mem: memory@95700000 {
109			reg = <0x0 0x95700000 0x0 0x100000>;
110			no-map;
111		};
112
113		mdata_mem: mpss-metadata {
114			alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
115			size = <0x0 0x4000>;
116			no-map;
117		};
118	};
119
120	clocks {
121		xo: xo-board {
122			compatible = "fixed-clock";
123			#clock-cells = <0>;
124			clock-frequency = <19200000>;
125			clock-output-names = "xo_board";
126		};
127
128		sleep_clk: sleep-clk {
129			compatible = "fixed-clock";
130			#clock-cells = <0>;
131			clock-frequency = <32764>;
132		};
133	};
134
135	cpus {
136		#address-cells = <2>;
137		#size-cells = <0>;
138
139		CPU0: cpu@0 {
140			device_type = "cpu";
141			compatible = "qcom,kryo280";
142			reg = <0x0 0x0>;
143			enable-method = "psci";
144			capacity-dmips-mhz = <1024>;
145			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
146			next-level-cache = <&L2_0>;
147			L2_0: l2-cache {
148				compatible = "cache";
149				cache-level = <2>;
150				cache-unified;
151			};
152		};
153
154		CPU1: cpu@1 {
155			device_type = "cpu";
156			compatible = "qcom,kryo280";
157			reg = <0x0 0x1>;
158			enable-method = "psci";
159			capacity-dmips-mhz = <1024>;
160			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
161			next-level-cache = <&L2_0>;
162		};
163
164		CPU2: cpu@2 {
165			device_type = "cpu";
166			compatible = "qcom,kryo280";
167			reg = <0x0 0x2>;
168			enable-method = "psci";
169			capacity-dmips-mhz = <1024>;
170			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
171			next-level-cache = <&L2_0>;
172		};
173
174		CPU3: cpu@3 {
175			device_type = "cpu";
176			compatible = "qcom,kryo280";
177			reg = <0x0 0x3>;
178			enable-method = "psci";
179			capacity-dmips-mhz = <1024>;
180			cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
181			next-level-cache = <&L2_0>;
182		};
183
184		CPU4: cpu@100 {
185			device_type = "cpu";
186			compatible = "qcom,kryo280";
187			reg = <0x0 0x100>;
188			enable-method = "psci";
189			capacity-dmips-mhz = <1536>;
190			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
191			next-level-cache = <&L2_1>;
192			L2_1: l2-cache {
193				compatible = "cache";
194				cache-level = <2>;
195				cache-unified;
196			};
197		};
198
199		CPU5: cpu@101 {
200			device_type = "cpu";
201			compatible = "qcom,kryo280";
202			reg = <0x0 0x101>;
203			enable-method = "psci";
204			capacity-dmips-mhz = <1536>;
205			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
206			next-level-cache = <&L2_1>;
207		};
208
209		CPU6: cpu@102 {
210			device_type = "cpu";
211			compatible = "qcom,kryo280";
212			reg = <0x0 0x102>;
213			enable-method = "psci";
214			capacity-dmips-mhz = <1536>;
215			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
216			next-level-cache = <&L2_1>;
217		};
218
219		CPU7: cpu@103 {
220			device_type = "cpu";
221			compatible = "qcom,kryo280";
222			reg = <0x0 0x103>;
223			enable-method = "psci";
224			capacity-dmips-mhz = <1536>;
225			cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
226			next-level-cache = <&L2_1>;
227		};
228
229		cpu-map {
230			cluster0 {
231				core0 {
232					cpu = <&CPU0>;
233				};
234
235				core1 {
236					cpu = <&CPU1>;
237				};
238
239				core2 {
240					cpu = <&CPU2>;
241				};
242
243				core3 {
244					cpu = <&CPU3>;
245				};
246			};
247
248			cluster1 {
249				core0 {
250					cpu = <&CPU4>;
251				};
252
253				core1 {
254					cpu = <&CPU5>;
255				};
256
257				core2 {
258					cpu = <&CPU6>;
259				};
260
261				core3 {
262					cpu = <&CPU7>;
263				};
264			};
265		};
266
267		idle-states {
268			entry-method = "psci";
269
270			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
271				compatible = "arm,idle-state";
272				idle-state-name = "little-retention";
273				/* CPU Retention (C2D), L2 Active */
274				arm,psci-suspend-param = <0x00000002>;
275				entry-latency-us = <81>;
276				exit-latency-us = <86>;
277				min-residency-us = <504>;
278			};
279
280			LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
281				compatible = "arm,idle-state";
282				idle-state-name = "little-power-collapse";
283				/* CPU + L2 Power Collapse (C3, D4) */
284				arm,psci-suspend-param = <0x40000003>;
285				entry-latency-us = <814>;
286				exit-latency-us = <4562>;
287				min-residency-us = <9183>;
288				local-timer-stop;
289			};
290
291			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
292				compatible = "arm,idle-state";
293				idle-state-name = "big-retention";
294				/* CPU Retention (C2D), L2 Active */
295				arm,psci-suspend-param = <0x00000002>;
296				entry-latency-us = <79>;
297				exit-latency-us = <82>;
298				min-residency-us = <1302>;
299			};
300
301			BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
302				compatible = "arm,idle-state";
303				idle-state-name = "big-power-collapse";
304				/* CPU + L2 Power Collapse (C3, D4) */
305				arm,psci-suspend-param = <0x40000003>;
306				entry-latency-us = <724>;
307				exit-latency-us = <2027>;
308				min-residency-us = <9419>;
309				local-timer-stop;
310			};
311		};
312	};
313
314	firmware {
315		scm {
316			compatible = "qcom,scm-msm8998", "qcom,scm";
317		};
318	};
319
320	dsi_opp_table: opp-table-dsi {
321		compatible = "operating-points-v2";
322
323		opp-131250000 {
324			opp-hz = /bits/ 64 <131250000>;
325			required-opps = <&rpmpd_opp_low_svs>;
326		};
327
328		opp-210000000 {
329			opp-hz = /bits/ 64 <210000000>;
330			required-opps = <&rpmpd_opp_svs>;
331		};
332
333		opp-312500000 {
334			opp-hz = /bits/ 64 <312500000>;
335			required-opps = <&rpmpd_opp_nom>;
336		};
337	};
338
339	psci {
340		compatible = "arm,psci-1.0";
341		method = "smc";
342	};
343
344	rpm: remoteproc {
345		compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
346
347		glink-edge {
348			compatible = "qcom,glink-rpm";
349
350			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
351			qcom,rpm-msg-ram = <&rpm_msg_ram>;
352			mboxes = <&apcs_glb 0>;
353
354			rpm_requests: rpm-requests {
355				compatible = "qcom,rpm-msm8998";
356				qcom,glink-channels = "rpm_requests";
357
358				rpmcc: clock-controller {
359					compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
360					clocks = <&xo>;
361					clock-names = "xo";
362					#clock-cells = <1>;
363				};
364
365				rpmpd: power-controller {
366					compatible = "qcom,msm8998-rpmpd";
367					#power-domain-cells = <1>;
368					operating-points-v2 = <&rpmpd_opp_table>;
369
370					rpmpd_opp_table: opp-table {
371						compatible = "operating-points-v2";
372
373						rpmpd_opp_ret: opp1 {
374							opp-level = <RPM_SMD_LEVEL_RETENTION>;
375						};
376
377						rpmpd_opp_ret_plus: opp2 {
378							opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
379						};
380
381						rpmpd_opp_min_svs: opp3 {
382							opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
383						};
384
385						rpmpd_opp_low_svs: opp4 {
386							opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
387						};
388
389						rpmpd_opp_svs: opp5 {
390							opp-level = <RPM_SMD_LEVEL_SVS>;
391						};
392
393						rpmpd_opp_svs_plus: opp6 {
394							opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
395						};
396
397						rpmpd_opp_nom: opp7 {
398							opp-level = <RPM_SMD_LEVEL_NOM>;
399						};
400
401						rpmpd_opp_nom_plus: opp8 {
402							opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
403						};
404
405						rpmpd_opp_turbo: opp9 {
406							opp-level = <RPM_SMD_LEVEL_TURBO>;
407						};
408
409						rpmpd_opp_turbo_plus: opp10 {
410							opp-level = <RPM_SMD_LEVEL_BINNING>;
411						};
412					};
413				};
414			};
415		};
416	};
417
418	smem {
419		compatible = "qcom,smem";
420		memory-region = <&smem_mem>;
421		hwlocks = <&tcsr_mutex 3>;
422	};
423
424	smp2p-lpass {
425		compatible = "qcom,smp2p";
426		qcom,smem = <443>, <429>;
427
428		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
429
430		mboxes = <&apcs_glb 10>;
431
432		qcom,local-pid = <0>;
433		qcom,remote-pid = <2>;
434
435		adsp_smp2p_out: master-kernel {
436			qcom,entry-name = "master-kernel";
437			#qcom,smem-state-cells = <1>;
438		};
439
440		adsp_smp2p_in: slave-kernel {
441			qcom,entry-name = "slave-kernel";
442
443			interrupt-controller;
444			#interrupt-cells = <2>;
445		};
446	};
447
448	smp2p-mpss {
449		compatible = "qcom,smp2p";
450		qcom,smem = <435>, <428>;
451		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
452		mboxes = <&apcs_glb 14>;
453		qcom,local-pid = <0>;
454		qcom,remote-pid = <1>;
455
456		modem_smp2p_out: master-kernel {
457			qcom,entry-name = "master-kernel";
458			#qcom,smem-state-cells = <1>;
459		};
460
461		modem_smp2p_in: slave-kernel {
462			qcom,entry-name = "slave-kernel";
463			interrupt-controller;
464			#interrupt-cells = <2>;
465		};
466	};
467
468	smp2p-slpi {
469		compatible = "qcom,smp2p";
470		qcom,smem = <481>, <430>;
471		interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
472		mboxes = <&apcs_glb 26>;
473		qcom,local-pid = <0>;
474		qcom,remote-pid = <3>;
475
476		slpi_smp2p_out: master-kernel {
477			qcom,entry-name = "master-kernel";
478			#qcom,smem-state-cells = <1>;
479		};
480
481		slpi_smp2p_in: slave-kernel {
482			qcom,entry-name = "slave-kernel";
483			interrupt-controller;
484			#interrupt-cells = <2>;
485		};
486	};
487
488	thermal-zones {
489		cpu0-thermal {
490			polling-delay-passive = <250>;
491			polling-delay = <1000>;
492
493			thermal-sensors = <&tsens0 1>;
494
495			trips {
496				cpu0_alert0: trip-point0 {
497					temperature = <75000>;
498					hysteresis = <2000>;
499					type = "passive";
500				};
501
502				cpu0_crit: cpu-crit {
503					temperature = <110000>;
504					hysteresis = <2000>;
505					type = "critical";
506				};
507			};
508		};
509
510		cpu1-thermal {
511			polling-delay-passive = <250>;
512			polling-delay = <1000>;
513
514			thermal-sensors = <&tsens0 2>;
515
516			trips {
517				cpu1_alert0: trip-point0 {
518					temperature = <75000>;
519					hysteresis = <2000>;
520					type = "passive";
521				};
522
523				cpu1_crit: cpu-crit {
524					temperature = <110000>;
525					hysteresis = <2000>;
526					type = "critical";
527				};
528			};
529		};
530
531		cpu2-thermal {
532			polling-delay-passive = <250>;
533			polling-delay = <1000>;
534
535			thermal-sensors = <&tsens0 3>;
536
537			trips {
538				cpu2_alert0: trip-point0 {
539					temperature = <75000>;
540					hysteresis = <2000>;
541					type = "passive";
542				};
543
544				cpu2_crit: cpu-crit {
545					temperature = <110000>;
546					hysteresis = <2000>;
547					type = "critical";
548				};
549			};
550		};
551
552		cpu3-thermal {
553			polling-delay-passive = <250>;
554			polling-delay = <1000>;
555
556			thermal-sensors = <&tsens0 4>;
557
558			trips {
559				cpu3_alert0: trip-point0 {
560					temperature = <75000>;
561					hysteresis = <2000>;
562					type = "passive";
563				};
564
565				cpu3_crit: cpu-crit {
566					temperature = <110000>;
567					hysteresis = <2000>;
568					type = "critical";
569				};
570			};
571		};
572
573		cpu4-thermal {
574			polling-delay-passive = <250>;
575			polling-delay = <1000>;
576
577			thermal-sensors = <&tsens0 7>;
578
579			trips {
580				cpu4_alert0: trip-point0 {
581					temperature = <75000>;
582					hysteresis = <2000>;
583					type = "passive";
584				};
585
586				cpu4_crit: cpu-crit {
587					temperature = <110000>;
588					hysteresis = <2000>;
589					type = "critical";
590				};
591			};
592		};
593
594		cpu5-thermal {
595			polling-delay-passive = <250>;
596			polling-delay = <1000>;
597
598			thermal-sensors = <&tsens0 8>;
599
600			trips {
601				cpu5_alert0: trip-point0 {
602					temperature = <75000>;
603					hysteresis = <2000>;
604					type = "passive";
605				};
606
607				cpu5_crit: cpu-crit {
608					temperature = <110000>;
609					hysteresis = <2000>;
610					type = "critical";
611				};
612			};
613		};
614
615		cpu6-thermal {
616			polling-delay-passive = <250>;
617			polling-delay = <1000>;
618
619			thermal-sensors = <&tsens0 9>;
620
621			trips {
622				cpu6_alert0: trip-point0 {
623					temperature = <75000>;
624					hysteresis = <2000>;
625					type = "passive";
626				};
627
628				cpu6_crit: cpu-crit {
629					temperature = <110000>;
630					hysteresis = <2000>;
631					type = "critical";
632				};
633			};
634		};
635
636		cpu7-thermal {
637			polling-delay-passive = <250>;
638			polling-delay = <1000>;
639
640			thermal-sensors = <&tsens0 10>;
641
642			trips {
643				cpu7_alert0: trip-point0 {
644					temperature = <75000>;
645					hysteresis = <2000>;
646					type = "passive";
647				};
648
649				cpu7_crit: cpu-crit {
650					temperature = <110000>;
651					hysteresis = <2000>;
652					type = "critical";
653				};
654			};
655		};
656
657		gpu-bottom-thermal {
658			polling-delay-passive = <250>;
659			polling-delay = <1000>;
660
661			thermal-sensors = <&tsens0 12>;
662
663			trips {
664				gpu1_alert0: trip-point0 {
665					temperature = <90000>;
666					hysteresis = <2000>;
667					type = "hot";
668				};
669			};
670		};
671
672		gpu-top-thermal {
673			polling-delay-passive = <250>;
674			polling-delay = <1000>;
675
676			thermal-sensors = <&tsens0 13>;
677
678			trips {
679				gpu2_alert0: trip-point0 {
680					temperature = <90000>;
681					hysteresis = <2000>;
682					type = "hot";
683				};
684			};
685		};
686
687		clust0-mhm-thermal {
688			polling-delay-passive = <250>;
689			polling-delay = <1000>;
690
691			thermal-sensors = <&tsens0 5>;
692
693			trips {
694				cluster0_mhm_alert0: trip-point0 {
695					temperature = <90000>;
696					hysteresis = <2000>;
697					type = "hot";
698				};
699			};
700		};
701
702		clust1-mhm-thermal {
703			polling-delay-passive = <250>;
704			polling-delay = <1000>;
705
706			thermal-sensors = <&tsens0 6>;
707
708			trips {
709				cluster1_mhm_alert0: trip-point0 {
710					temperature = <90000>;
711					hysteresis = <2000>;
712					type = "hot";
713				};
714			};
715		};
716
717		cluster1-l2-thermal {
718			polling-delay-passive = <250>;
719			polling-delay = <1000>;
720
721			thermal-sensors = <&tsens0 11>;
722
723			trips {
724				cluster1_l2_alert0: trip-point0 {
725					temperature = <90000>;
726					hysteresis = <2000>;
727					type = "hot";
728				};
729			};
730		};
731
732		modem-thermal {
733			polling-delay-passive = <250>;
734			polling-delay = <1000>;
735
736			thermal-sensors = <&tsens1 1>;
737
738			trips {
739				modem_alert0: trip-point0 {
740					temperature = <90000>;
741					hysteresis = <2000>;
742					type = "hot";
743				};
744			};
745		};
746
747		mem-thermal {
748			polling-delay-passive = <250>;
749			polling-delay = <1000>;
750
751			thermal-sensors = <&tsens1 2>;
752
753			trips {
754				mem_alert0: trip-point0 {
755					temperature = <90000>;
756					hysteresis = <2000>;
757					type = "hot";
758				};
759			};
760		};
761
762		wlan-thermal {
763			polling-delay-passive = <250>;
764			polling-delay = <1000>;
765
766			thermal-sensors = <&tsens1 3>;
767
768			trips {
769				wlan_alert0: trip-point0 {
770					temperature = <90000>;
771					hysteresis = <2000>;
772					type = "hot";
773				};
774			};
775		};
776
777		q6-dsp-thermal {
778			polling-delay-passive = <250>;
779			polling-delay = <1000>;
780
781			thermal-sensors = <&tsens1 4>;
782
783			trips {
784				q6_dsp_alert0: trip-point0 {
785					temperature = <90000>;
786					hysteresis = <2000>;
787					type = "hot";
788				};
789			};
790		};
791
792		camera-thermal {
793			polling-delay-passive = <250>;
794			polling-delay = <1000>;
795
796			thermal-sensors = <&tsens1 5>;
797
798			trips {
799				camera_alert0: trip-point0 {
800					temperature = <90000>;
801					hysteresis = <2000>;
802					type = "hot";
803				};
804			};
805		};
806
807		multimedia-thermal {
808			polling-delay-passive = <250>;
809			polling-delay = <1000>;
810
811			thermal-sensors = <&tsens1 6>;
812
813			trips {
814				multimedia_alert0: trip-point0 {
815					temperature = <90000>;
816					hysteresis = <2000>;
817					type = "hot";
818				};
819			};
820		};
821	};
822
823	timer {
824		compatible = "arm,armv8-timer";
825		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
826			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
827			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
828			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
829	};
830
831	soc: soc@0 {
832		#address-cells = <1>;
833		#size-cells = <1>;
834		ranges = <0 0 0 0xffffffff>;
835		compatible = "simple-bus";
836
837		gcc: clock-controller@100000 {
838			compatible = "qcom,gcc-msm8998";
839			#clock-cells = <1>;
840			#reset-cells = <1>;
841			#power-domain-cells = <1>;
842			reg = <0x00100000 0xb0000>;
843
844			clock-names = "xo", "sleep_clk";
845			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
846
847			/*
848			 * The hypervisor typically configures the memory region where these clocks
849			 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
850			 * these clocks on a device with such configuration (e.g. because they are
851			 * enabled but unused during boot-up), the device will most likely decide
852			 * to reboot.
853			 * In light of that, we are conservative here and we list all such clocks
854			 * as protected. The board dts (or a user-supplied dts) can override the
855			 * list of protected clocks if it differs from the norm, and it is in fact
856			 * desired for the HLOS to manage these clocks
857			 */
858			protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
859					   <SSC_XO>,
860					   <SSC_CNOC_AHBS_CLK>;
861		};
862
863		rpm_msg_ram: sram@778000 {
864			compatible = "qcom,rpm-msg-ram";
865			reg = <0x00778000 0x7000>;
866		};
867
868		qfprom: qfprom@784000 {
869			compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
870			reg = <0x00784000 0x621c>;
871			#address-cells = <1>;
872			#size-cells = <1>;
873
874			qusb2_hstx_trim: hstx-trim@23a {
875				reg = <0x23a 0x1>;
876				bits = <0 4>;
877			};
878		};
879
880		tsens0: thermal@10ab000 {
881			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
882			reg = <0x010ab000 0x1000>, /* TM */
883			      <0x010aa000 0x1000>; /* SROT */
884			#qcom,sensors = <14>;
885			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
886				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
887			interrupt-names = "uplow", "critical";
888			#thermal-sensor-cells = <1>;
889		};
890
891		tsens1: thermal@10ae000 {
892			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
893			reg = <0x010ae000 0x1000>, /* TM */
894			      <0x010ad000 0x1000>; /* SROT */
895			#qcom,sensors = <8>;
896			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
897				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
898			interrupt-names = "uplow", "critical";
899			#thermal-sensor-cells = <1>;
900		};
901
902		anoc1_smmu: iommu@1680000 {
903			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
904			reg = <0x01680000 0x10000>;
905			#iommu-cells = <1>;
906
907			#global-interrupts = <0>;
908			interrupts =
909				<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
910				<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
911				<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
912				<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
913				<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
914				<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
915		};
916
917		anoc2_smmu: iommu@16c0000 {
918			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
919			reg = <0x016c0000 0x40000>;
920			#iommu-cells = <1>;
921
922			#global-interrupts = <0>;
923			interrupts =
924				<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
925				<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
926				<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
927				<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
928				<GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
929				<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
930				<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
931				<GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
932				<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
933				<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
934		};
935
936		pcie0: pcie@1c00000 {
937			compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
938			reg = <0x01c00000 0x2000>,
939			      <0x1b000000 0xf1d>,
940			      <0x1b000f20 0xa8>,
941			      <0x1b100000 0x100000>;
942			reg-names = "parf", "dbi", "elbi", "config";
943			device_type = "pci";
944			linux,pci-domain = <0>;
945			bus-range = <0x00 0xff>;
946			#address-cells = <3>;
947			#size-cells = <2>;
948			num-lanes = <1>;
949			phys = <&pcie_phy>;
950			phy-names = "pciephy";
951			status = "disabled";
952
953			ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
954				 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
955
956			#interrupt-cells = <1>;
957			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
958			interrupt-names = "msi";
959			interrupt-map-mask = <0 0 0 0x7>;
960			interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
961					<0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
962					<0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
963					<0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
964
965			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
966				 <&gcc GCC_PCIE_0_AUX_CLK>,
967				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
968				 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
969				 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
970			clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
971
972			power-domains = <&gcc PCIE_0_GDSC>;
973			iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
974			perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
975
976			pcie@0 {
977				device_type = "pci";
978				reg = <0x0 0x0 0x0 0x0 0x0>;
979				bus-range = <0x01 0xff>;
980
981				#address-cells = <3>;
982				#size-cells = <2>;
983				ranges;
984			};
985		};
986
987		pcie_phy: phy@1c06000 {
988			compatible = "qcom,msm8998-qmp-pcie-phy";
989			reg = <0x01c06000 0x1000>;
990			status = "disabled";
991
992			clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
993				 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
994				 <&gcc GCC_PCIE_CLKREF_CLK>,
995				 <&gcc GCC_PCIE_0_PIPE_CLK>;
996			clock-names = "aux",
997				      "cfg_ahb",
998				      "ref",
999				      "pipe";
1000
1001			clock-output-names = "pcie_0_pipe_clk_src";
1002			#clock-cells = <0>;
1003
1004			#phy-cells = <0>;
1005
1006			resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
1007			reset-names = "phy", "common";
1008
1009			vdda-phy-supply = <&vreg_l1a_0p875>;
1010			vdda-pll-supply = <&vreg_l2a_1p2>;
1011		};
1012
1013		ufshc: ufshc@1da4000 {
1014			compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1015			reg = <0x01da4000 0x2500>;
1016			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1017			phys = <&ufsphy>;
1018			phy-names = "ufsphy";
1019			lanes-per-direction = <2>;
1020			power-domains = <&gcc UFS_GDSC>;
1021			status = "disabled";
1022			#reset-cells = <1>;
1023
1024			clock-names =
1025				"core_clk",
1026				"bus_aggr_clk",
1027				"iface_clk",
1028				"core_clk_unipro",
1029				"ref_clk",
1030				"tx_lane0_sync_clk",
1031				"rx_lane0_sync_clk",
1032				"rx_lane1_sync_clk";
1033			clocks =
1034				<&gcc GCC_UFS_AXI_CLK>,
1035				<&gcc GCC_AGGRE1_UFS_AXI_CLK>,
1036				<&gcc GCC_UFS_AHB_CLK>,
1037				<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1038				<&rpmcc RPM_SMD_LN_BB_CLK1>,
1039				<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1040				<&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
1041				<&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
1042			freq-table-hz =
1043				<50000000 200000000>,
1044				<0 0>,
1045				<0 0>,
1046				<37500000 150000000>,
1047				<0 0>,
1048				<0 0>,
1049				<0 0>,
1050				<0 0>;
1051
1052			resets = <&gcc GCC_UFS_BCR>;
1053			reset-names = "rst";
1054		};
1055
1056		ufsphy: phy@1da7000 {
1057			compatible = "qcom,msm8998-qmp-ufs-phy";
1058			reg = <0x01da7000 0x1000>;
1059
1060			clocks = <&rpmcc RPM_SMD_LN_BB_CLK1>,
1061				 <&gcc GCC_UFS_PHY_AUX_CLK>,
1062				 <&gcc GCC_UFS_CLKREF_CLK>;
1063			clock-names = "ref",
1064				      "ref_aux",
1065				      "qref";
1066
1067			reset-names = "ufsphy";
1068			resets = <&ufshc 0>;
1069
1070			#phy-cells = <0>;
1071			status = "disabled";
1072		};
1073
1074		tcsr_mutex: hwlock@1f40000 {
1075			compatible = "qcom,tcsr-mutex";
1076			reg = <0x01f40000 0x20000>;
1077			#hwlock-cells = <1>;
1078		};
1079
1080		tcsr_regs_1: syscon@1f60000 {
1081			compatible = "qcom,msm8998-tcsr", "syscon";
1082			reg = <0x01f60000 0x20000>;
1083		};
1084
1085		tcsr_regs_2: syscon@1fc0000 {
1086			compatible = "qcom,msm8998-tcsr", "syscon";
1087			reg = <0x01fc0000 0x26000>;
1088		};
1089
1090		tlmm: pinctrl@3400000 {
1091			compatible = "qcom,msm8998-pinctrl";
1092			reg = <0x03400000 0xc00000>;
1093			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1094			gpio-ranges = <&tlmm 0 0 150>;
1095			gpio-controller;
1096			#gpio-cells = <2>;
1097			interrupt-controller;
1098			#interrupt-cells = <2>;
1099
1100			sdc2_on: sdc2-on-state {
1101				clk-pins {
1102					pins = "sdc2_clk";
1103					drive-strength = <16>;
1104					bias-disable;
1105				};
1106
1107				cmd-pins {
1108					pins = "sdc2_cmd";
1109					drive-strength = <10>;
1110					bias-pull-up;
1111				};
1112
1113				data-pins {
1114					pins = "sdc2_data";
1115					drive-strength = <10>;
1116					bias-pull-up;
1117				};
1118			};
1119
1120			sdc2_off: sdc2-off-state {
1121				clk-pins {
1122					pins = "sdc2_clk";
1123					drive-strength = <2>;
1124					bias-disable;
1125				};
1126
1127				cmd-pins {
1128					pins = "sdc2_cmd";
1129					drive-strength = <2>;
1130					bias-pull-up;
1131				};
1132
1133				data-pins {
1134					pins = "sdc2_data";
1135					drive-strength = <2>;
1136					bias-pull-up;
1137				};
1138			};
1139
1140			sdc2_cd: sdc2-cd-state {
1141				pins = "gpio95";
1142				function = "gpio";
1143				bias-pull-up;
1144				drive-strength = <2>;
1145			};
1146
1147			blsp1_uart3_on: blsp1-uart3-on-state {
1148				tx-pins {
1149					pins = "gpio45";
1150					function = "blsp_uart3_a";
1151					drive-strength = <2>;
1152					bias-disable;
1153				};
1154
1155				rx-pins {
1156					pins = "gpio46";
1157					function = "blsp_uart3_a";
1158					drive-strength = <2>;
1159					bias-disable;
1160				};
1161
1162				cts-pins {
1163					pins = "gpio47";
1164					function = "blsp_uart3_a";
1165					drive-strength = <2>;
1166					bias-disable;
1167				};
1168
1169				rfr-pins {
1170					pins = "gpio48";
1171					function = "blsp_uart3_a";
1172					drive-strength = <2>;
1173					bias-disable;
1174				};
1175			};
1176
1177			blsp1_i2c1_default: blsp1-i2c1-default-state {
1178				pins = "gpio2", "gpio3";
1179				function = "blsp_i2c1";
1180				drive-strength = <2>;
1181				bias-disable;
1182			};
1183
1184			blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1185				pins = "gpio2", "gpio3";
1186				function = "blsp_i2c1";
1187				drive-strength = <2>;
1188				bias-pull-up;
1189			};
1190
1191			blsp1_i2c2_default: blsp1-i2c2-default-state {
1192				pins = "gpio32", "gpio33";
1193				function = "blsp_i2c2";
1194				drive-strength = <2>;
1195				bias-disable;
1196			};
1197
1198			blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1199				pins = "gpio32", "gpio33";
1200				function = "blsp_i2c2";
1201				drive-strength = <2>;
1202				bias-pull-up;
1203			};
1204
1205			blsp1_i2c3_default: blsp1-i2c3-default-state {
1206				pins = "gpio47", "gpio48";
1207				function = "blsp_i2c3";
1208				drive-strength = <2>;
1209				bias-disable;
1210			};
1211
1212			blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1213				pins = "gpio47", "gpio48";
1214				function = "blsp_i2c3";
1215				drive-strength = <2>;
1216				bias-pull-up;
1217			};
1218
1219			blsp1_i2c4_default: blsp1-i2c4-default-state {
1220				pins = "gpio10", "gpio11";
1221				function = "blsp_i2c4";
1222				drive-strength = <2>;
1223				bias-disable;
1224			};
1225
1226			blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1227				pins = "gpio10", "gpio11";
1228				function = "blsp_i2c4";
1229				drive-strength = <2>;
1230				bias-pull-up;
1231			};
1232
1233			blsp1_i2c5_default: blsp1-i2c5-default-state {
1234				pins = "gpio87", "gpio88";
1235				function = "blsp_i2c5";
1236				drive-strength = <2>;
1237				bias-disable;
1238			};
1239
1240			blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1241				pins = "gpio87", "gpio88";
1242				function = "blsp_i2c5";
1243				drive-strength = <2>;
1244				bias-pull-up;
1245			};
1246
1247			blsp1_i2c6_default: blsp1-i2c6-default-state {
1248				pins = "gpio43", "gpio44";
1249				function = "blsp_i2c6";
1250				drive-strength = <2>;
1251				bias-disable;
1252			};
1253
1254			blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1255				pins = "gpio43", "gpio44";
1256				function = "blsp_i2c6";
1257				drive-strength = <2>;
1258				bias-pull-up;
1259			};
1260
1261			blsp1_spi_b_default: blsp1-spi-b-default-state {
1262				pins = "gpio23", "gpio28";
1263				function = "blsp1_spi_b";
1264				drive-strength = <6>;
1265				bias-disable;
1266			};
1267
1268			blsp1_spi1_default: blsp1-spi1-default-state {
1269				pins = "gpio0", "gpio1", "gpio2", "gpio3";
1270				function = "blsp_spi1";
1271				drive-strength = <6>;
1272				bias-disable;
1273			};
1274
1275			blsp1_spi2_default: blsp1-spi2-default-state {
1276				pins = "gpio31", "gpio34", "gpio32", "gpio33";
1277				function = "blsp_spi2";
1278				drive-strength = <6>;
1279				bias-disable;
1280			};
1281
1282			blsp1_spi3_default: blsp1-spi3-default-state {
1283				pins = "gpio45", "gpio46", "gpio47", "gpio48";
1284				function = "blsp_spi2";
1285				drive-strength = <6>;
1286				bias-disable;
1287			};
1288
1289			blsp1_spi4_default: blsp1-spi4-default-state {
1290				pins = "gpio8", "gpio9", "gpio10", "gpio11";
1291				function = "blsp_spi4";
1292				drive-strength = <6>;
1293				bias-disable;
1294			};
1295
1296			blsp1_spi5_default: blsp1-spi5-default-state {
1297				pins = "gpio85", "gpio86", "gpio87", "gpio88";
1298				function = "blsp_spi5";
1299				drive-strength = <6>;
1300				bias-disable;
1301			};
1302
1303			blsp1_spi6_default: blsp1-spi6-default-state {
1304				pins = "gpio41", "gpio42", "gpio43", "gpio44";
1305				function = "blsp_spi6";
1306				drive-strength = <6>;
1307				bias-disable;
1308			};
1309
1310
1311			/* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
1312			blsp2_i2c1_default: blsp2-i2c1-default-state {
1313				pins = "gpio55", "gpio56";
1314				function = "blsp_i2c7";
1315				drive-strength = <2>;
1316				bias-disable;
1317			};
1318
1319			blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1320				pins = "gpio55", "gpio56";
1321				function = "blsp_i2c7";
1322				drive-strength = <2>;
1323				bias-pull-up;
1324			};
1325
1326			blsp2_i2c2_default: blsp2-i2c2-default-state {
1327				pins = "gpio6", "gpio7";
1328				function = "blsp_i2c8";
1329				drive-strength = <2>;
1330				bias-disable;
1331			};
1332
1333			blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1334				pins = "gpio6", "gpio7";
1335				function = "blsp_i2c8";
1336				drive-strength = <2>;
1337				bias-pull-up;
1338			};
1339
1340			blsp2_i2c3_default: blsp2-i2c3-default-state {
1341				pins = "gpio51", "gpio52";
1342				function = "blsp_i2c9";
1343				drive-strength = <2>;
1344				bias-disable;
1345			};
1346
1347			blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1348				pins = "gpio51", "gpio52";
1349				function = "blsp_i2c9";
1350				drive-strength = <2>;
1351				bias-pull-up;
1352			};
1353
1354			blsp2_i2c4_default: blsp2-i2c4-default-state {
1355				pins = "gpio67", "gpio68";
1356				function = "blsp_i2c10";
1357				drive-strength = <2>;
1358				bias-disable;
1359			};
1360
1361			blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1362				pins = "gpio67", "gpio68";
1363				function = "blsp_i2c10";
1364				drive-strength = <2>;
1365				bias-pull-up;
1366			};
1367
1368			blsp2_i2c5_default: blsp2-i2c5-default-state {
1369				pins = "gpio60", "gpio61";
1370				function = "blsp_i2c11";
1371				drive-strength = <2>;
1372				bias-disable;
1373			};
1374
1375			blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1376				pins = "gpio60", "gpio61";
1377				function = "blsp_i2c11";
1378				drive-strength = <2>;
1379				bias-pull-up;
1380			};
1381
1382			blsp2_i2c6_default: blsp2-i2c6-default-state {
1383				pins = "gpio83", "gpio84";
1384				function = "blsp_i2c12";
1385				drive-strength = <2>;
1386				bias-disable;
1387			};
1388
1389			blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1390				pins = "gpio83", "gpio84";
1391				function = "blsp_i2c12";
1392				drive-strength = <2>;
1393				bias-pull-up;
1394			};
1395
1396			blsp2_spi1_default: blsp2-spi1-default-state {
1397				pins = "gpio53", "gpio54", "gpio55", "gpio56";
1398				function = "blsp_spi7";
1399				drive-strength = <6>;
1400				bias-disable;
1401			};
1402
1403			blsp2_spi2_default: blsp2-spi2-default-state {
1404				pins = "gpio4", "gpio5", "gpio6", "gpio7";
1405				function = "blsp_spi8";
1406				drive-strength = <6>;
1407				bias-disable;
1408			};
1409
1410			blsp2_spi3_default: blsp2-spi3-default-state {
1411				pins = "gpio49", "gpio50", "gpio51", "gpio52";
1412				function = "blsp_spi9";
1413				drive-strength = <6>;
1414				bias-disable;
1415			};
1416
1417			blsp2_spi4_default: blsp2-spi4-default-state {
1418				pins = "gpio65", "gpio66", "gpio67", "gpio68";
1419				function = "blsp_spi10";
1420				drive-strength = <6>;
1421				bias-disable;
1422			};
1423
1424			blsp2_spi5_default: blsp2-spi5-default-state {
1425				pins = "gpio58", "gpio59", "gpio60", "gpio61";
1426				function = "blsp_spi11";
1427				drive-strength = <6>;
1428				bias-disable;
1429			};
1430
1431			blsp2_spi6_default: blsp2-spi6-default-state {
1432				pins = "gpio81", "gpio82", "gpio83", "gpio84";
1433				function = "blsp_spi12";
1434				drive-strength = <6>;
1435				bias-disable;
1436			};
1437		};
1438
1439		remoteproc_mss: remoteproc@4080000 {
1440			compatible = "qcom,msm8998-mss-pil";
1441			reg = <0x04080000 0x100>, <0x04180000 0x20>;
1442			reg-names = "qdsp6", "rmb";
1443
1444			interrupts-extended =
1445				<&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
1446				<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1447				<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1448				<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1449				<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1450				<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1451			interrupt-names = "wdog", "fatal", "ready",
1452					  "handover", "stop-ack",
1453					  "shutdown-ack";
1454
1455			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1456				 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
1457				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
1458				 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
1459				 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1460				 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
1461				 <&rpmcc RPM_SMD_QDSS_CLK>,
1462				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1463			clock-names = "iface", "bus", "mem", "gpll0_mss",
1464				      "snoc_axi", "mnoc_axi", "qdss", "xo";
1465
1466			qcom,smem-states = <&modem_smp2p_out 0>;
1467			qcom,smem-state-names = "stop";
1468
1469			resets = <&gcc GCC_MSS_RESTART>;
1470			reset-names = "mss_restart";
1471
1472			qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1473
1474			power-domains = <&rpmpd MSM8998_VDDCX>,
1475					<&rpmpd MSM8998_VDDMX>;
1476			power-domain-names = "cx", "mx";
1477
1478			status = "disabled";
1479
1480			mba {
1481				memory-region = <&mba_mem>;
1482			};
1483
1484			mpss {
1485				memory-region = <&mpss_mem>;
1486			};
1487
1488			metadata {
1489				memory-region = <&mdata_mem>;
1490			};
1491
1492			glink-edge {
1493				interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
1494				label = "modem";
1495				qcom,remote-pid = <1>;
1496				mboxes = <&apcs_glb 15>;
1497			};
1498		};
1499
1500		adreno_gpu: gpu@5000000 {
1501			compatible = "qcom,adreno-540.1", "qcom,adreno";
1502			reg = <0x05000000 0x40000>;
1503			reg-names = "kgsl_3d0_reg_memory";
1504
1505			clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1506				<&gpucc RBBMTIMER_CLK>,
1507				<&gcc GCC_BIMC_GFX_CLK>,
1508				<&gcc GCC_GPU_BIMC_GFX_CLK>,
1509				<&gpucc RBCPR_CLK>,
1510				<&gpucc GFX3D_CLK>;
1511			clock-names = "iface",
1512				"rbbmtimer",
1513				"mem",
1514				"mem_iface",
1515				"rbcpr",
1516				"core";
1517
1518			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1519			iommus = <&adreno_smmu 0>;
1520			operating-points-v2 = <&gpu_opp_table>;
1521			power-domains = <&rpmpd MSM8998_VDDMX>;
1522			status = "disabled";
1523
1524			gpu_opp_table: opp-table {
1525				compatible = "operating-points-v2";
1526				opp-710000097 {
1527					opp-hz = /bits/ 64 <710000097>;
1528					opp-level = <RPM_SMD_LEVEL_TURBO>;
1529					opp-supported-hw = <0xff>;
1530				};
1531
1532				opp-670000048 {
1533					opp-hz = /bits/ 64 <670000048>;
1534					opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1535					opp-supported-hw = <0xff>;
1536				};
1537
1538				opp-596000097 {
1539					opp-hz = /bits/ 64 <596000097>;
1540					opp-level = <RPM_SMD_LEVEL_NOM>;
1541					opp-supported-hw = <0xff>;
1542				};
1543
1544				opp-515000097 {
1545					opp-hz = /bits/ 64 <515000097>;
1546					opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1547					opp-supported-hw = <0xff>;
1548				};
1549
1550				opp-414000000 {
1551					opp-hz = /bits/ 64 <414000000>;
1552					opp-level = <RPM_SMD_LEVEL_SVS>;
1553					opp-supported-hw = <0xff>;
1554				};
1555
1556				opp-342000000 {
1557					opp-hz = /bits/ 64 <342000000>;
1558					opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1559					opp-supported-hw = <0xff>;
1560				};
1561
1562				opp-257000000 {
1563					opp-hz = /bits/ 64 <257000000>;
1564					opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1565					opp-supported-hw = <0xff>;
1566				};
1567			};
1568		};
1569
1570		adreno_smmu: iommu@5040000 {
1571			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1572			reg = <0x05040000 0x10000>;
1573			clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
1574				 <&gcc GCC_BIMC_GFX_CLK>,
1575				 <&gcc GCC_GPU_BIMC_GFX_CLK>;
1576			clock-names = "iface", "mem", "mem_iface";
1577
1578			#global-interrupts = <0>;
1579			#iommu-cells = <1>;
1580			interrupts =
1581				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1582				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1583				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1584			/*
1585			 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1586			 * GPU-CX for SMMU but we need both of them up for Adreno.
1587			 * Contemporarily, we also need to manage the VDDMX rpmpd
1588			 * domain in the Adreno driver.
1589			 * Enable GPU CX/GX GDSCs here so that we can manage the
1590			 * SoC VDDMX RPM Power Domain in the Adreno driver.
1591			 */
1592			power-domains = <&gpucc GPU_GX_GDSC>;
1593			status = "disabled";
1594		};
1595
1596		gpucc: clock-controller@5065000 {
1597			compatible = "qcom,msm8998-gpucc";
1598			#clock-cells = <1>;
1599			#reset-cells = <1>;
1600			#power-domain-cells = <1>;
1601			reg = <0x05065000 0x9000>;
1602
1603			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1604				 <&gcc GCC_GPU_GPLL0_CLK>;
1605			clock-names = "xo",
1606				      "gpll0";
1607		};
1608
1609		remoteproc_slpi: remoteproc@5800000 {
1610			compatible = "qcom,msm8998-slpi-pas";
1611			reg = <0x05800000 0x4040>;
1612
1613			interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1614					      <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1615					      <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1616					      <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1617					      <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1618			interrupt-names = "wdog", "fatal", "ready",
1619					  "handover", "stop-ack";
1620
1621			px-supply = <&vreg_lvs2a_1p8>;
1622
1623			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1624			clock-names = "xo";
1625
1626			memory-region = <&slpi_mem>;
1627
1628			qcom,smem-states = <&slpi_smp2p_out 0>;
1629			qcom,smem-state-names = "stop";
1630
1631			power-domains = <&rpmpd MSM8998_SSCCX>;
1632			power-domain-names = "ssc_cx";
1633
1634			status = "disabled";
1635
1636			glink-edge {
1637				interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
1638				label = "dsps";
1639				qcom,remote-pid = <3>;
1640				mboxes = <&apcs_glb 27>;
1641			};
1642		};
1643
1644		stm: stm@6002000 {
1645			compatible = "arm,coresight-stm", "arm,primecell";
1646			reg = <0x06002000 0x1000>,
1647			      <0x16280000 0x180000>;
1648			reg-names = "stm-base", "stm-stimulus-base";
1649			status = "disabled";
1650
1651			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1652			clock-names = "apb_pclk", "atclk";
1653
1654			out-ports {
1655				port {
1656					stm_out: endpoint {
1657						remote-endpoint = <&funnel0_in7>;
1658					};
1659				};
1660			};
1661		};
1662
1663		funnel1: funnel@6041000 {
1664			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1665			reg = <0x06041000 0x1000>;
1666			status = "disabled";
1667
1668			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1669			clock-names = "apb_pclk", "atclk";
1670
1671			out-ports {
1672				port {
1673					funnel0_out: endpoint {
1674						remote-endpoint =
1675						  <&merge_funnel_in0>;
1676					};
1677				};
1678			};
1679
1680			in-ports {
1681				#address-cells = <1>;
1682				#size-cells = <0>;
1683
1684				port@7 {
1685					reg = <7>;
1686					funnel0_in7: endpoint {
1687						remote-endpoint = <&stm_out>;
1688					};
1689				};
1690			};
1691		};
1692
1693		funnel2: funnel@6042000 {
1694			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1695			reg = <0x06042000 0x1000>;
1696			status = "disabled";
1697
1698			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1699			clock-names = "apb_pclk", "atclk";
1700
1701			out-ports {
1702				port {
1703					funnel1_out: endpoint {
1704						remote-endpoint =
1705						  <&merge_funnel_in1>;
1706					};
1707				};
1708			};
1709
1710			in-ports {
1711				#address-cells = <1>;
1712				#size-cells = <0>;
1713
1714				port@6 {
1715					reg = <6>;
1716					funnel1_in6: endpoint {
1717						remote-endpoint =
1718						  <&apss_merge_funnel_out>;
1719					};
1720				};
1721			};
1722		};
1723
1724		funnel3: funnel@6045000 {
1725			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1726			reg = <0x06045000 0x1000>;
1727			status = "disabled";
1728
1729			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1730			clock-names = "apb_pclk", "atclk";
1731
1732			out-ports {
1733				port {
1734					merge_funnel_out: endpoint {
1735						remote-endpoint =
1736						  <&etf_in>;
1737					};
1738				};
1739			};
1740
1741			in-ports {
1742				#address-cells = <1>;
1743				#size-cells = <0>;
1744
1745				port@0 {
1746					reg = <0>;
1747					merge_funnel_in0: endpoint {
1748						remote-endpoint =
1749						  <&funnel0_out>;
1750					};
1751				};
1752
1753				port@1 {
1754					reg = <1>;
1755					merge_funnel_in1: endpoint {
1756						remote-endpoint =
1757						  <&funnel1_out>;
1758					};
1759				};
1760			};
1761		};
1762
1763		replicator1: replicator@6046000 {
1764			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1765			reg = <0x06046000 0x1000>;
1766			status = "disabled";
1767
1768			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1769			clock-names = "apb_pclk", "atclk";
1770
1771			out-ports {
1772				port {
1773					replicator_out: endpoint {
1774						remote-endpoint = <&etr_in>;
1775					};
1776				};
1777			};
1778
1779			in-ports {
1780				port {
1781					replicator_in: endpoint {
1782						remote-endpoint = <&etf_out>;
1783					};
1784				};
1785			};
1786		};
1787
1788		etf: etf@6047000 {
1789			compatible = "arm,coresight-tmc", "arm,primecell";
1790			reg = <0x06047000 0x1000>;
1791			status = "disabled";
1792
1793			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1794			clock-names = "apb_pclk", "atclk";
1795
1796			out-ports {
1797				port {
1798					etf_out: endpoint {
1799						remote-endpoint =
1800						  <&replicator_in>;
1801					};
1802				};
1803			};
1804
1805			in-ports {
1806				port {
1807					etf_in: endpoint {
1808						remote-endpoint =
1809						  <&merge_funnel_out>;
1810					};
1811				};
1812			};
1813		};
1814
1815		etr: etr@6048000 {
1816			compatible = "arm,coresight-tmc", "arm,primecell";
1817			reg = <0x06048000 0x1000>;
1818			status = "disabled";
1819
1820			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1821			clock-names = "apb_pclk", "atclk";
1822			arm,scatter-gather;
1823
1824			in-ports {
1825				port {
1826					etr_in: endpoint {
1827						remote-endpoint =
1828						  <&replicator_out>;
1829					};
1830				};
1831			};
1832		};
1833
1834		etm1: etm@7840000 {
1835			compatible = "arm,coresight-etm4x", "arm,primecell";
1836			reg = <0x07840000 0x1000>;
1837			status = "disabled";
1838
1839			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1840			clock-names = "apb_pclk", "atclk";
1841
1842			cpu = <&CPU0>;
1843
1844			out-ports {
1845				port {
1846					etm0_out: endpoint {
1847						remote-endpoint =
1848						  <&apss_funnel_in0>;
1849					};
1850				};
1851			};
1852		};
1853
1854		etm2: etm@7940000 {
1855			compatible = "arm,coresight-etm4x", "arm,primecell";
1856			reg = <0x07940000 0x1000>;
1857			status = "disabled";
1858
1859			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1860			clock-names = "apb_pclk", "atclk";
1861
1862			cpu = <&CPU1>;
1863
1864			out-ports {
1865				port {
1866					etm1_out: endpoint {
1867						remote-endpoint =
1868						  <&apss_funnel_in1>;
1869					};
1870				};
1871			};
1872		};
1873
1874		etm3: etm@7a40000 {
1875			compatible = "arm,coresight-etm4x", "arm,primecell";
1876			reg = <0x07a40000 0x1000>;
1877			status = "disabled";
1878
1879			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1880			clock-names = "apb_pclk", "atclk";
1881
1882			cpu = <&CPU2>;
1883
1884			out-ports {
1885				port {
1886					etm2_out: endpoint {
1887						remote-endpoint =
1888						  <&apss_funnel_in2>;
1889					};
1890				};
1891			};
1892		};
1893
1894		etm4: etm@7b40000 {
1895			compatible = "arm,coresight-etm4x", "arm,primecell";
1896			reg = <0x07b40000 0x1000>;
1897			status = "disabled";
1898
1899			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1900			clock-names = "apb_pclk", "atclk";
1901
1902			cpu = <&CPU3>;
1903
1904			out-ports {
1905				port {
1906					etm3_out: endpoint {
1907						remote-endpoint =
1908						  <&apss_funnel_in3>;
1909					};
1910				};
1911			};
1912		};
1913
1914		funnel4: funnel@7b60000 { /* APSS Funnel */
1915			compatible = "arm,coresight-etm4x", "arm,primecell";
1916			reg = <0x07b60000 0x1000>;
1917			status = "disabled";
1918
1919			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1920			clock-names = "apb_pclk", "atclk";
1921
1922			out-ports {
1923				port {
1924					apss_funnel_out: endpoint {
1925						remote-endpoint =
1926						  <&apss_merge_funnel_in>;
1927					};
1928				};
1929			};
1930
1931			in-ports {
1932				#address-cells = <1>;
1933				#size-cells = <0>;
1934
1935				port@0 {
1936					reg = <0>;
1937					apss_funnel_in0: endpoint {
1938						remote-endpoint =
1939						  <&etm0_out>;
1940					};
1941				};
1942
1943				port@1 {
1944					reg = <1>;
1945					apss_funnel_in1: endpoint {
1946						remote-endpoint =
1947						  <&etm1_out>;
1948					};
1949				};
1950
1951				port@2 {
1952					reg = <2>;
1953					apss_funnel_in2: endpoint {
1954						remote-endpoint =
1955						  <&etm2_out>;
1956					};
1957				};
1958
1959				port@3 {
1960					reg = <3>;
1961					apss_funnel_in3: endpoint {
1962						remote-endpoint =
1963						  <&etm3_out>;
1964					};
1965				};
1966
1967				port@4 {
1968					reg = <4>;
1969					apss_funnel_in4: endpoint {
1970						remote-endpoint =
1971						  <&etm4_out>;
1972					};
1973				};
1974
1975				port@5 {
1976					reg = <5>;
1977					apss_funnel_in5: endpoint {
1978						remote-endpoint =
1979						  <&etm5_out>;
1980					};
1981				};
1982
1983				port@6 {
1984					reg = <6>;
1985					apss_funnel_in6: endpoint {
1986						remote-endpoint =
1987						  <&etm6_out>;
1988					};
1989				};
1990
1991				port@7 {
1992					reg = <7>;
1993					apss_funnel_in7: endpoint {
1994						remote-endpoint =
1995						  <&etm7_out>;
1996					};
1997				};
1998			};
1999		};
2000
2001		funnel5: funnel@7b70000 {
2002			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2003			reg = <0x07b70000 0x1000>;
2004			status = "disabled";
2005
2006			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2007			clock-names = "apb_pclk", "atclk";
2008
2009			out-ports {
2010				port {
2011					apss_merge_funnel_out: endpoint {
2012						remote-endpoint =
2013						  <&funnel1_in6>;
2014					};
2015				};
2016			};
2017
2018			in-ports {
2019				port {
2020					apss_merge_funnel_in: endpoint {
2021						remote-endpoint =
2022						  <&apss_funnel_out>;
2023					};
2024				};
2025			};
2026		};
2027
2028		etm5: etm@7c40000 {
2029			compatible = "arm,coresight-etm4x", "arm,primecell";
2030			reg = <0x07c40000 0x1000>;
2031			status = "disabled";
2032
2033			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2034			clock-names = "apb_pclk", "atclk";
2035
2036			cpu = <&CPU4>;
2037
2038			out-ports {
2039				port {
2040					etm4_out: endpoint {
2041						remote-endpoint = <&apss_funnel_in4>;
2042					};
2043				};
2044			};
2045		};
2046
2047		etm6: etm@7d40000 {
2048			compatible = "arm,coresight-etm4x", "arm,primecell";
2049			reg = <0x07d40000 0x1000>;
2050			status = "disabled";
2051
2052			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2053			clock-names = "apb_pclk", "atclk";
2054
2055			cpu = <&CPU5>;
2056
2057			out-ports {
2058				port {
2059					etm5_out: endpoint {
2060						remote-endpoint = <&apss_funnel_in5>;
2061					};
2062				};
2063			};
2064		};
2065
2066		etm7: etm@7e40000 {
2067			compatible = "arm,coresight-etm4x", "arm,primecell";
2068			reg = <0x07e40000 0x1000>;
2069			status = "disabled";
2070
2071			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2072			clock-names = "apb_pclk", "atclk";
2073
2074			cpu = <&CPU6>;
2075
2076			out-ports {
2077				port {
2078					etm6_out: endpoint {
2079						remote-endpoint = <&apss_funnel_in6>;
2080					};
2081				};
2082			};
2083		};
2084
2085		etm8: etm@7f40000 {
2086			compatible = "arm,coresight-etm4x", "arm,primecell";
2087			reg = <0x07f40000 0x1000>;
2088			status = "disabled";
2089
2090			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
2091			clock-names = "apb_pclk", "atclk";
2092
2093			cpu = <&CPU7>;
2094
2095			out-ports {
2096				port {
2097					etm7_out: endpoint {
2098						remote-endpoint = <&apss_funnel_in7>;
2099					};
2100				};
2101			};
2102		};
2103
2104		sram@290000 {
2105			compatible = "qcom,rpm-stats";
2106			reg = <0x00290000 0x10000>;
2107		};
2108
2109		spmi_bus: spmi@800f000 {
2110			compatible = "qcom,spmi-pmic-arb";
2111			reg = <0x0800f000 0x1000>,
2112			      <0x08400000 0x1000000>,
2113			      <0x09400000 0x1000000>,
2114			      <0x0a400000 0x220000>,
2115			      <0x0800a000 0x3000>;
2116			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2117			interrupt-names = "periph_irq";
2118			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
2119			qcom,ee = <0>;
2120			qcom,channel = <0>;
2121			#address-cells = <2>;
2122			#size-cells = <0>;
2123			interrupt-controller;
2124			#interrupt-cells = <4>;
2125		};
2126
2127		usb3: usb@a8f8800 {
2128			compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2129			reg = <0x0a8f8800 0x400>;
2130			status = "disabled";
2131			#address-cells = <1>;
2132			#size-cells = <1>;
2133			ranges;
2134
2135			clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
2136				 <&gcc GCC_USB30_MASTER_CLK>,
2137				 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
2138				 <&gcc GCC_USB30_SLEEP_CLK>,
2139				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
2140			clock-names = "cfg_noc",
2141				      "core",
2142				      "iface",
2143				      "sleep",
2144				      "mock_utmi";
2145
2146			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2147					  <&gcc GCC_USB30_MASTER_CLK>;
2148			assigned-clock-rates = <19200000>, <120000000>;
2149
2150			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
2151				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
2152				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
2153			interrupt-names = "pwr_event",
2154					  "qusb2_phy",
2155					  "ss_phy_irq";
2156
2157			power-domains = <&gcc USB_30_GDSC>;
2158
2159			resets = <&gcc GCC_USB_30_BCR>;
2160
2161			usb3_dwc3: usb@a800000 {
2162				compatible = "snps,dwc3";
2163				reg = <0x0a800000 0xcd00>;
2164				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
2165				snps,dis_u2_susphy_quirk;
2166				snps,dis_enblslpm_quirk;
2167				phys = <&qusb2phy>, <&usb3phy>;
2168				phy-names = "usb2-phy", "usb3-phy";
2169				snps,has-lpm-erratum;
2170				snps,hird-threshold = /bits/ 8 <0x10>;
2171			};
2172		};
2173
2174		usb3phy: phy@c010000 {
2175			compatible = "qcom,msm8998-qmp-usb3-phy";
2176			reg = <0x0c010000 0x1000>;
2177
2178			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
2179				 <&gcc GCC_USB3_CLKREF_CLK>,
2180				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2181				 <&gcc GCC_USB3_PHY_PIPE_CLK>;
2182			clock-names = "aux",
2183				      "ref",
2184				      "cfg_ahb",
2185				      "pipe";
2186			clock-output-names = "usb3_phy_pipe_clk_src";
2187			#clock-cells = <0>;
2188			#phy-cells = <0>;
2189
2190			resets = <&gcc GCC_USB3_PHY_BCR>,
2191				 <&gcc GCC_USB3PHY_PHY_BCR>;
2192			reset-names = "phy",
2193				      "phy_phy";
2194
2195			qcom,tcsr-reg = <&tcsr_regs_2 0xb244>;
2196
2197			status = "disabled";
2198		};
2199
2200		qusb2phy: phy@c012000 {
2201			compatible = "qcom,msm8998-qusb2-phy";
2202			reg = <0x0c012000 0x2a8>;
2203			status = "disabled";
2204			#phy-cells = <0>;
2205
2206			clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2207				 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
2208			clock-names = "cfg_ahb", "ref";
2209
2210			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2211
2212			nvmem-cells = <&qusb2_hstx_trim>;
2213		};
2214
2215		sdhc2: mmc@c0a4900 {
2216			compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2217			reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
2218			reg-names = "hc", "core";
2219
2220			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2221				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
2222			interrupt-names = "hc_irq", "pwr_irq";
2223
2224			clock-names = "iface", "core", "xo";
2225			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2226				 <&gcc GCC_SDCC2_APPS_CLK>,
2227				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2228			bus-width = <4>;
2229			status = "disabled";
2230		};
2231
2232		blsp1_dma: dma-controller@c144000 {
2233			compatible = "qcom,bam-v1.7.0";
2234			reg = <0x0c144000 0x25000>;
2235			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
2236			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2237			clock-names = "bam_clk";
2238			#dma-cells = <1>;
2239			qcom,ee = <0>;
2240			qcom,controlled-remotely;
2241			num-channels = <18>;
2242			qcom,num-ees = <4>;
2243		};
2244
2245		blsp1_uart3: serial@c171000 {
2246			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2247			reg = <0x0c171000 0x1000>;
2248			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
2249			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
2250				 <&gcc GCC_BLSP1_AHB_CLK>;
2251			clock-names = "core", "iface";
2252			dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
2253			dma-names = "tx", "rx";
2254			pinctrl-names = "default";
2255			pinctrl-0 = <&blsp1_uart3_on>;
2256			status = "disabled";
2257		};
2258
2259		blsp1_i2c1: i2c@c175000 {
2260			compatible = "qcom,i2c-qup-v2.2.1";
2261			reg = <0x0c175000 0x600>;
2262			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2263
2264			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2265				 <&gcc GCC_BLSP1_AHB_CLK>;
2266			clock-names = "core", "iface";
2267			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2268			dma-names = "tx", "rx";
2269			pinctrl-names = "default", "sleep";
2270			pinctrl-0 = <&blsp1_i2c1_default>;
2271			pinctrl-1 = <&blsp1_i2c1_sleep>;
2272			clock-frequency = <400000>;
2273
2274			status = "disabled";
2275			#address-cells = <1>;
2276			#size-cells = <0>;
2277		};
2278
2279		blsp1_i2c2: i2c@c176000 {
2280			compatible = "qcom,i2c-qup-v2.2.1";
2281			reg = <0x0c176000 0x600>;
2282			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2283
2284			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2285				 <&gcc GCC_BLSP1_AHB_CLK>;
2286			clock-names = "core", "iface";
2287			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2288			dma-names = "tx", "rx";
2289			pinctrl-names = "default", "sleep";
2290			pinctrl-0 = <&blsp1_i2c2_default>;
2291			pinctrl-1 = <&blsp1_i2c2_sleep>;
2292			clock-frequency = <400000>;
2293
2294			status = "disabled";
2295			#address-cells = <1>;
2296			#size-cells = <0>;
2297		};
2298
2299		blsp1_i2c3: i2c@c177000 {
2300			compatible = "qcom,i2c-qup-v2.2.1";
2301			reg = <0x0c177000 0x600>;
2302			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2303
2304			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2305				 <&gcc GCC_BLSP1_AHB_CLK>;
2306			clock-names = "core", "iface";
2307			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2308			dma-names = "tx", "rx";
2309			pinctrl-names = "default", "sleep";
2310			pinctrl-0 = <&blsp1_i2c3_default>;
2311			pinctrl-1 = <&blsp1_i2c3_sleep>;
2312			clock-frequency = <400000>;
2313
2314			status = "disabled";
2315			#address-cells = <1>;
2316			#size-cells = <0>;
2317		};
2318
2319		blsp1_i2c4: i2c@c178000 {
2320			compatible = "qcom,i2c-qup-v2.2.1";
2321			reg = <0x0c178000 0x600>;
2322			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2323
2324			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2325				 <&gcc GCC_BLSP1_AHB_CLK>;
2326			clock-names = "core", "iface";
2327			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2328			dma-names = "tx", "rx";
2329			pinctrl-names = "default", "sleep";
2330			pinctrl-0 = <&blsp1_i2c4_default>;
2331			pinctrl-1 = <&blsp1_i2c4_sleep>;
2332			clock-frequency = <400000>;
2333
2334			status = "disabled";
2335			#address-cells = <1>;
2336			#size-cells = <0>;
2337		};
2338
2339		blsp1_i2c5: i2c@c179000 {
2340			compatible = "qcom,i2c-qup-v2.2.1";
2341			reg = <0x0c179000 0x600>;
2342			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2343
2344			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2345				 <&gcc GCC_BLSP1_AHB_CLK>;
2346			clock-names = "core", "iface";
2347			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2348			dma-names = "tx", "rx";
2349			pinctrl-names = "default", "sleep";
2350			pinctrl-0 = <&blsp1_i2c5_default>;
2351			pinctrl-1 = <&blsp1_i2c5_sleep>;
2352			clock-frequency = <400000>;
2353
2354			status = "disabled";
2355			#address-cells = <1>;
2356			#size-cells = <0>;
2357		};
2358
2359		blsp1_i2c6: i2c@c17a000 {
2360			compatible = "qcom,i2c-qup-v2.2.1";
2361			reg = <0x0c17a000 0x600>;
2362			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2363
2364			clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2365				 <&gcc GCC_BLSP1_AHB_CLK>;
2366			clock-names = "core", "iface";
2367			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2368			dma-names = "tx", "rx";
2369			pinctrl-names = "default", "sleep";
2370			pinctrl-0 = <&blsp1_i2c6_default>;
2371			pinctrl-1 = <&blsp1_i2c6_sleep>;
2372			clock-frequency = <400000>;
2373
2374			status = "disabled";
2375			#address-cells = <1>;
2376			#size-cells = <0>;
2377		};
2378
2379		blsp1_spi1: spi@c175000 {
2380			compatible = "qcom,spi-qup-v2.2.1";
2381			reg = <0x0c175000 0x600>;
2382			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
2383
2384			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2385				 <&gcc GCC_BLSP1_AHB_CLK>;
2386			clock-names = "core", "iface";
2387			dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
2388			dma-names = "tx", "rx";
2389			pinctrl-names = "default";
2390			pinctrl-0 = <&blsp1_spi1_default>;
2391
2392			status = "disabled";
2393			#address-cells = <1>;
2394			#size-cells = <0>;
2395		};
2396
2397		blsp1_spi2: spi@c176000 {
2398			compatible = "qcom,spi-qup-v2.2.1";
2399			reg = <0x0c176000 0x600>;
2400			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
2401
2402			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2403				 <&gcc GCC_BLSP1_AHB_CLK>;
2404			clock-names = "core", "iface";
2405			dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
2406			dma-names = "tx", "rx";
2407			pinctrl-names = "default";
2408			pinctrl-0 = <&blsp1_spi2_default>;
2409
2410			status = "disabled";
2411			#address-cells = <1>;
2412			#size-cells = <0>;
2413		};
2414
2415		blsp1_spi3: spi@c177000 {
2416			compatible = "qcom,spi-qup-v2.2.1";
2417			reg = <0x0c177000 0x600>;
2418			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
2419
2420			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2421				 <&gcc GCC_BLSP1_AHB_CLK>;
2422			clock-names = "core", "iface";
2423			dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
2424			dma-names = "tx", "rx";
2425			pinctrl-names = "default";
2426			pinctrl-0 = <&blsp1_spi3_default>;
2427
2428			status = "disabled";
2429			#address-cells = <1>;
2430			#size-cells = <0>;
2431		};
2432
2433		blsp1_spi4: spi@c178000 {
2434			compatible = "qcom,spi-qup-v2.2.1";
2435			reg = <0x0c178000 0x600>;
2436			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2437
2438			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2439				 <&gcc GCC_BLSP1_AHB_CLK>;
2440			clock-names = "core", "iface";
2441			dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
2442			dma-names = "tx", "rx";
2443			pinctrl-names = "default";
2444			pinctrl-0 = <&blsp1_spi4_default>;
2445
2446			status = "disabled";
2447			#address-cells = <1>;
2448			#size-cells = <0>;
2449		};
2450
2451		blsp1_spi5: spi@c179000 {
2452			compatible = "qcom,spi-qup-v2.2.1";
2453			reg = <0x0c179000 0x600>;
2454			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
2455
2456			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2457				 <&gcc GCC_BLSP1_AHB_CLK>;
2458			clock-names = "core", "iface";
2459			dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
2460			dma-names = "tx", "rx";
2461			pinctrl-names = "default";
2462			pinctrl-0 = <&blsp1_spi5_default>;
2463
2464			status = "disabled";
2465			#address-cells = <1>;
2466			#size-cells = <0>;
2467		};
2468
2469		blsp1_spi6: spi@c17a000 {
2470			compatible = "qcom,spi-qup-v2.2.1";
2471			reg = <0x0c17a000 0x600>;
2472			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
2473
2474			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2475				 <&gcc GCC_BLSP1_AHB_CLK>;
2476			clock-names = "core", "iface";
2477			dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
2478			dma-names = "tx", "rx";
2479			pinctrl-names = "default";
2480			pinctrl-0 = <&blsp1_spi6_default>;
2481
2482			status = "disabled";
2483			#address-cells = <1>;
2484			#size-cells = <0>;
2485		};
2486
2487		blsp2_dma: dma-controller@c184000 {
2488			compatible = "qcom,bam-v1.7.0";
2489			reg = <0x0c184000 0x25000>;
2490			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
2491			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
2492			clock-names = "bam_clk";
2493			#dma-cells = <1>;
2494			qcom,ee = <0>;
2495			qcom,controlled-remotely;
2496			num-channels = <18>;
2497			qcom,num-ees = <4>;
2498		};
2499
2500		blsp2_uart1: serial@c1b0000 {
2501			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2502			reg = <0x0c1b0000 0x1000>;
2503			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
2504			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
2505				 <&gcc GCC_BLSP2_AHB_CLK>;
2506			clock-names = "core", "iface";
2507			status = "disabled";
2508		};
2509
2510		blsp2_i2c1: i2c@c1b5000 {
2511			compatible = "qcom,i2c-qup-v2.2.1";
2512			reg = <0x0c1b5000 0x600>;
2513			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2514
2515			clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
2516				 <&gcc GCC_BLSP2_AHB_CLK>;
2517			clock-names = "core", "iface";
2518			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2519			dma-names = "tx", "rx";
2520			pinctrl-names = "default", "sleep";
2521			pinctrl-0 = <&blsp2_i2c1_default>;
2522			pinctrl-1 = <&blsp2_i2c1_sleep>;
2523			clock-frequency = <400000>;
2524
2525			status = "disabled";
2526			#address-cells = <1>;
2527			#size-cells = <0>;
2528		};
2529
2530		blsp2_i2c2: i2c@c1b6000 {
2531			compatible = "qcom,i2c-qup-v2.2.1";
2532			reg = <0x0c1b6000 0x600>;
2533			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2534
2535			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
2536				 <&gcc GCC_BLSP2_AHB_CLK>;
2537			clock-names = "core", "iface";
2538			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2539			dma-names = "tx", "rx";
2540			pinctrl-names = "default", "sleep";
2541			pinctrl-0 = <&blsp2_i2c2_default>;
2542			pinctrl-1 = <&blsp2_i2c2_sleep>;
2543			clock-frequency = <400000>;
2544
2545			status = "disabled";
2546			#address-cells = <1>;
2547			#size-cells = <0>;
2548		};
2549
2550		blsp2_i2c3: i2c@c1b7000 {
2551			compatible = "qcom,i2c-qup-v2.2.1";
2552			reg = <0x0c1b7000 0x600>;
2553			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2554
2555			clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
2556				 <&gcc GCC_BLSP2_AHB_CLK>;
2557			clock-names = "core", "iface";
2558			dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2559			dma-names = "tx", "rx";
2560			pinctrl-names = "default", "sleep";
2561			pinctrl-0 = <&blsp2_i2c3_default>;
2562			pinctrl-1 = <&blsp2_i2c3_sleep>;
2563			clock-frequency = <400000>;
2564
2565			status = "disabled";
2566			#address-cells = <1>;
2567			#size-cells = <0>;
2568		};
2569
2570		blsp2_i2c4: i2c@c1b8000 {
2571			compatible = "qcom,i2c-qup-v2.2.1";
2572			reg = <0x0c1b8000 0x600>;
2573			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2574
2575			clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
2576				 <&gcc GCC_BLSP2_AHB_CLK>;
2577			clock-names = "core", "iface";
2578			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2579			dma-names = "tx", "rx";
2580			pinctrl-names = "default", "sleep";
2581			pinctrl-0 = <&blsp2_i2c4_default>;
2582			pinctrl-1 = <&blsp2_i2c4_sleep>;
2583			clock-frequency = <400000>;
2584
2585			status = "disabled";
2586			#address-cells = <1>;
2587			#size-cells = <0>;
2588		};
2589
2590		blsp2_i2c5: i2c@c1b9000 {
2591			compatible = "qcom,i2c-qup-v2.2.1";
2592			reg = <0x0c1b9000 0x600>;
2593			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2594
2595			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
2596				 <&gcc GCC_BLSP2_AHB_CLK>;
2597			clock-names = "core", "iface";
2598			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2599			dma-names = "tx", "rx";
2600			pinctrl-names = "default", "sleep";
2601			pinctrl-0 = <&blsp2_i2c5_default>;
2602			pinctrl-1 = <&blsp2_i2c5_sleep>;
2603			clock-frequency = <400000>;
2604
2605			status = "disabled";
2606			#address-cells = <1>;
2607			#size-cells = <0>;
2608		};
2609
2610		blsp2_i2c6: i2c@c1ba000 {
2611			compatible = "qcom,i2c-qup-v2.2.1";
2612			reg = <0x0c1ba000 0x600>;
2613			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2614
2615			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
2616				 <&gcc GCC_BLSP2_AHB_CLK>;
2617			clock-names = "core", "iface";
2618			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2619			dma-names = "tx", "rx";
2620			pinctrl-names = "default", "sleep";
2621			pinctrl-0 = <&blsp2_i2c6_default>;
2622			pinctrl-1 = <&blsp2_i2c6_sleep>;
2623			clock-frequency = <400000>;
2624
2625			status = "disabled";
2626			#address-cells = <1>;
2627			#size-cells = <0>;
2628		};
2629
2630		blsp2_spi1: spi@c1b5000 {
2631			compatible = "qcom,spi-qup-v2.2.1";
2632			reg = <0x0c1b5000 0x600>;
2633			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
2634
2635			clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>,
2636				 <&gcc GCC_BLSP2_AHB_CLK>;
2637			clock-names = "core", "iface";
2638			dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
2639			dma-names = "tx", "rx";
2640			pinctrl-names = "default";
2641			pinctrl-0 = <&blsp2_spi1_default>;
2642
2643			status = "disabled";
2644			#address-cells = <1>;
2645			#size-cells = <0>;
2646		};
2647
2648		blsp2_spi2: spi@c1b6000 {
2649			compatible = "qcom,spi-qup-v2.2.1";
2650			reg = <0x0c1b6000 0x600>;
2651			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
2652
2653			clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>,
2654				 <&gcc GCC_BLSP2_AHB_CLK>;
2655			clock-names = "core", "iface";
2656			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
2657			dma-names = "tx", "rx";
2658			pinctrl-names = "default";
2659			pinctrl-0 = <&blsp2_spi2_default>;
2660
2661			status = "disabled";
2662			#address-cells = <1>;
2663			#size-cells = <0>;
2664		};
2665
2666		blsp2_spi3: spi@c1b7000 {
2667			compatible = "qcom,spi-qup-v2.2.1";
2668			reg = <0x0c1b7000 0x600>;
2669			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2670
2671			clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
2672				 <&gcc GCC_BLSP2_AHB_CLK>;
2673			clock-names = "core", "iface";
2674			dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
2675			dma-names = "tx", "rx";
2676			pinctrl-names = "default";
2677			pinctrl-0 = <&blsp2_spi3_default>;
2678
2679			status = "disabled";
2680			#address-cells = <1>;
2681			#size-cells = <0>;
2682		};
2683
2684		blsp2_spi4: spi@c1b8000 {
2685			compatible = "qcom,spi-qup-v2.2.1";
2686			reg = <0x0c1b8000 0x600>;
2687			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
2688
2689			clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
2690				 <&gcc GCC_BLSP2_AHB_CLK>;
2691			clock-names = "core", "iface";
2692			dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
2693			dma-names = "tx", "rx";
2694			pinctrl-names = "default";
2695			pinctrl-0 = <&blsp2_spi4_default>;
2696
2697			status = "disabled";
2698			#address-cells = <1>;
2699			#size-cells = <0>;
2700		};
2701
2702		blsp2_spi5: spi@c1b9000 {
2703			compatible = "qcom,spi-qup-v2.2.1";
2704			reg = <0x0c1b9000 0x600>;
2705			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
2706
2707			clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>,
2708				 <&gcc GCC_BLSP2_AHB_CLK>;
2709			clock-names = "core", "iface";
2710			dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
2711			dma-names = "tx", "rx";
2712			pinctrl-names = "default";
2713			pinctrl-0 = <&blsp2_spi5_default>;
2714
2715			status = "disabled";
2716			#address-cells = <1>;
2717			#size-cells = <0>;
2718		};
2719
2720		blsp2_spi6: spi@c1ba000 {
2721			compatible = "qcom,spi-qup-v2.2.1";
2722			reg = <0x0c1ba000 0x600>;
2723			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
2724
2725			clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
2726				 <&gcc GCC_BLSP2_AHB_CLK>;
2727			clock-names = "core", "iface";
2728			dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
2729			dma-names = "tx", "rx";
2730			pinctrl-names = "default";
2731			pinctrl-0 = <&blsp2_spi6_default>;
2732
2733			status = "disabled";
2734			#address-cells = <1>;
2735			#size-cells = <0>;
2736		};
2737
2738		mmcc: clock-controller@c8c0000 {
2739			compatible = "qcom,mmcc-msm8998";
2740			#clock-cells = <1>;
2741			#reset-cells = <1>;
2742			#power-domain-cells = <1>;
2743			reg = <0xc8c0000 0x40000>;
2744
2745			clock-names = "xo",
2746				      "gpll0",
2747				      "dsi0dsi",
2748				      "dsi0byte",
2749				      "dsi1dsi",
2750				      "dsi1byte",
2751				      "hdmipll",
2752				      "dplink",
2753				      "dpvco",
2754				      "gpll0_div";
2755			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2756				 <&gcc GCC_MMSS_GPLL0_CLK>,
2757				 <&mdss_dsi0_phy 1>,
2758				 <&mdss_dsi0_phy 0>,
2759				 <&mdss_dsi1_phy 1>,
2760				 <&mdss_dsi1_phy 0>,
2761				 <0>,
2762				 <0>,
2763				 <0>,
2764				 <&gcc GCC_MMSS_GPLL0_DIV_CLK>;
2765		};
2766
2767		mdss: display-subsystem@c900000 {
2768			compatible = "qcom,msm8998-mdss";
2769			reg = <0x0c900000 0x1000>;
2770			reg-names = "mdss";
2771
2772			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2773			interrupt-controller;
2774			#interrupt-cells = <1>;
2775
2776			clocks = <&mmcc MDSS_AHB_CLK>,
2777				 <&mmcc MDSS_AXI_CLK>,
2778				 <&mmcc MDSS_MDP_CLK>;
2779			clock-names = "iface",
2780				      "bus",
2781				      "core";
2782
2783			power-domains = <&mmcc MDSS_GDSC>;
2784			iommus = <&mmss_smmu 0>;
2785
2786			#address-cells = <1>;
2787			#size-cells = <1>;
2788			ranges;
2789
2790			status = "disabled";
2791
2792			mdss_mdp: display-controller@c901000 {
2793				compatible = "qcom,msm8998-dpu";
2794				reg = <0x0c901000 0x8f000>,
2795				      <0x0c9a8e00 0xf0>,
2796				      <0x0c9b0000 0x2008>,
2797				      <0x0c9b8000 0x1040>;
2798				reg-names = "mdp",
2799					    "regdma",
2800					    "vbif",
2801					    "vbif_nrt";
2802
2803				interrupt-parent = <&mdss>;
2804				interrupts = <0>;
2805
2806				clocks = <&mmcc MDSS_AHB_CLK>,
2807					 <&mmcc MDSS_AXI_CLK>,
2808					 <&mmcc MNOC_AHB_CLK>,
2809					 <&mmcc MDSS_MDP_CLK>,
2810					 <&mmcc MDSS_VSYNC_CLK>;
2811				clock-names = "iface",
2812					      "bus",
2813					      "mnoc",
2814					      "core",
2815					      "vsync";
2816
2817				assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2818				assigned-clock-rates = <19200000>;
2819
2820				operating-points-v2 = <&mdp_opp_table>;
2821				power-domains = <&rpmpd MSM8998_VDDMX>;
2822
2823				mdp_opp_table: opp-table {
2824					compatible = "operating-points-v2";
2825
2826					opp-171430000 {
2827						opp-hz = /bits/ 64 <171430000>;
2828						required-opps = <&rpmpd_opp_low_svs>;
2829					};
2830
2831					opp-275000000 {
2832						opp-hz = /bits/ 64 <275000000>;
2833						required-opps = <&rpmpd_opp_svs>;
2834					};
2835
2836					opp-330000000 {
2837						opp-hz = /bits/ 64 <330000000>;
2838						required-opps = <&rpmpd_opp_nom>;
2839					};
2840
2841					opp-412500000 {
2842						opp-hz = /bits/ 64 <412500000>;
2843						required-opps = <&rpmpd_opp_turbo>;
2844					};
2845				};
2846
2847				ports {
2848					#address-cells = <1>;
2849					#size-cells = <0>;
2850
2851					port@0 {
2852						reg = <0>;
2853
2854						dpu_intf1_out: endpoint {
2855							remote-endpoint = <&mdss_dsi0_in>;
2856						};
2857					};
2858
2859					port@1 {
2860						reg = <1>;
2861
2862						dpu_intf2_out: endpoint {
2863							remote-endpoint = <&mdss_dsi1_in>;
2864						};
2865					};
2866				};
2867			};
2868
2869			mdss_dsi0: dsi@c994000 {
2870				compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2871				reg = <0x0c994000 0x400>;
2872				reg-names = "dsi_ctrl";
2873
2874				interrupt-parent = <&mdss>;
2875				interrupts = <4>;
2876
2877				clocks = <&mmcc MDSS_BYTE0_CLK>,
2878					 <&mmcc MDSS_BYTE0_INTF_CLK>,
2879					 <&mmcc MDSS_PCLK0_CLK>,
2880					 <&mmcc MDSS_ESC0_CLK>,
2881					 <&mmcc MDSS_AHB_CLK>,
2882					 <&mmcc MDSS_AXI_CLK>;
2883				clock-names = "byte",
2884					      "byte_intf",
2885					      "pixel",
2886					      "core",
2887					      "iface",
2888					      "bus";
2889				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2890						  <&mmcc PCLK0_CLK_SRC>;
2891				assigned-clock-parents = <&mdss_dsi0_phy 0>,
2892							 <&mdss_dsi0_phy 1>;
2893
2894				operating-points-v2 = <&dsi_opp_table>;
2895				power-domains = <&rpmpd MSM8998_VDDCX>;
2896
2897				phys = <&mdss_dsi0_phy>;
2898				phy-names = "dsi";
2899
2900				#address-cells = <1>;
2901				#size-cells = <0>;
2902
2903				status = "disabled";
2904
2905				ports {
2906					#address-cells = <1>;
2907					#size-cells = <0>;
2908
2909					port@0 {
2910						reg = <0>;
2911
2912						mdss_dsi0_in: endpoint {
2913							remote-endpoint = <&dpu_intf1_out>;
2914						};
2915					};
2916
2917					port@1 {
2918						reg = <1>;
2919
2920						mdss_dsi0_out: endpoint {
2921						};
2922					};
2923				};
2924			};
2925
2926			mdss_dsi0_phy: phy@c994400 {
2927				compatible = "qcom,dsi-phy-10nm-8998";
2928				reg = <0x0c994400 0x200>,
2929				      <0x0c994600 0x280>,
2930				      <0x0c994a00 0x1e0>;
2931				reg-names = "dsi_phy",
2932					    "dsi_phy_lane",
2933					    "dsi_pll";
2934
2935				clocks = <&mmcc MDSS_AHB_CLK>,
2936					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2937				clock-names = "iface", "ref";
2938
2939				#clock-cells = <1>;
2940				#phy-cells = <0>;
2941
2942				status = "disabled";
2943			};
2944
2945			mdss_dsi1: dsi@c996000 {
2946				compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2947				reg = <0x0c996000 0x400>;
2948				reg-names = "dsi_ctrl";
2949
2950				interrupt-parent = <&mdss>;
2951				interrupts = <5>;
2952
2953				clocks = <&mmcc MDSS_BYTE1_CLK>,
2954					 <&mmcc MDSS_BYTE1_INTF_CLK>,
2955					 <&mmcc MDSS_PCLK1_CLK>,
2956					 <&mmcc MDSS_ESC1_CLK>,
2957					 <&mmcc MDSS_AHB_CLK>,
2958					 <&mmcc MDSS_AXI_CLK>;
2959				clock-names = "byte",
2960					      "byte_intf",
2961					      "pixel",
2962					      "core",
2963					      "iface",
2964					      "bus";
2965				assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2966						  <&mmcc PCLK1_CLK_SRC>;
2967				assigned-clock-parents = <&mdss_dsi1_phy 0>,
2968							 <&mdss_dsi1_phy 1>;
2969
2970				operating-points-v2 = <&dsi_opp_table>;
2971				power-domains = <&rpmpd MSM8998_VDDCX>;
2972
2973				phys = <&mdss_dsi1_phy>;
2974				phy-names = "dsi";
2975
2976				#address-cells = <1>;
2977				#size-cells = <0>;
2978
2979				status = "disabled";
2980
2981				ports {
2982					#address-cells = <1>;
2983					#size-cells = <0>;
2984
2985					port@0 {
2986						reg = <0>;
2987
2988						mdss_dsi1_in: endpoint {
2989							remote-endpoint = <&dpu_intf2_out>;
2990						};
2991					};
2992
2993					port@1 {
2994						reg = <1>;
2995
2996						mdss_dsi1_out: endpoint {
2997						};
2998					};
2999				};
3000			};
3001
3002			mdss_dsi1_phy: phy@c996400 {
3003				compatible = "qcom,dsi-phy-10nm-8998";
3004				reg = <0x0c996400 0x200>,
3005				      <0x0c996600 0x280>,
3006				      <0x0c996a00 0x10e>;
3007				reg-names = "dsi_phy",
3008					    "dsi_phy_lane",
3009					    "dsi_pll";
3010
3011				clocks = <&mmcc MDSS_AHB_CLK>,
3012					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
3013				clock-names = "iface",
3014					      "ref";
3015
3016				#clock-cells = <1>;
3017				#phy-cells = <0>;
3018
3019				status = "disabled";
3020			};
3021		};
3022
3023		mmss_smmu: iommu@cd00000 {
3024			compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3025			reg = <0x0cd00000 0x40000>;
3026			#iommu-cells = <1>;
3027
3028			clocks = <&mmcc MNOC_AHB_CLK>,
3029				 <&mmcc BIMC_SMMU_AHB_CLK>,
3030				 <&mmcc BIMC_SMMU_AXI_CLK>;
3031			clock-names = "iface-mm",
3032				      "iface-smmu",
3033				      "bus-smmu";
3034
3035			#global-interrupts = <0>;
3036			interrupts =
3037				<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3038				<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3039				<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3040				<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
3041				<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
3042				<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3043				<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3044				<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
3045				<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3046				<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3047				<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3048				<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
3049				<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3050				<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3051				<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3052				<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
3053				<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
3054				<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3055				<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3056				<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3057
3058			power-domains = <&mmcc BIMC_SMMU_GDSC>;
3059		};
3060
3061		remoteproc_adsp: remoteproc@17300000 {
3062			compatible = "qcom,msm8998-adsp-pas";
3063			reg = <0x17300000 0x4040>;
3064
3065			interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3066					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3067					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
3068					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
3069					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
3070			interrupt-names = "wdog", "fatal", "ready",
3071					  "handover", "stop-ack";
3072
3073			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
3074			clock-names = "xo";
3075
3076			memory-region = <&adsp_mem>;
3077
3078			qcom,smem-states = <&adsp_smp2p_out 0>;
3079			qcom,smem-state-names = "stop";
3080
3081			power-domains = <&rpmpd MSM8998_VDDCX>;
3082			power-domain-names = "cx";
3083
3084			status = "disabled";
3085
3086			glink-edge {
3087				interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
3088				label = "lpass";
3089				qcom,remote-pid = <2>;
3090				mboxes = <&apcs_glb 9>;
3091			};
3092		};
3093
3094		apcs_glb: mailbox@17911000 {
3095			compatible = "qcom,msm8998-apcs-hmss-global",
3096				     "qcom,msm8994-apcs-kpss-global";
3097			reg = <0x17911000 0x1000>;
3098
3099			#mbox-cells = <1>;
3100		};
3101
3102		timer@17920000 {
3103			#address-cells = <1>;
3104			#size-cells = <1>;
3105			ranges;
3106			compatible = "arm,armv7-timer-mem";
3107			reg = <0x17920000 0x1000>;
3108
3109			frame@17921000 {
3110				frame-number = <0>;
3111				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3112					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3113				reg = <0x17921000 0x1000>,
3114				      <0x17922000 0x1000>;
3115			};
3116
3117			frame@17923000 {
3118				frame-number = <1>;
3119				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3120				reg = <0x17923000 0x1000>;
3121				status = "disabled";
3122			};
3123
3124			frame@17924000 {
3125				frame-number = <2>;
3126				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3127				reg = <0x17924000 0x1000>;
3128				status = "disabled";
3129			};
3130
3131			frame@17925000 {
3132				frame-number = <3>;
3133				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3134				reg = <0x17925000 0x1000>;
3135				status = "disabled";
3136			};
3137
3138			frame@17926000 {
3139				frame-number = <4>;
3140				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3141				reg = <0x17926000 0x1000>;
3142				status = "disabled";
3143			};
3144
3145			frame@17927000 {
3146				frame-number = <5>;
3147				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3148				reg = <0x17927000 0x1000>;
3149				status = "disabled";
3150			};
3151
3152			frame@17928000 {
3153				frame-number = <6>;
3154				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3155				reg = <0x17928000 0x1000>;
3156				status = "disabled";
3157			};
3158		};
3159
3160		intc: interrupt-controller@17a00000 {
3161			compatible = "arm,gic-v3";
3162			reg = <0x17a00000 0x10000>,       /* GICD */
3163			      <0x17b00000 0x100000>;      /* GICR * 8 */
3164			#interrupt-cells = <3>;
3165			#address-cells = <1>;
3166			#size-cells = <1>;
3167			ranges;
3168			interrupt-controller;
3169			#redistributor-regions = <1>;
3170			redistributor-stride = <0x0 0x20000>;
3171			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3172		};
3173
3174		wifi: wifi@18800000 {
3175			compatible = "qcom,wcn3990-wifi";
3176			status = "disabled";
3177			reg = <0x18800000 0x800000>;
3178			reg-names = "membase";
3179			memory-region = <&wlan_msa_mem>;
3180			clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
3181			clock-names = "cxo_ref_clk_pin";
3182			interrupts =
3183				<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
3184				<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
3185				<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
3186				<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
3187				<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
3188				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
3189				<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
3190				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
3191				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
3192				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
3193				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
3194				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
3195			iommus = <&anoc2_smmu 0x1900>,
3196				 <&anoc2_smmu 0x1901>;
3197			qcom,snoc-host-cap-8bit-quirk;
3198		};
3199	};
3200};
3201