1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8998.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/firmware/qcom,scm.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 qcom,msm-id = <292 0x0>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 memory@80000000 { 24 device_type = "memory"; 25 /* We expect the bootloader to fill in the reg */ 26 reg = <0x0 0x80000000 0x0 0x0>; 27 }; 28 29 reserved-memory { 30 #address-cells = <2>; 31 #size-cells = <2>; 32 ranges; 33 34 hyp_mem: memory@85800000 { 35 reg = <0x0 0x85800000 0x0 0x600000>; 36 no-map; 37 }; 38 39 xbl_mem: memory@85e00000 { 40 reg = <0x0 0x85e00000 0x0 0x100000>; 41 no-map; 42 }; 43 44 smem_mem: smem-mem@86000000 { 45 reg = <0x0 0x86000000 0x0 0x200000>; 46 no-map; 47 }; 48 49 tz_mem: memory@86200000 { 50 reg = <0x0 0x86200000 0x0 0x2d00000>; 51 no-map; 52 }; 53 54 rmtfs_mem: memory@88f00000 { 55 compatible = "qcom,rmtfs-mem"; 56 reg = <0x0 0x88f00000 0x0 0x200000>; 57 no-map; 58 59 qcom,client-id = <1>; 60 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 61 }; 62 63 spss_mem: memory@8ab00000 { 64 reg = <0x0 0x8ab00000 0x0 0x700000>; 65 no-map; 66 }; 67 68 adsp_mem: memory@8b200000 { 69 reg = <0x0 0x8b200000 0x0 0x1a00000>; 70 no-map; 71 }; 72 73 mpss_mem: memory@8cc00000 { 74 reg = <0x0 0x8cc00000 0x0 0x7000000>; 75 no-map; 76 }; 77 78 venus_mem: memory@93c00000 { 79 reg = <0x0 0x93c00000 0x0 0x500000>; 80 no-map; 81 }; 82 83 mba_mem: memory@94100000 { 84 reg = <0x0 0x94100000 0x0 0x200000>; 85 no-map; 86 }; 87 88 slpi_mem: memory@94300000 { 89 reg = <0x0 0x94300000 0x0 0xf00000>; 90 no-map; 91 }; 92 93 ipa_fw_mem: memory@95200000 { 94 reg = <0x0 0x95200000 0x0 0x10000>; 95 no-map; 96 }; 97 98 ipa_gsi_mem: memory@95210000 { 99 reg = <0x0 0x95210000 0x0 0x5000>; 100 no-map; 101 }; 102 103 gpu_mem: memory@95600000 { 104 reg = <0x0 0x95600000 0x0 0x100000>; 105 no-map; 106 }; 107 108 wlan_msa_mem: memory@95700000 { 109 reg = <0x0 0x95700000 0x0 0x100000>; 110 no-map; 111 }; 112 113 mdata_mem: mpss-metadata { 114 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 115 size = <0x0 0x4000>; 116 no-map; 117 }; 118 }; 119 120 clocks { 121 xo: xo-board { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <19200000>; 125 clock-output-names = "xo_board"; 126 }; 127 128 sleep_clk: sleep-clk { 129 compatible = "fixed-clock"; 130 #clock-cells = <0>; 131 clock-frequency = <32764>; 132 }; 133 }; 134 135 cpus { 136 #address-cells = <2>; 137 #size-cells = <0>; 138 139 cpu0: cpu@0 { 140 device_type = "cpu"; 141 compatible = "qcom,kryo280"; 142 reg = <0x0 0x0>; 143 enable-method = "psci"; 144 capacity-dmips-mhz = <1024>; 145 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 146 next-level-cache = <&l2_0>; 147 l2_0: l2-cache { 148 compatible = "cache"; 149 cache-level = <2>; 150 cache-unified; 151 }; 152 }; 153 154 cpu1: cpu@1 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo280"; 157 reg = <0x0 0x1>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1024>; 160 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 161 next-level-cache = <&l2_0>; 162 }; 163 164 cpu2: cpu@2 { 165 device_type = "cpu"; 166 compatible = "qcom,kryo280"; 167 reg = <0x0 0x2>; 168 enable-method = "psci"; 169 capacity-dmips-mhz = <1024>; 170 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 171 next-level-cache = <&l2_0>; 172 }; 173 174 cpu3: cpu@3 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo280"; 177 reg = <0x0 0x3>; 178 enable-method = "psci"; 179 capacity-dmips-mhz = <1024>; 180 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 181 next-level-cache = <&l2_0>; 182 }; 183 184 cpu4: cpu@100 { 185 device_type = "cpu"; 186 compatible = "qcom,kryo280"; 187 reg = <0x0 0x100>; 188 enable-method = "psci"; 189 capacity-dmips-mhz = <1536>; 190 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 191 next-level-cache = <&l2_1>; 192 l2_1: l2-cache { 193 compatible = "cache"; 194 cache-level = <2>; 195 cache-unified; 196 }; 197 }; 198 199 cpu5: cpu@101 { 200 device_type = "cpu"; 201 compatible = "qcom,kryo280"; 202 reg = <0x0 0x101>; 203 enable-method = "psci"; 204 capacity-dmips-mhz = <1536>; 205 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 206 next-level-cache = <&l2_1>; 207 }; 208 209 cpu6: cpu@102 { 210 device_type = "cpu"; 211 compatible = "qcom,kryo280"; 212 reg = <0x0 0x102>; 213 enable-method = "psci"; 214 capacity-dmips-mhz = <1536>; 215 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 216 next-level-cache = <&l2_1>; 217 }; 218 219 cpu7: cpu@103 { 220 device_type = "cpu"; 221 compatible = "qcom,kryo280"; 222 reg = <0x0 0x103>; 223 enable-method = "psci"; 224 capacity-dmips-mhz = <1536>; 225 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 226 next-level-cache = <&l2_1>; 227 }; 228 229 cpu-map { 230 cluster0 { 231 core0 { 232 cpu = <&cpu0>; 233 }; 234 235 core1 { 236 cpu = <&cpu1>; 237 }; 238 239 core2 { 240 cpu = <&cpu2>; 241 }; 242 243 core3 { 244 cpu = <&cpu3>; 245 }; 246 }; 247 248 cluster1 { 249 core0 { 250 cpu = <&cpu4>; 251 }; 252 253 core1 { 254 cpu = <&cpu5>; 255 }; 256 257 core2 { 258 cpu = <&cpu6>; 259 }; 260 261 core3 { 262 cpu = <&cpu7>; 263 }; 264 }; 265 }; 266 267 idle-states { 268 entry-method = "psci"; 269 270 little_cpu_sleep_0: cpu-sleep-0-0 { 271 compatible = "arm,idle-state"; 272 idle-state-name = "little-retention"; 273 /* CPU Retention (C2D), L2 Active */ 274 arm,psci-suspend-param = <0x00000002>; 275 entry-latency-us = <81>; 276 exit-latency-us = <86>; 277 min-residency-us = <504>; 278 }; 279 280 little_cpu_sleep_1: cpu-sleep-0-1 { 281 compatible = "arm,idle-state"; 282 idle-state-name = "little-power-collapse"; 283 /* CPU + L2 Power Collapse (C3, D4) */ 284 arm,psci-suspend-param = <0x40000003>; 285 entry-latency-us = <814>; 286 exit-latency-us = <4562>; 287 min-residency-us = <9183>; 288 local-timer-stop; 289 }; 290 291 big_cpu_sleep_0: cpu-sleep-1-0 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "big-retention"; 294 /* CPU Retention (C2D), L2 Active */ 295 arm,psci-suspend-param = <0x00000002>; 296 entry-latency-us = <79>; 297 exit-latency-us = <82>; 298 min-residency-us = <1302>; 299 }; 300 301 big_cpu_sleep_1: cpu-sleep-1-1 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "big-power-collapse"; 304 /* CPU + L2 Power Collapse (C3, D4) */ 305 arm,psci-suspend-param = <0x40000003>; 306 entry-latency-us = <724>; 307 exit-latency-us = <2027>; 308 min-residency-us = <9419>; 309 local-timer-stop; 310 }; 311 }; 312 }; 313 314 firmware { 315 scm { 316 compatible = "qcom,scm-msm8998", "qcom,scm"; 317 }; 318 }; 319 320 dsi_opp_table: opp-table-dsi { 321 compatible = "operating-points-v2"; 322 323 opp-131250000 { 324 opp-hz = /bits/ 64 <131250000>; 325 required-opps = <&rpmpd_opp_low_svs>; 326 }; 327 328 opp-210000000 { 329 opp-hz = /bits/ 64 <210000000>; 330 required-opps = <&rpmpd_opp_svs>; 331 }; 332 333 opp-312500000 { 334 opp-hz = /bits/ 64 <312500000>; 335 required-opps = <&rpmpd_opp_nom>; 336 }; 337 }; 338 339 psci { 340 compatible = "arm,psci-1.0"; 341 method = "smc"; 342 }; 343 344 rpm: remoteproc { 345 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; 346 347 glink-edge { 348 compatible = "qcom,glink-rpm"; 349 350 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 351 qcom,rpm-msg-ram = <&rpm_msg_ram>; 352 mboxes = <&apcs_glb 0>; 353 354 rpm_requests: rpm-requests { 355 compatible = "qcom,rpm-msm8998", "qcom,glink-smd-rpm"; 356 qcom,glink-channels = "rpm_requests"; 357 358 rpmcc: clock-controller { 359 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 360 clocks = <&xo>; 361 clock-names = "xo"; 362 #clock-cells = <1>; 363 }; 364 365 rpmpd: power-controller { 366 compatible = "qcom,msm8998-rpmpd"; 367 #power-domain-cells = <1>; 368 operating-points-v2 = <&rpmpd_opp_table>; 369 370 rpmpd_opp_table: opp-table { 371 compatible = "operating-points-v2"; 372 373 rpmpd_opp_ret: opp1 { 374 opp-level = <RPM_SMD_LEVEL_RETENTION>; 375 }; 376 377 rpmpd_opp_ret_plus: opp2 { 378 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 379 }; 380 381 rpmpd_opp_min_svs: opp3 { 382 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 383 }; 384 385 rpmpd_opp_low_svs: opp4 { 386 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 387 }; 388 389 rpmpd_opp_svs: opp5 { 390 opp-level = <RPM_SMD_LEVEL_SVS>; 391 }; 392 393 rpmpd_opp_svs_plus: opp6 { 394 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 395 }; 396 397 rpmpd_opp_nom: opp7 { 398 opp-level = <RPM_SMD_LEVEL_NOM>; 399 }; 400 401 rpmpd_opp_nom_plus: opp8 { 402 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 403 }; 404 405 rpmpd_opp_turbo: opp9 { 406 opp-level = <RPM_SMD_LEVEL_TURBO>; 407 }; 408 409 rpmpd_opp_turbo_plus: opp10 { 410 opp-level = <RPM_SMD_LEVEL_BINNING>; 411 }; 412 }; 413 }; 414 }; 415 }; 416 }; 417 418 smem { 419 compatible = "qcom,smem"; 420 memory-region = <&smem_mem>; 421 hwlocks = <&tcsr_mutex 3>; 422 }; 423 424 smp2p-lpass { 425 compatible = "qcom,smp2p"; 426 qcom,smem = <443>, <429>; 427 428 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 429 430 mboxes = <&apcs_glb 10>; 431 432 qcom,local-pid = <0>; 433 qcom,remote-pid = <2>; 434 435 adsp_smp2p_out: master-kernel { 436 qcom,entry-name = "master-kernel"; 437 #qcom,smem-state-cells = <1>; 438 }; 439 440 adsp_smp2p_in: slave-kernel { 441 qcom,entry-name = "slave-kernel"; 442 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 }; 446 }; 447 448 smp2p-mpss { 449 compatible = "qcom,smp2p"; 450 qcom,smem = <435>, <428>; 451 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 452 mboxes = <&apcs_glb 14>; 453 qcom,local-pid = <0>; 454 qcom,remote-pid = <1>; 455 456 modem_smp2p_out: master-kernel { 457 qcom,entry-name = "master-kernel"; 458 #qcom,smem-state-cells = <1>; 459 }; 460 461 modem_smp2p_in: slave-kernel { 462 qcom,entry-name = "slave-kernel"; 463 interrupt-controller; 464 #interrupt-cells = <2>; 465 }; 466 }; 467 468 smp2p-slpi { 469 compatible = "qcom,smp2p"; 470 qcom,smem = <481>, <430>; 471 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 472 mboxes = <&apcs_glb 26>; 473 qcom,local-pid = <0>; 474 qcom,remote-pid = <3>; 475 476 slpi_smp2p_out: master-kernel { 477 qcom,entry-name = "master-kernel"; 478 #qcom,smem-state-cells = <1>; 479 }; 480 481 slpi_smp2p_in: slave-kernel { 482 qcom,entry-name = "slave-kernel"; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 }; 486 }; 487 488 thermal-zones { 489 cpu0-thermal { 490 polling-delay-passive = <250>; 491 492 thermal-sensors = <&tsens0 1>; 493 494 trips { 495 cpu0_alert0: trip-point0 { 496 temperature = <75000>; 497 hysteresis = <2000>; 498 type = "passive"; 499 }; 500 501 cpu0_crit: cpu-crit { 502 temperature = <110000>; 503 hysteresis = <2000>; 504 type = "critical"; 505 }; 506 }; 507 }; 508 509 cpu1-thermal { 510 polling-delay-passive = <250>; 511 512 thermal-sensors = <&tsens0 2>; 513 514 trips { 515 cpu1_alert0: trip-point0 { 516 temperature = <75000>; 517 hysteresis = <2000>; 518 type = "passive"; 519 }; 520 521 cpu1_crit: cpu-crit { 522 temperature = <110000>; 523 hysteresis = <2000>; 524 type = "critical"; 525 }; 526 }; 527 }; 528 529 cpu2-thermal { 530 polling-delay-passive = <250>; 531 532 thermal-sensors = <&tsens0 3>; 533 534 trips { 535 cpu2_alert0: trip-point0 { 536 temperature = <75000>; 537 hysteresis = <2000>; 538 type = "passive"; 539 }; 540 541 cpu2_crit: cpu-crit { 542 temperature = <110000>; 543 hysteresis = <2000>; 544 type = "critical"; 545 }; 546 }; 547 }; 548 549 cpu3-thermal { 550 polling-delay-passive = <250>; 551 552 thermal-sensors = <&tsens0 4>; 553 554 trips { 555 cpu3_alert0: trip-point0 { 556 temperature = <75000>; 557 hysteresis = <2000>; 558 type = "passive"; 559 }; 560 561 cpu3_crit: cpu-crit { 562 temperature = <110000>; 563 hysteresis = <2000>; 564 type = "critical"; 565 }; 566 }; 567 }; 568 569 cpu4-thermal { 570 polling-delay-passive = <250>; 571 572 thermal-sensors = <&tsens0 7>; 573 574 trips { 575 cpu4_alert0: trip-point0 { 576 temperature = <75000>; 577 hysteresis = <2000>; 578 type = "passive"; 579 }; 580 581 cpu4_crit: cpu-crit { 582 temperature = <110000>; 583 hysteresis = <2000>; 584 type = "critical"; 585 }; 586 }; 587 }; 588 589 cpu5-thermal { 590 polling-delay-passive = <250>; 591 592 thermal-sensors = <&tsens0 8>; 593 594 trips { 595 cpu5_alert0: trip-point0 { 596 temperature = <75000>; 597 hysteresis = <2000>; 598 type = "passive"; 599 }; 600 601 cpu5_crit: cpu-crit { 602 temperature = <110000>; 603 hysteresis = <2000>; 604 type = "critical"; 605 }; 606 }; 607 }; 608 609 cpu6-thermal { 610 polling-delay-passive = <250>; 611 612 thermal-sensors = <&tsens0 9>; 613 614 trips { 615 cpu6_alert0: trip-point0 { 616 temperature = <75000>; 617 hysteresis = <2000>; 618 type = "passive"; 619 }; 620 621 cpu6_crit: cpu-crit { 622 temperature = <110000>; 623 hysteresis = <2000>; 624 type = "critical"; 625 }; 626 }; 627 }; 628 629 cpu7-thermal { 630 polling-delay-passive = <250>; 631 632 thermal-sensors = <&tsens0 10>; 633 634 trips { 635 cpu7_alert0: trip-point0 { 636 temperature = <75000>; 637 hysteresis = <2000>; 638 type = "passive"; 639 }; 640 641 cpu7_crit: cpu-crit { 642 temperature = <110000>; 643 hysteresis = <2000>; 644 type = "critical"; 645 }; 646 }; 647 }; 648 649 gpu-bottom-thermal { 650 polling-delay-passive = <250>; 651 652 thermal-sensors = <&tsens0 12>; 653 654 trips { 655 gpu1_alert0: trip-point0 { 656 temperature = <90000>; 657 hysteresis = <2000>; 658 type = "hot"; 659 }; 660 }; 661 }; 662 663 gpu-top-thermal { 664 polling-delay-passive = <250>; 665 666 thermal-sensors = <&tsens0 13>; 667 668 trips { 669 gpu2_alert0: trip-point0 { 670 temperature = <90000>; 671 hysteresis = <2000>; 672 type = "hot"; 673 }; 674 }; 675 }; 676 677 clust0-mhm-thermal { 678 polling-delay-passive = <250>; 679 680 thermal-sensors = <&tsens0 5>; 681 682 trips { 683 cluster0_mhm_alert0: trip-point0 { 684 temperature = <90000>; 685 hysteresis = <2000>; 686 type = "hot"; 687 }; 688 }; 689 }; 690 691 clust1-mhm-thermal { 692 polling-delay-passive = <250>; 693 694 thermal-sensors = <&tsens0 6>; 695 696 trips { 697 cluster1_mhm_alert0: trip-point0 { 698 temperature = <90000>; 699 hysteresis = <2000>; 700 type = "hot"; 701 }; 702 }; 703 }; 704 705 cluster1-l2-thermal { 706 polling-delay-passive = <250>; 707 708 thermal-sensors = <&tsens0 11>; 709 710 trips { 711 cluster1_l2_alert0: trip-point0 { 712 temperature = <90000>; 713 hysteresis = <2000>; 714 type = "hot"; 715 }; 716 }; 717 }; 718 719 modem-thermal { 720 polling-delay-passive = <250>; 721 722 thermal-sensors = <&tsens1 1>; 723 724 trips { 725 modem_alert0: trip-point0 { 726 temperature = <90000>; 727 hysteresis = <2000>; 728 type = "hot"; 729 }; 730 }; 731 }; 732 733 mem-thermal { 734 polling-delay-passive = <250>; 735 736 thermal-sensors = <&tsens1 2>; 737 738 trips { 739 mem_alert0: trip-point0 { 740 temperature = <90000>; 741 hysteresis = <2000>; 742 type = "hot"; 743 }; 744 }; 745 }; 746 747 wlan-thermal { 748 polling-delay-passive = <250>; 749 750 thermal-sensors = <&tsens1 3>; 751 752 trips { 753 wlan_alert0: trip-point0 { 754 temperature = <90000>; 755 hysteresis = <2000>; 756 type = "hot"; 757 }; 758 }; 759 }; 760 761 q6-dsp-thermal { 762 polling-delay-passive = <250>; 763 764 thermal-sensors = <&tsens1 4>; 765 766 trips { 767 q6_dsp_alert0: trip-point0 { 768 temperature = <90000>; 769 hysteresis = <2000>; 770 type = "hot"; 771 }; 772 }; 773 }; 774 775 camera-thermal { 776 polling-delay-passive = <250>; 777 778 thermal-sensors = <&tsens1 5>; 779 780 trips { 781 camera_alert0: trip-point0 { 782 temperature = <90000>; 783 hysteresis = <2000>; 784 type = "hot"; 785 }; 786 }; 787 }; 788 789 multimedia-thermal { 790 polling-delay-passive = <250>; 791 792 thermal-sensors = <&tsens1 6>; 793 794 trips { 795 multimedia_alert0: trip-point0 { 796 temperature = <90000>; 797 hysteresis = <2000>; 798 type = "hot"; 799 }; 800 }; 801 }; 802 }; 803 804 timer { 805 compatible = "arm,armv8-timer"; 806 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 807 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 808 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 809 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 810 }; 811 812 soc: soc@0 { 813 #address-cells = <1>; 814 #size-cells = <1>; 815 ranges = <0 0 0 0xffffffff>; 816 compatible = "simple-bus"; 817 818 gcc: clock-controller@100000 { 819 compatible = "qcom,gcc-msm8998"; 820 #clock-cells = <1>; 821 #reset-cells = <1>; 822 #power-domain-cells = <1>; 823 reg = <0x00100000 0xb0000>; 824 825 clock-names = "xo", "sleep_clk"; 826 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 827 828 /* 829 * The hypervisor typically configures the memory region where these clocks 830 * reside as read-only for the HLOS. If the HLOS tried to enable or disable 831 * these clocks on a device with such configuration (e.g. because they are 832 * enabled but unused during boot-up), the device will most likely decide 833 * to reboot. 834 * In light of that, we are conservative here and we list all such clocks 835 * as protected. The board dts (or a user-supplied dts) can override the 836 * list of protected clocks if it differs from the norm, and it is in fact 837 * desired for the HLOS to manage these clocks 838 */ 839 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>, 840 <SSC_XO>, 841 <SSC_CNOC_AHBS_CLK>; 842 }; 843 844 rpm_msg_ram: sram@778000 { 845 compatible = "qcom,rpm-msg-ram"; 846 reg = <0x00778000 0x7000>; 847 }; 848 849 qfprom: qfprom@784000 { 850 compatible = "qcom,msm8998-qfprom", "qcom,qfprom"; 851 reg = <0x00784000 0x621c>; 852 #address-cells = <1>; 853 #size-cells = <1>; 854 855 qusb2_hstx_trim: hstx-trim@23a { 856 reg = <0x23a 0x1>; 857 bits = <0 4>; 858 }; 859 }; 860 861 tsens0: thermal@10ab000 { 862 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 863 reg = <0x010ab000 0x1000>, /* TM */ 864 <0x010aa000 0x1000>; /* SROT */ 865 #qcom,sensors = <14>; 866 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 868 interrupt-names = "uplow", "critical"; 869 #thermal-sensor-cells = <1>; 870 }; 871 872 tsens1: thermal@10ae000 { 873 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 874 reg = <0x010ae000 0x1000>, /* TM */ 875 <0x010ad000 0x1000>; /* SROT */ 876 #qcom,sensors = <8>; 877 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 879 interrupt-names = "uplow", "critical"; 880 #thermal-sensor-cells = <1>; 881 }; 882 883 anoc1_smmu: iommu@1680000 { 884 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 885 reg = <0x01680000 0x10000>; 886 #iommu-cells = <1>; 887 888 #global-interrupts = <0>; 889 interrupts = 890 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 891 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 892 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 893 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 894 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 895 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 896 }; 897 898 anoc2_smmu: iommu@16c0000 { 899 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 900 reg = <0x016c0000 0x40000>; 901 #iommu-cells = <1>; 902 903 #global-interrupts = <0>; 904 interrupts = 905 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 906 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 907 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 908 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 909 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 910 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 911 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 912 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 913 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 914 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 915 }; 916 917 pcie0: pcie@1c00000 { 918 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; 919 reg = <0x01c00000 0x2000>, 920 <0x1b000000 0xf1d>, 921 <0x1b000f20 0xa8>, 922 <0x1b100000 0x100000>; 923 reg-names = "parf", "dbi", "elbi", "config"; 924 device_type = "pci"; 925 linux,pci-domain = <0>; 926 bus-range = <0x00 0xff>; 927 #address-cells = <3>; 928 #size-cells = <2>; 929 num-lanes = <1>; 930 phys = <&pcie_phy>; 931 phy-names = "pciephy"; 932 status = "disabled"; 933 934 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, 935 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 936 937 #interrupt-cells = <1>; 938 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 939 interrupt-names = "msi"; 940 interrupt-map-mask = <0 0 0 0x7>; 941 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, 942 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, 943 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, 944 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; 945 946 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 947 <&gcc GCC_PCIE_0_AUX_CLK>, 948 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 949 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 950 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 951 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave"; 952 953 power-domains = <&gcc PCIE_0_GDSC>; 954 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 955 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 956 957 pcie@0 { 958 device_type = "pci"; 959 reg = <0x0 0x0 0x0 0x0 0x0>; 960 bus-range = <0x01 0xff>; 961 962 #address-cells = <3>; 963 #size-cells = <2>; 964 ranges; 965 }; 966 }; 967 968 pcie_phy: phy@1c06000 { 969 compatible = "qcom,msm8998-qmp-pcie-phy"; 970 reg = <0x01c06000 0x1000>; 971 status = "disabled"; 972 973 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 974 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 975 <&gcc GCC_PCIE_CLKREF_CLK>, 976 <&gcc GCC_PCIE_0_PIPE_CLK>; 977 clock-names = "aux", 978 "cfg_ahb", 979 "ref", 980 "pipe"; 981 982 clock-output-names = "pcie_0_pipe_clk_src"; 983 #clock-cells = <0>; 984 985 #phy-cells = <0>; 986 987 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 988 reset-names = "phy", "common"; 989 990 vdda-phy-supply = <&vreg_l1a_0p875>; 991 vdda-pll-supply = <&vreg_l2a_1p2>; 992 }; 993 994 ufshc: ufshc@1da4000 { 995 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 996 reg = <0x01da4000 0x2500>; 997 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 998 phys = <&ufsphy>; 999 phy-names = "ufsphy"; 1000 lanes-per-direction = <2>; 1001 power-domains = <&gcc UFS_GDSC>; 1002 status = "disabled"; 1003 #reset-cells = <1>; 1004 1005 clock-names = 1006 "core_clk", 1007 "bus_aggr_clk", 1008 "iface_clk", 1009 "core_clk_unipro", 1010 "ref_clk", 1011 "tx_lane0_sync_clk", 1012 "rx_lane0_sync_clk", 1013 "rx_lane1_sync_clk"; 1014 clocks = 1015 <&gcc GCC_UFS_AXI_CLK>, 1016 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1017 <&gcc GCC_UFS_AHB_CLK>, 1018 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1019 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1020 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1021 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1022 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1023 freq-table-hz = 1024 <50000000 200000000>, 1025 <0 0>, 1026 <0 0>, 1027 <37500000 150000000>, 1028 <0 0>, 1029 <0 0>, 1030 <0 0>, 1031 <0 0>; 1032 1033 resets = <&gcc GCC_UFS_BCR>; 1034 reset-names = "rst"; 1035 }; 1036 1037 ufsphy: phy@1da7000 { 1038 compatible = "qcom,msm8998-qmp-ufs-phy"; 1039 reg = <0x01da7000 0x1000>; 1040 1041 clocks = <&rpmcc RPM_SMD_LN_BB_CLK1>, 1042 <&gcc GCC_UFS_PHY_AUX_CLK>, 1043 <&gcc GCC_UFS_CLKREF_CLK>; 1044 clock-names = "ref", 1045 "ref_aux", 1046 "qref"; 1047 1048 reset-names = "ufsphy"; 1049 resets = <&ufshc 0>; 1050 1051 #phy-cells = <0>; 1052 status = "disabled"; 1053 }; 1054 1055 tcsr_mutex: hwlock@1f40000 { 1056 compatible = "qcom,tcsr-mutex"; 1057 reg = <0x01f40000 0x20000>; 1058 #hwlock-cells = <1>; 1059 }; 1060 1061 tcsr_regs_1: syscon@1f60000 { 1062 compatible = "qcom,msm8998-tcsr", "syscon"; 1063 reg = <0x01f60000 0x20000>; 1064 }; 1065 1066 tcsr_regs_2: syscon@1fc0000 { 1067 compatible = "qcom,msm8998-tcsr", "syscon"; 1068 reg = <0x01fc0000 0x26000>; 1069 }; 1070 1071 tlmm: pinctrl@3400000 { 1072 compatible = "qcom,msm8998-pinctrl"; 1073 reg = <0x03400000 0xc00000>; 1074 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1075 gpio-ranges = <&tlmm 0 0 150>; 1076 gpio-controller; 1077 #gpio-cells = <2>; 1078 interrupt-controller; 1079 #interrupt-cells = <2>; 1080 1081 sdc2_on: sdc2-on-state { 1082 clk-pins { 1083 pins = "sdc2_clk"; 1084 drive-strength = <16>; 1085 bias-disable; 1086 }; 1087 1088 cmd-pins { 1089 pins = "sdc2_cmd"; 1090 drive-strength = <10>; 1091 bias-pull-up; 1092 }; 1093 1094 data-pins { 1095 pins = "sdc2_data"; 1096 drive-strength = <10>; 1097 bias-pull-up; 1098 }; 1099 }; 1100 1101 sdc2_off: sdc2-off-state { 1102 clk-pins { 1103 pins = "sdc2_clk"; 1104 drive-strength = <2>; 1105 bias-disable; 1106 }; 1107 1108 cmd-pins { 1109 pins = "sdc2_cmd"; 1110 drive-strength = <2>; 1111 bias-pull-up; 1112 }; 1113 1114 data-pins { 1115 pins = "sdc2_data"; 1116 drive-strength = <2>; 1117 bias-pull-up; 1118 }; 1119 }; 1120 1121 sdc2_cd: sdc2-cd-state { 1122 pins = "gpio95"; 1123 function = "gpio"; 1124 bias-pull-up; 1125 drive-strength = <2>; 1126 }; 1127 1128 blsp1_uart3_on: blsp1-uart3-on-state { 1129 tx-pins { 1130 pins = "gpio45"; 1131 function = "blsp_uart3_a"; 1132 drive-strength = <2>; 1133 bias-disable; 1134 }; 1135 1136 rx-pins { 1137 pins = "gpio46"; 1138 function = "blsp_uart3_a"; 1139 drive-strength = <2>; 1140 bias-disable; 1141 }; 1142 1143 cts-pins { 1144 pins = "gpio47"; 1145 function = "blsp_uart3_a"; 1146 drive-strength = <2>; 1147 bias-disable; 1148 }; 1149 1150 rfr-pins { 1151 pins = "gpio48"; 1152 function = "blsp_uart3_a"; 1153 drive-strength = <2>; 1154 bias-disable; 1155 }; 1156 }; 1157 1158 blsp1_i2c1_default: blsp1-i2c1-default-state { 1159 pins = "gpio2", "gpio3"; 1160 function = "blsp_i2c1"; 1161 drive-strength = <2>; 1162 bias-disable; 1163 }; 1164 1165 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state { 1166 pins = "gpio2", "gpio3"; 1167 function = "blsp_i2c1"; 1168 drive-strength = <2>; 1169 bias-pull-up; 1170 }; 1171 1172 blsp1_i2c2_default: blsp1-i2c2-default-state { 1173 pins = "gpio32", "gpio33"; 1174 function = "blsp_i2c2"; 1175 drive-strength = <2>; 1176 bias-disable; 1177 }; 1178 1179 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state { 1180 pins = "gpio32", "gpio33"; 1181 function = "blsp_i2c2"; 1182 drive-strength = <2>; 1183 bias-pull-up; 1184 }; 1185 1186 blsp1_i2c3_default: blsp1-i2c3-default-state { 1187 pins = "gpio47", "gpio48"; 1188 function = "blsp_i2c3"; 1189 drive-strength = <2>; 1190 bias-disable; 1191 }; 1192 1193 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1194 pins = "gpio47", "gpio48"; 1195 function = "blsp_i2c3"; 1196 drive-strength = <2>; 1197 bias-pull-up; 1198 }; 1199 1200 blsp1_i2c4_default: blsp1-i2c4-default-state { 1201 pins = "gpio10", "gpio11"; 1202 function = "blsp_i2c4"; 1203 drive-strength = <2>; 1204 bias-disable; 1205 }; 1206 1207 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 1208 pins = "gpio10", "gpio11"; 1209 function = "blsp_i2c4"; 1210 drive-strength = <2>; 1211 bias-pull-up; 1212 }; 1213 1214 blsp1_i2c5_default: blsp1-i2c5-default-state { 1215 pins = "gpio87", "gpio88"; 1216 function = "blsp_i2c5"; 1217 drive-strength = <2>; 1218 bias-disable; 1219 }; 1220 1221 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state { 1222 pins = "gpio87", "gpio88"; 1223 function = "blsp_i2c5"; 1224 drive-strength = <2>; 1225 bias-pull-up; 1226 }; 1227 1228 blsp1_i2c6_default: blsp1-i2c6-default-state { 1229 pins = "gpio43", "gpio44"; 1230 function = "blsp_i2c6"; 1231 drive-strength = <2>; 1232 bias-disable; 1233 }; 1234 1235 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1236 pins = "gpio43", "gpio44"; 1237 function = "blsp_i2c6"; 1238 drive-strength = <2>; 1239 bias-pull-up; 1240 }; 1241 1242 blsp1_spi_b_default: blsp1-spi-b-default-state { 1243 pins = "gpio23", "gpio28"; 1244 function = "blsp1_spi_b"; 1245 drive-strength = <6>; 1246 bias-disable; 1247 }; 1248 1249 blsp1_spi1_default: blsp1-spi1-default-state { 1250 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1251 function = "blsp_spi1"; 1252 drive-strength = <6>; 1253 bias-disable; 1254 }; 1255 1256 blsp1_spi2_default: blsp1-spi2-default-state { 1257 pins = "gpio31", "gpio34", "gpio32", "gpio33"; 1258 function = "blsp_spi2"; 1259 drive-strength = <6>; 1260 bias-disable; 1261 }; 1262 1263 blsp1_spi3_default: blsp1-spi3-default-state { 1264 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 1265 function = "blsp_spi2"; 1266 drive-strength = <6>; 1267 bias-disable; 1268 }; 1269 1270 blsp1_spi4_default: blsp1-spi4-default-state { 1271 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 1272 function = "blsp_spi4"; 1273 drive-strength = <6>; 1274 bias-disable; 1275 }; 1276 1277 blsp1_spi5_default: blsp1-spi5-default-state { 1278 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1279 function = "blsp_spi5"; 1280 drive-strength = <6>; 1281 bias-disable; 1282 }; 1283 1284 blsp1_spi6_default: blsp1-spi6-default-state { 1285 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1286 function = "blsp_spi6"; 1287 drive-strength = <6>; 1288 bias-disable; 1289 }; 1290 1291 1292 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1293 blsp2_i2c1_default: blsp2-i2c1-default-state { 1294 pins = "gpio55", "gpio56"; 1295 function = "blsp_i2c7"; 1296 drive-strength = <2>; 1297 bias-disable; 1298 }; 1299 1300 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1301 pins = "gpio55", "gpio56"; 1302 function = "blsp_i2c7"; 1303 drive-strength = <2>; 1304 bias-pull-up; 1305 }; 1306 1307 blsp2_i2c2_default: blsp2-i2c2-default-state { 1308 pins = "gpio6", "gpio7"; 1309 function = "blsp_i2c8"; 1310 drive-strength = <2>; 1311 bias-disable; 1312 }; 1313 1314 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1315 pins = "gpio6", "gpio7"; 1316 function = "blsp_i2c8"; 1317 drive-strength = <2>; 1318 bias-pull-up; 1319 }; 1320 1321 blsp2_i2c3_default: blsp2-i2c3-default-state { 1322 pins = "gpio51", "gpio52"; 1323 function = "blsp_i2c9"; 1324 drive-strength = <2>; 1325 bias-disable; 1326 }; 1327 1328 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1329 pins = "gpio51", "gpio52"; 1330 function = "blsp_i2c9"; 1331 drive-strength = <2>; 1332 bias-pull-up; 1333 }; 1334 1335 blsp2_i2c4_default: blsp2-i2c4-default-state { 1336 pins = "gpio67", "gpio68"; 1337 function = "blsp_i2c10"; 1338 drive-strength = <2>; 1339 bias-disable; 1340 }; 1341 1342 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 1343 pins = "gpio67", "gpio68"; 1344 function = "blsp_i2c10"; 1345 drive-strength = <2>; 1346 bias-pull-up; 1347 }; 1348 1349 blsp2_i2c5_default: blsp2-i2c5-default-state { 1350 pins = "gpio60", "gpio61"; 1351 function = "blsp_i2c11"; 1352 drive-strength = <2>; 1353 bias-disable; 1354 }; 1355 1356 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1357 pins = "gpio60", "gpio61"; 1358 function = "blsp_i2c11"; 1359 drive-strength = <2>; 1360 bias-pull-up; 1361 }; 1362 1363 blsp2_i2c6_default: blsp2-i2c6-default-state { 1364 pins = "gpio83", "gpio84"; 1365 function = "blsp_i2c12"; 1366 drive-strength = <2>; 1367 bias-disable; 1368 }; 1369 1370 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1371 pins = "gpio83", "gpio84"; 1372 function = "blsp_i2c12"; 1373 drive-strength = <2>; 1374 bias-pull-up; 1375 }; 1376 1377 blsp2_spi1_default: blsp2-spi1-default-state { 1378 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1379 function = "blsp_spi7"; 1380 drive-strength = <6>; 1381 bias-disable; 1382 }; 1383 1384 blsp2_spi2_default: blsp2-spi2-default-state { 1385 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 1386 function = "blsp_spi8"; 1387 drive-strength = <6>; 1388 bias-disable; 1389 }; 1390 1391 blsp2_spi3_default: blsp2-spi3-default-state { 1392 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1393 function = "blsp_spi9"; 1394 drive-strength = <6>; 1395 bias-disable; 1396 }; 1397 1398 blsp2_spi4_default: blsp2-spi4-default-state { 1399 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 1400 function = "blsp_spi10"; 1401 drive-strength = <6>; 1402 bias-disable; 1403 }; 1404 1405 blsp2_spi5_default: blsp2-spi5-default-state { 1406 pins = "gpio58", "gpio59", "gpio60", "gpio61"; 1407 function = "blsp_spi11"; 1408 drive-strength = <6>; 1409 bias-disable; 1410 }; 1411 1412 blsp2_spi6_default: blsp2-spi6-default-state { 1413 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 1414 function = "blsp_spi12"; 1415 drive-strength = <6>; 1416 bias-disable; 1417 }; 1418 1419 hdmi_cec_default: hdmi-cec-default-state { 1420 pins = "gpio31"; 1421 function = "hdmi_cec"; 1422 drive-strength = <2>; 1423 bias-pull-up; 1424 }; 1425 1426 hdmi_ddc_default: hdmi-ddc-default-state { 1427 pins = "gpio32", "gpio33"; 1428 function = "hdmi_ddc"; 1429 drive-strength = <2>; 1430 bias-pull-up; 1431 }; 1432 1433 hdmi_hpd_default: hdmi-hpd-default-state { 1434 pins = "gpio34"; 1435 function = "hdmi_hot"; 1436 drive-strength = <16>; 1437 bias-pull-down; 1438 }; 1439 1440 hdmi_hpd_sleep: hdmi-hpd-sleep-state { 1441 pins = "gpio34"; 1442 function = "hdmi_hot"; 1443 drive-strength = <2>; 1444 bias-pull-down; 1445 }; 1446 }; 1447 1448 remoteproc_mss: remoteproc@4080000 { 1449 compatible = "qcom,msm8998-mss-pil"; 1450 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1451 reg-names = "qdsp6", "rmb"; 1452 1453 interrupts-extended = 1454 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1455 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1456 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1457 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1458 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1459 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1460 interrupt-names = "wdog", "fatal", "ready", 1461 "handover", "stop-ack", 1462 "shutdown-ack"; 1463 1464 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1465 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1466 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1467 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1468 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1469 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1470 <&rpmcc RPM_SMD_QDSS_CLK>, 1471 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1472 clock-names = "iface", "bus", "mem", "gpll0_mss", 1473 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1474 1475 qcom,smem-states = <&modem_smp2p_out 0>; 1476 qcom,smem-state-names = "stop"; 1477 1478 resets = <&gcc GCC_MSS_RESTART>; 1479 reset-names = "mss_restart"; 1480 1481 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1482 1483 power-domains = <&rpmpd MSM8998_VDDCX>, 1484 <&rpmpd MSM8998_VDDMX>; 1485 power-domain-names = "cx", "mx"; 1486 1487 status = "disabled"; 1488 1489 mba { 1490 memory-region = <&mba_mem>; 1491 }; 1492 1493 mpss { 1494 memory-region = <&mpss_mem>; 1495 }; 1496 1497 metadata { 1498 memory-region = <&mdata_mem>; 1499 }; 1500 1501 glink-edge { 1502 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1503 label = "modem"; 1504 qcom,remote-pid = <1>; 1505 mboxes = <&apcs_glb 15>; 1506 }; 1507 }; 1508 1509 adreno_gpu: gpu@5000000 { 1510 compatible = "qcom,adreno-540.1", "qcom,adreno"; 1511 reg = <0x05000000 0x40000>; 1512 reg-names = "kgsl_3d0_reg_memory"; 1513 1514 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1515 <&gpucc RBBMTIMER_CLK>, 1516 <&gcc GCC_BIMC_GFX_CLK>, 1517 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1518 <&gpucc RBCPR_CLK>, 1519 <&gpucc GFX3D_CLK>; 1520 clock-names = "iface", 1521 "rbbmtimer", 1522 "mem", 1523 "mem_iface", 1524 "rbcpr", 1525 "core"; 1526 1527 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1528 iommus = <&adreno_smmu 0>; 1529 operating-points-v2 = <&gpu_opp_table>; 1530 power-domains = <&rpmpd MSM8998_VDDMX>; 1531 status = "disabled"; 1532 1533 gpu_opp_table: opp-table { 1534 compatible = "operating-points-v2"; 1535 opp-710000097 { 1536 opp-hz = /bits/ 64 <710000097>; 1537 opp-level = <RPM_SMD_LEVEL_TURBO>; 1538 opp-supported-hw = <0xff>; 1539 }; 1540 1541 opp-670000048 { 1542 opp-hz = /bits/ 64 <670000048>; 1543 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1544 opp-supported-hw = <0xff>; 1545 }; 1546 1547 opp-596000097 { 1548 opp-hz = /bits/ 64 <596000097>; 1549 opp-level = <RPM_SMD_LEVEL_NOM>; 1550 opp-supported-hw = <0xff>; 1551 }; 1552 1553 opp-515000097 { 1554 opp-hz = /bits/ 64 <515000097>; 1555 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1556 opp-supported-hw = <0xff>; 1557 }; 1558 1559 opp-414000000 { 1560 opp-hz = /bits/ 64 <414000000>; 1561 opp-level = <RPM_SMD_LEVEL_SVS>; 1562 opp-supported-hw = <0xff>; 1563 }; 1564 1565 opp-342000000 { 1566 opp-hz = /bits/ 64 <342000000>; 1567 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1568 opp-supported-hw = <0xff>; 1569 }; 1570 1571 opp-257000000 { 1572 opp-hz = /bits/ 64 <257000000>; 1573 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1574 opp-supported-hw = <0xff>; 1575 }; 1576 }; 1577 }; 1578 1579 adreno_smmu: iommu@5040000 { 1580 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1581 reg = <0x05040000 0x10000>; 1582 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1583 <&gcc GCC_BIMC_GFX_CLK>, 1584 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1585 clock-names = "iface", "mem", "mem_iface"; 1586 1587 #global-interrupts = <0>; 1588 #iommu-cells = <1>; 1589 interrupts = 1590 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1593 /* 1594 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the 1595 * GPU-CX for SMMU but we need both of them up for Adreno. 1596 * Contemporarily, we also need to manage the VDDMX rpmpd 1597 * domain in the Adreno driver. 1598 * Enable GPU CX/GX GDSCs here so that we can manage the 1599 * SoC VDDMX RPM Power Domain in the Adreno driver. 1600 */ 1601 power-domains = <&gpucc GPU_GX_GDSC>; 1602 }; 1603 1604 gpucc: clock-controller@5065000 { 1605 compatible = "qcom,msm8998-gpucc"; 1606 #clock-cells = <1>; 1607 #reset-cells = <1>; 1608 #power-domain-cells = <1>; 1609 reg = <0x05065000 0x9000>; 1610 1611 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1612 <&gcc GCC_GPU_GPLL0_CLK>; 1613 clock-names = "xo", 1614 "gpll0"; 1615 }; 1616 1617 lpass_q6_smmu: iommu@5100000 { 1618 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1619 reg = <0x05100000 0x40000>; 1620 clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 1621 clock-names = "bus"; 1622 1623 #global-interrupts = <0>; 1624 #iommu-cells = <1>; 1625 interrupts = 1626 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1639 1640 power-domains = <&gcc LPASS_ADSP_GDSC>; 1641 status = "disabled"; 1642 }; 1643 1644 remoteproc_slpi: remoteproc@5800000 { 1645 compatible = "qcom,msm8998-slpi-pas"; 1646 reg = <0x05800000 0x4040>; 1647 1648 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1649 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1650 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1651 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1652 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1653 interrupt-names = "wdog", "fatal", "ready", 1654 "handover", "stop-ack"; 1655 1656 px-supply = <&vreg_lvs2a_1p8>; 1657 1658 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1659 clock-names = "xo"; 1660 1661 memory-region = <&slpi_mem>; 1662 1663 qcom,smem-states = <&slpi_smp2p_out 0>; 1664 qcom,smem-state-names = "stop"; 1665 1666 power-domains = <&rpmpd MSM8998_SSCCX>; 1667 power-domain-names = "ssc_cx"; 1668 1669 status = "disabled"; 1670 1671 glink-edge { 1672 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1673 label = "dsps"; 1674 qcom,remote-pid = <3>; 1675 mboxes = <&apcs_glb 27>; 1676 }; 1677 }; 1678 1679 stm: stm@6002000 { 1680 compatible = "arm,coresight-stm", "arm,primecell"; 1681 reg = <0x06002000 0x1000>, 1682 <0x16280000 0x180000>; 1683 reg-names = "stm-base", "stm-stimulus-base"; 1684 status = "disabled"; 1685 1686 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1687 clock-names = "apb_pclk", "atclk"; 1688 1689 out-ports { 1690 port { 1691 stm_out: endpoint { 1692 remote-endpoint = <&funnel0_in7>; 1693 }; 1694 }; 1695 }; 1696 }; 1697 1698 funnel1: funnel@6041000 { 1699 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1700 reg = <0x06041000 0x1000>; 1701 status = "disabled"; 1702 1703 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1704 clock-names = "apb_pclk", "atclk"; 1705 1706 out-ports { 1707 port { 1708 funnel0_out: endpoint { 1709 remote-endpoint = 1710 <&merge_funnel_in0>; 1711 }; 1712 }; 1713 }; 1714 1715 in-ports { 1716 #address-cells = <1>; 1717 #size-cells = <0>; 1718 1719 port@7 { 1720 reg = <7>; 1721 funnel0_in7: endpoint { 1722 remote-endpoint = <&stm_out>; 1723 }; 1724 }; 1725 }; 1726 }; 1727 1728 funnel2: funnel@6042000 { 1729 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1730 reg = <0x06042000 0x1000>; 1731 status = "disabled"; 1732 1733 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1734 clock-names = "apb_pclk", "atclk"; 1735 1736 out-ports { 1737 port { 1738 funnel1_out: endpoint { 1739 remote-endpoint = 1740 <&merge_funnel_in1>; 1741 }; 1742 }; 1743 }; 1744 1745 in-ports { 1746 #address-cells = <1>; 1747 #size-cells = <0>; 1748 1749 port@6 { 1750 reg = <6>; 1751 funnel1_in6: endpoint { 1752 remote-endpoint = 1753 <&apss_merge_funnel_out>; 1754 }; 1755 }; 1756 }; 1757 }; 1758 1759 funnel3: funnel@6045000 { 1760 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1761 reg = <0x06045000 0x1000>; 1762 status = "disabled"; 1763 1764 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1765 clock-names = "apb_pclk", "atclk"; 1766 1767 out-ports { 1768 port { 1769 merge_funnel_out: endpoint { 1770 remote-endpoint = 1771 <&etf_in>; 1772 }; 1773 }; 1774 }; 1775 1776 in-ports { 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 1780 port@0 { 1781 reg = <0>; 1782 merge_funnel_in0: endpoint { 1783 remote-endpoint = 1784 <&funnel0_out>; 1785 }; 1786 }; 1787 1788 port@1 { 1789 reg = <1>; 1790 merge_funnel_in1: endpoint { 1791 remote-endpoint = 1792 <&funnel1_out>; 1793 }; 1794 }; 1795 }; 1796 }; 1797 1798 replicator1: replicator@6046000 { 1799 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1800 reg = <0x06046000 0x1000>; 1801 status = "disabled"; 1802 1803 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1804 clock-names = "apb_pclk", "atclk"; 1805 1806 out-ports { 1807 port { 1808 replicator_out: endpoint { 1809 remote-endpoint = <&etr_in>; 1810 }; 1811 }; 1812 }; 1813 1814 in-ports { 1815 port { 1816 replicator_in: endpoint { 1817 remote-endpoint = <&etf_out>; 1818 }; 1819 }; 1820 }; 1821 }; 1822 1823 etf: etf@6047000 { 1824 compatible = "arm,coresight-tmc", "arm,primecell"; 1825 reg = <0x06047000 0x1000>; 1826 status = "disabled"; 1827 1828 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1829 clock-names = "apb_pclk", "atclk"; 1830 1831 out-ports { 1832 port { 1833 etf_out: endpoint { 1834 remote-endpoint = 1835 <&replicator_in>; 1836 }; 1837 }; 1838 }; 1839 1840 in-ports { 1841 port { 1842 etf_in: endpoint { 1843 remote-endpoint = 1844 <&merge_funnel_out>; 1845 }; 1846 }; 1847 }; 1848 }; 1849 1850 etr: etr@6048000 { 1851 compatible = "arm,coresight-tmc", "arm,primecell"; 1852 reg = <0x06048000 0x1000>; 1853 status = "disabled"; 1854 1855 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1856 clock-names = "apb_pclk", "atclk"; 1857 arm,scatter-gather; 1858 1859 in-ports { 1860 port { 1861 etr_in: endpoint { 1862 remote-endpoint = 1863 <&replicator_out>; 1864 }; 1865 }; 1866 }; 1867 }; 1868 1869 etm1: etm@7840000 { 1870 compatible = "arm,coresight-etm4x", "arm,primecell"; 1871 reg = <0x07840000 0x1000>; 1872 status = "disabled"; 1873 1874 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1875 clock-names = "apb_pclk", "atclk"; 1876 1877 cpu = <&cpu0>; 1878 1879 out-ports { 1880 port { 1881 etm0_out: endpoint { 1882 remote-endpoint = 1883 <&apss_funnel_in0>; 1884 }; 1885 }; 1886 }; 1887 }; 1888 1889 etm2: etm@7940000 { 1890 compatible = "arm,coresight-etm4x", "arm,primecell"; 1891 reg = <0x07940000 0x1000>; 1892 status = "disabled"; 1893 1894 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1895 clock-names = "apb_pclk", "atclk"; 1896 1897 cpu = <&cpu1>; 1898 1899 out-ports { 1900 port { 1901 etm1_out: endpoint { 1902 remote-endpoint = 1903 <&apss_funnel_in1>; 1904 }; 1905 }; 1906 }; 1907 }; 1908 1909 etm3: etm@7a40000 { 1910 compatible = "arm,coresight-etm4x", "arm,primecell"; 1911 reg = <0x07a40000 0x1000>; 1912 status = "disabled"; 1913 1914 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1915 clock-names = "apb_pclk", "atclk"; 1916 1917 cpu = <&cpu2>; 1918 1919 out-ports { 1920 port { 1921 etm2_out: endpoint { 1922 remote-endpoint = 1923 <&apss_funnel_in2>; 1924 }; 1925 }; 1926 }; 1927 }; 1928 1929 etm4: etm@7b40000 { 1930 compatible = "arm,coresight-etm4x", "arm,primecell"; 1931 reg = <0x07b40000 0x1000>; 1932 status = "disabled"; 1933 1934 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1935 clock-names = "apb_pclk", "atclk"; 1936 1937 cpu = <&cpu3>; 1938 1939 out-ports { 1940 port { 1941 etm3_out: endpoint { 1942 remote-endpoint = 1943 <&apss_funnel_in3>; 1944 }; 1945 }; 1946 }; 1947 }; 1948 1949 funnel4: funnel@7b60000 { /* APSS Funnel */ 1950 compatible = "arm,coresight-etm4x", "arm,primecell"; 1951 reg = <0x07b60000 0x1000>; 1952 status = "disabled"; 1953 1954 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1955 clock-names = "apb_pclk", "atclk"; 1956 1957 out-ports { 1958 port { 1959 apss_funnel_out: endpoint { 1960 remote-endpoint = 1961 <&apss_merge_funnel_in>; 1962 }; 1963 }; 1964 }; 1965 1966 in-ports { 1967 #address-cells = <1>; 1968 #size-cells = <0>; 1969 1970 port@0 { 1971 reg = <0>; 1972 apss_funnel_in0: endpoint { 1973 remote-endpoint = 1974 <&etm0_out>; 1975 }; 1976 }; 1977 1978 port@1 { 1979 reg = <1>; 1980 apss_funnel_in1: endpoint { 1981 remote-endpoint = 1982 <&etm1_out>; 1983 }; 1984 }; 1985 1986 port@2 { 1987 reg = <2>; 1988 apss_funnel_in2: endpoint { 1989 remote-endpoint = 1990 <&etm2_out>; 1991 }; 1992 }; 1993 1994 port@3 { 1995 reg = <3>; 1996 apss_funnel_in3: endpoint { 1997 remote-endpoint = 1998 <&etm3_out>; 1999 }; 2000 }; 2001 2002 port@4 { 2003 reg = <4>; 2004 apss_funnel_in4: endpoint { 2005 remote-endpoint = 2006 <&etm4_out>; 2007 }; 2008 }; 2009 2010 port@5 { 2011 reg = <5>; 2012 apss_funnel_in5: endpoint { 2013 remote-endpoint = 2014 <&etm5_out>; 2015 }; 2016 }; 2017 2018 port@6 { 2019 reg = <6>; 2020 apss_funnel_in6: endpoint { 2021 remote-endpoint = 2022 <&etm6_out>; 2023 }; 2024 }; 2025 2026 port@7 { 2027 reg = <7>; 2028 apss_funnel_in7: endpoint { 2029 remote-endpoint = 2030 <&etm7_out>; 2031 }; 2032 }; 2033 }; 2034 }; 2035 2036 funnel5: funnel@7b70000 { 2037 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2038 reg = <0x07b70000 0x1000>; 2039 status = "disabled"; 2040 2041 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2042 clock-names = "apb_pclk", "atclk"; 2043 2044 out-ports { 2045 port { 2046 apss_merge_funnel_out: endpoint { 2047 remote-endpoint = 2048 <&funnel1_in6>; 2049 }; 2050 }; 2051 }; 2052 2053 in-ports { 2054 port { 2055 apss_merge_funnel_in: endpoint { 2056 remote-endpoint = 2057 <&apss_funnel_out>; 2058 }; 2059 }; 2060 }; 2061 }; 2062 2063 etm5: etm@7c40000 { 2064 compatible = "arm,coresight-etm4x", "arm,primecell"; 2065 reg = <0x07c40000 0x1000>; 2066 status = "disabled"; 2067 2068 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2069 clock-names = "apb_pclk", "atclk"; 2070 2071 cpu = <&cpu4>; 2072 2073 out-ports { 2074 port { 2075 etm4_out: endpoint { 2076 remote-endpoint = <&apss_funnel_in4>; 2077 }; 2078 }; 2079 }; 2080 }; 2081 2082 etm6: etm@7d40000 { 2083 compatible = "arm,coresight-etm4x", "arm,primecell"; 2084 reg = <0x07d40000 0x1000>; 2085 status = "disabled"; 2086 2087 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2088 clock-names = "apb_pclk", "atclk"; 2089 2090 cpu = <&cpu5>; 2091 2092 out-ports { 2093 port { 2094 etm5_out: endpoint { 2095 remote-endpoint = <&apss_funnel_in5>; 2096 }; 2097 }; 2098 }; 2099 }; 2100 2101 etm7: etm@7e40000 { 2102 compatible = "arm,coresight-etm4x", "arm,primecell"; 2103 reg = <0x07e40000 0x1000>; 2104 status = "disabled"; 2105 2106 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2107 clock-names = "apb_pclk", "atclk"; 2108 2109 cpu = <&cpu6>; 2110 2111 out-ports { 2112 port { 2113 etm6_out: endpoint { 2114 remote-endpoint = <&apss_funnel_in6>; 2115 }; 2116 }; 2117 }; 2118 }; 2119 2120 etm8: etm@7f40000 { 2121 compatible = "arm,coresight-etm4x", "arm,primecell"; 2122 reg = <0x07f40000 0x1000>; 2123 status = "disabled"; 2124 2125 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2126 clock-names = "apb_pclk", "atclk"; 2127 2128 cpu = <&cpu7>; 2129 2130 out-ports { 2131 port { 2132 etm7_out: endpoint { 2133 remote-endpoint = <&apss_funnel_in7>; 2134 }; 2135 }; 2136 }; 2137 }; 2138 2139 sram@290000 { 2140 compatible = "qcom,rpm-stats"; 2141 reg = <0x00290000 0x10000>; 2142 }; 2143 2144 spmi_bus: spmi@800f000 { 2145 compatible = "qcom,spmi-pmic-arb"; 2146 reg = <0x0800f000 0x1000>, 2147 <0x08400000 0x1000000>, 2148 <0x09400000 0x1000000>, 2149 <0x0a400000 0x220000>, 2150 <0x0800a000 0x3000>; 2151 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2152 interrupt-names = "periph_irq"; 2153 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 2154 qcom,ee = <0>; 2155 qcom,channel = <0>; 2156 #address-cells = <2>; 2157 #size-cells = <0>; 2158 interrupt-controller; 2159 #interrupt-cells = <4>; 2160 }; 2161 2162 usb3: usb@a8f8800 { 2163 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 2164 reg = <0x0a8f8800 0x400>; 2165 status = "disabled"; 2166 #address-cells = <1>; 2167 #size-cells = <1>; 2168 ranges; 2169 2170 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 2171 <&gcc GCC_USB30_MASTER_CLK>, 2172 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 2173 <&gcc GCC_USB30_SLEEP_CLK>, 2174 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2175 clock-names = "cfg_noc", 2176 "core", 2177 "iface", 2178 "sleep", 2179 "mock_utmi"; 2180 2181 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2182 <&gcc GCC_USB30_MASTER_CLK>; 2183 assigned-clock-rates = <19200000>, <120000000>; 2184 2185 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2188 interrupt-names = "pwr_event", 2189 "qusb2_phy", 2190 "ss_phy_irq"; 2191 2192 power-domains = <&gcc USB_30_GDSC>; 2193 2194 resets = <&gcc GCC_USB_30_BCR>; 2195 2196 usb3_dwc3: usb@a800000 { 2197 compatible = "snps,dwc3"; 2198 reg = <0x0a800000 0xcd00>; 2199 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2200 snps,dis_u2_susphy_quirk; 2201 snps,dis_enblslpm_quirk; 2202 snps,parkmode-disable-ss-quirk; 2203 phys = <&qusb2phy>, <&usb3phy>; 2204 phy-names = "usb2-phy", "usb3-phy"; 2205 snps,has-lpm-erratum; 2206 snps,hird-threshold = /bits/ 8 <0x10>; 2207 }; 2208 }; 2209 2210 usb3phy: phy@c010000 { 2211 compatible = "qcom,msm8998-qmp-usb3-phy"; 2212 reg = <0x0c010000 0x1000>; 2213 2214 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2215 <&gcc GCC_USB3_CLKREF_CLK>, 2216 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2217 <&gcc GCC_USB3_PHY_PIPE_CLK>; 2218 clock-names = "aux", 2219 "ref", 2220 "cfg_ahb", 2221 "pipe"; 2222 clock-output-names = "usb3_phy_pipe_clk_src"; 2223 #clock-cells = <0>; 2224 #phy-cells = <0>; 2225 2226 resets = <&gcc GCC_USB3_PHY_BCR>, 2227 <&gcc GCC_USB3PHY_PHY_BCR>; 2228 reset-names = "phy", 2229 "phy_phy"; 2230 2231 qcom,tcsr-reg = <&tcsr_regs_2 0xb244>; 2232 2233 status = "disabled"; 2234 }; 2235 2236 qusb2phy: phy@c012000 { 2237 compatible = "qcom,msm8998-qusb2-phy"; 2238 reg = <0x0c012000 0x2a8>; 2239 status = "disabled"; 2240 #phy-cells = <0>; 2241 2242 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2243 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2244 clock-names = "cfg_ahb", "ref"; 2245 2246 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2247 2248 nvmem-cells = <&qusb2_hstx_trim>; 2249 }; 2250 2251 sdhc2: mmc@c0a4900 { 2252 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; 2253 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 2254 reg-names = "hc", "core"; 2255 2256 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2257 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2258 interrupt-names = "hc_irq", "pwr_irq"; 2259 2260 clock-names = "iface", "core", "xo"; 2261 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2262 <&gcc GCC_SDCC2_APPS_CLK>, 2263 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2264 bus-width = <4>; 2265 status = "disabled"; 2266 }; 2267 2268 blsp1_dma: dma-controller@c144000 { 2269 compatible = "qcom,bam-v1.7.0"; 2270 reg = <0x0c144000 0x25000>; 2271 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2272 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2273 clock-names = "bam_clk"; 2274 #dma-cells = <1>; 2275 qcom,ee = <0>; 2276 qcom,controlled-remotely; 2277 num-channels = <18>; 2278 qcom,num-ees = <4>; 2279 }; 2280 2281 blsp1_uart3: serial@c171000 { 2282 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2283 reg = <0x0c171000 0x1000>; 2284 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 2285 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 2286 <&gcc GCC_BLSP1_AHB_CLK>; 2287 clock-names = "core", "iface"; 2288 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 2289 dma-names = "tx", "rx"; 2290 pinctrl-names = "default"; 2291 pinctrl-0 = <&blsp1_uart3_on>; 2292 status = "disabled"; 2293 }; 2294 2295 blsp1_i2c1: i2c@c175000 { 2296 compatible = "qcom,i2c-qup-v2.2.1"; 2297 reg = <0x0c175000 0x600>; 2298 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2299 2300 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2301 <&gcc GCC_BLSP1_AHB_CLK>; 2302 clock-names = "core", "iface"; 2303 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2304 dma-names = "tx", "rx"; 2305 pinctrl-names = "default", "sleep"; 2306 pinctrl-0 = <&blsp1_i2c1_default>; 2307 pinctrl-1 = <&blsp1_i2c1_sleep>; 2308 clock-frequency = <400000>; 2309 2310 status = "disabled"; 2311 #address-cells = <1>; 2312 #size-cells = <0>; 2313 }; 2314 2315 blsp1_i2c2: i2c@c176000 { 2316 compatible = "qcom,i2c-qup-v2.2.1"; 2317 reg = <0x0c176000 0x600>; 2318 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2319 2320 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2321 <&gcc GCC_BLSP1_AHB_CLK>; 2322 clock-names = "core", "iface"; 2323 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2324 dma-names = "tx", "rx"; 2325 pinctrl-names = "default", "sleep"; 2326 pinctrl-0 = <&blsp1_i2c2_default>; 2327 pinctrl-1 = <&blsp1_i2c2_sleep>; 2328 clock-frequency = <400000>; 2329 2330 status = "disabled"; 2331 #address-cells = <1>; 2332 #size-cells = <0>; 2333 }; 2334 2335 blsp1_i2c3: i2c@c177000 { 2336 compatible = "qcom,i2c-qup-v2.2.1"; 2337 reg = <0x0c177000 0x600>; 2338 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2339 2340 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2341 <&gcc GCC_BLSP1_AHB_CLK>; 2342 clock-names = "core", "iface"; 2343 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2344 dma-names = "tx", "rx"; 2345 pinctrl-names = "default", "sleep"; 2346 pinctrl-0 = <&blsp1_i2c3_default>; 2347 pinctrl-1 = <&blsp1_i2c3_sleep>; 2348 clock-frequency = <400000>; 2349 2350 status = "disabled"; 2351 #address-cells = <1>; 2352 #size-cells = <0>; 2353 }; 2354 2355 blsp1_i2c4: i2c@c178000 { 2356 compatible = "qcom,i2c-qup-v2.2.1"; 2357 reg = <0x0c178000 0x600>; 2358 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2359 2360 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2361 <&gcc GCC_BLSP1_AHB_CLK>; 2362 clock-names = "core", "iface"; 2363 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2364 dma-names = "tx", "rx"; 2365 pinctrl-names = "default", "sleep"; 2366 pinctrl-0 = <&blsp1_i2c4_default>; 2367 pinctrl-1 = <&blsp1_i2c4_sleep>; 2368 clock-frequency = <400000>; 2369 2370 status = "disabled"; 2371 #address-cells = <1>; 2372 #size-cells = <0>; 2373 }; 2374 2375 blsp1_i2c5: i2c@c179000 { 2376 compatible = "qcom,i2c-qup-v2.2.1"; 2377 reg = <0x0c179000 0x600>; 2378 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2379 2380 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2381 <&gcc GCC_BLSP1_AHB_CLK>; 2382 clock-names = "core", "iface"; 2383 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2384 dma-names = "tx", "rx"; 2385 pinctrl-names = "default", "sleep"; 2386 pinctrl-0 = <&blsp1_i2c5_default>; 2387 pinctrl-1 = <&blsp1_i2c5_sleep>; 2388 clock-frequency = <400000>; 2389 2390 status = "disabled"; 2391 #address-cells = <1>; 2392 #size-cells = <0>; 2393 }; 2394 2395 blsp1_i2c6: i2c@c17a000 { 2396 compatible = "qcom,i2c-qup-v2.2.1"; 2397 reg = <0x0c17a000 0x600>; 2398 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2399 2400 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2401 <&gcc GCC_BLSP1_AHB_CLK>; 2402 clock-names = "core", "iface"; 2403 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2404 dma-names = "tx", "rx"; 2405 pinctrl-names = "default", "sleep"; 2406 pinctrl-0 = <&blsp1_i2c6_default>; 2407 pinctrl-1 = <&blsp1_i2c6_sleep>; 2408 clock-frequency = <400000>; 2409 2410 status = "disabled"; 2411 #address-cells = <1>; 2412 #size-cells = <0>; 2413 }; 2414 2415 blsp1_spi1: spi@c175000 { 2416 compatible = "qcom,spi-qup-v2.2.1"; 2417 reg = <0x0c175000 0x600>; 2418 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2419 2420 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2421 <&gcc GCC_BLSP1_AHB_CLK>; 2422 clock-names = "core", "iface"; 2423 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2424 dma-names = "tx", "rx"; 2425 pinctrl-names = "default"; 2426 pinctrl-0 = <&blsp1_spi1_default>; 2427 2428 status = "disabled"; 2429 #address-cells = <1>; 2430 #size-cells = <0>; 2431 }; 2432 2433 blsp1_spi2: spi@c176000 { 2434 compatible = "qcom,spi-qup-v2.2.1"; 2435 reg = <0x0c176000 0x600>; 2436 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2437 2438 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 2439 <&gcc GCC_BLSP1_AHB_CLK>; 2440 clock-names = "core", "iface"; 2441 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2442 dma-names = "tx", "rx"; 2443 pinctrl-names = "default"; 2444 pinctrl-0 = <&blsp1_spi2_default>; 2445 2446 status = "disabled"; 2447 #address-cells = <1>; 2448 #size-cells = <0>; 2449 }; 2450 2451 blsp1_spi3: spi@c177000 { 2452 compatible = "qcom,spi-qup-v2.2.1"; 2453 reg = <0x0c177000 0x600>; 2454 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2455 2456 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 2457 <&gcc GCC_BLSP1_AHB_CLK>; 2458 clock-names = "core", "iface"; 2459 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2460 dma-names = "tx", "rx"; 2461 pinctrl-names = "default"; 2462 pinctrl-0 = <&blsp1_spi3_default>; 2463 2464 status = "disabled"; 2465 #address-cells = <1>; 2466 #size-cells = <0>; 2467 }; 2468 2469 blsp1_spi4: spi@c178000 { 2470 compatible = "qcom,spi-qup-v2.2.1"; 2471 reg = <0x0c178000 0x600>; 2472 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2473 2474 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 2475 <&gcc GCC_BLSP1_AHB_CLK>; 2476 clock-names = "core", "iface"; 2477 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2478 dma-names = "tx", "rx"; 2479 pinctrl-names = "default"; 2480 pinctrl-0 = <&blsp1_spi4_default>; 2481 2482 status = "disabled"; 2483 #address-cells = <1>; 2484 #size-cells = <0>; 2485 }; 2486 2487 blsp1_spi5: spi@c179000 { 2488 compatible = "qcom,spi-qup-v2.2.1"; 2489 reg = <0x0c179000 0x600>; 2490 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2491 2492 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 2493 <&gcc GCC_BLSP1_AHB_CLK>; 2494 clock-names = "core", "iface"; 2495 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2496 dma-names = "tx", "rx"; 2497 pinctrl-names = "default"; 2498 pinctrl-0 = <&blsp1_spi5_default>; 2499 2500 status = "disabled"; 2501 #address-cells = <1>; 2502 #size-cells = <0>; 2503 }; 2504 2505 blsp1_spi6: spi@c17a000 { 2506 compatible = "qcom,spi-qup-v2.2.1"; 2507 reg = <0x0c17a000 0x600>; 2508 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2509 2510 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 2511 <&gcc GCC_BLSP1_AHB_CLK>; 2512 clock-names = "core", "iface"; 2513 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2514 dma-names = "tx", "rx"; 2515 pinctrl-names = "default"; 2516 pinctrl-0 = <&blsp1_spi6_default>; 2517 2518 status = "disabled"; 2519 #address-cells = <1>; 2520 #size-cells = <0>; 2521 }; 2522 2523 blsp2_dma: dma-controller@c184000 { 2524 compatible = "qcom,bam-v1.7.0"; 2525 reg = <0x0c184000 0x25000>; 2526 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2527 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2528 clock-names = "bam_clk"; 2529 #dma-cells = <1>; 2530 qcom,ee = <0>; 2531 qcom,controlled-remotely; 2532 num-channels = <18>; 2533 qcom,num-ees = <4>; 2534 }; 2535 2536 blsp2_uart1: serial@c1b0000 { 2537 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2538 reg = <0x0c1b0000 0x1000>; 2539 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2540 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2541 <&gcc GCC_BLSP2_AHB_CLK>; 2542 clock-names = "core", "iface"; 2543 status = "disabled"; 2544 }; 2545 2546 blsp2_i2c1: i2c@c1b5000 { 2547 compatible = "qcom,i2c-qup-v2.2.1"; 2548 reg = <0x0c1b5000 0x600>; 2549 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2550 2551 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2552 <&gcc GCC_BLSP2_AHB_CLK>; 2553 clock-names = "core", "iface"; 2554 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2555 dma-names = "tx", "rx"; 2556 pinctrl-names = "default", "sleep"; 2557 pinctrl-0 = <&blsp2_i2c1_default>; 2558 pinctrl-1 = <&blsp2_i2c1_sleep>; 2559 clock-frequency = <400000>; 2560 2561 status = "disabled"; 2562 #address-cells = <1>; 2563 #size-cells = <0>; 2564 }; 2565 2566 blsp2_i2c2: i2c@c1b6000 { 2567 compatible = "qcom,i2c-qup-v2.2.1"; 2568 reg = <0x0c1b6000 0x600>; 2569 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2570 2571 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2572 <&gcc GCC_BLSP2_AHB_CLK>; 2573 clock-names = "core", "iface"; 2574 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2575 dma-names = "tx", "rx"; 2576 pinctrl-names = "default", "sleep"; 2577 pinctrl-0 = <&blsp2_i2c2_default>; 2578 pinctrl-1 = <&blsp2_i2c2_sleep>; 2579 clock-frequency = <400000>; 2580 2581 status = "disabled"; 2582 #address-cells = <1>; 2583 #size-cells = <0>; 2584 }; 2585 2586 blsp2_i2c3: i2c@c1b7000 { 2587 compatible = "qcom,i2c-qup-v2.2.1"; 2588 reg = <0x0c1b7000 0x600>; 2589 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2590 2591 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 2592 <&gcc GCC_BLSP2_AHB_CLK>; 2593 clock-names = "core", "iface"; 2594 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2595 dma-names = "tx", "rx"; 2596 pinctrl-names = "default", "sleep"; 2597 pinctrl-0 = <&blsp2_i2c3_default>; 2598 pinctrl-1 = <&blsp2_i2c3_sleep>; 2599 clock-frequency = <400000>; 2600 2601 status = "disabled"; 2602 #address-cells = <1>; 2603 #size-cells = <0>; 2604 }; 2605 2606 blsp2_i2c4: i2c@c1b8000 { 2607 compatible = "qcom,i2c-qup-v2.2.1"; 2608 reg = <0x0c1b8000 0x600>; 2609 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2610 2611 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 2612 <&gcc GCC_BLSP2_AHB_CLK>; 2613 clock-names = "core", "iface"; 2614 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2615 dma-names = "tx", "rx"; 2616 pinctrl-names = "default", "sleep"; 2617 pinctrl-0 = <&blsp2_i2c4_default>; 2618 pinctrl-1 = <&blsp2_i2c4_sleep>; 2619 clock-frequency = <400000>; 2620 2621 status = "disabled"; 2622 #address-cells = <1>; 2623 #size-cells = <0>; 2624 }; 2625 2626 blsp2_i2c5: i2c@c1b9000 { 2627 compatible = "qcom,i2c-qup-v2.2.1"; 2628 reg = <0x0c1b9000 0x600>; 2629 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2630 2631 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 2632 <&gcc GCC_BLSP2_AHB_CLK>; 2633 clock-names = "core", "iface"; 2634 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2635 dma-names = "tx", "rx"; 2636 pinctrl-names = "default", "sleep"; 2637 pinctrl-0 = <&blsp2_i2c5_default>; 2638 pinctrl-1 = <&blsp2_i2c5_sleep>; 2639 clock-frequency = <400000>; 2640 2641 status = "disabled"; 2642 #address-cells = <1>; 2643 #size-cells = <0>; 2644 }; 2645 2646 blsp2_i2c6: i2c@c1ba000 { 2647 compatible = "qcom,i2c-qup-v2.2.1"; 2648 reg = <0x0c1ba000 0x600>; 2649 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2650 2651 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 2652 <&gcc GCC_BLSP2_AHB_CLK>; 2653 clock-names = "core", "iface"; 2654 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2655 dma-names = "tx", "rx"; 2656 pinctrl-names = "default", "sleep"; 2657 pinctrl-0 = <&blsp2_i2c6_default>; 2658 pinctrl-1 = <&blsp2_i2c6_sleep>; 2659 clock-frequency = <400000>; 2660 2661 status = "disabled"; 2662 #address-cells = <1>; 2663 #size-cells = <0>; 2664 }; 2665 2666 blsp2_spi1: spi@c1b5000 { 2667 compatible = "qcom,spi-qup-v2.2.1"; 2668 reg = <0x0c1b5000 0x600>; 2669 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2670 2671 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, 2672 <&gcc GCC_BLSP2_AHB_CLK>; 2673 clock-names = "core", "iface"; 2674 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2675 dma-names = "tx", "rx"; 2676 pinctrl-names = "default"; 2677 pinctrl-0 = <&blsp2_spi1_default>; 2678 2679 status = "disabled"; 2680 #address-cells = <1>; 2681 #size-cells = <0>; 2682 }; 2683 2684 blsp2_spi2: spi@c1b6000 { 2685 compatible = "qcom,spi-qup-v2.2.1"; 2686 reg = <0x0c1b6000 0x600>; 2687 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2688 2689 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, 2690 <&gcc GCC_BLSP2_AHB_CLK>; 2691 clock-names = "core", "iface"; 2692 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2693 dma-names = "tx", "rx"; 2694 pinctrl-names = "default"; 2695 pinctrl-0 = <&blsp2_spi2_default>; 2696 2697 status = "disabled"; 2698 #address-cells = <1>; 2699 #size-cells = <0>; 2700 }; 2701 2702 blsp2_spi3: spi@c1b7000 { 2703 compatible = "qcom,spi-qup-v2.2.1"; 2704 reg = <0x0c1b7000 0x600>; 2705 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2706 2707 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, 2708 <&gcc GCC_BLSP2_AHB_CLK>; 2709 clock-names = "core", "iface"; 2710 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2711 dma-names = "tx", "rx"; 2712 pinctrl-names = "default"; 2713 pinctrl-0 = <&blsp2_spi3_default>; 2714 2715 status = "disabled"; 2716 #address-cells = <1>; 2717 #size-cells = <0>; 2718 }; 2719 2720 blsp2_spi4: spi@c1b8000 { 2721 compatible = "qcom,spi-qup-v2.2.1"; 2722 reg = <0x0c1b8000 0x600>; 2723 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2724 2725 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, 2726 <&gcc GCC_BLSP2_AHB_CLK>; 2727 clock-names = "core", "iface"; 2728 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2729 dma-names = "tx", "rx"; 2730 pinctrl-names = "default"; 2731 pinctrl-0 = <&blsp2_spi4_default>; 2732 2733 status = "disabled"; 2734 #address-cells = <1>; 2735 #size-cells = <0>; 2736 }; 2737 2738 blsp2_spi5: spi@c1b9000 { 2739 compatible = "qcom,spi-qup-v2.2.1"; 2740 reg = <0x0c1b9000 0x600>; 2741 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2742 2743 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, 2744 <&gcc GCC_BLSP2_AHB_CLK>; 2745 clock-names = "core", "iface"; 2746 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2747 dma-names = "tx", "rx"; 2748 pinctrl-names = "default"; 2749 pinctrl-0 = <&blsp2_spi5_default>; 2750 2751 status = "disabled"; 2752 #address-cells = <1>; 2753 #size-cells = <0>; 2754 }; 2755 2756 blsp2_spi6: spi@c1ba000 { 2757 compatible = "qcom,spi-qup-v2.2.1"; 2758 reg = <0x0c1ba000 0x600>; 2759 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2760 2761 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 2762 <&gcc GCC_BLSP2_AHB_CLK>; 2763 clock-names = "core", "iface"; 2764 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2765 dma-names = "tx", "rx"; 2766 pinctrl-names = "default"; 2767 pinctrl-0 = <&blsp2_spi6_default>; 2768 2769 status = "disabled"; 2770 #address-cells = <1>; 2771 #size-cells = <0>; 2772 }; 2773 2774 mmcc: clock-controller@c8c0000 { 2775 compatible = "qcom,mmcc-msm8998"; 2776 #clock-cells = <1>; 2777 #reset-cells = <1>; 2778 #power-domain-cells = <1>; 2779 reg = <0xc8c0000 0x40000>; 2780 2781 clock-names = "xo", 2782 "gpll0", 2783 "dsi0dsi", 2784 "dsi0byte", 2785 "dsi1dsi", 2786 "dsi1byte", 2787 "hdmipll", 2788 "dplink", 2789 "dpvco", 2790 "gpll0_div"; 2791 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2792 <&gcc GCC_MMSS_GPLL0_CLK>, 2793 <&mdss_dsi0_phy 1>, 2794 <&mdss_dsi0_phy 0>, 2795 <&mdss_dsi1_phy 1>, 2796 <&mdss_dsi1_phy 0>, 2797 <&mdss_hdmi_phy 0>, 2798 <0>, 2799 <0>, 2800 <&gcc GCC_MMSS_GPLL0_DIV_CLK>; 2801 }; 2802 2803 mdss: display-subsystem@c900000 { 2804 compatible = "qcom,msm8998-mdss"; 2805 reg = <0x0c900000 0x1000>; 2806 reg-names = "mdss"; 2807 2808 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2809 interrupt-controller; 2810 #interrupt-cells = <1>; 2811 2812 clocks = <&mmcc MDSS_AHB_CLK>, 2813 <&mmcc MDSS_AXI_CLK>, 2814 <&mmcc MDSS_MDP_CLK>; 2815 clock-names = "iface", 2816 "bus", 2817 "core"; 2818 2819 power-domains = <&mmcc MDSS_GDSC>; 2820 iommus = <&mmss_smmu 0>; 2821 2822 #address-cells = <1>; 2823 #size-cells = <1>; 2824 ranges; 2825 2826 status = "disabled"; 2827 2828 mdss_mdp: display-controller@c901000 { 2829 compatible = "qcom,msm8998-dpu"; 2830 reg = <0x0c901000 0x8f000>, 2831 <0x0c9a8e00 0xf0>, 2832 <0x0c9b0000 0x2008>, 2833 <0x0c9b8000 0x1040>; 2834 reg-names = "mdp", 2835 "regdma", 2836 "vbif", 2837 "vbif_nrt"; 2838 2839 interrupt-parent = <&mdss>; 2840 interrupts = <0>; 2841 2842 clocks = <&mmcc MDSS_AHB_CLK>, 2843 <&mmcc MDSS_AXI_CLK>, 2844 <&mmcc MNOC_AHB_CLK>, 2845 <&mmcc MDSS_MDP_CLK>, 2846 <&mmcc MDSS_VSYNC_CLK>; 2847 clock-names = "iface", 2848 "bus", 2849 "mnoc", 2850 "core", 2851 "vsync"; 2852 2853 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>; 2854 assigned-clock-rates = <19200000>; 2855 2856 operating-points-v2 = <&mdp_opp_table>; 2857 power-domains = <&rpmpd MSM8998_VDDMX>; 2858 2859 mdp_opp_table: opp-table { 2860 compatible = "operating-points-v2"; 2861 2862 opp-171430000 { 2863 opp-hz = /bits/ 64 <171430000>; 2864 required-opps = <&rpmpd_opp_low_svs>; 2865 }; 2866 2867 opp-275000000 { 2868 opp-hz = /bits/ 64 <275000000>; 2869 required-opps = <&rpmpd_opp_svs>; 2870 }; 2871 2872 opp-330000000 { 2873 opp-hz = /bits/ 64 <330000000>; 2874 required-opps = <&rpmpd_opp_nom>; 2875 }; 2876 2877 opp-412500000 { 2878 opp-hz = /bits/ 64 <412500000>; 2879 required-opps = <&rpmpd_opp_turbo>; 2880 }; 2881 }; 2882 2883 ports { 2884 #address-cells = <1>; 2885 #size-cells = <0>; 2886 2887 port@0 { 2888 reg = <0>; 2889 2890 dpu_intf1_out: endpoint { 2891 remote-endpoint = <&mdss_dsi0_in>; 2892 }; 2893 }; 2894 2895 port@1 { 2896 reg = <1>; 2897 2898 dpu_intf2_out: endpoint { 2899 remote-endpoint = <&mdss_dsi1_in>; 2900 }; 2901 }; 2902 2903 port@2 { 2904 reg = <2>; 2905 2906 dpu_intf3_out: endpoint { 2907 remote-endpoint = <&hdmi_in>; 2908 }; 2909 }; 2910 }; 2911 }; 2912 2913 mdss_dsi0: dsi@c994000 { 2914 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2915 reg = <0x0c994000 0x400>; 2916 reg-names = "dsi_ctrl"; 2917 2918 interrupt-parent = <&mdss>; 2919 interrupts = <4>; 2920 2921 clocks = <&mmcc MDSS_BYTE0_CLK>, 2922 <&mmcc MDSS_BYTE0_INTF_CLK>, 2923 <&mmcc MDSS_PCLK0_CLK>, 2924 <&mmcc MDSS_ESC0_CLK>, 2925 <&mmcc MDSS_AHB_CLK>, 2926 <&mmcc MDSS_AXI_CLK>; 2927 clock-names = "byte", 2928 "byte_intf", 2929 "pixel", 2930 "core", 2931 "iface", 2932 "bus"; 2933 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 2934 <&mmcc PCLK0_CLK_SRC>; 2935 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2936 <&mdss_dsi0_phy 1>; 2937 2938 operating-points-v2 = <&dsi_opp_table>; 2939 power-domains = <&rpmpd MSM8998_VDDCX>; 2940 2941 phys = <&mdss_dsi0_phy>; 2942 phy-names = "dsi"; 2943 2944 #address-cells = <1>; 2945 #size-cells = <0>; 2946 2947 status = "disabled"; 2948 2949 ports { 2950 #address-cells = <1>; 2951 #size-cells = <0>; 2952 2953 port@0 { 2954 reg = <0>; 2955 2956 mdss_dsi0_in: endpoint { 2957 remote-endpoint = <&dpu_intf1_out>; 2958 }; 2959 }; 2960 2961 port@1 { 2962 reg = <1>; 2963 2964 mdss_dsi0_out: endpoint { 2965 }; 2966 }; 2967 }; 2968 }; 2969 2970 mdss_dsi0_phy: phy@c994400 { 2971 compatible = "qcom,dsi-phy-10nm-8998"; 2972 reg = <0x0c994400 0x200>, 2973 <0x0c994600 0x280>, 2974 <0x0c994a00 0x1e0>; 2975 reg-names = "dsi_phy", 2976 "dsi_phy_lane", 2977 "dsi_pll"; 2978 2979 clocks = <&mmcc MDSS_AHB_CLK>, 2980 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2981 clock-names = "iface", "ref"; 2982 2983 #clock-cells = <1>; 2984 #phy-cells = <0>; 2985 2986 status = "disabled"; 2987 }; 2988 2989 mdss_dsi1: dsi@c996000 { 2990 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2991 reg = <0x0c996000 0x400>; 2992 reg-names = "dsi_ctrl"; 2993 2994 interrupt-parent = <&mdss>; 2995 interrupts = <5>; 2996 2997 clocks = <&mmcc MDSS_BYTE1_CLK>, 2998 <&mmcc MDSS_BYTE1_INTF_CLK>, 2999 <&mmcc MDSS_PCLK1_CLK>, 3000 <&mmcc MDSS_ESC1_CLK>, 3001 <&mmcc MDSS_AHB_CLK>, 3002 <&mmcc MDSS_AXI_CLK>; 3003 clock-names = "byte", 3004 "byte_intf", 3005 "pixel", 3006 "core", 3007 "iface", 3008 "bus"; 3009 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, 3010 <&mmcc PCLK1_CLK_SRC>; 3011 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3012 <&mdss_dsi1_phy 1>; 3013 3014 operating-points-v2 = <&dsi_opp_table>; 3015 power-domains = <&rpmpd MSM8998_VDDCX>; 3016 3017 phys = <&mdss_dsi1_phy>; 3018 phy-names = "dsi"; 3019 3020 #address-cells = <1>; 3021 #size-cells = <0>; 3022 3023 status = "disabled"; 3024 3025 ports { 3026 #address-cells = <1>; 3027 #size-cells = <0>; 3028 3029 port@0 { 3030 reg = <0>; 3031 3032 mdss_dsi1_in: endpoint { 3033 remote-endpoint = <&dpu_intf2_out>; 3034 }; 3035 }; 3036 3037 port@1 { 3038 reg = <1>; 3039 3040 mdss_dsi1_out: endpoint { 3041 }; 3042 }; 3043 }; 3044 }; 3045 3046 mdss_dsi1_phy: phy@c996400 { 3047 compatible = "qcom,dsi-phy-10nm-8998"; 3048 reg = <0x0c996400 0x200>, 3049 <0x0c996600 0x280>, 3050 <0x0c996a00 0x10e>; 3051 reg-names = "dsi_phy", 3052 "dsi_phy_lane", 3053 "dsi_pll"; 3054 3055 clocks = <&mmcc MDSS_AHB_CLK>, 3056 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3057 clock-names = "iface", 3058 "ref"; 3059 3060 #clock-cells = <1>; 3061 #phy-cells = <0>; 3062 3063 status = "disabled"; 3064 }; 3065 3066 mdss_hdmi: hdmi-tx@c9a0000 { 3067 compatible = "qcom,hdmi-tx-8998"; 3068 reg = <0x0c9a0000 0x50c>, 3069 <0x00780000 0x6220>, 3070 <0x0c9e0000 0x2c>; 3071 reg-names = "core_physical", 3072 "qfprom_physical", 3073 "hdcp_physical"; 3074 3075 interrupt-parent = <&mdss>; 3076 interrupts = <8>; 3077 3078 clocks = <&mmcc MDSS_MDP_CLK>, 3079 <&mmcc MDSS_AHB_CLK>, 3080 <&mmcc MDSS_HDMI_CLK>, 3081 <&mmcc MDSS_HDMI_DP_AHB_CLK>, 3082 <&mmcc MDSS_EXTPCLK_CLK>, 3083 <&mmcc MDSS_AXI_CLK>, 3084 <&mmcc MNOC_AHB_CLK>, 3085 <&mmcc MISC_AHB_CLK>; 3086 clock-names = 3087 "mdp_core", 3088 "iface", 3089 "core", 3090 "alt_iface", 3091 "extp", 3092 "bus", 3093 "mnoc", 3094 "iface_mmss"; 3095 3096 phys = <&mdss_hdmi_phy>; 3097 #sound-dai-cells = <1>; 3098 3099 pinctrl-0 = <&hdmi_hpd_default>, 3100 <&hdmi_ddc_default>, 3101 <&hdmi_cec_default>; 3102 pinctrl-1 = <&hdmi_hpd_sleep>, 3103 <&hdmi_ddc_default>, 3104 <&hdmi_cec_default>; 3105 pinctrl-names = "default", "sleep"; 3106 3107 status = "disabled"; 3108 3109 ports { 3110 #address-cells = <1>; 3111 #size-cells = <0>; 3112 3113 port@0 { 3114 reg = <0>; 3115 hdmi_in: endpoint { 3116 remote-endpoint = <&dpu_intf3_out>; 3117 }; 3118 }; 3119 3120 port@1 { 3121 reg = <1>; 3122 hdmi_out: endpoint { 3123 }; 3124 }; 3125 }; 3126 }; 3127 3128 mdss_hdmi_phy: hdmi-phy@c9a0600 { 3129 compatible = "qcom,hdmi-phy-8998"; 3130 reg = <0x0c9a0600 0x18b>, 3131 <0x0c9a0a00 0x38>, 3132 <0x0c9a0c00 0x38>, 3133 <0x0c9a0e00 0x38>, 3134 <0x0c9a1000 0x38>, 3135 <0x0c9a1200 0x0e8>; 3136 reg-names = "hdmi_pll", 3137 "hdmi_tx_l0", 3138 "hdmi_tx_l1", 3139 "hdmi_tx_l2", 3140 "hdmi_tx_l3", 3141 "hdmi_phy"; 3142 3143 #clock-cells = <0>; 3144 #phy-cells = <0>; 3145 3146 clocks = <&mmcc MDSS_AHB_CLK>, 3147 <&gcc GCC_HDMI_CLKREF_CLK>, 3148 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3149 clock-names = "iface", 3150 "ref", 3151 "xo"; 3152 3153 status = "disabled"; 3154 }; 3155 }; 3156 3157 venus: video-codec@cc00000 { 3158 compatible = "qcom,msm8998-venus"; 3159 reg = <0x0cc00000 0xff000>; 3160 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 3161 power-domains = <&mmcc VIDEO_TOP_GDSC>; 3162 clocks = <&mmcc VIDEO_CORE_CLK>, 3163 <&mmcc VIDEO_AHB_CLK>, 3164 <&mmcc VIDEO_AXI_CLK>, 3165 <&mmcc VIDEO_MAXI_CLK>; 3166 clock-names = "core", "iface", "bus", "mbus"; 3167 iommus = <&mmss_smmu 0x400>, 3168 <&mmss_smmu 0x401>, 3169 <&mmss_smmu 0x40a>, 3170 <&mmss_smmu 0x407>, 3171 <&mmss_smmu 0x40e>, 3172 <&mmss_smmu 0x40f>, 3173 <&mmss_smmu 0x408>, 3174 <&mmss_smmu 0x409>, 3175 <&mmss_smmu 0x40b>, 3176 <&mmss_smmu 0x40c>, 3177 <&mmss_smmu 0x40d>, 3178 <&mmss_smmu 0x410>, 3179 <&mmss_smmu 0x421>, 3180 <&mmss_smmu 0x428>, 3181 <&mmss_smmu 0x429>, 3182 <&mmss_smmu 0x42b>, 3183 <&mmss_smmu 0x42c>, 3184 <&mmss_smmu 0x42d>, 3185 <&mmss_smmu 0x411>, 3186 <&mmss_smmu 0x431>; 3187 memory-region = <&venus_mem>; 3188 status = "disabled"; 3189 3190 video-decoder { 3191 compatible = "venus-decoder"; 3192 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 3193 clock-names = "core"; 3194 power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>; 3195 }; 3196 3197 video-encoder { 3198 compatible = "venus-encoder"; 3199 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 3200 clock-names = "core"; 3201 power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>; 3202 }; 3203 }; 3204 3205 mmss_smmu: iommu@cd00000 { 3206 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 3207 reg = <0x0cd00000 0x40000>; 3208 #iommu-cells = <1>; 3209 3210 clocks = <&mmcc MNOC_AHB_CLK>, 3211 <&mmcc BIMC_SMMU_AHB_CLK>, 3212 <&mmcc BIMC_SMMU_AXI_CLK>; 3213 clock-names = "iface-mm", 3214 "iface-smmu", 3215 "bus-smmu"; 3216 3217 #global-interrupts = <0>; 3218 interrupts = 3219 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 3220 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 3221 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 3222 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 3223 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 3224 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 3225 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 3226 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 3227 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 3228 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 3229 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 3230 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 3231 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 3232 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 3238 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3239 3240 power-domains = <&mmcc BIMC_SMMU_GDSC>; 3241 }; 3242 3243 remoteproc_adsp: remoteproc@17300000 { 3244 compatible = "qcom,msm8998-adsp-pas"; 3245 reg = <0x17300000 0x4040>; 3246 3247 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3248 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3249 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3250 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3251 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3252 interrupt-names = "wdog", "fatal", "ready", 3253 "handover", "stop-ack"; 3254 3255 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3256 clock-names = "xo"; 3257 3258 memory-region = <&adsp_mem>; 3259 3260 qcom,smem-states = <&adsp_smp2p_out 0>; 3261 qcom,smem-state-names = "stop"; 3262 3263 power-domains = <&rpmpd MSM8998_VDDCX>; 3264 power-domain-names = "cx"; 3265 3266 status = "disabled"; 3267 3268 glink-edge { 3269 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 3270 label = "lpass"; 3271 qcom,remote-pid = <2>; 3272 mboxes = <&apcs_glb 9>; 3273 }; 3274 }; 3275 3276 apcs_glb: mailbox@17911000 { 3277 compatible = "qcom,msm8998-apcs-hmss-global", 3278 "qcom,msm8994-apcs-kpss-global"; 3279 reg = <0x17911000 0x1000>; 3280 3281 #mbox-cells = <1>; 3282 }; 3283 3284 timer@17920000 { 3285 #address-cells = <1>; 3286 #size-cells = <1>; 3287 ranges; 3288 compatible = "arm,armv7-timer-mem"; 3289 reg = <0x17920000 0x1000>; 3290 3291 frame@17921000 { 3292 frame-number = <0>; 3293 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 3295 reg = <0x17921000 0x1000>, 3296 <0x17922000 0x1000>; 3297 }; 3298 3299 frame@17923000 { 3300 frame-number = <1>; 3301 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3302 reg = <0x17923000 0x1000>; 3303 status = "disabled"; 3304 }; 3305 3306 frame@17924000 { 3307 frame-number = <2>; 3308 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3309 reg = <0x17924000 0x1000>; 3310 status = "disabled"; 3311 }; 3312 3313 frame@17925000 { 3314 frame-number = <3>; 3315 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3316 reg = <0x17925000 0x1000>; 3317 status = "disabled"; 3318 }; 3319 3320 frame@17926000 { 3321 frame-number = <4>; 3322 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3323 reg = <0x17926000 0x1000>; 3324 status = "disabled"; 3325 }; 3326 3327 frame@17927000 { 3328 frame-number = <5>; 3329 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3330 reg = <0x17927000 0x1000>; 3331 status = "disabled"; 3332 }; 3333 3334 frame@17928000 { 3335 frame-number = <6>; 3336 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3337 reg = <0x17928000 0x1000>; 3338 status = "disabled"; 3339 }; 3340 }; 3341 3342 intc: interrupt-controller@17a00000 { 3343 compatible = "arm,gic-v3"; 3344 reg = <0x17a00000 0x10000>, /* GICD */ 3345 <0x17b00000 0x100000>; /* GICR * 8 */ 3346 #interrupt-cells = <3>; 3347 #address-cells = <1>; 3348 #size-cells = <1>; 3349 ranges; 3350 interrupt-controller; 3351 #redistributor-regions = <1>; 3352 redistributor-stride = <0x0 0x20000>; 3353 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3354 }; 3355 3356 wifi: wifi@18800000 { 3357 compatible = "qcom,wcn3990-wifi"; 3358 status = "disabled"; 3359 reg = <0x18800000 0x800000>; 3360 reg-names = "membase"; 3361 memory-region = <&wlan_msa_mem>; 3362 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 3363 clock-names = "cxo_ref_clk_pin"; 3364 interrupts = 3365 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3377 iommus = <&anoc2_smmu 0x1900>, 3378 <&anoc2_smmu 0x1901>; 3379 qcom,snoc-host-cap-8bit-quirk; 3380 qcom,no-msa-ready-indicator; 3381 }; 3382 }; 3383}; 3384