1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,gcc-msm8998.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/power/qcom-rpmpd.h> 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 interrupt-parent = <&intc>; 12 13 qcom,msm-id = <292 0x0>; 14 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { }; 19 20 memory { 21 device_type = "memory"; 22 /* We expect the bootloader to fill in the reg */ 23 reg = <0 0 0 0>; 24 }; 25 26 reserved-memory { 27 #address-cells = <2>; 28 #size-cells = <2>; 29 ranges; 30 31 memory@85800000 { 32 reg = <0x0 0x85800000 0x0 0x800000>; 33 no-map; 34 }; 35 36 smem_mem: smem-mem@86000000 { 37 reg = <0x0 0x86000000 0x0 0x200000>; 38 no-map; 39 }; 40 41 memory@86200000 { 42 reg = <0x0 0x86200000 0x0 0x2d00000>; 43 no-map; 44 }; 45 46 rmtfs { 47 compatible = "qcom,rmtfs-mem"; 48 49 size = <0x0 0x200000>; 50 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 51 no-map; 52 53 qcom,client-id = <1>; 54 qcom,vmid = <15>; 55 }; 56 }; 57 58 clocks { 59 xo: xo-board { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <19200000>; 63 clock-output-names = "xo_board"; 64 }; 65 66 sleep_clk { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <32764>; 70 }; 71 }; 72 73 cpus { 74 #address-cells = <2>; 75 #size-cells = <0>; 76 77 CPU0: cpu@0 { 78 device_type = "cpu"; 79 compatible = "arm,armv8"; 80 reg = <0x0 0x0>; 81 enable-method = "psci"; 82 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 83 next-level-cache = <&L2_0>; 84 L2_0: l2-cache { 85 compatible = "arm,arch-cache"; 86 cache-level = <2>; 87 }; 88 L1_I_0: l1-icache { 89 compatible = "arm,arch-cache"; 90 }; 91 L1_D_0: l1-dcache { 92 compatible = "arm,arch-cache"; 93 }; 94 }; 95 96 CPU1: cpu@1 { 97 device_type = "cpu"; 98 compatible = "arm,armv8"; 99 reg = <0x0 0x1>; 100 enable-method = "psci"; 101 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 102 next-level-cache = <&L2_0>; 103 L1_I_1: l1-icache { 104 compatible = "arm,arch-cache"; 105 }; 106 L1_D_1: l1-dcache { 107 compatible = "arm,arch-cache"; 108 }; 109 }; 110 111 CPU2: cpu@2 { 112 device_type = "cpu"; 113 compatible = "arm,armv8"; 114 reg = <0x0 0x2>; 115 enable-method = "psci"; 116 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 117 next-level-cache = <&L2_0>; 118 L1_I_2: l1-icache { 119 compatible = "arm,arch-cache"; 120 }; 121 L1_D_2: l1-dcache { 122 compatible = "arm,arch-cache"; 123 }; 124 }; 125 126 CPU3: cpu@3 { 127 device_type = "cpu"; 128 compatible = "arm,armv8"; 129 reg = <0x0 0x3>; 130 enable-method = "psci"; 131 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 132 next-level-cache = <&L2_0>; 133 L1_I_3: l1-icache { 134 compatible = "arm,arch-cache"; 135 }; 136 L1_D_3: l1-dcache { 137 compatible = "arm,arch-cache"; 138 }; 139 }; 140 141 CPU4: cpu@100 { 142 device_type = "cpu"; 143 compatible = "arm,armv8"; 144 reg = <0x0 0x100>; 145 enable-method = "psci"; 146 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 147 next-level-cache = <&L2_1>; 148 L2_1: l2-cache { 149 compatible = "arm,arch-cache"; 150 cache-level = <2>; 151 }; 152 L1_I_100: l1-icache { 153 compatible = "arm,arch-cache"; 154 }; 155 L1_D_100: l1-dcache { 156 compatible = "arm,arch-cache"; 157 }; 158 }; 159 160 CPU5: cpu@101 { 161 device_type = "cpu"; 162 compatible = "arm,armv8"; 163 reg = <0x0 0x101>; 164 enable-method = "psci"; 165 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 166 next-level-cache = <&L2_1>; 167 L1_I_101: l1-icache { 168 compatible = "arm,arch-cache"; 169 }; 170 L1_D_101: l1-dcache { 171 compatible = "arm,arch-cache"; 172 }; 173 }; 174 175 CPU6: cpu@102 { 176 device_type = "cpu"; 177 compatible = "arm,armv8"; 178 reg = <0x0 0x102>; 179 enable-method = "psci"; 180 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 181 next-level-cache = <&L2_1>; 182 L1_I_102: l1-icache { 183 compatible = "arm,arch-cache"; 184 }; 185 L1_D_102: l1-dcache { 186 compatible = "arm,arch-cache"; 187 }; 188 }; 189 190 CPU7: cpu@103 { 191 device_type = "cpu"; 192 compatible = "arm,armv8"; 193 reg = <0x0 0x103>; 194 enable-method = "psci"; 195 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 196 next-level-cache = <&L2_1>; 197 L1_I_103: l1-icache { 198 compatible = "arm,arch-cache"; 199 }; 200 L1_D_103: l1-dcache { 201 compatible = "arm,arch-cache"; 202 }; 203 }; 204 205 cpu-map { 206 cluster0 { 207 core0 { 208 cpu = <&CPU0>; 209 }; 210 211 core1 { 212 cpu = <&CPU1>; 213 }; 214 215 core2 { 216 cpu = <&CPU2>; 217 }; 218 219 core3 { 220 cpu = <&CPU3>; 221 }; 222 }; 223 224 cluster1 { 225 core0 { 226 cpu = <&CPU4>; 227 }; 228 229 core1 { 230 cpu = <&CPU5>; 231 }; 232 233 core2 { 234 cpu = <&CPU6>; 235 }; 236 237 core3 { 238 cpu = <&CPU7>; 239 }; 240 }; 241 }; 242 243 idle-states { 244 entry-method = "psci"; 245 246 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 247 compatible = "arm,idle-state"; 248 idle-state-name = "little-retention"; 249 arm,psci-suspend-param = <0x00000002>; 250 entry-latency-us = <81>; 251 exit-latency-us = <86>; 252 min-residency-us = <200>; 253 }; 254 255 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 256 compatible = "arm,idle-state"; 257 idle-state-name = "little-power-collapse"; 258 arm,psci-suspend-param = <0x40000003>; 259 entry-latency-us = <273>; 260 exit-latency-us = <612>; 261 min-residency-us = <1000>; 262 local-timer-stop; 263 }; 264 265 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 266 compatible = "arm,idle-state"; 267 idle-state-name = "big-retention"; 268 arm,psci-suspend-param = <0x00000002>; 269 entry-latency-us = <79>; 270 exit-latency-us = <82>; 271 min-residency-us = <200>; 272 }; 273 274 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 275 compatible = "arm,idle-state"; 276 idle-state-name = "big-power-collapse"; 277 arm,psci-suspend-param = <0x40000003>; 278 entry-latency-us = <336>; 279 exit-latency-us = <525>; 280 min-residency-us = <1000>; 281 local-timer-stop; 282 }; 283 }; 284 }; 285 286 firmware { 287 scm { 288 compatible = "qcom,scm-msm8998", "qcom,scm"; 289 }; 290 }; 291 292 tcsr_mutex: hwlock { 293 compatible = "qcom,tcsr-mutex"; 294 syscon = <&tcsr_mutex_regs 0 0x1000>; 295 #hwlock-cells = <1>; 296 }; 297 298 psci { 299 compatible = "arm,psci-1.0"; 300 method = "smc"; 301 }; 302 303 rpm-glink { 304 compatible = "qcom,glink-rpm"; 305 306 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 307 qcom,rpm-msg-ram = <&rpm_msg_ram>; 308 mboxes = <&apcs_glb 0>; 309 310 rpm_requests: rpm-requests { 311 compatible = "qcom,rpm-msm8998"; 312 qcom,glink-channels = "rpm_requests"; 313 314 rpmcc: clock-controller { 315 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 316 #clock-cells = <1>; 317 }; 318 319 rpmpd: power-controller { 320 compatible = "qcom,msm8998-rpmpd"; 321 #power-domain-cells = <1>; 322 operating-points-v2 = <&rpmpd_opp_table>; 323 324 rpmpd_opp_table: opp-table { 325 compatible = "operating-points-v2"; 326 327 rpmpd_opp_ret: opp1 { 328 opp-level = <16>; 329 }; 330 331 rpmpd_opp_ret_plus: opp2 { 332 opp-level = <32>; 333 }; 334 335 rpmpd_opp_min_svs: opp3 { 336 opp-level = <48>; 337 }; 338 339 rpmpd_opp_low_svs: opp4 { 340 opp-level = <64>; 341 }; 342 343 rpmpd_opp_svs: opp5 { 344 opp-level = <128>; 345 }; 346 347 rpmpd_opp_svs_plus: opp6 { 348 opp-level = <192>; 349 }; 350 351 rpmpd_opp_nom: opp7 { 352 opp-level = <256>; 353 }; 354 355 rpmpd_opp_nom_plus: opp8 { 356 opp-level = <320>; 357 }; 358 359 rpmpd_opp_turbo: opp9 { 360 opp-level = <384>; 361 }; 362 363 rpmpd_opp_turbo_plus: opp10 { 364 opp-level = <512>; 365 }; 366 }; 367 }; 368 }; 369 }; 370 371 smem { 372 compatible = "qcom,smem"; 373 memory-region = <&smem_mem>; 374 hwlocks = <&tcsr_mutex 3>; 375 }; 376 377 smp2p-lpass { 378 compatible = "qcom,smp2p"; 379 qcom,smem = <443>, <429>; 380 381 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 382 383 mboxes = <&apcs_glb 10>; 384 385 qcom,local-pid = <0>; 386 qcom,remote-pid = <2>; 387 388 adsp_smp2p_out: master-kernel { 389 qcom,entry-name = "master-kernel"; 390 #qcom,smem-state-cells = <1>; 391 }; 392 393 adsp_smp2p_in: slave-kernel { 394 qcom,entry-name = "slave-kernel"; 395 396 interrupt-controller; 397 #interrupt-cells = <2>; 398 }; 399 }; 400 401 smp2p-mpss { 402 compatible = "qcom,smp2p"; 403 qcom,smem = <435>, <428>; 404 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 405 mboxes = <&apcs_glb 14>; 406 qcom,local-pid = <0>; 407 qcom,remote-pid = <1>; 408 409 modem_smp2p_out: master-kernel { 410 qcom,entry-name = "master-kernel"; 411 #qcom,smem-state-cells = <1>; 412 }; 413 414 modem_smp2p_in: slave-kernel { 415 qcom,entry-name = "slave-kernel"; 416 interrupt-controller; 417 #interrupt-cells = <2>; 418 }; 419 }; 420 421 smp2p-slpi { 422 compatible = "qcom,smp2p"; 423 qcom,smem = <481>, <430>; 424 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 425 mboxes = <&apcs_glb 26>; 426 qcom,local-pid = <0>; 427 qcom,remote-pid = <3>; 428 429 slpi_smp2p_out: master-kernel { 430 qcom,entry-name = "master-kernel"; 431 #qcom,smem-state-cells = <1>; 432 }; 433 434 slpi_smp2p_in: slave-kernel { 435 qcom,entry-name = "slave-kernel"; 436 interrupt-controller; 437 #interrupt-cells = <2>; 438 }; 439 }; 440 441 thermal-zones { 442 cpu0-thermal { 443 polling-delay-passive = <250>; 444 polling-delay = <1000>; 445 446 thermal-sensors = <&tsens0 1>; 447 448 trips { 449 cpu0_alert0: trip-point@0 { 450 temperature = <75000>; 451 hysteresis = <2000>; 452 type = "passive"; 453 }; 454 455 cpu0_crit: cpu_crit { 456 temperature = <110000>; 457 hysteresis = <2000>; 458 type = "critical"; 459 }; 460 }; 461 }; 462 463 cpu1-thermal { 464 polling-delay-passive = <250>; 465 polling-delay = <1000>; 466 467 thermal-sensors = <&tsens0 2>; 468 469 trips { 470 cpu1_alert0: trip-point@0 { 471 temperature = <75000>; 472 hysteresis = <2000>; 473 type = "passive"; 474 }; 475 476 cpu1_crit: cpu_crit { 477 temperature = <110000>; 478 hysteresis = <2000>; 479 type = "critical"; 480 }; 481 }; 482 }; 483 484 cpu2-thermal { 485 polling-delay-passive = <250>; 486 polling-delay = <1000>; 487 488 thermal-sensors = <&tsens0 3>; 489 490 trips { 491 cpu2_alert0: trip-point@0 { 492 temperature = <75000>; 493 hysteresis = <2000>; 494 type = "passive"; 495 }; 496 497 cpu2_crit: cpu_crit { 498 temperature = <110000>; 499 hysteresis = <2000>; 500 type = "critical"; 501 }; 502 }; 503 }; 504 505 cpu3-thermal { 506 polling-delay-passive = <250>; 507 polling-delay = <1000>; 508 509 thermal-sensors = <&tsens0 4>; 510 511 trips { 512 cpu3_alert0: trip-point@0 { 513 temperature = <75000>; 514 hysteresis = <2000>; 515 type = "passive"; 516 }; 517 518 cpu3_crit: cpu_crit { 519 temperature = <110000>; 520 hysteresis = <2000>; 521 type = "critical"; 522 }; 523 }; 524 }; 525 526 cpu4-thermal { 527 polling-delay-passive = <250>; 528 polling-delay = <1000>; 529 530 thermal-sensors = <&tsens0 7>; 531 532 trips { 533 cpu4_alert0: trip-point@0 { 534 temperature = <75000>; 535 hysteresis = <2000>; 536 type = "passive"; 537 }; 538 539 cpu4_crit: cpu_crit { 540 temperature = <110000>; 541 hysteresis = <2000>; 542 type = "critical"; 543 }; 544 }; 545 }; 546 547 cpu5-thermal { 548 polling-delay-passive = <250>; 549 polling-delay = <1000>; 550 551 thermal-sensors = <&tsens0 8>; 552 553 trips { 554 cpu5_alert0: trip-point@0 { 555 temperature = <75000>; 556 hysteresis = <2000>; 557 type = "passive"; 558 }; 559 560 cpu5_crit: cpu_crit { 561 temperature = <110000>; 562 hysteresis = <2000>; 563 type = "critical"; 564 }; 565 }; 566 }; 567 568 cpu6-thermal { 569 polling-delay-passive = <250>; 570 polling-delay = <1000>; 571 572 thermal-sensors = <&tsens0 9>; 573 574 trips { 575 cpu6_alert0: trip-point@0 { 576 temperature = <75000>; 577 hysteresis = <2000>; 578 type = "passive"; 579 }; 580 581 cpu6_crit: cpu_crit { 582 temperature = <110000>; 583 hysteresis = <2000>; 584 type = "critical"; 585 }; 586 }; 587 }; 588 589 cpu7-thermal { 590 polling-delay-passive = <250>; 591 polling-delay = <1000>; 592 593 thermal-sensors = <&tsens0 10>; 594 595 trips { 596 cpu7_alert0: trip-point@0 { 597 temperature = <75000>; 598 hysteresis = <2000>; 599 type = "passive"; 600 }; 601 602 cpu7_crit: cpu_crit { 603 temperature = <110000>; 604 hysteresis = <2000>; 605 type = "critical"; 606 }; 607 }; 608 }; 609 610 gpu-thermal-bottom { 611 polling-delay-passive = <250>; 612 polling-delay = <1000>; 613 614 thermal-sensors = <&tsens0 12>; 615 616 trips { 617 gpu1_alert0: trip-point@0 { 618 temperature = <90000>; 619 hysteresis = <2000>; 620 type = "hot"; 621 }; 622 }; 623 }; 624 625 gpu-thermal-top { 626 polling-delay-passive = <250>; 627 polling-delay = <1000>; 628 629 thermal-sensors = <&tsens0 13>; 630 631 trips { 632 gpu2_alert0: trip-point@0 { 633 temperature = <90000>; 634 hysteresis = <2000>; 635 type = "hot"; 636 }; 637 }; 638 }; 639 640 clust0-mhm-thermal { 641 polling-delay-passive = <250>; 642 polling-delay = <1000>; 643 644 thermal-sensors = <&tsens0 5>; 645 646 trips { 647 cluster0_mhm_alert0: trip-point@0 { 648 temperature = <90000>; 649 hysteresis = <2000>; 650 type = "hot"; 651 }; 652 }; 653 }; 654 655 clust1-mhm-thermal { 656 polling-delay-passive = <250>; 657 polling-delay = <1000>; 658 659 thermal-sensors = <&tsens0 6>; 660 661 trips { 662 cluster1_mhm_alert0: trip-point@0 { 663 temperature = <90000>; 664 hysteresis = <2000>; 665 type = "hot"; 666 }; 667 }; 668 }; 669 670 cluster1-l2-thermal { 671 polling-delay-passive = <250>; 672 polling-delay = <1000>; 673 674 thermal-sensors = <&tsens0 11>; 675 676 trips { 677 cluster1_l2_alert0: trip-point@0 { 678 temperature = <90000>; 679 hysteresis = <2000>; 680 type = "hot"; 681 }; 682 }; 683 }; 684 685 modem-thermal { 686 polling-delay-passive = <250>; 687 polling-delay = <1000>; 688 689 thermal-sensors = <&tsens1 1>; 690 691 trips { 692 modem_alert0: trip-point@0 { 693 temperature = <90000>; 694 hysteresis = <2000>; 695 type = "hot"; 696 }; 697 }; 698 }; 699 700 mem-thermal { 701 polling-delay-passive = <250>; 702 polling-delay = <1000>; 703 704 thermal-sensors = <&tsens1 2>; 705 706 trips { 707 mem_alert0: trip-point@0 { 708 temperature = <90000>; 709 hysteresis = <2000>; 710 type = "hot"; 711 }; 712 }; 713 }; 714 715 wlan-thermal { 716 polling-delay-passive = <250>; 717 polling-delay = <1000>; 718 719 thermal-sensors = <&tsens1 3>; 720 721 trips { 722 wlan_alert0: trip-point@0 { 723 temperature = <90000>; 724 hysteresis = <2000>; 725 type = "hot"; 726 }; 727 }; 728 }; 729 730 q6-dsp-thermal { 731 polling-delay-passive = <250>; 732 polling-delay = <1000>; 733 734 thermal-sensors = <&tsens1 4>; 735 736 trips { 737 q6_dsp_alert0: trip-point@0 { 738 temperature = <90000>; 739 hysteresis = <2000>; 740 type = "hot"; 741 }; 742 }; 743 }; 744 745 camera-thermal { 746 polling-delay-passive = <250>; 747 polling-delay = <1000>; 748 749 thermal-sensors = <&tsens1 5>; 750 751 trips { 752 camera_alert0: trip-point@0 { 753 temperature = <90000>; 754 hysteresis = <2000>; 755 type = "hot"; 756 }; 757 }; 758 }; 759 760 multimedia-thermal { 761 polling-delay-passive = <250>; 762 polling-delay = <1000>; 763 764 thermal-sensors = <&tsens1 6>; 765 766 trips { 767 multimedia_alert0: trip-point@0 { 768 temperature = <90000>; 769 hysteresis = <2000>; 770 type = "hot"; 771 }; 772 }; 773 }; 774 }; 775 776 timer { 777 compatible = "arm,armv8-timer"; 778 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 779 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 780 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 781 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 782 }; 783 784 soc: soc { 785 #address-cells = <1>; 786 #size-cells = <1>; 787 ranges = <0 0 0 0xffffffff>; 788 compatible = "simple-bus"; 789 790 rpm_msg_ram: memory@68000 { 791 compatible = "qcom,rpm-msg-ram"; 792 reg = <0x778000 0x7000>; 793 }; 794 795 qfprom: qfprom@780000 { 796 compatible = "qcom,qfprom"; 797 reg = <0x780000 0x621c>; 798 #address-cells = <1>; 799 #size-cells = <1>; 800 801 qusb2_hstx_trim: hstx-trim@423a { 802 reg = <0x423a 0x1>; 803 bits = <0 4>; 804 }; 805 }; 806 807 gcc: clock-controller@100000 { 808 compatible = "qcom,gcc-msm8998"; 809 #clock-cells = <1>; 810 #reset-cells = <1>; 811 #power-domain-cells = <1>; 812 reg = <0x100000 0xb0000>; 813 }; 814 815 tlmm: pinctrl@3400000 { 816 compatible = "qcom,msm8998-pinctrl"; 817 reg = <0x3400000 0xc00000>; 818 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 819 gpio-controller; 820 #gpio-cells = <0x2>; 821 interrupt-controller; 822 #interrupt-cells = <0x2>; 823 }; 824 825 spmi_bus: spmi@800f000 { 826 compatible = "qcom,spmi-pmic-arb"; 827 reg = <0x800f000 0x1000>, 828 <0x8400000 0x1000000>, 829 <0x9400000 0x1000000>, 830 <0xa400000 0x220000>, 831 <0x800a000 0x3000>; 832 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 833 interrupt-names = "periph_irq"; 834 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 835 qcom,ee = <0>; 836 qcom,channel = <0>; 837 #address-cells = <2>; 838 #size-cells = <0>; 839 interrupt-controller; 840 #interrupt-cells = <4>; 841 cell-index = <0>; 842 }; 843 844 tsens0: thermal@10ab000 { 845 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 846 reg = <0x10ab000 0x1000>, /* TM */ 847 <0x10aa000 0x1000>; /* SROT */ 848 849 #qcom,sensors = <14>; 850 #thermal-sensor-cells = <1>; 851 }; 852 853 tsens1: thermal@10ae000 { 854 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 855 reg = <0x10ae000 0x1000>, /* TM */ 856 <0x10ad000 0x1000>; /* SROT */ 857 858 #qcom,sensors = <8>; 859 #thermal-sensor-cells = <1>; 860 }; 861 862 anoc1_smmu: iommu@1680000 { 863 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 864 reg = <0x01680000 0x10000>; 865 #iommu-cells = <1>; 866 867 #global-interrupts = <0>; 868 interrupts = 869 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 870 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 871 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 872 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 873 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 874 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 875 }; 876 877 pcie0: pci@1c00000 { 878 compatible = "qcom,pcie-msm8996"; 879 reg = <0x01c00000 0x2000>, 880 <0x1b000000 0xf1d>, 881 <0x1b000f20 0xa8>, 882 <0x1b100000 0x100000>; 883 reg-names = "parf", "dbi", "elbi", "config"; 884 device_type = "pci"; 885 linux,pci-domain = <0>; 886 bus-range = <0x00 0xff>; 887 #address-cells = <3>; 888 #size-cells = <2>; 889 num-lanes = <1>; 890 phys = <&pciephy>; 891 phy-names = "pciephy"; 892 893 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>, 894 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 895 896 #interrupt-cells = <1>; 897 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 898 interrupt-names = "msi"; 899 interrupt-map-mask = <0 0 0 0x7>; 900 interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>, 901 <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>, 902 <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>, 903 <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>; 904 905 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 906 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 907 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 908 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 909 <&gcc GCC_PCIE_0_AUX_CLK>; 910 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux"; 911 912 power-domains = <&gcc PCIE_0_GDSC>; 913 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 914 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 915 }; 916 917 phy@1c06000 { 918 compatible = "qcom,msm8998-qmp-pcie-phy"; 919 reg = <0x01c06000 0x18c>; 920 #address-cells = <1>; 921 #size-cells = <1>; 922 ranges; 923 924 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 925 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 926 <&gcc GCC_PCIE_CLKREF_CLK>; 927 clock-names = "aux", "cfg_ahb", "ref"; 928 929 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 930 reset-names = "phy", "common"; 931 932 vdda-phy-supply = <&vreg_l1a_0p875>; 933 vdda-pll-supply = <&vreg_l2a_1p2>; 934 935 pciephy: lane@1c06800 { 936 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; 937 #phy-cells = <0>; 938 939 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 940 clock-names = "pipe0"; 941 clock-output-names = "pcie_0_pipe_clk_src"; 942 #clock-cells = <0>; 943 }; 944 }; 945 946 tcsr_mutex_regs: syscon@1f40000 { 947 compatible = "syscon"; 948 reg = <0x1f40000 0x20000>; 949 }; 950 951 apcs_glb: mailbox@9820000 { 952 compatible = "qcom,msm8998-apcs-hmss-global"; 953 reg = <0x17911000 0x1000>; 954 955 #mbox-cells = <1>; 956 }; 957 958 usb3: usb@a8f8800 { 959 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 960 reg = <0x0a8f8800 0x400>; 961 status = "disabled"; 962 #address-cells = <1>; 963 #size-cells = <1>; 964 ranges; 965 966 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 967 <&gcc GCC_USB30_MASTER_CLK>, 968 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 969 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 970 <&gcc GCC_USB30_SLEEP_CLK>; 971 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 972 "sleep"; 973 974 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 975 <&gcc GCC_USB30_MASTER_CLK>; 976 assigned-clock-rates = <19200000>, <120000000>; 977 978 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 980 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 981 982 power-domains = <&gcc USB_30_GDSC>; 983 984 resets = <&gcc GCC_USB_30_BCR>; 985 986 usb3_dwc3: dwc3@a800000 { 987 compatible = "snps,dwc3"; 988 reg = <0x0a800000 0xcd00>; 989 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 990 snps,dis_u2_susphy_quirk; 991 snps,dis_enblslpm_quirk; 992 phys = <&qusb2phy>, <&usb1_ssphy>; 993 phy-names = "usb2-phy", "usb3-phy"; 994 snps,has-lpm-erratum; 995 snps,hird-threshold = /bits/ 8 <0x10>; 996 }; 997 }; 998 999 usb3phy: phy@c010000 { 1000 compatible = "qcom,msm8998-qmp-usb3-phy"; 1001 reg = <0x0c010000 0x18c>; 1002 status = "disabled"; 1003 #clock-cells = <1>; 1004 #address-cells = <1>; 1005 #size-cells = <1>; 1006 ranges; 1007 1008 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1009 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1010 <&gcc GCC_USB3_CLKREF_CLK>; 1011 clock-names = "aux", "cfg_ahb", "ref"; 1012 1013 resets = <&gcc GCC_USB3_PHY_BCR>, 1014 <&gcc GCC_USB3PHY_PHY_BCR>; 1015 reset-names = "phy", "common"; 1016 1017 usb1_ssphy: lane@c010200 { 1018 reg = <0xc010200 0x128>, 1019 <0xc010400 0x200>, 1020 <0xc010c00 0x20c>, 1021 <0xc010600 0x128>, 1022 <0xc010800 0x200>; 1023 #phy-cells = <0>; 1024 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 1025 clock-names = "pipe0"; 1026 clock-output-names = "usb3_phy_pipe_clk_src"; 1027 }; 1028 }; 1029 1030 qusb2phy: phy@c012000 { 1031 compatible = "qcom,msm8998-qusb2-phy"; 1032 reg = <0x0c012000 0x2a8>; 1033 status = "disabled"; 1034 #phy-cells = <0>; 1035 1036 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1037 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1038 clock-names = "cfg_ahb", "ref"; 1039 1040 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1041 1042 nvmem-cells = <&qusb2_hstx_trim>; 1043 }; 1044 1045 sdhc2: sdhci@c0a4900 { 1046 compatible = "qcom,sdhci-msm-v4"; 1047 reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>; 1048 reg-names = "hc_mem", "core_mem"; 1049 1050 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1052 interrupt-names = "hc_irq", "pwr_irq"; 1053 1054 clock-names = "iface", "core", "xo"; 1055 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1056 <&gcc GCC_SDCC2_APPS_CLK>, 1057 <&xo>; 1058 bus-width = <4>; 1059 status = "disabled"; 1060 }; 1061 1062 blsp1_i2c1: i2c@c175000 { 1063 compatible = "qcom,i2c-qup-v2.2.1"; 1064 reg = <0x0c175000 0x600>; 1065 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1066 1067 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1068 <&gcc GCC_BLSP1_AHB_CLK>; 1069 clock-names = "core", "iface"; 1070 clock-frequency = <400000>; 1071 1072 status = "disabled"; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 }; 1076 1077 blsp1_i2c2: i2c@c176000 { 1078 compatible = "qcom,i2c-qup-v2.2.1"; 1079 reg = <0x0c176000 0x600>; 1080 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1081 1082 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1083 <&gcc GCC_BLSP1_AHB_CLK>; 1084 clock-names = "core", "iface"; 1085 clock-frequency = <400000>; 1086 1087 status = "disabled"; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 }; 1091 1092 blsp1_i2c3: i2c@c177000 { 1093 compatible = "qcom,i2c-qup-v2.2.1"; 1094 reg = <0x0c177000 0x600>; 1095 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1096 1097 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1098 <&gcc GCC_BLSP1_AHB_CLK>; 1099 clock-names = "core", "iface"; 1100 clock-frequency = <400000>; 1101 1102 status = "disabled"; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 }; 1106 1107 blsp1_i2c4: i2c@c178000 { 1108 compatible = "qcom,i2c-qup-v2.2.1"; 1109 reg = <0x0c178000 0x600>; 1110 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1111 1112 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1113 <&gcc GCC_BLSP1_AHB_CLK>; 1114 clock-names = "core", "iface"; 1115 clock-frequency = <400000>; 1116 1117 status = "disabled"; 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 }; 1121 1122 blsp1_i2c5: i2c@c179000 { 1123 compatible = "qcom,i2c-qup-v2.2.1"; 1124 reg = <0x0c179000 0x600>; 1125 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1126 1127 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1128 <&gcc GCC_BLSP1_AHB_CLK>; 1129 clock-names = "core", "iface"; 1130 clock-frequency = <400000>; 1131 1132 status = "disabled"; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 }; 1136 1137 blsp1_i2c6: i2c@c17a000 { 1138 compatible = "qcom,i2c-qup-v2.2.1"; 1139 reg = <0x0c17a000 0x600>; 1140 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1141 1142 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1143 <&gcc GCC_BLSP1_AHB_CLK>; 1144 clock-names = "core", "iface"; 1145 clock-frequency = <400000>; 1146 1147 status = "disabled"; 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 }; 1151 1152 blsp2_i2c0: i2c@c1b5000 { 1153 compatible = "qcom,i2c-qup-v2.2.1"; 1154 reg = <0x0c1b5000 0x600>; 1155 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1156 1157 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1158 <&gcc GCC_BLSP2_AHB_CLK>; 1159 clock-names = "core", "iface"; 1160 clock-frequency = <400000>; 1161 1162 status = "disabled"; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 }; 1166 1167 blsp2_i2c1: i2c@c1b6000 { 1168 compatible = "qcom,i2c-qup-v2.2.1"; 1169 reg = <0x0c1b6000 0x600>; 1170 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1171 1172 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1173 <&gcc GCC_BLSP2_AHB_CLK>; 1174 clock-names = "core", "iface"; 1175 clock-frequency = <400000>; 1176 1177 status = "disabled"; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 }; 1181 1182 blsp2_i2c2: i2c@c1b7000 { 1183 compatible = "qcom,i2c-qup-v2.2.1"; 1184 reg = <0x0c1b7000 0x600>; 1185 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1186 1187 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1188 <&gcc GCC_BLSP2_AHB_CLK>; 1189 clock-names = "core", "iface"; 1190 clock-frequency = <400000>; 1191 1192 status = "disabled"; 1193 #address-cells = <1>; 1194 #size-cells = <0>; 1195 }; 1196 1197 blsp2_i2c3: i2c@c1b8000 { 1198 compatible = "qcom,i2c-qup-v2.2.1"; 1199 reg = <0x0c1b8000 0x600>; 1200 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1201 1202 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1203 <&gcc GCC_BLSP2_AHB_CLK>; 1204 clock-names = "core", "iface"; 1205 clock-frequency = <400000>; 1206 1207 status = "disabled"; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 }; 1211 1212 blsp2_i2c4: i2c@c1b9000 { 1213 compatible = "qcom,i2c-qup-v2.2.1"; 1214 reg = <0x0c1b9000 0x600>; 1215 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1216 1217 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 1218 <&gcc GCC_BLSP2_AHB_CLK>; 1219 clock-names = "core", "iface"; 1220 clock-frequency = <400000>; 1221 1222 status = "disabled"; 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 }; 1226 1227 blsp2_i2c5: i2c@c1ba000 { 1228 compatible = "qcom,i2c-qup-v2.2.1"; 1229 reg = <0x0c1ba000 0x600>; 1230 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1231 1232 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 1233 <&gcc GCC_BLSP2_AHB_CLK>; 1234 clock-names = "core", "iface"; 1235 clock-frequency = <400000>; 1236 1237 status = "disabled"; 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 }; 1241 1242 blsp2_uart1: serial@c1b0000 { 1243 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1244 reg = <0xc1b0000 0x1000>; 1245 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 1247 <&gcc GCC_BLSP2_AHB_CLK>; 1248 clock-names = "core", "iface"; 1249 status = "disabled"; 1250 }; 1251 1252 timer@17920000 { 1253 #address-cells = <1>; 1254 #size-cells = <1>; 1255 ranges; 1256 compatible = "arm,armv7-timer-mem"; 1257 reg = <0x17920000 0x1000>; 1258 1259 frame@17921000 { 1260 frame-number = <0>; 1261 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1263 reg = <0x17921000 0x1000>, 1264 <0x17922000 0x1000>; 1265 }; 1266 1267 frame@17923000 { 1268 frame-number = <1>; 1269 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1270 reg = <0x17923000 0x1000>; 1271 status = "disabled"; 1272 }; 1273 1274 frame@17924000 { 1275 frame-number = <2>; 1276 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1277 reg = <0x17924000 0x1000>; 1278 status = "disabled"; 1279 }; 1280 1281 frame@17925000 { 1282 frame-number = <3>; 1283 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1284 reg = <0x17925000 0x1000>; 1285 status = "disabled"; 1286 }; 1287 1288 frame@17926000 { 1289 frame-number = <4>; 1290 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1291 reg = <0x17926000 0x1000>; 1292 status = "disabled"; 1293 }; 1294 1295 frame@17927000 { 1296 frame-number = <5>; 1297 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1298 reg = <0x17927000 0x1000>; 1299 status = "disabled"; 1300 }; 1301 1302 frame@17928000 { 1303 frame-number = <6>; 1304 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1305 reg = <0x17928000 0x1000>; 1306 status = "disabled"; 1307 }; 1308 }; 1309 1310 intc: interrupt-controller@17a00000 { 1311 compatible = "arm,gic-v3"; 1312 reg = <0x17a00000 0x10000>, /* GICD */ 1313 <0x17b00000 0x100000>; /* GICR * 8 */ 1314 #interrupt-cells = <3>; 1315 #address-cells = <1>; 1316 #size-cells = <1>; 1317 ranges; 1318 interrupt-controller; 1319 #redistributor-regions = <1>; 1320 redistributor-stride = <0x0 0x20000>; 1321 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1322 }; 1323 1324 ufshc: ufshc@1da4000 { 1325 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1326 reg = <0x01da4000 0x2500>; 1327 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1328 phys = <&ufsphy_lanes>; 1329 phy-names = "ufsphy"; 1330 lanes-per-direction = <2>; 1331 power-domains = <&gcc UFS_GDSC>; 1332 #reset-cells = <1>; 1333 1334 clock-names = 1335 "core_clk", 1336 "bus_aggr_clk", 1337 "iface_clk", 1338 "core_clk_unipro", 1339 "ref_clk", 1340 "tx_lane0_sync_clk", 1341 "rx_lane0_sync_clk", 1342 "rx_lane1_sync_clk"; 1343 clocks = 1344 <&gcc GCC_UFS_AXI_CLK>, 1345 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1346 <&gcc GCC_UFS_AHB_CLK>, 1347 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1348 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1349 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1350 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1351 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1352 freq-table-hz = 1353 <50000000 200000000>, 1354 <0 0>, 1355 <0 0>, 1356 <37500000 150000000>, 1357 <0 0>, 1358 <0 0>, 1359 <0 0>, 1360 <0 0>; 1361 1362 resets = <&gcc GCC_UFS_BCR>; 1363 reset-names = "rst"; 1364 }; 1365 1366 ufsphy: phy@1da7000 { 1367 compatible = "qcom,msm8998-qmp-ufs-phy"; 1368 reg = <0x01da7000 0x18c>; 1369 #address-cells = <1>; 1370 #size-cells = <1>; 1371 ranges; 1372 1373 clock-names = 1374 "ref", 1375 "ref_aux"; 1376 clocks = 1377 <&gcc GCC_UFS_CLKREF_CLK>, 1378 <&gcc GCC_UFS_PHY_AUX_CLK>; 1379 1380 reset-names = "ufsphy"; 1381 resets = <&ufshc 0>; 1382 1383 ufsphy_lanes: lanes@1da7400 { 1384 reg = <0x01da7400 0x128>, 1385 <0x01da7600 0x1fc>, 1386 <0x01da7c00 0x1dc>, 1387 <0x01da7800 0x128>, 1388 <0x01da7a00 0x1fc>; 1389 #phy-cells = <0>; 1390 }; 1391 }; 1392 }; 1393}; 1394 1395#include "msm8998-pins.dtsi" 1396