1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8996.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/interconnect/qcom,msm8996.h> 11#include <dt-bindings/interconnect/qcom,msm8996-cbf.h> 12#include <dt-bindings/firmware/qcom,scm.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,apr.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <19200000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32764>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "qcom,kryo"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 cpu-idle-states = <&CPU_SLEEP_0>; 52 capacity-dmips-mhz = <1024>; 53 clocks = <&kryocc 0>; 54 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 55 operating-points-v2 = <&cluster0_opp>; 56 #cooling-cells = <2>; 57 next-level-cache = <&L2_0>; 58 L2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 }; 63 }; 64 65 CPU1: cpu@1 { 66 device_type = "cpu"; 67 compatible = "qcom,kryo"; 68 reg = <0x0 0x1>; 69 enable-method = "psci"; 70 cpu-idle-states = <&CPU_SLEEP_0>; 71 capacity-dmips-mhz = <1024>; 72 clocks = <&kryocc 0>; 73 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 74 operating-points-v2 = <&cluster0_opp>; 75 #cooling-cells = <2>; 76 next-level-cache = <&L2_0>; 77 }; 78 79 CPU2: cpu@100 { 80 device_type = "cpu"; 81 compatible = "qcom,kryo"; 82 reg = <0x0 0x100>; 83 enable-method = "psci"; 84 cpu-idle-states = <&CPU_SLEEP_0>; 85 capacity-dmips-mhz = <1024>; 86 clocks = <&kryocc 1>; 87 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 88 operating-points-v2 = <&cluster1_opp>; 89 #cooling-cells = <2>; 90 next-level-cache = <&L2_1>; 91 L2_1: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 cache-unified; 95 }; 96 }; 97 98 CPU3: cpu@101 { 99 device_type = "cpu"; 100 compatible = "qcom,kryo"; 101 reg = <0x0 0x101>; 102 enable-method = "psci"; 103 cpu-idle-states = <&CPU_SLEEP_0>; 104 capacity-dmips-mhz = <1024>; 105 clocks = <&kryocc 1>; 106 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 107 operating-points-v2 = <&cluster1_opp>; 108 #cooling-cells = <2>; 109 next-level-cache = <&L2_1>; 110 }; 111 112 cpu-map { 113 cluster0 { 114 core0 { 115 cpu = <&CPU0>; 116 }; 117 118 core1 { 119 cpu = <&CPU1>; 120 }; 121 }; 122 123 cluster1 { 124 core0 { 125 cpu = <&CPU2>; 126 }; 127 128 core1 { 129 cpu = <&CPU3>; 130 }; 131 }; 132 }; 133 134 idle-states { 135 entry-method = "psci"; 136 137 CPU_SLEEP_0: cpu-sleep-0 { 138 compatible = "arm,idle-state"; 139 idle-state-name = "standalone-power-collapse"; 140 arm,psci-suspend-param = <0x00000004>; 141 entry-latency-us = <130>; 142 exit-latency-us = <80>; 143 min-residency-us = <300>; 144 }; 145 }; 146 }; 147 148 cluster0_opp: opp-table-cluster0 { 149 compatible = "operating-points-v2-kryo-cpu"; 150 nvmem-cells = <&speedbin_efuse>; 151 opp-shared; 152 153 /* Nominal fmax for now */ 154 opp-307200000 { 155 opp-hz = /bits/ 64 <307200000>; 156 opp-supported-hw = <0xf>; 157 clock-latency-ns = <200000>; 158 opp-peak-kBps = <307200>; 159 }; 160 opp-422400000 { 161 opp-hz = /bits/ 64 <422400000>; 162 opp-supported-hw = <0xf>; 163 clock-latency-ns = <200000>; 164 opp-peak-kBps = <307200>; 165 }; 166 opp-480000000 { 167 opp-hz = /bits/ 64 <480000000>; 168 opp-supported-hw = <0xf>; 169 clock-latency-ns = <200000>; 170 opp-peak-kBps = <307200>; 171 }; 172 opp-556800000 { 173 opp-hz = /bits/ 64 <556800000>; 174 opp-supported-hw = <0xf>; 175 clock-latency-ns = <200000>; 176 opp-peak-kBps = <307200>; 177 }; 178 opp-652800000 { 179 opp-hz = /bits/ 64 <652800000>; 180 opp-supported-hw = <0xf>; 181 clock-latency-ns = <200000>; 182 opp-peak-kBps = <384000>; 183 }; 184 opp-729600000 { 185 opp-hz = /bits/ 64 <729600000>; 186 opp-supported-hw = <0xf>; 187 clock-latency-ns = <200000>; 188 opp-peak-kBps = <460800>; 189 }; 190 opp-844800000 { 191 opp-hz = /bits/ 64 <844800000>; 192 opp-supported-hw = <0xf>; 193 clock-latency-ns = <200000>; 194 opp-peak-kBps = <537600>; 195 }; 196 opp-960000000 { 197 opp-hz = /bits/ 64 <960000000>; 198 opp-supported-hw = <0xf>; 199 clock-latency-ns = <200000>; 200 opp-peak-kBps = <672000>; 201 }; 202 opp-1036800000 { 203 opp-hz = /bits/ 64 <1036800000>; 204 opp-supported-hw = <0xf>; 205 clock-latency-ns = <200000>; 206 opp-peak-kBps = <672000>; 207 }; 208 opp-1113600000 { 209 opp-hz = /bits/ 64 <1113600000>; 210 opp-supported-hw = <0xf>; 211 clock-latency-ns = <200000>; 212 opp-peak-kBps = <825600>; 213 }; 214 opp-1190400000 { 215 opp-hz = /bits/ 64 <1190400000>; 216 opp-supported-hw = <0xf>; 217 clock-latency-ns = <200000>; 218 opp-peak-kBps = <825600>; 219 }; 220 opp-1228800000 { 221 opp-hz = /bits/ 64 <1228800000>; 222 opp-supported-hw = <0xf>; 223 clock-latency-ns = <200000>; 224 opp-peak-kBps = <902400>; 225 }; 226 opp-1324800000 { 227 opp-hz = /bits/ 64 <1324800000>; 228 opp-supported-hw = <0xd>; 229 clock-latency-ns = <200000>; 230 opp-peak-kBps = <1056000>; 231 }; 232 opp-1363200000 { 233 opp-hz = /bits/ 64 <1363200000>; 234 opp-supported-hw = <0x2>; 235 clock-latency-ns = <200000>; 236 opp-peak-kBps = <1132800>; 237 }; 238 opp-1401600000 { 239 opp-hz = /bits/ 64 <1401600000>; 240 opp-supported-hw = <0xd>; 241 clock-latency-ns = <200000>; 242 opp-peak-kBps = <1132800>; 243 }; 244 opp-1478400000 { 245 opp-hz = /bits/ 64 <1478400000>; 246 opp-supported-hw = <0x9>; 247 clock-latency-ns = <200000>; 248 opp-peak-kBps = <1190400>; 249 }; 250 opp-1497600000 { 251 opp-hz = /bits/ 64 <1497600000>; 252 opp-supported-hw = <0x04>; 253 clock-latency-ns = <200000>; 254 opp-peak-kBps = <1305600>; 255 }; 256 opp-1593600000 { 257 opp-hz = /bits/ 64 <1593600000>; 258 opp-supported-hw = <0x9>; 259 clock-latency-ns = <200000>; 260 opp-peak-kBps = <1382400>; 261 }; 262 }; 263 264 cluster1_opp: opp-table-cluster1 { 265 compatible = "operating-points-v2-kryo-cpu"; 266 nvmem-cells = <&speedbin_efuse>; 267 opp-shared; 268 269 /* Nominal fmax for now */ 270 opp-307200000 { 271 opp-hz = /bits/ 64 <307200000>; 272 opp-supported-hw = <0xf>; 273 clock-latency-ns = <200000>; 274 opp-peak-kBps = <307200>; 275 }; 276 opp-403200000 { 277 opp-hz = /bits/ 64 <403200000>; 278 opp-supported-hw = <0xf>; 279 clock-latency-ns = <200000>; 280 opp-peak-kBps = <307200>; 281 }; 282 opp-480000000 { 283 opp-hz = /bits/ 64 <480000000>; 284 opp-supported-hw = <0xf>; 285 clock-latency-ns = <200000>; 286 opp-peak-kBps = <307200>; 287 }; 288 opp-556800000 { 289 opp-hz = /bits/ 64 <556800000>; 290 opp-supported-hw = <0xf>; 291 clock-latency-ns = <200000>; 292 opp-peak-kBps = <307200>; 293 }; 294 opp-652800000 { 295 opp-hz = /bits/ 64 <652800000>; 296 opp-supported-hw = <0xf>; 297 clock-latency-ns = <200000>; 298 opp-peak-kBps = <307200>; 299 }; 300 opp-729600000 { 301 opp-hz = /bits/ 64 <729600000>; 302 opp-supported-hw = <0xf>; 303 clock-latency-ns = <200000>; 304 opp-peak-kBps = <307200>; 305 }; 306 opp-806400000 { 307 opp-hz = /bits/ 64 <806400000>; 308 opp-supported-hw = <0xf>; 309 clock-latency-ns = <200000>; 310 opp-peak-kBps = <384000>; 311 }; 312 opp-883200000 { 313 opp-hz = /bits/ 64 <883200000>; 314 opp-supported-hw = <0xf>; 315 clock-latency-ns = <200000>; 316 opp-peak-kBps = <460800>; 317 }; 318 opp-940800000 { 319 opp-hz = /bits/ 64 <940800000>; 320 opp-supported-hw = <0xf>; 321 clock-latency-ns = <200000>; 322 opp-peak-kBps = <537600>; 323 }; 324 opp-1036800000 { 325 opp-hz = /bits/ 64 <1036800000>; 326 opp-supported-hw = <0xf>; 327 clock-latency-ns = <200000>; 328 opp-peak-kBps = <595200>; 329 }; 330 opp-1113600000 { 331 opp-hz = /bits/ 64 <1113600000>; 332 opp-supported-hw = <0xf>; 333 clock-latency-ns = <200000>; 334 opp-peak-kBps = <672000>; 335 }; 336 opp-1190400000 { 337 opp-hz = /bits/ 64 <1190400000>; 338 opp-supported-hw = <0xf>; 339 clock-latency-ns = <200000>; 340 opp-peak-kBps = <672000>; 341 }; 342 opp-1248000000 { 343 opp-hz = /bits/ 64 <1248000000>; 344 opp-supported-hw = <0xf>; 345 clock-latency-ns = <200000>; 346 opp-peak-kBps = <748800>; 347 }; 348 opp-1324800000 { 349 opp-hz = /bits/ 64 <1324800000>; 350 opp-supported-hw = <0xf>; 351 clock-latency-ns = <200000>; 352 opp-peak-kBps = <825600>; 353 }; 354 opp-1401600000 { 355 opp-hz = /bits/ 64 <1401600000>; 356 opp-supported-hw = <0xf>; 357 clock-latency-ns = <200000>; 358 opp-peak-kBps = <902400>; 359 }; 360 opp-1478400000 { 361 opp-hz = /bits/ 64 <1478400000>; 362 opp-supported-hw = <0xf>; 363 clock-latency-ns = <200000>; 364 opp-peak-kBps = <979200>; 365 }; 366 opp-1555200000 { 367 opp-hz = /bits/ 64 <1555200000>; 368 opp-supported-hw = <0xf>; 369 clock-latency-ns = <200000>; 370 opp-peak-kBps = <1056000>; 371 }; 372 opp-1632000000 { 373 opp-hz = /bits/ 64 <1632000000>; 374 opp-supported-hw = <0xf>; 375 clock-latency-ns = <200000>; 376 opp-peak-kBps = <1190400>; 377 }; 378 opp-1708800000 { 379 opp-hz = /bits/ 64 <1708800000>; 380 opp-supported-hw = <0xf>; 381 clock-latency-ns = <200000>; 382 opp-peak-kBps = <1228800>; 383 }; 384 opp-1785600000 { 385 opp-hz = /bits/ 64 <1785600000>; 386 opp-supported-hw = <0xf>; 387 clock-latency-ns = <200000>; 388 opp-peak-kBps = <1305600>; 389 }; 390 opp-1804800000 { 391 opp-hz = /bits/ 64 <1804800000>; 392 opp-supported-hw = <0xe>; 393 clock-latency-ns = <200000>; 394 opp-peak-kBps = <1305600>; 395 }; 396 opp-1824000000 { 397 opp-hz = /bits/ 64 <1824000000>; 398 opp-supported-hw = <0x1>; 399 clock-latency-ns = <200000>; 400 opp-peak-kBps = <1382400>; 401 }; 402 opp-1900800000 { 403 opp-hz = /bits/ 64 <1900800000>; 404 opp-supported-hw = <0x4>; 405 clock-latency-ns = <200000>; 406 opp-peak-kBps = <1305600>; 407 }; 408 opp-1920000000 { 409 opp-hz = /bits/ 64 <1920000000>; 410 opp-supported-hw = <0x1>; 411 clock-latency-ns = <200000>; 412 opp-peak-kBps = <1459200>; 413 }; 414 opp-1996800000 { 415 opp-hz = /bits/ 64 <1996800000>; 416 opp-supported-hw = <0x1>; 417 clock-latency-ns = <200000>; 418 opp-peak-kBps = <1593600>; 419 }; 420 opp-2073600000 { 421 opp-hz = /bits/ 64 <2073600000>; 422 opp-supported-hw = <0x1>; 423 clock-latency-ns = <200000>; 424 opp-peak-kBps = <1593600>; 425 }; 426 opp-2150400000 { 427 opp-hz = /bits/ 64 <2150400000>; 428 opp-supported-hw = <0x1>; 429 clock-latency-ns = <200000>; 430 opp-peak-kBps = <1593600>; 431 }; 432 }; 433 434 firmware { 435 scm { 436 compatible = "qcom,scm-msm8996", "qcom,scm"; 437 qcom,dload-mode = <&tcsr_2 0x13000>; 438 }; 439 }; 440 441 memory@80000000 { 442 device_type = "memory"; 443 /* We expect the bootloader to fill in the reg */ 444 reg = <0x0 0x80000000 0x0 0x0>; 445 }; 446 447 etm { 448 compatible = "qcom,coresight-remote-etm"; 449 450 out-ports { 451 port { 452 modem_etm_out_funnel_in2: endpoint { 453 remote-endpoint = 454 <&funnel_in2_in_modem_etm>; 455 }; 456 }; 457 }; 458 }; 459 460 psci { 461 compatible = "arm,psci-1.0"; 462 method = "smc"; 463 }; 464 465 rpm: remoteproc { 466 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc"; 467 468 glink-edge { 469 compatible = "qcom,glink-rpm"; 470 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 471 qcom,rpm-msg-ram = <&rpm_msg_ram>; 472 mboxes = <&apcs_glb 0>; 473 474 rpm_requests: rpm-requests { 475 compatible = "qcom,rpm-msm8996"; 476 qcom,glink-channels = "rpm_requests"; 477 478 rpmcc: clock-controller { 479 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 480 #clock-cells = <1>; 481 clocks = <&xo_board>; 482 clock-names = "xo"; 483 }; 484 485 rpmpd: power-controller { 486 compatible = "qcom,msm8996-rpmpd"; 487 #power-domain-cells = <1>; 488 operating-points-v2 = <&rpmpd_opp_table>; 489 490 rpmpd_opp_table: opp-table { 491 compatible = "operating-points-v2"; 492 493 rpmpd_opp1: opp1 { 494 opp-level = <1>; 495 }; 496 497 rpmpd_opp2: opp2 { 498 opp-level = <2>; 499 }; 500 501 rpmpd_opp3: opp3 { 502 opp-level = <3>; 503 }; 504 505 rpmpd_opp4: opp4 { 506 opp-level = <4>; 507 }; 508 509 rpmpd_opp5: opp5 { 510 opp-level = <5>; 511 }; 512 513 rpmpd_opp6: opp6 { 514 opp-level = <6>; 515 }; 516 }; 517 }; 518 }; 519 }; 520 }; 521 522 reserved-memory { 523 #address-cells = <2>; 524 #size-cells = <2>; 525 ranges; 526 527 hyp_mem: memory@85800000 { 528 reg = <0x0 0x85800000 0x0 0x600000>; 529 no-map; 530 }; 531 532 xbl_mem: memory@85e00000 { 533 reg = <0x0 0x85e00000 0x0 0x200000>; 534 no-map; 535 }; 536 537 smem_mem: smem-mem@86000000 { 538 reg = <0x0 0x86000000 0x0 0x200000>; 539 no-map; 540 }; 541 542 tz_mem: memory@86200000 { 543 reg = <0x0 0x86200000 0x0 0x2600000>; 544 no-map; 545 }; 546 547 rmtfs_mem: rmtfs { 548 compatible = "qcom,rmtfs-mem"; 549 550 size = <0x0 0x200000>; 551 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 552 no-map; 553 554 qcom,client-id = <1>; 555 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 556 }; 557 558 mpss_mem: mpss@88800000 { 559 reg = <0x0 0x88800000 0x0 0x6200000>; 560 no-map; 561 }; 562 563 adsp_mem: adsp@8ea00000 { 564 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 565 no-map; 566 }; 567 568 slpi_mem: slpi@90500000 { 569 reg = <0x0 0x90500000 0x0 0xa00000>; 570 no-map; 571 }; 572 573 gpu_mem: gpu@90f00000 { 574 compatible = "shared-dma-pool"; 575 reg = <0x0 0x90f00000 0x0 0x100000>; 576 no-map; 577 }; 578 579 venus_mem: venus@91000000 { 580 reg = <0x0 0x91000000 0x0 0x500000>; 581 no-map; 582 }; 583 584 mba_mem: mba@91500000 { 585 reg = <0x0 0x91500000 0x0 0x200000>; 586 no-map; 587 }; 588 589 mdata_mem: mpss-metadata { 590 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 591 size = <0x0 0x4000>; 592 no-map; 593 }; 594 }; 595 596 smem { 597 compatible = "qcom,smem"; 598 memory-region = <&smem_mem>; 599 hwlocks = <&tcsr_mutex 3>; 600 }; 601 602 smp2p-adsp { 603 compatible = "qcom,smp2p"; 604 qcom,smem = <443>, <429>; 605 606 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 607 608 mboxes = <&apcs_glb 10>; 609 610 qcom,local-pid = <0>; 611 qcom,remote-pid = <2>; 612 613 adsp_smp2p_out: master-kernel { 614 qcom,entry-name = "master-kernel"; 615 #qcom,smem-state-cells = <1>; 616 }; 617 618 adsp_smp2p_in: slave-kernel { 619 qcom,entry-name = "slave-kernel"; 620 621 interrupt-controller; 622 #interrupt-cells = <2>; 623 }; 624 }; 625 626 smp2p-mpss { 627 compatible = "qcom,smp2p"; 628 qcom,smem = <435>, <428>; 629 630 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 631 632 mboxes = <&apcs_glb 14>; 633 634 qcom,local-pid = <0>; 635 qcom,remote-pid = <1>; 636 637 mpss_smp2p_out: master-kernel { 638 qcom,entry-name = "master-kernel"; 639 #qcom,smem-state-cells = <1>; 640 }; 641 642 mpss_smp2p_in: slave-kernel { 643 qcom,entry-name = "slave-kernel"; 644 645 interrupt-controller; 646 #interrupt-cells = <2>; 647 }; 648 }; 649 650 smp2p-slpi { 651 compatible = "qcom,smp2p"; 652 qcom,smem = <481>, <430>; 653 654 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 655 656 mboxes = <&apcs_glb 26>; 657 658 qcom,local-pid = <0>; 659 qcom,remote-pid = <3>; 660 661 slpi_smp2p_out: master-kernel { 662 qcom,entry-name = "master-kernel"; 663 #qcom,smem-state-cells = <1>; 664 }; 665 666 slpi_smp2p_in: slave-kernel { 667 qcom,entry-name = "slave-kernel"; 668 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 }; 672 }; 673 674 soc: soc@0 { 675 #address-cells = <1>; 676 #size-cells = <1>; 677 ranges = <0 0 0 0xffffffff>; 678 compatible = "simple-bus"; 679 680 pcie_phy: phy-wrapper@34000 { 681 compatible = "qcom,msm8996-qmp-pcie-phy"; 682 reg = <0x00034000 0x488>; 683 #address-cells = <1>; 684 #size-cells = <1>; 685 ranges = <0x0 0x00034000 0x4000>; 686 687 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 688 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 689 <&gcc GCC_PCIE_CLKREF_CLK>; 690 clock-names = "aux", "cfg_ahb", "ref"; 691 692 resets = <&gcc GCC_PCIE_PHY_BCR>, 693 <&gcc GCC_PCIE_PHY_COM_BCR>, 694 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 695 reset-names = "phy", "common", "cfg"; 696 697 status = "disabled"; 698 699 pciephy_0: phy@1000 { 700 reg = <0x1000 0x130>, 701 <0x1200 0x200>, 702 <0x1400 0x1dc>; 703 704 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 705 clock-names = "pipe0"; 706 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 707 reset-names = "lane0"; 708 709 #clock-cells = <0>; 710 clock-output-names = "pcie_0_pipe_clk_src"; 711 712 #phy-cells = <0>; 713 }; 714 715 pciephy_1: phy@2000 { 716 reg = <0x2000 0x130>, 717 <0x2200 0x200>, 718 <0x2400 0x1dc>; 719 720 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 721 clock-names = "pipe1"; 722 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 723 reset-names = "lane1"; 724 725 #clock-cells = <0>; 726 clock-output-names = "pcie_1_pipe_clk_src"; 727 728 #phy-cells = <0>; 729 }; 730 731 pciephy_2: phy@3000 { 732 reg = <0x3000 0x130>, 733 <0x3200 0x200>, 734 <0x3400 0x1dc>; 735 736 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 737 clock-names = "pipe2"; 738 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 739 reset-names = "lane2"; 740 741 #clock-cells = <0>; 742 clock-output-names = "pcie_2_pipe_clk_src"; 743 744 #phy-cells = <0>; 745 }; 746 }; 747 748 rpm_msg_ram: sram@68000 { 749 compatible = "qcom,rpm-msg-ram"; 750 reg = <0x00068000 0x6000>; 751 }; 752 753 qfprom@74000 { 754 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 755 reg = <0x00074000 0x8ff>; 756 #address-cells = <1>; 757 #size-cells = <1>; 758 759 qusb2p_hstx_trim: hstx-trim@24e { 760 reg = <0x24e 0x2>; 761 bits = <5 4>; 762 }; 763 764 qusb2s_hstx_trim: hstx-trim@24f { 765 reg = <0x24f 0x1>; 766 bits = <1 4>; 767 }; 768 769 speedbin_efuse: speedbin@133 { 770 reg = <0x133 0x1>; 771 bits = <5 3>; 772 }; 773 }; 774 775 rng: rng@83000 { 776 compatible = "qcom,prng-ee"; 777 reg = <0x00083000 0x1000>; 778 clocks = <&gcc GCC_PRNG_AHB_CLK>; 779 clock-names = "core"; 780 }; 781 782 gcc: clock-controller@300000 { 783 compatible = "qcom,gcc-msm8996"; 784 #clock-cells = <1>; 785 #reset-cells = <1>; 786 #power-domain-cells = <1>; 787 reg = <0x00300000 0x90000>; 788 789 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 790 <&rpmcc RPM_SMD_LN_BB_CLK>, 791 <&sleep_clk>, 792 <&pciephy_0>, 793 <&pciephy_1>, 794 <&pciephy_2>, 795 <&usb3phy>, 796 <&ufsphy 0>, 797 <&ufsphy 1>, 798 <&ufsphy 2>; 799 clock-names = "cxo", 800 "cxo2", 801 "sleep_clk", 802 "pcie_0_pipe_clk_src", 803 "pcie_1_pipe_clk_src", 804 "pcie_2_pipe_clk_src", 805 "usb3_phy_pipe_clk_src", 806 "ufs_rx_symbol_0_clk_src", 807 "ufs_rx_symbol_1_clk_src", 808 "ufs_tx_symbol_0_clk_src"; 809 }; 810 811 bimc: interconnect@408000 { 812 compatible = "qcom,msm8996-bimc"; 813 reg = <0x00408000 0x5a000>; 814 #interconnect-cells = <1>; 815 }; 816 817 tsens0: thermal-sensor@4a9000 { 818 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 819 reg = <0x004a9000 0x1000>, /* TM */ 820 <0x004a8000 0x1000>; /* SROT */ 821 #qcom,sensors = <13>; 822 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 824 interrupt-names = "uplow", "critical"; 825 #thermal-sensor-cells = <1>; 826 }; 827 828 tsens1: thermal-sensor@4ad000 { 829 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 830 reg = <0x004ad000 0x1000>, /* TM */ 831 <0x004ac000 0x1000>; /* SROT */ 832 #qcom,sensors = <8>; 833 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 835 interrupt-names = "uplow", "critical"; 836 #thermal-sensor-cells = <1>; 837 }; 838 839 cryptobam: dma-controller@644000 { 840 compatible = "qcom,bam-v1.7.0"; 841 reg = <0x00644000 0x24000>; 842 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&gcc GCC_CE1_CLK>; 844 clock-names = "bam_clk"; 845 #dma-cells = <1>; 846 qcom,ee = <0>; 847 qcom,controlled-remotely; 848 }; 849 850 crypto: crypto@67a000 { 851 compatible = "qcom,crypto-v5.4"; 852 reg = <0x0067a000 0x6000>; 853 clocks = <&gcc GCC_CE1_AHB_CLK>, 854 <&gcc GCC_CE1_AXI_CLK>, 855 <&gcc GCC_CE1_CLK>; 856 clock-names = "iface", "bus", "core"; 857 dmas = <&cryptobam 6>, <&cryptobam 7>; 858 dma-names = "rx", "tx"; 859 }; 860 861 cnoc: interconnect@500000 { 862 compatible = "qcom,msm8996-cnoc"; 863 reg = <0x00500000 0x1000>; 864 #interconnect-cells = <1>; 865 }; 866 867 snoc: interconnect@524000 { 868 compatible = "qcom,msm8996-snoc"; 869 reg = <0x00524000 0x1c000>; 870 #interconnect-cells = <1>; 871 }; 872 873 a0noc: interconnect@543000 { 874 compatible = "qcom,msm8996-a0noc"; 875 reg = <0x00543000 0x6000>; 876 #interconnect-cells = <1>; 877 clock-names = "aggre0_snoc_axi", 878 "aggre0_cnoc_ahb", 879 "aggre0_noc_mpu_cfg"; 880 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 881 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 882 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 883 power-domains = <&gcc AGGRE0_NOC_GDSC>; 884 }; 885 886 a1noc: interconnect@562000 { 887 compatible = "qcom,msm8996-a1noc"; 888 reg = <0x00562000 0x5000>; 889 #interconnect-cells = <1>; 890 }; 891 892 a2noc: interconnect@583000 { 893 compatible = "qcom,msm8996-a2noc"; 894 reg = <0x00583000 0x7000>; 895 #interconnect-cells = <1>; 896 clock-names = "aggre2_ufs_axi", "ufs_axi"; 897 clocks = <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 898 <&gcc GCC_UFS_AXI_CLK>; 899 }; 900 901 mnoc: interconnect@5a4000 { 902 compatible = "qcom,msm8996-mnoc"; 903 reg = <0x005a4000 0x1c000>; 904 #interconnect-cells = <1>; 905 clock-names = "iface"; 906 clocks = <&mmcc AHB_CLK_SRC>; 907 }; 908 909 pnoc: interconnect@5c0000 { 910 compatible = "qcom,msm8996-pnoc"; 911 reg = <0x005c0000 0x3000>; 912 #interconnect-cells = <1>; 913 }; 914 915 tcsr_mutex: hwlock@740000 { 916 compatible = "qcom,tcsr-mutex"; 917 reg = <0x00740000 0x20000>; 918 #hwlock-cells = <1>; 919 }; 920 921 tcsr_1: syscon@760000 { 922 compatible = "qcom,tcsr-msm8996", "syscon"; 923 reg = <0x00760000 0x20000>; 924 }; 925 926 tcsr_2: syscon@7a0000 { 927 compatible = "qcom,tcsr-msm8996", "syscon"; 928 reg = <0x007a0000 0x18000>; 929 }; 930 931 mmcc: clock-controller@8c0000 { 932 compatible = "qcom,mmcc-msm8996"; 933 #clock-cells = <1>; 934 #reset-cells = <1>; 935 #power-domain-cells = <1>; 936 reg = <0x008c0000 0x40000>; 937 clocks = <&xo_board>, 938 <&gcc GPLL0>, 939 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 940 <&mdss_dsi0_phy 1>, 941 <&mdss_dsi0_phy 0>, 942 <&mdss_dsi1_phy 1>, 943 <&mdss_dsi1_phy 0>, 944 <&mdss_hdmi_phy>; 945 clock-names = "xo", 946 "gpll0", 947 "gcc_mmss_noc_cfg_ahb_clk", 948 "dsi0pll", 949 "dsi0pllbyte", 950 "dsi1pll", 951 "dsi1pllbyte", 952 "hdmipll"; 953 assigned-clocks = <&mmcc MMPLL9_PLL>, 954 <&mmcc MMPLL1_PLL>, 955 <&mmcc MMPLL3_PLL>, 956 <&mmcc MMPLL4_PLL>, 957 <&mmcc MMPLL5_PLL>; 958 assigned-clock-rates = <624000000>, 959 <810000000>, 960 <980000000>, 961 <960000000>, 962 <825000000>; 963 }; 964 965 mdss: display-subsystem@900000 { 966 compatible = "qcom,mdss"; 967 968 reg = <0x00900000 0x1000>, 969 <0x009b0000 0x1040>, 970 <0x009b8000 0x1040>; 971 reg-names = "mdss_phys", 972 "vbif_phys", 973 "vbif_nrt_phys"; 974 975 power-domains = <&mmcc MDSS_GDSC>; 976 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 977 978 interrupt-controller; 979 #interrupt-cells = <1>; 980 981 clocks = <&mmcc MDSS_AHB_CLK>, 982 <&mmcc MDSS_MDP_CLK>; 983 clock-names = "iface", "core"; 984 985 #address-cells = <1>; 986 #size-cells = <1>; 987 ranges; 988 989 status = "disabled"; 990 991 mdp: display-controller@901000 { 992 compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; 993 reg = <0x00901000 0x90000>; 994 reg-names = "mdp_phys"; 995 996 interrupt-parent = <&mdss>; 997 interrupts = <0>; 998 999 clocks = <&mmcc MDSS_AHB_CLK>, 1000 <&mmcc MDSS_AXI_CLK>, 1001 <&mmcc MDSS_MDP_CLK>, 1002 <&mmcc SMMU_MDP_AXI_CLK>, 1003 <&mmcc MDSS_VSYNC_CLK>; 1004 clock-names = "iface", 1005 "bus", 1006 "core", 1007 "iommu", 1008 "vsync"; 1009 1010 iommus = <&mdp_smmu 0>; 1011 1012 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1013 <&mmcc MDSS_VSYNC_CLK>; 1014 assigned-clock-rates = <300000000>, 1015 <19200000>; 1016 1017 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 1018 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 1019 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 1020 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 1021 1022 ports { 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 1026 port@0 { 1027 reg = <0>; 1028 mdp5_intf3_out: endpoint { 1029 remote-endpoint = <&mdss_hdmi_in>; 1030 }; 1031 }; 1032 1033 port@1 { 1034 reg = <1>; 1035 mdp5_intf1_out: endpoint { 1036 remote-endpoint = <&mdss_dsi0_in>; 1037 }; 1038 }; 1039 1040 port@2 { 1041 reg = <2>; 1042 mdp5_intf2_out: endpoint { 1043 remote-endpoint = <&mdss_dsi1_in>; 1044 }; 1045 }; 1046 }; 1047 }; 1048 1049 mdss_dsi0: dsi@994000 { 1050 compatible = "qcom,msm8996-dsi-ctrl", 1051 "qcom,mdss-dsi-ctrl"; 1052 reg = <0x00994000 0x400>; 1053 reg-names = "dsi_ctrl"; 1054 1055 interrupt-parent = <&mdss>; 1056 interrupts = <4>; 1057 1058 clocks = <&mmcc MDSS_MDP_CLK>, 1059 <&mmcc MDSS_BYTE0_CLK>, 1060 <&mmcc MDSS_AHB_CLK>, 1061 <&mmcc MDSS_AXI_CLK>, 1062 <&mmcc MMSS_MISC_AHB_CLK>, 1063 <&mmcc MDSS_PCLK0_CLK>, 1064 <&mmcc MDSS_ESC0_CLK>; 1065 clock-names = "mdp_core", 1066 "byte", 1067 "iface", 1068 "bus", 1069 "core_mmss", 1070 "pixel", 1071 "core"; 1072 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1073 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1074 1075 phys = <&mdss_dsi0_phy>; 1076 status = "disabled"; 1077 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 1081 ports { 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 1085 port@0 { 1086 reg = <0>; 1087 mdss_dsi0_in: endpoint { 1088 remote-endpoint = <&mdp5_intf1_out>; 1089 }; 1090 }; 1091 1092 port@1 { 1093 reg = <1>; 1094 mdss_dsi0_out: endpoint { 1095 }; 1096 }; 1097 }; 1098 }; 1099 1100 mdss_dsi0_phy: phy@994400 { 1101 compatible = "qcom,dsi-phy-14nm"; 1102 reg = <0x00994400 0x100>, 1103 <0x00994500 0x300>, 1104 <0x00994800 0x188>; 1105 reg-names = "dsi_phy", 1106 "dsi_phy_lane", 1107 "dsi_pll"; 1108 1109 #clock-cells = <1>; 1110 #phy-cells = <0>; 1111 1112 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1113 clock-names = "iface", "ref"; 1114 status = "disabled"; 1115 }; 1116 1117 mdss_dsi1: dsi@996000 { 1118 compatible = "qcom,msm8996-dsi-ctrl", 1119 "qcom,mdss-dsi-ctrl"; 1120 reg = <0x00996000 0x400>; 1121 reg-names = "dsi_ctrl"; 1122 1123 interrupt-parent = <&mdss>; 1124 interrupts = <5>; 1125 1126 clocks = <&mmcc MDSS_MDP_CLK>, 1127 <&mmcc MDSS_BYTE1_CLK>, 1128 <&mmcc MDSS_AHB_CLK>, 1129 <&mmcc MDSS_AXI_CLK>, 1130 <&mmcc MMSS_MISC_AHB_CLK>, 1131 <&mmcc MDSS_PCLK1_CLK>, 1132 <&mmcc MDSS_ESC1_CLK>; 1133 clock-names = "mdp_core", 1134 "byte", 1135 "iface", 1136 "bus", 1137 "core_mmss", 1138 "pixel", 1139 "core"; 1140 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 1141 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 1142 1143 phys = <&mdss_dsi1_phy>; 1144 status = "disabled"; 1145 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 1149 ports { 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 1153 port@0 { 1154 reg = <0>; 1155 mdss_dsi1_in: endpoint { 1156 remote-endpoint = <&mdp5_intf2_out>; 1157 }; 1158 }; 1159 1160 port@1 { 1161 reg = <1>; 1162 mdss_dsi1_out: endpoint { 1163 }; 1164 }; 1165 }; 1166 }; 1167 1168 mdss_dsi1_phy: phy@996400 { 1169 compatible = "qcom,dsi-phy-14nm"; 1170 reg = <0x00996400 0x100>, 1171 <0x00996500 0x300>, 1172 <0x00996800 0x188>; 1173 reg-names = "dsi_phy", 1174 "dsi_phy_lane", 1175 "dsi_pll"; 1176 1177 #clock-cells = <1>; 1178 #phy-cells = <0>; 1179 1180 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1181 clock-names = "iface", "ref"; 1182 status = "disabled"; 1183 }; 1184 1185 mdss_hdmi: hdmi-tx@9a0000 { 1186 compatible = "qcom,hdmi-tx-8996"; 1187 reg = <0x009a0000 0x50c>, 1188 <0x00070000 0x6158>, 1189 <0x009e0000 0xfff>; 1190 reg-names = "core_physical", 1191 "qfprom_physical", 1192 "hdcp_physical"; 1193 1194 interrupt-parent = <&mdss>; 1195 interrupts = <8>; 1196 1197 clocks = <&mmcc MDSS_MDP_CLK>, 1198 <&mmcc MDSS_AHB_CLK>, 1199 <&mmcc MDSS_HDMI_CLK>, 1200 <&mmcc MDSS_HDMI_AHB_CLK>, 1201 <&mmcc MDSS_EXTPCLK_CLK>; 1202 clock-names = 1203 "mdp_core", 1204 "iface", 1205 "core", 1206 "alt_iface", 1207 "extp"; 1208 1209 phys = <&mdss_hdmi_phy>; 1210 #sound-dai-cells = <1>; 1211 1212 status = "disabled"; 1213 1214 ports { 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 1218 port@0 { 1219 reg = <0>; 1220 mdss_hdmi_in: endpoint { 1221 remote-endpoint = <&mdp5_intf3_out>; 1222 }; 1223 }; 1224 }; 1225 }; 1226 1227 mdss_hdmi_phy: phy@9a0600 { 1228 #phy-cells = <0>; 1229 compatible = "qcom,hdmi-phy-8996"; 1230 reg = <0x009a0600 0x1c4>, 1231 <0x009a0a00 0x124>, 1232 <0x009a0c00 0x124>, 1233 <0x009a0e00 0x124>, 1234 <0x009a1000 0x124>, 1235 <0x009a1200 0x0c8>; 1236 reg-names = "hdmi_pll", 1237 "hdmi_tx_l0", 1238 "hdmi_tx_l1", 1239 "hdmi_tx_l2", 1240 "hdmi_tx_l3", 1241 "hdmi_phy"; 1242 1243 clocks = <&mmcc MDSS_AHB_CLK>, 1244 <&gcc GCC_HDMI_CLKREF_CLK>, 1245 <&xo_board>; 1246 clock-names = "iface", 1247 "ref", 1248 "xo"; 1249 1250 #clock-cells = <0>; 1251 1252 status = "disabled"; 1253 }; 1254 }; 1255 1256 gpu: gpu@b00000 { 1257 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1258 1259 reg = <0x00b00000 0x3f000>; 1260 reg-names = "kgsl_3d0_reg_memory"; 1261 1262 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1263 1264 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1265 <&mmcc GPU_AHB_CLK>, 1266 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1267 <&gcc GCC_BIMC_GFX_CLK>, 1268 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1269 1270 clock-names = "core", 1271 "iface", 1272 "rbbmtimer", 1273 "mem", 1274 "mem_iface"; 1275 1276 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1277 interconnect-names = "gfx-mem"; 1278 1279 power-domains = <&mmcc GPU_GX_GDSC>; 1280 iommus = <&adreno_smmu 0>; 1281 1282 nvmem-cells = <&speedbin_efuse>; 1283 nvmem-cell-names = "speed_bin"; 1284 1285 operating-points-v2 = <&gpu_opp_table>; 1286 1287 status = "disabled"; 1288 1289 #cooling-cells = <2>; 1290 1291 gpu_opp_table: opp-table { 1292 compatible = "operating-points-v2"; 1293 1294 /* 1295 * 624Mhz is only available on speed bins 0 and 3. 1296 * 560Mhz is only available on speed bins 0, 2 and 3. 1297 * All the rest are available on all bins of the hardware. 1298 */ 1299 opp-624000000 { 1300 opp-hz = /bits/ 64 <624000000>; 1301 opp-supported-hw = <0x09>; 1302 }; 1303 opp-560000000 { 1304 opp-hz = /bits/ 64 <560000000>; 1305 opp-supported-hw = <0x0d>; 1306 }; 1307 opp-510000000 { 1308 opp-hz = /bits/ 64 <510000000>; 1309 opp-supported-hw = <0xff>; 1310 }; 1311 opp-401800000 { 1312 opp-hz = /bits/ 64 <401800000>; 1313 opp-supported-hw = <0xff>; 1314 }; 1315 opp-315000000 { 1316 opp-hz = /bits/ 64 <315000000>; 1317 opp-supported-hw = <0xff>; 1318 }; 1319 opp-214000000 { 1320 opp-hz = /bits/ 64 <214000000>; 1321 opp-supported-hw = <0xff>; 1322 }; 1323 opp-133000000 { 1324 opp-hz = /bits/ 64 <133000000>; 1325 opp-supported-hw = <0xff>; 1326 }; 1327 }; 1328 1329 zap-shader { 1330 memory-region = <&gpu_mem>; 1331 }; 1332 }; 1333 1334 tlmm: pinctrl@1010000 { 1335 compatible = "qcom,msm8996-pinctrl"; 1336 reg = <0x01010000 0x300000>; 1337 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1338 gpio-controller; 1339 gpio-ranges = <&tlmm 0 0 150>; 1340 #gpio-cells = <2>; 1341 interrupt-controller; 1342 #interrupt-cells = <2>; 1343 1344 blsp1_spi1_default: blsp1-spi1-default-state { 1345 spi-pins { 1346 pins = "gpio0", "gpio1", "gpio3"; 1347 function = "blsp_spi1"; 1348 drive-strength = <12>; 1349 bias-disable; 1350 }; 1351 1352 cs-pins { 1353 pins = "gpio2"; 1354 function = "gpio"; 1355 drive-strength = <16>; 1356 bias-disable; 1357 output-high; 1358 }; 1359 }; 1360 1361 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 1362 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1363 function = "gpio"; 1364 drive-strength = <2>; 1365 bias-pull-down; 1366 }; 1367 1368 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { 1369 pins = "gpio4", "gpio5"; 1370 function = "blsp_uart8"; 1371 drive-strength = <16>; 1372 bias-disable; 1373 }; 1374 1375 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { 1376 pins = "gpio4", "gpio5"; 1377 function = "gpio"; 1378 drive-strength = <2>; 1379 bias-disable; 1380 }; 1381 1382 blsp2_i2c2_default: blsp2-i2c2-state { 1383 pins = "gpio6", "gpio7"; 1384 function = "blsp_i2c8"; 1385 drive-strength = <16>; 1386 bias-disable; 1387 }; 1388 1389 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1390 pins = "gpio6", "gpio7"; 1391 function = "gpio"; 1392 drive-strength = <2>; 1393 bias-disable; 1394 }; 1395 1396 blsp1_i2c6_default: blsp1-i2c6-state { 1397 pins = "gpio27", "gpio28"; 1398 function = "blsp_i2c6"; 1399 drive-strength = <16>; 1400 bias-disable; 1401 }; 1402 1403 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1404 pins = "gpio27", "gpio28"; 1405 function = "gpio"; 1406 drive-strength = <2>; 1407 bias-pull-up; 1408 }; 1409 1410 cci0_default: cci0-default-state { 1411 pins = "gpio17", "gpio18"; 1412 function = "cci_i2c"; 1413 drive-strength = <16>; 1414 bias-disable; 1415 }; 1416 1417 camera0_state_on: 1418 camera_rear_default: camera-rear-default-state { 1419 camera0_mclk: mclk0-pins { 1420 pins = "gpio13"; 1421 function = "cam_mclk"; 1422 drive-strength = <16>; 1423 bias-disable; 1424 }; 1425 1426 camera0_rst: rst-pins { 1427 pins = "gpio25"; 1428 function = "gpio"; 1429 drive-strength = <16>; 1430 bias-disable; 1431 }; 1432 1433 camera0_pwdn: pwdn-pins { 1434 pins = "gpio26"; 1435 function = "gpio"; 1436 drive-strength = <16>; 1437 bias-disable; 1438 }; 1439 }; 1440 1441 cci1_default: cci1-default-state { 1442 pins = "gpio19", "gpio20"; 1443 function = "cci_i2c"; 1444 drive-strength = <16>; 1445 bias-disable; 1446 }; 1447 1448 camera1_state_on: 1449 camera_board_default: camera-board-default-state { 1450 mclk1-pins { 1451 pins = "gpio14"; 1452 function = "cam_mclk"; 1453 drive-strength = <16>; 1454 bias-disable; 1455 }; 1456 1457 pwdn-pins { 1458 pins = "gpio98"; 1459 function = "gpio"; 1460 drive-strength = <16>; 1461 bias-disable; 1462 }; 1463 1464 rst-pins { 1465 pins = "gpio104"; 1466 function = "gpio"; 1467 drive-strength = <16>; 1468 bias-disable; 1469 }; 1470 }; 1471 1472 camera2_state_on: 1473 camera_front_default: camera-front-default-state { 1474 camera2_mclk: mclk2-pins { 1475 pins = "gpio15"; 1476 function = "cam_mclk"; 1477 drive-strength = <16>; 1478 bias-disable; 1479 }; 1480 1481 camera2_rst: rst-pins { 1482 pins = "gpio23"; 1483 function = "gpio"; 1484 drive-strength = <16>; 1485 bias-disable; 1486 }; 1487 1488 pwdn-pins { 1489 pins = "gpio133"; 1490 function = "gpio"; 1491 drive-strength = <16>; 1492 bias-disable; 1493 }; 1494 }; 1495 1496 pcie0_state_on: pcie0-state-on-state { 1497 perst-pins { 1498 pins = "gpio35"; 1499 function = "gpio"; 1500 drive-strength = <2>; 1501 bias-pull-down; 1502 }; 1503 1504 clkreq-pins { 1505 pins = "gpio36"; 1506 function = "pci_e0"; 1507 drive-strength = <2>; 1508 bias-pull-up; 1509 }; 1510 1511 wake-pins { 1512 pins = "gpio37"; 1513 function = "gpio"; 1514 drive-strength = <2>; 1515 bias-pull-up; 1516 }; 1517 }; 1518 1519 pcie0_state_off: pcie0-state-off-state { 1520 perst-pins { 1521 pins = "gpio35"; 1522 function = "gpio"; 1523 drive-strength = <2>; 1524 bias-pull-down; 1525 }; 1526 1527 clkreq-pins { 1528 pins = "gpio36"; 1529 function = "gpio"; 1530 drive-strength = <2>; 1531 bias-disable; 1532 }; 1533 1534 wake-pins { 1535 pins = "gpio37"; 1536 function = "gpio"; 1537 drive-strength = <2>; 1538 bias-disable; 1539 }; 1540 }; 1541 1542 blsp1_uart2_default: blsp1-uart2-default-state { 1543 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1544 function = "blsp_uart2"; 1545 drive-strength = <16>; 1546 bias-disable; 1547 }; 1548 1549 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 1550 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1551 function = "gpio"; 1552 drive-strength = <2>; 1553 bias-disable; 1554 }; 1555 1556 blsp1_i2c3_default: blsp1-i2c3-default-state { 1557 pins = "gpio47", "gpio48"; 1558 function = "blsp_i2c3"; 1559 drive-strength = <16>; 1560 bias-disable; 1561 }; 1562 1563 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1564 pins = "gpio47", "gpio48"; 1565 function = "gpio"; 1566 drive-strength = <2>; 1567 bias-disable; 1568 }; 1569 1570 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { 1571 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1572 function = "blsp_uart9"; 1573 drive-strength = <16>; 1574 bias-disable; 1575 }; 1576 1577 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { 1578 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1579 function = "blsp_uart9"; 1580 drive-strength = <2>; 1581 bias-disable; 1582 }; 1583 1584 blsp2_i2c3_default: blsp2-i2c3-state-state { 1585 pins = "gpio51", "gpio52"; 1586 function = "blsp_i2c9"; 1587 drive-strength = <16>; 1588 bias-disable; 1589 }; 1590 1591 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1592 pins = "gpio51", "gpio52"; 1593 function = "gpio"; 1594 drive-strength = <2>; 1595 bias-disable; 1596 }; 1597 1598 wcd_intr_default: wcd-intr-default-state { 1599 pins = "gpio54"; 1600 function = "gpio"; 1601 drive-strength = <2>; 1602 bias-pull-down; 1603 }; 1604 1605 blsp2_i2c1_default: blsp2-i2c1-state { 1606 pins = "gpio55", "gpio56"; 1607 function = "blsp_i2c7"; 1608 drive-strength = <16>; 1609 bias-disable; 1610 }; 1611 1612 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1613 pins = "gpio55", "gpio56"; 1614 function = "gpio"; 1615 drive-strength = <2>; 1616 bias-disable; 1617 }; 1618 1619 blsp2_i2c5_default: blsp2-i2c5-state { 1620 pins = "gpio60", "gpio61"; 1621 function = "blsp_i2c11"; 1622 drive-strength = <2>; 1623 bias-disable; 1624 }; 1625 1626 /* Sleep state for BLSP2_I2C5 is missing.. */ 1627 1628 cdc_reset_active: cdc-reset-active-state { 1629 pins = "gpio64"; 1630 function = "gpio"; 1631 drive-strength = <16>; 1632 bias-pull-down; 1633 output-high; 1634 }; 1635 1636 cdc_reset_sleep: cdc-reset-sleep-state { 1637 pins = "gpio64"; 1638 function = "gpio"; 1639 drive-strength = <16>; 1640 bias-disable; 1641 output-low; 1642 }; 1643 1644 blsp2_spi6_default: blsp2-spi6-default-state { 1645 spi-pins { 1646 pins = "gpio85", "gpio86", "gpio88"; 1647 function = "blsp_spi12"; 1648 drive-strength = <12>; 1649 bias-disable; 1650 }; 1651 1652 cs-pins { 1653 pins = "gpio87"; 1654 function = "gpio"; 1655 drive-strength = <16>; 1656 bias-disable; 1657 output-high; 1658 }; 1659 }; 1660 1661 blsp2_spi6_sleep: blsp2-spi6-sleep-state { 1662 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1663 function = "gpio"; 1664 drive-strength = <2>; 1665 bias-pull-down; 1666 }; 1667 1668 blsp2_i2c6_default: blsp2-i2c6-state { 1669 pins = "gpio87", "gpio88"; 1670 function = "blsp_i2c12"; 1671 drive-strength = <16>; 1672 bias-disable; 1673 }; 1674 1675 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1676 pins = "gpio87", "gpio88"; 1677 function = "gpio"; 1678 drive-strength = <2>; 1679 bias-disable; 1680 }; 1681 1682 pcie1_state_on: pcie1-on-state { 1683 perst-pins { 1684 pins = "gpio130"; 1685 function = "gpio"; 1686 drive-strength = <2>; 1687 bias-pull-down; 1688 }; 1689 1690 clkreq-pins { 1691 pins = "gpio131"; 1692 function = "pci_e1"; 1693 drive-strength = <2>; 1694 bias-pull-up; 1695 }; 1696 1697 wake-pins { 1698 pins = "gpio132"; 1699 function = "gpio"; 1700 drive-strength = <2>; 1701 bias-pull-down; 1702 }; 1703 }; 1704 1705 pcie1_state_off: pcie1-off-state { 1706 /* Perst is missing? */ 1707 clkreq-pins { 1708 pins = "gpio131"; 1709 function = "gpio"; 1710 drive-strength = <2>; 1711 bias-disable; 1712 }; 1713 1714 wake-pins { 1715 pins = "gpio132"; 1716 function = "gpio"; 1717 drive-strength = <2>; 1718 bias-disable; 1719 }; 1720 }; 1721 1722 pcie2_state_on: pcie2-on-state { 1723 perst-pins { 1724 pins = "gpio114"; 1725 function = "gpio"; 1726 drive-strength = <2>; 1727 bias-pull-down; 1728 }; 1729 1730 clkreq-pins { 1731 pins = "gpio115"; 1732 function = "pci_e2"; 1733 drive-strength = <2>; 1734 bias-pull-up; 1735 }; 1736 1737 wake-pins { 1738 pins = "gpio116"; 1739 function = "gpio"; 1740 drive-strength = <2>; 1741 bias-pull-down; 1742 }; 1743 }; 1744 1745 pcie2_state_off: pcie2-off-state { 1746 /* Perst is missing? */ 1747 clkreq-pins { 1748 pins = "gpio115"; 1749 function = "gpio"; 1750 drive-strength = <2>; 1751 bias-disable; 1752 }; 1753 1754 wake-pins { 1755 pins = "gpio116"; 1756 function = "gpio"; 1757 drive-strength = <2>; 1758 bias-disable; 1759 }; 1760 }; 1761 1762 sdc1_state_on: sdc1-on-state { 1763 clk-pins { 1764 pins = "sdc1_clk"; 1765 bias-disable; 1766 drive-strength = <16>; 1767 }; 1768 1769 cmd-pins { 1770 pins = "sdc1_cmd"; 1771 bias-pull-up; 1772 drive-strength = <10>; 1773 }; 1774 1775 data-pins { 1776 pins = "sdc1_data"; 1777 bias-pull-up; 1778 drive-strength = <10>; 1779 }; 1780 1781 rclk-pins { 1782 pins = "sdc1_rclk"; 1783 bias-pull-down; 1784 }; 1785 }; 1786 1787 sdc1_state_off: sdc1-off-state { 1788 clk-pins { 1789 pins = "sdc1_clk"; 1790 bias-disable; 1791 drive-strength = <2>; 1792 }; 1793 1794 cmd-pins { 1795 pins = "sdc1_cmd"; 1796 bias-pull-up; 1797 drive-strength = <2>; 1798 }; 1799 1800 data-pins { 1801 pins = "sdc1_data"; 1802 bias-pull-up; 1803 drive-strength = <2>; 1804 }; 1805 1806 rclk-pins { 1807 pins = "sdc1_rclk"; 1808 bias-pull-down; 1809 }; 1810 }; 1811 1812 sdc2_state_on: sdc2-on-state { 1813 clk-pins { 1814 pins = "sdc2_clk"; 1815 bias-disable; 1816 drive-strength = <16>; 1817 }; 1818 1819 cmd-pins { 1820 pins = "sdc2_cmd"; 1821 bias-pull-up; 1822 drive-strength = <10>; 1823 }; 1824 1825 data-pins { 1826 pins = "sdc2_data"; 1827 bias-pull-up; 1828 drive-strength = <10>; 1829 }; 1830 }; 1831 1832 sdc2_state_off: sdc2-off-state { 1833 clk-pins { 1834 pins = "sdc2_clk"; 1835 bias-disable; 1836 drive-strength = <2>; 1837 }; 1838 1839 cmd-pins { 1840 pins = "sdc2_cmd"; 1841 bias-pull-up; 1842 drive-strength = <2>; 1843 }; 1844 1845 data-pins { 1846 pins = "sdc2_data"; 1847 bias-pull-up; 1848 drive-strength = <2>; 1849 }; 1850 }; 1851 }; 1852 1853 sram@290000 { 1854 compatible = "qcom,rpm-stats"; 1855 reg = <0x00290000 0x10000>; 1856 }; 1857 1858 spmi_bus: spmi@400f000 { 1859 compatible = "qcom,spmi-pmic-arb"; 1860 reg = <0x0400f000 0x1000>, 1861 <0x04400000 0x800000>, 1862 <0x04c00000 0x800000>, 1863 <0x05800000 0x200000>, 1864 <0x0400a000 0x002100>; 1865 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1866 interrupt-names = "periph_irq"; 1867 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1868 qcom,ee = <0>; 1869 qcom,channel = <0>; 1870 #address-cells = <2>; 1871 #size-cells = <0>; 1872 interrupt-controller; 1873 #interrupt-cells = <4>; 1874 }; 1875 1876 bus@0 { 1877 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1878 compatible = "simple-pm-bus"; 1879 #address-cells = <1>; 1880 #size-cells = <1>; 1881 ranges = <0x0 0x0 0xffffffff>; 1882 1883 pcie0: pcie@600000 { 1884 compatible = "qcom,pcie-msm8996"; 1885 status = "disabled"; 1886 power-domains = <&gcc PCIE0_GDSC>; 1887 bus-range = <0x00 0xff>; 1888 num-lanes = <1>; 1889 1890 reg = <0x00600000 0x2000>, 1891 <0x0c000000 0xf1d>, 1892 <0x0c000f20 0xa8>, 1893 <0x0c100000 0x100000>; 1894 reg-names = "parf", "dbi", "elbi","config"; 1895 1896 phys = <&pciephy_0>; 1897 phy-names = "pciephy"; 1898 1899 #address-cells = <3>; 1900 #size-cells = <2>; 1901 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, 1902 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1903 1904 device_type = "pci"; 1905 1906 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1907 interrupt-names = "msi"; 1908 #interrupt-cells = <1>; 1909 interrupt-map-mask = <0 0 0 0x7>; 1910 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1911 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1912 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1913 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1914 1915 pinctrl-names = "default", "sleep"; 1916 pinctrl-0 = <&pcie0_state_on>; 1917 pinctrl-1 = <&pcie0_state_off>; 1918 1919 linux,pci-domain = <0>; 1920 1921 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1922 <&gcc GCC_PCIE_0_AUX_CLK>, 1923 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1924 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1925 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1926 1927 clock-names = "pipe", 1928 "aux", 1929 "cfg", 1930 "bus_master", 1931 "bus_slave"; 1932 1933 pcie@0 { 1934 device_type = "pci"; 1935 reg = <0x0 0x0 0x0 0x0 0x0>; 1936 bus-range = <0x01 0xff>; 1937 1938 #address-cells = <3>; 1939 #size-cells = <2>; 1940 ranges; 1941 }; 1942 }; 1943 1944 pcie1: pcie@608000 { 1945 compatible = "qcom,pcie-msm8996"; 1946 power-domains = <&gcc PCIE1_GDSC>; 1947 bus-range = <0x00 0xff>; 1948 num-lanes = <1>; 1949 1950 status = "disabled"; 1951 1952 reg = <0x00608000 0x2000>, 1953 <0x0d000000 0xf1d>, 1954 <0x0d000f20 0xa8>, 1955 <0x0d100000 0x100000>; 1956 1957 reg-names = "parf", "dbi", "elbi","config"; 1958 1959 phys = <&pciephy_1>; 1960 phy-names = "pciephy"; 1961 1962 #address-cells = <3>; 1963 #size-cells = <2>; 1964 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, 1965 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1966 1967 device_type = "pci"; 1968 1969 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1970 interrupt-names = "msi"; 1971 #interrupt-cells = <1>; 1972 interrupt-map-mask = <0 0 0 0x7>; 1973 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1974 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1975 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1976 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1977 1978 pinctrl-names = "default", "sleep"; 1979 pinctrl-0 = <&pcie1_state_on>; 1980 pinctrl-1 = <&pcie1_state_off>; 1981 1982 linux,pci-domain = <1>; 1983 1984 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1985 <&gcc GCC_PCIE_1_AUX_CLK>, 1986 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1987 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1988 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1989 1990 clock-names = "pipe", 1991 "aux", 1992 "cfg", 1993 "bus_master", 1994 "bus_slave"; 1995 1996 pcie@0 { 1997 device_type = "pci"; 1998 reg = <0x0 0x0 0x0 0x0 0x0>; 1999 bus-range = <0x01 0xff>; 2000 2001 #address-cells = <3>; 2002 #size-cells = <2>; 2003 ranges; 2004 }; 2005 }; 2006 2007 pcie2: pcie@610000 { 2008 compatible = "qcom,pcie-msm8996"; 2009 power-domains = <&gcc PCIE2_GDSC>; 2010 bus-range = <0x00 0xff>; 2011 num-lanes = <1>; 2012 status = "disabled"; 2013 reg = <0x00610000 0x2000>, 2014 <0x0e000000 0xf1d>, 2015 <0x0e000f20 0xa8>, 2016 <0x0e100000 0x100000>; 2017 2018 reg-names = "parf", "dbi", "elbi","config"; 2019 2020 phys = <&pciephy_2>; 2021 phy-names = "pciephy"; 2022 2023 #address-cells = <3>; 2024 #size-cells = <2>; 2025 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, 2026 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 2027 2028 device_type = "pci"; 2029 2030 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 2031 interrupt-names = "msi"; 2032 #interrupt-cells = <1>; 2033 interrupt-map-mask = <0 0 0 0x7>; 2034 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2035 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2036 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2037 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2038 2039 pinctrl-names = "default", "sleep"; 2040 pinctrl-0 = <&pcie2_state_on>; 2041 pinctrl-1 = <&pcie2_state_off>; 2042 2043 linux,pci-domain = <2>; 2044 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2045 <&gcc GCC_PCIE_2_AUX_CLK>, 2046 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2047 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2048 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 2049 2050 clock-names = "pipe", 2051 "aux", 2052 "cfg", 2053 "bus_master", 2054 "bus_slave"; 2055 2056 pcie@0 { 2057 device_type = "pci"; 2058 reg = <0x0 0x0 0x0 0x0 0x0>; 2059 bus-range = <0x01 0xff>; 2060 2061 #address-cells = <3>; 2062 #size-cells = <2>; 2063 ranges; 2064 }; 2065 }; 2066 }; 2067 2068 ufshc: ufshc@624000 { 2069 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 2070 "jedec,ufs-2.0"; 2071 reg = <0x00624000 0x2500>; 2072 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2073 2074 phys = <&ufsphy>; 2075 phy-names = "ufsphy"; 2076 2077 power-domains = <&gcc UFS_GDSC>; 2078 2079 clock-names = 2080 "core_clk_src", 2081 "core_clk", 2082 "bus_clk", 2083 "bus_aggr_clk", 2084 "iface_clk", 2085 "core_clk_unipro_src", 2086 "core_clk_unipro", 2087 "core_clk_ice", 2088 "ref_clk", 2089 "tx_lane0_sync_clk", 2090 "rx_lane0_sync_clk"; 2091 clocks = 2092 <&gcc UFS_AXI_CLK_SRC>, 2093 <&gcc GCC_UFS_AXI_CLK>, 2094 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 2095 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 2096 <&gcc GCC_UFS_AHB_CLK>, 2097 <&gcc UFS_ICE_CORE_CLK_SRC>, 2098 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 2099 <&gcc GCC_UFS_ICE_CORE_CLK>, 2100 <&rpmcc RPM_SMD_LN_BB_CLK>, 2101 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 2102 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 2103 freq-table-hz = 2104 <100000000 200000000>, 2105 <0 0>, 2106 <0 0>, 2107 <0 0>, 2108 <0 0>, 2109 <150000000 300000000>, 2110 <75000000 150000000>, 2111 <0 0>, 2112 <0 0>, 2113 <0 0>, 2114 <0 0>; 2115 2116 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, 2117 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; 2118 interconnect-names = "ufs-ddr", "cpu-ufs"; 2119 2120 lanes-per-direction = <1>; 2121 #reset-cells = <1>; 2122 status = "disabled"; 2123 }; 2124 2125 ufsphy: phy@627000 { 2126 compatible = "qcom,msm8996-qmp-ufs-phy"; 2127 reg = <0x00627000 0x1000>; 2128 2129 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>; 2130 clock-names = "ref", "qref"; 2131 2132 resets = <&ufshc 0>; 2133 reset-names = "ufsphy"; 2134 2135 #clock-cells = <1>; 2136 #phy-cells = <0>; 2137 2138 status = "disabled"; 2139 }; 2140 2141 camss: camss@a34000 { 2142 compatible = "qcom,msm8996-camss"; 2143 reg = <0x00a34000 0x1000>, 2144 <0x00a00030 0x4>, 2145 <0x00a35000 0x1000>, 2146 <0x00a00038 0x4>, 2147 <0x00a36000 0x1000>, 2148 <0x00a00040 0x4>, 2149 <0x00a30000 0x100>, 2150 <0x00a30400 0x100>, 2151 <0x00a30800 0x100>, 2152 <0x00a30c00 0x100>, 2153 <0x00a31000 0x500>, 2154 <0x00a00020 0x10>, 2155 <0x00a10000 0x1000>, 2156 <0x00a14000 0x1000>; 2157 reg-names = "csiphy0", 2158 "csiphy0_clk_mux", 2159 "csiphy1", 2160 "csiphy1_clk_mux", 2161 "csiphy2", 2162 "csiphy2_clk_mux", 2163 "csid0", 2164 "csid1", 2165 "csid2", 2166 "csid3", 2167 "ispif", 2168 "csi_clk_mux", 2169 "vfe0", 2170 "vfe1"; 2171 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2179 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2180 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2181 interrupt-names = "csiphy0", 2182 "csiphy1", 2183 "csiphy2", 2184 "csid0", 2185 "csid1", 2186 "csid2", 2187 "csid3", 2188 "ispif", 2189 "vfe0", 2190 "vfe1"; 2191 power-domains = <&mmcc VFE0_GDSC>, 2192 <&mmcc VFE1_GDSC>; 2193 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2194 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2195 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2196 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2197 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2198 <&mmcc CAMSS_CSI0_AHB_CLK>, 2199 <&mmcc CAMSS_CSI0_CLK>, 2200 <&mmcc CAMSS_CSI0PHY_CLK>, 2201 <&mmcc CAMSS_CSI0PIX_CLK>, 2202 <&mmcc CAMSS_CSI0RDI_CLK>, 2203 <&mmcc CAMSS_CSI1_AHB_CLK>, 2204 <&mmcc CAMSS_CSI1_CLK>, 2205 <&mmcc CAMSS_CSI1PHY_CLK>, 2206 <&mmcc CAMSS_CSI1PIX_CLK>, 2207 <&mmcc CAMSS_CSI1RDI_CLK>, 2208 <&mmcc CAMSS_CSI2_AHB_CLK>, 2209 <&mmcc CAMSS_CSI2_CLK>, 2210 <&mmcc CAMSS_CSI2PHY_CLK>, 2211 <&mmcc CAMSS_CSI2PIX_CLK>, 2212 <&mmcc CAMSS_CSI2RDI_CLK>, 2213 <&mmcc CAMSS_CSI3_AHB_CLK>, 2214 <&mmcc CAMSS_CSI3_CLK>, 2215 <&mmcc CAMSS_CSI3PHY_CLK>, 2216 <&mmcc CAMSS_CSI3PIX_CLK>, 2217 <&mmcc CAMSS_CSI3RDI_CLK>, 2218 <&mmcc CAMSS_AHB_CLK>, 2219 <&mmcc CAMSS_VFE0_CLK>, 2220 <&mmcc CAMSS_CSI_VFE0_CLK>, 2221 <&mmcc CAMSS_VFE0_AHB_CLK>, 2222 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2223 <&mmcc CAMSS_VFE1_CLK>, 2224 <&mmcc CAMSS_CSI_VFE1_CLK>, 2225 <&mmcc CAMSS_VFE1_AHB_CLK>, 2226 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2227 <&mmcc CAMSS_VFE_AHB_CLK>, 2228 <&mmcc CAMSS_VFE_AXI_CLK>; 2229 clock-names = "top_ahb", 2230 "ispif_ahb", 2231 "csiphy0_timer", 2232 "csiphy1_timer", 2233 "csiphy2_timer", 2234 "csi0_ahb", 2235 "csi0", 2236 "csi0_phy", 2237 "csi0_pix", 2238 "csi0_rdi", 2239 "csi1_ahb", 2240 "csi1", 2241 "csi1_phy", 2242 "csi1_pix", 2243 "csi1_rdi", 2244 "csi2_ahb", 2245 "csi2", 2246 "csi2_phy", 2247 "csi2_pix", 2248 "csi2_rdi", 2249 "csi3_ahb", 2250 "csi3", 2251 "csi3_phy", 2252 "csi3_pix", 2253 "csi3_rdi", 2254 "ahb", 2255 "vfe0", 2256 "csi_vfe0", 2257 "vfe0_ahb", 2258 "vfe0_stream", 2259 "vfe1", 2260 "csi_vfe1", 2261 "vfe1_ahb", 2262 "vfe1_stream", 2263 "vfe_ahb", 2264 "vfe_axi"; 2265 iommus = <&vfe_smmu 0>, 2266 <&vfe_smmu 1>, 2267 <&vfe_smmu 2>, 2268 <&vfe_smmu 3>; 2269 status = "disabled"; 2270 ports { 2271 #address-cells = <1>; 2272 #size-cells = <0>; 2273 }; 2274 }; 2275 2276 cci: cci@a0c000 { 2277 compatible = "qcom,msm8996-cci"; 2278 #address-cells = <1>; 2279 #size-cells = <0>; 2280 reg = <0xa0c000 0x1000>; 2281 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2282 power-domains = <&mmcc CAMSS_GDSC>; 2283 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2284 <&mmcc CAMSS_CCI_AHB_CLK>, 2285 <&mmcc CAMSS_CCI_CLK>, 2286 <&mmcc CAMSS_AHB_CLK>; 2287 clock-names = "camss_top_ahb", 2288 "cci_ahb", 2289 "cci", 2290 "camss_ahb"; 2291 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2292 <&mmcc CAMSS_CCI_CLK>; 2293 assigned-clock-rates = <80000000>, <37500000>; 2294 pinctrl-names = "default"; 2295 pinctrl-0 = <&cci0_default &cci1_default>; 2296 status = "disabled"; 2297 2298 cci_i2c0: i2c-bus@0 { 2299 reg = <0>; 2300 clock-frequency = <400000>; 2301 #address-cells = <1>; 2302 #size-cells = <0>; 2303 }; 2304 2305 cci_i2c1: i2c-bus@1 { 2306 reg = <1>; 2307 clock-frequency = <400000>; 2308 #address-cells = <1>; 2309 #size-cells = <0>; 2310 }; 2311 }; 2312 2313 adreno_smmu: iommu@b40000 { 2314 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2315 reg = <0x00b40000 0x10000>; 2316 2317 #global-interrupts = <1>; 2318 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2319 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2320 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2321 #iommu-cells = <1>; 2322 2323 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, 2324 <&mmcc GPU_AHB_CLK>; 2325 clock-names = "bus", "iface"; 2326 2327 power-domains = <&mmcc GPU_GDSC>; 2328 }; 2329 2330 venus: video-codec@c00000 { 2331 compatible = "qcom,msm8996-venus"; 2332 reg = <0x00c00000 0xff000>; 2333 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2334 power-domains = <&mmcc VENUS_GDSC>; 2335 clocks = <&mmcc VIDEO_CORE_CLK>, 2336 <&mmcc VIDEO_AHB_CLK>, 2337 <&mmcc VIDEO_AXI_CLK>, 2338 <&mmcc VIDEO_MAXI_CLK>; 2339 clock-names = "core", "iface", "bus", "mbus"; 2340 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2341 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2342 interconnect-names = "video-mem", "cpu-cfg"; 2343 iommus = <&venus_smmu 0x00>, 2344 <&venus_smmu 0x01>, 2345 <&venus_smmu 0x0a>, 2346 <&venus_smmu 0x07>, 2347 <&venus_smmu 0x0e>, 2348 <&venus_smmu 0x0f>, 2349 <&venus_smmu 0x08>, 2350 <&venus_smmu 0x09>, 2351 <&venus_smmu 0x0b>, 2352 <&venus_smmu 0x0c>, 2353 <&venus_smmu 0x0d>, 2354 <&venus_smmu 0x10>, 2355 <&venus_smmu 0x11>, 2356 <&venus_smmu 0x21>, 2357 <&venus_smmu 0x28>, 2358 <&venus_smmu 0x29>, 2359 <&venus_smmu 0x2b>, 2360 <&venus_smmu 0x2c>, 2361 <&venus_smmu 0x2d>, 2362 <&venus_smmu 0x31>; 2363 memory-region = <&venus_mem>; 2364 status = "disabled"; 2365 2366 video-decoder { 2367 compatible = "venus-decoder"; 2368 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2369 clock-names = "core"; 2370 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2371 }; 2372 2373 video-encoder { 2374 compatible = "venus-encoder"; 2375 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2376 clock-names = "core"; 2377 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2378 }; 2379 }; 2380 2381 mdp_smmu: iommu@d00000 { 2382 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2383 reg = <0x00d00000 0x10000>; 2384 2385 #global-interrupts = <1>; 2386 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2387 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2388 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2389 #iommu-cells = <1>; 2390 clocks = <&mmcc SMMU_MDP_AXI_CLK>, 2391 <&mmcc SMMU_MDP_AHB_CLK>; 2392 clock-names = "bus", "iface"; 2393 2394 power-domains = <&mmcc MDSS_GDSC>; 2395 }; 2396 2397 venus_smmu: iommu@d40000 { 2398 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2399 reg = <0x00d40000 0x20000>; 2400 #global-interrupts = <1>; 2401 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2405 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2406 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2407 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2408 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2409 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2410 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, 2411 <&mmcc SMMU_VIDEO_AHB_CLK>; 2412 clock-names = "bus", "iface"; 2413 #iommu-cells = <1>; 2414 status = "okay"; 2415 }; 2416 2417 vfe_smmu: iommu@da0000 { 2418 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2419 reg = <0x00da0000 0x10000>; 2420 2421 #global-interrupts = <1>; 2422 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2423 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2424 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2425 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2426 clocks = <&mmcc SMMU_VFE_AXI_CLK>, 2427 <&mmcc SMMU_VFE_AHB_CLK>; 2428 clock-names = "bus", "iface"; 2429 #iommu-cells = <1>; 2430 }; 2431 2432 lpass_q6_smmu: iommu@1600000 { 2433 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2434 reg = <0x01600000 0x20000>; 2435 #iommu-cells = <1>; 2436 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2437 2438 #global-interrupts = <1>; 2439 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2440 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2441 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2448 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2449 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2450 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2451 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2452 2453 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, 2454 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; 2455 clock-names = "bus", "iface"; 2456 }; 2457 2458 slpi_pil: remoteproc@1c00000 { 2459 compatible = "qcom,msm8996-slpi-pil"; 2460 reg = <0x01c00000 0x4000>; 2461 2462 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2463 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2464 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2465 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2466 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2467 interrupt-names = "wdog", 2468 "fatal", 2469 "ready", 2470 "handover", 2471 "stop-ack"; 2472 2473 clocks = <&xo_board>; 2474 clock-names = "xo"; 2475 2476 memory-region = <&slpi_mem>; 2477 2478 qcom,smem-states = <&slpi_smp2p_out 0>; 2479 qcom,smem-state-names = "stop"; 2480 2481 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2482 power-domain-names = "ssc_cx"; 2483 2484 status = "disabled"; 2485 2486 smd-edge { 2487 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2488 2489 label = "dsps"; 2490 mboxes = <&apcs_glb 25>; 2491 qcom,smd-edge = <3>; 2492 qcom,remote-pid = <3>; 2493 }; 2494 }; 2495 2496 mss_pil: remoteproc@2080000 { 2497 compatible = "qcom,msm8996-mss-pil"; 2498 reg = <0x2080000 0x100>, 2499 <0x2180000 0x020>; 2500 reg-names = "qdsp6", "rmb"; 2501 2502 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2503 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2504 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2505 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2506 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2507 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2508 interrupt-names = "wdog", "fatal", "ready", 2509 "handover", "stop-ack", 2510 "shutdown-ack"; 2511 2512 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2513 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2514 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2515 <&xo_board>, 2516 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2517 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2518 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2519 <&rpmcc RPM_SMD_QDSS_CLK>; 2520 clock-names = "iface", 2521 "bus", 2522 "mem", 2523 "xo", 2524 "gpll0_mss", 2525 "snoc_axi", 2526 "mnoc_axi", 2527 "qdss"; 2528 2529 resets = <&gcc GCC_MSS_RESTART>; 2530 reset-names = "mss_restart"; 2531 2532 power-domains = <&rpmpd MSM8996_VDDCX>, 2533 <&rpmpd MSM8996_VDDMX>; 2534 power-domain-names = "cx", "mx"; 2535 2536 qcom,smem-states = <&mpss_smp2p_out 0>; 2537 qcom,smem-state-names = "stop"; 2538 2539 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2540 2541 status = "disabled"; 2542 2543 mba { 2544 memory-region = <&mba_mem>; 2545 }; 2546 2547 mpss { 2548 memory-region = <&mpss_mem>; 2549 }; 2550 2551 metadata { 2552 memory-region = <&mdata_mem>; 2553 }; 2554 2555 smd-edge { 2556 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2557 2558 label = "mpss"; 2559 mboxes = <&apcs_glb 12>; 2560 qcom,smd-edge = <0>; 2561 qcom,remote-pid = <1>; 2562 }; 2563 }; 2564 2565 stm@3002000 { 2566 compatible = "arm,coresight-stm", "arm,primecell"; 2567 reg = <0x3002000 0x1000>, 2568 <0x8280000 0x180000>; 2569 reg-names = "stm-base", "stm-stimulus-base"; 2570 2571 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2572 clock-names = "apb_pclk", "atclk"; 2573 2574 out-ports { 2575 port { 2576 stm_out: endpoint { 2577 remote-endpoint = 2578 <&funnel0_in>; 2579 }; 2580 }; 2581 }; 2582 }; 2583 2584 tpiu@3020000 { 2585 compatible = "arm,coresight-tpiu", "arm,primecell"; 2586 reg = <0x3020000 0x1000>; 2587 2588 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2589 clock-names = "apb_pclk", "atclk"; 2590 2591 in-ports { 2592 port { 2593 tpiu_in: endpoint { 2594 remote-endpoint = 2595 <&replicator_out1>; 2596 }; 2597 }; 2598 }; 2599 }; 2600 2601 funnel@3021000 { 2602 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2603 reg = <0x3021000 0x1000>; 2604 2605 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2606 clock-names = "apb_pclk", "atclk"; 2607 2608 in-ports { 2609 #address-cells = <1>; 2610 #size-cells = <0>; 2611 2612 port@7 { 2613 reg = <7>; 2614 funnel0_in: endpoint { 2615 remote-endpoint = 2616 <&stm_out>; 2617 }; 2618 }; 2619 }; 2620 2621 out-ports { 2622 port { 2623 funnel0_out: endpoint { 2624 remote-endpoint = 2625 <&merge_funnel_in0>; 2626 }; 2627 }; 2628 }; 2629 }; 2630 2631 funnel@3022000 { 2632 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2633 reg = <0x3022000 0x1000>; 2634 2635 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2636 clock-names = "apb_pclk", "atclk"; 2637 2638 in-ports { 2639 #address-cells = <1>; 2640 #size-cells = <0>; 2641 2642 port@6 { 2643 reg = <6>; 2644 funnel1_in: endpoint { 2645 remote-endpoint = 2646 <&apss_merge_funnel_out>; 2647 }; 2648 }; 2649 }; 2650 2651 out-ports { 2652 port { 2653 funnel1_out: endpoint { 2654 remote-endpoint = 2655 <&merge_funnel_in1>; 2656 }; 2657 }; 2658 }; 2659 }; 2660 2661 funnel@3023000 { 2662 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2663 reg = <0x3023000 0x1000>; 2664 2665 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2666 clock-names = "apb_pclk", "atclk"; 2667 2668 in-ports { 2669 port { 2670 funnel_in2_in_modem_etm: endpoint { 2671 remote-endpoint = 2672 <&modem_etm_out_funnel_in2>; 2673 }; 2674 }; 2675 }; 2676 2677 out-ports { 2678 port { 2679 funnel2_out: endpoint { 2680 remote-endpoint = 2681 <&merge_funnel_in2>; 2682 }; 2683 }; 2684 }; 2685 }; 2686 2687 funnel@3025000 { 2688 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2689 reg = <0x3025000 0x1000>; 2690 2691 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2692 clock-names = "apb_pclk", "atclk"; 2693 2694 in-ports { 2695 #address-cells = <1>; 2696 #size-cells = <0>; 2697 2698 port@0 { 2699 reg = <0>; 2700 merge_funnel_in0: endpoint { 2701 remote-endpoint = 2702 <&funnel0_out>; 2703 }; 2704 }; 2705 2706 port@1 { 2707 reg = <1>; 2708 merge_funnel_in1: endpoint { 2709 remote-endpoint = 2710 <&funnel1_out>; 2711 }; 2712 }; 2713 2714 port@2 { 2715 reg = <2>; 2716 merge_funnel_in2: endpoint { 2717 remote-endpoint = 2718 <&funnel2_out>; 2719 }; 2720 }; 2721 }; 2722 2723 out-ports { 2724 port { 2725 merge_funnel_out: endpoint { 2726 remote-endpoint = 2727 <&etf_in>; 2728 }; 2729 }; 2730 }; 2731 }; 2732 2733 replicator@3026000 { 2734 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2735 reg = <0x3026000 0x1000>; 2736 2737 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2738 clock-names = "apb_pclk", "atclk"; 2739 2740 in-ports { 2741 port { 2742 replicator_in: endpoint { 2743 remote-endpoint = 2744 <&etf_out>; 2745 }; 2746 }; 2747 }; 2748 2749 out-ports { 2750 #address-cells = <1>; 2751 #size-cells = <0>; 2752 2753 port@0 { 2754 reg = <0>; 2755 replicator_out0: endpoint { 2756 remote-endpoint = 2757 <&etr_in>; 2758 }; 2759 }; 2760 2761 port@1 { 2762 reg = <1>; 2763 replicator_out1: endpoint { 2764 remote-endpoint = 2765 <&tpiu_in>; 2766 }; 2767 }; 2768 }; 2769 }; 2770 2771 etf@3027000 { 2772 compatible = "arm,coresight-tmc", "arm,primecell"; 2773 reg = <0x3027000 0x1000>; 2774 2775 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2776 clock-names = "apb_pclk", "atclk"; 2777 2778 in-ports { 2779 port { 2780 etf_in: endpoint { 2781 remote-endpoint = 2782 <&merge_funnel_out>; 2783 }; 2784 }; 2785 }; 2786 2787 out-ports { 2788 port { 2789 etf_out: endpoint { 2790 remote-endpoint = 2791 <&replicator_in>; 2792 }; 2793 }; 2794 }; 2795 }; 2796 2797 etr@3028000 { 2798 compatible = "arm,coresight-tmc", "arm,primecell"; 2799 reg = <0x3028000 0x1000>; 2800 2801 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2802 clock-names = "apb_pclk", "atclk"; 2803 arm,scatter-gather; 2804 2805 in-ports { 2806 port { 2807 etr_in: endpoint { 2808 remote-endpoint = 2809 <&replicator_out0>; 2810 }; 2811 }; 2812 }; 2813 }; 2814 2815 debug@3810000 { 2816 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2817 reg = <0x3810000 0x1000>; 2818 2819 clocks = <&rpmcc RPM_QDSS_CLK>; 2820 clock-names = "apb_pclk"; 2821 2822 cpu = <&CPU0>; 2823 }; 2824 2825 etm@3840000 { 2826 compatible = "arm,coresight-etm4x", "arm,primecell"; 2827 reg = <0x3840000 0x1000>; 2828 2829 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2830 clock-names = "apb_pclk", "atclk"; 2831 2832 cpu = <&CPU0>; 2833 2834 out-ports { 2835 port { 2836 etm0_out: endpoint { 2837 remote-endpoint = 2838 <&apss_funnel0_in0>; 2839 }; 2840 }; 2841 }; 2842 }; 2843 2844 debug@3910000 { 2845 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2846 reg = <0x3910000 0x1000>; 2847 2848 clocks = <&rpmcc RPM_QDSS_CLK>; 2849 clock-names = "apb_pclk"; 2850 2851 cpu = <&CPU1>; 2852 }; 2853 2854 etm@3940000 { 2855 compatible = "arm,coresight-etm4x", "arm,primecell"; 2856 reg = <0x3940000 0x1000>; 2857 2858 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2859 clock-names = "apb_pclk", "atclk"; 2860 2861 cpu = <&CPU1>; 2862 2863 out-ports { 2864 port { 2865 etm1_out: endpoint { 2866 remote-endpoint = 2867 <&apss_funnel0_in1>; 2868 }; 2869 }; 2870 }; 2871 }; 2872 2873 funnel@39b0000 { /* APSS Funnel 0 */ 2874 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2875 reg = <0x39b0000 0x1000>; 2876 2877 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2878 clock-names = "apb_pclk", "atclk"; 2879 2880 in-ports { 2881 #address-cells = <1>; 2882 #size-cells = <0>; 2883 2884 port@0 { 2885 reg = <0>; 2886 apss_funnel0_in0: endpoint { 2887 remote-endpoint = <&etm0_out>; 2888 }; 2889 }; 2890 2891 port@1 { 2892 reg = <1>; 2893 apss_funnel0_in1: endpoint { 2894 remote-endpoint = <&etm1_out>; 2895 }; 2896 }; 2897 }; 2898 2899 out-ports { 2900 port { 2901 apss_funnel0_out: endpoint { 2902 remote-endpoint = 2903 <&apss_merge_funnel_in0>; 2904 }; 2905 }; 2906 }; 2907 }; 2908 2909 debug@3a10000 { 2910 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2911 reg = <0x3a10000 0x1000>; 2912 2913 clocks = <&rpmcc RPM_QDSS_CLK>; 2914 clock-names = "apb_pclk"; 2915 2916 cpu = <&CPU2>; 2917 }; 2918 2919 etm@3a40000 { 2920 compatible = "arm,coresight-etm4x", "arm,primecell"; 2921 reg = <0x3a40000 0x1000>; 2922 2923 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2924 clock-names = "apb_pclk", "atclk"; 2925 2926 cpu = <&CPU2>; 2927 2928 out-ports { 2929 port { 2930 etm2_out: endpoint { 2931 remote-endpoint = 2932 <&apss_funnel1_in0>; 2933 }; 2934 }; 2935 }; 2936 }; 2937 2938 debug@3b10000 { 2939 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2940 reg = <0x3b10000 0x1000>; 2941 2942 clocks = <&rpmcc RPM_QDSS_CLK>; 2943 clock-names = "apb_pclk"; 2944 2945 cpu = <&CPU3>; 2946 }; 2947 2948 etm@3b40000 { 2949 compatible = "arm,coresight-etm4x", "arm,primecell"; 2950 reg = <0x3b40000 0x1000>; 2951 2952 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2953 clock-names = "apb_pclk", "atclk"; 2954 2955 cpu = <&CPU3>; 2956 2957 out-ports { 2958 port { 2959 etm3_out: endpoint { 2960 remote-endpoint = 2961 <&apss_funnel1_in1>; 2962 }; 2963 }; 2964 }; 2965 }; 2966 2967 funnel@3bb0000 { /* APSS Funnel 1 */ 2968 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2969 reg = <0x3bb0000 0x1000>; 2970 2971 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2972 clock-names = "apb_pclk", "atclk"; 2973 2974 in-ports { 2975 #address-cells = <1>; 2976 #size-cells = <0>; 2977 2978 port@0 { 2979 reg = <0>; 2980 apss_funnel1_in0: endpoint { 2981 remote-endpoint = <&etm2_out>; 2982 }; 2983 }; 2984 2985 port@1 { 2986 reg = <1>; 2987 apss_funnel1_in1: endpoint { 2988 remote-endpoint = <&etm3_out>; 2989 }; 2990 }; 2991 }; 2992 2993 out-ports { 2994 port { 2995 apss_funnel1_out: endpoint { 2996 remote-endpoint = 2997 <&apss_merge_funnel_in1>; 2998 }; 2999 }; 3000 }; 3001 }; 3002 3003 funnel@3bc0000 { 3004 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3005 reg = <0x3bc0000 0x1000>; 3006 3007 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 3008 clock-names = "apb_pclk", "atclk"; 3009 3010 in-ports { 3011 #address-cells = <1>; 3012 #size-cells = <0>; 3013 3014 port@0 { 3015 reg = <0>; 3016 apss_merge_funnel_in0: endpoint { 3017 remote-endpoint = 3018 <&apss_funnel0_out>; 3019 }; 3020 }; 3021 3022 port@1 { 3023 reg = <1>; 3024 apss_merge_funnel_in1: endpoint { 3025 remote-endpoint = 3026 <&apss_funnel1_out>; 3027 }; 3028 }; 3029 }; 3030 3031 out-ports { 3032 port { 3033 apss_merge_funnel_out: endpoint { 3034 remote-endpoint = 3035 <&funnel1_in>; 3036 }; 3037 }; 3038 }; 3039 }; 3040 3041 kryocc: clock-controller@6400000 { 3042 compatible = "qcom,msm8996-apcc"; 3043 reg = <0x06400000 0x90000>; 3044 3045 clock-names = "xo", "sys_apcs_aux"; 3046 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3047 3048 #clock-cells = <1>; 3049 }; 3050 3051 usb3: usb@6af8800 { 3052 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3053 reg = <0x06af8800 0x400>; 3054 #address-cells = <1>; 3055 #size-cells = <1>; 3056 ranges; 3057 3058 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 3059 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 3060 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 3061 3062 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 3063 <&gcc GCC_USB30_MASTER_CLK>, 3064 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 3065 <&gcc GCC_USB30_SLEEP_CLK>, 3066 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 3067 clock-names = "cfg_noc", 3068 "core", 3069 "iface", 3070 "sleep", 3071 "mock_utmi"; 3072 3073 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 3074 <&gcc GCC_USB30_MASTER_CLK>; 3075 assigned-clock-rates = <19200000>, <120000000>; 3076 3077 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 3078 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 3079 interconnect-names = "usb-ddr", "apps-usb"; 3080 3081 power-domains = <&gcc USB30_GDSC>; 3082 status = "disabled"; 3083 3084 usb3_dwc3: usb@6a00000 { 3085 compatible = "snps,dwc3"; 3086 reg = <0x06a00000 0xcc00>; 3087 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 3088 phys = <&hsusb_phy1>, <&usb3phy>; 3089 phy-names = "usb2-phy", "usb3-phy"; 3090 snps,hird-threshold = /bits/ 8 <0>; 3091 snps,dis_u2_susphy_quirk; 3092 snps,dis_enblslpm_quirk; 3093 snps,is-utmi-l1-suspend; 3094 tx-fifo-resize; 3095 }; 3096 }; 3097 3098 usb3phy: phy@7410000 { 3099 compatible = "qcom,msm8996-qmp-usb3-phy"; 3100 reg = <0x07410000 0x1000>; 3101 3102 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 3103 <&gcc GCC_USB3_CLKREF_CLK>, 3104 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3105 <&gcc GCC_USB3_PHY_PIPE_CLK>; 3106 clock-names = "aux", 3107 "ref", 3108 "cfg_ahb", 3109 "pipe"; 3110 clock-output-names = "usb3_phy_pipe_clk_src"; 3111 #clock-cells = <0>; 3112 #phy-cells = <0>; 3113 3114 resets = <&gcc GCC_USB3_PHY_BCR>, 3115 <&gcc GCC_USB3PHY_PHY_BCR>; 3116 reset-names = "phy", 3117 "phy_phy"; 3118 3119 status = "disabled"; 3120 }; 3121 3122 hsusb_phy1: phy@7411000 { 3123 compatible = "qcom,msm8996-qusb2-phy"; 3124 reg = <0x07411000 0x180>; 3125 #phy-cells = <0>; 3126 3127 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3128 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3129 clock-names = "cfg_ahb", "ref"; 3130 3131 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3132 nvmem-cells = <&qusb2p_hstx_trim>; 3133 status = "disabled"; 3134 }; 3135 3136 hsusb_phy2: phy@7412000 { 3137 compatible = "qcom,msm8996-qusb2-phy"; 3138 reg = <0x07412000 0x180>; 3139 #phy-cells = <0>; 3140 3141 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3142 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3143 clock-names = "cfg_ahb", "ref"; 3144 3145 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3146 nvmem-cells = <&qusb2s_hstx_trim>; 3147 status = "disabled"; 3148 }; 3149 3150 sdhc1: mmc@7464900 { 3151 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3152 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3153 reg-names = "hc", "core"; 3154 3155 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3157 interrupt-names = "hc_irq", "pwr_irq"; 3158 3159 clock-names = "iface", "core", "xo"; 3160 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3161 <&gcc GCC_SDCC1_APPS_CLK>, 3162 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3163 resets = <&gcc GCC_SDCC1_BCR>; 3164 3165 pinctrl-names = "default", "sleep"; 3166 pinctrl-0 = <&sdc1_state_on>; 3167 pinctrl-1 = <&sdc1_state_off>; 3168 3169 bus-width = <8>; 3170 non-removable; 3171 status = "disabled"; 3172 }; 3173 3174 sdhc2: mmc@74a4900 { 3175 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3176 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3177 reg-names = "hc", "core"; 3178 3179 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3181 interrupt-names = "hc_irq", "pwr_irq"; 3182 3183 clock-names = "iface", "core", "xo"; 3184 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3185 <&gcc GCC_SDCC2_APPS_CLK>, 3186 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3187 resets = <&gcc GCC_SDCC2_BCR>; 3188 3189 pinctrl-names = "default", "sleep"; 3190 pinctrl-0 = <&sdc2_state_on>; 3191 pinctrl-1 = <&sdc2_state_off>; 3192 3193 bus-width = <4>; 3194 status = "disabled"; 3195 }; 3196 3197 blsp1_dma: dma-controller@7544000 { 3198 compatible = "qcom,bam-v1.7.0"; 3199 reg = <0x07544000 0x2b000>; 3200 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3201 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3202 clock-names = "bam_clk"; 3203 qcom,controlled-remotely; 3204 #dma-cells = <1>; 3205 qcom,ee = <0>; 3206 }; 3207 3208 blsp1_uart2: serial@7570000 { 3209 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3210 reg = <0x07570000 0x1000>; 3211 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3212 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3213 <&gcc GCC_BLSP1_AHB_CLK>; 3214 clock-names = "core", "iface"; 3215 pinctrl-names = "default", "sleep"; 3216 pinctrl-0 = <&blsp1_uart2_default>; 3217 pinctrl-1 = <&blsp1_uart2_sleep>; 3218 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3219 dma-names = "tx", "rx"; 3220 status = "disabled"; 3221 }; 3222 3223 blsp1_spi1: spi@7575000 { 3224 compatible = "qcom,spi-qup-v2.2.1"; 3225 reg = <0x07575000 0x600>; 3226 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3227 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3228 <&gcc GCC_BLSP1_AHB_CLK>; 3229 clock-names = "core", "iface"; 3230 pinctrl-names = "default", "sleep"; 3231 pinctrl-0 = <&blsp1_spi1_default>; 3232 pinctrl-1 = <&blsp1_spi1_sleep>; 3233 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3234 dma-names = "tx", "rx"; 3235 #address-cells = <1>; 3236 #size-cells = <0>; 3237 status = "disabled"; 3238 }; 3239 3240 blsp1_i2c3: i2c@7577000 { 3241 compatible = "qcom,i2c-qup-v2.2.1"; 3242 reg = <0x07577000 0x1000>; 3243 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3244 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3245 <&gcc GCC_BLSP1_AHB_CLK>; 3246 clock-names = "core", "iface"; 3247 pinctrl-names = "default", "sleep"; 3248 pinctrl-0 = <&blsp1_i2c3_default>; 3249 pinctrl-1 = <&blsp1_i2c3_sleep>; 3250 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3251 dma-names = "tx", "rx"; 3252 #address-cells = <1>; 3253 #size-cells = <0>; 3254 status = "disabled"; 3255 }; 3256 3257 blsp1_i2c6: i2c@757a000 { 3258 compatible = "qcom,i2c-qup-v2.2.1"; 3259 reg = <0x757a000 0x1000>; 3260 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3261 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 3262 <&gcc GCC_BLSP1_AHB_CLK>; 3263 clock-names = "core", "iface"; 3264 pinctrl-names = "default", "sleep"; 3265 pinctrl-0 = <&blsp1_i2c6_default>; 3266 pinctrl-1 = <&blsp1_i2c6_sleep>; 3267 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 3268 dma-names = "tx", "rx"; 3269 #address-cells = <1>; 3270 #size-cells = <0>; 3271 status = "disabled"; 3272 }; 3273 3274 blsp2_dma: dma-controller@7584000 { 3275 compatible = "qcom,bam-v1.7.0"; 3276 reg = <0x07584000 0x2b000>; 3277 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3278 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3279 clock-names = "bam_clk"; 3280 qcom,controlled-remotely; 3281 #dma-cells = <1>; 3282 qcom,ee = <0>; 3283 }; 3284 3285 blsp2_uart2: serial@75b0000 { 3286 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3287 reg = <0x075b0000 0x1000>; 3288 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3289 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3290 <&gcc GCC_BLSP2_AHB_CLK>; 3291 clock-names = "core", "iface"; 3292 status = "disabled"; 3293 }; 3294 3295 blsp2_uart3: serial@75b1000 { 3296 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3297 reg = <0x075b1000 0x1000>; 3298 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3299 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3300 <&gcc GCC_BLSP2_AHB_CLK>; 3301 clock-names = "core", "iface"; 3302 status = "disabled"; 3303 }; 3304 3305 blsp2_i2c1: i2c@75b5000 { 3306 compatible = "qcom,i2c-qup-v2.2.1"; 3307 reg = <0x075b5000 0x1000>; 3308 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3309 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3310 <&gcc GCC_BLSP2_AHB_CLK>; 3311 clock-names = "core", "iface"; 3312 pinctrl-names = "default", "sleep"; 3313 pinctrl-0 = <&blsp2_i2c1_default>; 3314 pinctrl-1 = <&blsp2_i2c1_sleep>; 3315 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3316 dma-names = "tx", "rx"; 3317 #address-cells = <1>; 3318 #size-cells = <0>; 3319 status = "disabled"; 3320 }; 3321 3322 blsp2_i2c2: i2c@75b6000 { 3323 compatible = "qcom,i2c-qup-v2.2.1"; 3324 reg = <0x075b6000 0x1000>; 3325 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3326 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3327 <&gcc GCC_BLSP2_AHB_CLK>; 3328 clock-names = "core", "iface"; 3329 pinctrl-names = "default", "sleep"; 3330 pinctrl-0 = <&blsp2_i2c2_default>; 3331 pinctrl-1 = <&blsp2_i2c2_sleep>; 3332 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3333 dma-names = "tx", "rx"; 3334 #address-cells = <1>; 3335 #size-cells = <0>; 3336 status = "disabled"; 3337 }; 3338 3339 blsp2_i2c3: i2c@75b7000 { 3340 compatible = "qcom,i2c-qup-v2.2.1"; 3341 reg = <0x075b7000 0x1000>; 3342 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3343 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3344 <&gcc GCC_BLSP2_AHB_CLK>; 3345 clock-names = "core", "iface"; 3346 clock-frequency = <400000>; 3347 pinctrl-names = "default", "sleep"; 3348 pinctrl-0 = <&blsp2_i2c3_default>; 3349 pinctrl-1 = <&blsp2_i2c3_sleep>; 3350 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3351 dma-names = "tx", "rx"; 3352 #address-cells = <1>; 3353 #size-cells = <0>; 3354 status = "disabled"; 3355 }; 3356 3357 blsp2_i2c5: i2c@75b9000 { 3358 compatible = "qcom,i2c-qup-v2.2.1"; 3359 reg = <0x75b9000 0x1000>; 3360 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3361 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3362 <&gcc GCC_BLSP2_AHB_CLK>; 3363 clock-names = "core", "iface"; 3364 pinctrl-names = "default"; 3365 pinctrl-0 = <&blsp2_i2c5_default>; 3366 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3367 dma-names = "tx", "rx"; 3368 #address-cells = <1>; 3369 #size-cells = <0>; 3370 status = "disabled"; 3371 }; 3372 3373 blsp2_i2c6: i2c@75ba000 { 3374 compatible = "qcom,i2c-qup-v2.2.1"; 3375 reg = <0x75ba000 0x1000>; 3376 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3377 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3378 <&gcc GCC_BLSP2_AHB_CLK>; 3379 clock-names = "core", "iface"; 3380 pinctrl-names = "default", "sleep"; 3381 pinctrl-0 = <&blsp2_i2c6_default>; 3382 pinctrl-1 = <&blsp2_i2c6_sleep>; 3383 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3384 dma-names = "tx", "rx"; 3385 #address-cells = <1>; 3386 #size-cells = <0>; 3387 status = "disabled"; 3388 }; 3389 3390 blsp2_spi6: spi@75ba000 { 3391 compatible = "qcom,spi-qup-v2.2.1"; 3392 reg = <0x075ba000 0x600>; 3393 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3394 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3395 <&gcc GCC_BLSP2_AHB_CLK>; 3396 clock-names = "core", "iface"; 3397 pinctrl-names = "default", "sleep"; 3398 pinctrl-0 = <&blsp2_spi6_default>; 3399 pinctrl-1 = <&blsp2_spi6_sleep>; 3400 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3401 dma-names = "tx", "rx"; 3402 #address-cells = <1>; 3403 #size-cells = <0>; 3404 status = "disabled"; 3405 }; 3406 3407 usb2: usb@76f8800 { 3408 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3409 reg = <0x076f8800 0x400>; 3410 #address-cells = <1>; 3411 #size-cells = <1>; 3412 ranges; 3413 3414 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 3417 interrupt-names = "pwr_event", 3418 "qusb2_phy", 3419 "hs_phy_irq"; 3420 3421 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3422 <&gcc GCC_USB20_MASTER_CLK>, 3423 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3424 <&gcc GCC_USB20_SLEEP_CLK>, 3425 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3426 clock-names = "cfg_noc", 3427 "core", 3428 "iface", 3429 "sleep", 3430 "mock_utmi"; 3431 3432 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3433 <&gcc GCC_USB20_MASTER_CLK>; 3434 assigned-clock-rates = <19200000>, <60000000>; 3435 3436 power-domains = <&gcc USB30_GDSC>; 3437 qcom,select-utmi-as-pipe-clk; 3438 status = "disabled"; 3439 3440 usb2_dwc3: usb@7600000 { 3441 compatible = "snps,dwc3"; 3442 reg = <0x07600000 0xcc00>; 3443 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3444 phys = <&hsusb_phy2>; 3445 phy-names = "usb2-phy"; 3446 maximum-speed = "high-speed"; 3447 snps,dis_u2_susphy_quirk; 3448 snps,dis_enblslpm_quirk; 3449 }; 3450 }; 3451 3452 slimbam: dma-controller@9184000 { 3453 compatible = "qcom,bam-v1.7.0"; 3454 qcom,controlled-remotely; 3455 reg = <0x09184000 0x32000>; 3456 num-channels = <31>; 3457 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 3458 #dma-cells = <1>; 3459 qcom,ee = <1>; 3460 qcom,num-ees = <2>; 3461 }; 3462 3463 slim_msm: slim-ngd@91c0000 { 3464 compatible = "qcom,slim-ngd-v1.5.0"; 3465 reg = <0x091c0000 0x2c000>; 3466 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3467 dmas = <&slimbam 3>, <&slimbam 4>; 3468 dma-names = "rx", "tx"; 3469 #address-cells = <1>; 3470 #size-cells = <0>; 3471 3472 status = "disabled"; 3473 }; 3474 3475 adsp_pil: remoteproc@9300000 { 3476 compatible = "qcom,msm8996-adsp-pil"; 3477 reg = <0x09300000 0x80000>; 3478 3479 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3480 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3481 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3482 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3483 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3484 interrupt-names = "wdog", "fatal", "ready", 3485 "handover", "stop-ack"; 3486 3487 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3488 clock-names = "xo"; 3489 3490 memory-region = <&adsp_mem>; 3491 3492 qcom,smem-states = <&adsp_smp2p_out 0>; 3493 qcom,smem-state-names = "stop"; 3494 3495 power-domains = <&rpmpd MSM8996_VDDCX>; 3496 power-domain-names = "cx"; 3497 3498 status = "disabled"; 3499 3500 smd-edge { 3501 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3502 3503 label = "lpass"; 3504 mboxes = <&apcs_glb 8>; 3505 qcom,smd-edge = <1>; 3506 qcom,remote-pid = <2>; 3507 3508 apr { 3509 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3510 compatible = "qcom,apr-v2"; 3511 qcom,smd-channels = "apr_audio_svc"; 3512 qcom,domain = <APR_DOMAIN_ADSP>; 3513 #address-cells = <1>; 3514 #size-cells = <0>; 3515 3516 service@3 { 3517 reg = <APR_SVC_ADSP_CORE>; 3518 compatible = "qcom,q6core"; 3519 }; 3520 3521 q6afe: service@4 { 3522 compatible = "qcom,q6afe"; 3523 reg = <APR_SVC_AFE>; 3524 q6afedai: dais { 3525 compatible = "qcom,q6afe-dais"; 3526 #address-cells = <1>; 3527 #size-cells = <0>; 3528 #sound-dai-cells = <1>; 3529 dai@1 { 3530 reg = <1>; 3531 }; 3532 }; 3533 }; 3534 3535 q6asm: service@7 { 3536 compatible = "qcom,q6asm"; 3537 reg = <APR_SVC_ASM>; 3538 q6asmdai: dais { 3539 compatible = "qcom,q6asm-dais"; 3540 #address-cells = <1>; 3541 #size-cells = <0>; 3542 #sound-dai-cells = <1>; 3543 iommus = <&lpass_q6_smmu 1>; 3544 }; 3545 }; 3546 3547 q6adm: service@8 { 3548 compatible = "qcom,q6adm"; 3549 reg = <APR_SVC_ADM>; 3550 q6routing: routing { 3551 compatible = "qcom,q6adm-routing"; 3552 #sound-dai-cells = <0>; 3553 }; 3554 }; 3555 }; 3556 }; 3557 }; 3558 3559 apcs_glb: mailbox@9820000 { 3560 compatible = "qcom,msm8996-apcs-hmss-global"; 3561 reg = <0x09820000 0x1000>; 3562 3563 #mbox-cells = <1>; 3564 #clock-cells = <0>; 3565 }; 3566 3567 timer@9840000 { 3568 #address-cells = <1>; 3569 #size-cells = <1>; 3570 ranges; 3571 compatible = "arm,armv7-timer-mem"; 3572 reg = <0x09840000 0x1000>; 3573 clock-frequency = <19200000>; 3574 3575 frame@9850000 { 3576 frame-number = <0>; 3577 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3578 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3579 reg = <0x09850000 0x1000>, 3580 <0x09860000 0x1000>; 3581 }; 3582 3583 frame@9870000 { 3584 frame-number = <1>; 3585 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3586 reg = <0x09870000 0x1000>; 3587 status = "disabled"; 3588 }; 3589 3590 frame@9880000 { 3591 frame-number = <2>; 3592 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3593 reg = <0x09880000 0x1000>; 3594 status = "disabled"; 3595 }; 3596 3597 frame@9890000 { 3598 frame-number = <3>; 3599 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3600 reg = <0x09890000 0x1000>; 3601 status = "disabled"; 3602 }; 3603 3604 frame@98a0000 { 3605 frame-number = <4>; 3606 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3607 reg = <0x098a0000 0x1000>; 3608 status = "disabled"; 3609 }; 3610 3611 frame@98b0000 { 3612 frame-number = <5>; 3613 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3614 reg = <0x098b0000 0x1000>; 3615 status = "disabled"; 3616 }; 3617 3618 frame@98c0000 { 3619 frame-number = <6>; 3620 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3621 reg = <0x098c0000 0x1000>; 3622 status = "disabled"; 3623 }; 3624 }; 3625 3626 saw3: syscon@9a10000 { 3627 compatible = "syscon"; 3628 reg = <0x09a10000 0x1000>; 3629 }; 3630 3631 cbf: clock-controller@9a11000 { 3632 compatible = "qcom,msm8996-cbf"; 3633 reg = <0x09a11000 0x10000>; 3634 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3635 #clock-cells = <0>; 3636 #interconnect-cells = <1>; 3637 }; 3638 3639 intc: interrupt-controller@9bc0000 { 3640 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3641 #interrupt-cells = <3>; 3642 interrupt-controller; 3643 #redistributor-regions = <1>; 3644 redistributor-stride = <0x0 0x40000>; 3645 reg = <0x09bc0000 0x10000>, 3646 <0x09c00000 0x100000>; 3647 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3648 }; 3649 }; 3650 3651 sound: sound { 3652 }; 3653 3654 thermal-zones { 3655 cpu0-thermal { 3656 polling-delay-passive = <250>; 3657 polling-delay = <1000>; 3658 3659 thermal-sensors = <&tsens0 3>; 3660 3661 trips { 3662 cpu0_alert0: trip-point0 { 3663 temperature = <75000>; 3664 hysteresis = <2000>; 3665 type = "passive"; 3666 }; 3667 3668 cpu0_crit: cpu-crit { 3669 temperature = <110000>; 3670 hysteresis = <2000>; 3671 type = "critical"; 3672 }; 3673 }; 3674 }; 3675 3676 cpu1-thermal { 3677 polling-delay-passive = <250>; 3678 polling-delay = <1000>; 3679 3680 thermal-sensors = <&tsens0 5>; 3681 3682 trips { 3683 cpu1_alert0: trip-point0 { 3684 temperature = <75000>; 3685 hysteresis = <2000>; 3686 type = "passive"; 3687 }; 3688 3689 cpu1_crit: cpu-crit { 3690 temperature = <110000>; 3691 hysteresis = <2000>; 3692 type = "critical"; 3693 }; 3694 }; 3695 }; 3696 3697 cpu2-thermal { 3698 polling-delay-passive = <250>; 3699 polling-delay = <1000>; 3700 3701 thermal-sensors = <&tsens0 8>; 3702 3703 trips { 3704 cpu2_alert0: trip-point0 { 3705 temperature = <75000>; 3706 hysteresis = <2000>; 3707 type = "passive"; 3708 }; 3709 3710 cpu2_crit: cpu-crit { 3711 temperature = <110000>; 3712 hysteresis = <2000>; 3713 type = "critical"; 3714 }; 3715 }; 3716 }; 3717 3718 cpu3-thermal { 3719 polling-delay-passive = <250>; 3720 polling-delay = <1000>; 3721 3722 thermal-sensors = <&tsens0 10>; 3723 3724 trips { 3725 cpu3_alert0: trip-point0 { 3726 temperature = <75000>; 3727 hysteresis = <2000>; 3728 type = "passive"; 3729 }; 3730 3731 cpu3_crit: cpu-crit { 3732 temperature = <110000>; 3733 hysteresis = <2000>; 3734 type = "critical"; 3735 }; 3736 }; 3737 }; 3738 3739 gpu-top-thermal { 3740 polling-delay-passive = <250>; 3741 polling-delay = <1000>; 3742 3743 thermal-sensors = <&tsens1 6>; 3744 3745 trips { 3746 gpu1_alert0: trip-point0 { 3747 temperature = <90000>; 3748 hysteresis = <2000>; 3749 type = "passive"; 3750 }; 3751 }; 3752 3753 cooling-maps { 3754 map0 { 3755 trip = <&gpu1_alert0>; 3756 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3757 }; 3758 }; 3759 }; 3760 3761 gpu-bottom-thermal { 3762 polling-delay-passive = <250>; 3763 polling-delay = <1000>; 3764 3765 thermal-sensors = <&tsens1 7>; 3766 3767 trips { 3768 gpu2_alert0: trip-point0 { 3769 temperature = <90000>; 3770 hysteresis = <2000>; 3771 type = "passive"; 3772 }; 3773 }; 3774 3775 cooling-maps { 3776 map0 { 3777 trip = <&gpu2_alert0>; 3778 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3779 }; 3780 }; 3781 }; 3782 3783 m4m-thermal { 3784 polling-delay-passive = <250>; 3785 polling-delay = <1000>; 3786 3787 thermal-sensors = <&tsens0 1>; 3788 3789 trips { 3790 m4m_alert0: trip-point0 { 3791 temperature = <90000>; 3792 hysteresis = <2000>; 3793 type = "hot"; 3794 }; 3795 }; 3796 }; 3797 3798 l3-or-venus-thermal { 3799 polling-delay-passive = <250>; 3800 polling-delay = <1000>; 3801 3802 thermal-sensors = <&tsens0 2>; 3803 3804 trips { 3805 l3_or_venus_alert0: trip-point0 { 3806 temperature = <90000>; 3807 hysteresis = <2000>; 3808 type = "hot"; 3809 }; 3810 }; 3811 }; 3812 3813 cluster0-l2-thermal { 3814 polling-delay-passive = <250>; 3815 polling-delay = <1000>; 3816 3817 thermal-sensors = <&tsens0 7>; 3818 3819 trips { 3820 cluster0_l2_alert0: trip-point0 { 3821 temperature = <90000>; 3822 hysteresis = <2000>; 3823 type = "hot"; 3824 }; 3825 }; 3826 }; 3827 3828 cluster1-l2-thermal { 3829 polling-delay-passive = <250>; 3830 polling-delay = <1000>; 3831 3832 thermal-sensors = <&tsens0 12>; 3833 3834 trips { 3835 cluster1_l2_alert0: trip-point0 { 3836 temperature = <90000>; 3837 hysteresis = <2000>; 3838 type = "hot"; 3839 }; 3840 }; 3841 }; 3842 3843 camera-thermal { 3844 polling-delay-passive = <250>; 3845 polling-delay = <1000>; 3846 3847 thermal-sensors = <&tsens1 1>; 3848 3849 trips { 3850 camera_alert0: trip-point0 { 3851 temperature = <90000>; 3852 hysteresis = <2000>; 3853 type = "hot"; 3854 }; 3855 }; 3856 }; 3857 3858 q6-dsp-thermal { 3859 polling-delay-passive = <250>; 3860 polling-delay = <1000>; 3861 3862 thermal-sensors = <&tsens1 2>; 3863 3864 trips { 3865 q6_dsp_alert0: trip-point0 { 3866 temperature = <90000>; 3867 hysteresis = <2000>; 3868 type = "hot"; 3869 }; 3870 }; 3871 }; 3872 3873 mem-thermal { 3874 polling-delay-passive = <250>; 3875 polling-delay = <1000>; 3876 3877 thermal-sensors = <&tsens1 3>; 3878 3879 trips { 3880 mem_alert0: trip-point0 { 3881 temperature = <90000>; 3882 hysteresis = <2000>; 3883 type = "hot"; 3884 }; 3885 }; 3886 }; 3887 3888 modemtx-thermal { 3889 polling-delay-passive = <250>; 3890 polling-delay = <1000>; 3891 3892 thermal-sensors = <&tsens1 4>; 3893 3894 trips { 3895 modemtx_alert0: trip-point0 { 3896 temperature = <90000>; 3897 hysteresis = <2000>; 3898 type = "hot"; 3899 }; 3900 }; 3901 }; 3902 }; 3903 3904 timer { 3905 compatible = "arm,armv8-timer"; 3906 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3907 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3908 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3909 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3910 }; 3911}; 3912