1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8996.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/interconnect/qcom,msm8996.h> 11#include <dt-bindings/interconnect/qcom,msm8996-cbf.h> 12#include <dt-bindings/firmware/qcom,scm.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,apr.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <19200000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32764>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "qcom,kryo"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 cpu-idle-states = <&CPU_SLEEP_0>; 52 capacity-dmips-mhz = <1024>; 53 clocks = <&kryocc 0>; 54 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 55 operating-points-v2 = <&cluster0_opp>; 56 #cooling-cells = <2>; 57 next-level-cache = <&L2_0>; 58 L2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 }; 63 }; 64 65 CPU1: cpu@1 { 66 device_type = "cpu"; 67 compatible = "qcom,kryo"; 68 reg = <0x0 0x1>; 69 enable-method = "psci"; 70 cpu-idle-states = <&CPU_SLEEP_0>; 71 capacity-dmips-mhz = <1024>; 72 clocks = <&kryocc 0>; 73 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 74 operating-points-v2 = <&cluster0_opp>; 75 #cooling-cells = <2>; 76 next-level-cache = <&L2_0>; 77 }; 78 79 CPU2: cpu@100 { 80 device_type = "cpu"; 81 compatible = "qcom,kryo"; 82 reg = <0x0 0x100>; 83 enable-method = "psci"; 84 cpu-idle-states = <&CPU_SLEEP_0>; 85 capacity-dmips-mhz = <1024>; 86 clocks = <&kryocc 1>; 87 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 88 operating-points-v2 = <&cluster1_opp>; 89 #cooling-cells = <2>; 90 next-level-cache = <&L2_1>; 91 L2_1: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 cache-unified; 95 }; 96 }; 97 98 CPU3: cpu@101 { 99 device_type = "cpu"; 100 compatible = "qcom,kryo"; 101 reg = <0x0 0x101>; 102 enable-method = "psci"; 103 cpu-idle-states = <&CPU_SLEEP_0>; 104 capacity-dmips-mhz = <1024>; 105 clocks = <&kryocc 1>; 106 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 107 operating-points-v2 = <&cluster1_opp>; 108 #cooling-cells = <2>; 109 next-level-cache = <&L2_1>; 110 }; 111 112 cpu-map { 113 cluster0 { 114 core0 { 115 cpu = <&CPU0>; 116 }; 117 118 core1 { 119 cpu = <&CPU1>; 120 }; 121 }; 122 123 cluster1 { 124 core0 { 125 cpu = <&CPU2>; 126 }; 127 128 core1 { 129 cpu = <&CPU3>; 130 }; 131 }; 132 }; 133 134 idle-states { 135 entry-method = "psci"; 136 137 CPU_SLEEP_0: cpu-sleep-0 { 138 compatible = "arm,idle-state"; 139 idle-state-name = "standalone-power-collapse"; 140 arm,psci-suspend-param = <0x00000004>; 141 entry-latency-us = <130>; 142 exit-latency-us = <80>; 143 min-residency-us = <300>; 144 }; 145 }; 146 }; 147 148 cluster0_opp: opp-table-cluster0 { 149 compatible = "operating-points-v2-kryo-cpu"; 150 nvmem-cells = <&speedbin_efuse>; 151 opp-shared; 152 153 /* Nominal fmax for now */ 154 opp-307200000 { 155 opp-hz = /bits/ 64 <307200000>; 156 opp-supported-hw = <0xf>; 157 clock-latency-ns = <200000>; 158 opp-peak-kBps = <307200>; 159 }; 160 opp-422400000 { 161 opp-hz = /bits/ 64 <422400000>; 162 opp-supported-hw = <0xf>; 163 clock-latency-ns = <200000>; 164 opp-peak-kBps = <307200>; 165 }; 166 opp-480000000 { 167 opp-hz = /bits/ 64 <480000000>; 168 opp-supported-hw = <0xf>; 169 clock-latency-ns = <200000>; 170 opp-peak-kBps = <307200>; 171 }; 172 opp-556800000 { 173 opp-hz = /bits/ 64 <556800000>; 174 opp-supported-hw = <0xf>; 175 clock-latency-ns = <200000>; 176 opp-peak-kBps = <307200>; 177 }; 178 opp-652800000 { 179 opp-hz = /bits/ 64 <652800000>; 180 opp-supported-hw = <0xf>; 181 clock-latency-ns = <200000>; 182 opp-peak-kBps = <384000>; 183 }; 184 opp-729600000 { 185 opp-hz = /bits/ 64 <729600000>; 186 opp-supported-hw = <0xf>; 187 clock-latency-ns = <200000>; 188 opp-peak-kBps = <460800>; 189 }; 190 opp-844800000 { 191 opp-hz = /bits/ 64 <844800000>; 192 opp-supported-hw = <0xf>; 193 clock-latency-ns = <200000>; 194 opp-peak-kBps = <537600>; 195 }; 196 opp-960000000 { 197 opp-hz = /bits/ 64 <960000000>; 198 opp-supported-hw = <0xf>; 199 clock-latency-ns = <200000>; 200 opp-peak-kBps = <672000>; 201 }; 202 opp-1036800000 { 203 opp-hz = /bits/ 64 <1036800000>; 204 opp-supported-hw = <0xf>; 205 clock-latency-ns = <200000>; 206 opp-peak-kBps = <672000>; 207 }; 208 opp-1113600000 { 209 opp-hz = /bits/ 64 <1113600000>; 210 opp-supported-hw = <0xf>; 211 clock-latency-ns = <200000>; 212 opp-peak-kBps = <825600>; 213 }; 214 opp-1190400000 { 215 opp-hz = /bits/ 64 <1190400000>; 216 opp-supported-hw = <0xf>; 217 clock-latency-ns = <200000>; 218 opp-peak-kBps = <825600>; 219 }; 220 opp-1228800000 { 221 opp-hz = /bits/ 64 <1228800000>; 222 opp-supported-hw = <0xf>; 223 clock-latency-ns = <200000>; 224 opp-peak-kBps = <902400>; 225 }; 226 opp-1324800000 { 227 opp-hz = /bits/ 64 <1324800000>; 228 opp-supported-hw = <0xd>; 229 clock-latency-ns = <200000>; 230 opp-peak-kBps = <1056000>; 231 }; 232 opp-1363200000 { 233 opp-hz = /bits/ 64 <1363200000>; 234 opp-supported-hw = <0x2>; 235 clock-latency-ns = <200000>; 236 opp-peak-kBps = <1132800>; 237 }; 238 opp-1401600000 { 239 opp-hz = /bits/ 64 <1401600000>; 240 opp-supported-hw = <0xd>; 241 clock-latency-ns = <200000>; 242 opp-peak-kBps = <1132800>; 243 }; 244 opp-1478400000 { 245 opp-hz = /bits/ 64 <1478400000>; 246 opp-supported-hw = <0x9>; 247 clock-latency-ns = <200000>; 248 opp-peak-kBps = <1190400>; 249 }; 250 opp-1497600000 { 251 opp-hz = /bits/ 64 <1497600000>; 252 opp-supported-hw = <0x04>; 253 clock-latency-ns = <200000>; 254 opp-peak-kBps = <1305600>; 255 }; 256 opp-1593600000 { 257 opp-hz = /bits/ 64 <1593600000>; 258 opp-supported-hw = <0x9>; 259 clock-latency-ns = <200000>; 260 opp-peak-kBps = <1382400>; 261 }; 262 }; 263 264 cluster1_opp: opp-table-cluster1 { 265 compatible = "operating-points-v2-kryo-cpu"; 266 nvmem-cells = <&speedbin_efuse>; 267 opp-shared; 268 269 /* Nominal fmax for now */ 270 opp-307200000 { 271 opp-hz = /bits/ 64 <307200000>; 272 opp-supported-hw = <0xf>; 273 clock-latency-ns = <200000>; 274 opp-peak-kBps = <307200>; 275 }; 276 opp-403200000 { 277 opp-hz = /bits/ 64 <403200000>; 278 opp-supported-hw = <0xf>; 279 clock-latency-ns = <200000>; 280 opp-peak-kBps = <307200>; 281 }; 282 opp-480000000 { 283 opp-hz = /bits/ 64 <480000000>; 284 opp-supported-hw = <0xf>; 285 clock-latency-ns = <200000>; 286 opp-peak-kBps = <307200>; 287 }; 288 opp-556800000 { 289 opp-hz = /bits/ 64 <556800000>; 290 opp-supported-hw = <0xf>; 291 clock-latency-ns = <200000>; 292 opp-peak-kBps = <307200>; 293 }; 294 opp-652800000 { 295 opp-hz = /bits/ 64 <652800000>; 296 opp-supported-hw = <0xf>; 297 clock-latency-ns = <200000>; 298 opp-peak-kBps = <307200>; 299 }; 300 opp-729600000 { 301 opp-hz = /bits/ 64 <729600000>; 302 opp-supported-hw = <0xf>; 303 clock-latency-ns = <200000>; 304 opp-peak-kBps = <307200>; 305 }; 306 opp-806400000 { 307 opp-hz = /bits/ 64 <806400000>; 308 opp-supported-hw = <0xf>; 309 clock-latency-ns = <200000>; 310 opp-peak-kBps = <384000>; 311 }; 312 opp-883200000 { 313 opp-hz = /bits/ 64 <883200000>; 314 opp-supported-hw = <0xf>; 315 clock-latency-ns = <200000>; 316 opp-peak-kBps = <460800>; 317 }; 318 opp-940800000 { 319 opp-hz = /bits/ 64 <940800000>; 320 opp-supported-hw = <0xf>; 321 clock-latency-ns = <200000>; 322 opp-peak-kBps = <537600>; 323 }; 324 opp-1036800000 { 325 opp-hz = /bits/ 64 <1036800000>; 326 opp-supported-hw = <0xf>; 327 clock-latency-ns = <200000>; 328 opp-peak-kBps = <595200>; 329 }; 330 opp-1113600000 { 331 opp-hz = /bits/ 64 <1113600000>; 332 opp-supported-hw = <0xf>; 333 clock-latency-ns = <200000>; 334 opp-peak-kBps = <672000>; 335 }; 336 opp-1190400000 { 337 opp-hz = /bits/ 64 <1190400000>; 338 opp-supported-hw = <0xf>; 339 clock-latency-ns = <200000>; 340 opp-peak-kBps = <672000>; 341 }; 342 opp-1248000000 { 343 opp-hz = /bits/ 64 <1248000000>; 344 opp-supported-hw = <0xf>; 345 clock-latency-ns = <200000>; 346 opp-peak-kBps = <748800>; 347 }; 348 opp-1324800000 { 349 opp-hz = /bits/ 64 <1324800000>; 350 opp-supported-hw = <0xf>; 351 clock-latency-ns = <200000>; 352 opp-peak-kBps = <825600>; 353 }; 354 opp-1401600000 { 355 opp-hz = /bits/ 64 <1401600000>; 356 opp-supported-hw = <0xf>; 357 clock-latency-ns = <200000>; 358 opp-peak-kBps = <902400>; 359 }; 360 opp-1478400000 { 361 opp-hz = /bits/ 64 <1478400000>; 362 opp-supported-hw = <0xf>; 363 clock-latency-ns = <200000>; 364 opp-peak-kBps = <979200>; 365 }; 366 opp-1555200000 { 367 opp-hz = /bits/ 64 <1555200000>; 368 opp-supported-hw = <0xf>; 369 clock-latency-ns = <200000>; 370 opp-peak-kBps = <1056000>; 371 }; 372 opp-1632000000 { 373 opp-hz = /bits/ 64 <1632000000>; 374 opp-supported-hw = <0xf>; 375 clock-latency-ns = <200000>; 376 opp-peak-kBps = <1190400>; 377 }; 378 opp-1708800000 { 379 opp-hz = /bits/ 64 <1708800000>; 380 opp-supported-hw = <0xf>; 381 clock-latency-ns = <200000>; 382 opp-peak-kBps = <1228800>; 383 }; 384 opp-1785600000 { 385 opp-hz = /bits/ 64 <1785600000>; 386 opp-supported-hw = <0xf>; 387 clock-latency-ns = <200000>; 388 opp-peak-kBps = <1305600>; 389 }; 390 opp-1804800000 { 391 opp-hz = /bits/ 64 <1804800000>; 392 opp-supported-hw = <0xe>; 393 clock-latency-ns = <200000>; 394 opp-peak-kBps = <1305600>; 395 }; 396 opp-1824000000 { 397 opp-hz = /bits/ 64 <1824000000>; 398 opp-supported-hw = <0x1>; 399 clock-latency-ns = <200000>; 400 opp-peak-kBps = <1382400>; 401 }; 402 opp-1900800000 { 403 opp-hz = /bits/ 64 <1900800000>; 404 opp-supported-hw = <0x4>; 405 clock-latency-ns = <200000>; 406 opp-peak-kBps = <1305600>; 407 }; 408 opp-1920000000 { 409 opp-hz = /bits/ 64 <1920000000>; 410 opp-supported-hw = <0x1>; 411 clock-latency-ns = <200000>; 412 opp-peak-kBps = <1459200>; 413 }; 414 opp-1996800000 { 415 opp-hz = /bits/ 64 <1996800000>; 416 opp-supported-hw = <0x1>; 417 clock-latency-ns = <200000>; 418 opp-peak-kBps = <1593600>; 419 }; 420 opp-2073600000 { 421 opp-hz = /bits/ 64 <2073600000>; 422 opp-supported-hw = <0x1>; 423 clock-latency-ns = <200000>; 424 opp-peak-kBps = <1593600>; 425 }; 426 opp-2150400000 { 427 opp-hz = /bits/ 64 <2150400000>; 428 opp-supported-hw = <0x1>; 429 clock-latency-ns = <200000>; 430 opp-peak-kBps = <1593600>; 431 }; 432 }; 433 434 firmware { 435 scm { 436 compatible = "qcom,scm-msm8996", "qcom,scm"; 437 qcom,dload-mode = <&tcsr_2 0x13000>; 438 }; 439 }; 440 441 memory@80000000 { 442 device_type = "memory"; 443 /* We expect the bootloader to fill in the reg */ 444 reg = <0x0 0x80000000 0x0 0x0>; 445 }; 446 447 etm { 448 compatible = "qcom,coresight-remote-etm"; 449 450 out-ports { 451 port { 452 modem_etm_out_funnel_in2: endpoint { 453 remote-endpoint = 454 <&funnel_in2_in_modem_etm>; 455 }; 456 }; 457 }; 458 }; 459 460 mpm: interrupt-controller { 461 compatible = "qcom,mpm"; 462 qcom,rpm-msg-ram = <&apss_mpm>; 463 interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>; 464 mboxes = <&apcs_glb 1>; 465 interrupt-controller; 466 #interrupt-cells = <2>; 467 #power-domain-cells = <0>; 468 interrupt-parent = <&intc>; 469 qcom,mpm-pin-count = <96>; 470 qcom,mpm-pin-map = <2 184>, /* TSENS1 upper_lower_int */ 471 <52 243>, /* DWC3_PRI ss_phy_irq */ 472 <79 347>, /* DWC3_PRI hs_phy_irq */ 473 <80 352>, /* DWC3_SEC hs_phy_irq */ 474 <81 347>, /* QUSB2_PHY_PRI DP+DM */ 475 <82 352>, /* QUSB2_PHY_SEC DP+DM */ 476 <87 326>; /* SPMI */ 477 }; 478 479 psci { 480 compatible = "arm,psci-1.0"; 481 method = "smc"; 482 }; 483 484 rpm: remoteproc { 485 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc"; 486 487 glink-edge { 488 compatible = "qcom,glink-rpm"; 489 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 490 qcom,rpm-msg-ram = <&rpm_msg_ram>; 491 mboxes = <&apcs_glb 0>; 492 493 rpm_requests: rpm-requests { 494 compatible = "qcom,rpm-msm8996"; 495 qcom,glink-channels = "rpm_requests"; 496 497 rpmcc: clock-controller { 498 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 499 #clock-cells = <1>; 500 clocks = <&xo_board>; 501 clock-names = "xo"; 502 }; 503 504 rpmpd: power-controller { 505 compatible = "qcom,msm8996-rpmpd"; 506 #power-domain-cells = <1>; 507 operating-points-v2 = <&rpmpd_opp_table>; 508 509 rpmpd_opp_table: opp-table { 510 compatible = "operating-points-v2"; 511 512 rpmpd_opp1: opp1 { 513 opp-level = <1>; 514 }; 515 516 rpmpd_opp2: opp2 { 517 opp-level = <2>; 518 }; 519 520 rpmpd_opp3: opp3 { 521 opp-level = <3>; 522 }; 523 524 rpmpd_opp4: opp4 { 525 opp-level = <4>; 526 }; 527 528 rpmpd_opp5: opp5 { 529 opp-level = <5>; 530 }; 531 532 rpmpd_opp6: opp6 { 533 opp-level = <6>; 534 }; 535 }; 536 }; 537 }; 538 }; 539 }; 540 541 reserved-memory { 542 #address-cells = <2>; 543 #size-cells = <2>; 544 ranges; 545 546 hyp_mem: memory@85800000 { 547 reg = <0x0 0x85800000 0x0 0x600000>; 548 no-map; 549 }; 550 551 xbl_mem: memory@85e00000 { 552 reg = <0x0 0x85e00000 0x0 0x200000>; 553 no-map; 554 }; 555 556 smem_mem: smem-mem@86000000 { 557 reg = <0x0 0x86000000 0x0 0x200000>; 558 no-map; 559 }; 560 561 tz_mem: memory@86200000 { 562 reg = <0x0 0x86200000 0x0 0x2600000>; 563 no-map; 564 }; 565 566 rmtfs_mem: rmtfs { 567 compatible = "qcom,rmtfs-mem"; 568 569 size = <0x0 0x200000>; 570 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 571 no-map; 572 573 qcom,client-id = <1>; 574 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 575 }; 576 577 mpss_mem: mpss@88800000 { 578 reg = <0x0 0x88800000 0x0 0x6200000>; 579 no-map; 580 }; 581 582 adsp_mem: adsp@8ea00000 { 583 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 584 no-map; 585 }; 586 587 slpi_mem: slpi@90500000 { 588 reg = <0x0 0x90500000 0x0 0xa00000>; 589 no-map; 590 }; 591 592 gpu_mem: gpu@90f00000 { 593 compatible = "shared-dma-pool"; 594 reg = <0x0 0x90f00000 0x0 0x100000>; 595 no-map; 596 }; 597 598 venus_mem: venus@91000000 { 599 reg = <0x0 0x91000000 0x0 0x500000>; 600 no-map; 601 }; 602 603 mba_mem: mba@91500000 { 604 reg = <0x0 0x91500000 0x0 0x200000>; 605 no-map; 606 }; 607 608 mdata_mem: mpss-metadata { 609 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 610 size = <0x0 0x4000>; 611 no-map; 612 }; 613 }; 614 615 smem { 616 compatible = "qcom,smem"; 617 memory-region = <&smem_mem>; 618 hwlocks = <&tcsr_mutex 3>; 619 }; 620 621 smp2p-adsp { 622 compatible = "qcom,smp2p"; 623 qcom,smem = <443>, <429>; 624 625 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 626 627 mboxes = <&apcs_glb 10>; 628 629 qcom,local-pid = <0>; 630 qcom,remote-pid = <2>; 631 632 adsp_smp2p_out: master-kernel { 633 qcom,entry-name = "master-kernel"; 634 #qcom,smem-state-cells = <1>; 635 }; 636 637 adsp_smp2p_in: slave-kernel { 638 qcom,entry-name = "slave-kernel"; 639 640 interrupt-controller; 641 #interrupt-cells = <2>; 642 }; 643 }; 644 645 smp2p-mpss { 646 compatible = "qcom,smp2p"; 647 qcom,smem = <435>, <428>; 648 649 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 650 651 mboxes = <&apcs_glb 14>; 652 653 qcom,local-pid = <0>; 654 qcom,remote-pid = <1>; 655 656 mpss_smp2p_out: master-kernel { 657 qcom,entry-name = "master-kernel"; 658 #qcom,smem-state-cells = <1>; 659 }; 660 661 mpss_smp2p_in: slave-kernel { 662 qcom,entry-name = "slave-kernel"; 663 664 interrupt-controller; 665 #interrupt-cells = <2>; 666 }; 667 }; 668 669 smp2p-slpi { 670 compatible = "qcom,smp2p"; 671 qcom,smem = <481>, <430>; 672 673 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 674 675 mboxes = <&apcs_glb 26>; 676 677 qcom,local-pid = <0>; 678 qcom,remote-pid = <3>; 679 680 slpi_smp2p_out: master-kernel { 681 qcom,entry-name = "master-kernel"; 682 #qcom,smem-state-cells = <1>; 683 }; 684 685 slpi_smp2p_in: slave-kernel { 686 qcom,entry-name = "slave-kernel"; 687 688 interrupt-controller; 689 #interrupt-cells = <2>; 690 }; 691 }; 692 693 soc: soc@0 { 694 #address-cells = <1>; 695 #size-cells = <1>; 696 ranges = <0 0 0 0xffffffff>; 697 compatible = "simple-bus"; 698 699 pcie_phy: phy-wrapper@34000 { 700 compatible = "qcom,msm8996-qmp-pcie-phy"; 701 reg = <0x00034000 0x488>; 702 #address-cells = <1>; 703 #size-cells = <1>; 704 ranges = <0x0 0x00034000 0x4000>; 705 706 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 707 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 708 <&gcc GCC_PCIE_CLKREF_CLK>; 709 clock-names = "aux", "cfg_ahb", "ref"; 710 711 resets = <&gcc GCC_PCIE_PHY_BCR>, 712 <&gcc GCC_PCIE_PHY_COM_BCR>, 713 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 714 reset-names = "phy", "common", "cfg"; 715 716 status = "disabled"; 717 718 pciephy_0: phy@1000 { 719 reg = <0x1000 0x130>, 720 <0x1200 0x200>, 721 <0x1400 0x1dc>; 722 723 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 724 clock-names = "pipe0"; 725 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 726 reset-names = "lane0"; 727 728 #clock-cells = <0>; 729 clock-output-names = "pcie_0_pipe_clk_src"; 730 731 #phy-cells = <0>; 732 }; 733 734 pciephy_1: phy@2000 { 735 reg = <0x2000 0x130>, 736 <0x2200 0x200>, 737 <0x2400 0x1dc>; 738 739 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 740 clock-names = "pipe1"; 741 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 742 reset-names = "lane1"; 743 744 #clock-cells = <0>; 745 clock-output-names = "pcie_1_pipe_clk_src"; 746 747 #phy-cells = <0>; 748 }; 749 750 pciephy_2: phy@3000 { 751 reg = <0x3000 0x130>, 752 <0x3200 0x200>, 753 <0x3400 0x1dc>; 754 755 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 756 clock-names = "pipe2"; 757 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 758 reset-names = "lane2"; 759 760 #clock-cells = <0>; 761 clock-output-names = "pcie_2_pipe_clk_src"; 762 763 #phy-cells = <0>; 764 }; 765 }; 766 767 rpm_msg_ram: sram@68000 { 768 compatible = "qcom,rpm-msg-ram", "mmio-sram"; 769 reg = <0x00068000 0x6000>; 770 #address-cells = <1>; 771 #size-cells = <1>; 772 ranges = <0 0x00068000 0x7000>; 773 774 apss_mpm: sram@1b8 { 775 reg = <0x1b8 0x48>; 776 }; 777 }; 778 779 qfprom@74000 { 780 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 781 reg = <0x00074000 0x8ff>; 782 #address-cells = <1>; 783 #size-cells = <1>; 784 785 qusb2p_hstx_trim: hstx_trim@24e { 786 reg = <0x24e 0x2>; 787 bits = <5 4>; 788 }; 789 790 qusb2s_hstx_trim: hstx_trim@24f { 791 reg = <0x24f 0x1>; 792 bits = <1 4>; 793 }; 794 795 speedbin_efuse: speedbin@133 { 796 reg = <0x133 0x1>; 797 bits = <5 3>; 798 }; 799 }; 800 801 rng: rng@83000 { 802 compatible = "qcom,prng-ee"; 803 reg = <0x00083000 0x1000>; 804 clocks = <&gcc GCC_PRNG_AHB_CLK>; 805 clock-names = "core"; 806 }; 807 808 gcc: clock-controller@300000 { 809 compatible = "qcom,gcc-msm8996"; 810 #clock-cells = <1>; 811 #reset-cells = <1>; 812 #power-domain-cells = <1>; 813 reg = <0x00300000 0x90000>; 814 815 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 816 <&rpmcc RPM_SMD_LN_BB_CLK>, 817 <&sleep_clk>, 818 <&pciephy_0>, 819 <&pciephy_1>, 820 <&pciephy_2>, 821 <&usb3phy>, 822 <&ufsphy 0>, 823 <&ufsphy 1>, 824 <&ufsphy 2>; 825 clock-names = "cxo", 826 "cxo2", 827 "sleep_clk", 828 "pcie_0_pipe_clk_src", 829 "pcie_1_pipe_clk_src", 830 "pcie_2_pipe_clk_src", 831 "usb3_phy_pipe_clk_src", 832 "ufs_rx_symbol_0_clk_src", 833 "ufs_rx_symbol_1_clk_src", 834 "ufs_tx_symbol_0_clk_src"; 835 }; 836 837 bimc: interconnect@408000 { 838 compatible = "qcom,msm8996-bimc"; 839 reg = <0x00408000 0x5a000>; 840 #interconnect-cells = <1>; 841 }; 842 843 tsens0: thermal-sensor@4a9000 { 844 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 845 reg = <0x004a9000 0x1000>, /* TM */ 846 <0x004a8000 0x1000>; /* SROT */ 847 #qcom,sensors = <13>; 848 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 850 interrupt-names = "uplow", "critical"; 851 #thermal-sensor-cells = <1>; 852 }; 853 854 tsens1: thermal-sensor@4ad000 { 855 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 856 reg = <0x004ad000 0x1000>, /* TM */ 857 <0x004ac000 0x1000>; /* SROT */ 858 #qcom,sensors = <8>; 859 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, 860 <&intc GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 861 interrupt-names = "uplow", "critical"; 862 #thermal-sensor-cells = <1>; 863 }; 864 865 cryptobam: dma-controller@644000 { 866 compatible = "qcom,bam-v1.7.0"; 867 reg = <0x00644000 0x24000>; 868 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&gcc GCC_CE1_CLK>; 870 clock-names = "bam_clk"; 871 #dma-cells = <1>; 872 qcom,ee = <0>; 873 qcom,controlled-remotely; 874 }; 875 876 crypto: crypto@67a000 { 877 compatible = "qcom,crypto-v5.4"; 878 reg = <0x0067a000 0x6000>; 879 clocks = <&gcc GCC_CE1_AHB_CLK>, 880 <&gcc GCC_CE1_AXI_CLK>, 881 <&gcc GCC_CE1_CLK>; 882 clock-names = "iface", "bus", "core"; 883 dmas = <&cryptobam 6>, <&cryptobam 7>; 884 dma-names = "rx", "tx"; 885 }; 886 887 cnoc: interconnect@500000 { 888 compatible = "qcom,msm8996-cnoc"; 889 reg = <0x00500000 0x1000>; 890 #interconnect-cells = <1>; 891 }; 892 893 snoc: interconnect@524000 { 894 compatible = "qcom,msm8996-snoc"; 895 reg = <0x00524000 0x1c000>; 896 #interconnect-cells = <1>; 897 }; 898 899 a0noc: interconnect@543000 { 900 compatible = "qcom,msm8996-a0noc"; 901 reg = <0x00543000 0x6000>; 902 #interconnect-cells = <1>; 903 clock-names = "aggre0_snoc_axi", 904 "aggre0_cnoc_ahb", 905 "aggre0_noc_mpu_cfg"; 906 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 907 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 908 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 909 power-domains = <&gcc AGGRE0_NOC_GDSC>; 910 }; 911 912 a1noc: interconnect@562000 { 913 compatible = "qcom,msm8996-a1noc"; 914 reg = <0x00562000 0x5000>; 915 #interconnect-cells = <1>; 916 }; 917 918 a2noc: interconnect@583000 { 919 compatible = "qcom,msm8996-a2noc"; 920 reg = <0x00583000 0x7000>; 921 #interconnect-cells = <1>; 922 clock-names = "aggre2_ufs_axi", "ufs_axi"; 923 clocks = <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 924 <&gcc GCC_UFS_AXI_CLK>; 925 }; 926 927 mnoc: interconnect@5a4000 { 928 compatible = "qcom,msm8996-mnoc"; 929 reg = <0x005a4000 0x1c000>; 930 #interconnect-cells = <1>; 931 clock-names = "iface"; 932 clocks = <&mmcc AHB_CLK_SRC>; 933 }; 934 935 pnoc: interconnect@5c0000 { 936 compatible = "qcom,msm8996-pnoc"; 937 reg = <0x005c0000 0x3000>; 938 #interconnect-cells = <1>; 939 }; 940 941 tcsr_mutex: hwlock@740000 { 942 compatible = "qcom,tcsr-mutex"; 943 reg = <0x00740000 0x20000>; 944 #hwlock-cells = <1>; 945 }; 946 947 tcsr_1: syscon@760000 { 948 compatible = "qcom,tcsr-msm8996", "syscon"; 949 reg = <0x00760000 0x20000>; 950 }; 951 952 tcsr_2: syscon@7a0000 { 953 compatible = "qcom,tcsr-msm8996", "syscon"; 954 reg = <0x007a0000 0x18000>; 955 }; 956 957 mmcc: clock-controller@8c0000 { 958 compatible = "qcom,mmcc-msm8996"; 959 #clock-cells = <1>; 960 #reset-cells = <1>; 961 #power-domain-cells = <1>; 962 reg = <0x008c0000 0x40000>; 963 clocks = <&xo_board>, 964 <&gcc GPLL0>, 965 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 966 <&mdss_dsi0_phy 1>, 967 <&mdss_dsi0_phy 0>, 968 <&mdss_dsi1_phy 1>, 969 <&mdss_dsi1_phy 0>, 970 <&mdss_hdmi_phy>; 971 clock-names = "xo", 972 "gpll0", 973 "gcc_mmss_noc_cfg_ahb_clk", 974 "dsi0pll", 975 "dsi0pllbyte", 976 "dsi1pll", 977 "dsi1pllbyte", 978 "hdmipll"; 979 assigned-clocks = <&mmcc MMPLL9_PLL>, 980 <&mmcc MMPLL1_PLL>, 981 <&mmcc MMPLL3_PLL>, 982 <&mmcc MMPLL4_PLL>, 983 <&mmcc MMPLL5_PLL>; 984 assigned-clock-rates = <624000000>, 985 <810000000>, 986 <980000000>, 987 <960000000>, 988 <825000000>; 989 }; 990 991 mdss: display-subsystem@900000 { 992 compatible = "qcom,mdss"; 993 994 reg = <0x00900000 0x1000>, 995 <0x009b0000 0x1040>, 996 <0x009b8000 0x1040>; 997 reg-names = "mdss_phys", 998 "vbif_phys", 999 "vbif_nrt_phys"; 1000 1001 power-domains = <&mmcc MDSS_GDSC>; 1002 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1003 1004 interrupt-controller; 1005 #interrupt-cells = <1>; 1006 1007 clocks = <&mmcc MDSS_AHB_CLK>, 1008 <&mmcc MDSS_MDP_CLK>; 1009 clock-names = "iface", "core"; 1010 1011 #address-cells = <1>; 1012 #size-cells = <1>; 1013 ranges; 1014 1015 status = "disabled"; 1016 1017 mdp: display-controller@901000 { 1018 compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; 1019 reg = <0x00901000 0x90000>; 1020 reg-names = "mdp_phys"; 1021 1022 interrupt-parent = <&mdss>; 1023 interrupts = <0>; 1024 1025 clocks = <&mmcc MDSS_AHB_CLK>, 1026 <&mmcc MDSS_AXI_CLK>, 1027 <&mmcc MDSS_MDP_CLK>, 1028 <&mmcc SMMU_MDP_AXI_CLK>, 1029 <&mmcc MDSS_VSYNC_CLK>; 1030 clock-names = "iface", 1031 "bus", 1032 "core", 1033 "iommu", 1034 "vsync"; 1035 1036 iommus = <&mdp_smmu 0>; 1037 1038 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1039 <&mmcc MDSS_VSYNC_CLK>; 1040 assigned-clock-rates = <300000000>, 1041 <19200000>; 1042 1043 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 1044 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 1045 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 1046 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 1047 1048 ports { 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 1052 port@0 { 1053 reg = <0>; 1054 mdp5_intf3_out: endpoint { 1055 remote-endpoint = <&mdss_hdmi_in>; 1056 }; 1057 }; 1058 1059 port@1 { 1060 reg = <1>; 1061 mdp5_intf1_out: endpoint { 1062 remote-endpoint = <&mdss_dsi0_in>; 1063 }; 1064 }; 1065 1066 port@2 { 1067 reg = <2>; 1068 mdp5_intf2_out: endpoint { 1069 remote-endpoint = <&mdss_dsi1_in>; 1070 }; 1071 }; 1072 }; 1073 }; 1074 1075 mdss_dsi0: dsi@994000 { 1076 compatible = "qcom,msm8996-dsi-ctrl", 1077 "qcom,mdss-dsi-ctrl"; 1078 reg = <0x00994000 0x400>; 1079 reg-names = "dsi_ctrl"; 1080 1081 interrupt-parent = <&mdss>; 1082 interrupts = <4>; 1083 1084 clocks = <&mmcc MDSS_MDP_CLK>, 1085 <&mmcc MDSS_BYTE0_CLK>, 1086 <&mmcc MDSS_AHB_CLK>, 1087 <&mmcc MDSS_AXI_CLK>, 1088 <&mmcc MMSS_MISC_AHB_CLK>, 1089 <&mmcc MDSS_PCLK0_CLK>, 1090 <&mmcc MDSS_ESC0_CLK>; 1091 clock-names = "mdp_core", 1092 "byte", 1093 "iface", 1094 "bus", 1095 "core_mmss", 1096 "pixel", 1097 "core"; 1098 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1099 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1100 1101 phys = <&mdss_dsi0_phy>; 1102 status = "disabled"; 1103 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 1107 ports { 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 1111 port@0 { 1112 reg = <0>; 1113 mdss_dsi0_in: endpoint { 1114 remote-endpoint = <&mdp5_intf1_out>; 1115 }; 1116 }; 1117 1118 port@1 { 1119 reg = <1>; 1120 mdss_dsi0_out: endpoint { 1121 }; 1122 }; 1123 }; 1124 }; 1125 1126 mdss_dsi0_phy: phy@994400 { 1127 compatible = "qcom,dsi-phy-14nm"; 1128 reg = <0x00994400 0x100>, 1129 <0x00994500 0x300>, 1130 <0x00994800 0x188>; 1131 reg-names = "dsi_phy", 1132 "dsi_phy_lane", 1133 "dsi_pll"; 1134 1135 #clock-cells = <1>; 1136 #phy-cells = <0>; 1137 1138 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1139 clock-names = "iface", "ref"; 1140 status = "disabled"; 1141 }; 1142 1143 mdss_dsi1: dsi@996000 { 1144 compatible = "qcom,msm8996-dsi-ctrl", 1145 "qcom,mdss-dsi-ctrl"; 1146 reg = <0x00996000 0x400>; 1147 reg-names = "dsi_ctrl"; 1148 1149 interrupt-parent = <&mdss>; 1150 interrupts = <5>; 1151 1152 clocks = <&mmcc MDSS_MDP_CLK>, 1153 <&mmcc MDSS_BYTE1_CLK>, 1154 <&mmcc MDSS_AHB_CLK>, 1155 <&mmcc MDSS_AXI_CLK>, 1156 <&mmcc MMSS_MISC_AHB_CLK>, 1157 <&mmcc MDSS_PCLK1_CLK>, 1158 <&mmcc MDSS_ESC1_CLK>; 1159 clock-names = "mdp_core", 1160 "byte", 1161 "iface", 1162 "bus", 1163 "core_mmss", 1164 "pixel", 1165 "core"; 1166 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 1167 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 1168 1169 phys = <&mdss_dsi1_phy>; 1170 status = "disabled"; 1171 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 1175 ports { 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 1179 port@0 { 1180 reg = <0>; 1181 mdss_dsi1_in: endpoint { 1182 remote-endpoint = <&mdp5_intf2_out>; 1183 }; 1184 }; 1185 1186 port@1 { 1187 reg = <1>; 1188 mdss_dsi1_out: endpoint { 1189 }; 1190 }; 1191 }; 1192 }; 1193 1194 mdss_dsi1_phy: phy@996400 { 1195 compatible = "qcom,dsi-phy-14nm"; 1196 reg = <0x00996400 0x100>, 1197 <0x00996500 0x300>, 1198 <0x00996800 0x188>; 1199 reg-names = "dsi_phy", 1200 "dsi_phy_lane", 1201 "dsi_pll"; 1202 1203 #clock-cells = <1>; 1204 #phy-cells = <0>; 1205 1206 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1207 clock-names = "iface", "ref"; 1208 status = "disabled"; 1209 }; 1210 1211 mdss_hdmi: hdmi-tx@9a0000 { 1212 compatible = "qcom,hdmi-tx-8996"; 1213 reg = <0x009a0000 0x50c>, 1214 <0x00070000 0x6158>, 1215 <0x009e0000 0xfff>; 1216 reg-names = "core_physical", 1217 "qfprom_physical", 1218 "hdcp_physical"; 1219 1220 interrupt-parent = <&mdss>; 1221 interrupts = <8>; 1222 1223 clocks = <&mmcc MDSS_MDP_CLK>, 1224 <&mmcc MDSS_AHB_CLK>, 1225 <&mmcc MDSS_HDMI_CLK>, 1226 <&mmcc MDSS_HDMI_AHB_CLK>, 1227 <&mmcc MDSS_EXTPCLK_CLK>; 1228 clock-names = 1229 "mdp_core", 1230 "iface", 1231 "core", 1232 "alt_iface", 1233 "extp"; 1234 1235 phys = <&mdss_hdmi_phy>; 1236 #sound-dai-cells = <1>; 1237 1238 status = "disabled"; 1239 1240 ports { 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 1244 port@0 { 1245 reg = <0>; 1246 mdss_hdmi_in: endpoint { 1247 remote-endpoint = <&mdp5_intf3_out>; 1248 }; 1249 }; 1250 }; 1251 }; 1252 1253 mdss_hdmi_phy: phy@9a0600 { 1254 #phy-cells = <0>; 1255 compatible = "qcom,hdmi-phy-8996"; 1256 reg = <0x009a0600 0x1c4>, 1257 <0x009a0a00 0x124>, 1258 <0x009a0c00 0x124>, 1259 <0x009a0e00 0x124>, 1260 <0x009a1000 0x124>, 1261 <0x009a1200 0x0c8>; 1262 reg-names = "hdmi_pll", 1263 "hdmi_tx_l0", 1264 "hdmi_tx_l1", 1265 "hdmi_tx_l2", 1266 "hdmi_tx_l3", 1267 "hdmi_phy"; 1268 1269 clocks = <&mmcc MDSS_AHB_CLK>, 1270 <&gcc GCC_HDMI_CLKREF_CLK>, 1271 <&xo_board>; 1272 clock-names = "iface", 1273 "ref", 1274 "xo"; 1275 1276 #clock-cells = <0>; 1277 1278 status = "disabled"; 1279 }; 1280 }; 1281 1282 gpu: gpu@b00000 { 1283 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1284 1285 reg = <0x00b00000 0x3f000>; 1286 reg-names = "kgsl_3d0_reg_memory"; 1287 1288 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1289 1290 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1291 <&mmcc GPU_AHB_CLK>, 1292 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1293 <&gcc GCC_BIMC_GFX_CLK>, 1294 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1295 1296 clock-names = "core", 1297 "iface", 1298 "rbbmtimer", 1299 "mem", 1300 "mem_iface"; 1301 1302 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1303 interconnect-names = "gfx-mem"; 1304 1305 power-domains = <&mmcc GPU_GX_GDSC>; 1306 iommus = <&adreno_smmu 0>; 1307 1308 nvmem-cells = <&speedbin_efuse>; 1309 nvmem-cell-names = "speed_bin"; 1310 1311 operating-points-v2 = <&gpu_opp_table>; 1312 1313 status = "disabled"; 1314 1315 #cooling-cells = <2>; 1316 1317 gpu_opp_table: opp-table { 1318 compatible = "operating-points-v2"; 1319 1320 /* 1321 * 624Mhz is only available on speed bins 0 and 3. 1322 * 560Mhz is only available on speed bins 0, 2 and 3. 1323 * All the rest are available on all bins of the hardware. 1324 */ 1325 opp-624000000 { 1326 opp-hz = /bits/ 64 <624000000>; 1327 opp-supported-hw = <0x09>; 1328 }; 1329 opp-560000000 { 1330 opp-hz = /bits/ 64 <560000000>; 1331 opp-supported-hw = <0x0d>; 1332 }; 1333 opp-510000000 { 1334 opp-hz = /bits/ 64 <510000000>; 1335 opp-supported-hw = <0xff>; 1336 }; 1337 opp-401800000 { 1338 opp-hz = /bits/ 64 <401800000>; 1339 opp-supported-hw = <0xff>; 1340 }; 1341 opp-315000000 { 1342 opp-hz = /bits/ 64 <315000000>; 1343 opp-supported-hw = <0xff>; 1344 }; 1345 opp-214000000 { 1346 opp-hz = /bits/ 64 <214000000>; 1347 opp-supported-hw = <0xff>; 1348 }; 1349 opp-133000000 { 1350 opp-hz = /bits/ 64 <133000000>; 1351 opp-supported-hw = <0xff>; 1352 }; 1353 }; 1354 1355 zap-shader { 1356 memory-region = <&gpu_mem>; 1357 }; 1358 }; 1359 1360 tlmm: pinctrl@1010000 { 1361 compatible = "qcom,msm8996-pinctrl"; 1362 reg = <0x01010000 0x300000>; 1363 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1364 gpio-controller; 1365 gpio-ranges = <&tlmm 0 0 150>; 1366 wakeup-parent = <&mpm>; 1367 #gpio-cells = <2>; 1368 interrupt-controller; 1369 #interrupt-cells = <2>; 1370 1371 blsp1_spi1_default: blsp1-spi1-default-state { 1372 spi-pins { 1373 pins = "gpio0", "gpio1", "gpio3"; 1374 function = "blsp_spi1"; 1375 drive-strength = <12>; 1376 bias-disable; 1377 }; 1378 1379 cs-pins { 1380 pins = "gpio2"; 1381 function = "gpio"; 1382 drive-strength = <16>; 1383 bias-disable; 1384 output-high; 1385 }; 1386 }; 1387 1388 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 1389 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1390 function = "gpio"; 1391 drive-strength = <2>; 1392 bias-pull-down; 1393 }; 1394 1395 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { 1396 pins = "gpio4", "gpio5"; 1397 function = "blsp_uart8"; 1398 drive-strength = <16>; 1399 bias-disable; 1400 }; 1401 1402 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { 1403 pins = "gpio4", "gpio5"; 1404 function = "gpio"; 1405 drive-strength = <2>; 1406 bias-disable; 1407 }; 1408 1409 blsp2_i2c2_default: blsp2-i2c2-state { 1410 pins = "gpio6", "gpio7"; 1411 function = "blsp_i2c8"; 1412 drive-strength = <16>; 1413 bias-disable; 1414 }; 1415 1416 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1417 pins = "gpio6", "gpio7"; 1418 function = "gpio"; 1419 drive-strength = <2>; 1420 bias-disable; 1421 }; 1422 1423 blsp1_i2c6_default: blsp1-i2c6-state { 1424 pins = "gpio27", "gpio28"; 1425 function = "blsp_i2c6"; 1426 drive-strength = <16>; 1427 bias-disable; 1428 }; 1429 1430 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1431 pins = "gpio27", "gpio28"; 1432 function = "gpio"; 1433 drive-strength = <2>; 1434 bias-pull-up; 1435 }; 1436 1437 cci0_default: cci0-default-state { 1438 pins = "gpio17", "gpio18"; 1439 function = "cci_i2c"; 1440 drive-strength = <16>; 1441 bias-disable; 1442 }; 1443 1444 camera0_state_on: 1445 camera_rear_default: camera-rear-default-state { 1446 camera0_mclk: mclk0-pins { 1447 pins = "gpio13"; 1448 function = "cam_mclk"; 1449 drive-strength = <16>; 1450 bias-disable; 1451 }; 1452 1453 camera0_rst: rst-pins { 1454 pins = "gpio25"; 1455 function = "gpio"; 1456 drive-strength = <16>; 1457 bias-disable; 1458 }; 1459 1460 camera0_pwdn: pwdn-pins { 1461 pins = "gpio26"; 1462 function = "gpio"; 1463 drive-strength = <16>; 1464 bias-disable; 1465 }; 1466 }; 1467 1468 cci1_default: cci1-default-state { 1469 pins = "gpio19", "gpio20"; 1470 function = "cci_i2c"; 1471 drive-strength = <16>; 1472 bias-disable; 1473 }; 1474 1475 camera1_state_on: 1476 camera_board_default: camera-board-default-state { 1477 mclk1-pins { 1478 pins = "gpio14"; 1479 function = "cam_mclk"; 1480 drive-strength = <16>; 1481 bias-disable; 1482 }; 1483 1484 pwdn-pins { 1485 pins = "gpio98"; 1486 function = "gpio"; 1487 drive-strength = <16>; 1488 bias-disable; 1489 }; 1490 1491 rst-pins { 1492 pins = "gpio104"; 1493 function = "gpio"; 1494 drive-strength = <16>; 1495 bias-disable; 1496 }; 1497 }; 1498 1499 camera2_state_on: 1500 camera_front_default: camera-front-default-state { 1501 camera2_mclk: mclk2-pins { 1502 pins = "gpio15"; 1503 function = "cam_mclk"; 1504 drive-strength = <16>; 1505 bias-disable; 1506 }; 1507 1508 camera2_rst: rst-pins { 1509 pins = "gpio23"; 1510 function = "gpio"; 1511 drive-strength = <16>; 1512 bias-disable; 1513 }; 1514 1515 pwdn-pins { 1516 pins = "gpio133"; 1517 function = "gpio"; 1518 drive-strength = <16>; 1519 bias-disable; 1520 }; 1521 }; 1522 1523 pcie0_state_on: pcie0-state-on-state { 1524 perst-pins { 1525 pins = "gpio35"; 1526 function = "gpio"; 1527 drive-strength = <2>; 1528 bias-pull-down; 1529 }; 1530 1531 clkreq-pins { 1532 pins = "gpio36"; 1533 function = "pci_e0"; 1534 drive-strength = <2>; 1535 bias-pull-up; 1536 }; 1537 1538 wake-pins { 1539 pins = "gpio37"; 1540 function = "gpio"; 1541 drive-strength = <2>; 1542 bias-pull-up; 1543 }; 1544 }; 1545 1546 pcie0_state_off: pcie0-state-off-state { 1547 perst-pins { 1548 pins = "gpio35"; 1549 function = "gpio"; 1550 drive-strength = <2>; 1551 bias-pull-down; 1552 }; 1553 1554 clkreq-pins { 1555 pins = "gpio36"; 1556 function = "gpio"; 1557 drive-strength = <2>; 1558 bias-disable; 1559 }; 1560 1561 wake-pins { 1562 pins = "gpio37"; 1563 function = "gpio"; 1564 drive-strength = <2>; 1565 bias-disable; 1566 }; 1567 }; 1568 1569 blsp1_uart2_default: blsp1-uart2-default-state { 1570 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1571 function = "blsp_uart2"; 1572 drive-strength = <16>; 1573 bias-disable; 1574 }; 1575 1576 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 1577 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1578 function = "gpio"; 1579 drive-strength = <2>; 1580 bias-disable; 1581 }; 1582 1583 blsp1_i2c3_default: blsp1-i2c3-default-state { 1584 pins = "gpio47", "gpio48"; 1585 function = "blsp_i2c3"; 1586 drive-strength = <16>; 1587 bias-disable; 1588 }; 1589 1590 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1591 pins = "gpio47", "gpio48"; 1592 function = "gpio"; 1593 drive-strength = <2>; 1594 bias-disable; 1595 }; 1596 1597 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { 1598 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1599 function = "blsp_uart9"; 1600 drive-strength = <16>; 1601 bias-disable; 1602 }; 1603 1604 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { 1605 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1606 function = "blsp_uart9"; 1607 drive-strength = <2>; 1608 bias-disable; 1609 }; 1610 1611 blsp2_i2c3_default: blsp2-i2c3-state-state { 1612 pins = "gpio51", "gpio52"; 1613 function = "blsp_i2c9"; 1614 drive-strength = <16>; 1615 bias-disable; 1616 }; 1617 1618 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1619 pins = "gpio51", "gpio52"; 1620 function = "gpio"; 1621 drive-strength = <2>; 1622 bias-disable; 1623 }; 1624 1625 wcd_intr_default: wcd-intr-default-state { 1626 pins = "gpio54"; 1627 function = "gpio"; 1628 drive-strength = <2>; 1629 bias-pull-down; 1630 }; 1631 1632 blsp2_i2c1_default: blsp2-i2c1-state { 1633 pins = "gpio55", "gpio56"; 1634 function = "blsp_i2c7"; 1635 drive-strength = <16>; 1636 bias-disable; 1637 }; 1638 1639 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1640 pins = "gpio55", "gpio56"; 1641 function = "gpio"; 1642 drive-strength = <2>; 1643 bias-disable; 1644 }; 1645 1646 blsp2_i2c5_default: blsp2-i2c5-state { 1647 pins = "gpio60", "gpio61"; 1648 function = "blsp_i2c11"; 1649 drive-strength = <2>; 1650 bias-disable; 1651 }; 1652 1653 /* Sleep state for BLSP2_I2C5 is missing.. */ 1654 1655 cdc_reset_active: cdc-reset-active-state { 1656 pins = "gpio64"; 1657 function = "gpio"; 1658 drive-strength = <16>; 1659 bias-pull-down; 1660 output-high; 1661 }; 1662 1663 cdc_reset_sleep: cdc-reset-sleep-state { 1664 pins = "gpio64"; 1665 function = "gpio"; 1666 drive-strength = <16>; 1667 bias-disable; 1668 output-low; 1669 }; 1670 1671 blsp2_spi6_default: blsp2-spi6-default-state { 1672 spi-pins { 1673 pins = "gpio85", "gpio86", "gpio88"; 1674 function = "blsp_spi12"; 1675 drive-strength = <12>; 1676 bias-disable; 1677 }; 1678 1679 cs-pins { 1680 pins = "gpio87"; 1681 function = "gpio"; 1682 drive-strength = <16>; 1683 bias-disable; 1684 output-high; 1685 }; 1686 }; 1687 1688 blsp2_spi6_sleep: blsp2-spi6-sleep-state { 1689 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1690 function = "gpio"; 1691 drive-strength = <2>; 1692 bias-pull-down; 1693 }; 1694 1695 blsp2_i2c6_default: blsp2-i2c6-state { 1696 pins = "gpio87", "gpio88"; 1697 function = "blsp_i2c12"; 1698 drive-strength = <16>; 1699 bias-disable; 1700 }; 1701 1702 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1703 pins = "gpio87", "gpio88"; 1704 function = "gpio"; 1705 drive-strength = <2>; 1706 bias-disable; 1707 }; 1708 1709 pcie1_state_on: pcie1-on-state { 1710 perst-pins { 1711 pins = "gpio130"; 1712 function = "gpio"; 1713 drive-strength = <2>; 1714 bias-pull-down; 1715 }; 1716 1717 clkreq-pins { 1718 pins = "gpio131"; 1719 function = "pci_e1"; 1720 drive-strength = <2>; 1721 bias-pull-up; 1722 }; 1723 1724 wake-pins { 1725 pins = "gpio132"; 1726 function = "gpio"; 1727 drive-strength = <2>; 1728 bias-pull-down; 1729 }; 1730 }; 1731 1732 pcie1_state_off: pcie1-off-state { 1733 /* Perst is missing? */ 1734 clkreq-pins { 1735 pins = "gpio131"; 1736 function = "gpio"; 1737 drive-strength = <2>; 1738 bias-disable; 1739 }; 1740 1741 wake-pins { 1742 pins = "gpio132"; 1743 function = "gpio"; 1744 drive-strength = <2>; 1745 bias-disable; 1746 }; 1747 }; 1748 1749 pcie2_state_on: pcie2-on-state { 1750 perst-pins { 1751 pins = "gpio114"; 1752 function = "gpio"; 1753 drive-strength = <2>; 1754 bias-pull-down; 1755 }; 1756 1757 clkreq-pins { 1758 pins = "gpio115"; 1759 function = "pci_e2"; 1760 drive-strength = <2>; 1761 bias-pull-up; 1762 }; 1763 1764 wake-pins { 1765 pins = "gpio116"; 1766 function = "gpio"; 1767 drive-strength = <2>; 1768 bias-pull-down; 1769 }; 1770 }; 1771 1772 pcie2_state_off: pcie2-off-state { 1773 /* Perst is missing? */ 1774 clkreq-pins { 1775 pins = "gpio115"; 1776 function = "gpio"; 1777 drive-strength = <2>; 1778 bias-disable; 1779 }; 1780 1781 wake-pins { 1782 pins = "gpio116"; 1783 function = "gpio"; 1784 drive-strength = <2>; 1785 bias-disable; 1786 }; 1787 }; 1788 1789 sdc1_state_on: sdc1-on-state { 1790 clk-pins { 1791 pins = "sdc1_clk"; 1792 bias-disable; 1793 drive-strength = <16>; 1794 }; 1795 1796 cmd-pins { 1797 pins = "sdc1_cmd"; 1798 bias-pull-up; 1799 drive-strength = <10>; 1800 }; 1801 1802 data-pins { 1803 pins = "sdc1_data"; 1804 bias-pull-up; 1805 drive-strength = <10>; 1806 }; 1807 1808 rclk-pins { 1809 pins = "sdc1_rclk"; 1810 bias-pull-down; 1811 }; 1812 }; 1813 1814 sdc1_state_off: sdc1-off-state { 1815 clk-pins { 1816 pins = "sdc1_clk"; 1817 bias-disable; 1818 drive-strength = <2>; 1819 }; 1820 1821 cmd-pins { 1822 pins = "sdc1_cmd"; 1823 bias-pull-up; 1824 drive-strength = <2>; 1825 }; 1826 1827 data-pins { 1828 pins = "sdc1_data"; 1829 bias-pull-up; 1830 drive-strength = <2>; 1831 }; 1832 1833 rclk-pins { 1834 pins = "sdc1_rclk"; 1835 bias-pull-down; 1836 }; 1837 }; 1838 1839 sdc2_state_on: sdc2-on-state { 1840 clk-pins { 1841 pins = "sdc2_clk"; 1842 bias-disable; 1843 drive-strength = <16>; 1844 }; 1845 1846 cmd-pins { 1847 pins = "sdc2_cmd"; 1848 bias-pull-up; 1849 drive-strength = <10>; 1850 }; 1851 1852 data-pins { 1853 pins = "sdc2_data"; 1854 bias-pull-up; 1855 drive-strength = <10>; 1856 }; 1857 }; 1858 1859 sdc2_state_off: sdc2-off-state { 1860 clk-pins { 1861 pins = "sdc2_clk"; 1862 bias-disable; 1863 drive-strength = <2>; 1864 }; 1865 1866 cmd-pins { 1867 pins = "sdc2_cmd"; 1868 bias-pull-up; 1869 drive-strength = <2>; 1870 }; 1871 1872 data-pins { 1873 pins = "sdc2_data"; 1874 bias-pull-up; 1875 drive-strength = <2>; 1876 }; 1877 }; 1878 }; 1879 1880 sram@290000 { 1881 compatible = "qcom,rpm-stats"; 1882 reg = <0x00290000 0x10000>; 1883 }; 1884 1885 spmi_bus: spmi@400f000 { 1886 compatible = "qcom,spmi-pmic-arb"; 1887 reg = <0x0400f000 0x1000>, 1888 <0x04400000 0x800000>, 1889 <0x04c00000 0x800000>, 1890 <0x05800000 0x200000>, 1891 <0x0400a000 0x002100>; 1892 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1893 interrupt-names = "periph_irq"; 1894 interrupts-extended = <&mpm 87 IRQ_TYPE_LEVEL_HIGH>; 1895 qcom,ee = <0>; 1896 qcom,channel = <0>; 1897 #address-cells = <2>; 1898 #size-cells = <0>; 1899 interrupt-controller; 1900 #interrupt-cells = <4>; 1901 }; 1902 1903 bus@0 { 1904 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1905 compatible = "simple-pm-bus"; 1906 #address-cells = <1>; 1907 #size-cells = <1>; 1908 ranges = <0x0 0x0 0xffffffff>; 1909 1910 pcie0: pcie@600000 { 1911 compatible = "qcom,pcie-msm8996"; 1912 status = "disabled"; 1913 power-domains = <&gcc PCIE0_GDSC>; 1914 bus-range = <0x00 0xff>; 1915 num-lanes = <1>; 1916 1917 reg = <0x00600000 0x2000>, 1918 <0x0c000000 0xf1d>, 1919 <0x0c000f20 0xa8>, 1920 <0x0c100000 0x100000>; 1921 reg-names = "parf", "dbi", "elbi","config"; 1922 1923 phys = <&pciephy_0>; 1924 phy-names = "pciephy"; 1925 1926 #address-cells = <3>; 1927 #size-cells = <2>; 1928 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, 1929 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1930 1931 device_type = "pci"; 1932 1933 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1934 interrupt-names = "msi"; 1935 #interrupt-cells = <1>; 1936 interrupt-map-mask = <0 0 0 0x7>; 1937 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1938 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1939 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1940 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1941 1942 pinctrl-names = "default", "sleep"; 1943 pinctrl-0 = <&pcie0_state_on>; 1944 pinctrl-1 = <&pcie0_state_off>; 1945 1946 linux,pci-domain = <0>; 1947 1948 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1949 <&gcc GCC_PCIE_0_AUX_CLK>, 1950 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1951 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1952 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1953 1954 clock-names = "pipe", 1955 "aux", 1956 "cfg", 1957 "bus_master", 1958 "bus_slave"; 1959 }; 1960 1961 pcie1: pcie@608000 { 1962 compatible = "qcom,pcie-msm8996"; 1963 power-domains = <&gcc PCIE1_GDSC>; 1964 bus-range = <0x00 0xff>; 1965 num-lanes = <1>; 1966 1967 status = "disabled"; 1968 1969 reg = <0x00608000 0x2000>, 1970 <0x0d000000 0xf1d>, 1971 <0x0d000f20 0xa8>, 1972 <0x0d100000 0x100000>; 1973 1974 reg-names = "parf", "dbi", "elbi","config"; 1975 1976 phys = <&pciephy_1>; 1977 phy-names = "pciephy"; 1978 1979 #address-cells = <3>; 1980 #size-cells = <2>; 1981 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, 1982 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1983 1984 device_type = "pci"; 1985 1986 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1987 interrupt-names = "msi"; 1988 #interrupt-cells = <1>; 1989 interrupt-map-mask = <0 0 0 0x7>; 1990 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1991 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1992 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1993 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1994 1995 pinctrl-names = "default", "sleep"; 1996 pinctrl-0 = <&pcie1_state_on>; 1997 pinctrl-1 = <&pcie1_state_off>; 1998 1999 linux,pci-domain = <1>; 2000 2001 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2002 <&gcc GCC_PCIE_1_AUX_CLK>, 2003 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2004 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2005 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 2006 2007 clock-names = "pipe", 2008 "aux", 2009 "cfg", 2010 "bus_master", 2011 "bus_slave"; 2012 }; 2013 2014 pcie2: pcie@610000 { 2015 compatible = "qcom,pcie-msm8996"; 2016 power-domains = <&gcc PCIE2_GDSC>; 2017 bus-range = <0x00 0xff>; 2018 num-lanes = <1>; 2019 status = "disabled"; 2020 reg = <0x00610000 0x2000>, 2021 <0x0e000000 0xf1d>, 2022 <0x0e000f20 0xa8>, 2023 <0x0e100000 0x100000>; 2024 2025 reg-names = "parf", "dbi", "elbi","config"; 2026 2027 phys = <&pciephy_2>; 2028 phy-names = "pciephy"; 2029 2030 #address-cells = <3>; 2031 #size-cells = <2>; 2032 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, 2033 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 2034 2035 device_type = "pci"; 2036 2037 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 2038 interrupt-names = "msi"; 2039 #interrupt-cells = <1>; 2040 interrupt-map-mask = <0 0 0 0x7>; 2041 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2042 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2043 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2044 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2045 2046 pinctrl-names = "default", "sleep"; 2047 pinctrl-0 = <&pcie2_state_on>; 2048 pinctrl-1 = <&pcie2_state_off>; 2049 2050 linux,pci-domain = <2>; 2051 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2052 <&gcc GCC_PCIE_2_AUX_CLK>, 2053 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2054 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2055 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 2056 2057 clock-names = "pipe", 2058 "aux", 2059 "cfg", 2060 "bus_master", 2061 "bus_slave"; 2062 }; 2063 }; 2064 2065 ufshc: ufshc@624000 { 2066 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 2067 "jedec,ufs-2.0"; 2068 reg = <0x00624000 0x2500>; 2069 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2070 2071 phys = <&ufsphy>; 2072 phy-names = "ufsphy"; 2073 2074 power-domains = <&gcc UFS_GDSC>; 2075 2076 clock-names = 2077 "core_clk_src", 2078 "core_clk", 2079 "bus_clk", 2080 "bus_aggr_clk", 2081 "iface_clk", 2082 "core_clk_unipro_src", 2083 "core_clk_unipro", 2084 "core_clk_ice", 2085 "ref_clk", 2086 "tx_lane0_sync_clk", 2087 "rx_lane0_sync_clk"; 2088 clocks = 2089 <&gcc UFS_AXI_CLK_SRC>, 2090 <&gcc GCC_UFS_AXI_CLK>, 2091 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 2092 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 2093 <&gcc GCC_UFS_AHB_CLK>, 2094 <&gcc UFS_ICE_CORE_CLK_SRC>, 2095 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 2096 <&gcc GCC_UFS_ICE_CORE_CLK>, 2097 <&rpmcc RPM_SMD_LN_BB_CLK>, 2098 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 2099 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 2100 freq-table-hz = 2101 <100000000 200000000>, 2102 <0 0>, 2103 <0 0>, 2104 <0 0>, 2105 <0 0>, 2106 <150000000 300000000>, 2107 <0 0>, 2108 <0 0>, 2109 <0 0>, 2110 <0 0>, 2111 <0 0>; 2112 2113 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, 2114 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; 2115 interconnect-names = "ufs-ddr", "cpu-ufs"; 2116 2117 lanes-per-direction = <1>; 2118 #reset-cells = <1>; 2119 status = "disabled"; 2120 }; 2121 2122 ufsphy: phy@627000 { 2123 compatible = "qcom,msm8996-qmp-ufs-phy"; 2124 reg = <0x00627000 0x1000>; 2125 2126 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 2127 clock-names = "ref"; 2128 2129 resets = <&ufshc 0>; 2130 reset-names = "ufsphy"; 2131 2132 #clock-cells = <1>; 2133 #phy-cells = <0>; 2134 2135 status = "disabled"; 2136 }; 2137 2138 camss: camss@a34000 { 2139 compatible = "qcom,msm8996-camss"; 2140 reg = <0x00a34000 0x1000>, 2141 <0x00a00030 0x4>, 2142 <0x00a35000 0x1000>, 2143 <0x00a00038 0x4>, 2144 <0x00a36000 0x1000>, 2145 <0x00a00040 0x4>, 2146 <0x00a30000 0x100>, 2147 <0x00a30400 0x100>, 2148 <0x00a30800 0x100>, 2149 <0x00a30c00 0x100>, 2150 <0x00a31000 0x500>, 2151 <0x00a00020 0x10>, 2152 <0x00a10000 0x1000>, 2153 <0x00a14000 0x1000>; 2154 reg-names = "csiphy0", 2155 "csiphy0_clk_mux", 2156 "csiphy1", 2157 "csiphy1_clk_mux", 2158 "csiphy2", 2159 "csiphy2_clk_mux", 2160 "csid0", 2161 "csid1", 2162 "csid2", 2163 "csid3", 2164 "ispif", 2165 "csi_clk_mux", 2166 "vfe0", 2167 "vfe1"; 2168 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2169 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2170 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2171 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2178 interrupt-names = "csiphy0", 2179 "csiphy1", 2180 "csiphy2", 2181 "csid0", 2182 "csid1", 2183 "csid2", 2184 "csid3", 2185 "ispif", 2186 "vfe0", 2187 "vfe1"; 2188 power-domains = <&mmcc VFE0_GDSC>, 2189 <&mmcc VFE1_GDSC>; 2190 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2191 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2192 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2193 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2194 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2195 <&mmcc CAMSS_CSI0_AHB_CLK>, 2196 <&mmcc CAMSS_CSI0_CLK>, 2197 <&mmcc CAMSS_CSI0PHY_CLK>, 2198 <&mmcc CAMSS_CSI0PIX_CLK>, 2199 <&mmcc CAMSS_CSI0RDI_CLK>, 2200 <&mmcc CAMSS_CSI1_AHB_CLK>, 2201 <&mmcc CAMSS_CSI1_CLK>, 2202 <&mmcc CAMSS_CSI1PHY_CLK>, 2203 <&mmcc CAMSS_CSI1PIX_CLK>, 2204 <&mmcc CAMSS_CSI1RDI_CLK>, 2205 <&mmcc CAMSS_CSI2_AHB_CLK>, 2206 <&mmcc CAMSS_CSI2_CLK>, 2207 <&mmcc CAMSS_CSI2PHY_CLK>, 2208 <&mmcc CAMSS_CSI2PIX_CLK>, 2209 <&mmcc CAMSS_CSI2RDI_CLK>, 2210 <&mmcc CAMSS_CSI3_AHB_CLK>, 2211 <&mmcc CAMSS_CSI3_CLK>, 2212 <&mmcc CAMSS_CSI3PHY_CLK>, 2213 <&mmcc CAMSS_CSI3PIX_CLK>, 2214 <&mmcc CAMSS_CSI3RDI_CLK>, 2215 <&mmcc CAMSS_AHB_CLK>, 2216 <&mmcc CAMSS_VFE0_CLK>, 2217 <&mmcc CAMSS_CSI_VFE0_CLK>, 2218 <&mmcc CAMSS_VFE0_AHB_CLK>, 2219 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2220 <&mmcc CAMSS_VFE1_CLK>, 2221 <&mmcc CAMSS_CSI_VFE1_CLK>, 2222 <&mmcc CAMSS_VFE1_AHB_CLK>, 2223 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2224 <&mmcc CAMSS_VFE_AHB_CLK>, 2225 <&mmcc CAMSS_VFE_AXI_CLK>; 2226 clock-names = "top_ahb", 2227 "ispif_ahb", 2228 "csiphy0_timer", 2229 "csiphy1_timer", 2230 "csiphy2_timer", 2231 "csi0_ahb", 2232 "csi0", 2233 "csi0_phy", 2234 "csi0_pix", 2235 "csi0_rdi", 2236 "csi1_ahb", 2237 "csi1", 2238 "csi1_phy", 2239 "csi1_pix", 2240 "csi1_rdi", 2241 "csi2_ahb", 2242 "csi2", 2243 "csi2_phy", 2244 "csi2_pix", 2245 "csi2_rdi", 2246 "csi3_ahb", 2247 "csi3", 2248 "csi3_phy", 2249 "csi3_pix", 2250 "csi3_rdi", 2251 "ahb", 2252 "vfe0", 2253 "csi_vfe0", 2254 "vfe0_ahb", 2255 "vfe0_stream", 2256 "vfe1", 2257 "csi_vfe1", 2258 "vfe1_ahb", 2259 "vfe1_stream", 2260 "vfe_ahb", 2261 "vfe_axi"; 2262 iommus = <&vfe_smmu 0>, 2263 <&vfe_smmu 1>, 2264 <&vfe_smmu 2>, 2265 <&vfe_smmu 3>; 2266 status = "disabled"; 2267 ports { 2268 #address-cells = <1>; 2269 #size-cells = <0>; 2270 }; 2271 }; 2272 2273 cci: cci@a0c000 { 2274 compatible = "qcom,msm8996-cci"; 2275 #address-cells = <1>; 2276 #size-cells = <0>; 2277 reg = <0xa0c000 0x1000>; 2278 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2279 power-domains = <&mmcc CAMSS_GDSC>; 2280 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2281 <&mmcc CAMSS_CCI_AHB_CLK>, 2282 <&mmcc CAMSS_CCI_CLK>, 2283 <&mmcc CAMSS_AHB_CLK>; 2284 clock-names = "camss_top_ahb", 2285 "cci_ahb", 2286 "cci", 2287 "camss_ahb"; 2288 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2289 <&mmcc CAMSS_CCI_CLK>; 2290 assigned-clock-rates = <80000000>, <37500000>; 2291 pinctrl-names = "default"; 2292 pinctrl-0 = <&cci0_default &cci1_default>; 2293 status = "disabled"; 2294 2295 cci_i2c0: i2c-bus@0 { 2296 reg = <0>; 2297 clock-frequency = <400000>; 2298 #address-cells = <1>; 2299 #size-cells = <0>; 2300 }; 2301 2302 cci_i2c1: i2c-bus@1 { 2303 reg = <1>; 2304 clock-frequency = <400000>; 2305 #address-cells = <1>; 2306 #size-cells = <0>; 2307 }; 2308 }; 2309 2310 adreno_smmu: iommu@b40000 { 2311 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2312 reg = <0x00b40000 0x10000>; 2313 2314 #global-interrupts = <1>; 2315 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2316 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2317 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2318 #iommu-cells = <1>; 2319 2320 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, 2321 <&mmcc GPU_AHB_CLK>; 2322 clock-names = "bus", "iface"; 2323 2324 power-domains = <&mmcc GPU_GDSC>; 2325 }; 2326 2327 venus: video-codec@c00000 { 2328 compatible = "qcom,msm8996-venus"; 2329 reg = <0x00c00000 0xff000>; 2330 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2331 power-domains = <&mmcc VENUS_GDSC>; 2332 clocks = <&mmcc VIDEO_CORE_CLK>, 2333 <&mmcc VIDEO_AHB_CLK>, 2334 <&mmcc VIDEO_AXI_CLK>, 2335 <&mmcc VIDEO_MAXI_CLK>; 2336 clock-names = "core", "iface", "bus", "mbus"; 2337 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2338 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2339 interconnect-names = "video-mem", "cpu-cfg"; 2340 iommus = <&venus_smmu 0x00>, 2341 <&venus_smmu 0x01>, 2342 <&venus_smmu 0x0a>, 2343 <&venus_smmu 0x07>, 2344 <&venus_smmu 0x0e>, 2345 <&venus_smmu 0x0f>, 2346 <&venus_smmu 0x08>, 2347 <&venus_smmu 0x09>, 2348 <&venus_smmu 0x0b>, 2349 <&venus_smmu 0x0c>, 2350 <&venus_smmu 0x0d>, 2351 <&venus_smmu 0x10>, 2352 <&venus_smmu 0x11>, 2353 <&venus_smmu 0x21>, 2354 <&venus_smmu 0x28>, 2355 <&venus_smmu 0x29>, 2356 <&venus_smmu 0x2b>, 2357 <&venus_smmu 0x2c>, 2358 <&venus_smmu 0x2d>, 2359 <&venus_smmu 0x31>; 2360 memory-region = <&venus_mem>; 2361 status = "disabled"; 2362 2363 video-decoder { 2364 compatible = "venus-decoder"; 2365 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2366 clock-names = "core"; 2367 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2368 }; 2369 2370 video-encoder { 2371 compatible = "venus-encoder"; 2372 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2373 clock-names = "core"; 2374 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2375 }; 2376 }; 2377 2378 mdp_smmu: iommu@d00000 { 2379 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2380 reg = <0x00d00000 0x10000>; 2381 2382 #global-interrupts = <1>; 2383 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2384 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2385 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2386 #iommu-cells = <1>; 2387 clocks = <&mmcc SMMU_MDP_AXI_CLK>, 2388 <&mmcc SMMU_MDP_AHB_CLK>; 2389 clock-names = "bus", "iface"; 2390 2391 power-domains = <&mmcc MDSS_GDSC>; 2392 }; 2393 2394 venus_smmu: iommu@d40000 { 2395 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2396 reg = <0x00d40000 0x20000>; 2397 #global-interrupts = <1>; 2398 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2399 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2400 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2405 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2406 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2407 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, 2408 <&mmcc SMMU_VIDEO_AHB_CLK>; 2409 clock-names = "bus", "iface"; 2410 #iommu-cells = <1>; 2411 status = "okay"; 2412 }; 2413 2414 vfe_smmu: iommu@da0000 { 2415 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2416 reg = <0x00da0000 0x10000>; 2417 2418 #global-interrupts = <1>; 2419 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2420 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2421 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2422 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2423 clocks = <&mmcc SMMU_VFE_AXI_CLK>, 2424 <&mmcc SMMU_VFE_AHB_CLK>; 2425 clock-names = "bus", "iface"; 2426 #iommu-cells = <1>; 2427 }; 2428 2429 lpass_q6_smmu: iommu@1600000 { 2430 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2431 reg = <0x01600000 0x20000>; 2432 #iommu-cells = <1>; 2433 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2434 2435 #global-interrupts = <1>; 2436 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2440 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2441 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2448 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2449 2450 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, 2451 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; 2452 clock-names = "bus", "iface"; 2453 }; 2454 2455 slpi_pil: remoteproc@1c00000 { 2456 compatible = "qcom,msm8996-slpi-pil"; 2457 reg = <0x01c00000 0x4000>; 2458 2459 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2460 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2461 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2462 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2463 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2464 interrupt-names = "wdog", 2465 "fatal", 2466 "ready", 2467 "handover", 2468 "stop-ack"; 2469 2470 clocks = <&xo_board>; 2471 clock-names = "xo"; 2472 2473 memory-region = <&slpi_mem>; 2474 2475 qcom,smem-states = <&slpi_smp2p_out 0>; 2476 qcom,smem-state-names = "stop"; 2477 2478 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2479 power-domain-names = "ssc_cx"; 2480 2481 status = "disabled"; 2482 2483 smd-edge { 2484 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2485 2486 label = "dsps"; 2487 mboxes = <&apcs_glb 25>; 2488 qcom,smd-edge = <3>; 2489 qcom,remote-pid = <3>; 2490 }; 2491 }; 2492 2493 mss_pil: remoteproc@2080000 { 2494 compatible = "qcom,msm8996-mss-pil"; 2495 reg = <0x2080000 0x100>, 2496 <0x2180000 0x020>; 2497 reg-names = "qdsp6", "rmb"; 2498 2499 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2500 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2501 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2502 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2503 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2504 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2505 interrupt-names = "wdog", "fatal", "ready", 2506 "handover", "stop-ack", 2507 "shutdown-ack"; 2508 2509 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2510 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2511 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2512 <&xo_board>, 2513 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2514 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2515 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2516 <&rpmcc RPM_SMD_QDSS_CLK>; 2517 clock-names = "iface", 2518 "bus", 2519 "mem", 2520 "xo", 2521 "gpll0_mss", 2522 "snoc_axi", 2523 "mnoc_axi", 2524 "qdss"; 2525 2526 resets = <&gcc GCC_MSS_RESTART>; 2527 reset-names = "mss_restart"; 2528 2529 power-domains = <&rpmpd MSM8996_VDDCX>, 2530 <&rpmpd MSM8996_VDDMX>; 2531 power-domain-names = "cx", "mx"; 2532 2533 qcom,smem-states = <&mpss_smp2p_out 0>; 2534 qcom,smem-state-names = "stop"; 2535 2536 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2537 2538 status = "disabled"; 2539 2540 mba { 2541 memory-region = <&mba_mem>; 2542 }; 2543 2544 mpss { 2545 memory-region = <&mpss_mem>; 2546 }; 2547 2548 metadata { 2549 memory-region = <&mdata_mem>; 2550 }; 2551 2552 smd-edge { 2553 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2554 2555 label = "mpss"; 2556 mboxes = <&apcs_glb 12>; 2557 qcom,smd-edge = <0>; 2558 qcom,remote-pid = <1>; 2559 }; 2560 }; 2561 2562 stm@3002000 { 2563 compatible = "arm,coresight-stm", "arm,primecell"; 2564 reg = <0x3002000 0x1000>, 2565 <0x8280000 0x180000>; 2566 reg-names = "stm-base", "stm-stimulus-base"; 2567 2568 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2569 clock-names = "apb_pclk", "atclk"; 2570 2571 out-ports { 2572 port { 2573 stm_out: endpoint { 2574 remote-endpoint = 2575 <&funnel0_in>; 2576 }; 2577 }; 2578 }; 2579 }; 2580 2581 tpiu@3020000 { 2582 compatible = "arm,coresight-tpiu", "arm,primecell"; 2583 reg = <0x3020000 0x1000>; 2584 2585 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2586 clock-names = "apb_pclk", "atclk"; 2587 2588 in-ports { 2589 port { 2590 tpiu_in: endpoint { 2591 remote-endpoint = 2592 <&replicator_out1>; 2593 }; 2594 }; 2595 }; 2596 }; 2597 2598 funnel@3021000 { 2599 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2600 reg = <0x3021000 0x1000>; 2601 2602 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2603 clock-names = "apb_pclk", "atclk"; 2604 2605 in-ports { 2606 #address-cells = <1>; 2607 #size-cells = <0>; 2608 2609 port@7 { 2610 reg = <7>; 2611 funnel0_in: endpoint { 2612 remote-endpoint = 2613 <&stm_out>; 2614 }; 2615 }; 2616 }; 2617 2618 out-ports { 2619 port { 2620 funnel0_out: endpoint { 2621 remote-endpoint = 2622 <&merge_funnel_in0>; 2623 }; 2624 }; 2625 }; 2626 }; 2627 2628 funnel@3022000 { 2629 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2630 reg = <0x3022000 0x1000>; 2631 2632 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2633 clock-names = "apb_pclk", "atclk"; 2634 2635 in-ports { 2636 #address-cells = <1>; 2637 #size-cells = <0>; 2638 2639 port@6 { 2640 reg = <6>; 2641 funnel1_in: endpoint { 2642 remote-endpoint = 2643 <&apss_merge_funnel_out>; 2644 }; 2645 }; 2646 }; 2647 2648 out-ports { 2649 port { 2650 funnel1_out: endpoint { 2651 remote-endpoint = 2652 <&merge_funnel_in1>; 2653 }; 2654 }; 2655 }; 2656 }; 2657 2658 funnel@3023000 { 2659 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2660 reg = <0x3023000 0x1000>; 2661 2662 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2663 clock-names = "apb_pclk", "atclk"; 2664 2665 in-ports { 2666 port { 2667 funnel_in2_in_modem_etm: endpoint { 2668 remote-endpoint = 2669 <&modem_etm_out_funnel_in2>; 2670 }; 2671 }; 2672 }; 2673 2674 out-ports { 2675 port { 2676 funnel2_out: endpoint { 2677 remote-endpoint = 2678 <&merge_funnel_in2>; 2679 }; 2680 }; 2681 }; 2682 }; 2683 2684 funnel@3025000 { 2685 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2686 reg = <0x3025000 0x1000>; 2687 2688 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2689 clock-names = "apb_pclk", "atclk"; 2690 2691 in-ports { 2692 #address-cells = <1>; 2693 #size-cells = <0>; 2694 2695 port@0 { 2696 reg = <0>; 2697 merge_funnel_in0: endpoint { 2698 remote-endpoint = 2699 <&funnel0_out>; 2700 }; 2701 }; 2702 2703 port@1 { 2704 reg = <1>; 2705 merge_funnel_in1: endpoint { 2706 remote-endpoint = 2707 <&funnel1_out>; 2708 }; 2709 }; 2710 2711 port@2 { 2712 reg = <2>; 2713 merge_funnel_in2: endpoint { 2714 remote-endpoint = 2715 <&funnel2_out>; 2716 }; 2717 }; 2718 }; 2719 2720 out-ports { 2721 port { 2722 merge_funnel_out: endpoint { 2723 remote-endpoint = 2724 <&etf_in>; 2725 }; 2726 }; 2727 }; 2728 }; 2729 2730 replicator@3026000 { 2731 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2732 reg = <0x3026000 0x1000>; 2733 2734 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2735 clock-names = "apb_pclk", "atclk"; 2736 2737 in-ports { 2738 port { 2739 replicator_in: endpoint { 2740 remote-endpoint = 2741 <&etf_out>; 2742 }; 2743 }; 2744 }; 2745 2746 out-ports { 2747 #address-cells = <1>; 2748 #size-cells = <0>; 2749 2750 port@0 { 2751 reg = <0>; 2752 replicator_out0: endpoint { 2753 remote-endpoint = 2754 <&etr_in>; 2755 }; 2756 }; 2757 2758 port@1 { 2759 reg = <1>; 2760 replicator_out1: endpoint { 2761 remote-endpoint = 2762 <&tpiu_in>; 2763 }; 2764 }; 2765 }; 2766 }; 2767 2768 etf@3027000 { 2769 compatible = "arm,coresight-tmc", "arm,primecell"; 2770 reg = <0x3027000 0x1000>; 2771 2772 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2773 clock-names = "apb_pclk", "atclk"; 2774 2775 in-ports { 2776 port { 2777 etf_in: endpoint { 2778 remote-endpoint = 2779 <&merge_funnel_out>; 2780 }; 2781 }; 2782 }; 2783 2784 out-ports { 2785 port { 2786 etf_out: endpoint { 2787 remote-endpoint = 2788 <&replicator_in>; 2789 }; 2790 }; 2791 }; 2792 }; 2793 2794 etr@3028000 { 2795 compatible = "arm,coresight-tmc", "arm,primecell"; 2796 reg = <0x3028000 0x1000>; 2797 2798 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2799 clock-names = "apb_pclk", "atclk"; 2800 arm,scatter-gather; 2801 2802 in-ports { 2803 port { 2804 etr_in: endpoint { 2805 remote-endpoint = 2806 <&replicator_out0>; 2807 }; 2808 }; 2809 }; 2810 }; 2811 2812 debug@3810000 { 2813 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2814 reg = <0x3810000 0x1000>; 2815 2816 clocks = <&rpmcc RPM_QDSS_CLK>; 2817 clock-names = "apb_pclk"; 2818 2819 cpu = <&CPU0>; 2820 }; 2821 2822 etm@3840000 { 2823 compatible = "arm,coresight-etm4x", "arm,primecell"; 2824 reg = <0x3840000 0x1000>; 2825 2826 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2827 clock-names = "apb_pclk", "atclk"; 2828 2829 cpu = <&CPU0>; 2830 2831 out-ports { 2832 port { 2833 etm0_out: endpoint { 2834 remote-endpoint = 2835 <&apss_funnel0_in0>; 2836 }; 2837 }; 2838 }; 2839 }; 2840 2841 debug@3910000 { 2842 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2843 reg = <0x3910000 0x1000>; 2844 2845 clocks = <&rpmcc RPM_QDSS_CLK>; 2846 clock-names = "apb_pclk"; 2847 2848 cpu = <&CPU1>; 2849 }; 2850 2851 etm@3940000 { 2852 compatible = "arm,coresight-etm4x", "arm,primecell"; 2853 reg = <0x3940000 0x1000>; 2854 2855 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2856 clock-names = "apb_pclk", "atclk"; 2857 2858 cpu = <&CPU1>; 2859 2860 out-ports { 2861 port { 2862 etm1_out: endpoint { 2863 remote-endpoint = 2864 <&apss_funnel0_in1>; 2865 }; 2866 }; 2867 }; 2868 }; 2869 2870 funnel@39b0000 { /* APSS Funnel 0 */ 2871 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2872 reg = <0x39b0000 0x1000>; 2873 2874 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2875 clock-names = "apb_pclk", "atclk"; 2876 2877 in-ports { 2878 #address-cells = <1>; 2879 #size-cells = <0>; 2880 2881 port@0 { 2882 reg = <0>; 2883 apss_funnel0_in0: endpoint { 2884 remote-endpoint = <&etm0_out>; 2885 }; 2886 }; 2887 2888 port@1 { 2889 reg = <1>; 2890 apss_funnel0_in1: endpoint { 2891 remote-endpoint = <&etm1_out>; 2892 }; 2893 }; 2894 }; 2895 2896 out-ports { 2897 port { 2898 apss_funnel0_out: endpoint { 2899 remote-endpoint = 2900 <&apss_merge_funnel_in0>; 2901 }; 2902 }; 2903 }; 2904 }; 2905 2906 debug@3a10000 { 2907 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2908 reg = <0x3a10000 0x1000>; 2909 2910 clocks = <&rpmcc RPM_QDSS_CLK>; 2911 clock-names = "apb_pclk"; 2912 2913 cpu = <&CPU2>; 2914 }; 2915 2916 etm@3a40000 { 2917 compatible = "arm,coresight-etm4x", "arm,primecell"; 2918 reg = <0x3a40000 0x1000>; 2919 2920 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2921 clock-names = "apb_pclk", "atclk"; 2922 2923 cpu = <&CPU2>; 2924 2925 out-ports { 2926 port { 2927 etm2_out: endpoint { 2928 remote-endpoint = 2929 <&apss_funnel1_in0>; 2930 }; 2931 }; 2932 }; 2933 }; 2934 2935 debug@3b10000 { 2936 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2937 reg = <0x3b10000 0x1000>; 2938 2939 clocks = <&rpmcc RPM_QDSS_CLK>; 2940 clock-names = "apb_pclk"; 2941 2942 cpu = <&CPU3>; 2943 }; 2944 2945 etm@3b40000 { 2946 compatible = "arm,coresight-etm4x", "arm,primecell"; 2947 reg = <0x3b40000 0x1000>; 2948 2949 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2950 clock-names = "apb_pclk", "atclk"; 2951 2952 cpu = <&CPU3>; 2953 2954 out-ports { 2955 port { 2956 etm3_out: endpoint { 2957 remote-endpoint = 2958 <&apss_funnel1_in1>; 2959 }; 2960 }; 2961 }; 2962 }; 2963 2964 funnel@3bb0000 { /* APSS Funnel 1 */ 2965 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2966 reg = <0x3bb0000 0x1000>; 2967 2968 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2969 clock-names = "apb_pclk", "atclk"; 2970 2971 in-ports { 2972 #address-cells = <1>; 2973 #size-cells = <0>; 2974 2975 port@0 { 2976 reg = <0>; 2977 apss_funnel1_in0: endpoint { 2978 remote-endpoint = <&etm2_out>; 2979 }; 2980 }; 2981 2982 port@1 { 2983 reg = <1>; 2984 apss_funnel1_in1: endpoint { 2985 remote-endpoint = <&etm3_out>; 2986 }; 2987 }; 2988 }; 2989 2990 out-ports { 2991 port { 2992 apss_funnel1_out: endpoint { 2993 remote-endpoint = 2994 <&apss_merge_funnel_in1>; 2995 }; 2996 }; 2997 }; 2998 }; 2999 3000 funnel@3bc0000 { 3001 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3002 reg = <0x3bc0000 0x1000>; 3003 3004 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 3005 clock-names = "apb_pclk", "atclk"; 3006 3007 in-ports { 3008 #address-cells = <1>; 3009 #size-cells = <0>; 3010 3011 port@0 { 3012 reg = <0>; 3013 apss_merge_funnel_in0: endpoint { 3014 remote-endpoint = 3015 <&apss_funnel0_out>; 3016 }; 3017 }; 3018 3019 port@1 { 3020 reg = <1>; 3021 apss_merge_funnel_in1: endpoint { 3022 remote-endpoint = 3023 <&apss_funnel1_out>; 3024 }; 3025 }; 3026 }; 3027 3028 out-ports { 3029 port { 3030 apss_merge_funnel_out: endpoint { 3031 remote-endpoint = 3032 <&funnel1_in>; 3033 }; 3034 }; 3035 }; 3036 }; 3037 3038 kryocc: clock-controller@6400000 { 3039 compatible = "qcom,msm8996-apcc"; 3040 reg = <0x06400000 0x90000>; 3041 3042 clock-names = "xo", "sys_apcs_aux"; 3043 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3044 3045 #clock-cells = <1>; 3046 }; 3047 3048 usb3: usb@6af8800 { 3049 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3050 reg = <0x06af8800 0x400>; 3051 #address-cells = <1>; 3052 #size-cells = <1>; 3053 ranges; 3054 3055 interrupts-extended = <&mpm 79 IRQ_TYPE_LEVEL_HIGH>, 3056 <&mpm 52 IRQ_TYPE_LEVEL_HIGH>; 3057 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 3058 3059 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 3060 <&gcc GCC_USB30_MASTER_CLK>, 3061 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 3062 <&gcc GCC_USB30_SLEEP_CLK>, 3063 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 3064 clock-names = "cfg_noc", 3065 "core", 3066 "iface", 3067 "sleep", 3068 "mock_utmi"; 3069 3070 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 3071 <&gcc GCC_USB30_MASTER_CLK>; 3072 assigned-clock-rates = <19200000>, <120000000>; 3073 3074 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 3075 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 3076 interconnect-names = "usb-ddr", "apps-usb"; 3077 3078 power-domains = <&gcc USB30_GDSC>; 3079 status = "disabled"; 3080 3081 usb3_dwc3: usb@6a00000 { 3082 compatible = "snps,dwc3"; 3083 reg = <0x06a00000 0xcc00>; 3084 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 3085 phys = <&hsusb_phy1>, <&usb3phy>; 3086 phy-names = "usb2-phy", "usb3-phy"; 3087 snps,hird-threshold = /bits/ 8 <0>; 3088 snps,dis_u2_susphy_quirk; 3089 snps,dis_enblslpm_quirk; 3090 snps,is-utmi-l1-suspend; 3091 tx-fifo-resize; 3092 }; 3093 }; 3094 3095 usb3phy: phy@7410000 { 3096 compatible = "qcom,msm8996-qmp-usb3-phy"; 3097 reg = <0x07410000 0x1000>; 3098 3099 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 3100 <&gcc GCC_USB3_CLKREF_CLK>, 3101 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3102 <&gcc GCC_USB3_PHY_PIPE_CLK>; 3103 clock-names = "aux", 3104 "ref", 3105 "cfg_ahb", 3106 "pipe"; 3107 clock-output-names = "usb3_phy_pipe_clk_src"; 3108 #clock-cells = <0>; 3109 #phy-cells = <0>; 3110 3111 resets = <&gcc GCC_USB3_PHY_BCR>, 3112 <&gcc GCC_USB3PHY_PHY_BCR>; 3113 reset-names = "phy", 3114 "phy_phy"; 3115 3116 status = "disabled"; 3117 }; 3118 3119 hsusb_phy1: phy@7411000 { 3120 compatible = "qcom,msm8996-qusb2-phy"; 3121 reg = <0x07411000 0x180>; 3122 #phy-cells = <0>; 3123 3124 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3125 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3126 clock-names = "cfg_ahb", "ref"; 3127 3128 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3129 nvmem-cells = <&qusb2p_hstx_trim>; 3130 status = "disabled"; 3131 }; 3132 3133 hsusb_phy2: phy@7412000 { 3134 compatible = "qcom,msm8996-qusb2-phy"; 3135 reg = <0x07412000 0x180>; 3136 #phy-cells = <0>; 3137 3138 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3139 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3140 clock-names = "cfg_ahb", "ref"; 3141 3142 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3143 nvmem-cells = <&qusb2s_hstx_trim>; 3144 status = "disabled"; 3145 }; 3146 3147 sdhc1: mmc@7464900 { 3148 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3149 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3150 reg-names = "hc", "core"; 3151 3152 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3154 interrupt-names = "hc_irq", "pwr_irq"; 3155 3156 clock-names = "iface", "core", "xo"; 3157 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3158 <&gcc GCC_SDCC1_APPS_CLK>, 3159 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3160 resets = <&gcc GCC_SDCC1_BCR>; 3161 3162 pinctrl-names = "default", "sleep"; 3163 pinctrl-0 = <&sdc1_state_on>; 3164 pinctrl-1 = <&sdc1_state_off>; 3165 3166 bus-width = <8>; 3167 non-removable; 3168 status = "disabled"; 3169 }; 3170 3171 sdhc2: mmc@74a4900 { 3172 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3173 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3174 reg-names = "hc", "core"; 3175 3176 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3178 interrupt-names = "hc_irq", "pwr_irq"; 3179 3180 clock-names = "iface", "core", "xo"; 3181 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3182 <&gcc GCC_SDCC2_APPS_CLK>, 3183 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3184 resets = <&gcc GCC_SDCC2_BCR>; 3185 3186 pinctrl-names = "default", "sleep"; 3187 pinctrl-0 = <&sdc2_state_on>; 3188 pinctrl-1 = <&sdc2_state_off>; 3189 3190 bus-width = <4>; 3191 status = "disabled"; 3192 }; 3193 3194 blsp1_dma: dma-controller@7544000 { 3195 compatible = "qcom,bam-v1.7.0"; 3196 reg = <0x07544000 0x2b000>; 3197 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3198 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3199 clock-names = "bam_clk"; 3200 qcom,controlled-remotely; 3201 #dma-cells = <1>; 3202 qcom,ee = <0>; 3203 }; 3204 3205 blsp1_uart2: serial@7570000 { 3206 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3207 reg = <0x07570000 0x1000>; 3208 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3209 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3210 <&gcc GCC_BLSP1_AHB_CLK>; 3211 clock-names = "core", "iface"; 3212 pinctrl-names = "default", "sleep"; 3213 pinctrl-0 = <&blsp1_uart2_default>; 3214 pinctrl-1 = <&blsp1_uart2_sleep>; 3215 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3216 dma-names = "tx", "rx"; 3217 status = "disabled"; 3218 }; 3219 3220 blsp1_spi1: spi@7575000 { 3221 compatible = "qcom,spi-qup-v2.2.1"; 3222 reg = <0x07575000 0x600>; 3223 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3224 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3225 <&gcc GCC_BLSP1_AHB_CLK>; 3226 clock-names = "core", "iface"; 3227 pinctrl-names = "default", "sleep"; 3228 pinctrl-0 = <&blsp1_spi1_default>; 3229 pinctrl-1 = <&blsp1_spi1_sleep>; 3230 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3231 dma-names = "tx", "rx"; 3232 #address-cells = <1>; 3233 #size-cells = <0>; 3234 status = "disabled"; 3235 }; 3236 3237 blsp1_i2c3: i2c@7577000 { 3238 compatible = "qcom,i2c-qup-v2.2.1"; 3239 reg = <0x07577000 0x1000>; 3240 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3241 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3242 <&gcc GCC_BLSP1_AHB_CLK>; 3243 clock-names = "core", "iface"; 3244 pinctrl-names = "default", "sleep"; 3245 pinctrl-0 = <&blsp1_i2c3_default>; 3246 pinctrl-1 = <&blsp1_i2c3_sleep>; 3247 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3248 dma-names = "tx", "rx"; 3249 #address-cells = <1>; 3250 #size-cells = <0>; 3251 status = "disabled"; 3252 }; 3253 3254 blsp1_i2c6: i2c@757a000 { 3255 compatible = "qcom,i2c-qup-v2.2.1"; 3256 reg = <0x757a000 0x1000>; 3257 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3258 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 3259 <&gcc GCC_BLSP1_AHB_CLK>; 3260 clock-names = "core", "iface"; 3261 pinctrl-names = "default", "sleep"; 3262 pinctrl-0 = <&blsp1_i2c6_default>; 3263 pinctrl-1 = <&blsp1_i2c6_sleep>; 3264 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 3265 dma-names = "tx", "rx"; 3266 #address-cells = <1>; 3267 #size-cells = <0>; 3268 status = "disabled"; 3269 }; 3270 3271 blsp2_dma: dma-controller@7584000 { 3272 compatible = "qcom,bam-v1.7.0"; 3273 reg = <0x07584000 0x2b000>; 3274 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3275 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3276 clock-names = "bam_clk"; 3277 qcom,controlled-remotely; 3278 #dma-cells = <1>; 3279 qcom,ee = <0>; 3280 }; 3281 3282 blsp2_uart2: serial@75b0000 { 3283 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3284 reg = <0x075b0000 0x1000>; 3285 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3286 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3287 <&gcc GCC_BLSP2_AHB_CLK>; 3288 clock-names = "core", "iface"; 3289 status = "disabled"; 3290 }; 3291 3292 blsp2_uart3: serial@75b1000 { 3293 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3294 reg = <0x075b1000 0x1000>; 3295 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3296 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3297 <&gcc GCC_BLSP2_AHB_CLK>; 3298 clock-names = "core", "iface"; 3299 status = "disabled"; 3300 }; 3301 3302 blsp2_i2c1: i2c@75b5000 { 3303 compatible = "qcom,i2c-qup-v2.2.1"; 3304 reg = <0x075b5000 0x1000>; 3305 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3306 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3307 <&gcc GCC_BLSP2_AHB_CLK>; 3308 clock-names = "core", "iface"; 3309 pinctrl-names = "default", "sleep"; 3310 pinctrl-0 = <&blsp2_i2c1_default>; 3311 pinctrl-1 = <&blsp2_i2c1_sleep>; 3312 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3313 dma-names = "tx", "rx"; 3314 #address-cells = <1>; 3315 #size-cells = <0>; 3316 status = "disabled"; 3317 }; 3318 3319 blsp2_i2c2: i2c@75b6000 { 3320 compatible = "qcom,i2c-qup-v2.2.1"; 3321 reg = <0x075b6000 0x1000>; 3322 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3323 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3324 <&gcc GCC_BLSP2_AHB_CLK>; 3325 clock-names = "core", "iface"; 3326 pinctrl-names = "default", "sleep"; 3327 pinctrl-0 = <&blsp2_i2c2_default>; 3328 pinctrl-1 = <&blsp2_i2c2_sleep>; 3329 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3330 dma-names = "tx", "rx"; 3331 #address-cells = <1>; 3332 #size-cells = <0>; 3333 status = "disabled"; 3334 }; 3335 3336 blsp2_i2c3: i2c@75b7000 { 3337 compatible = "qcom,i2c-qup-v2.2.1"; 3338 reg = <0x075b7000 0x1000>; 3339 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3340 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3341 <&gcc GCC_BLSP2_AHB_CLK>; 3342 clock-names = "core", "iface"; 3343 clock-frequency = <400000>; 3344 pinctrl-names = "default", "sleep"; 3345 pinctrl-0 = <&blsp2_i2c3_default>; 3346 pinctrl-1 = <&blsp2_i2c3_sleep>; 3347 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3348 dma-names = "tx", "rx"; 3349 #address-cells = <1>; 3350 #size-cells = <0>; 3351 status = "disabled"; 3352 }; 3353 3354 blsp2_i2c5: i2c@75b9000 { 3355 compatible = "qcom,i2c-qup-v2.2.1"; 3356 reg = <0x75b9000 0x1000>; 3357 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3358 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3359 <&gcc GCC_BLSP2_AHB_CLK>; 3360 clock-names = "core", "iface"; 3361 pinctrl-names = "default"; 3362 pinctrl-0 = <&blsp2_i2c5_default>; 3363 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3364 dma-names = "tx", "rx"; 3365 #address-cells = <1>; 3366 #size-cells = <0>; 3367 status = "disabled"; 3368 }; 3369 3370 blsp2_i2c6: i2c@75ba000 { 3371 compatible = "qcom,i2c-qup-v2.2.1"; 3372 reg = <0x75ba000 0x1000>; 3373 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3374 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3375 <&gcc GCC_BLSP2_AHB_CLK>; 3376 clock-names = "core", "iface"; 3377 pinctrl-names = "default", "sleep"; 3378 pinctrl-0 = <&blsp2_i2c6_default>; 3379 pinctrl-1 = <&blsp2_i2c6_sleep>; 3380 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3381 dma-names = "tx", "rx"; 3382 #address-cells = <1>; 3383 #size-cells = <0>; 3384 status = "disabled"; 3385 }; 3386 3387 blsp2_spi6: spi@75ba000 { 3388 compatible = "qcom,spi-qup-v2.2.1"; 3389 reg = <0x075ba000 0x600>; 3390 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3391 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3392 <&gcc GCC_BLSP2_AHB_CLK>; 3393 clock-names = "core", "iface"; 3394 pinctrl-names = "default", "sleep"; 3395 pinctrl-0 = <&blsp2_spi6_default>; 3396 pinctrl-1 = <&blsp2_spi6_sleep>; 3397 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3398 dma-names = "tx", "rx"; 3399 #address-cells = <1>; 3400 #size-cells = <0>; 3401 status = "disabled"; 3402 }; 3403 3404 usb2: usb@76f8800 { 3405 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3406 reg = <0x076f8800 0x400>; 3407 #address-cells = <1>; 3408 #size-cells = <1>; 3409 ranges; 3410 3411 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 3412 interrupt-names = "hs_phy_irq"; 3413 3414 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3415 <&gcc GCC_USB20_MASTER_CLK>, 3416 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3417 <&gcc GCC_USB20_SLEEP_CLK>, 3418 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3419 clock-names = "cfg_noc", 3420 "core", 3421 "iface", 3422 "sleep", 3423 "mock_utmi"; 3424 3425 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3426 <&gcc GCC_USB20_MASTER_CLK>; 3427 assigned-clock-rates = <19200000>, <60000000>; 3428 3429 power-domains = <&gcc USB30_GDSC>; 3430 qcom,select-utmi-as-pipe-clk; 3431 status = "disabled"; 3432 3433 usb2_dwc3: usb@7600000 { 3434 compatible = "snps,dwc3"; 3435 reg = <0x07600000 0xcc00>; 3436 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3437 phys = <&hsusb_phy2>; 3438 phy-names = "usb2-phy"; 3439 maximum-speed = "high-speed"; 3440 snps,dis_u2_susphy_quirk; 3441 snps,dis_enblslpm_quirk; 3442 }; 3443 }; 3444 3445 slimbam: dma-controller@9184000 { 3446 compatible = "qcom,bam-v1.7.0"; 3447 qcom,controlled-remotely; 3448 reg = <0x09184000 0x32000>; 3449 num-channels = <31>; 3450 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 3451 #dma-cells = <1>; 3452 qcom,ee = <1>; 3453 qcom,num-ees = <2>; 3454 }; 3455 3456 slim_msm: slim-ngd@91c0000 { 3457 compatible = "qcom,slim-ngd-v1.5.0"; 3458 reg = <0x091c0000 0x2c000>; 3459 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3460 dmas = <&slimbam 3>, <&slimbam 4>; 3461 dma-names = "rx", "tx"; 3462 #address-cells = <1>; 3463 #size-cells = <0>; 3464 3465 status = "disabled"; 3466 }; 3467 3468 adsp_pil: remoteproc@9300000 { 3469 compatible = "qcom,msm8996-adsp-pil"; 3470 reg = <0x09300000 0x80000>; 3471 3472 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3473 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3474 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3475 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3476 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3477 interrupt-names = "wdog", "fatal", "ready", 3478 "handover", "stop-ack"; 3479 3480 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3481 clock-names = "xo"; 3482 3483 memory-region = <&adsp_mem>; 3484 3485 qcom,smem-states = <&adsp_smp2p_out 0>; 3486 qcom,smem-state-names = "stop"; 3487 3488 power-domains = <&rpmpd MSM8996_VDDCX>; 3489 power-domain-names = "cx"; 3490 3491 status = "disabled"; 3492 3493 smd-edge { 3494 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3495 3496 label = "lpass"; 3497 mboxes = <&apcs_glb 8>; 3498 qcom,smd-edge = <1>; 3499 qcom,remote-pid = <2>; 3500 3501 apr { 3502 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3503 compatible = "qcom,apr-v2"; 3504 qcom,smd-channels = "apr_audio_svc"; 3505 qcom,domain = <APR_DOMAIN_ADSP>; 3506 #address-cells = <1>; 3507 #size-cells = <0>; 3508 3509 service@3 { 3510 reg = <APR_SVC_ADSP_CORE>; 3511 compatible = "qcom,q6core"; 3512 }; 3513 3514 q6afe: service@4 { 3515 compatible = "qcom,q6afe"; 3516 reg = <APR_SVC_AFE>; 3517 q6afedai: dais { 3518 compatible = "qcom,q6afe-dais"; 3519 #address-cells = <1>; 3520 #size-cells = <0>; 3521 #sound-dai-cells = <1>; 3522 dai@1 { 3523 reg = <1>; 3524 }; 3525 }; 3526 }; 3527 3528 q6asm: service@7 { 3529 compatible = "qcom,q6asm"; 3530 reg = <APR_SVC_ASM>; 3531 q6asmdai: dais { 3532 compatible = "qcom,q6asm-dais"; 3533 #address-cells = <1>; 3534 #size-cells = <0>; 3535 #sound-dai-cells = <1>; 3536 iommus = <&lpass_q6_smmu 1>; 3537 }; 3538 }; 3539 3540 q6adm: service@8 { 3541 compatible = "qcom,q6adm"; 3542 reg = <APR_SVC_ADM>; 3543 q6routing: routing { 3544 compatible = "qcom,q6adm-routing"; 3545 #sound-dai-cells = <0>; 3546 }; 3547 }; 3548 }; 3549 }; 3550 }; 3551 3552 apcs_glb: mailbox@9820000 { 3553 compatible = "qcom,msm8996-apcs-hmss-global"; 3554 reg = <0x09820000 0x1000>; 3555 3556 #mbox-cells = <1>; 3557 #clock-cells = <0>; 3558 }; 3559 3560 timer@9840000 { 3561 #address-cells = <1>; 3562 #size-cells = <1>; 3563 ranges; 3564 compatible = "arm,armv7-timer-mem"; 3565 reg = <0x09840000 0x1000>; 3566 clock-frequency = <19200000>; 3567 3568 frame@9850000 { 3569 frame-number = <0>; 3570 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3571 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3572 reg = <0x09850000 0x1000>, 3573 <0x09860000 0x1000>; 3574 }; 3575 3576 frame@9870000 { 3577 frame-number = <1>; 3578 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3579 reg = <0x09870000 0x1000>; 3580 status = "disabled"; 3581 }; 3582 3583 frame@9880000 { 3584 frame-number = <2>; 3585 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3586 reg = <0x09880000 0x1000>; 3587 status = "disabled"; 3588 }; 3589 3590 frame@9890000 { 3591 frame-number = <3>; 3592 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3593 reg = <0x09890000 0x1000>; 3594 status = "disabled"; 3595 }; 3596 3597 frame@98a0000 { 3598 frame-number = <4>; 3599 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3600 reg = <0x098a0000 0x1000>; 3601 status = "disabled"; 3602 }; 3603 3604 frame@98b0000 { 3605 frame-number = <5>; 3606 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3607 reg = <0x098b0000 0x1000>; 3608 status = "disabled"; 3609 }; 3610 3611 frame@98c0000 { 3612 frame-number = <6>; 3613 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3614 reg = <0x098c0000 0x1000>; 3615 status = "disabled"; 3616 }; 3617 }; 3618 3619 saw3: syscon@9a10000 { 3620 compatible = "syscon"; 3621 reg = <0x09a10000 0x1000>; 3622 }; 3623 3624 cbf: clock-controller@9a11000 { 3625 compatible = "qcom,msm8996-cbf"; 3626 reg = <0x09a11000 0x10000>; 3627 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3628 #clock-cells = <0>; 3629 #interconnect-cells = <1>; 3630 }; 3631 3632 intc: interrupt-controller@9bc0000 { 3633 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3634 #interrupt-cells = <3>; 3635 interrupt-controller; 3636 #redistributor-regions = <1>; 3637 redistributor-stride = <0x0 0x40000>; 3638 reg = <0x09bc0000 0x10000>, 3639 <0x09c00000 0x100000>; 3640 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3641 }; 3642 }; 3643 3644 sound: sound { 3645 }; 3646 3647 thermal-zones { 3648 cpu0-thermal { 3649 polling-delay-passive = <250>; 3650 polling-delay = <1000>; 3651 3652 thermal-sensors = <&tsens0 3>; 3653 3654 trips { 3655 cpu0_alert0: trip-point0 { 3656 temperature = <75000>; 3657 hysteresis = <2000>; 3658 type = "passive"; 3659 }; 3660 3661 cpu0_crit: cpu-crit { 3662 temperature = <110000>; 3663 hysteresis = <2000>; 3664 type = "critical"; 3665 }; 3666 }; 3667 }; 3668 3669 cpu1-thermal { 3670 polling-delay-passive = <250>; 3671 polling-delay = <1000>; 3672 3673 thermal-sensors = <&tsens0 5>; 3674 3675 trips { 3676 cpu1_alert0: trip-point0 { 3677 temperature = <75000>; 3678 hysteresis = <2000>; 3679 type = "passive"; 3680 }; 3681 3682 cpu1_crit: cpu-crit { 3683 temperature = <110000>; 3684 hysteresis = <2000>; 3685 type = "critical"; 3686 }; 3687 }; 3688 }; 3689 3690 cpu2-thermal { 3691 polling-delay-passive = <250>; 3692 polling-delay = <1000>; 3693 3694 thermal-sensors = <&tsens0 8>; 3695 3696 trips { 3697 cpu2_alert0: trip-point0 { 3698 temperature = <75000>; 3699 hysteresis = <2000>; 3700 type = "passive"; 3701 }; 3702 3703 cpu2_crit: cpu-crit { 3704 temperature = <110000>; 3705 hysteresis = <2000>; 3706 type = "critical"; 3707 }; 3708 }; 3709 }; 3710 3711 cpu3-thermal { 3712 polling-delay-passive = <250>; 3713 polling-delay = <1000>; 3714 3715 thermal-sensors = <&tsens0 10>; 3716 3717 trips { 3718 cpu3_alert0: trip-point0 { 3719 temperature = <75000>; 3720 hysteresis = <2000>; 3721 type = "passive"; 3722 }; 3723 3724 cpu3_crit: cpu-crit { 3725 temperature = <110000>; 3726 hysteresis = <2000>; 3727 type = "critical"; 3728 }; 3729 }; 3730 }; 3731 3732 gpu-top-thermal { 3733 polling-delay-passive = <250>; 3734 polling-delay = <1000>; 3735 3736 thermal-sensors = <&tsens1 6>; 3737 3738 trips { 3739 gpu1_alert0: trip-point0 { 3740 temperature = <90000>; 3741 hysteresis = <2000>; 3742 type = "passive"; 3743 }; 3744 }; 3745 3746 cooling-maps { 3747 map0 { 3748 trip = <&gpu1_alert0>; 3749 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3750 }; 3751 }; 3752 }; 3753 3754 gpu-bottom-thermal { 3755 polling-delay-passive = <250>; 3756 polling-delay = <1000>; 3757 3758 thermal-sensors = <&tsens1 7>; 3759 3760 trips { 3761 gpu2_alert0: trip-point0 { 3762 temperature = <90000>; 3763 hysteresis = <2000>; 3764 type = "passive"; 3765 }; 3766 }; 3767 3768 cooling-maps { 3769 map0 { 3770 trip = <&gpu2_alert0>; 3771 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3772 }; 3773 }; 3774 }; 3775 3776 m4m-thermal { 3777 polling-delay-passive = <250>; 3778 polling-delay = <1000>; 3779 3780 thermal-sensors = <&tsens0 1>; 3781 3782 trips { 3783 m4m_alert0: trip-point0 { 3784 temperature = <90000>; 3785 hysteresis = <2000>; 3786 type = "hot"; 3787 }; 3788 }; 3789 }; 3790 3791 l3-or-venus-thermal { 3792 polling-delay-passive = <250>; 3793 polling-delay = <1000>; 3794 3795 thermal-sensors = <&tsens0 2>; 3796 3797 trips { 3798 l3_or_venus_alert0: trip-point0 { 3799 temperature = <90000>; 3800 hysteresis = <2000>; 3801 type = "hot"; 3802 }; 3803 }; 3804 }; 3805 3806 cluster0-l2-thermal { 3807 polling-delay-passive = <250>; 3808 polling-delay = <1000>; 3809 3810 thermal-sensors = <&tsens0 7>; 3811 3812 trips { 3813 cluster0_l2_alert0: trip-point0 { 3814 temperature = <90000>; 3815 hysteresis = <2000>; 3816 type = "hot"; 3817 }; 3818 }; 3819 }; 3820 3821 cluster1-l2-thermal { 3822 polling-delay-passive = <250>; 3823 polling-delay = <1000>; 3824 3825 thermal-sensors = <&tsens0 12>; 3826 3827 trips { 3828 cluster1_l2_alert0: trip-point0 { 3829 temperature = <90000>; 3830 hysteresis = <2000>; 3831 type = "hot"; 3832 }; 3833 }; 3834 }; 3835 3836 camera-thermal { 3837 polling-delay-passive = <250>; 3838 polling-delay = <1000>; 3839 3840 thermal-sensors = <&tsens1 1>; 3841 3842 trips { 3843 camera_alert0: trip-point0 { 3844 temperature = <90000>; 3845 hysteresis = <2000>; 3846 type = "hot"; 3847 }; 3848 }; 3849 }; 3850 3851 q6-dsp-thermal { 3852 polling-delay-passive = <250>; 3853 polling-delay = <1000>; 3854 3855 thermal-sensors = <&tsens1 2>; 3856 3857 trips { 3858 q6_dsp_alert0: trip-point0 { 3859 temperature = <90000>; 3860 hysteresis = <2000>; 3861 type = "hot"; 3862 }; 3863 }; 3864 }; 3865 3866 mem-thermal { 3867 polling-delay-passive = <250>; 3868 polling-delay = <1000>; 3869 3870 thermal-sensors = <&tsens1 3>; 3871 3872 trips { 3873 mem_alert0: trip-point0 { 3874 temperature = <90000>; 3875 hysteresis = <2000>; 3876 type = "hot"; 3877 }; 3878 }; 3879 }; 3880 3881 modemtx-thermal { 3882 polling-delay-passive = <250>; 3883 polling-delay = <1000>; 3884 3885 thermal-sensors = <&tsens1 4>; 3886 3887 trips { 3888 modemtx_alert0: trip-point0 { 3889 temperature = <90000>; 3890 hysteresis = <2000>; 3891 type = "hot"; 3892 }; 3893 }; 3894 }; 3895 }; 3896 3897 timer { 3898 compatible = "arm,armv8-timer"; 3899 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3900 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3901 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3902 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3903 }; 3904}; 3905