1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 8#include <dt-bindings/clock/qcom,gcc-msm8996.h> 9#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/interconnect/qcom,msm8996.h> 12#include <dt-bindings/interconnect/qcom,msm8996-cbf.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,apr.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <19200000>; 32 clock-output-names = "xo_board"; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 clock-output-names = "sleep_clk"; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo"; 50 reg = <0x0 0x0>; 51 enable-method = "psci"; 52 cpu-idle-states = <&cpu_sleep_0>; 53 capacity-dmips-mhz = <1024>; 54 clocks = <&kryocc 0>; 55 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 56 operating-points-v2 = <&cluster0_opp>; 57 #cooling-cells = <2>; 58 next-level-cache = <&l2_0>; 59 l2_0: l2-cache { 60 compatible = "cache"; 61 cache-level = <2>; 62 cache-unified; 63 }; 64 }; 65 66 cpu1: cpu@1 { 67 device_type = "cpu"; 68 compatible = "qcom,kryo"; 69 reg = <0x0 0x1>; 70 enable-method = "psci"; 71 cpu-idle-states = <&cpu_sleep_0>; 72 capacity-dmips-mhz = <1024>; 73 clocks = <&kryocc 0>; 74 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 75 operating-points-v2 = <&cluster0_opp>; 76 #cooling-cells = <2>; 77 next-level-cache = <&l2_0>; 78 }; 79 80 cpu2: cpu@100 { 81 device_type = "cpu"; 82 compatible = "qcom,kryo"; 83 reg = <0x0 0x100>; 84 enable-method = "psci"; 85 cpu-idle-states = <&cpu_sleep_0>; 86 capacity-dmips-mhz = <1024>; 87 clocks = <&kryocc 1>; 88 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 89 operating-points-v2 = <&cluster1_opp>; 90 #cooling-cells = <2>; 91 next-level-cache = <&l2_1>; 92 l2_1: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 }; 97 }; 98 99 cpu3: cpu@101 { 100 device_type = "cpu"; 101 compatible = "qcom,kryo"; 102 reg = <0x0 0x101>; 103 enable-method = "psci"; 104 cpu-idle-states = <&cpu_sleep_0>; 105 capacity-dmips-mhz = <1024>; 106 clocks = <&kryocc 1>; 107 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 108 operating-points-v2 = <&cluster1_opp>; 109 #cooling-cells = <2>; 110 next-level-cache = <&l2_1>; 111 }; 112 113 cpu-map { 114 cluster0 { 115 core0 { 116 cpu = <&cpu0>; 117 }; 118 119 core1 { 120 cpu = <&cpu1>; 121 }; 122 }; 123 124 cluster1 { 125 core0 { 126 cpu = <&cpu2>; 127 }; 128 129 core1 { 130 cpu = <&cpu3>; 131 }; 132 }; 133 }; 134 135 idle-states { 136 entry-method = "psci"; 137 138 cpu_sleep_0: cpu-sleep-0 { 139 compatible = "arm,idle-state"; 140 idle-state-name = "standalone-power-collapse"; 141 arm,psci-suspend-param = <0x00000004>; 142 entry-latency-us = <130>; 143 exit-latency-us = <80>; 144 min-residency-us = <300>; 145 }; 146 }; 147 }; 148 149 cluster0_opp: opp-table-cluster0 { 150 compatible = "operating-points-v2-kryo-cpu"; 151 nvmem-cells = <&speedbin_efuse>; 152 opp-shared; 153 154 /* Nominal fmax for now */ 155 opp-307200000 { 156 opp-hz = /bits/ 64 <307200000>; 157 opp-supported-hw = <0xf>; 158 clock-latency-ns = <200000>; 159 opp-peak-kBps = <307200>; 160 }; 161 opp-422400000 { 162 opp-hz = /bits/ 64 <422400000>; 163 opp-supported-hw = <0xf>; 164 clock-latency-ns = <200000>; 165 opp-peak-kBps = <307200>; 166 }; 167 opp-480000000 { 168 opp-hz = /bits/ 64 <480000000>; 169 opp-supported-hw = <0xf>; 170 clock-latency-ns = <200000>; 171 opp-peak-kBps = <307200>; 172 }; 173 opp-556800000 { 174 opp-hz = /bits/ 64 <556800000>; 175 opp-supported-hw = <0xf>; 176 clock-latency-ns = <200000>; 177 opp-peak-kBps = <307200>; 178 }; 179 opp-652800000 { 180 opp-hz = /bits/ 64 <652800000>; 181 opp-supported-hw = <0xf>; 182 clock-latency-ns = <200000>; 183 opp-peak-kBps = <384000>; 184 }; 185 opp-729600000 { 186 opp-hz = /bits/ 64 <729600000>; 187 opp-supported-hw = <0xf>; 188 clock-latency-ns = <200000>; 189 opp-peak-kBps = <460800>; 190 }; 191 opp-844800000 { 192 opp-hz = /bits/ 64 <844800000>; 193 opp-supported-hw = <0xf>; 194 clock-latency-ns = <200000>; 195 opp-peak-kBps = <537600>; 196 }; 197 opp-960000000 { 198 opp-hz = /bits/ 64 <960000000>; 199 opp-supported-hw = <0xf>; 200 clock-latency-ns = <200000>; 201 opp-peak-kBps = <672000>; 202 }; 203 opp-1036800000 { 204 opp-hz = /bits/ 64 <1036800000>; 205 opp-supported-hw = <0xf>; 206 clock-latency-ns = <200000>; 207 opp-peak-kBps = <672000>; 208 }; 209 opp-1113600000 { 210 opp-hz = /bits/ 64 <1113600000>; 211 opp-supported-hw = <0xf>; 212 clock-latency-ns = <200000>; 213 opp-peak-kBps = <825600>; 214 }; 215 opp-1190400000 { 216 opp-hz = /bits/ 64 <1190400000>; 217 opp-supported-hw = <0xf>; 218 clock-latency-ns = <200000>; 219 opp-peak-kBps = <825600>; 220 }; 221 opp-1228800000 { 222 opp-hz = /bits/ 64 <1228800000>; 223 opp-supported-hw = <0xf>; 224 clock-latency-ns = <200000>; 225 opp-peak-kBps = <902400>; 226 }; 227 opp-1324800000 { 228 opp-hz = /bits/ 64 <1324800000>; 229 opp-supported-hw = <0xd>; 230 clock-latency-ns = <200000>; 231 opp-peak-kBps = <1056000>; 232 }; 233 opp-1363200000 { 234 opp-hz = /bits/ 64 <1363200000>; 235 opp-supported-hw = <0x2>; 236 clock-latency-ns = <200000>; 237 opp-peak-kBps = <1132800>; 238 }; 239 opp-1401600000 { 240 opp-hz = /bits/ 64 <1401600000>; 241 opp-supported-hw = <0xd>; 242 clock-latency-ns = <200000>; 243 opp-peak-kBps = <1132800>; 244 }; 245 opp-1478400000 { 246 opp-hz = /bits/ 64 <1478400000>; 247 opp-supported-hw = <0x9>; 248 clock-latency-ns = <200000>; 249 opp-peak-kBps = <1190400>; 250 }; 251 opp-1497600000 { 252 opp-hz = /bits/ 64 <1497600000>; 253 opp-supported-hw = <0x04>; 254 clock-latency-ns = <200000>; 255 opp-peak-kBps = <1305600>; 256 }; 257 opp-1593600000 { 258 opp-hz = /bits/ 64 <1593600000>; 259 opp-supported-hw = <0x9>; 260 clock-latency-ns = <200000>; 261 opp-peak-kBps = <1382400>; 262 }; 263 }; 264 265 cluster1_opp: opp-table-cluster1 { 266 compatible = "operating-points-v2-kryo-cpu"; 267 nvmem-cells = <&speedbin_efuse>; 268 opp-shared; 269 270 /* Nominal fmax for now */ 271 opp-307200000 { 272 opp-hz = /bits/ 64 <307200000>; 273 opp-supported-hw = <0xf>; 274 clock-latency-ns = <200000>; 275 opp-peak-kBps = <307200>; 276 }; 277 opp-403200000 { 278 opp-hz = /bits/ 64 <403200000>; 279 opp-supported-hw = <0xf>; 280 clock-latency-ns = <200000>; 281 opp-peak-kBps = <307200>; 282 }; 283 opp-480000000 { 284 opp-hz = /bits/ 64 <480000000>; 285 opp-supported-hw = <0xf>; 286 clock-latency-ns = <200000>; 287 opp-peak-kBps = <307200>; 288 }; 289 opp-556800000 { 290 opp-hz = /bits/ 64 <556800000>; 291 opp-supported-hw = <0xf>; 292 clock-latency-ns = <200000>; 293 opp-peak-kBps = <307200>; 294 }; 295 opp-652800000 { 296 opp-hz = /bits/ 64 <652800000>; 297 opp-supported-hw = <0xf>; 298 clock-latency-ns = <200000>; 299 opp-peak-kBps = <307200>; 300 }; 301 opp-729600000 { 302 opp-hz = /bits/ 64 <729600000>; 303 opp-supported-hw = <0xf>; 304 clock-latency-ns = <200000>; 305 opp-peak-kBps = <307200>; 306 }; 307 opp-806400000 { 308 opp-hz = /bits/ 64 <806400000>; 309 opp-supported-hw = <0xf>; 310 clock-latency-ns = <200000>; 311 opp-peak-kBps = <384000>; 312 }; 313 opp-883200000 { 314 opp-hz = /bits/ 64 <883200000>; 315 opp-supported-hw = <0xf>; 316 clock-latency-ns = <200000>; 317 opp-peak-kBps = <460800>; 318 }; 319 opp-940800000 { 320 opp-hz = /bits/ 64 <940800000>; 321 opp-supported-hw = <0xf>; 322 clock-latency-ns = <200000>; 323 opp-peak-kBps = <537600>; 324 }; 325 opp-1036800000 { 326 opp-hz = /bits/ 64 <1036800000>; 327 opp-supported-hw = <0xf>; 328 clock-latency-ns = <200000>; 329 opp-peak-kBps = <595200>; 330 }; 331 opp-1113600000 { 332 opp-hz = /bits/ 64 <1113600000>; 333 opp-supported-hw = <0xf>; 334 clock-latency-ns = <200000>; 335 opp-peak-kBps = <672000>; 336 }; 337 opp-1190400000 { 338 opp-hz = /bits/ 64 <1190400000>; 339 opp-supported-hw = <0xf>; 340 clock-latency-ns = <200000>; 341 opp-peak-kBps = <672000>; 342 }; 343 opp-1248000000 { 344 opp-hz = /bits/ 64 <1248000000>; 345 opp-supported-hw = <0xf>; 346 clock-latency-ns = <200000>; 347 opp-peak-kBps = <748800>; 348 }; 349 opp-1324800000 { 350 opp-hz = /bits/ 64 <1324800000>; 351 opp-supported-hw = <0xf>; 352 clock-latency-ns = <200000>; 353 opp-peak-kBps = <825600>; 354 }; 355 opp-1401600000 { 356 opp-hz = /bits/ 64 <1401600000>; 357 opp-supported-hw = <0xf>; 358 clock-latency-ns = <200000>; 359 opp-peak-kBps = <902400>; 360 }; 361 opp-1478400000 { 362 opp-hz = /bits/ 64 <1478400000>; 363 opp-supported-hw = <0xf>; 364 clock-latency-ns = <200000>; 365 opp-peak-kBps = <979200>; 366 }; 367 opp-1555200000 { 368 opp-hz = /bits/ 64 <1555200000>; 369 opp-supported-hw = <0xf>; 370 clock-latency-ns = <200000>; 371 opp-peak-kBps = <1056000>; 372 }; 373 opp-1632000000 { 374 opp-hz = /bits/ 64 <1632000000>; 375 opp-supported-hw = <0xf>; 376 clock-latency-ns = <200000>; 377 opp-peak-kBps = <1190400>; 378 }; 379 opp-1708800000 { 380 opp-hz = /bits/ 64 <1708800000>; 381 opp-supported-hw = <0xf>; 382 clock-latency-ns = <200000>; 383 opp-peak-kBps = <1228800>; 384 }; 385 opp-1785600000 { 386 opp-hz = /bits/ 64 <1785600000>; 387 opp-supported-hw = <0xf>; 388 clock-latency-ns = <200000>; 389 opp-peak-kBps = <1305600>; 390 }; 391 opp-1804800000 { 392 opp-hz = /bits/ 64 <1804800000>; 393 opp-supported-hw = <0xe>; 394 clock-latency-ns = <200000>; 395 opp-peak-kBps = <1305600>; 396 }; 397 opp-1824000000 { 398 opp-hz = /bits/ 64 <1824000000>; 399 opp-supported-hw = <0x1>; 400 clock-latency-ns = <200000>; 401 opp-peak-kBps = <1382400>; 402 }; 403 opp-1900800000 { 404 opp-hz = /bits/ 64 <1900800000>; 405 opp-supported-hw = <0x4>; 406 clock-latency-ns = <200000>; 407 opp-peak-kBps = <1305600>; 408 }; 409 opp-1920000000 { 410 opp-hz = /bits/ 64 <1920000000>; 411 opp-supported-hw = <0x1>; 412 clock-latency-ns = <200000>; 413 opp-peak-kBps = <1459200>; 414 }; 415 opp-1996800000 { 416 opp-hz = /bits/ 64 <1996800000>; 417 opp-supported-hw = <0x1>; 418 clock-latency-ns = <200000>; 419 opp-peak-kBps = <1593600>; 420 }; 421 opp-2073600000 { 422 opp-hz = /bits/ 64 <2073600000>; 423 opp-supported-hw = <0x1>; 424 clock-latency-ns = <200000>; 425 opp-peak-kBps = <1593600>; 426 }; 427 opp-2150400000 { 428 opp-hz = /bits/ 64 <2150400000>; 429 opp-supported-hw = <0x1>; 430 clock-latency-ns = <200000>; 431 opp-peak-kBps = <1593600>; 432 }; 433 }; 434 435 firmware { 436 scm { 437 compatible = "qcom,scm-msm8996", "qcom,scm"; 438 qcom,dload-mode = <&tcsr_2 0x13000>; 439 }; 440 }; 441 442 memory@80000000 { 443 device_type = "memory"; 444 /* We expect the bootloader to fill in the reg */ 445 reg = <0x0 0x80000000 0x0 0x0>; 446 }; 447 448 etm { 449 compatible = "qcom,coresight-remote-etm"; 450 451 out-ports { 452 port { 453 modem_etm_out_funnel_in2: endpoint { 454 remote-endpoint = 455 <&funnel_in2_in_modem_etm>; 456 }; 457 }; 458 }; 459 }; 460 461 psci { 462 compatible = "arm,psci-1.0"; 463 method = "smc"; 464 }; 465 466 rpm: remoteproc { 467 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc"; 468 469 glink-edge { 470 compatible = "qcom,glink-rpm"; 471 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 472 qcom,rpm-msg-ram = <&rpm_msg_ram>; 473 mboxes = <&apcs_glb 0>; 474 475 rpm_requests: rpm-requests { 476 compatible = "qcom,rpm-msm8996", "qcom,glink-smd-rpm"; 477 qcom,glink-channels = "rpm_requests"; 478 479 rpmcc: clock-controller { 480 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 481 #clock-cells = <1>; 482 clocks = <&xo_board>; 483 clock-names = "xo"; 484 }; 485 486 rpmpd: power-controller { 487 compatible = "qcom,msm8996-rpmpd"; 488 #power-domain-cells = <1>; 489 operating-points-v2 = <&rpmpd_opp_table>; 490 491 rpmpd_opp_table: opp-table { 492 compatible = "operating-points-v2"; 493 494 rpmpd_opp1: opp1 { 495 opp-level = <1>; 496 }; 497 498 rpmpd_opp2: opp2 { 499 opp-level = <2>; 500 }; 501 502 rpmpd_opp3: opp3 { 503 opp-level = <3>; 504 }; 505 506 rpmpd_opp4: opp4 { 507 opp-level = <4>; 508 }; 509 510 rpmpd_opp5: opp5 { 511 opp-level = <5>; 512 }; 513 514 rpmpd_opp6: opp6 { 515 opp-level = <6>; 516 }; 517 }; 518 }; 519 }; 520 }; 521 }; 522 523 reserved-memory { 524 #address-cells = <2>; 525 #size-cells = <2>; 526 ranges; 527 528 hyp_mem: memory@85800000 { 529 reg = <0x0 0x85800000 0x0 0x600000>; 530 no-map; 531 }; 532 533 xbl_mem: memory@85e00000 { 534 reg = <0x0 0x85e00000 0x0 0x200000>; 535 no-map; 536 }; 537 538 smem_mem: smem-mem@86000000 { 539 reg = <0x0 0x86000000 0x0 0x200000>; 540 no-map; 541 }; 542 543 tz_mem: memory@86200000 { 544 reg = <0x0 0x86200000 0x0 0x2600000>; 545 no-map; 546 }; 547 548 rmtfs_mem: rmtfs { 549 compatible = "qcom,rmtfs-mem"; 550 551 size = <0x0 0x200000>; 552 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 553 no-map; 554 555 qcom,client-id = <1>; 556 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 557 }; 558 559 mpss_mem: mpss@88800000 { 560 reg = <0x0 0x88800000 0x0 0x6200000>; 561 no-map; 562 }; 563 564 adsp_mem: adsp@8ea00000 { 565 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 566 no-map; 567 }; 568 569 slpi_mem: slpi@90500000 { 570 reg = <0x0 0x90500000 0x0 0xa00000>; 571 no-map; 572 }; 573 574 gpu_mem: gpu@90f00000 { 575 compatible = "shared-dma-pool"; 576 reg = <0x0 0x90f00000 0x0 0x100000>; 577 no-map; 578 }; 579 580 venus_mem: venus@91000000 { 581 reg = <0x0 0x91000000 0x0 0x500000>; 582 no-map; 583 }; 584 585 mba_mem: mba@91500000 { 586 reg = <0x0 0x91500000 0x0 0x200000>; 587 no-map; 588 }; 589 590 mdata_mem: mpss-metadata { 591 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 592 size = <0x0 0x4000>; 593 no-map; 594 }; 595 }; 596 597 smem { 598 compatible = "qcom,smem"; 599 memory-region = <&smem_mem>; 600 hwlocks = <&tcsr_mutex 3>; 601 }; 602 603 smp2p-adsp { 604 compatible = "qcom,smp2p"; 605 qcom,smem = <443>, <429>; 606 607 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 608 609 mboxes = <&apcs_glb 10>; 610 611 qcom,local-pid = <0>; 612 qcom,remote-pid = <2>; 613 614 adsp_smp2p_out: master-kernel { 615 qcom,entry-name = "master-kernel"; 616 #qcom,smem-state-cells = <1>; 617 }; 618 619 adsp_smp2p_in: slave-kernel { 620 qcom,entry-name = "slave-kernel"; 621 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 }; 625 }; 626 627 smp2p-mpss { 628 compatible = "qcom,smp2p"; 629 qcom,smem = <435>, <428>; 630 631 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 632 633 mboxes = <&apcs_glb 14>; 634 635 qcom,local-pid = <0>; 636 qcom,remote-pid = <1>; 637 638 mpss_smp2p_out: master-kernel { 639 qcom,entry-name = "master-kernel"; 640 #qcom,smem-state-cells = <1>; 641 }; 642 643 mpss_smp2p_in: slave-kernel { 644 qcom,entry-name = "slave-kernel"; 645 646 interrupt-controller; 647 #interrupt-cells = <2>; 648 }; 649 }; 650 651 smp2p-slpi { 652 compatible = "qcom,smp2p"; 653 qcom,smem = <481>, <430>; 654 655 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 656 657 mboxes = <&apcs_glb 26>; 658 659 qcom,local-pid = <0>; 660 qcom,remote-pid = <3>; 661 662 slpi_smp2p_out: master-kernel { 663 qcom,entry-name = "master-kernel"; 664 #qcom,smem-state-cells = <1>; 665 }; 666 667 slpi_smp2p_in: slave-kernel { 668 qcom,entry-name = "slave-kernel"; 669 670 interrupt-controller; 671 #interrupt-cells = <2>; 672 }; 673 }; 674 675 soc: soc@0 { 676 #address-cells = <1>; 677 #size-cells = <1>; 678 ranges = <0 0 0 0xffffffff>; 679 compatible = "simple-bus"; 680 681 pcie_phy: phy-wrapper@34000 { 682 compatible = "qcom,msm8996-qmp-pcie-phy"; 683 reg = <0x00034000 0x488>; 684 #address-cells = <1>; 685 #size-cells = <1>; 686 ranges = <0x0 0x00034000 0x4000>; 687 688 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 689 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 690 <&gcc GCC_PCIE_CLKREF_CLK>; 691 clock-names = "aux", "cfg_ahb", "ref"; 692 693 resets = <&gcc GCC_PCIE_PHY_BCR>, 694 <&gcc GCC_PCIE_PHY_COM_BCR>, 695 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 696 reset-names = "phy", "common", "cfg"; 697 698 status = "disabled"; 699 700 pciephy_0: phy@1000 { 701 reg = <0x1000 0x130>, 702 <0x1200 0x200>, 703 <0x1400 0x1dc>; 704 705 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 706 clock-names = "pipe0"; 707 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 708 reset-names = "lane0"; 709 710 #clock-cells = <0>; 711 clock-output-names = "pcie_0_pipe_clk_src"; 712 713 #phy-cells = <0>; 714 }; 715 716 pciephy_1: phy@2000 { 717 reg = <0x2000 0x130>, 718 <0x2200 0x200>, 719 <0x2400 0x1dc>; 720 721 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 722 clock-names = "pipe1"; 723 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 724 reset-names = "lane1"; 725 726 #clock-cells = <0>; 727 clock-output-names = "pcie_1_pipe_clk_src"; 728 729 #phy-cells = <0>; 730 }; 731 732 pciephy_2: phy@3000 { 733 reg = <0x3000 0x130>, 734 <0x3200 0x200>, 735 <0x3400 0x1dc>; 736 737 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 738 clock-names = "pipe2"; 739 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 740 reset-names = "lane2"; 741 742 #clock-cells = <0>; 743 clock-output-names = "pcie_2_pipe_clk_src"; 744 745 #phy-cells = <0>; 746 }; 747 }; 748 749 rpm_msg_ram: sram@68000 { 750 compatible = "qcom,rpm-msg-ram"; 751 reg = <0x00068000 0x6000>; 752 }; 753 754 qfprom@74000 { 755 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 756 reg = <0x00074000 0x8ff>; 757 #address-cells = <1>; 758 #size-cells = <1>; 759 760 qusb2p_hstx_trim: hstx-trim@24e { 761 reg = <0x24e 0x2>; 762 bits = <5 4>; 763 }; 764 765 qusb2s_hstx_trim: hstx-trim@24f { 766 reg = <0x24f 0x1>; 767 bits = <1 4>; 768 }; 769 770 speedbin_efuse: speedbin@133 { 771 reg = <0x133 0x1>; 772 bits = <5 3>; 773 }; 774 }; 775 776 rng: rng@83000 { 777 compatible = "qcom,prng-ee"; 778 reg = <0x00083000 0x1000>; 779 clocks = <&gcc GCC_PRNG_AHB_CLK>; 780 clock-names = "core"; 781 }; 782 783 gcc: clock-controller@300000 { 784 compatible = "qcom,gcc-msm8996"; 785 #clock-cells = <1>; 786 #reset-cells = <1>; 787 #power-domain-cells = <1>; 788 reg = <0x00300000 0x90000>; 789 790 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 791 <&rpmcc RPM_SMD_LN_BB_CLK>, 792 <&sleep_clk>, 793 <&pciephy_0>, 794 <&pciephy_1>, 795 <&pciephy_2>, 796 <&usb3phy>, 797 <&ufsphy 0>, 798 <&ufsphy 1>, 799 <&ufsphy 2>; 800 clock-names = "cxo", 801 "cxo2", 802 "sleep_clk", 803 "pcie_0_pipe_clk_src", 804 "pcie_1_pipe_clk_src", 805 "pcie_2_pipe_clk_src", 806 "usb3_phy_pipe_clk_src", 807 "ufs_rx_symbol_0_clk_src", 808 "ufs_rx_symbol_1_clk_src", 809 "ufs_tx_symbol_0_clk_src"; 810 }; 811 812 bimc: interconnect@408000 { 813 compatible = "qcom,msm8996-bimc"; 814 reg = <0x00408000 0x5a000>; 815 #interconnect-cells = <1>; 816 }; 817 818 tsens0: thermal-sensor@4a9000 { 819 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 820 reg = <0x004a9000 0x1000>, /* TM */ 821 <0x004a8000 0x1000>; /* SROT */ 822 #qcom,sensors = <13>; 823 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 825 interrupt-names = "uplow", "critical"; 826 #thermal-sensor-cells = <1>; 827 }; 828 829 tsens1: thermal-sensor@4ad000 { 830 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 831 reg = <0x004ad000 0x1000>, /* TM */ 832 <0x004ac000 0x1000>; /* SROT */ 833 #qcom,sensors = <8>; 834 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 836 interrupt-names = "uplow", "critical"; 837 #thermal-sensor-cells = <1>; 838 }; 839 840 cryptobam: dma-controller@644000 { 841 compatible = "qcom,bam-v1.7.0"; 842 reg = <0x00644000 0x24000>; 843 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&gcc GCC_CE1_CLK>; 845 clock-names = "bam_clk"; 846 #dma-cells = <1>; 847 qcom,ee = <0>; 848 qcom,controlled-remotely; 849 }; 850 851 crypto: crypto@67a000 { 852 compatible = "qcom,crypto-v5.4"; 853 reg = <0x0067a000 0x6000>; 854 clocks = <&gcc GCC_CE1_AHB_CLK>, 855 <&gcc GCC_CE1_AXI_CLK>, 856 <&gcc GCC_CE1_CLK>; 857 clock-names = "iface", "bus", "core"; 858 dmas = <&cryptobam 6>, <&cryptobam 7>; 859 dma-names = "rx", "tx"; 860 }; 861 862 cnoc: interconnect@500000 { 863 compatible = "qcom,msm8996-cnoc"; 864 reg = <0x00500000 0x1000>; 865 #interconnect-cells = <1>; 866 }; 867 868 snoc: interconnect@524000 { 869 compatible = "qcom,msm8996-snoc"; 870 reg = <0x00524000 0x1c000>; 871 #interconnect-cells = <1>; 872 }; 873 874 a0noc: interconnect@543000 { 875 compatible = "qcom,msm8996-a0noc"; 876 reg = <0x00543000 0x6000>; 877 #interconnect-cells = <1>; 878 clock-names = "aggre0_snoc_axi", 879 "aggre0_cnoc_ahb", 880 "aggre0_noc_mpu_cfg"; 881 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 882 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 883 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 884 power-domains = <&gcc AGGRE0_NOC_GDSC>; 885 }; 886 887 a1noc: interconnect@562000 { 888 compatible = "qcom,msm8996-a1noc"; 889 reg = <0x00562000 0x5000>; 890 #interconnect-cells = <1>; 891 }; 892 893 a2noc: interconnect@583000 { 894 compatible = "qcom,msm8996-a2noc"; 895 reg = <0x00583000 0x7000>; 896 #interconnect-cells = <1>; 897 clock-names = "aggre2_ufs_axi", "ufs_axi"; 898 clocks = <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 899 <&gcc GCC_UFS_AXI_CLK>; 900 }; 901 902 mnoc: interconnect@5a4000 { 903 compatible = "qcom,msm8996-mnoc"; 904 reg = <0x005a4000 0x1c000>; 905 #interconnect-cells = <1>; 906 clock-names = "iface"; 907 clocks = <&mmcc AHB_CLK_SRC>; 908 }; 909 910 pnoc: interconnect@5c0000 { 911 compatible = "qcom,msm8996-pnoc"; 912 reg = <0x005c0000 0x3000>; 913 #interconnect-cells = <1>; 914 }; 915 916 tcsr_mutex: hwlock@740000 { 917 compatible = "qcom,tcsr-mutex"; 918 reg = <0x00740000 0x20000>; 919 #hwlock-cells = <1>; 920 }; 921 922 tcsr_1: syscon@760000 { 923 compatible = "qcom,tcsr-msm8996", "syscon"; 924 reg = <0x00760000 0x20000>; 925 }; 926 927 tcsr_2: syscon@7a0000 { 928 compatible = "qcom,tcsr-msm8996", "syscon"; 929 reg = <0x007a0000 0x18000>; 930 }; 931 932 mmcc: clock-controller@8c0000 { 933 compatible = "qcom,mmcc-msm8996"; 934 #clock-cells = <1>; 935 #reset-cells = <1>; 936 #power-domain-cells = <1>; 937 reg = <0x008c0000 0x40000>; 938 clocks = <&xo_board>, 939 <&gcc GPLL0>, 940 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 941 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 942 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 943 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 944 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 945 <&mdss_hdmi_phy>; 946 clock-names = "xo", 947 "gpll0", 948 "gcc_mmss_noc_cfg_ahb_clk", 949 "dsi0pll", 950 "dsi0pllbyte", 951 "dsi1pll", 952 "dsi1pllbyte", 953 "hdmipll"; 954 assigned-clocks = <&mmcc MMPLL9_PLL>, 955 <&mmcc MMPLL1_PLL>, 956 <&mmcc MMPLL3_PLL>, 957 <&mmcc MMPLL4_PLL>, 958 <&mmcc MMPLL5_PLL>; 959 assigned-clock-rates = <624000000>, 960 <810000000>, 961 <980000000>, 962 <960000000>, 963 <825000000>; 964 }; 965 966 mdss: display-subsystem@900000 { 967 compatible = "qcom,mdss"; 968 969 reg = <0x00900000 0x1000>, 970 <0x009b0000 0x1040>, 971 <0x009b8000 0x1040>; 972 reg-names = "mdss_phys", 973 "vbif_phys", 974 "vbif_nrt_phys"; 975 976 power-domains = <&mmcc MDSS_GDSC>; 977 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 978 979 interrupt-controller; 980 #interrupt-cells = <1>; 981 982 clocks = <&mmcc MDSS_AHB_CLK>, 983 <&mmcc MDSS_MDP_CLK>; 984 clock-names = "iface", "core"; 985 986 resets = <&mmcc MDSS_BCR>; 987 988 #address-cells = <1>; 989 #size-cells = <1>; 990 ranges; 991 992 status = "disabled"; 993 994 mdp: display-controller@901000 { 995 compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; 996 reg = <0x00901000 0x90000>; 997 reg-names = "mdp_phys"; 998 999 interrupt-parent = <&mdss>; 1000 interrupts = <0>; 1001 1002 clocks = <&mmcc MDSS_AHB_CLK>, 1003 <&mmcc MDSS_AXI_CLK>, 1004 <&mmcc MDSS_MDP_CLK>, 1005 <&mmcc SMMU_MDP_AXI_CLK>, 1006 <&mmcc MDSS_VSYNC_CLK>; 1007 clock-names = "iface", 1008 "bus", 1009 "core", 1010 "iommu", 1011 "vsync"; 1012 1013 iommus = <&mdp_smmu 0>; 1014 1015 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1016 <&mmcc MDSS_VSYNC_CLK>; 1017 assigned-clock-rates = <300000000>, 1018 <19200000>; 1019 1020 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 1021 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 1022 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 1023 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 1024 1025 ports { 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 1029 port@0 { 1030 reg = <0>; 1031 mdp5_intf3_out: endpoint { 1032 remote-endpoint = <&mdss_hdmi_in>; 1033 }; 1034 }; 1035 1036 port@1 { 1037 reg = <1>; 1038 mdp5_intf1_out: endpoint { 1039 remote-endpoint = <&mdss_dsi0_in>; 1040 }; 1041 }; 1042 1043 port@2 { 1044 reg = <2>; 1045 mdp5_intf2_out: endpoint { 1046 remote-endpoint = <&mdss_dsi1_in>; 1047 }; 1048 }; 1049 }; 1050 }; 1051 1052 mdss_dsi0: dsi@994000 { 1053 compatible = "qcom,msm8996-dsi-ctrl", 1054 "qcom,mdss-dsi-ctrl"; 1055 reg = <0x00994000 0x400>; 1056 reg-names = "dsi_ctrl"; 1057 1058 interrupt-parent = <&mdss>; 1059 interrupts = <4>; 1060 1061 clocks = <&mmcc MDSS_MDP_CLK>, 1062 <&mmcc MDSS_BYTE0_CLK>, 1063 <&mmcc MDSS_AHB_CLK>, 1064 <&mmcc MDSS_AXI_CLK>, 1065 <&mmcc MMSS_MISC_AHB_CLK>, 1066 <&mmcc MDSS_PCLK0_CLK>, 1067 <&mmcc MDSS_ESC0_CLK>; 1068 clock-names = "mdp_core", 1069 "byte", 1070 "iface", 1071 "bus", 1072 "core_mmss", 1073 "pixel", 1074 "core"; 1075 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1076 <&mmcc PCLK0_CLK_SRC>; 1077 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1078 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1079 1080 phys = <&mdss_dsi0_phy>; 1081 status = "disabled"; 1082 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 1086 ports { 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 1090 port@0 { 1091 reg = <0>; 1092 mdss_dsi0_in: endpoint { 1093 remote-endpoint = <&mdp5_intf1_out>; 1094 }; 1095 }; 1096 1097 port@1 { 1098 reg = <1>; 1099 mdss_dsi0_out: endpoint { 1100 }; 1101 }; 1102 }; 1103 }; 1104 1105 mdss_dsi0_phy: phy@994400 { 1106 compatible = "qcom,dsi-phy-14nm"; 1107 reg = <0x00994400 0x100>, 1108 <0x00994500 0x300>, 1109 <0x00994800 0x188>; 1110 reg-names = "dsi_phy", 1111 "dsi_phy_lane", 1112 "dsi_pll"; 1113 1114 #clock-cells = <1>; 1115 #phy-cells = <0>; 1116 1117 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1118 clock-names = "iface", "ref"; 1119 status = "disabled"; 1120 }; 1121 1122 mdss_dsi1: dsi@996000 { 1123 compatible = "qcom,msm8996-dsi-ctrl", 1124 "qcom,mdss-dsi-ctrl"; 1125 reg = <0x00996000 0x400>; 1126 reg-names = "dsi_ctrl"; 1127 1128 interrupt-parent = <&mdss>; 1129 interrupts = <5>; 1130 1131 clocks = <&mmcc MDSS_MDP_CLK>, 1132 <&mmcc MDSS_BYTE1_CLK>, 1133 <&mmcc MDSS_AHB_CLK>, 1134 <&mmcc MDSS_AXI_CLK>, 1135 <&mmcc MMSS_MISC_AHB_CLK>, 1136 <&mmcc MDSS_PCLK1_CLK>, 1137 <&mmcc MDSS_ESC1_CLK>; 1138 clock-names = "mdp_core", 1139 "byte", 1140 "iface", 1141 "bus", 1142 "core_mmss", 1143 "pixel", 1144 "core"; 1145 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, 1146 <&mmcc PCLK1_CLK_SRC>; 1147 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 1148 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 1149 1150 phys = <&mdss_dsi1_phy>; 1151 status = "disabled"; 1152 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 1156 ports { 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 1160 port@0 { 1161 reg = <0>; 1162 mdss_dsi1_in: endpoint { 1163 remote-endpoint = <&mdp5_intf2_out>; 1164 }; 1165 }; 1166 1167 port@1 { 1168 reg = <1>; 1169 mdss_dsi1_out: endpoint { 1170 }; 1171 }; 1172 }; 1173 }; 1174 1175 mdss_dsi1_phy: phy@996400 { 1176 compatible = "qcom,dsi-phy-14nm"; 1177 reg = <0x00996400 0x100>, 1178 <0x00996500 0x300>, 1179 <0x00996800 0x188>; 1180 reg-names = "dsi_phy", 1181 "dsi_phy_lane", 1182 "dsi_pll"; 1183 1184 #clock-cells = <1>; 1185 #phy-cells = <0>; 1186 1187 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1188 clock-names = "iface", "ref"; 1189 status = "disabled"; 1190 }; 1191 1192 mdss_hdmi: hdmi-tx@9a0000 { 1193 compatible = "qcom,hdmi-tx-8996"; 1194 reg = <0x009a0000 0x50c>, 1195 <0x00070000 0x6158>, 1196 <0x009e0000 0xfff>; 1197 reg-names = "core_physical", 1198 "qfprom_physical", 1199 "hdcp_physical"; 1200 1201 interrupt-parent = <&mdss>; 1202 interrupts = <8>; 1203 1204 clocks = <&mmcc MDSS_MDP_CLK>, 1205 <&mmcc MDSS_AHB_CLK>, 1206 <&mmcc MDSS_HDMI_CLK>, 1207 <&mmcc MDSS_HDMI_AHB_CLK>, 1208 <&mmcc MDSS_EXTPCLK_CLK>; 1209 clock-names = 1210 "mdp_core", 1211 "iface", 1212 "core", 1213 "alt_iface", 1214 "extp"; 1215 1216 phys = <&mdss_hdmi_phy>; 1217 #sound-dai-cells = <1>; 1218 1219 status = "disabled"; 1220 1221 ports { 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 1225 port@0 { 1226 reg = <0>; 1227 mdss_hdmi_in: endpoint { 1228 remote-endpoint = <&mdp5_intf3_out>; 1229 }; 1230 }; 1231 }; 1232 }; 1233 1234 mdss_hdmi_phy: phy@9a0600 { 1235 #phy-cells = <0>; 1236 compatible = "qcom,hdmi-phy-8996"; 1237 reg = <0x009a0600 0x1c4>, 1238 <0x009a0a00 0x124>, 1239 <0x009a0c00 0x124>, 1240 <0x009a0e00 0x124>, 1241 <0x009a1000 0x124>, 1242 <0x009a1200 0x0c8>; 1243 reg-names = "hdmi_pll", 1244 "hdmi_tx_l0", 1245 "hdmi_tx_l1", 1246 "hdmi_tx_l2", 1247 "hdmi_tx_l3", 1248 "hdmi_phy"; 1249 1250 clocks = <&mmcc MDSS_AHB_CLK>, 1251 <&gcc GCC_HDMI_CLKREF_CLK>, 1252 <&xo_board>; 1253 clock-names = "iface", 1254 "ref", 1255 "xo"; 1256 1257 #clock-cells = <0>; 1258 1259 status = "disabled"; 1260 }; 1261 }; 1262 1263 gpu: gpu@b00000 { 1264 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1265 1266 reg = <0x00b00000 0x3f000>; 1267 reg-names = "kgsl_3d0_reg_memory"; 1268 1269 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1270 1271 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1272 <&mmcc GPU_AHB_CLK>, 1273 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1274 <&gcc GCC_BIMC_GFX_CLK>, 1275 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1276 1277 clock-names = "core", 1278 "iface", 1279 "rbbmtimer", 1280 "mem", 1281 "mem_iface"; 1282 1283 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1284 interconnect-names = "gfx-mem"; 1285 1286 power-domains = <&mmcc GPU_GX_GDSC>; 1287 iommus = <&adreno_smmu 0>; 1288 1289 nvmem-cells = <&speedbin_efuse>; 1290 nvmem-cell-names = "speed_bin"; 1291 1292 operating-points-v2 = <&gpu_opp_table>; 1293 1294 status = "disabled"; 1295 1296 #cooling-cells = <2>; 1297 1298 gpu_opp_table: opp-table { 1299 compatible = "operating-points-v2"; 1300 1301 /* 1302 * 624Mhz is only available on speed bins 0 and 3. 1303 * 560Mhz is only available on speed bins 0, 2 and 3. 1304 * All the rest are available on all bins of the hardware. 1305 */ 1306 opp-624000000 { 1307 opp-hz = /bits/ 64 <624000000>; 1308 opp-supported-hw = <0x09>; 1309 }; 1310 opp-560000000 { 1311 opp-hz = /bits/ 64 <560000000>; 1312 opp-supported-hw = <0x0d>; 1313 }; 1314 opp-510000000 { 1315 opp-hz = /bits/ 64 <510000000>; 1316 opp-supported-hw = <0xff>; 1317 }; 1318 opp-401800000 { 1319 opp-hz = /bits/ 64 <401800000>; 1320 opp-supported-hw = <0xff>; 1321 }; 1322 opp-315000000 { 1323 opp-hz = /bits/ 64 <315000000>; 1324 opp-supported-hw = <0xff>; 1325 }; 1326 opp-214000000 { 1327 opp-hz = /bits/ 64 <214000000>; 1328 opp-supported-hw = <0xff>; 1329 }; 1330 opp-133000000 { 1331 opp-hz = /bits/ 64 <133000000>; 1332 opp-supported-hw = <0xff>; 1333 }; 1334 }; 1335 1336 zap-shader { 1337 memory-region = <&gpu_mem>; 1338 }; 1339 }; 1340 1341 tlmm: pinctrl@1010000 { 1342 compatible = "qcom,msm8996-pinctrl"; 1343 reg = <0x01010000 0x300000>; 1344 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1345 gpio-controller; 1346 gpio-ranges = <&tlmm 0 0 150>; 1347 #gpio-cells = <2>; 1348 interrupt-controller; 1349 #interrupt-cells = <2>; 1350 1351 blsp1_spi1_default: blsp1-spi1-default-state { 1352 spi-pins { 1353 pins = "gpio0", "gpio1", "gpio3"; 1354 function = "blsp_spi1"; 1355 drive-strength = <12>; 1356 bias-disable; 1357 }; 1358 1359 cs-pins { 1360 pins = "gpio2"; 1361 function = "gpio"; 1362 drive-strength = <16>; 1363 bias-disable; 1364 output-high; 1365 }; 1366 }; 1367 1368 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 1369 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1370 function = "gpio"; 1371 drive-strength = <2>; 1372 bias-pull-down; 1373 }; 1374 1375 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { 1376 pins = "gpio4", "gpio5"; 1377 function = "blsp_uart8"; 1378 drive-strength = <16>; 1379 bias-disable; 1380 }; 1381 1382 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { 1383 pins = "gpio4", "gpio5"; 1384 function = "gpio"; 1385 drive-strength = <2>; 1386 bias-disable; 1387 }; 1388 1389 blsp2_i2c2_default: blsp2-i2c2-state { 1390 pins = "gpio6", "gpio7"; 1391 function = "blsp_i2c8"; 1392 drive-strength = <16>; 1393 bias-disable; 1394 }; 1395 1396 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1397 pins = "gpio6", "gpio7"; 1398 function = "gpio"; 1399 drive-strength = <2>; 1400 bias-disable; 1401 }; 1402 1403 blsp1_i2c6_default: blsp1-i2c6-state { 1404 pins = "gpio27", "gpio28"; 1405 function = "blsp_i2c6"; 1406 drive-strength = <16>; 1407 bias-disable; 1408 }; 1409 1410 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1411 pins = "gpio27", "gpio28"; 1412 function = "gpio"; 1413 drive-strength = <2>; 1414 bias-pull-up; 1415 }; 1416 1417 cci0_default: cci0-default-state { 1418 pins = "gpio17", "gpio18"; 1419 function = "cci_i2c"; 1420 drive-strength = <16>; 1421 bias-disable; 1422 }; 1423 1424 camera0_state_on: 1425 camera_rear_default: camera-rear-default-state { 1426 camera0_mclk: mclk0-pins { 1427 pins = "gpio13"; 1428 function = "cam_mclk"; 1429 drive-strength = <16>; 1430 bias-disable; 1431 }; 1432 1433 camera0_rst: rst-pins { 1434 pins = "gpio25"; 1435 function = "gpio"; 1436 drive-strength = <16>; 1437 bias-disable; 1438 }; 1439 1440 camera0_pwdn: pwdn-pins { 1441 pins = "gpio26"; 1442 function = "gpio"; 1443 drive-strength = <16>; 1444 bias-disable; 1445 }; 1446 }; 1447 1448 cci1_default: cci1-default-state { 1449 pins = "gpio19", "gpio20"; 1450 function = "cci_i2c"; 1451 drive-strength = <16>; 1452 bias-disable; 1453 }; 1454 1455 camera1_state_on: 1456 camera_board_default: camera-board-default-state { 1457 mclk1-pins { 1458 pins = "gpio14"; 1459 function = "cam_mclk"; 1460 drive-strength = <16>; 1461 bias-disable; 1462 }; 1463 1464 pwdn-pins { 1465 pins = "gpio98"; 1466 function = "gpio"; 1467 drive-strength = <16>; 1468 bias-disable; 1469 }; 1470 1471 rst-pins { 1472 pins = "gpio104"; 1473 function = "gpio"; 1474 drive-strength = <16>; 1475 bias-disable; 1476 }; 1477 }; 1478 1479 camera2_state_on: 1480 camera_front_default: camera-front-default-state { 1481 camera2_mclk: mclk2-pins { 1482 pins = "gpio15"; 1483 function = "cam_mclk"; 1484 drive-strength = <16>; 1485 bias-disable; 1486 }; 1487 1488 camera2_rst: rst-pins { 1489 pins = "gpio23"; 1490 function = "gpio"; 1491 drive-strength = <16>; 1492 bias-disable; 1493 }; 1494 1495 pwdn-pins { 1496 pins = "gpio133"; 1497 function = "gpio"; 1498 drive-strength = <16>; 1499 bias-disable; 1500 }; 1501 }; 1502 1503 pcie0_state_on: pcie0-state-on-state { 1504 perst-pins { 1505 pins = "gpio35"; 1506 function = "gpio"; 1507 drive-strength = <2>; 1508 bias-pull-down; 1509 }; 1510 1511 clkreq-pins { 1512 pins = "gpio36"; 1513 function = "pci_e0"; 1514 drive-strength = <2>; 1515 bias-pull-up; 1516 }; 1517 1518 wake-pins { 1519 pins = "gpio37"; 1520 function = "gpio"; 1521 drive-strength = <2>; 1522 bias-pull-up; 1523 }; 1524 }; 1525 1526 pcie0_state_off: pcie0-state-off-state { 1527 perst-pins { 1528 pins = "gpio35"; 1529 function = "gpio"; 1530 drive-strength = <2>; 1531 bias-pull-down; 1532 }; 1533 1534 clkreq-pins { 1535 pins = "gpio36"; 1536 function = "gpio"; 1537 drive-strength = <2>; 1538 bias-disable; 1539 }; 1540 1541 wake-pins { 1542 pins = "gpio37"; 1543 function = "gpio"; 1544 drive-strength = <2>; 1545 bias-disable; 1546 }; 1547 }; 1548 1549 blsp1_uart2_default: blsp1-uart2-default-state { 1550 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1551 function = "blsp_uart2"; 1552 drive-strength = <16>; 1553 bias-disable; 1554 }; 1555 1556 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 1557 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1558 function = "gpio"; 1559 drive-strength = <2>; 1560 bias-disable; 1561 }; 1562 1563 blsp1_i2c3_default: blsp1-i2c3-default-state { 1564 pins = "gpio47", "gpio48"; 1565 function = "blsp_i2c3"; 1566 drive-strength = <16>; 1567 bias-disable; 1568 }; 1569 1570 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1571 pins = "gpio47", "gpio48"; 1572 function = "gpio"; 1573 drive-strength = <2>; 1574 bias-disable; 1575 }; 1576 1577 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { 1578 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1579 function = "blsp_uart9"; 1580 drive-strength = <16>; 1581 bias-disable; 1582 }; 1583 1584 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { 1585 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1586 function = "blsp_uart9"; 1587 drive-strength = <2>; 1588 bias-disable; 1589 }; 1590 1591 blsp2_i2c3_default: blsp2-i2c3-state-state { 1592 pins = "gpio51", "gpio52"; 1593 function = "blsp_i2c9"; 1594 drive-strength = <16>; 1595 bias-disable; 1596 }; 1597 1598 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1599 pins = "gpio51", "gpio52"; 1600 function = "gpio"; 1601 drive-strength = <2>; 1602 bias-disable; 1603 }; 1604 1605 wcd_intr_default: wcd-intr-default-state { 1606 pins = "gpio54"; 1607 function = "gpio"; 1608 drive-strength = <2>; 1609 bias-pull-down; 1610 }; 1611 1612 blsp2_i2c1_default: blsp2-i2c1-state { 1613 pins = "gpio55", "gpio56"; 1614 function = "blsp_i2c7"; 1615 drive-strength = <16>; 1616 bias-disable; 1617 }; 1618 1619 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1620 pins = "gpio55", "gpio56"; 1621 function = "gpio"; 1622 drive-strength = <2>; 1623 bias-disable; 1624 }; 1625 1626 blsp2_i2c5_default: blsp2-i2c5-state { 1627 pins = "gpio60", "gpio61"; 1628 function = "blsp_i2c11"; 1629 drive-strength = <2>; 1630 bias-disable; 1631 }; 1632 1633 /* Sleep state for BLSP2_I2C5 is missing.. */ 1634 1635 cdc_reset_active: cdc-reset-active-state { 1636 pins = "gpio64"; 1637 function = "gpio"; 1638 drive-strength = <16>; 1639 bias-pull-down; 1640 output-high; 1641 }; 1642 1643 cdc_reset_sleep: cdc-reset-sleep-state { 1644 pins = "gpio64"; 1645 function = "gpio"; 1646 drive-strength = <16>; 1647 bias-disable; 1648 output-low; 1649 }; 1650 1651 blsp2_spi6_default: blsp2-spi6-default-state { 1652 spi-pins { 1653 pins = "gpio85", "gpio86", "gpio88"; 1654 function = "blsp_spi12"; 1655 drive-strength = <12>; 1656 bias-disable; 1657 }; 1658 1659 cs-pins { 1660 pins = "gpio87"; 1661 function = "gpio"; 1662 drive-strength = <16>; 1663 bias-disable; 1664 output-high; 1665 }; 1666 }; 1667 1668 blsp2_spi6_sleep: blsp2-spi6-sleep-state { 1669 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1670 function = "gpio"; 1671 drive-strength = <2>; 1672 bias-pull-down; 1673 }; 1674 1675 blsp2_i2c6_default: blsp2-i2c6-state { 1676 pins = "gpio87", "gpio88"; 1677 function = "blsp_i2c12"; 1678 drive-strength = <16>; 1679 bias-disable; 1680 }; 1681 1682 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1683 pins = "gpio87", "gpio88"; 1684 function = "gpio"; 1685 drive-strength = <2>; 1686 bias-disable; 1687 }; 1688 1689 pcie1_state_on: pcie1-on-state { 1690 perst-pins { 1691 pins = "gpio130"; 1692 function = "gpio"; 1693 drive-strength = <2>; 1694 bias-pull-down; 1695 }; 1696 1697 clkreq-pins { 1698 pins = "gpio131"; 1699 function = "pci_e1"; 1700 drive-strength = <2>; 1701 bias-pull-up; 1702 }; 1703 1704 wake-pins { 1705 pins = "gpio132"; 1706 function = "gpio"; 1707 drive-strength = <2>; 1708 bias-pull-down; 1709 }; 1710 }; 1711 1712 pcie1_state_off: pcie1-off-state { 1713 /* Perst is missing? */ 1714 clkreq-pins { 1715 pins = "gpio131"; 1716 function = "gpio"; 1717 drive-strength = <2>; 1718 bias-disable; 1719 }; 1720 1721 wake-pins { 1722 pins = "gpio132"; 1723 function = "gpio"; 1724 drive-strength = <2>; 1725 bias-disable; 1726 }; 1727 }; 1728 1729 pcie2_state_on: pcie2-on-state { 1730 perst-pins { 1731 pins = "gpio114"; 1732 function = "gpio"; 1733 drive-strength = <2>; 1734 bias-pull-down; 1735 }; 1736 1737 clkreq-pins { 1738 pins = "gpio115"; 1739 function = "pci_e2"; 1740 drive-strength = <2>; 1741 bias-pull-up; 1742 }; 1743 1744 wake-pins { 1745 pins = "gpio116"; 1746 function = "gpio"; 1747 drive-strength = <2>; 1748 bias-pull-down; 1749 }; 1750 }; 1751 1752 pcie2_state_off: pcie2-off-state { 1753 /* Perst is missing? */ 1754 clkreq-pins { 1755 pins = "gpio115"; 1756 function = "gpio"; 1757 drive-strength = <2>; 1758 bias-disable; 1759 }; 1760 1761 wake-pins { 1762 pins = "gpio116"; 1763 function = "gpio"; 1764 drive-strength = <2>; 1765 bias-disable; 1766 }; 1767 }; 1768 1769 sdc1_state_on: sdc1-on-state { 1770 clk-pins { 1771 pins = "sdc1_clk"; 1772 bias-disable; 1773 drive-strength = <16>; 1774 }; 1775 1776 cmd-pins { 1777 pins = "sdc1_cmd"; 1778 bias-pull-up; 1779 drive-strength = <10>; 1780 }; 1781 1782 data-pins { 1783 pins = "sdc1_data"; 1784 bias-pull-up; 1785 drive-strength = <10>; 1786 }; 1787 1788 rclk-pins { 1789 pins = "sdc1_rclk"; 1790 bias-pull-down; 1791 }; 1792 }; 1793 1794 sdc1_state_off: sdc1-off-state { 1795 clk-pins { 1796 pins = "sdc1_clk"; 1797 bias-disable; 1798 drive-strength = <2>; 1799 }; 1800 1801 cmd-pins { 1802 pins = "sdc1_cmd"; 1803 bias-pull-up; 1804 drive-strength = <2>; 1805 }; 1806 1807 data-pins { 1808 pins = "sdc1_data"; 1809 bias-pull-up; 1810 drive-strength = <2>; 1811 }; 1812 1813 rclk-pins { 1814 pins = "sdc1_rclk"; 1815 bias-pull-down; 1816 }; 1817 }; 1818 1819 sdc2_state_on: sdc2-on-state { 1820 clk-pins { 1821 pins = "sdc2_clk"; 1822 bias-disable; 1823 drive-strength = <16>; 1824 }; 1825 1826 cmd-pins { 1827 pins = "sdc2_cmd"; 1828 bias-pull-up; 1829 drive-strength = <10>; 1830 }; 1831 1832 data-pins { 1833 pins = "sdc2_data"; 1834 bias-pull-up; 1835 drive-strength = <10>; 1836 }; 1837 }; 1838 1839 sdc2_state_off: sdc2-off-state { 1840 clk-pins { 1841 pins = "sdc2_clk"; 1842 bias-disable; 1843 drive-strength = <2>; 1844 }; 1845 1846 cmd-pins { 1847 pins = "sdc2_cmd"; 1848 bias-pull-up; 1849 drive-strength = <2>; 1850 }; 1851 1852 data-pins { 1853 pins = "sdc2_data"; 1854 bias-pull-up; 1855 drive-strength = <2>; 1856 }; 1857 }; 1858 }; 1859 1860 sram@290000 { 1861 compatible = "qcom,rpm-stats"; 1862 reg = <0x00290000 0x10000>; 1863 }; 1864 1865 spmi_bus: spmi@400f000 { 1866 compatible = "qcom,spmi-pmic-arb"; 1867 reg = <0x0400f000 0x1000>, 1868 <0x04400000 0x800000>, 1869 <0x04c00000 0x800000>, 1870 <0x05800000 0x200000>, 1871 <0x0400a000 0x002100>; 1872 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1873 interrupt-names = "periph_irq"; 1874 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1875 qcom,ee = <0>; 1876 qcom,channel = <0>; 1877 #address-cells = <2>; 1878 #size-cells = <0>; 1879 interrupt-controller; 1880 #interrupt-cells = <4>; 1881 }; 1882 1883 bus@0 { 1884 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1885 compatible = "simple-pm-bus"; 1886 #address-cells = <1>; 1887 #size-cells = <1>; 1888 ranges = <0x0 0x0 0xffffffff>; 1889 1890 pcie0: pcie@600000 { 1891 compatible = "qcom,pcie-msm8996"; 1892 status = "disabled"; 1893 power-domains = <&gcc PCIE0_GDSC>; 1894 bus-range = <0x00 0xff>; 1895 num-lanes = <1>; 1896 1897 reg = <0x00600000 0x2000>, 1898 <0x0c000000 0xf1d>, 1899 <0x0c000f20 0xa8>, 1900 <0x0c100000 0x100000>; 1901 reg-names = "parf", "dbi", "elbi","config"; 1902 1903 phys = <&pciephy_0>; 1904 phy-names = "pciephy"; 1905 1906 #address-cells = <3>; 1907 #size-cells = <2>; 1908 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, 1909 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1910 1911 device_type = "pci"; 1912 1913 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1914 interrupt-names = "msi"; 1915 #interrupt-cells = <1>; 1916 interrupt-map-mask = <0 0 0 0x7>; 1917 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1918 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1919 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1920 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1921 1922 pinctrl-names = "default", "sleep"; 1923 pinctrl-0 = <&pcie0_state_on>; 1924 pinctrl-1 = <&pcie0_state_off>; 1925 1926 linux,pci-domain = <0>; 1927 1928 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1929 <&gcc GCC_PCIE_0_AUX_CLK>, 1930 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1931 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1932 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1933 1934 clock-names = "pipe", 1935 "aux", 1936 "cfg", 1937 "bus_master", 1938 "bus_slave"; 1939 1940 pcie@0 { 1941 device_type = "pci"; 1942 reg = <0x0 0x0 0x0 0x0 0x0>; 1943 bus-range = <0x01 0xff>; 1944 1945 #address-cells = <3>; 1946 #size-cells = <2>; 1947 ranges; 1948 }; 1949 }; 1950 1951 pcie1: pcie@608000 { 1952 compatible = "qcom,pcie-msm8996"; 1953 power-domains = <&gcc PCIE1_GDSC>; 1954 bus-range = <0x00 0xff>; 1955 num-lanes = <1>; 1956 1957 status = "disabled"; 1958 1959 reg = <0x00608000 0x2000>, 1960 <0x0d000000 0xf1d>, 1961 <0x0d000f20 0xa8>, 1962 <0x0d100000 0x100000>; 1963 1964 reg-names = "parf", "dbi", "elbi","config"; 1965 1966 phys = <&pciephy_1>; 1967 phy-names = "pciephy"; 1968 1969 #address-cells = <3>; 1970 #size-cells = <2>; 1971 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, 1972 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1973 1974 device_type = "pci"; 1975 1976 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1977 interrupt-names = "msi"; 1978 #interrupt-cells = <1>; 1979 interrupt-map-mask = <0 0 0 0x7>; 1980 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1981 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1982 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1983 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1984 1985 pinctrl-names = "default", "sleep"; 1986 pinctrl-0 = <&pcie1_state_on>; 1987 pinctrl-1 = <&pcie1_state_off>; 1988 1989 linux,pci-domain = <1>; 1990 1991 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1992 <&gcc GCC_PCIE_1_AUX_CLK>, 1993 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1994 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1995 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1996 1997 clock-names = "pipe", 1998 "aux", 1999 "cfg", 2000 "bus_master", 2001 "bus_slave"; 2002 2003 pcie@0 { 2004 device_type = "pci"; 2005 reg = <0x0 0x0 0x0 0x0 0x0>; 2006 bus-range = <0x01 0xff>; 2007 2008 #address-cells = <3>; 2009 #size-cells = <2>; 2010 ranges; 2011 }; 2012 }; 2013 2014 pcie2: pcie@610000 { 2015 compatible = "qcom,pcie-msm8996"; 2016 power-domains = <&gcc PCIE2_GDSC>; 2017 bus-range = <0x00 0xff>; 2018 num-lanes = <1>; 2019 status = "disabled"; 2020 reg = <0x00610000 0x2000>, 2021 <0x0e000000 0xf1d>, 2022 <0x0e000f20 0xa8>, 2023 <0x0e100000 0x100000>; 2024 2025 reg-names = "parf", "dbi", "elbi","config"; 2026 2027 phys = <&pciephy_2>; 2028 phy-names = "pciephy"; 2029 2030 #address-cells = <3>; 2031 #size-cells = <2>; 2032 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, 2033 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 2034 2035 device_type = "pci"; 2036 2037 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 2038 interrupt-names = "msi"; 2039 #interrupt-cells = <1>; 2040 interrupt-map-mask = <0 0 0 0x7>; 2041 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2042 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2043 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2044 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2045 2046 pinctrl-names = "default", "sleep"; 2047 pinctrl-0 = <&pcie2_state_on>; 2048 pinctrl-1 = <&pcie2_state_off>; 2049 2050 linux,pci-domain = <2>; 2051 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2052 <&gcc GCC_PCIE_2_AUX_CLK>, 2053 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2054 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2055 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 2056 2057 clock-names = "pipe", 2058 "aux", 2059 "cfg", 2060 "bus_master", 2061 "bus_slave"; 2062 2063 pcie@0 { 2064 device_type = "pci"; 2065 reg = <0x0 0x0 0x0 0x0 0x0>; 2066 bus-range = <0x01 0xff>; 2067 2068 #address-cells = <3>; 2069 #size-cells = <2>; 2070 ranges; 2071 }; 2072 }; 2073 }; 2074 2075 ufshc: ufshc@624000 { 2076 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 2077 "jedec,ufs-2.0"; 2078 reg = <0x00624000 0x2500>; 2079 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2080 2081 phys = <&ufsphy>; 2082 phy-names = "ufsphy"; 2083 2084 power-domains = <&gcc UFS_GDSC>; 2085 2086 clock-names = 2087 "core_clk", 2088 "bus_clk", 2089 "bus_aggr_clk", 2090 "iface_clk", 2091 "core_clk_unipro", 2092 "core_clk_ice", 2093 "ref_clk", 2094 "tx_lane0_sync_clk", 2095 "rx_lane0_sync_clk"; 2096 clocks = 2097 <&gcc GCC_UFS_AXI_CLK>, 2098 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 2099 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 2100 <&gcc GCC_UFS_AHB_CLK>, 2101 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 2102 <&gcc GCC_UFS_ICE_CORE_CLK>, 2103 <&rpmcc RPM_SMD_LN_BB_CLK>, 2104 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 2105 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 2106 freq-table-hz = 2107 <100000000 200000000>, 2108 <0 0>, 2109 <0 0>, 2110 <0 0>, 2111 <75000000 150000000>, 2112 <150000000 300000000>, 2113 <0 0>, 2114 <0 0>, 2115 <0 0>; 2116 2117 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, 2118 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; 2119 interconnect-names = "ufs-ddr", "cpu-ufs"; 2120 2121 lanes-per-direction = <1>; 2122 #reset-cells = <1>; 2123 status = "disabled"; 2124 }; 2125 2126 ufsphy: phy@627000 { 2127 compatible = "qcom,msm8996-qmp-ufs-phy"; 2128 reg = <0x00627000 0x1000>; 2129 2130 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_UFS_CLKREF_CLK>; 2131 clock-names = "ref", "qref"; 2132 2133 resets = <&ufshc 0>; 2134 reset-names = "ufsphy"; 2135 2136 #clock-cells = <1>; 2137 #phy-cells = <0>; 2138 2139 status = "disabled"; 2140 }; 2141 2142 camss: camss@a34000 { 2143 compatible = "qcom,msm8996-camss"; 2144 reg = <0x00a34000 0x1000>, 2145 <0x00a00030 0x4>, 2146 <0x00a35000 0x1000>, 2147 <0x00a00038 0x4>, 2148 <0x00a36000 0x1000>, 2149 <0x00a00040 0x4>, 2150 <0x00a30000 0x100>, 2151 <0x00a30400 0x100>, 2152 <0x00a30800 0x100>, 2153 <0x00a30c00 0x100>, 2154 <0x00a31000 0x500>, 2155 <0x00a00020 0x10>, 2156 <0x00a10000 0x1000>, 2157 <0x00a14000 0x1000>; 2158 reg-names = "csiphy0", 2159 "csiphy0_clk_mux", 2160 "csiphy1", 2161 "csiphy1_clk_mux", 2162 "csiphy2", 2163 "csiphy2_clk_mux", 2164 "csid0", 2165 "csid1", 2166 "csid2", 2167 "csid3", 2168 "ispif", 2169 "csi_clk_mux", 2170 "vfe0", 2171 "vfe1"; 2172 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2179 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2180 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2181 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2182 interrupt-names = "csiphy0", 2183 "csiphy1", 2184 "csiphy2", 2185 "csid0", 2186 "csid1", 2187 "csid2", 2188 "csid3", 2189 "ispif", 2190 "vfe0", 2191 "vfe1"; 2192 power-domains = <&mmcc VFE0_GDSC>, 2193 <&mmcc VFE1_GDSC>; 2194 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2195 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2196 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2197 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2198 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2199 <&mmcc CAMSS_CSI0_AHB_CLK>, 2200 <&mmcc CAMSS_CSI0_CLK>, 2201 <&mmcc CAMSS_CSI0PHY_CLK>, 2202 <&mmcc CAMSS_CSI0PIX_CLK>, 2203 <&mmcc CAMSS_CSI0RDI_CLK>, 2204 <&mmcc CAMSS_CSI1_AHB_CLK>, 2205 <&mmcc CAMSS_CSI1_CLK>, 2206 <&mmcc CAMSS_CSI1PHY_CLK>, 2207 <&mmcc CAMSS_CSI1PIX_CLK>, 2208 <&mmcc CAMSS_CSI1RDI_CLK>, 2209 <&mmcc CAMSS_CSI2_AHB_CLK>, 2210 <&mmcc CAMSS_CSI2_CLK>, 2211 <&mmcc CAMSS_CSI2PHY_CLK>, 2212 <&mmcc CAMSS_CSI2PIX_CLK>, 2213 <&mmcc CAMSS_CSI2RDI_CLK>, 2214 <&mmcc CAMSS_CSI3_AHB_CLK>, 2215 <&mmcc CAMSS_CSI3_CLK>, 2216 <&mmcc CAMSS_CSI3PHY_CLK>, 2217 <&mmcc CAMSS_CSI3PIX_CLK>, 2218 <&mmcc CAMSS_CSI3RDI_CLK>, 2219 <&mmcc CAMSS_AHB_CLK>, 2220 <&mmcc CAMSS_VFE0_CLK>, 2221 <&mmcc CAMSS_CSI_VFE0_CLK>, 2222 <&mmcc CAMSS_VFE0_AHB_CLK>, 2223 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2224 <&mmcc CAMSS_VFE1_CLK>, 2225 <&mmcc CAMSS_CSI_VFE1_CLK>, 2226 <&mmcc CAMSS_VFE1_AHB_CLK>, 2227 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2228 <&mmcc CAMSS_VFE_AHB_CLK>, 2229 <&mmcc CAMSS_VFE_AXI_CLK>; 2230 clock-names = "top_ahb", 2231 "ispif_ahb", 2232 "csiphy0_timer", 2233 "csiphy1_timer", 2234 "csiphy2_timer", 2235 "csi0_ahb", 2236 "csi0", 2237 "csi0_phy", 2238 "csi0_pix", 2239 "csi0_rdi", 2240 "csi1_ahb", 2241 "csi1", 2242 "csi1_phy", 2243 "csi1_pix", 2244 "csi1_rdi", 2245 "csi2_ahb", 2246 "csi2", 2247 "csi2_phy", 2248 "csi2_pix", 2249 "csi2_rdi", 2250 "csi3_ahb", 2251 "csi3", 2252 "csi3_phy", 2253 "csi3_pix", 2254 "csi3_rdi", 2255 "ahb", 2256 "vfe0", 2257 "csi_vfe0", 2258 "vfe0_ahb", 2259 "vfe0_stream", 2260 "vfe1", 2261 "csi_vfe1", 2262 "vfe1_ahb", 2263 "vfe1_stream", 2264 "vfe_ahb", 2265 "vfe_axi"; 2266 iommus = <&vfe_smmu 0>, 2267 <&vfe_smmu 1>, 2268 <&vfe_smmu 2>, 2269 <&vfe_smmu 3>; 2270 status = "disabled"; 2271 ports { 2272 #address-cells = <1>; 2273 #size-cells = <0>; 2274 }; 2275 }; 2276 2277 cci: cci@a0c000 { 2278 compatible = "qcom,msm8996-cci"; 2279 #address-cells = <1>; 2280 #size-cells = <0>; 2281 reg = <0xa0c000 0x1000>; 2282 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2283 power-domains = <&mmcc CAMSS_GDSC>; 2284 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2285 <&mmcc CAMSS_CCI_AHB_CLK>, 2286 <&mmcc CAMSS_CCI_CLK>, 2287 <&mmcc CAMSS_AHB_CLK>; 2288 clock-names = "camss_top_ahb", 2289 "cci_ahb", 2290 "cci", 2291 "camss_ahb"; 2292 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2293 <&mmcc CAMSS_CCI_CLK>; 2294 assigned-clock-rates = <80000000>, <37500000>; 2295 pinctrl-names = "default"; 2296 pinctrl-0 = <&cci0_default &cci1_default>; 2297 status = "disabled"; 2298 2299 cci_i2c0: i2c-bus@0 { 2300 reg = <0>; 2301 clock-frequency = <400000>; 2302 #address-cells = <1>; 2303 #size-cells = <0>; 2304 }; 2305 2306 cci_i2c1: i2c-bus@1 { 2307 reg = <1>; 2308 clock-frequency = <400000>; 2309 #address-cells = <1>; 2310 #size-cells = <0>; 2311 }; 2312 }; 2313 2314 adreno_smmu: iommu@b40000 { 2315 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2316 reg = <0x00b40000 0x10000>; 2317 2318 #global-interrupts = <1>; 2319 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2320 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2321 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2322 #iommu-cells = <1>; 2323 2324 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, 2325 <&mmcc GPU_AHB_CLK>; 2326 clock-names = "bus", "iface"; 2327 2328 power-domains = <&mmcc GPU_GDSC>; 2329 }; 2330 2331 venus: video-codec@c00000 { 2332 compatible = "qcom,msm8996-venus"; 2333 reg = <0x00c00000 0xff000>; 2334 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2335 power-domains = <&mmcc VENUS_GDSC>; 2336 clocks = <&mmcc VIDEO_CORE_CLK>, 2337 <&mmcc VIDEO_AHB_CLK>, 2338 <&mmcc VIDEO_AXI_CLK>, 2339 <&mmcc VIDEO_MAXI_CLK>; 2340 clock-names = "core", "iface", "bus", "mbus"; 2341 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2342 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2343 interconnect-names = "video-mem", "cpu-cfg"; 2344 iommus = <&venus_smmu 0x00>, 2345 <&venus_smmu 0x01>, 2346 <&venus_smmu 0x0a>, 2347 <&venus_smmu 0x07>, 2348 <&venus_smmu 0x0e>, 2349 <&venus_smmu 0x0f>, 2350 <&venus_smmu 0x08>, 2351 <&venus_smmu 0x09>, 2352 <&venus_smmu 0x0b>, 2353 <&venus_smmu 0x0c>, 2354 <&venus_smmu 0x0d>, 2355 <&venus_smmu 0x10>, 2356 <&venus_smmu 0x11>, 2357 <&venus_smmu 0x21>, 2358 <&venus_smmu 0x28>, 2359 <&venus_smmu 0x29>, 2360 <&venus_smmu 0x2b>, 2361 <&venus_smmu 0x2c>, 2362 <&venus_smmu 0x2d>, 2363 <&venus_smmu 0x31>; 2364 memory-region = <&venus_mem>; 2365 status = "disabled"; 2366 2367 video-decoder { 2368 compatible = "venus-decoder"; 2369 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2370 clock-names = "core"; 2371 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2372 }; 2373 2374 video-encoder { 2375 compatible = "venus-encoder"; 2376 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2377 clock-names = "core"; 2378 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2379 }; 2380 }; 2381 2382 mdp_smmu: iommu@d00000 { 2383 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2384 reg = <0x00d00000 0x10000>; 2385 2386 #global-interrupts = <1>; 2387 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2388 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2389 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2390 #iommu-cells = <1>; 2391 clocks = <&mmcc SMMU_MDP_AXI_CLK>, 2392 <&mmcc SMMU_MDP_AHB_CLK>; 2393 clock-names = "bus", "iface"; 2394 2395 power-domains = <&mmcc MDSS_GDSC>; 2396 }; 2397 2398 venus_smmu: iommu@d40000 { 2399 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2400 reg = <0x00d40000 0x20000>; 2401 #global-interrupts = <1>; 2402 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2405 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2406 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2407 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2408 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2409 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2410 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2411 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, 2412 <&mmcc SMMU_VIDEO_AHB_CLK>; 2413 clock-names = "bus", "iface"; 2414 #iommu-cells = <1>; 2415 status = "okay"; 2416 }; 2417 2418 vfe_smmu: iommu@da0000 { 2419 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2420 reg = <0x00da0000 0x10000>; 2421 2422 #global-interrupts = <1>; 2423 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2424 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2426 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2427 clocks = <&mmcc SMMU_VFE_AXI_CLK>, 2428 <&mmcc SMMU_VFE_AHB_CLK>; 2429 clock-names = "bus", "iface"; 2430 #iommu-cells = <1>; 2431 }; 2432 2433 lpass_q6_smmu: iommu@1600000 { 2434 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2435 reg = <0x01600000 0x20000>; 2436 #iommu-cells = <1>; 2437 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2438 2439 #global-interrupts = <1>; 2440 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2441 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2448 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2449 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2450 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2451 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2452 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2453 2454 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, 2455 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; 2456 clock-names = "bus", "iface"; 2457 }; 2458 2459 slpi_pil: remoteproc@1c00000 { 2460 compatible = "qcom,msm8996-slpi-pil"; 2461 reg = <0x01c00000 0x4000>; 2462 2463 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2464 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2465 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2466 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2467 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2468 interrupt-names = "wdog", 2469 "fatal", 2470 "ready", 2471 "handover", 2472 "stop-ack"; 2473 2474 clocks = <&xo_board>; 2475 clock-names = "xo"; 2476 2477 memory-region = <&slpi_mem>; 2478 2479 qcom,smem-states = <&slpi_smp2p_out 0>; 2480 qcom,smem-state-names = "stop"; 2481 2482 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2483 power-domain-names = "ssc_cx"; 2484 2485 status = "disabled"; 2486 2487 glink-edge { 2488 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 2489 label = "dsps"; 2490 qcom,remote-pid = <3>; 2491 mboxes = <&apcs_glb 27>; 2492 }; 2493 2494 smd-edge { 2495 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2496 2497 label = "dsps"; 2498 mboxes = <&apcs_glb 25>; 2499 qcom,smd-edge = <3>; 2500 qcom,remote-pid = <3>; 2501 }; 2502 }; 2503 2504 mss_pil: remoteproc@2080000 { 2505 compatible = "qcom,msm8996-mss-pil"; 2506 reg = <0x2080000 0x100>, 2507 <0x2180000 0x020>; 2508 reg-names = "qdsp6", "rmb"; 2509 2510 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2511 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2512 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2513 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2514 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2515 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2516 interrupt-names = "wdog", "fatal", "ready", 2517 "handover", "stop-ack", 2518 "shutdown-ack"; 2519 2520 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2521 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2522 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2523 <&xo_board>, 2524 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2525 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2526 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2527 <&rpmcc RPM_SMD_QDSS_CLK>; 2528 clock-names = "iface", 2529 "bus", 2530 "mem", 2531 "xo", 2532 "gpll0_mss", 2533 "snoc_axi", 2534 "mnoc_axi", 2535 "qdss"; 2536 2537 resets = <&gcc GCC_MSS_RESTART>; 2538 reset-names = "mss_restart"; 2539 2540 power-domains = <&rpmpd MSM8996_VDDCX>, 2541 <&rpmpd MSM8996_VDDMX>; 2542 power-domain-names = "cx", "mx"; 2543 2544 qcom,smem-states = <&mpss_smp2p_out 0>; 2545 qcom,smem-state-names = "stop"; 2546 2547 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2548 2549 status = "disabled"; 2550 2551 mba { 2552 memory-region = <&mba_mem>; 2553 }; 2554 2555 mpss { 2556 memory-region = <&mpss_mem>; 2557 }; 2558 2559 metadata { 2560 memory-region = <&mdata_mem>; 2561 }; 2562 2563 glink-edge { 2564 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 2565 label = "modem"; 2566 qcom,remote-pid = <1>; 2567 mboxes = <&apcs_glb 15>; 2568 }; 2569 2570 smd-edge { 2571 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2572 2573 label = "mpss"; 2574 mboxes = <&apcs_glb 12>; 2575 qcom,smd-edge = <0>; 2576 qcom,remote-pid = <1>; 2577 }; 2578 }; 2579 2580 stm@3002000 { 2581 compatible = "arm,coresight-stm", "arm,primecell"; 2582 reg = <0x3002000 0x1000>, 2583 <0x8280000 0x180000>; 2584 reg-names = "stm-base", "stm-stimulus-base"; 2585 2586 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2587 clock-names = "apb_pclk", "atclk"; 2588 2589 out-ports { 2590 port { 2591 stm_out: endpoint { 2592 remote-endpoint = 2593 <&funnel0_in>; 2594 }; 2595 }; 2596 }; 2597 }; 2598 2599 tpiu@3020000 { 2600 compatible = "arm,coresight-tpiu", "arm,primecell"; 2601 reg = <0x3020000 0x1000>; 2602 2603 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2604 clock-names = "apb_pclk", "atclk"; 2605 2606 in-ports { 2607 port { 2608 tpiu_in: endpoint { 2609 remote-endpoint = 2610 <&replicator_out1>; 2611 }; 2612 }; 2613 }; 2614 }; 2615 2616 funnel@3021000 { 2617 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2618 reg = <0x3021000 0x1000>; 2619 2620 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2621 clock-names = "apb_pclk", "atclk"; 2622 2623 in-ports { 2624 #address-cells = <1>; 2625 #size-cells = <0>; 2626 2627 port@7 { 2628 reg = <7>; 2629 funnel0_in: endpoint { 2630 remote-endpoint = 2631 <&stm_out>; 2632 }; 2633 }; 2634 }; 2635 2636 out-ports { 2637 port { 2638 funnel0_out: endpoint { 2639 remote-endpoint = 2640 <&merge_funnel_in0>; 2641 }; 2642 }; 2643 }; 2644 }; 2645 2646 funnel@3022000 { 2647 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2648 reg = <0x3022000 0x1000>; 2649 2650 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2651 clock-names = "apb_pclk", "atclk"; 2652 2653 in-ports { 2654 #address-cells = <1>; 2655 #size-cells = <0>; 2656 2657 port@6 { 2658 reg = <6>; 2659 funnel1_in: endpoint { 2660 remote-endpoint = 2661 <&apss_merge_funnel_out>; 2662 }; 2663 }; 2664 }; 2665 2666 out-ports { 2667 port { 2668 funnel1_out: endpoint { 2669 remote-endpoint = 2670 <&merge_funnel_in1>; 2671 }; 2672 }; 2673 }; 2674 }; 2675 2676 funnel@3023000 { 2677 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2678 reg = <0x3023000 0x1000>; 2679 2680 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2681 clock-names = "apb_pclk", "atclk"; 2682 2683 in-ports { 2684 port { 2685 funnel_in2_in_modem_etm: endpoint { 2686 remote-endpoint = 2687 <&modem_etm_out_funnel_in2>; 2688 }; 2689 }; 2690 }; 2691 2692 out-ports { 2693 port { 2694 funnel2_out: endpoint { 2695 remote-endpoint = 2696 <&merge_funnel_in2>; 2697 }; 2698 }; 2699 }; 2700 }; 2701 2702 funnel@3025000 { 2703 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2704 reg = <0x3025000 0x1000>; 2705 2706 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2707 clock-names = "apb_pclk", "atclk"; 2708 2709 in-ports { 2710 #address-cells = <1>; 2711 #size-cells = <0>; 2712 2713 port@0 { 2714 reg = <0>; 2715 merge_funnel_in0: endpoint { 2716 remote-endpoint = 2717 <&funnel0_out>; 2718 }; 2719 }; 2720 2721 port@1 { 2722 reg = <1>; 2723 merge_funnel_in1: endpoint { 2724 remote-endpoint = 2725 <&funnel1_out>; 2726 }; 2727 }; 2728 2729 port@2 { 2730 reg = <2>; 2731 merge_funnel_in2: endpoint { 2732 remote-endpoint = 2733 <&funnel2_out>; 2734 }; 2735 }; 2736 }; 2737 2738 out-ports { 2739 port { 2740 merge_funnel_out: endpoint { 2741 remote-endpoint = 2742 <&etf_in>; 2743 }; 2744 }; 2745 }; 2746 }; 2747 2748 replicator@3026000 { 2749 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2750 reg = <0x3026000 0x1000>; 2751 2752 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2753 clock-names = "apb_pclk", "atclk"; 2754 2755 in-ports { 2756 port { 2757 replicator_in: endpoint { 2758 remote-endpoint = 2759 <&etf_out>; 2760 }; 2761 }; 2762 }; 2763 2764 out-ports { 2765 #address-cells = <1>; 2766 #size-cells = <0>; 2767 2768 port@0 { 2769 reg = <0>; 2770 replicator_out0: endpoint { 2771 remote-endpoint = 2772 <&etr_in>; 2773 }; 2774 }; 2775 2776 port@1 { 2777 reg = <1>; 2778 replicator_out1: endpoint { 2779 remote-endpoint = 2780 <&tpiu_in>; 2781 }; 2782 }; 2783 }; 2784 }; 2785 2786 etf@3027000 { 2787 compatible = "arm,coresight-tmc", "arm,primecell"; 2788 reg = <0x3027000 0x1000>; 2789 2790 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2791 clock-names = "apb_pclk", "atclk"; 2792 2793 in-ports { 2794 port { 2795 etf_in: endpoint { 2796 remote-endpoint = 2797 <&merge_funnel_out>; 2798 }; 2799 }; 2800 }; 2801 2802 out-ports { 2803 port { 2804 etf_out: endpoint { 2805 remote-endpoint = 2806 <&replicator_in>; 2807 }; 2808 }; 2809 }; 2810 }; 2811 2812 etr@3028000 { 2813 compatible = "arm,coresight-tmc", "arm,primecell"; 2814 reg = <0x3028000 0x1000>; 2815 2816 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2817 clock-names = "apb_pclk", "atclk"; 2818 arm,scatter-gather; 2819 2820 in-ports { 2821 port { 2822 etr_in: endpoint { 2823 remote-endpoint = 2824 <&replicator_out0>; 2825 }; 2826 }; 2827 }; 2828 }; 2829 2830 debug@3810000 { 2831 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2832 reg = <0x3810000 0x1000>; 2833 2834 clocks = <&rpmcc RPM_QDSS_CLK>; 2835 clock-names = "apb_pclk"; 2836 2837 cpu = <&cpu0>; 2838 }; 2839 2840 etm@3840000 { 2841 compatible = "arm,coresight-etm4x", "arm,primecell"; 2842 reg = <0x3840000 0x1000>; 2843 2844 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2845 clock-names = "apb_pclk", "atclk"; 2846 2847 cpu = <&cpu0>; 2848 2849 out-ports { 2850 port { 2851 etm0_out: endpoint { 2852 remote-endpoint = 2853 <&apss_funnel0_in0>; 2854 }; 2855 }; 2856 }; 2857 }; 2858 2859 debug@3910000 { 2860 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2861 reg = <0x3910000 0x1000>; 2862 2863 clocks = <&rpmcc RPM_QDSS_CLK>; 2864 clock-names = "apb_pclk"; 2865 2866 cpu = <&cpu1>; 2867 }; 2868 2869 etm@3940000 { 2870 compatible = "arm,coresight-etm4x", "arm,primecell"; 2871 reg = <0x3940000 0x1000>; 2872 2873 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2874 clock-names = "apb_pclk", "atclk"; 2875 2876 cpu = <&cpu1>; 2877 2878 out-ports { 2879 port { 2880 etm1_out: endpoint { 2881 remote-endpoint = 2882 <&apss_funnel0_in1>; 2883 }; 2884 }; 2885 }; 2886 }; 2887 2888 funnel@39b0000 { /* APSS Funnel 0 */ 2889 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2890 reg = <0x39b0000 0x1000>; 2891 2892 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2893 clock-names = "apb_pclk", "atclk"; 2894 2895 in-ports { 2896 #address-cells = <1>; 2897 #size-cells = <0>; 2898 2899 port@0 { 2900 reg = <0>; 2901 apss_funnel0_in0: endpoint { 2902 remote-endpoint = <&etm0_out>; 2903 }; 2904 }; 2905 2906 port@1 { 2907 reg = <1>; 2908 apss_funnel0_in1: endpoint { 2909 remote-endpoint = <&etm1_out>; 2910 }; 2911 }; 2912 }; 2913 2914 out-ports { 2915 port { 2916 apss_funnel0_out: endpoint { 2917 remote-endpoint = 2918 <&apss_merge_funnel_in0>; 2919 }; 2920 }; 2921 }; 2922 }; 2923 2924 debug@3a10000 { 2925 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2926 reg = <0x3a10000 0x1000>; 2927 2928 clocks = <&rpmcc RPM_QDSS_CLK>; 2929 clock-names = "apb_pclk"; 2930 2931 cpu = <&cpu2>; 2932 }; 2933 2934 etm@3a40000 { 2935 compatible = "arm,coresight-etm4x", "arm,primecell"; 2936 reg = <0x3a40000 0x1000>; 2937 2938 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2939 clock-names = "apb_pclk", "atclk"; 2940 2941 cpu = <&cpu2>; 2942 2943 out-ports { 2944 port { 2945 etm2_out: endpoint { 2946 remote-endpoint = 2947 <&apss_funnel1_in0>; 2948 }; 2949 }; 2950 }; 2951 }; 2952 2953 debug@3b10000 { 2954 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2955 reg = <0x3b10000 0x1000>; 2956 2957 clocks = <&rpmcc RPM_QDSS_CLK>; 2958 clock-names = "apb_pclk"; 2959 2960 cpu = <&cpu3>; 2961 }; 2962 2963 etm@3b40000 { 2964 compatible = "arm,coresight-etm4x", "arm,primecell"; 2965 reg = <0x3b40000 0x1000>; 2966 2967 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2968 clock-names = "apb_pclk", "atclk"; 2969 2970 cpu = <&cpu3>; 2971 2972 out-ports { 2973 port { 2974 etm3_out: endpoint { 2975 remote-endpoint = 2976 <&apss_funnel1_in1>; 2977 }; 2978 }; 2979 }; 2980 }; 2981 2982 funnel@3bb0000 { /* APSS Funnel 1 */ 2983 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2984 reg = <0x3bb0000 0x1000>; 2985 2986 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2987 clock-names = "apb_pclk", "atclk"; 2988 2989 in-ports { 2990 #address-cells = <1>; 2991 #size-cells = <0>; 2992 2993 port@0 { 2994 reg = <0>; 2995 apss_funnel1_in0: endpoint { 2996 remote-endpoint = <&etm2_out>; 2997 }; 2998 }; 2999 3000 port@1 { 3001 reg = <1>; 3002 apss_funnel1_in1: endpoint { 3003 remote-endpoint = <&etm3_out>; 3004 }; 3005 }; 3006 }; 3007 3008 out-ports { 3009 port { 3010 apss_funnel1_out: endpoint { 3011 remote-endpoint = 3012 <&apss_merge_funnel_in1>; 3013 }; 3014 }; 3015 }; 3016 }; 3017 3018 funnel@3bc0000 { 3019 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3020 reg = <0x3bc0000 0x1000>; 3021 3022 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 3023 clock-names = "apb_pclk", "atclk"; 3024 3025 in-ports { 3026 #address-cells = <1>; 3027 #size-cells = <0>; 3028 3029 port@0 { 3030 reg = <0>; 3031 apss_merge_funnel_in0: endpoint { 3032 remote-endpoint = 3033 <&apss_funnel0_out>; 3034 }; 3035 }; 3036 3037 port@1 { 3038 reg = <1>; 3039 apss_merge_funnel_in1: endpoint { 3040 remote-endpoint = 3041 <&apss_funnel1_out>; 3042 }; 3043 }; 3044 }; 3045 3046 out-ports { 3047 port { 3048 apss_merge_funnel_out: endpoint { 3049 remote-endpoint = 3050 <&funnel1_in>; 3051 }; 3052 }; 3053 }; 3054 }; 3055 3056 kryocc: clock-controller@6400000 { 3057 compatible = "qcom,msm8996-apcc"; 3058 reg = <0x06400000 0x90000>; 3059 3060 clock-names = "xo", "sys_apcs_aux"; 3061 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3062 3063 #clock-cells = <1>; 3064 }; 3065 3066 usb3: usb@6af8800 { 3067 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3068 reg = <0x06af8800 0x400>; 3069 #address-cells = <1>; 3070 #size-cells = <1>; 3071 ranges; 3072 3073 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 3076 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 3077 interrupt-names = "pwr_event", 3078 "qusb2_phy", 3079 "hs_phy_irq", 3080 "ss_phy_irq"; 3081 3082 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 3083 <&gcc GCC_USB30_MASTER_CLK>, 3084 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 3085 <&gcc GCC_USB30_SLEEP_CLK>, 3086 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 3087 clock-names = "cfg_noc", 3088 "core", 3089 "iface", 3090 "sleep", 3091 "mock_utmi"; 3092 3093 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 3094 <&gcc GCC_USB30_MASTER_CLK>; 3095 assigned-clock-rates = <19200000>, <120000000>; 3096 3097 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 3098 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 3099 interconnect-names = "usb-ddr", "apps-usb"; 3100 3101 power-domains = <&gcc USB30_GDSC>; 3102 status = "disabled"; 3103 3104 usb3_dwc3: usb@6a00000 { 3105 compatible = "snps,dwc3"; 3106 reg = <0x06a00000 0xcc00>; 3107 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 3108 phys = <&hsusb_phy1>, <&usb3phy>; 3109 phy-names = "usb2-phy", "usb3-phy"; 3110 snps,hird-threshold = /bits/ 8 <0>; 3111 snps,dis_u2_susphy_quirk; 3112 snps,dis_enblslpm_quirk; 3113 snps,is-utmi-l1-suspend; 3114 snps,parkmode-disable-ss-quirk; 3115 tx-fifo-resize; 3116 }; 3117 }; 3118 3119 usb3phy: phy@7410000 { 3120 compatible = "qcom,msm8996-qmp-usb3-phy"; 3121 reg = <0x07410000 0x1000>; 3122 3123 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 3124 <&gcc GCC_USB3_CLKREF_CLK>, 3125 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3126 <&gcc GCC_USB3_PHY_PIPE_CLK>; 3127 clock-names = "aux", 3128 "ref", 3129 "cfg_ahb", 3130 "pipe"; 3131 clock-output-names = "usb3_phy_pipe_clk_src"; 3132 #clock-cells = <0>; 3133 #phy-cells = <0>; 3134 3135 resets = <&gcc GCC_USB3_PHY_BCR>, 3136 <&gcc GCC_USB3PHY_PHY_BCR>; 3137 reset-names = "phy", 3138 "phy_phy"; 3139 3140 status = "disabled"; 3141 }; 3142 3143 hsusb_phy1: phy@7411000 { 3144 compatible = "qcom,msm8996-qusb2-phy"; 3145 reg = <0x07411000 0x180>; 3146 #phy-cells = <0>; 3147 3148 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3149 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3150 clock-names = "cfg_ahb", "ref"; 3151 3152 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3153 nvmem-cells = <&qusb2p_hstx_trim>; 3154 status = "disabled"; 3155 }; 3156 3157 hsusb_phy2: phy@7412000 { 3158 compatible = "qcom,msm8996-qusb2-phy"; 3159 reg = <0x07412000 0x180>; 3160 #phy-cells = <0>; 3161 3162 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3163 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3164 clock-names = "cfg_ahb", "ref"; 3165 3166 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3167 nvmem-cells = <&qusb2s_hstx_trim>; 3168 status = "disabled"; 3169 }; 3170 3171 sdhc1: mmc@7464900 { 3172 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3173 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3174 reg-names = "hc", "core"; 3175 3176 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3178 interrupt-names = "hc_irq", "pwr_irq"; 3179 3180 clock-names = "iface", "core", "xo"; 3181 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3182 <&gcc GCC_SDCC1_APPS_CLK>, 3183 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3184 resets = <&gcc GCC_SDCC1_BCR>; 3185 3186 pinctrl-names = "default", "sleep"; 3187 pinctrl-0 = <&sdc1_state_on>; 3188 pinctrl-1 = <&sdc1_state_off>; 3189 3190 bus-width = <8>; 3191 non-removable; 3192 status = "disabled"; 3193 }; 3194 3195 sdhc2: mmc@74a4900 { 3196 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3197 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3198 reg-names = "hc", "core"; 3199 3200 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3201 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3202 interrupt-names = "hc_irq", "pwr_irq"; 3203 3204 clock-names = "iface", "core", "xo"; 3205 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3206 <&gcc GCC_SDCC2_APPS_CLK>, 3207 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3208 resets = <&gcc GCC_SDCC2_BCR>; 3209 3210 pinctrl-names = "default", "sleep"; 3211 pinctrl-0 = <&sdc2_state_on>; 3212 pinctrl-1 = <&sdc2_state_off>; 3213 3214 bus-width = <4>; 3215 status = "disabled"; 3216 }; 3217 3218 blsp1_dma: dma-controller@7544000 { 3219 compatible = "qcom,bam-v1.7.0"; 3220 reg = <0x07544000 0x2b000>; 3221 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3222 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3223 clock-names = "bam_clk"; 3224 qcom,controlled-remotely; 3225 #dma-cells = <1>; 3226 qcom,ee = <0>; 3227 }; 3228 3229 blsp1_uart2: serial@7570000 { 3230 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3231 reg = <0x07570000 0x1000>; 3232 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3233 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3234 <&gcc GCC_BLSP1_AHB_CLK>; 3235 clock-names = "core", "iface"; 3236 pinctrl-names = "default", "sleep"; 3237 pinctrl-0 = <&blsp1_uart2_default>; 3238 pinctrl-1 = <&blsp1_uart2_sleep>; 3239 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3240 dma-names = "tx", "rx"; 3241 status = "disabled"; 3242 }; 3243 3244 blsp1_spi1: spi@7575000 { 3245 compatible = "qcom,spi-qup-v2.2.1"; 3246 reg = <0x07575000 0x600>; 3247 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3248 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3249 <&gcc GCC_BLSP1_AHB_CLK>; 3250 clock-names = "core", "iface"; 3251 pinctrl-names = "default", "sleep"; 3252 pinctrl-0 = <&blsp1_spi1_default>; 3253 pinctrl-1 = <&blsp1_spi1_sleep>; 3254 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3255 dma-names = "tx", "rx"; 3256 #address-cells = <1>; 3257 #size-cells = <0>; 3258 status = "disabled"; 3259 }; 3260 3261 blsp1_i2c3: i2c@7577000 { 3262 compatible = "qcom,i2c-qup-v2.2.1"; 3263 reg = <0x07577000 0x1000>; 3264 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3265 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3266 <&gcc GCC_BLSP1_AHB_CLK>; 3267 clock-names = "core", "iface"; 3268 pinctrl-names = "default", "sleep"; 3269 pinctrl-0 = <&blsp1_i2c3_default>; 3270 pinctrl-1 = <&blsp1_i2c3_sleep>; 3271 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3272 dma-names = "tx", "rx"; 3273 #address-cells = <1>; 3274 #size-cells = <0>; 3275 status = "disabled"; 3276 }; 3277 3278 blsp1_i2c6: i2c@757a000 { 3279 compatible = "qcom,i2c-qup-v2.2.1"; 3280 reg = <0x757a000 0x1000>; 3281 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3282 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 3283 <&gcc GCC_BLSP1_AHB_CLK>; 3284 clock-names = "core", "iface"; 3285 pinctrl-names = "default", "sleep"; 3286 pinctrl-0 = <&blsp1_i2c6_default>; 3287 pinctrl-1 = <&blsp1_i2c6_sleep>; 3288 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 3289 dma-names = "tx", "rx"; 3290 #address-cells = <1>; 3291 #size-cells = <0>; 3292 status = "disabled"; 3293 }; 3294 3295 blsp2_dma: dma-controller@7584000 { 3296 compatible = "qcom,bam-v1.7.0"; 3297 reg = <0x07584000 0x2b000>; 3298 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3299 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3300 clock-names = "bam_clk"; 3301 qcom,controlled-remotely; 3302 #dma-cells = <1>; 3303 qcom,ee = <0>; 3304 }; 3305 3306 blsp2_uart2: serial@75b0000 { 3307 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3308 reg = <0x075b0000 0x1000>; 3309 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3310 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3311 <&gcc GCC_BLSP2_AHB_CLK>; 3312 clock-names = "core", "iface"; 3313 status = "disabled"; 3314 }; 3315 3316 blsp2_uart3: serial@75b1000 { 3317 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3318 reg = <0x075b1000 0x1000>; 3319 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3320 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3321 <&gcc GCC_BLSP2_AHB_CLK>; 3322 clock-names = "core", "iface"; 3323 status = "disabled"; 3324 }; 3325 3326 blsp2_i2c1: i2c@75b5000 { 3327 compatible = "qcom,i2c-qup-v2.2.1"; 3328 reg = <0x075b5000 0x1000>; 3329 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3330 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3331 <&gcc GCC_BLSP2_AHB_CLK>; 3332 clock-names = "core", "iface"; 3333 pinctrl-names = "default", "sleep"; 3334 pinctrl-0 = <&blsp2_i2c1_default>; 3335 pinctrl-1 = <&blsp2_i2c1_sleep>; 3336 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3337 dma-names = "tx", "rx"; 3338 #address-cells = <1>; 3339 #size-cells = <0>; 3340 status = "disabled"; 3341 }; 3342 3343 blsp2_i2c2: i2c@75b6000 { 3344 compatible = "qcom,i2c-qup-v2.2.1"; 3345 reg = <0x075b6000 0x1000>; 3346 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3347 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3348 <&gcc GCC_BLSP2_AHB_CLK>; 3349 clock-names = "core", "iface"; 3350 pinctrl-names = "default", "sleep"; 3351 pinctrl-0 = <&blsp2_i2c2_default>; 3352 pinctrl-1 = <&blsp2_i2c2_sleep>; 3353 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3354 dma-names = "tx", "rx"; 3355 #address-cells = <1>; 3356 #size-cells = <0>; 3357 status = "disabled"; 3358 }; 3359 3360 blsp2_i2c3: i2c@75b7000 { 3361 compatible = "qcom,i2c-qup-v2.2.1"; 3362 reg = <0x075b7000 0x1000>; 3363 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3364 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3365 <&gcc GCC_BLSP2_AHB_CLK>; 3366 clock-names = "core", "iface"; 3367 clock-frequency = <400000>; 3368 pinctrl-names = "default", "sleep"; 3369 pinctrl-0 = <&blsp2_i2c3_default>; 3370 pinctrl-1 = <&blsp2_i2c3_sleep>; 3371 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3372 dma-names = "tx", "rx"; 3373 #address-cells = <1>; 3374 #size-cells = <0>; 3375 status = "disabled"; 3376 }; 3377 3378 blsp2_i2c5: i2c@75b9000 { 3379 compatible = "qcom,i2c-qup-v2.2.1"; 3380 reg = <0x75b9000 0x1000>; 3381 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3382 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3383 <&gcc GCC_BLSP2_AHB_CLK>; 3384 clock-names = "core", "iface"; 3385 pinctrl-names = "default"; 3386 pinctrl-0 = <&blsp2_i2c5_default>; 3387 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3388 dma-names = "tx", "rx"; 3389 #address-cells = <1>; 3390 #size-cells = <0>; 3391 status = "disabled"; 3392 }; 3393 3394 blsp2_i2c6: i2c@75ba000 { 3395 compatible = "qcom,i2c-qup-v2.2.1"; 3396 reg = <0x75ba000 0x1000>; 3397 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3398 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3399 <&gcc GCC_BLSP2_AHB_CLK>; 3400 clock-names = "core", "iface"; 3401 pinctrl-names = "default", "sleep"; 3402 pinctrl-0 = <&blsp2_i2c6_default>; 3403 pinctrl-1 = <&blsp2_i2c6_sleep>; 3404 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3405 dma-names = "tx", "rx"; 3406 #address-cells = <1>; 3407 #size-cells = <0>; 3408 status = "disabled"; 3409 }; 3410 3411 blsp2_spi6: spi@75ba000 { 3412 compatible = "qcom,spi-qup-v2.2.1"; 3413 reg = <0x075ba000 0x600>; 3414 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3415 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3416 <&gcc GCC_BLSP2_AHB_CLK>; 3417 clock-names = "core", "iface"; 3418 pinctrl-names = "default", "sleep"; 3419 pinctrl-0 = <&blsp2_spi6_default>; 3420 pinctrl-1 = <&blsp2_spi6_sleep>; 3421 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3422 dma-names = "tx", "rx"; 3423 #address-cells = <1>; 3424 #size-cells = <0>; 3425 status = "disabled"; 3426 }; 3427 3428 usb2: usb@76f8800 { 3429 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3430 reg = <0x076f8800 0x400>; 3431 #address-cells = <1>; 3432 #size-cells = <1>; 3433 ranges; 3434 3435 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 3436 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 3437 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 3438 interrupt-names = "pwr_event", 3439 "qusb2_phy", 3440 "hs_phy_irq"; 3441 3442 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3443 <&gcc GCC_USB20_MASTER_CLK>, 3444 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3445 <&gcc GCC_USB20_SLEEP_CLK>, 3446 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3447 clock-names = "cfg_noc", 3448 "core", 3449 "iface", 3450 "sleep", 3451 "mock_utmi"; 3452 3453 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3454 <&gcc GCC_USB20_MASTER_CLK>; 3455 assigned-clock-rates = <19200000>, <60000000>; 3456 3457 power-domains = <&gcc USB30_GDSC>; 3458 qcom,select-utmi-as-pipe-clk; 3459 status = "disabled"; 3460 3461 usb2_dwc3: usb@7600000 { 3462 compatible = "snps,dwc3"; 3463 reg = <0x07600000 0xcc00>; 3464 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3465 phys = <&hsusb_phy2>; 3466 phy-names = "usb2-phy"; 3467 maximum-speed = "high-speed"; 3468 snps,dis_u2_susphy_quirk; 3469 snps,dis_enblslpm_quirk; 3470 }; 3471 }; 3472 3473 slimbam: dma-controller@9184000 { 3474 compatible = "qcom,bam-v1.7.0"; 3475 qcom,controlled-remotely; 3476 reg = <0x09184000 0x32000>; 3477 num-channels = <31>; 3478 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 3479 #dma-cells = <1>; 3480 qcom,ee = <1>; 3481 qcom,num-ees = <2>; 3482 }; 3483 3484 slim_msm: slim-ngd@91c0000 { 3485 compatible = "qcom,slim-ngd-v1.5.0"; 3486 reg = <0x091c0000 0x2c000>; 3487 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3488 dmas = <&slimbam 3>, <&slimbam 4>; 3489 dma-names = "rx", "tx"; 3490 #address-cells = <1>; 3491 #size-cells = <0>; 3492 3493 status = "disabled"; 3494 }; 3495 3496 adsp_pil: remoteproc@9300000 { 3497 compatible = "qcom,msm8996-adsp-pil"; 3498 reg = <0x09300000 0x80000>; 3499 3500 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3501 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3502 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3503 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3504 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3505 interrupt-names = "wdog", "fatal", "ready", 3506 "handover", "stop-ack"; 3507 3508 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3509 clock-names = "xo"; 3510 3511 memory-region = <&adsp_mem>; 3512 3513 qcom,smem-states = <&adsp_smp2p_out 0>; 3514 qcom,smem-state-names = "stop"; 3515 3516 power-domains = <&rpmpd MSM8996_VDDCX>; 3517 power-domain-names = "cx"; 3518 3519 status = "disabled"; 3520 3521 glink-edge { 3522 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 3523 label = "lpass"; 3524 qcom,remote-pid = <2>; 3525 mboxes = <&apcs_glb 9>; 3526 }; 3527 3528 3529 smd-edge { 3530 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3531 3532 label = "lpass"; 3533 mboxes = <&apcs_glb 8>; 3534 qcom,smd-edge = <1>; 3535 qcom,remote-pid = <2>; 3536 3537 apr { 3538 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3539 compatible = "qcom,apr-v2"; 3540 qcom,smd-channels = "apr_audio_svc"; 3541 qcom,domain = <APR_DOMAIN_ADSP>; 3542 #address-cells = <1>; 3543 #size-cells = <0>; 3544 3545 service@3 { 3546 reg = <APR_SVC_ADSP_CORE>; 3547 compatible = "qcom,q6core"; 3548 }; 3549 3550 q6afe: service@4 { 3551 compatible = "qcom,q6afe"; 3552 reg = <APR_SVC_AFE>; 3553 q6afedai: dais { 3554 compatible = "qcom,q6afe-dais"; 3555 #address-cells = <1>; 3556 #size-cells = <0>; 3557 #sound-dai-cells = <1>; 3558 dai@1 { 3559 reg = <1>; 3560 }; 3561 }; 3562 }; 3563 3564 q6asm: service@7 { 3565 compatible = "qcom,q6asm"; 3566 reg = <APR_SVC_ASM>; 3567 q6asmdai: dais { 3568 compatible = "qcom,q6asm-dais"; 3569 #address-cells = <1>; 3570 #size-cells = <0>; 3571 #sound-dai-cells = <1>; 3572 iommus = <&lpass_q6_smmu 1>; 3573 }; 3574 }; 3575 3576 q6adm: service@8 { 3577 compatible = "qcom,q6adm"; 3578 reg = <APR_SVC_ADM>; 3579 q6routing: routing { 3580 compatible = "qcom,q6adm-routing"; 3581 #sound-dai-cells = <0>; 3582 }; 3583 }; 3584 }; 3585 3586 fastrpc { 3587 compatible = "qcom,fastrpc"; 3588 qcom,smd-channels = "fastrpcsmd-apps-dsp"; 3589 label = "adsp"; 3590 qcom,non-secure-domain; 3591 #address-cells = <1>; 3592 #size-cells = <0>; 3593 3594 cb@5 { 3595 compatible = "qcom,fastrpc-compute-cb"; 3596 reg = <5>; 3597 iommus = <&lpass_q6_smmu 5>; 3598 }; 3599 3600 cb@6 { 3601 compatible = "qcom,fastrpc-compute-cb"; 3602 reg = <6>; 3603 iommus = <&lpass_q6_smmu 6>; 3604 }; 3605 3606 cb@7 { 3607 compatible = "qcom,fastrpc-compute-cb"; 3608 reg = <7>; 3609 iommus = <&lpass_q6_smmu 7>; 3610 }; 3611 3612 cb@8 { 3613 compatible = "qcom,fastrpc-compute-cb"; 3614 reg = <8>; 3615 iommus = <&lpass_q6_smmu 8>; 3616 }; 3617 3618 cb@9 { 3619 compatible = "qcom,fastrpc-compute-cb"; 3620 reg = <9>; 3621 iommus = <&lpass_q6_smmu 9>; 3622 }; 3623 3624 cb@10 { 3625 compatible = "qcom,fastrpc-compute-cb"; 3626 reg = <10>; 3627 iommus = <&lpass_q6_smmu 10>; 3628 }; 3629 3630 cb@11 { 3631 compatible = "qcom,fastrpc-compute-cb"; 3632 reg = <11>; 3633 iommus = <&lpass_q6_smmu 11>; 3634 }; 3635 3636 cb@12 { 3637 compatible = "qcom,fastrpc-compute-cb"; 3638 reg = <12>; 3639 iommus = <&lpass_q6_smmu 12>; 3640 }; 3641 }; 3642 }; 3643 }; 3644 3645 apcs_glb: mailbox@9820000 { 3646 compatible = "qcom,msm8996-apcs-hmss-global"; 3647 reg = <0x09820000 0x1000>; 3648 3649 #mbox-cells = <1>; 3650 #clock-cells = <0>; 3651 }; 3652 3653 timer@9840000 { 3654 #address-cells = <1>; 3655 #size-cells = <1>; 3656 ranges; 3657 compatible = "arm,armv7-timer-mem"; 3658 reg = <0x09840000 0x1000>; 3659 clock-frequency = <19200000>; 3660 3661 frame@9850000 { 3662 frame-number = <0>; 3663 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3665 reg = <0x09850000 0x1000>, 3666 <0x09860000 0x1000>; 3667 }; 3668 3669 frame@9870000 { 3670 frame-number = <1>; 3671 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3672 reg = <0x09870000 0x1000>; 3673 status = "disabled"; 3674 }; 3675 3676 frame@9880000 { 3677 frame-number = <2>; 3678 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3679 reg = <0x09880000 0x1000>; 3680 status = "disabled"; 3681 }; 3682 3683 frame@9890000 { 3684 frame-number = <3>; 3685 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3686 reg = <0x09890000 0x1000>; 3687 status = "disabled"; 3688 }; 3689 3690 frame@98a0000 { 3691 frame-number = <4>; 3692 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3693 reg = <0x098a0000 0x1000>; 3694 status = "disabled"; 3695 }; 3696 3697 frame@98b0000 { 3698 frame-number = <5>; 3699 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3700 reg = <0x098b0000 0x1000>; 3701 status = "disabled"; 3702 }; 3703 3704 frame@98c0000 { 3705 frame-number = <6>; 3706 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3707 reg = <0x098c0000 0x1000>; 3708 status = "disabled"; 3709 }; 3710 }; 3711 3712 saw3: syscon@9a10000 { 3713 compatible = "syscon"; 3714 reg = <0x09a10000 0x1000>; 3715 }; 3716 3717 cbf: clock-controller@9a11000 { 3718 compatible = "qcom,msm8996-cbf"; 3719 reg = <0x09a11000 0x10000>; 3720 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3721 #clock-cells = <0>; 3722 #interconnect-cells = <1>; 3723 }; 3724 3725 intc: interrupt-controller@9bc0000 { 3726 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3727 #interrupt-cells = <3>; 3728 interrupt-controller; 3729 #redistributor-regions = <1>; 3730 redistributor-stride = <0x0 0x40000>; 3731 reg = <0x09bc0000 0x10000>, 3732 <0x09c00000 0x100000>; 3733 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3734 }; 3735 }; 3736 3737 sound: sound { 3738 }; 3739 3740 thermal-zones { 3741 cpu0-thermal { 3742 polling-delay-passive = <250>; 3743 3744 thermal-sensors = <&tsens0 3>; 3745 3746 trips { 3747 cpu0_alert0: trip-point0 { 3748 temperature = <75000>; 3749 hysteresis = <2000>; 3750 type = "passive"; 3751 }; 3752 3753 cpu0_crit: cpu-crit { 3754 temperature = <110000>; 3755 hysteresis = <2000>; 3756 type = "critical"; 3757 }; 3758 }; 3759 }; 3760 3761 cpu1-thermal { 3762 polling-delay-passive = <250>; 3763 3764 thermal-sensors = <&tsens0 5>; 3765 3766 trips { 3767 cpu1_alert0: trip-point0 { 3768 temperature = <75000>; 3769 hysteresis = <2000>; 3770 type = "passive"; 3771 }; 3772 3773 cpu1_crit: cpu-crit { 3774 temperature = <110000>; 3775 hysteresis = <2000>; 3776 type = "critical"; 3777 }; 3778 }; 3779 }; 3780 3781 cpu2-thermal { 3782 polling-delay-passive = <250>; 3783 3784 thermal-sensors = <&tsens0 8>; 3785 3786 trips { 3787 cpu2_alert0: trip-point0 { 3788 temperature = <75000>; 3789 hysteresis = <2000>; 3790 type = "passive"; 3791 }; 3792 3793 cpu2_crit: cpu-crit { 3794 temperature = <110000>; 3795 hysteresis = <2000>; 3796 type = "critical"; 3797 }; 3798 }; 3799 }; 3800 3801 cpu3-thermal { 3802 polling-delay-passive = <250>; 3803 3804 thermal-sensors = <&tsens0 10>; 3805 3806 trips { 3807 cpu3_alert0: trip-point0 { 3808 temperature = <75000>; 3809 hysteresis = <2000>; 3810 type = "passive"; 3811 }; 3812 3813 cpu3_crit: cpu-crit { 3814 temperature = <110000>; 3815 hysteresis = <2000>; 3816 type = "critical"; 3817 }; 3818 }; 3819 }; 3820 3821 gpu-top-thermal { 3822 polling-delay-passive = <250>; 3823 3824 thermal-sensors = <&tsens1 6>; 3825 3826 trips { 3827 gpu1_alert0: trip-point0 { 3828 temperature = <90000>; 3829 hysteresis = <2000>; 3830 type = "passive"; 3831 }; 3832 }; 3833 3834 cooling-maps { 3835 map0 { 3836 trip = <&gpu1_alert0>; 3837 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3838 }; 3839 }; 3840 }; 3841 3842 gpu-bottom-thermal { 3843 polling-delay-passive = <250>; 3844 3845 thermal-sensors = <&tsens1 7>; 3846 3847 trips { 3848 gpu2_alert0: trip-point0 { 3849 temperature = <90000>; 3850 hysteresis = <2000>; 3851 type = "passive"; 3852 }; 3853 }; 3854 3855 cooling-maps { 3856 map0 { 3857 trip = <&gpu2_alert0>; 3858 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3859 }; 3860 }; 3861 }; 3862 3863 m4m-thermal { 3864 polling-delay-passive = <250>; 3865 3866 thermal-sensors = <&tsens0 1>; 3867 3868 trips { 3869 m4m_alert0: trip-point0 { 3870 temperature = <90000>; 3871 hysteresis = <2000>; 3872 type = "hot"; 3873 }; 3874 }; 3875 }; 3876 3877 l3-or-venus-thermal { 3878 polling-delay-passive = <250>; 3879 3880 thermal-sensors = <&tsens0 2>; 3881 3882 trips { 3883 l3_or_venus_alert0: trip-point0 { 3884 temperature = <90000>; 3885 hysteresis = <2000>; 3886 type = "hot"; 3887 }; 3888 }; 3889 }; 3890 3891 cluster0-l2-thermal { 3892 polling-delay-passive = <250>; 3893 3894 thermal-sensors = <&tsens0 7>; 3895 3896 trips { 3897 cluster0_l2_alert0: trip-point0 { 3898 temperature = <90000>; 3899 hysteresis = <2000>; 3900 type = "hot"; 3901 }; 3902 }; 3903 }; 3904 3905 cluster1-l2-thermal { 3906 polling-delay-passive = <250>; 3907 3908 thermal-sensors = <&tsens0 12>; 3909 3910 trips { 3911 cluster1_l2_alert0: trip-point0 { 3912 temperature = <90000>; 3913 hysteresis = <2000>; 3914 type = "hot"; 3915 }; 3916 }; 3917 }; 3918 3919 camera-thermal { 3920 polling-delay-passive = <250>; 3921 3922 thermal-sensors = <&tsens1 1>; 3923 3924 trips { 3925 camera_alert0: trip-point0 { 3926 temperature = <90000>; 3927 hysteresis = <2000>; 3928 type = "hot"; 3929 }; 3930 }; 3931 }; 3932 3933 q6-dsp-thermal { 3934 polling-delay-passive = <250>; 3935 3936 thermal-sensors = <&tsens1 2>; 3937 3938 trips { 3939 q6_dsp_alert0: trip-point0 { 3940 temperature = <90000>; 3941 hysteresis = <2000>; 3942 type = "hot"; 3943 }; 3944 }; 3945 }; 3946 3947 mem-thermal { 3948 polling-delay-passive = <250>; 3949 3950 thermal-sensors = <&tsens1 3>; 3951 3952 trips { 3953 mem_alert0: trip-point0 { 3954 temperature = <90000>; 3955 hysteresis = <2000>; 3956 type = "hot"; 3957 }; 3958 }; 3959 }; 3960 3961 modemtx-thermal { 3962 polling-delay-passive = <250>; 3963 3964 thermal-sensors = <&tsens1 4>; 3965 3966 trips { 3967 modemtx_alert0: trip-point0 { 3968 temperature = <90000>; 3969 hysteresis = <2000>; 3970 type = "hot"; 3971 }; 3972 }; 3973 }; 3974 }; 3975 3976 timer { 3977 compatible = "arm,armv8-timer"; 3978 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3979 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3980 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3981 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3982 }; 3983}; 3984