1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 3 */ 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8996.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,apr.h> 10 11/ { 12 interrupt-parent = <&intc>; 13 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo_board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <19200000>; 24 clock-output-names = "xo_board"; 25 }; 26 27 sleep_clk: sleep_clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <32764>; 31 clock-output-names = "sleep_clk"; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "qcom,kryo"; 42 reg = <0x0 0x0>; 43 enable-method = "psci"; 44 cpu-idle-states = <&CPU_SLEEP_0>; 45 capacity-dmips-mhz = <1024>; 46 next-level-cache = <&L2_0>; 47 L2_0: l2-cache { 48 compatible = "cache"; 49 cache-level = <2>; 50 }; 51 }; 52 53 CPU1: cpu@1 { 54 device_type = "cpu"; 55 compatible = "qcom,kryo"; 56 reg = <0x0 0x1>; 57 enable-method = "psci"; 58 cpu-idle-states = <&CPU_SLEEP_0>; 59 capacity-dmips-mhz = <1024>; 60 next-level-cache = <&L2_0>; 61 }; 62 63 CPU2: cpu@100 { 64 device_type = "cpu"; 65 compatible = "qcom,kryo"; 66 reg = <0x0 0x100>; 67 enable-method = "psci"; 68 cpu-idle-states = <&CPU_SLEEP_0>; 69 capacity-dmips-mhz = <1024>; 70 next-level-cache = <&L2_1>; 71 L2_1: l2-cache { 72 compatible = "cache"; 73 cache-level = <2>; 74 }; 75 }; 76 77 CPU3: cpu@101 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo"; 80 reg = <0x0 0x101>; 81 enable-method = "psci"; 82 cpu-idle-states = <&CPU_SLEEP_0>; 83 capacity-dmips-mhz = <1024>; 84 next-level-cache = <&L2_1>; 85 }; 86 87 cpu-map { 88 cluster0 { 89 core0 { 90 cpu = <&CPU0>; 91 }; 92 93 core1 { 94 cpu = <&CPU1>; 95 }; 96 }; 97 98 cluster1 { 99 core0 { 100 cpu = <&CPU2>; 101 }; 102 103 core1 { 104 cpu = <&CPU3>; 105 }; 106 }; 107 }; 108 109 idle-states { 110 entry-method = "psci"; 111 112 CPU_SLEEP_0: cpu-sleep-0 { 113 compatible = "arm,idle-state"; 114 idle-state-name = "standalone-power-collapse"; 115 arm,psci-suspend-param = <0x00000004>; 116 entry-latency-us = <130>; 117 exit-latency-us = <80>; 118 min-residency-us = <300>; 119 }; 120 }; 121 }; 122 123 firmware { 124 scm { 125 compatible = "qcom,scm-msm8996"; 126 qcom,dload-mode = <&tcsr 0x13000>; 127 }; 128 }; 129 130 tcsr_mutex: hwlock { 131 compatible = "qcom,tcsr-mutex"; 132 syscon = <&tcsr_mutex_regs 0 0x1000>; 133 #hwlock-cells = <1>; 134 }; 135 136 memory { 137 device_type = "memory"; 138 /* We expect the bootloader to fill in the reg */ 139 reg = <0 0 0 0>; 140 }; 141 142 psci { 143 compatible = "arm,psci-1.0"; 144 method = "smc"; 145 }; 146 147 reserved-memory { 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges; 151 152 mba_region: mba@91500000 { 153 reg = <0x0 0x91500000 0x0 0x200000>; 154 no-map; 155 }; 156 157 slpi_region: slpi@90b00000 { 158 reg = <0x0 0x90b00000 0x0 0xa00000>; 159 no-map; 160 }; 161 162 venus_region: venus@90400000 { 163 reg = <0x0 0x90400000 0x0 0x700000>; 164 no-map; 165 }; 166 167 adsp_region: adsp@8ea00000 { 168 reg = <0x0 0x8ea00000 0x0 0x1a00000>; 169 no-map; 170 }; 171 172 mpss_region: mpss@88800000 { 173 reg = <0x0 0x88800000 0x0 0x6200000>; 174 no-map; 175 }; 176 177 smem_mem: smem-mem@86000000 { 178 reg = <0x0 0x86000000 0x0 0x200000>; 179 no-map; 180 }; 181 182 memory@85800000 { 183 reg = <0x0 0x85800000 0x0 0x800000>; 184 no-map; 185 }; 186 187 memory@86200000 { 188 reg = <0x0 0x86200000 0x0 0x2600000>; 189 no-map; 190 }; 191 192 rmtfs@86700000 { 193 compatible = "qcom,rmtfs-mem"; 194 195 size = <0x0 0x200000>; 196 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 197 no-map; 198 199 qcom,client-id = <1>; 200 qcom,vmid = <15>; 201 }; 202 203 zap_shader_region: gpu@8f200000 { 204 compatible = "shared-dma-pool"; 205 reg = <0x0 0x90b00000 0x0 0xa00000>; 206 no-map; 207 }; 208 }; 209 210 rpm-glink { 211 compatible = "qcom,glink-rpm"; 212 213 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 214 215 qcom,rpm-msg-ram = <&rpm_msg_ram>; 216 217 mboxes = <&apcs_glb 0>; 218 219 rpm_requests: rpm-requests { 220 compatible = "qcom,rpm-msm8996"; 221 qcom,glink-channels = "rpm_requests"; 222 223 rpmcc: qcom,rpmcc { 224 compatible = "qcom,rpmcc-msm8996"; 225 #clock-cells = <1>; 226 }; 227 228 rpmpd: power-controller { 229 compatible = "qcom,msm8996-rpmpd"; 230 #power-domain-cells = <1>; 231 operating-points-v2 = <&rpmpd_opp_table>; 232 233 rpmpd_opp_table: opp-table { 234 compatible = "operating-points-v2"; 235 236 rpmpd_opp1: opp1 { 237 opp-level = <1>; 238 }; 239 240 rpmpd_opp2: opp2 { 241 opp-level = <2>; 242 }; 243 244 rpmpd_opp3: opp3 { 245 opp-level = <3>; 246 }; 247 248 rpmpd_opp4: opp4 { 249 opp-level = <4>; 250 }; 251 252 rpmpd_opp5: opp5 { 253 opp-level = <5>; 254 }; 255 256 rpmpd_opp6: opp6 { 257 opp-level = <6>; 258 }; 259 }; 260 }; 261 }; 262 }; 263 264 smem { 265 compatible = "qcom,smem"; 266 memory-region = <&smem_mem>; 267 hwlocks = <&tcsr_mutex 3>; 268 }; 269 270 smp2p-adsp { 271 compatible = "qcom,smp2p"; 272 qcom,smem = <443>, <429>; 273 274 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; 275 276 mboxes = <&apcs_glb 10>; 277 278 qcom,local-pid = <0>; 279 qcom,remote-pid = <2>; 280 281 smp2p_adsp_out: master-kernel { 282 qcom,entry-name = "master-kernel"; 283 #qcom,smem-state-cells = <1>; 284 }; 285 286 smp2p_adsp_in: slave-kernel { 287 qcom,entry-name = "slave-kernel"; 288 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 }; 292 }; 293 294 smp2p-modem { 295 compatible = "qcom,smp2p"; 296 qcom,smem = <435>, <428>; 297 298 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 299 300 mboxes = <&apcs_glb 14>; 301 302 qcom,local-pid = <0>; 303 qcom,remote-pid = <1>; 304 305 modem_smp2p_out: master-kernel { 306 qcom,entry-name = "master-kernel"; 307 #qcom,smem-state-cells = <1>; 308 }; 309 310 modem_smp2p_in: slave-kernel { 311 qcom,entry-name = "slave-kernel"; 312 313 interrupt-controller; 314 #interrupt-cells = <2>; 315 }; 316 }; 317 318 smp2p-slpi { 319 compatible = "qcom,smp2p"; 320 qcom,smem = <481>, <430>; 321 322 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 323 324 mboxes = <&apcs_glb 26>; 325 326 qcom,local-pid = <0>; 327 qcom,remote-pid = <3>; 328 329 smp2p_slpi_in: slave-kernel { 330 qcom,entry-name = "slave-kernel"; 331 interrupt-controller; 332 #interrupt-cells = <2>; 333 }; 334 335 smp2p_slpi_out: master-kernel { 336 qcom,entry-name = "master-kernel"; 337 #qcom,smem-state-cells = <1>; 338 }; 339 }; 340 341 soc: soc { 342 #address-cells = <1>; 343 #size-cells = <1>; 344 ranges = <0 0 0 0xffffffff>; 345 compatible = "simple-bus"; 346 347 pcie_phy: phy@34000 { 348 compatible = "qcom,msm8996-qmp-pcie-phy"; 349 reg = <0x00034000 0x488>; 350 #clock-cells = <1>; 351 #address-cells = <1>; 352 #size-cells = <1>; 353 ranges; 354 355 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 356 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 357 <&gcc GCC_PCIE_CLKREF_CLK>; 358 clock-names = "aux", "cfg_ahb", "ref"; 359 360 resets = <&gcc GCC_PCIE_PHY_BCR>, 361 <&gcc GCC_PCIE_PHY_COM_BCR>, 362 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 363 reset-names = "phy", "common", "cfg"; 364 status = "disabled"; 365 366 pciephy_0: lane@35000 { 367 reg = <0x00035000 0x130>, 368 <0x00035200 0x200>, 369 <0x00035400 0x1dc>; 370 #phy-cells = <0>; 371 372 clock-output-names = "pcie_0_pipe_clk_src"; 373 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 374 clock-names = "pipe0"; 375 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 376 reset-names = "lane0"; 377 }; 378 379 pciephy_1: lane@36000 { 380 reg = <0x00036000 0x130>, 381 <0x00036200 0x200>, 382 <0x00036400 0x1dc>; 383 #phy-cells = <0>; 384 385 clock-output-names = "pcie_1_pipe_clk_src"; 386 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 387 clock-names = "pipe1"; 388 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 389 reset-names = "lane1"; 390 }; 391 392 pciephy_2: lane@37000 { 393 reg = <0x00037000 0x130>, 394 <0x00037200 0x200>, 395 <0x00037400 0x1dc>; 396 #phy-cells = <0>; 397 398 clock-output-names = "pcie_2_pipe_clk_src"; 399 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 400 clock-names = "pipe2"; 401 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 402 reset-names = "lane2"; 403 }; 404 }; 405 406 rpm_msg_ram: memory@68000 { 407 compatible = "qcom,rpm-msg-ram"; 408 reg = <0x00068000 0x6000>; 409 }; 410 411 qfprom@74000 { 412 compatible = "qcom,qfprom"; 413 reg = <0x00074000 0x8ff>; 414 #address-cells = <1>; 415 #size-cells = <1>; 416 417 qusb2p_hstx_trim: hstx_trim@24e { 418 reg = <0x24e 0x2>; 419 bits = <5 4>; 420 }; 421 422 qusb2s_hstx_trim: hstx_trim@24f { 423 reg = <0x24f 0x1>; 424 bits = <1 4>; 425 }; 426 427 gpu_speed_bin: gpu_speed_bin@133 { 428 reg = <0x133 0x1>; 429 bits = <5 3>; 430 }; 431 }; 432 433 rng: rng@83000 { 434 compatible = "qcom,prng-ee"; 435 reg = <0x00083000 0x1000>; 436 clocks = <&gcc GCC_PRNG_AHB_CLK>; 437 clock-names = "core"; 438 }; 439 440 gcc: clock-controller@300000 { 441 compatible = "qcom,gcc-msm8996"; 442 #clock-cells = <1>; 443 #reset-cells = <1>; 444 #power-domain-cells = <1>; 445 reg = <0x00300000 0x90000>; 446 447 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>; 448 clock-names = "cxo2"; 449 }; 450 451 tsens0: thermal-sensor@4a9000 { 452 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 453 reg = <0x004a9000 0x1000>, /* TM */ 454 <0x004a8000 0x1000>; /* SROT */ 455 #qcom,sensors = <13>; 456 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 458 interrupt-names = "uplow", "critical"; 459 #thermal-sensor-cells = <1>; 460 }; 461 462 tsens1: thermal-sensor@4ad000 { 463 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 464 reg = <0x004ad000 0x1000>, /* TM */ 465 <0x004ac000 0x1000>; /* SROT */ 466 #qcom,sensors = <8>; 467 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 469 interrupt-names = "uplow", "critical"; 470 #thermal-sensor-cells = <1>; 471 }; 472 473 tcsr_mutex_regs: syscon@740000 { 474 compatible = "syscon"; 475 reg = <0x00740000 0x20000>; 476 }; 477 478 tcsr: syscon@7a0000 { 479 compatible = "qcom,tcsr-msm8996", "syscon"; 480 reg = <0x007a0000 0x18000>; 481 }; 482 483 mmcc: clock-controller@8c0000 { 484 compatible = "qcom,mmcc-msm8996"; 485 #clock-cells = <1>; 486 #reset-cells = <1>; 487 #power-domain-cells = <1>; 488 reg = <0x008c0000 0x40000>; 489 assigned-clocks = <&mmcc MMPLL9_PLL>, 490 <&mmcc MMPLL1_PLL>, 491 <&mmcc MMPLL3_PLL>, 492 <&mmcc MMPLL4_PLL>, 493 <&mmcc MMPLL5_PLL>; 494 assigned-clock-rates = <624000000>, 495 <810000000>, 496 <980000000>, 497 <960000000>, 498 <825000000>; 499 }; 500 501 mdss: mdss@900000 { 502 compatible = "qcom,mdss"; 503 504 reg = <0x00900000 0x1000>, 505 <0x009b0000 0x1040>, 506 <0x009b8000 0x1040>; 507 reg-names = "mdss_phys", 508 "vbif_phys", 509 "vbif_nrt_phys"; 510 511 power-domains = <&mmcc MDSS_GDSC>; 512 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 513 514 interrupt-controller; 515 #interrupt-cells = <1>; 516 517 clocks = <&mmcc MDSS_AHB_CLK>; 518 clock-names = "iface"; 519 520 #address-cells = <1>; 521 #size-cells = <1>; 522 ranges; 523 524 mdp: mdp@901000 { 525 compatible = "qcom,mdp5"; 526 reg = <0x00901000 0x90000>; 527 reg-names = "mdp_phys"; 528 529 interrupt-parent = <&mdss>; 530 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 531 532 clocks = <&mmcc MDSS_AHB_CLK>, 533 <&mmcc MDSS_AXI_CLK>, 534 <&mmcc MDSS_MDP_CLK>, 535 <&mmcc SMMU_MDP_AXI_CLK>, 536 <&mmcc MDSS_VSYNC_CLK>; 537 clock-names = "iface", 538 "bus", 539 "core", 540 "iommu", 541 "vsync"; 542 543 iommus = <&mdp_smmu 0>; 544 545 ports { 546 #address-cells = <1>; 547 #size-cells = <0>; 548 549 port@0 { 550 reg = <0>; 551 mdp5_intf3_out: endpoint { 552 remote-endpoint = <&hdmi_in>; 553 }; 554 }; 555 }; 556 }; 557 558 hdmi: hdmi-tx@9a0000 { 559 compatible = "qcom,hdmi-tx-8996"; 560 reg = <0x009a0000 0x50c>, 561 <0x00070000 0x6158>, 562 <0x009e0000 0xfff>; 563 reg-names = "core_physical", 564 "qfprom_physical", 565 "hdcp_physical"; 566 567 interrupt-parent = <&mdss>; 568 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 569 570 clocks = <&mmcc MDSS_MDP_CLK>, 571 <&mmcc MDSS_AHB_CLK>, 572 <&mmcc MDSS_HDMI_CLK>, 573 <&mmcc MDSS_HDMI_AHB_CLK>, 574 <&mmcc MDSS_EXTPCLK_CLK>; 575 clock-names = 576 "mdp_core", 577 "iface", 578 "core", 579 "alt_iface", 580 "extp"; 581 582 phys = <&hdmi_phy>; 583 phy-names = "hdmi_phy"; 584 #sound-dai-cells = <1>; 585 586 ports { 587 #address-cells = <1>; 588 #size-cells = <0>; 589 590 port@0 { 591 reg = <0>; 592 hdmi_in: endpoint { 593 remote-endpoint = <&mdp5_intf3_out>; 594 }; 595 }; 596 }; 597 }; 598 599 hdmi_phy: hdmi-phy@9a0600 { 600 #phy-cells = <0>; 601 compatible = "qcom,hdmi-phy-8996"; 602 reg = <0x009a0600 0x1c4>, 603 <0x009a0a00 0x124>, 604 <0x009a0c00 0x124>, 605 <0x009a0e00 0x124>, 606 <0x009a1000 0x124>, 607 <0x009a1200 0x0c8>; 608 reg-names = "hdmi_pll", 609 "hdmi_tx_l0", 610 "hdmi_tx_l1", 611 "hdmi_tx_l2", 612 "hdmi_tx_l3", 613 "hdmi_phy"; 614 615 clocks = <&mmcc MDSS_AHB_CLK>, 616 <&gcc GCC_HDMI_CLKREF_CLK>; 617 clock-names = "iface", 618 "ref"; 619 }; 620 }; 621 gpu@b00000 { 622 compatible = "qcom,adreno-530.2", "qcom,adreno"; 623 #stream-id-cells = <16>; 624 625 reg = <0x00b00000 0x3f000>; 626 reg-names = "kgsl_3d0_reg_memory"; 627 628 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 629 630 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 631 <&mmcc GPU_AHB_CLK>, 632 <&mmcc GPU_GX_RBBMTIMER_CLK>, 633 <&gcc GCC_BIMC_GFX_CLK>, 634 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 635 636 clock-names = "core", 637 "iface", 638 "rbbmtimer", 639 "mem", 640 "mem_iface"; 641 642 power-domains = <&mmcc GPU_GX_GDSC>; 643 iommus = <&adreno_smmu 0>; 644 645 nvmem-cells = <&gpu_speed_bin>; 646 nvmem-cell-names = "speed_bin"; 647 648 qcom,gpu-quirk-two-pass-use-wfi; 649 qcom,gpu-quirk-fault-detect-mask; 650 651 operating-points-v2 = <&gpu_opp_table>; 652 653 gpu_opp_table: opp-table { 654 compatible ="operating-points-v2"; 655 656 /* 657 * 624Mhz and 560Mhz are only available on speed 658 * bin (1 << 0). All the rest are available on 659 * all bins of the hardware 660 */ 661 opp-624000000 { 662 opp-hz = /bits/ 64 <624000000>; 663 opp-supported-hw = <0x01>; 664 }; 665 opp-560000000 { 666 opp-hz = /bits/ 64 <560000000>; 667 opp-supported-hw = <0x01>; 668 }; 669 opp-510000000 { 670 opp-hz = /bits/ 64 <510000000>; 671 opp-supported-hw = <0xFF>; 672 }; 673 opp-401800000 { 674 opp-hz = /bits/ 64 <401800000>; 675 opp-supported-hw = <0xFF>; 676 }; 677 opp-315000000 { 678 opp-hz = /bits/ 64 <315000000>; 679 opp-supported-hw = <0xFF>; 680 }; 681 opp-214000000 { 682 opp-hz = /bits/ 64 <214000000>; 683 opp-supported-hw = <0xFF>; 684 }; 685 opp-133000000 { 686 opp-hz = /bits/ 64 <133000000>; 687 opp-supported-hw = <0xFF>; 688 }; 689 }; 690 691 zap-shader { 692 memory-region = <&zap_shader_region>; 693 }; 694 }; 695 696 msmgpio: pinctrl@1010000 { 697 compatible = "qcom,msm8996-pinctrl"; 698 reg = <0x01010000 0x300000>; 699 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 700 gpio-controller; 701 gpio-ranges = <&msmgpio 0 0 150>; 702 #gpio-cells = <2>; 703 interrupt-controller; 704 #interrupt-cells = <2>; 705 }; 706 707 spmi_bus: qcom,spmi@400f000 { 708 compatible = "qcom,spmi-pmic-arb"; 709 reg = <0x0400f000 0x1000>, 710 <0x04400000 0x800000>, 711 <0x04c00000 0x800000>, 712 <0x05800000 0x200000>, 713 <0x0400a000 0x002100>; 714 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 715 interrupt-names = "periph_irq"; 716 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 717 qcom,ee = <0>; 718 qcom,channel = <0>; 719 #address-cells = <2>; 720 #size-cells = <0>; 721 interrupt-controller; 722 #interrupt-cells = <4>; 723 }; 724 725 agnoc@0 { 726 power-domains = <&gcc AGGRE0_NOC_GDSC>; 727 compatible = "simple-pm-bus"; 728 #address-cells = <1>; 729 #size-cells = <1>; 730 ranges; 731 732 pcie0: pcie@600000 { 733 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 734 status = "disabled"; 735 power-domains = <&gcc PCIE0_GDSC>; 736 bus-range = <0x00 0xff>; 737 num-lanes = <1>; 738 739 reg = <0x00600000 0x2000>, 740 <0x0c000000 0xf1d>, 741 <0x0c000f20 0xa8>, 742 <0x0c100000 0x100000>; 743 reg-names = "parf", "dbi", "elbi","config"; 744 745 phys = <&pciephy_0>; 746 phy-names = "pciephy"; 747 748 #address-cells = <3>; 749 #size-cells = <2>; 750 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, 751 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 752 753 device_type = "pci"; 754 755 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 756 interrupt-names = "msi"; 757 #interrupt-cells = <1>; 758 interrupt-map-mask = <0 0 0 0x7>; 759 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 760 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 761 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 762 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 763 764 pinctrl-names = "default", "sleep"; 765 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; 766 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; 767 768 linux,pci-domain = <0>; 769 770 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 771 <&gcc GCC_PCIE_0_AUX_CLK>, 772 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 773 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 774 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 775 776 clock-names = "pipe", 777 "aux", 778 "cfg", 779 "bus_master", 780 "bus_slave"; 781 782 }; 783 784 pcie1: pcie@608000 { 785 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 786 power-domains = <&gcc PCIE1_GDSC>; 787 bus-range = <0x00 0xff>; 788 num-lanes = <1>; 789 790 status = "disabled"; 791 792 reg = <0x00608000 0x2000>, 793 <0x0d000000 0xf1d>, 794 <0x0d000f20 0xa8>, 795 <0x0d100000 0x100000>; 796 797 reg-names = "parf", "dbi", "elbi","config"; 798 799 phys = <&pciephy_1>; 800 phy-names = "pciephy"; 801 802 #address-cells = <3>; 803 #size-cells = <2>; 804 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, 805 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 806 807 device_type = "pci"; 808 809 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 810 interrupt-names = "msi"; 811 #interrupt-cells = <1>; 812 interrupt-map-mask = <0 0 0 0x7>; 813 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 814 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 815 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 816 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 817 818 pinctrl-names = "default", "sleep"; 819 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; 820 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; 821 822 linux,pci-domain = <1>; 823 824 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 825 <&gcc GCC_PCIE_1_AUX_CLK>, 826 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 827 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 828 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 829 830 clock-names = "pipe", 831 "aux", 832 "cfg", 833 "bus_master", 834 "bus_slave"; 835 }; 836 837 pcie2: pcie@610000 { 838 compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; 839 power-domains = <&gcc PCIE2_GDSC>; 840 bus-range = <0x00 0xff>; 841 num-lanes = <1>; 842 status = "disabled"; 843 reg = <0x00610000 0x2000>, 844 <0x0e000000 0xf1d>, 845 <0x0e000f20 0xa8>, 846 <0x0e100000 0x100000>; 847 848 reg-names = "parf", "dbi", "elbi","config"; 849 850 phys = <&pciephy_2>; 851 phy-names = "pciephy"; 852 853 #address-cells = <3>; 854 #size-cells = <2>; 855 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, 856 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 857 858 device_type = "pci"; 859 860 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 861 interrupt-names = "msi"; 862 #interrupt-cells = <1>; 863 interrupt-map-mask = <0 0 0 0x7>; 864 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 865 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 866 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 867 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 868 869 pinctrl-names = "default", "sleep"; 870 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; 871 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; 872 873 linux,pci-domain = <2>; 874 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 875 <&gcc GCC_PCIE_2_AUX_CLK>, 876 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 877 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 878 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 879 880 clock-names = "pipe", 881 "aux", 882 "cfg", 883 "bus_master", 884 "bus_slave"; 885 }; 886 }; 887 888 ufshc: ufshc@624000 { 889 compatible = "qcom,ufshc"; 890 reg = <0x00624000 0x2500>; 891 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 892 893 phys = <&ufsphy_lane>; 894 phy-names = "ufsphy"; 895 896 power-domains = <&gcc UFS_GDSC>; 897 898 clock-names = 899 "core_clk_src", 900 "core_clk", 901 "bus_clk", 902 "bus_aggr_clk", 903 "iface_clk", 904 "core_clk_unipro_src", 905 "core_clk_unipro", 906 "core_clk_ice", 907 "ref_clk", 908 "tx_lane0_sync_clk", 909 "rx_lane0_sync_clk"; 910 clocks = 911 <&gcc UFS_AXI_CLK_SRC>, 912 <&gcc GCC_UFS_AXI_CLK>, 913 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 914 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 915 <&gcc GCC_UFS_AHB_CLK>, 916 <&gcc UFS_ICE_CORE_CLK_SRC>, 917 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 918 <&gcc GCC_UFS_ICE_CORE_CLK>, 919 <&rpmcc RPM_SMD_LN_BB_CLK>, 920 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 921 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 922 freq-table-hz = 923 <100000000 200000000>, 924 <0 0>, 925 <0 0>, 926 <0 0>, 927 <0 0>, 928 <150000000 300000000>, 929 <0 0>, 930 <0 0>, 931 <0 0>, 932 <0 0>, 933 <0 0>; 934 935 lanes-per-direction = <1>; 936 #reset-cells = <1>; 937 status = "disabled"; 938 939 ufs_variant { 940 compatible = "qcom,ufs_variant"; 941 }; 942 }; 943 944 ufsphy: phy@627000 { 945 compatible = "qcom,msm8996-qmp-ufs-phy"; 946 reg = <0x00627000 0x1c4>; 947 #address-cells = <1>; 948 #size-cells = <1>; 949 ranges; 950 951 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 952 clock-names = "ref"; 953 954 resets = <&ufshc 0>; 955 reset-names = "ufsphy"; 956 status = "disabled"; 957 958 ufsphy_lane: lanes@627400 { 959 reg = <0x627400 0x12c>, 960 <0x627600 0x200>, 961 <0x627c00 0x1b4>; 962 #phy-cells = <0>; 963 }; 964 }; 965 966 camss: camss@a00000 { 967 compatible = "qcom,msm8996-camss"; 968 reg = <0x00a34000 0x1000>, 969 <0x00a00030 0x4>, 970 <0x00a35000 0x1000>, 971 <0x00a00038 0x4>, 972 <0x00a36000 0x1000>, 973 <0x00a00040 0x4>, 974 <0x00a30000 0x100>, 975 <0x00a30400 0x100>, 976 <0x00a30800 0x100>, 977 <0x00a30c00 0x100>, 978 <0x00a31000 0x500>, 979 <0x00a00020 0x10>, 980 <0x00a10000 0x1000>, 981 <0x00a14000 0x1000>; 982 reg-names = "csiphy0", 983 "csiphy0_clk_mux", 984 "csiphy1", 985 "csiphy1_clk_mux", 986 "csiphy2", 987 "csiphy2_clk_mux", 988 "csid0", 989 "csid1", 990 "csid2", 991 "csid3", 992 "ispif", 993 "csi_clk_mux", 994 "vfe0", 995 "vfe1"; 996 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 997 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 998 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 999 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1000 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1001 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1002 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1003 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1004 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1005 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1006 interrupt-names = "csiphy0", 1007 "csiphy1", 1008 "csiphy2", 1009 "csid0", 1010 "csid1", 1011 "csid2", 1012 "csid3", 1013 "ispif", 1014 "vfe0", 1015 "vfe1"; 1016 power-domains = <&mmcc VFE0_GDSC>, 1017 <&mmcc VFE1_GDSC>; 1018 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1019 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1020 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1021 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1022 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1023 <&mmcc CAMSS_CSI0_AHB_CLK>, 1024 <&mmcc CAMSS_CSI0_CLK>, 1025 <&mmcc CAMSS_CSI0PHY_CLK>, 1026 <&mmcc CAMSS_CSI0PIX_CLK>, 1027 <&mmcc CAMSS_CSI0RDI_CLK>, 1028 <&mmcc CAMSS_CSI1_AHB_CLK>, 1029 <&mmcc CAMSS_CSI1_CLK>, 1030 <&mmcc CAMSS_CSI1PHY_CLK>, 1031 <&mmcc CAMSS_CSI1PIX_CLK>, 1032 <&mmcc CAMSS_CSI1RDI_CLK>, 1033 <&mmcc CAMSS_CSI2_AHB_CLK>, 1034 <&mmcc CAMSS_CSI2_CLK>, 1035 <&mmcc CAMSS_CSI2PHY_CLK>, 1036 <&mmcc CAMSS_CSI2PIX_CLK>, 1037 <&mmcc CAMSS_CSI2RDI_CLK>, 1038 <&mmcc CAMSS_CSI3_AHB_CLK>, 1039 <&mmcc CAMSS_CSI3_CLK>, 1040 <&mmcc CAMSS_CSI3PHY_CLK>, 1041 <&mmcc CAMSS_CSI3PIX_CLK>, 1042 <&mmcc CAMSS_CSI3RDI_CLK>, 1043 <&mmcc CAMSS_AHB_CLK>, 1044 <&mmcc CAMSS_VFE0_CLK>, 1045 <&mmcc CAMSS_CSI_VFE0_CLK>, 1046 <&mmcc CAMSS_VFE0_AHB_CLK>, 1047 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1048 <&mmcc CAMSS_VFE1_CLK>, 1049 <&mmcc CAMSS_CSI_VFE1_CLK>, 1050 <&mmcc CAMSS_VFE1_AHB_CLK>, 1051 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1052 <&mmcc CAMSS_VFE_AHB_CLK>, 1053 <&mmcc CAMSS_VFE_AXI_CLK>; 1054 clock-names = "top_ahb", 1055 "ispif_ahb", 1056 "csiphy0_timer", 1057 "csiphy1_timer", 1058 "csiphy2_timer", 1059 "csi0_ahb", 1060 "csi0", 1061 "csi0_phy", 1062 "csi0_pix", 1063 "csi0_rdi", 1064 "csi1_ahb", 1065 "csi1", 1066 "csi1_phy", 1067 "csi1_pix", 1068 "csi1_rdi", 1069 "csi2_ahb", 1070 "csi2", 1071 "csi2_phy", 1072 "csi2_pix", 1073 "csi2_rdi", 1074 "csi3_ahb", 1075 "csi3", 1076 "csi3_phy", 1077 "csi3_pix", 1078 "csi3_rdi", 1079 "ahb", 1080 "vfe0", 1081 "csi_vfe0", 1082 "vfe0_ahb", 1083 "vfe0_stream", 1084 "vfe1", 1085 "csi_vfe1", 1086 "vfe1_ahb", 1087 "vfe1_stream", 1088 "vfe_ahb", 1089 "vfe_axi"; 1090 iommus = <&vfe_smmu 0>, 1091 <&vfe_smmu 1>, 1092 <&vfe_smmu 2>, 1093 <&vfe_smmu 3>; 1094 status = "disabled"; 1095 ports { 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 }; 1099 }; 1100 1101 cci: cci@a0c000 { 1102 compatible = "qcom,msm8996-cci"; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 reg = <0xa0c000 0x1000>; 1106 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 1107 power-domains = <&mmcc CAMSS_GDSC>; 1108 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1109 <&mmcc CAMSS_CCI_AHB_CLK>, 1110 <&mmcc CAMSS_CCI_CLK>, 1111 <&mmcc CAMSS_AHB_CLK>; 1112 clock-names = "camss_top_ahb", 1113 "cci_ahb", 1114 "cci", 1115 "camss_ahb"; 1116 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 1117 <&mmcc CAMSS_CCI_CLK>; 1118 assigned-clock-rates = <80000000>, <37500000>; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&cci0_default &cci1_default>; 1121 status = "disabled"; 1122 1123 cci_i2c0: i2c-bus@0 { 1124 reg = <0>; 1125 clock-frequency = <400000>; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 }; 1129 1130 cci_i2c1: i2c-bus@1 { 1131 reg = <1>; 1132 clock-frequency = <400000>; 1133 #address-cells = <1>; 1134 #size-cells = <0>; 1135 }; 1136 }; 1137 1138 adreno_smmu: iommu@b40000 { 1139 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1140 reg = <0x00b40000 0x10000>; 1141 1142 #global-interrupts = <1>; 1143 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1144 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1145 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1146 #iommu-cells = <1>; 1147 1148 clocks = <&mmcc GPU_AHB_CLK>, 1149 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1150 clock-names = "iface", "bus"; 1151 1152 power-domains = <&mmcc GPU_GDSC>; 1153 }; 1154 1155 video-codec@c00000 { 1156 compatible = "qcom,msm8996-venus"; 1157 reg = <0x00c00000 0xff000>; 1158 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 1159 power-domains = <&mmcc VENUS_GDSC>; 1160 clocks = <&mmcc VIDEO_CORE_CLK>, 1161 <&mmcc VIDEO_AHB_CLK>, 1162 <&mmcc VIDEO_AXI_CLK>, 1163 <&mmcc VIDEO_MAXI_CLK>; 1164 clock-names = "core", "iface", "bus", "mbus"; 1165 iommus = <&venus_smmu 0x00>, 1166 <&venus_smmu 0x01>, 1167 <&venus_smmu 0x0a>, 1168 <&venus_smmu 0x07>, 1169 <&venus_smmu 0x0e>, 1170 <&venus_smmu 0x0f>, 1171 <&venus_smmu 0x08>, 1172 <&venus_smmu 0x09>, 1173 <&venus_smmu 0x0b>, 1174 <&venus_smmu 0x0c>, 1175 <&venus_smmu 0x0d>, 1176 <&venus_smmu 0x10>, 1177 <&venus_smmu 0x11>, 1178 <&venus_smmu 0x21>, 1179 <&venus_smmu 0x28>, 1180 <&venus_smmu 0x29>, 1181 <&venus_smmu 0x2b>, 1182 <&venus_smmu 0x2c>, 1183 <&venus_smmu 0x2d>, 1184 <&venus_smmu 0x31>; 1185 memory-region = <&venus_region>; 1186 status = "okay"; 1187 1188 video-decoder { 1189 compatible = "venus-decoder"; 1190 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 1191 clock-names = "core"; 1192 power-domains = <&mmcc VENUS_CORE0_GDSC>; 1193 }; 1194 1195 video-encoder { 1196 compatible = "venus-encoder"; 1197 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 1198 clock-names = "core"; 1199 power-domains = <&mmcc VENUS_CORE1_GDSC>; 1200 }; 1201 }; 1202 1203 mdp_smmu: iommu@d00000 { 1204 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1205 reg = <0x00d00000 0x10000>; 1206 1207 #global-interrupts = <1>; 1208 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1211 #iommu-cells = <1>; 1212 clocks = <&mmcc SMMU_MDP_AHB_CLK>, 1213 <&mmcc SMMU_MDP_AXI_CLK>; 1214 clock-names = "iface", "bus"; 1215 1216 power-domains = <&mmcc MDSS_GDSC>; 1217 }; 1218 1219 venus_smmu: iommu@d40000 { 1220 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1221 reg = <0x00d40000 0x20000>; 1222 #global-interrupts = <1>; 1223 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 1231 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 1232 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, 1233 <&mmcc SMMU_VIDEO_AXI_CLK>; 1234 clock-names = "iface", "bus"; 1235 #iommu-cells = <1>; 1236 status = "okay"; 1237 }; 1238 1239 vfe_smmu: iommu@da0000 { 1240 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1241 reg = <0x00da0000 0x10000>; 1242 1243 #global-interrupts = <1>; 1244 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1247 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 1248 clocks = <&mmcc SMMU_VFE_AHB_CLK>, 1249 <&mmcc SMMU_VFE_AXI_CLK>; 1250 clock-names = "iface", 1251 "bus"; 1252 #iommu-cells = <1>; 1253 }; 1254 1255 lpass_q6_smmu: iommu@1600000 { 1256 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 1257 reg = <0x01600000 0x20000>; 1258 #iommu-cells = <1>; 1259 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 1260 1261 #global-interrupts = <1>; 1262 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 1275 1276 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, 1277 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 1278 clock-names = "iface", "bus"; 1279 }; 1280 1281 stm@3002000 { 1282 compatible = "arm,coresight-stm", "arm,primecell"; 1283 reg = <0x3002000 0x1000>, 1284 <0x8280000 0x180000>; 1285 reg-names = "stm-base", "stm-stimulus-base"; 1286 1287 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1288 clock-names = "apb_pclk", "atclk"; 1289 1290 out-ports { 1291 port { 1292 stm_out: endpoint { 1293 remote-endpoint = 1294 <&funnel0_in>; 1295 }; 1296 }; 1297 }; 1298 }; 1299 1300 tpiu@3020000 { 1301 compatible = "arm,coresight-tpiu", "arm,primecell"; 1302 reg = <0x3020000 0x1000>; 1303 1304 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1305 clock-names = "apb_pclk", "atclk"; 1306 1307 in-ports { 1308 port { 1309 tpiu_in: endpoint { 1310 remote-endpoint = 1311 <&replicator_out1>; 1312 }; 1313 }; 1314 }; 1315 }; 1316 1317 funnel@3021000 { 1318 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1319 reg = <0x3021000 0x1000>; 1320 1321 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1322 clock-names = "apb_pclk", "atclk"; 1323 1324 in-ports { 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 1328 port@7 { 1329 reg = <7>; 1330 funnel0_in: endpoint { 1331 remote-endpoint = 1332 <&stm_out>; 1333 }; 1334 }; 1335 }; 1336 1337 out-ports { 1338 port { 1339 funnel0_out: endpoint { 1340 remote-endpoint = 1341 <&merge_funnel_in0>; 1342 }; 1343 }; 1344 }; 1345 }; 1346 1347 funnel@3022000 { 1348 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1349 reg = <0x3022000 0x1000>; 1350 1351 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1352 clock-names = "apb_pclk", "atclk"; 1353 1354 in-ports { 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 1358 port@6 { 1359 reg = <6>; 1360 funnel1_in: endpoint { 1361 remote-endpoint = 1362 <&apss_merge_funnel_out>; 1363 }; 1364 }; 1365 }; 1366 1367 out-ports { 1368 port { 1369 funnel1_out: endpoint { 1370 remote-endpoint = 1371 <&merge_funnel_in1>; 1372 }; 1373 }; 1374 }; 1375 }; 1376 1377 funnel@3023000 { 1378 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1379 reg = <0x3023000 0x1000>; 1380 1381 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1382 clock-names = "apb_pclk", "atclk"; 1383 1384 1385 out-ports { 1386 port { 1387 funnel2_out: endpoint { 1388 remote-endpoint = 1389 <&merge_funnel_in2>; 1390 }; 1391 }; 1392 }; 1393 }; 1394 1395 funnel@3025000 { 1396 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1397 reg = <0x3025000 0x1000>; 1398 1399 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1400 clock-names = "apb_pclk", "atclk"; 1401 1402 in-ports { 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 1406 port@0 { 1407 reg = <0>; 1408 merge_funnel_in0: endpoint { 1409 remote-endpoint = 1410 <&funnel0_out>; 1411 }; 1412 }; 1413 1414 port@1 { 1415 reg = <1>; 1416 merge_funnel_in1: endpoint { 1417 remote-endpoint = 1418 <&funnel1_out>; 1419 }; 1420 }; 1421 1422 port@2 { 1423 reg = <2>; 1424 merge_funnel_in2: endpoint { 1425 remote-endpoint = 1426 <&funnel2_out>; 1427 }; 1428 }; 1429 }; 1430 1431 out-ports { 1432 port { 1433 merge_funnel_out: endpoint { 1434 remote-endpoint = 1435 <&etf_in>; 1436 }; 1437 }; 1438 }; 1439 }; 1440 1441 replicator@3026000 { 1442 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1443 reg = <0x3026000 0x1000>; 1444 1445 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1446 clock-names = "apb_pclk", "atclk"; 1447 1448 in-ports { 1449 port { 1450 replicator_in: endpoint { 1451 remote-endpoint = 1452 <&etf_out>; 1453 }; 1454 }; 1455 }; 1456 1457 out-ports { 1458 #address-cells = <1>; 1459 #size-cells = <0>; 1460 1461 port@0 { 1462 reg = <0>; 1463 replicator_out0: endpoint { 1464 remote-endpoint = 1465 <&etr_in>; 1466 }; 1467 }; 1468 1469 port@1 { 1470 reg = <1>; 1471 replicator_out1: endpoint { 1472 remote-endpoint = 1473 <&tpiu_in>; 1474 }; 1475 }; 1476 }; 1477 }; 1478 1479 etf@3027000 { 1480 compatible = "arm,coresight-tmc", "arm,primecell"; 1481 reg = <0x3027000 0x1000>; 1482 1483 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1484 clock-names = "apb_pclk", "atclk"; 1485 1486 in-ports { 1487 port { 1488 etf_in: endpoint { 1489 remote-endpoint = 1490 <&merge_funnel_out>; 1491 }; 1492 }; 1493 }; 1494 1495 out-ports { 1496 port { 1497 etf_out: endpoint { 1498 remote-endpoint = 1499 <&replicator_in>; 1500 }; 1501 }; 1502 }; 1503 }; 1504 1505 etr@3028000 { 1506 compatible = "arm,coresight-tmc", "arm,primecell"; 1507 reg = <0x3028000 0x1000>; 1508 1509 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1510 clock-names = "apb_pclk", "atclk"; 1511 arm,scatter-gather; 1512 1513 in-ports { 1514 port { 1515 etr_in: endpoint { 1516 remote-endpoint = 1517 <&replicator_out0>; 1518 }; 1519 }; 1520 }; 1521 }; 1522 1523 debug@3810000 { 1524 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1525 reg = <0x3810000 0x1000>; 1526 1527 clocks = <&rpmcc RPM_QDSS_CLK>; 1528 clock-names = "apb_pclk"; 1529 1530 cpu = <&CPU0>; 1531 }; 1532 1533 etm@3840000 { 1534 compatible = "arm,coresight-etm4x", "arm,primecell"; 1535 reg = <0x3840000 0x1000>; 1536 1537 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1538 clock-names = "apb_pclk", "atclk"; 1539 1540 cpu = <&CPU0>; 1541 1542 out-ports { 1543 port { 1544 etm0_out: endpoint { 1545 remote-endpoint = 1546 <&apss_funnel0_in0>; 1547 }; 1548 }; 1549 }; 1550 }; 1551 1552 debug@3910000 { 1553 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1554 reg = <0x3910000 0x1000>; 1555 1556 clocks = <&rpmcc RPM_QDSS_CLK>; 1557 clock-names = "apb_pclk"; 1558 1559 cpu = <&CPU1>; 1560 }; 1561 1562 etm@3940000 { 1563 compatible = "arm,coresight-etm4x", "arm,primecell"; 1564 reg = <0x3940000 0x1000>; 1565 1566 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1567 clock-names = "apb_pclk", "atclk"; 1568 1569 cpu = <&CPU1>; 1570 1571 out-ports { 1572 port { 1573 etm1_out: endpoint { 1574 remote-endpoint = 1575 <&apss_funnel0_in1>; 1576 }; 1577 }; 1578 }; 1579 }; 1580 1581 funnel@39b0000 { /* APSS Funnel 0 */ 1582 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1583 reg = <0x39b0000 0x1000>; 1584 1585 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1586 clock-names = "apb_pclk", "atclk"; 1587 1588 in-ports { 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 1592 port@0 { 1593 reg = <0>; 1594 apss_funnel0_in0: endpoint { 1595 remote-endpoint = <&etm0_out>; 1596 }; 1597 }; 1598 1599 port@1 { 1600 reg = <1>; 1601 apss_funnel0_in1: endpoint { 1602 remote-endpoint = <&etm1_out>; 1603 }; 1604 }; 1605 }; 1606 1607 out-ports { 1608 port { 1609 apss_funnel0_out: endpoint { 1610 remote-endpoint = 1611 <&apss_merge_funnel_in0>; 1612 }; 1613 }; 1614 }; 1615 }; 1616 1617 debug@3a10000 { 1618 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1619 reg = <0x3a10000 0x1000>; 1620 1621 clocks = <&rpmcc RPM_QDSS_CLK>; 1622 clock-names = "apb_pclk"; 1623 1624 cpu = <&CPU2>; 1625 }; 1626 1627 etm@3a40000 { 1628 compatible = "arm,coresight-etm4x", "arm,primecell"; 1629 reg = <0x3a40000 0x1000>; 1630 1631 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1632 clock-names = "apb_pclk", "atclk"; 1633 1634 cpu = <&CPU2>; 1635 1636 out-ports { 1637 port { 1638 etm2_out: endpoint { 1639 remote-endpoint = 1640 <&apss_funnel1_in0>; 1641 }; 1642 }; 1643 }; 1644 }; 1645 1646 debug@3b10000 { 1647 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 1648 reg = <0x3b10000 0x1000>; 1649 1650 clocks = <&rpmcc RPM_QDSS_CLK>; 1651 clock-names = "apb_pclk"; 1652 1653 cpu = <&CPU3>; 1654 }; 1655 1656 etm@3b40000 { 1657 compatible = "arm,coresight-etm4x", "arm,primecell"; 1658 reg = <0x3b40000 0x1000>; 1659 1660 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1661 clock-names = "apb_pclk", "atclk"; 1662 1663 cpu = <&CPU3>; 1664 1665 out-ports { 1666 port { 1667 etm3_out: endpoint { 1668 remote-endpoint = 1669 <&apss_funnel1_in1>; 1670 }; 1671 }; 1672 }; 1673 }; 1674 1675 funnel@3bb0000 { /* APSS Funnel 1 */ 1676 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1677 reg = <0x3bb0000 0x1000>; 1678 1679 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1680 clock-names = "apb_pclk", "atclk"; 1681 1682 in-ports { 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 1686 port@0 { 1687 reg = <0>; 1688 apss_funnel1_in0: endpoint { 1689 remote-endpoint = <&etm2_out>; 1690 }; 1691 }; 1692 1693 port@1 { 1694 reg = <1>; 1695 apss_funnel1_in1: endpoint { 1696 remote-endpoint = <&etm3_out>; 1697 }; 1698 }; 1699 }; 1700 1701 out-ports { 1702 port { 1703 apss_funnel1_out: endpoint { 1704 remote-endpoint = 1705 <&apss_merge_funnel_in1>; 1706 }; 1707 }; 1708 }; 1709 }; 1710 1711 funnel@3bc0000 { 1712 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1713 reg = <0x3bc0000 0x1000>; 1714 1715 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 1716 clock-names = "apb_pclk", "atclk"; 1717 1718 in-ports { 1719 #address-cells = <1>; 1720 #size-cells = <0>; 1721 1722 port@0 { 1723 reg = <0>; 1724 apss_merge_funnel_in0: endpoint { 1725 remote-endpoint = 1726 <&apss_funnel0_out>; 1727 }; 1728 }; 1729 1730 port@1 { 1731 reg = <1>; 1732 apss_merge_funnel_in1: endpoint { 1733 remote-endpoint = 1734 <&apss_funnel1_out>; 1735 }; 1736 }; 1737 }; 1738 1739 out-ports { 1740 port { 1741 apss_merge_funnel_out: endpoint { 1742 remote-endpoint = 1743 <&funnel1_in>; 1744 }; 1745 }; 1746 }; 1747 }; 1748 kryocc: clock-controller@6400000 { 1749 compatible = "qcom,apcc-msm8996"; 1750 reg = <0x06400000 0x90000>; 1751 #clock-cells = <1>; 1752 }; 1753 1754 usb3: usb@6af8800 { 1755 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 1756 reg = <0x06af8800 0x400>; 1757 #address-cells = <1>; 1758 #size-cells = <1>; 1759 ranges; 1760 1761 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 1762 <&gcc GCC_USB30_MASTER_CLK>, 1763 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1764 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1765 <&gcc GCC_USB30_SLEEP_CLK>, 1766 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 1767 1768 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1769 <&gcc GCC_USB30_MASTER_CLK>; 1770 assigned-clock-rates = <19200000>, <120000000>; 1771 1772 power-domains = <&gcc USB30_GDSC>; 1773 status = "disabled"; 1774 1775 dwc3@6a00000 { 1776 compatible = "snps,dwc3"; 1777 reg = <0x06a00000 0xcc00>; 1778 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; 1779 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 1780 phy-names = "usb2-phy", "usb3-phy"; 1781 snps,dis_u2_susphy_quirk; 1782 snps,dis_enblslpm_quirk; 1783 }; 1784 }; 1785 1786 usb3phy: phy@7410000 { 1787 compatible = "qcom,msm8996-qmp-usb3-phy"; 1788 reg = <0x07410000 0x1c4>; 1789 #clock-cells = <1>; 1790 #address-cells = <1>; 1791 #size-cells = <1>; 1792 ranges; 1793 1794 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1795 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1796 <&gcc GCC_USB3_CLKREF_CLK>; 1797 clock-names = "aux", "cfg_ahb", "ref"; 1798 1799 resets = <&gcc GCC_USB3_PHY_BCR>, 1800 <&gcc GCC_USB3PHY_PHY_BCR>; 1801 reset-names = "phy", "common"; 1802 status = "disabled"; 1803 1804 ssusb_phy_0: lane@7410200 { 1805 reg = <0x07410200 0x200>, 1806 <0x07410400 0x130>, 1807 <0x07410600 0x1a8>; 1808 #phy-cells = <0>; 1809 1810 clock-output-names = "usb3_phy_pipe_clk_src"; 1811 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 1812 clock-names = "pipe0"; 1813 }; 1814 }; 1815 1816 hsusb_phy1: phy@7411000 { 1817 compatible = "qcom,msm8996-qusb2-phy"; 1818 reg = <0x07411000 0x180>; 1819 #phy-cells = <0>; 1820 1821 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1822 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1823 clock-names = "cfg_ahb", "ref"; 1824 1825 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1826 nvmem-cells = <&qusb2p_hstx_trim>; 1827 status = "disabled"; 1828 }; 1829 1830 hsusb_phy2: phy@7412000 { 1831 compatible = "qcom,msm8996-qusb2-phy"; 1832 reg = <0x07412000 0x180>; 1833 #phy-cells = <0>; 1834 1835 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1836 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 1837 clock-names = "cfg_ahb", "ref"; 1838 1839 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1840 nvmem-cells = <&qusb2s_hstx_trim>; 1841 status = "disabled"; 1842 }; 1843 1844 sdhc2: sdhci@74a4900 { 1845 status = "disabled"; 1846 compatible = "qcom,sdhci-msm-v4"; 1847 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 1848 reg-names = "hc_mem", "core_mem"; 1849 1850 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, 1851 <0 221 IRQ_TYPE_LEVEL_HIGH>; 1852 interrupt-names = "hc_irq", "pwr_irq"; 1853 1854 clock-names = "iface", "core", "xo"; 1855 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1856 <&gcc GCC_SDCC2_APPS_CLK>, 1857 <&xo_board>; 1858 bus-width = <4>; 1859 }; 1860 1861 blsp1_uart1: serial@7570000 { 1862 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1863 reg = <0x07570000 0x1000>; 1864 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1865 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1866 <&gcc GCC_BLSP1_AHB_CLK>; 1867 clock-names = "core", "iface"; 1868 status = "disabled"; 1869 }; 1870 1871 blsp1_spi0: spi@7575000 { 1872 compatible = "qcom,spi-qup-v2.2.1"; 1873 reg = <0x07575000 0x600>; 1874 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1875 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1876 <&gcc GCC_BLSP1_AHB_CLK>; 1877 clock-names = "core", "iface"; 1878 pinctrl-names = "default", "sleep"; 1879 pinctrl-0 = <&blsp1_spi0_default>; 1880 pinctrl-1 = <&blsp1_spi0_sleep>; 1881 #address-cells = <1>; 1882 #size-cells = <0>; 1883 status = "disabled"; 1884 }; 1885 1886 blsp1_i2c2: i2c@7577000 { 1887 compatible = "qcom,i2c-qup-v2.2.1"; 1888 reg = <0x07577000 0x1000>; 1889 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1890 clocks = <&gcc GCC_BLSP1_AHB_CLK>, 1891 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 1892 clock-names = "iface", "core"; 1893 pinctrl-names = "default", "sleep"; 1894 pinctrl-0 = <&blsp1_i2c2_default>; 1895 pinctrl-1 = <&blsp1_i2c2_sleep>; 1896 #address-cells = <1>; 1897 #size-cells = <0>; 1898 status = "disabled"; 1899 }; 1900 1901 blsp2_uart1: serial@75b0000 { 1902 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1903 reg = <0x075b0000 0x1000>; 1904 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1905 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 1906 <&gcc GCC_BLSP2_AHB_CLK>; 1907 clock-names = "core", "iface"; 1908 status = "disabled"; 1909 }; 1910 1911 blsp2_uart2: serial@75b1000 { 1912 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1913 reg = <0x075b1000 0x1000>; 1914 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1915 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 1916 <&gcc GCC_BLSP2_AHB_CLK>; 1917 clock-names = "core", "iface"; 1918 status = "disabled"; 1919 }; 1920 1921 blsp2_i2c0: i2c@75b5000 { 1922 compatible = "qcom,i2c-qup-v2.2.1"; 1923 reg = <0x075b5000 0x1000>; 1924 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1925 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 1926 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; 1927 clock-names = "iface", "core"; 1928 pinctrl-names = "default", "sleep"; 1929 pinctrl-0 = <&blsp2_i2c0_default>; 1930 pinctrl-1 = <&blsp2_i2c0_sleep>; 1931 #address-cells = <1>; 1932 #size-cells = <0>; 1933 status = "disabled"; 1934 }; 1935 1936 blsp2_i2c1: i2c@75b6000 { 1937 compatible = "qcom,i2c-qup-v2.2.1"; 1938 reg = <0x075b6000 0x1000>; 1939 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1940 clocks = <&gcc GCC_BLSP2_AHB_CLK>, 1941 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; 1942 clock-names = "iface", "core"; 1943 pinctrl-names = "default", "sleep"; 1944 pinctrl-0 = <&blsp2_i2c1_default>; 1945 pinctrl-1 = <&blsp2_i2c1_sleep>; 1946 #address-cells = <1>; 1947 #size-cells = <0>; 1948 status = "disabled"; 1949 }; 1950 1951 blsp2_spi5: spi@75ba000{ 1952 compatible = "qcom,spi-qup-v2.2.1"; 1953 reg = <0x075ba000 0x600>; 1954 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1955 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 1956 <&gcc GCC_BLSP2_AHB_CLK>; 1957 clock-names = "core", "iface"; 1958 pinctrl-names = "default", "sleep"; 1959 pinctrl-0 = <&blsp2_spi5_default>; 1960 pinctrl-1 = <&blsp2_spi5_sleep>; 1961 #address-cells = <1>; 1962 #size-cells = <0>; 1963 status = "disabled"; 1964 }; 1965 1966 usb2: usb@76f8800 { 1967 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 1968 reg = <0x076f8800 0x400>; 1969 #address-cells = <1>; 1970 #size-cells = <1>; 1971 ranges; 1972 1973 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 1974 <&gcc GCC_USB20_MASTER_CLK>, 1975 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1976 <&gcc GCC_USB20_SLEEP_CLK>, 1977 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 1978 1979 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1980 <&gcc GCC_USB20_MASTER_CLK>; 1981 assigned-clock-rates = <19200000>, <60000000>; 1982 1983 power-domains = <&gcc USB30_GDSC>; 1984 status = "disabled"; 1985 1986 dwc3@7600000 { 1987 compatible = "snps,dwc3"; 1988 reg = <0x07600000 0xcc00>; 1989 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; 1990 phys = <&hsusb_phy2>; 1991 phy-names = "usb2-phy"; 1992 snps,dis_u2_susphy_quirk; 1993 snps,dis_enblslpm_quirk; 1994 }; 1995 }; 1996 1997 slimbam: dma-controller@9184000 { 1998 compatible = "qcom,bam-v1.7.0"; 1999 qcom,controlled-remotely; 2000 reg = <0x09184000 0x32000>; 2001 num-channels = <31>; 2002 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; 2003 #dma-cells = <1>; 2004 qcom,ee = <1>; 2005 qcom,num-ees = <2>; 2006 }; 2007 2008 slim_msm: slim@91c0000 { 2009 compatible = "qcom,slim-ngd-v1.5.0"; 2010 reg = <0x091c0000 0x2C000>; 2011 reg-names = "ctrl"; 2012 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; 2013 dmas = <&slimbam 3>, <&slimbam 4>, 2014 <&slimbam 5>, <&slimbam 6>; 2015 dma-names = "rx", "tx", "tx2", "rx2"; 2016 #address-cells = <1>; 2017 #size-cells = <0>; 2018 ngd@1 { 2019 reg = <1>; 2020 #address-cells = <1>; 2021 #size-cells = <1>; 2022 2023 tasha_ifd: tas-ifd { 2024 compatible = "slim217,1a0"; 2025 reg = <0 0>; 2026 }; 2027 2028 wcd9335: codec@1{ 2029 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; 2030 pinctrl-names = "default"; 2031 2032 compatible = "slim217,1a0"; 2033 reg = <1 0>; 2034 2035 interrupt-parent = <&msmgpio>; 2036 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, 2037 <53 IRQ_TYPE_LEVEL_HIGH>; 2038 interrupt-names = "intr1", "intr2"; 2039 interrupt-controller; 2040 #interrupt-cells = <1>; 2041 reset-gpios = <&msmgpio 64 0>; 2042 2043 slim-ifc-dev = <&tasha_ifd>; 2044 2045 #sound-dai-cells = <1>; 2046 }; 2047 }; 2048 }; 2049 2050 adsp_pil: remoteproc@9300000 { 2051 compatible = "qcom,msm8996-adsp-pil"; 2052 reg = <0x09300000 0x80000>; 2053 2054 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 2055 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2056 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2057 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2058 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2059 interrupt-names = "wdog", "fatal", "ready", 2060 "handover", "stop-ack"; 2061 2062 clocks = <&xo_board>; 2063 clock-names = "xo"; 2064 2065 memory-region = <&adsp_region>; 2066 2067 qcom,smem-states = <&smp2p_adsp_out 0>; 2068 qcom,smem-state-names = "stop"; 2069 2070 smd-edge { 2071 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 2072 2073 label = "lpass"; 2074 mboxes = <&apcs_glb 8>; 2075 qcom,smd-edge = <1>; 2076 qcom,remote-pid = <2>; 2077 #address-cells = <1>; 2078 #size-cells = <0>; 2079 apr { 2080 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 2081 compatible = "qcom,apr-v2"; 2082 qcom,smd-channels = "apr_audio_svc"; 2083 qcom,apr-domain = <APR_DOMAIN_ADSP>; 2084 #address-cells = <1>; 2085 #size-cells = <0>; 2086 2087 q6core { 2088 reg = <APR_SVC_ADSP_CORE>; 2089 compatible = "qcom,q6core"; 2090 }; 2091 2092 q6afe: q6afe { 2093 compatible = "qcom,q6afe"; 2094 reg = <APR_SVC_AFE>; 2095 q6afedai: dais { 2096 compatible = "qcom,q6afe-dais"; 2097 #address-cells = <1>; 2098 #size-cells = <0>; 2099 #sound-dai-cells = <1>; 2100 hdmi@1 { 2101 reg = <1>; 2102 }; 2103 }; 2104 }; 2105 2106 q6asm: q6asm { 2107 compatible = "qcom,q6asm"; 2108 reg = <APR_SVC_ASM>; 2109 q6asmdai: dais { 2110 compatible = "qcom,q6asm-dais"; 2111 #address-cells = <1>; 2112 #size-cells = <0>; 2113 #sound-dai-cells = <1>; 2114 iommus = <&lpass_q6_smmu 1>; 2115 }; 2116 }; 2117 2118 q6adm: q6adm { 2119 compatible = "qcom,q6adm"; 2120 reg = <APR_SVC_ADM>; 2121 q6routing: routing { 2122 compatible = "qcom,q6adm-routing"; 2123 #sound-dai-cells = <0>; 2124 }; 2125 }; 2126 }; 2127 2128 }; 2129 }; 2130 2131 apcs_glb: mailbox@9820000 { 2132 compatible = "qcom,msm8996-apcs-hmss-global"; 2133 reg = <0x09820000 0x1000>; 2134 2135 #mbox-cells = <1>; 2136 }; 2137 2138 timer@9840000 { 2139 #address-cells = <1>; 2140 #size-cells = <1>; 2141 ranges; 2142 compatible = "arm,armv7-timer-mem"; 2143 reg = <0x09840000 0x1000>; 2144 clock-frequency = <19200000>; 2145 2146 frame@9850000 { 2147 frame-number = <0>; 2148 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2150 reg = <0x09850000 0x1000>, 2151 <0x09860000 0x1000>; 2152 }; 2153 2154 frame@9870000 { 2155 frame-number = <1>; 2156 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 2157 reg = <0x09870000 0x1000>; 2158 status = "disabled"; 2159 }; 2160 2161 frame@9880000 { 2162 frame-number = <2>; 2163 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2164 reg = <0x09880000 0x1000>; 2165 status = "disabled"; 2166 }; 2167 2168 frame@9890000 { 2169 frame-number = <3>; 2170 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 2171 reg = <0x09890000 0x1000>; 2172 status = "disabled"; 2173 }; 2174 2175 frame@98a0000 { 2176 frame-number = <4>; 2177 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 2178 reg = <0x098a0000 0x1000>; 2179 status = "disabled"; 2180 }; 2181 2182 frame@98b0000 { 2183 frame-number = <5>; 2184 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2185 reg = <0x098b0000 0x1000>; 2186 status = "disabled"; 2187 }; 2188 2189 frame@98c0000 { 2190 frame-number = <6>; 2191 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2192 reg = <0x098c0000 0x1000>; 2193 status = "disabled"; 2194 }; 2195 }; 2196 2197 saw3: syscon@9a10000 { 2198 compatible = "syscon"; 2199 reg = <0x09a10000 0x1000>; 2200 }; 2201 2202 intc: interrupt-controller@9bc0000 { 2203 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 2204 #interrupt-cells = <3>; 2205 interrupt-controller; 2206 #redistributor-regions = <1>; 2207 redistributor-stride = <0x0 0x40000>; 2208 reg = <0x09bc0000 0x10000>, 2209 <0x09c00000 0x100000>; 2210 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2211 }; 2212 }; 2213 2214 sound: sound { 2215 }; 2216 2217 thermal-zones { 2218 cpu0-thermal { 2219 polling-delay-passive = <250>; 2220 polling-delay = <1000>; 2221 2222 thermal-sensors = <&tsens0 3>; 2223 2224 trips { 2225 cpu0_alert0: trip-point0 { 2226 temperature = <75000>; 2227 hysteresis = <2000>; 2228 type = "passive"; 2229 }; 2230 2231 cpu0_crit: cpu_crit { 2232 temperature = <110000>; 2233 hysteresis = <2000>; 2234 type = "critical"; 2235 }; 2236 }; 2237 }; 2238 2239 cpu1-thermal { 2240 polling-delay-passive = <250>; 2241 polling-delay = <1000>; 2242 2243 thermal-sensors = <&tsens0 5>; 2244 2245 trips { 2246 cpu1_alert0: trip-point0 { 2247 temperature = <75000>; 2248 hysteresis = <2000>; 2249 type = "passive"; 2250 }; 2251 2252 cpu1_crit: cpu_crit { 2253 temperature = <110000>; 2254 hysteresis = <2000>; 2255 type = "critical"; 2256 }; 2257 }; 2258 }; 2259 2260 cpu2-thermal { 2261 polling-delay-passive = <250>; 2262 polling-delay = <1000>; 2263 2264 thermal-sensors = <&tsens0 8>; 2265 2266 trips { 2267 cpu2_alert0: trip-point0 { 2268 temperature = <75000>; 2269 hysteresis = <2000>; 2270 type = "passive"; 2271 }; 2272 2273 cpu2_crit: cpu_crit { 2274 temperature = <110000>; 2275 hysteresis = <2000>; 2276 type = "critical"; 2277 }; 2278 }; 2279 }; 2280 2281 cpu3-thermal { 2282 polling-delay-passive = <250>; 2283 polling-delay = <1000>; 2284 2285 thermal-sensors = <&tsens0 10>; 2286 2287 trips { 2288 cpu3_alert0: trip-point0 { 2289 temperature = <75000>; 2290 hysteresis = <2000>; 2291 type = "passive"; 2292 }; 2293 2294 cpu3_crit: cpu_crit { 2295 temperature = <110000>; 2296 hysteresis = <2000>; 2297 type = "critical"; 2298 }; 2299 }; 2300 }; 2301 2302 gpu-thermal-top { 2303 polling-delay-passive = <250>; 2304 polling-delay = <1000>; 2305 2306 thermal-sensors = <&tsens1 6>; 2307 2308 trips { 2309 gpu1_alert0: trip-point0 { 2310 temperature = <90000>; 2311 hysteresis = <2000>; 2312 type = "hot"; 2313 }; 2314 }; 2315 }; 2316 2317 gpu-thermal-bottom { 2318 polling-delay-passive = <250>; 2319 polling-delay = <1000>; 2320 2321 thermal-sensors = <&tsens1 7>; 2322 2323 trips { 2324 gpu2_alert0: trip-point0 { 2325 temperature = <90000>; 2326 hysteresis = <2000>; 2327 type = "hot"; 2328 }; 2329 }; 2330 }; 2331 2332 m4m-thermal { 2333 polling-delay-passive = <250>; 2334 polling-delay = <1000>; 2335 2336 thermal-sensors = <&tsens0 1>; 2337 2338 trips { 2339 m4m_alert0: trip-point0 { 2340 temperature = <90000>; 2341 hysteresis = <2000>; 2342 type = "hot"; 2343 }; 2344 }; 2345 }; 2346 2347 l3-or-venus-thermal { 2348 polling-delay-passive = <250>; 2349 polling-delay = <1000>; 2350 2351 thermal-sensors = <&tsens0 2>; 2352 2353 trips { 2354 l3_or_venus_alert0: trip-point0 { 2355 temperature = <90000>; 2356 hysteresis = <2000>; 2357 type = "hot"; 2358 }; 2359 }; 2360 }; 2361 2362 cluster0-l2-thermal { 2363 polling-delay-passive = <250>; 2364 polling-delay = <1000>; 2365 2366 thermal-sensors = <&tsens0 7>; 2367 2368 trips { 2369 cluster0_l2_alert0: trip-point0 { 2370 temperature = <90000>; 2371 hysteresis = <2000>; 2372 type = "hot"; 2373 }; 2374 }; 2375 }; 2376 2377 cluster1-l2-thermal { 2378 polling-delay-passive = <250>; 2379 polling-delay = <1000>; 2380 2381 thermal-sensors = <&tsens0 12>; 2382 2383 trips { 2384 cluster1_l2_alert0: trip-point0 { 2385 temperature = <90000>; 2386 hysteresis = <2000>; 2387 type = "hot"; 2388 }; 2389 }; 2390 }; 2391 2392 camera-thermal { 2393 polling-delay-passive = <250>; 2394 polling-delay = <1000>; 2395 2396 thermal-sensors = <&tsens1 1>; 2397 2398 trips { 2399 camera_alert0: trip-point0 { 2400 temperature = <90000>; 2401 hysteresis = <2000>; 2402 type = "hot"; 2403 }; 2404 }; 2405 }; 2406 2407 q6-dsp-thermal { 2408 polling-delay-passive = <250>; 2409 polling-delay = <1000>; 2410 2411 thermal-sensors = <&tsens1 2>; 2412 2413 trips { 2414 q6_dsp_alert0: trip-point0 { 2415 temperature = <90000>; 2416 hysteresis = <2000>; 2417 type = "hot"; 2418 }; 2419 }; 2420 }; 2421 2422 mem-thermal { 2423 polling-delay-passive = <250>; 2424 polling-delay = <1000>; 2425 2426 thermal-sensors = <&tsens1 3>; 2427 2428 trips { 2429 mem_alert0: trip-point0 { 2430 temperature = <90000>; 2431 hysteresis = <2000>; 2432 type = "hot"; 2433 }; 2434 }; 2435 }; 2436 2437 modemtx-thermal { 2438 polling-delay-passive = <250>; 2439 polling-delay = <1000>; 2440 2441 thermal-sensors = <&tsens1 4>; 2442 2443 trips { 2444 modemtx_alert0: trip-point0 { 2445 temperature = <90000>; 2446 hysteresis = <2000>; 2447 type = "hot"; 2448 }; 2449 }; 2450 }; 2451 }; 2452 2453 timer { 2454 compatible = "arm,armv8-timer"; 2455 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2456 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2457 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2458 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2459 }; 2460}; 2461#include "msm8996-pins.dtsi" 2462