1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8996.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/interconnect/qcom,msm8996.h> 11#include <dt-bindings/interconnect/qcom,msm8996-cbf.h> 12#include <dt-bindings/firmware/qcom,scm.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,apr.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <19200000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32764>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "qcom,kryo"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 cpu-idle-states = <&CPU_SLEEP_0>; 52 capacity-dmips-mhz = <1024>; 53 clocks = <&kryocc 0>; 54 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 55 operating-points-v2 = <&cluster0_opp>; 56 #cooling-cells = <2>; 57 next-level-cache = <&L2_0>; 58 L2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 }; 63 }; 64 65 CPU1: cpu@1 { 66 device_type = "cpu"; 67 compatible = "qcom,kryo"; 68 reg = <0x0 0x1>; 69 enable-method = "psci"; 70 cpu-idle-states = <&CPU_SLEEP_0>; 71 capacity-dmips-mhz = <1024>; 72 clocks = <&kryocc 0>; 73 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 74 operating-points-v2 = <&cluster0_opp>; 75 #cooling-cells = <2>; 76 next-level-cache = <&L2_0>; 77 }; 78 79 CPU2: cpu@100 { 80 device_type = "cpu"; 81 compatible = "qcom,kryo"; 82 reg = <0x0 0x100>; 83 enable-method = "psci"; 84 cpu-idle-states = <&CPU_SLEEP_0>; 85 capacity-dmips-mhz = <1024>; 86 clocks = <&kryocc 1>; 87 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 88 operating-points-v2 = <&cluster1_opp>; 89 #cooling-cells = <2>; 90 next-level-cache = <&L2_1>; 91 L2_1: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 cache-unified; 95 }; 96 }; 97 98 CPU3: cpu@101 { 99 device_type = "cpu"; 100 compatible = "qcom,kryo"; 101 reg = <0x0 0x101>; 102 enable-method = "psci"; 103 cpu-idle-states = <&CPU_SLEEP_0>; 104 capacity-dmips-mhz = <1024>; 105 clocks = <&kryocc 1>; 106 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 107 operating-points-v2 = <&cluster1_opp>; 108 #cooling-cells = <2>; 109 next-level-cache = <&L2_1>; 110 }; 111 112 cpu-map { 113 cluster0 { 114 core0 { 115 cpu = <&CPU0>; 116 }; 117 118 core1 { 119 cpu = <&CPU1>; 120 }; 121 }; 122 123 cluster1 { 124 core0 { 125 cpu = <&CPU2>; 126 }; 127 128 core1 { 129 cpu = <&CPU3>; 130 }; 131 }; 132 }; 133 134 idle-states { 135 entry-method = "psci"; 136 137 CPU_SLEEP_0: cpu-sleep-0 { 138 compatible = "arm,idle-state"; 139 idle-state-name = "standalone-power-collapse"; 140 arm,psci-suspend-param = <0x00000004>; 141 entry-latency-us = <130>; 142 exit-latency-us = <80>; 143 min-residency-us = <300>; 144 }; 145 }; 146 }; 147 148 cluster0_opp: opp-table-cluster0 { 149 compatible = "operating-points-v2-kryo-cpu"; 150 nvmem-cells = <&speedbin_efuse>; 151 opp-shared; 152 153 /* Nominal fmax for now */ 154 opp-307200000 { 155 opp-hz = /bits/ 64 <307200000>; 156 opp-supported-hw = <0xf>; 157 clock-latency-ns = <200000>; 158 opp-peak-kBps = <307200>; 159 }; 160 opp-422400000 { 161 opp-hz = /bits/ 64 <422400000>; 162 opp-supported-hw = <0xf>; 163 clock-latency-ns = <200000>; 164 opp-peak-kBps = <307200>; 165 }; 166 opp-480000000 { 167 opp-hz = /bits/ 64 <480000000>; 168 opp-supported-hw = <0xf>; 169 clock-latency-ns = <200000>; 170 opp-peak-kBps = <307200>; 171 }; 172 opp-556800000 { 173 opp-hz = /bits/ 64 <556800000>; 174 opp-supported-hw = <0xf>; 175 clock-latency-ns = <200000>; 176 opp-peak-kBps = <307200>; 177 }; 178 opp-652800000 { 179 opp-hz = /bits/ 64 <652800000>; 180 opp-supported-hw = <0xf>; 181 clock-latency-ns = <200000>; 182 opp-peak-kBps = <384000>; 183 }; 184 opp-729600000 { 185 opp-hz = /bits/ 64 <729600000>; 186 opp-supported-hw = <0xf>; 187 clock-latency-ns = <200000>; 188 opp-peak-kBps = <460800>; 189 }; 190 opp-844800000 { 191 opp-hz = /bits/ 64 <844800000>; 192 opp-supported-hw = <0xf>; 193 clock-latency-ns = <200000>; 194 opp-peak-kBps = <537600>; 195 }; 196 opp-960000000 { 197 opp-hz = /bits/ 64 <960000000>; 198 opp-supported-hw = <0xf>; 199 clock-latency-ns = <200000>; 200 opp-peak-kBps = <672000>; 201 }; 202 opp-1036800000 { 203 opp-hz = /bits/ 64 <1036800000>; 204 opp-supported-hw = <0xf>; 205 clock-latency-ns = <200000>; 206 opp-peak-kBps = <672000>; 207 }; 208 opp-1113600000 { 209 opp-hz = /bits/ 64 <1113600000>; 210 opp-supported-hw = <0xf>; 211 clock-latency-ns = <200000>; 212 opp-peak-kBps = <825600>; 213 }; 214 opp-1190400000 { 215 opp-hz = /bits/ 64 <1190400000>; 216 opp-supported-hw = <0xf>; 217 clock-latency-ns = <200000>; 218 opp-peak-kBps = <825600>; 219 }; 220 opp-1228800000 { 221 opp-hz = /bits/ 64 <1228800000>; 222 opp-supported-hw = <0xf>; 223 clock-latency-ns = <200000>; 224 opp-peak-kBps = <902400>; 225 }; 226 opp-1324800000 { 227 opp-hz = /bits/ 64 <1324800000>; 228 opp-supported-hw = <0xd>; 229 clock-latency-ns = <200000>; 230 opp-peak-kBps = <1056000>; 231 }; 232 opp-1363200000 { 233 opp-hz = /bits/ 64 <1363200000>; 234 opp-supported-hw = <0x2>; 235 clock-latency-ns = <200000>; 236 opp-peak-kBps = <1132800>; 237 }; 238 opp-1401600000 { 239 opp-hz = /bits/ 64 <1401600000>; 240 opp-supported-hw = <0xd>; 241 clock-latency-ns = <200000>; 242 opp-peak-kBps = <1132800>; 243 }; 244 opp-1478400000 { 245 opp-hz = /bits/ 64 <1478400000>; 246 opp-supported-hw = <0x9>; 247 clock-latency-ns = <200000>; 248 opp-peak-kBps = <1190400>; 249 }; 250 opp-1497600000 { 251 opp-hz = /bits/ 64 <1497600000>; 252 opp-supported-hw = <0x04>; 253 clock-latency-ns = <200000>; 254 opp-peak-kBps = <1305600>; 255 }; 256 opp-1593600000 { 257 opp-hz = /bits/ 64 <1593600000>; 258 opp-supported-hw = <0x9>; 259 clock-latency-ns = <200000>; 260 opp-peak-kBps = <1382400>; 261 }; 262 }; 263 264 cluster1_opp: opp-table-cluster1 { 265 compatible = "operating-points-v2-kryo-cpu"; 266 nvmem-cells = <&speedbin_efuse>; 267 opp-shared; 268 269 /* Nominal fmax for now */ 270 opp-307200000 { 271 opp-hz = /bits/ 64 <307200000>; 272 opp-supported-hw = <0xf>; 273 clock-latency-ns = <200000>; 274 opp-peak-kBps = <307200>; 275 }; 276 opp-403200000 { 277 opp-hz = /bits/ 64 <403200000>; 278 opp-supported-hw = <0xf>; 279 clock-latency-ns = <200000>; 280 opp-peak-kBps = <307200>; 281 }; 282 opp-480000000 { 283 opp-hz = /bits/ 64 <480000000>; 284 opp-supported-hw = <0xf>; 285 clock-latency-ns = <200000>; 286 opp-peak-kBps = <307200>; 287 }; 288 opp-556800000 { 289 opp-hz = /bits/ 64 <556800000>; 290 opp-supported-hw = <0xf>; 291 clock-latency-ns = <200000>; 292 opp-peak-kBps = <307200>; 293 }; 294 opp-652800000 { 295 opp-hz = /bits/ 64 <652800000>; 296 opp-supported-hw = <0xf>; 297 clock-latency-ns = <200000>; 298 opp-peak-kBps = <307200>; 299 }; 300 opp-729600000 { 301 opp-hz = /bits/ 64 <729600000>; 302 opp-supported-hw = <0xf>; 303 clock-latency-ns = <200000>; 304 opp-peak-kBps = <307200>; 305 }; 306 opp-806400000 { 307 opp-hz = /bits/ 64 <806400000>; 308 opp-supported-hw = <0xf>; 309 clock-latency-ns = <200000>; 310 opp-peak-kBps = <384000>; 311 }; 312 opp-883200000 { 313 opp-hz = /bits/ 64 <883200000>; 314 opp-supported-hw = <0xf>; 315 clock-latency-ns = <200000>; 316 opp-peak-kBps = <460800>; 317 }; 318 opp-940800000 { 319 opp-hz = /bits/ 64 <940800000>; 320 opp-supported-hw = <0xf>; 321 clock-latency-ns = <200000>; 322 opp-peak-kBps = <537600>; 323 }; 324 opp-1036800000 { 325 opp-hz = /bits/ 64 <1036800000>; 326 opp-supported-hw = <0xf>; 327 clock-latency-ns = <200000>; 328 opp-peak-kBps = <595200>; 329 }; 330 opp-1113600000 { 331 opp-hz = /bits/ 64 <1113600000>; 332 opp-supported-hw = <0xf>; 333 clock-latency-ns = <200000>; 334 opp-peak-kBps = <672000>; 335 }; 336 opp-1190400000 { 337 opp-hz = /bits/ 64 <1190400000>; 338 opp-supported-hw = <0xf>; 339 clock-latency-ns = <200000>; 340 opp-peak-kBps = <672000>; 341 }; 342 opp-1248000000 { 343 opp-hz = /bits/ 64 <1248000000>; 344 opp-supported-hw = <0xf>; 345 clock-latency-ns = <200000>; 346 opp-peak-kBps = <748800>; 347 }; 348 opp-1324800000 { 349 opp-hz = /bits/ 64 <1324800000>; 350 opp-supported-hw = <0xf>; 351 clock-latency-ns = <200000>; 352 opp-peak-kBps = <825600>; 353 }; 354 opp-1401600000 { 355 opp-hz = /bits/ 64 <1401600000>; 356 opp-supported-hw = <0xf>; 357 clock-latency-ns = <200000>; 358 opp-peak-kBps = <902400>; 359 }; 360 opp-1478400000 { 361 opp-hz = /bits/ 64 <1478400000>; 362 opp-supported-hw = <0xf>; 363 clock-latency-ns = <200000>; 364 opp-peak-kBps = <979200>; 365 }; 366 opp-1555200000 { 367 opp-hz = /bits/ 64 <1555200000>; 368 opp-supported-hw = <0xf>; 369 clock-latency-ns = <200000>; 370 opp-peak-kBps = <1056000>; 371 }; 372 opp-1632000000 { 373 opp-hz = /bits/ 64 <1632000000>; 374 opp-supported-hw = <0xf>; 375 clock-latency-ns = <200000>; 376 opp-peak-kBps = <1190400>; 377 }; 378 opp-1708800000 { 379 opp-hz = /bits/ 64 <1708800000>; 380 opp-supported-hw = <0xf>; 381 clock-latency-ns = <200000>; 382 opp-peak-kBps = <1228800>; 383 }; 384 opp-1785600000 { 385 opp-hz = /bits/ 64 <1785600000>; 386 opp-supported-hw = <0xf>; 387 clock-latency-ns = <200000>; 388 opp-peak-kBps = <1305600>; 389 }; 390 opp-1804800000 { 391 opp-hz = /bits/ 64 <1804800000>; 392 opp-supported-hw = <0xe>; 393 clock-latency-ns = <200000>; 394 opp-peak-kBps = <1305600>; 395 }; 396 opp-1824000000 { 397 opp-hz = /bits/ 64 <1824000000>; 398 opp-supported-hw = <0x1>; 399 clock-latency-ns = <200000>; 400 opp-peak-kBps = <1382400>; 401 }; 402 opp-1900800000 { 403 opp-hz = /bits/ 64 <1900800000>; 404 opp-supported-hw = <0x4>; 405 clock-latency-ns = <200000>; 406 opp-peak-kBps = <1305600>; 407 }; 408 opp-1920000000 { 409 opp-hz = /bits/ 64 <1920000000>; 410 opp-supported-hw = <0x1>; 411 clock-latency-ns = <200000>; 412 opp-peak-kBps = <1459200>; 413 }; 414 opp-1996800000 { 415 opp-hz = /bits/ 64 <1996800000>; 416 opp-supported-hw = <0x1>; 417 clock-latency-ns = <200000>; 418 opp-peak-kBps = <1593600>; 419 }; 420 opp-2073600000 { 421 opp-hz = /bits/ 64 <2073600000>; 422 opp-supported-hw = <0x1>; 423 clock-latency-ns = <200000>; 424 opp-peak-kBps = <1593600>; 425 }; 426 opp-2150400000 { 427 opp-hz = /bits/ 64 <2150400000>; 428 opp-supported-hw = <0x1>; 429 clock-latency-ns = <200000>; 430 opp-peak-kBps = <1593600>; 431 }; 432 }; 433 434 firmware { 435 scm { 436 compatible = "qcom,scm-msm8996", "qcom,scm"; 437 qcom,dload-mode = <&tcsr_2 0x13000>; 438 }; 439 }; 440 441 memory@80000000 { 442 device_type = "memory"; 443 /* We expect the bootloader to fill in the reg */ 444 reg = <0x0 0x80000000 0x0 0x0>; 445 }; 446 447 psci { 448 compatible = "arm,psci-1.0"; 449 method = "smc"; 450 }; 451 452 rpm: remoteproc { 453 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc"; 454 455 glink-edge { 456 compatible = "qcom,glink-rpm"; 457 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 458 qcom,rpm-msg-ram = <&rpm_msg_ram>; 459 mboxes = <&apcs_glb 0>; 460 461 rpm_requests: rpm-requests { 462 compatible = "qcom,rpm-msm8996"; 463 qcom,glink-channels = "rpm_requests"; 464 465 rpmcc: clock-controller { 466 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 467 #clock-cells = <1>; 468 clocks = <&xo_board>; 469 clock-names = "xo"; 470 }; 471 472 rpmpd: power-controller { 473 compatible = "qcom,msm8996-rpmpd"; 474 #power-domain-cells = <1>; 475 operating-points-v2 = <&rpmpd_opp_table>; 476 477 rpmpd_opp_table: opp-table { 478 compatible = "operating-points-v2"; 479 480 rpmpd_opp1: opp1 { 481 opp-level = <1>; 482 }; 483 484 rpmpd_opp2: opp2 { 485 opp-level = <2>; 486 }; 487 488 rpmpd_opp3: opp3 { 489 opp-level = <3>; 490 }; 491 492 rpmpd_opp4: opp4 { 493 opp-level = <4>; 494 }; 495 496 rpmpd_opp5: opp5 { 497 opp-level = <5>; 498 }; 499 500 rpmpd_opp6: opp6 { 501 opp-level = <6>; 502 }; 503 }; 504 }; 505 }; 506 }; 507 }; 508 509 reserved-memory { 510 #address-cells = <2>; 511 #size-cells = <2>; 512 ranges; 513 514 hyp_mem: memory@85800000 { 515 reg = <0x0 0x85800000 0x0 0x600000>; 516 no-map; 517 }; 518 519 xbl_mem: memory@85e00000 { 520 reg = <0x0 0x85e00000 0x0 0x200000>; 521 no-map; 522 }; 523 524 smem_mem: smem-mem@86000000 { 525 reg = <0x0 0x86000000 0x0 0x200000>; 526 no-map; 527 }; 528 529 tz_mem: memory@86200000 { 530 reg = <0x0 0x86200000 0x0 0x2600000>; 531 no-map; 532 }; 533 534 rmtfs_mem: rmtfs { 535 compatible = "qcom,rmtfs-mem"; 536 537 size = <0x0 0x200000>; 538 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 539 no-map; 540 541 qcom,client-id = <1>; 542 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 543 }; 544 545 mpss_mem: mpss@88800000 { 546 reg = <0x0 0x88800000 0x0 0x6200000>; 547 no-map; 548 }; 549 550 adsp_mem: adsp@8ea00000 { 551 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 552 no-map; 553 }; 554 555 slpi_mem: slpi@90500000 { 556 reg = <0x0 0x90500000 0x0 0xa00000>; 557 no-map; 558 }; 559 560 gpu_mem: gpu@90f00000 { 561 compatible = "shared-dma-pool"; 562 reg = <0x0 0x90f00000 0x0 0x100000>; 563 no-map; 564 }; 565 566 venus_mem: venus@91000000 { 567 reg = <0x0 0x91000000 0x0 0x500000>; 568 no-map; 569 }; 570 571 mba_mem: mba@91500000 { 572 reg = <0x0 0x91500000 0x0 0x200000>; 573 no-map; 574 }; 575 576 mdata_mem: mpss-metadata { 577 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 578 size = <0x0 0x4000>; 579 no-map; 580 }; 581 }; 582 583 smem { 584 compatible = "qcom,smem"; 585 memory-region = <&smem_mem>; 586 hwlocks = <&tcsr_mutex 3>; 587 }; 588 589 smp2p-adsp { 590 compatible = "qcom,smp2p"; 591 qcom,smem = <443>, <429>; 592 593 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 594 595 mboxes = <&apcs_glb 10>; 596 597 qcom,local-pid = <0>; 598 qcom,remote-pid = <2>; 599 600 adsp_smp2p_out: master-kernel { 601 qcom,entry-name = "master-kernel"; 602 #qcom,smem-state-cells = <1>; 603 }; 604 605 adsp_smp2p_in: slave-kernel { 606 qcom,entry-name = "slave-kernel"; 607 608 interrupt-controller; 609 #interrupt-cells = <2>; 610 }; 611 }; 612 613 smp2p-mpss { 614 compatible = "qcom,smp2p"; 615 qcom,smem = <435>, <428>; 616 617 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 618 619 mboxes = <&apcs_glb 14>; 620 621 qcom,local-pid = <0>; 622 qcom,remote-pid = <1>; 623 624 mpss_smp2p_out: master-kernel { 625 qcom,entry-name = "master-kernel"; 626 #qcom,smem-state-cells = <1>; 627 }; 628 629 mpss_smp2p_in: slave-kernel { 630 qcom,entry-name = "slave-kernel"; 631 632 interrupt-controller; 633 #interrupt-cells = <2>; 634 }; 635 }; 636 637 smp2p-slpi { 638 compatible = "qcom,smp2p"; 639 qcom,smem = <481>, <430>; 640 641 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 642 643 mboxes = <&apcs_glb 26>; 644 645 qcom,local-pid = <0>; 646 qcom,remote-pid = <3>; 647 648 slpi_smp2p_out: master-kernel { 649 qcom,entry-name = "master-kernel"; 650 #qcom,smem-state-cells = <1>; 651 }; 652 653 slpi_smp2p_in: slave-kernel { 654 qcom,entry-name = "slave-kernel"; 655 656 interrupt-controller; 657 #interrupt-cells = <2>; 658 }; 659 }; 660 661 soc: soc@0 { 662 #address-cells = <1>; 663 #size-cells = <1>; 664 ranges = <0 0 0 0xffffffff>; 665 compatible = "simple-bus"; 666 667 pcie_phy: phy-wrapper@34000 { 668 compatible = "qcom,msm8996-qmp-pcie-phy"; 669 reg = <0x00034000 0x488>; 670 #address-cells = <1>; 671 #size-cells = <1>; 672 ranges = <0x0 0x00034000 0x4000>; 673 674 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 675 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 676 <&gcc GCC_PCIE_CLKREF_CLK>; 677 clock-names = "aux", "cfg_ahb", "ref"; 678 679 resets = <&gcc GCC_PCIE_PHY_BCR>, 680 <&gcc GCC_PCIE_PHY_COM_BCR>, 681 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 682 reset-names = "phy", "common", "cfg"; 683 684 status = "disabled"; 685 686 pciephy_0: phy@1000 { 687 reg = <0x1000 0x130>, 688 <0x1200 0x200>, 689 <0x1400 0x1dc>; 690 691 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 692 clock-names = "pipe0"; 693 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 694 reset-names = "lane0"; 695 696 #clock-cells = <0>; 697 clock-output-names = "pcie_0_pipe_clk_src"; 698 699 #phy-cells = <0>; 700 }; 701 702 pciephy_1: phy@2000 { 703 reg = <0x2000 0x130>, 704 <0x2200 0x200>, 705 <0x2400 0x1dc>; 706 707 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 708 clock-names = "pipe1"; 709 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 710 reset-names = "lane1"; 711 712 #clock-cells = <0>; 713 clock-output-names = "pcie_1_pipe_clk_src"; 714 715 #phy-cells = <0>; 716 }; 717 718 pciephy_2: phy@3000 { 719 reg = <0x3000 0x130>, 720 <0x3200 0x200>, 721 <0x3400 0x1dc>; 722 723 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 724 clock-names = "pipe2"; 725 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 726 reset-names = "lane2"; 727 728 #clock-cells = <0>; 729 clock-output-names = "pcie_2_pipe_clk_src"; 730 731 #phy-cells = <0>; 732 }; 733 }; 734 735 rpm_msg_ram: sram@68000 { 736 compatible = "qcom,rpm-msg-ram"; 737 reg = <0x00068000 0x6000>; 738 }; 739 740 qfprom@74000 { 741 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 742 reg = <0x00074000 0x8ff>; 743 #address-cells = <1>; 744 #size-cells = <1>; 745 746 qusb2p_hstx_trim: hstx_trim@24e { 747 reg = <0x24e 0x2>; 748 bits = <5 4>; 749 }; 750 751 qusb2s_hstx_trim: hstx_trim@24f { 752 reg = <0x24f 0x1>; 753 bits = <1 4>; 754 }; 755 756 speedbin_efuse: speedbin@133 { 757 reg = <0x133 0x1>; 758 bits = <5 3>; 759 }; 760 }; 761 762 rng: rng@83000 { 763 compatible = "qcom,prng-ee"; 764 reg = <0x00083000 0x1000>; 765 clocks = <&gcc GCC_PRNG_AHB_CLK>; 766 clock-names = "core"; 767 }; 768 769 gcc: clock-controller@300000 { 770 compatible = "qcom,gcc-msm8996"; 771 #clock-cells = <1>; 772 #reset-cells = <1>; 773 #power-domain-cells = <1>; 774 reg = <0x00300000 0x90000>; 775 776 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 777 <&rpmcc RPM_SMD_LN_BB_CLK>, 778 <&sleep_clk>, 779 <&pciephy_0>, 780 <&pciephy_1>, 781 <&pciephy_2>, 782 <&ssusb_phy_0>, 783 <&ufsphy_lane 0>, 784 <&ufsphy_lane 1>, 785 <&ufsphy_lane 2>; 786 clock-names = "cxo", 787 "cxo2", 788 "sleep_clk", 789 "pcie_0_pipe_clk_src", 790 "pcie_1_pipe_clk_src", 791 "pcie_2_pipe_clk_src", 792 "usb3_phy_pipe_clk_src", 793 "ufs_rx_symbol_0_clk_src", 794 "ufs_rx_symbol_1_clk_src", 795 "ufs_tx_symbol_0_clk_src"; 796 }; 797 798 bimc: interconnect@408000 { 799 compatible = "qcom,msm8996-bimc"; 800 reg = <0x00408000 0x5a000>; 801 #interconnect-cells = <1>; 802 clock-names = "bus", "bus_a"; 803 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 804 <&rpmcc RPM_SMD_BIMC_A_CLK>; 805 }; 806 807 tsens0: thermal-sensor@4a9000 { 808 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 809 reg = <0x004a9000 0x1000>, /* TM */ 810 <0x004a8000 0x1000>; /* SROT */ 811 #qcom,sensors = <13>; 812 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 814 interrupt-names = "uplow", "critical"; 815 #thermal-sensor-cells = <1>; 816 }; 817 818 tsens1: thermal-sensor@4ad000 { 819 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 820 reg = <0x004ad000 0x1000>, /* TM */ 821 <0x004ac000 0x1000>; /* SROT */ 822 #qcom,sensors = <8>; 823 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 825 interrupt-names = "uplow", "critical"; 826 #thermal-sensor-cells = <1>; 827 }; 828 829 cryptobam: dma-controller@644000 { 830 compatible = "qcom,bam-v1.7.0"; 831 reg = <0x00644000 0x24000>; 832 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&gcc GCC_CE1_CLK>; 834 clock-names = "bam_clk"; 835 #dma-cells = <1>; 836 qcom,ee = <0>; 837 qcom,controlled-remotely; 838 }; 839 840 crypto: crypto@67a000 { 841 compatible = "qcom,crypto-v5.4"; 842 reg = <0x0067a000 0x6000>; 843 clocks = <&gcc GCC_CE1_AHB_CLK>, 844 <&gcc GCC_CE1_AXI_CLK>, 845 <&gcc GCC_CE1_CLK>; 846 clock-names = "iface", "bus", "core"; 847 dmas = <&cryptobam 6>, <&cryptobam 7>; 848 dma-names = "rx", "tx"; 849 }; 850 851 cnoc: interconnect@500000 { 852 compatible = "qcom,msm8996-cnoc"; 853 reg = <0x00500000 0x1000>; 854 #interconnect-cells = <1>; 855 clock-names = "bus", "bus_a"; 856 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 857 <&rpmcc RPM_SMD_CNOC_A_CLK>; 858 }; 859 860 snoc: interconnect@524000 { 861 compatible = "qcom,msm8996-snoc"; 862 reg = <0x00524000 0x1c000>; 863 #interconnect-cells = <1>; 864 clock-names = "bus", "bus_a"; 865 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 866 <&rpmcc RPM_SMD_SNOC_A_CLK>; 867 }; 868 869 a0noc: interconnect@543000 { 870 compatible = "qcom,msm8996-a0noc"; 871 reg = <0x00543000 0x6000>; 872 #interconnect-cells = <1>; 873 clock-names = "aggre0_snoc_axi", 874 "aggre0_cnoc_ahb", 875 "aggre0_noc_mpu_cfg"; 876 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 877 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 878 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 879 power-domains = <&gcc AGGRE0_NOC_GDSC>; 880 }; 881 882 a1noc: interconnect@562000 { 883 compatible = "qcom,msm8996-a1noc"; 884 reg = <0x00562000 0x5000>; 885 #interconnect-cells = <1>; 886 clock-names = "bus", "bus_a"; 887 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, 888 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; 889 }; 890 891 a2noc: interconnect@583000 { 892 compatible = "qcom,msm8996-a2noc"; 893 reg = <0x00583000 0x7000>; 894 #interconnect-cells = <1>; 895 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi"; 896 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 897 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 898 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 899 <&gcc GCC_UFS_AXI_CLK>; 900 }; 901 902 mnoc: interconnect@5a4000 { 903 compatible = "qcom,msm8996-mnoc"; 904 reg = <0x005a4000 0x1c000>; 905 #interconnect-cells = <1>; 906 clock-names = "bus", "bus_a", "iface"; 907 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, 908 <&rpmcc RPM_SMD_MMAXI_A_CLK>, 909 <&mmcc AHB_CLK_SRC>; 910 }; 911 912 pnoc: interconnect@5c0000 { 913 compatible = "qcom,msm8996-pnoc"; 914 reg = <0x005c0000 0x3000>; 915 #interconnect-cells = <1>; 916 clock-names = "bus", "bus_a"; 917 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 918 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 919 }; 920 921 tcsr_mutex: hwlock@740000 { 922 compatible = "qcom,tcsr-mutex"; 923 reg = <0x00740000 0x20000>; 924 #hwlock-cells = <1>; 925 }; 926 927 tcsr_1: syscon@760000 { 928 compatible = "qcom,tcsr-msm8996", "syscon"; 929 reg = <0x00760000 0x20000>; 930 }; 931 932 tcsr_2: syscon@7a0000 { 933 compatible = "qcom,tcsr-msm8996", "syscon"; 934 reg = <0x007a0000 0x18000>; 935 }; 936 937 mmcc: clock-controller@8c0000 { 938 compatible = "qcom,mmcc-msm8996"; 939 #clock-cells = <1>; 940 #reset-cells = <1>; 941 #power-domain-cells = <1>; 942 reg = <0x008c0000 0x40000>; 943 clocks = <&xo_board>, 944 <&gcc GPLL0>, 945 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 946 <&mdss_dsi0_phy 1>, 947 <&mdss_dsi0_phy 0>, 948 <&mdss_dsi1_phy 1>, 949 <&mdss_dsi1_phy 0>, 950 <&mdss_hdmi_phy>; 951 clock-names = "xo", 952 "gpll0", 953 "gcc_mmss_noc_cfg_ahb_clk", 954 "dsi0pll", 955 "dsi0pllbyte", 956 "dsi1pll", 957 "dsi1pllbyte", 958 "hdmipll"; 959 assigned-clocks = <&mmcc MMPLL9_PLL>, 960 <&mmcc MMPLL1_PLL>, 961 <&mmcc MMPLL3_PLL>, 962 <&mmcc MMPLL4_PLL>, 963 <&mmcc MMPLL5_PLL>; 964 assigned-clock-rates = <624000000>, 965 <810000000>, 966 <980000000>, 967 <960000000>, 968 <825000000>; 969 }; 970 971 mdss: display-subsystem@900000 { 972 compatible = "qcom,mdss"; 973 974 reg = <0x00900000 0x1000>, 975 <0x009b0000 0x1040>, 976 <0x009b8000 0x1040>; 977 reg-names = "mdss_phys", 978 "vbif_phys", 979 "vbif_nrt_phys"; 980 981 power-domains = <&mmcc MDSS_GDSC>; 982 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 983 984 interrupt-controller; 985 #interrupt-cells = <1>; 986 987 clocks = <&mmcc MDSS_AHB_CLK>, 988 <&mmcc MDSS_MDP_CLK>; 989 clock-names = "iface", "core"; 990 991 #address-cells = <1>; 992 #size-cells = <1>; 993 ranges; 994 995 status = "disabled"; 996 997 mdp: display-controller@901000 { 998 compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; 999 reg = <0x00901000 0x90000>; 1000 reg-names = "mdp_phys"; 1001 1002 interrupt-parent = <&mdss>; 1003 interrupts = <0>; 1004 1005 clocks = <&mmcc MDSS_AHB_CLK>, 1006 <&mmcc MDSS_AXI_CLK>, 1007 <&mmcc MDSS_MDP_CLK>, 1008 <&mmcc SMMU_MDP_AXI_CLK>, 1009 <&mmcc MDSS_VSYNC_CLK>; 1010 clock-names = "iface", 1011 "bus", 1012 "core", 1013 "iommu", 1014 "vsync"; 1015 1016 iommus = <&mdp_smmu 0>; 1017 1018 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1019 <&mmcc MDSS_VSYNC_CLK>; 1020 assigned-clock-rates = <300000000>, 1021 <19200000>; 1022 1023 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 1024 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 1025 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 1026 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 1027 1028 ports { 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 1032 port@0 { 1033 reg = <0>; 1034 mdp5_intf3_out: endpoint { 1035 remote-endpoint = <&mdss_hdmi_in>; 1036 }; 1037 }; 1038 1039 port@1 { 1040 reg = <1>; 1041 mdp5_intf1_out: endpoint { 1042 remote-endpoint = <&mdss_dsi0_in>; 1043 }; 1044 }; 1045 1046 port@2 { 1047 reg = <2>; 1048 mdp5_intf2_out: endpoint { 1049 remote-endpoint = <&mdss_dsi1_in>; 1050 }; 1051 }; 1052 }; 1053 }; 1054 1055 mdss_dsi0: dsi@994000 { 1056 compatible = "qcom,msm8996-dsi-ctrl", 1057 "qcom,mdss-dsi-ctrl"; 1058 reg = <0x00994000 0x400>; 1059 reg-names = "dsi_ctrl"; 1060 1061 interrupt-parent = <&mdss>; 1062 interrupts = <4>; 1063 1064 clocks = <&mmcc MDSS_MDP_CLK>, 1065 <&mmcc MDSS_BYTE0_CLK>, 1066 <&mmcc MDSS_AHB_CLK>, 1067 <&mmcc MDSS_AXI_CLK>, 1068 <&mmcc MMSS_MISC_AHB_CLK>, 1069 <&mmcc MDSS_PCLK0_CLK>, 1070 <&mmcc MDSS_ESC0_CLK>; 1071 clock-names = "mdp_core", 1072 "byte", 1073 "iface", 1074 "bus", 1075 "core_mmss", 1076 "pixel", 1077 "core"; 1078 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1079 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1080 1081 phys = <&mdss_dsi0_phy>; 1082 status = "disabled"; 1083 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 1087 ports { 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 1091 port@0 { 1092 reg = <0>; 1093 mdss_dsi0_in: endpoint { 1094 remote-endpoint = <&mdp5_intf1_out>; 1095 }; 1096 }; 1097 1098 port@1 { 1099 reg = <1>; 1100 mdss_dsi0_out: endpoint { 1101 }; 1102 }; 1103 }; 1104 }; 1105 1106 mdss_dsi0_phy: phy@994400 { 1107 compatible = "qcom,dsi-phy-14nm"; 1108 reg = <0x00994400 0x100>, 1109 <0x00994500 0x300>, 1110 <0x00994800 0x188>; 1111 reg-names = "dsi_phy", 1112 "dsi_phy_lane", 1113 "dsi_pll"; 1114 1115 #clock-cells = <1>; 1116 #phy-cells = <0>; 1117 1118 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1119 clock-names = "iface", "ref"; 1120 status = "disabled"; 1121 }; 1122 1123 mdss_dsi1: dsi@996000 { 1124 compatible = "qcom,msm8996-dsi-ctrl", 1125 "qcom,mdss-dsi-ctrl"; 1126 reg = <0x00996000 0x400>; 1127 reg-names = "dsi_ctrl"; 1128 1129 interrupt-parent = <&mdss>; 1130 interrupts = <5>; 1131 1132 clocks = <&mmcc MDSS_MDP_CLK>, 1133 <&mmcc MDSS_BYTE1_CLK>, 1134 <&mmcc MDSS_AHB_CLK>, 1135 <&mmcc MDSS_AXI_CLK>, 1136 <&mmcc MMSS_MISC_AHB_CLK>, 1137 <&mmcc MDSS_PCLK1_CLK>, 1138 <&mmcc MDSS_ESC1_CLK>; 1139 clock-names = "mdp_core", 1140 "byte", 1141 "iface", 1142 "bus", 1143 "core_mmss", 1144 "pixel", 1145 "core"; 1146 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 1147 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 1148 1149 phys = <&mdss_dsi1_phy>; 1150 status = "disabled"; 1151 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 1155 ports { 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 1159 port@0 { 1160 reg = <0>; 1161 mdss_dsi1_in: endpoint { 1162 remote-endpoint = <&mdp5_intf2_out>; 1163 }; 1164 }; 1165 1166 port@1 { 1167 reg = <1>; 1168 mdss_dsi1_out: endpoint { 1169 }; 1170 }; 1171 }; 1172 }; 1173 1174 mdss_dsi1_phy: phy@996400 { 1175 compatible = "qcom,dsi-phy-14nm"; 1176 reg = <0x00996400 0x100>, 1177 <0x00996500 0x300>, 1178 <0x00996800 0x188>; 1179 reg-names = "dsi_phy", 1180 "dsi_phy_lane", 1181 "dsi_pll"; 1182 1183 #clock-cells = <1>; 1184 #phy-cells = <0>; 1185 1186 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1187 clock-names = "iface", "ref"; 1188 status = "disabled"; 1189 }; 1190 1191 mdss_hdmi: hdmi-tx@9a0000 { 1192 compatible = "qcom,hdmi-tx-8996"; 1193 reg = <0x009a0000 0x50c>, 1194 <0x00070000 0x6158>, 1195 <0x009e0000 0xfff>; 1196 reg-names = "core_physical", 1197 "qfprom_physical", 1198 "hdcp_physical"; 1199 1200 interrupt-parent = <&mdss>; 1201 interrupts = <8>; 1202 1203 clocks = <&mmcc MDSS_MDP_CLK>, 1204 <&mmcc MDSS_AHB_CLK>, 1205 <&mmcc MDSS_HDMI_CLK>, 1206 <&mmcc MDSS_HDMI_AHB_CLK>, 1207 <&mmcc MDSS_EXTPCLK_CLK>; 1208 clock-names = 1209 "mdp_core", 1210 "iface", 1211 "core", 1212 "alt_iface", 1213 "extp"; 1214 1215 phys = <&mdss_hdmi_phy>; 1216 #sound-dai-cells = <1>; 1217 1218 status = "disabled"; 1219 1220 ports { 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 1224 port@0 { 1225 reg = <0>; 1226 mdss_hdmi_in: endpoint { 1227 remote-endpoint = <&mdp5_intf3_out>; 1228 }; 1229 }; 1230 }; 1231 }; 1232 1233 mdss_hdmi_phy: phy@9a0600 { 1234 #phy-cells = <0>; 1235 compatible = "qcom,hdmi-phy-8996"; 1236 reg = <0x009a0600 0x1c4>, 1237 <0x009a0a00 0x124>, 1238 <0x009a0c00 0x124>, 1239 <0x009a0e00 0x124>, 1240 <0x009a1000 0x124>, 1241 <0x009a1200 0x0c8>; 1242 reg-names = "hdmi_pll", 1243 "hdmi_tx_l0", 1244 "hdmi_tx_l1", 1245 "hdmi_tx_l2", 1246 "hdmi_tx_l3", 1247 "hdmi_phy"; 1248 1249 clocks = <&mmcc MDSS_AHB_CLK>, 1250 <&gcc GCC_HDMI_CLKREF_CLK>, 1251 <&xo_board>; 1252 clock-names = "iface", 1253 "ref", 1254 "xo"; 1255 1256 #clock-cells = <0>; 1257 1258 status = "disabled"; 1259 }; 1260 }; 1261 1262 gpu: gpu@b00000 { 1263 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1264 1265 reg = <0x00b00000 0x3f000>; 1266 reg-names = "kgsl_3d0_reg_memory"; 1267 1268 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1269 1270 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1271 <&mmcc GPU_AHB_CLK>, 1272 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1273 <&gcc GCC_BIMC_GFX_CLK>, 1274 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1275 1276 clock-names = "core", 1277 "iface", 1278 "rbbmtimer", 1279 "mem", 1280 "mem_iface"; 1281 1282 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1283 interconnect-names = "gfx-mem"; 1284 1285 power-domains = <&mmcc GPU_GX_GDSC>; 1286 iommus = <&adreno_smmu 0>; 1287 1288 nvmem-cells = <&speedbin_efuse>; 1289 nvmem-cell-names = "speed_bin"; 1290 1291 operating-points-v2 = <&gpu_opp_table>; 1292 1293 status = "disabled"; 1294 1295 #cooling-cells = <2>; 1296 1297 gpu_opp_table: opp-table { 1298 compatible = "operating-points-v2"; 1299 1300 /* 1301 * 624Mhz is only available on speed bins 0 and 3. 1302 * 560Mhz is only available on speed bins 0, 2 and 3. 1303 * All the rest are available on all bins of the hardware. 1304 */ 1305 opp-624000000 { 1306 opp-hz = /bits/ 64 <624000000>; 1307 opp-supported-hw = <0x09>; 1308 }; 1309 opp-560000000 { 1310 opp-hz = /bits/ 64 <560000000>; 1311 opp-supported-hw = <0x0d>; 1312 }; 1313 opp-510000000 { 1314 opp-hz = /bits/ 64 <510000000>; 1315 opp-supported-hw = <0xff>; 1316 }; 1317 opp-401800000 { 1318 opp-hz = /bits/ 64 <401800000>; 1319 opp-supported-hw = <0xff>; 1320 }; 1321 opp-315000000 { 1322 opp-hz = /bits/ 64 <315000000>; 1323 opp-supported-hw = <0xff>; 1324 }; 1325 opp-214000000 { 1326 opp-hz = /bits/ 64 <214000000>; 1327 opp-supported-hw = <0xff>; 1328 }; 1329 opp-133000000 { 1330 opp-hz = /bits/ 64 <133000000>; 1331 opp-supported-hw = <0xff>; 1332 }; 1333 }; 1334 1335 zap-shader { 1336 memory-region = <&gpu_mem>; 1337 }; 1338 }; 1339 1340 tlmm: pinctrl@1010000 { 1341 compatible = "qcom,msm8996-pinctrl"; 1342 reg = <0x01010000 0x300000>; 1343 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1344 gpio-controller; 1345 gpio-ranges = <&tlmm 0 0 150>; 1346 #gpio-cells = <2>; 1347 interrupt-controller; 1348 #interrupt-cells = <2>; 1349 1350 blsp1_spi1_default: blsp1-spi1-default-state { 1351 spi-pins { 1352 pins = "gpio0", "gpio1", "gpio3"; 1353 function = "blsp_spi1"; 1354 drive-strength = <12>; 1355 bias-disable; 1356 }; 1357 1358 cs-pins { 1359 pins = "gpio2"; 1360 function = "gpio"; 1361 drive-strength = <16>; 1362 bias-disable; 1363 output-high; 1364 }; 1365 }; 1366 1367 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 1368 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1369 function = "gpio"; 1370 drive-strength = <2>; 1371 bias-pull-down; 1372 }; 1373 1374 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { 1375 pins = "gpio4", "gpio5"; 1376 function = "blsp_uart8"; 1377 drive-strength = <16>; 1378 bias-disable; 1379 }; 1380 1381 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { 1382 pins = "gpio4", "gpio5"; 1383 function = "gpio"; 1384 drive-strength = <2>; 1385 bias-disable; 1386 }; 1387 1388 blsp2_i2c2_default: blsp2-i2c2-state { 1389 pins = "gpio6", "gpio7"; 1390 function = "blsp_i2c8"; 1391 drive-strength = <16>; 1392 bias-disable; 1393 }; 1394 1395 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1396 pins = "gpio6", "gpio7"; 1397 function = "gpio"; 1398 drive-strength = <2>; 1399 bias-disable; 1400 }; 1401 1402 blsp1_i2c6_default: blsp1-i2c6-state { 1403 pins = "gpio27", "gpio28"; 1404 function = "blsp_i2c6"; 1405 drive-strength = <16>; 1406 bias-disable; 1407 }; 1408 1409 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1410 pins = "gpio27", "gpio28"; 1411 function = "gpio"; 1412 drive-strength = <2>; 1413 bias-pull-up; 1414 }; 1415 1416 cci0_default: cci0-default-state { 1417 pins = "gpio17", "gpio18"; 1418 function = "cci_i2c"; 1419 drive-strength = <16>; 1420 bias-disable; 1421 }; 1422 1423 camera0_state_on: 1424 camera_rear_default: camera-rear-default-state { 1425 camera0_mclk: mclk0-pins { 1426 pins = "gpio13"; 1427 function = "cam_mclk"; 1428 drive-strength = <16>; 1429 bias-disable; 1430 }; 1431 1432 camera0_rst: rst-pins { 1433 pins = "gpio25"; 1434 function = "gpio"; 1435 drive-strength = <16>; 1436 bias-disable; 1437 }; 1438 1439 camera0_pwdn: pwdn-pins { 1440 pins = "gpio26"; 1441 function = "gpio"; 1442 drive-strength = <16>; 1443 bias-disable; 1444 }; 1445 }; 1446 1447 cci1_default: cci1-default-state { 1448 pins = "gpio19", "gpio20"; 1449 function = "cci_i2c"; 1450 drive-strength = <16>; 1451 bias-disable; 1452 }; 1453 1454 camera1_state_on: 1455 camera_board_default: camera-board-default-state { 1456 mclk1-pins { 1457 pins = "gpio14"; 1458 function = "cam_mclk"; 1459 drive-strength = <16>; 1460 bias-disable; 1461 }; 1462 1463 pwdn-pins { 1464 pins = "gpio98"; 1465 function = "gpio"; 1466 drive-strength = <16>; 1467 bias-disable; 1468 }; 1469 1470 rst-pins { 1471 pins = "gpio104"; 1472 function = "gpio"; 1473 drive-strength = <16>; 1474 bias-disable; 1475 }; 1476 }; 1477 1478 camera2_state_on: 1479 camera_front_default: camera-front-default-state { 1480 camera2_mclk: mclk2-pins { 1481 pins = "gpio15"; 1482 function = "cam_mclk"; 1483 drive-strength = <16>; 1484 bias-disable; 1485 }; 1486 1487 camera2_rst: rst-pins { 1488 pins = "gpio23"; 1489 function = "gpio"; 1490 drive-strength = <16>; 1491 bias-disable; 1492 }; 1493 1494 pwdn-pins { 1495 pins = "gpio133"; 1496 function = "gpio"; 1497 drive-strength = <16>; 1498 bias-disable; 1499 }; 1500 }; 1501 1502 pcie0_state_on: pcie0-state-on-state { 1503 perst-pins { 1504 pins = "gpio35"; 1505 function = "gpio"; 1506 drive-strength = <2>; 1507 bias-pull-down; 1508 }; 1509 1510 clkreq-pins { 1511 pins = "gpio36"; 1512 function = "pci_e0"; 1513 drive-strength = <2>; 1514 bias-pull-up; 1515 }; 1516 1517 wake-pins { 1518 pins = "gpio37"; 1519 function = "gpio"; 1520 drive-strength = <2>; 1521 bias-pull-up; 1522 }; 1523 }; 1524 1525 pcie0_state_off: pcie0-state-off-state { 1526 perst-pins { 1527 pins = "gpio35"; 1528 function = "gpio"; 1529 drive-strength = <2>; 1530 bias-pull-down; 1531 }; 1532 1533 clkreq-pins { 1534 pins = "gpio36"; 1535 function = "gpio"; 1536 drive-strength = <2>; 1537 bias-disable; 1538 }; 1539 1540 wake-pins { 1541 pins = "gpio37"; 1542 function = "gpio"; 1543 drive-strength = <2>; 1544 bias-disable; 1545 }; 1546 }; 1547 1548 blsp1_uart2_default: blsp1-uart2-default-state { 1549 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1550 function = "blsp_uart2"; 1551 drive-strength = <16>; 1552 bias-disable; 1553 }; 1554 1555 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 1556 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1557 function = "gpio"; 1558 drive-strength = <2>; 1559 bias-disable; 1560 }; 1561 1562 blsp1_i2c3_default: blsp1-i2c3-default-state { 1563 pins = "gpio47", "gpio48"; 1564 function = "blsp_i2c3"; 1565 drive-strength = <16>; 1566 bias-disable; 1567 }; 1568 1569 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1570 pins = "gpio47", "gpio48"; 1571 function = "gpio"; 1572 drive-strength = <2>; 1573 bias-disable; 1574 }; 1575 1576 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { 1577 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1578 function = "blsp_uart9"; 1579 drive-strength = <16>; 1580 bias-disable; 1581 }; 1582 1583 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { 1584 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1585 function = "blsp_uart9"; 1586 drive-strength = <2>; 1587 bias-disable; 1588 }; 1589 1590 blsp2_i2c3_default: blsp2-i2c3-state-state { 1591 pins = "gpio51", "gpio52"; 1592 function = "blsp_i2c9"; 1593 drive-strength = <16>; 1594 bias-disable; 1595 }; 1596 1597 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1598 pins = "gpio51", "gpio52"; 1599 function = "gpio"; 1600 drive-strength = <2>; 1601 bias-disable; 1602 }; 1603 1604 wcd_intr_default: wcd-intr-default-state { 1605 pins = "gpio54"; 1606 function = "gpio"; 1607 drive-strength = <2>; 1608 bias-pull-down; 1609 }; 1610 1611 blsp2_i2c1_default: blsp2-i2c1-state { 1612 pins = "gpio55", "gpio56"; 1613 function = "blsp_i2c7"; 1614 drive-strength = <16>; 1615 bias-disable; 1616 }; 1617 1618 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1619 pins = "gpio55", "gpio56"; 1620 function = "gpio"; 1621 drive-strength = <2>; 1622 bias-disable; 1623 }; 1624 1625 blsp2_i2c5_default: blsp2-i2c5-state { 1626 pins = "gpio60", "gpio61"; 1627 function = "blsp_i2c11"; 1628 drive-strength = <2>; 1629 bias-disable; 1630 }; 1631 1632 /* Sleep state for BLSP2_I2C5 is missing.. */ 1633 1634 cdc_reset_active: cdc-reset-active-state { 1635 pins = "gpio64"; 1636 function = "gpio"; 1637 drive-strength = <16>; 1638 bias-pull-down; 1639 output-high; 1640 }; 1641 1642 cdc_reset_sleep: cdc-reset-sleep-state { 1643 pins = "gpio64"; 1644 function = "gpio"; 1645 drive-strength = <16>; 1646 bias-disable; 1647 output-low; 1648 }; 1649 1650 blsp2_spi6_default: blsp2-spi6-default-state { 1651 spi-pins { 1652 pins = "gpio85", "gpio86", "gpio88"; 1653 function = "blsp_spi12"; 1654 drive-strength = <12>; 1655 bias-disable; 1656 }; 1657 1658 cs-pins { 1659 pins = "gpio87"; 1660 function = "gpio"; 1661 drive-strength = <16>; 1662 bias-disable; 1663 output-high; 1664 }; 1665 }; 1666 1667 blsp2_spi6_sleep: blsp2-spi6-sleep-state { 1668 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1669 function = "gpio"; 1670 drive-strength = <2>; 1671 bias-pull-down; 1672 }; 1673 1674 blsp2_i2c6_default: blsp2-i2c6-state { 1675 pins = "gpio87", "gpio88"; 1676 function = "blsp_i2c12"; 1677 drive-strength = <16>; 1678 bias-disable; 1679 }; 1680 1681 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1682 pins = "gpio87", "gpio88"; 1683 function = "gpio"; 1684 drive-strength = <2>; 1685 bias-disable; 1686 }; 1687 1688 pcie1_state_on: pcie1-on-state { 1689 perst-pins { 1690 pins = "gpio130"; 1691 function = "gpio"; 1692 drive-strength = <2>; 1693 bias-pull-down; 1694 }; 1695 1696 clkreq-pins { 1697 pins = "gpio131"; 1698 function = "pci_e1"; 1699 drive-strength = <2>; 1700 bias-pull-up; 1701 }; 1702 1703 wake-pins { 1704 pins = "gpio132"; 1705 function = "gpio"; 1706 drive-strength = <2>; 1707 bias-pull-down; 1708 }; 1709 }; 1710 1711 pcie1_state_off: pcie1-off-state { 1712 /* Perst is missing? */ 1713 clkreq-pins { 1714 pins = "gpio131"; 1715 function = "gpio"; 1716 drive-strength = <2>; 1717 bias-disable; 1718 }; 1719 1720 wake-pins { 1721 pins = "gpio132"; 1722 function = "gpio"; 1723 drive-strength = <2>; 1724 bias-disable; 1725 }; 1726 }; 1727 1728 pcie2_state_on: pcie2-on-state { 1729 perst-pins { 1730 pins = "gpio114"; 1731 function = "gpio"; 1732 drive-strength = <2>; 1733 bias-pull-down; 1734 }; 1735 1736 clkreq-pins { 1737 pins = "gpio115"; 1738 function = "pci_e2"; 1739 drive-strength = <2>; 1740 bias-pull-up; 1741 }; 1742 1743 wake-pins { 1744 pins = "gpio116"; 1745 function = "gpio"; 1746 drive-strength = <2>; 1747 bias-pull-down; 1748 }; 1749 }; 1750 1751 pcie2_state_off: pcie2-off-state { 1752 /* Perst is missing? */ 1753 clkreq-pins { 1754 pins = "gpio115"; 1755 function = "gpio"; 1756 drive-strength = <2>; 1757 bias-disable; 1758 }; 1759 1760 wake-pins { 1761 pins = "gpio116"; 1762 function = "gpio"; 1763 drive-strength = <2>; 1764 bias-disable; 1765 }; 1766 }; 1767 1768 sdc1_state_on: sdc1-on-state { 1769 clk-pins { 1770 pins = "sdc1_clk"; 1771 bias-disable; 1772 drive-strength = <16>; 1773 }; 1774 1775 cmd-pins { 1776 pins = "sdc1_cmd"; 1777 bias-pull-up; 1778 drive-strength = <10>; 1779 }; 1780 1781 data-pins { 1782 pins = "sdc1_data"; 1783 bias-pull-up; 1784 drive-strength = <10>; 1785 }; 1786 1787 rclk-pins { 1788 pins = "sdc1_rclk"; 1789 bias-pull-down; 1790 }; 1791 }; 1792 1793 sdc1_state_off: sdc1-off-state { 1794 clk-pins { 1795 pins = "sdc1_clk"; 1796 bias-disable; 1797 drive-strength = <2>; 1798 }; 1799 1800 cmd-pins { 1801 pins = "sdc1_cmd"; 1802 bias-pull-up; 1803 drive-strength = <2>; 1804 }; 1805 1806 data-pins { 1807 pins = "sdc1_data"; 1808 bias-pull-up; 1809 drive-strength = <2>; 1810 }; 1811 1812 rclk-pins { 1813 pins = "sdc1_rclk"; 1814 bias-pull-down; 1815 }; 1816 }; 1817 1818 sdc2_state_on: sdc2-on-state { 1819 clk-pins { 1820 pins = "sdc2_clk"; 1821 bias-disable; 1822 drive-strength = <16>; 1823 }; 1824 1825 cmd-pins { 1826 pins = "sdc2_cmd"; 1827 bias-pull-up; 1828 drive-strength = <10>; 1829 }; 1830 1831 data-pins { 1832 pins = "sdc2_data"; 1833 bias-pull-up; 1834 drive-strength = <10>; 1835 }; 1836 }; 1837 1838 sdc2_state_off: sdc2-off-state { 1839 clk-pins { 1840 pins = "sdc2_clk"; 1841 bias-disable; 1842 drive-strength = <2>; 1843 }; 1844 1845 cmd-pins { 1846 pins = "sdc2_cmd"; 1847 bias-pull-up; 1848 drive-strength = <2>; 1849 }; 1850 1851 data-pins { 1852 pins = "sdc2_data"; 1853 bias-pull-up; 1854 drive-strength = <2>; 1855 }; 1856 }; 1857 }; 1858 1859 sram@290000 { 1860 compatible = "qcom,rpm-stats"; 1861 reg = <0x00290000 0x10000>; 1862 }; 1863 1864 spmi_bus: spmi@400f000 { 1865 compatible = "qcom,spmi-pmic-arb"; 1866 reg = <0x0400f000 0x1000>, 1867 <0x04400000 0x800000>, 1868 <0x04c00000 0x800000>, 1869 <0x05800000 0x200000>, 1870 <0x0400a000 0x002100>; 1871 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1872 interrupt-names = "periph_irq"; 1873 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1874 qcom,ee = <0>; 1875 qcom,channel = <0>; 1876 #address-cells = <2>; 1877 #size-cells = <0>; 1878 interrupt-controller; 1879 #interrupt-cells = <4>; 1880 }; 1881 1882 bus@0 { 1883 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1884 compatible = "simple-pm-bus"; 1885 #address-cells = <1>; 1886 #size-cells = <1>; 1887 ranges = <0x0 0x0 0xffffffff>; 1888 1889 pcie0: pcie@600000 { 1890 compatible = "qcom,pcie-msm8996"; 1891 status = "disabled"; 1892 power-domains = <&gcc PCIE0_GDSC>; 1893 bus-range = <0x00 0xff>; 1894 num-lanes = <1>; 1895 1896 reg = <0x00600000 0x2000>, 1897 <0x0c000000 0xf1d>, 1898 <0x0c000f20 0xa8>, 1899 <0x0c100000 0x100000>; 1900 reg-names = "parf", "dbi", "elbi","config"; 1901 1902 phys = <&pciephy_0>; 1903 phy-names = "pciephy"; 1904 1905 #address-cells = <3>; 1906 #size-cells = <2>; 1907 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, 1908 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1909 1910 device_type = "pci"; 1911 1912 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1913 interrupt-names = "msi"; 1914 #interrupt-cells = <1>; 1915 interrupt-map-mask = <0 0 0 0x7>; 1916 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1917 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1918 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1919 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1920 1921 pinctrl-names = "default", "sleep"; 1922 pinctrl-0 = <&pcie0_state_on>; 1923 pinctrl-1 = <&pcie0_state_off>; 1924 1925 linux,pci-domain = <0>; 1926 1927 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1928 <&gcc GCC_PCIE_0_AUX_CLK>, 1929 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1930 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1931 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1932 1933 clock-names = "pipe", 1934 "aux", 1935 "cfg", 1936 "bus_master", 1937 "bus_slave"; 1938 }; 1939 1940 pcie1: pcie@608000 { 1941 compatible = "qcom,pcie-msm8996"; 1942 power-domains = <&gcc PCIE1_GDSC>; 1943 bus-range = <0x00 0xff>; 1944 num-lanes = <1>; 1945 1946 status = "disabled"; 1947 1948 reg = <0x00608000 0x2000>, 1949 <0x0d000000 0xf1d>, 1950 <0x0d000f20 0xa8>, 1951 <0x0d100000 0x100000>; 1952 1953 reg-names = "parf", "dbi", "elbi","config"; 1954 1955 phys = <&pciephy_1>; 1956 phy-names = "pciephy"; 1957 1958 #address-cells = <3>; 1959 #size-cells = <2>; 1960 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, 1961 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 1962 1963 device_type = "pci"; 1964 1965 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1966 interrupt-names = "msi"; 1967 #interrupt-cells = <1>; 1968 interrupt-map-mask = <0 0 0 0x7>; 1969 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1970 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1971 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1972 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1973 1974 pinctrl-names = "default", "sleep"; 1975 pinctrl-0 = <&pcie1_state_on>; 1976 pinctrl-1 = <&pcie1_state_off>; 1977 1978 linux,pci-domain = <1>; 1979 1980 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1981 <&gcc GCC_PCIE_1_AUX_CLK>, 1982 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1983 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1984 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 1985 1986 clock-names = "pipe", 1987 "aux", 1988 "cfg", 1989 "bus_master", 1990 "bus_slave"; 1991 }; 1992 1993 pcie2: pcie@610000 { 1994 compatible = "qcom,pcie-msm8996"; 1995 power-domains = <&gcc PCIE2_GDSC>; 1996 bus-range = <0x00 0xff>; 1997 num-lanes = <1>; 1998 status = "disabled"; 1999 reg = <0x00610000 0x2000>, 2000 <0x0e000000 0xf1d>, 2001 <0x0e000f20 0xa8>, 2002 <0x0e100000 0x100000>; 2003 2004 reg-names = "parf", "dbi", "elbi","config"; 2005 2006 phys = <&pciephy_2>; 2007 phy-names = "pciephy"; 2008 2009 #address-cells = <3>; 2010 #size-cells = <2>; 2011 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, 2012 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 2013 2014 device_type = "pci"; 2015 2016 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 2017 interrupt-names = "msi"; 2018 #interrupt-cells = <1>; 2019 interrupt-map-mask = <0 0 0 0x7>; 2020 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2021 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2022 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2023 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2024 2025 pinctrl-names = "default", "sleep"; 2026 pinctrl-0 = <&pcie2_state_on>; 2027 pinctrl-1 = <&pcie2_state_off>; 2028 2029 linux,pci-domain = <2>; 2030 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2031 <&gcc GCC_PCIE_2_AUX_CLK>, 2032 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2033 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2034 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 2035 2036 clock-names = "pipe", 2037 "aux", 2038 "cfg", 2039 "bus_master", 2040 "bus_slave"; 2041 }; 2042 }; 2043 2044 ufshc: ufshc@624000 { 2045 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 2046 "jedec,ufs-2.0"; 2047 reg = <0x00624000 0x2500>; 2048 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2049 2050 phys = <&ufsphy_lane>; 2051 phy-names = "ufsphy"; 2052 2053 power-domains = <&gcc UFS_GDSC>; 2054 2055 clock-names = 2056 "core_clk_src", 2057 "core_clk", 2058 "bus_clk", 2059 "bus_aggr_clk", 2060 "iface_clk", 2061 "core_clk_unipro_src", 2062 "core_clk_unipro", 2063 "core_clk_ice", 2064 "ref_clk", 2065 "tx_lane0_sync_clk", 2066 "rx_lane0_sync_clk"; 2067 clocks = 2068 <&gcc UFS_AXI_CLK_SRC>, 2069 <&gcc GCC_UFS_AXI_CLK>, 2070 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 2071 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 2072 <&gcc GCC_UFS_AHB_CLK>, 2073 <&gcc UFS_ICE_CORE_CLK_SRC>, 2074 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 2075 <&gcc GCC_UFS_ICE_CORE_CLK>, 2076 <&rpmcc RPM_SMD_LN_BB_CLK>, 2077 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 2078 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 2079 freq-table-hz = 2080 <100000000 200000000>, 2081 <0 0>, 2082 <0 0>, 2083 <0 0>, 2084 <0 0>, 2085 <150000000 300000000>, 2086 <0 0>, 2087 <0 0>, 2088 <0 0>, 2089 <0 0>, 2090 <0 0>; 2091 2092 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, 2093 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; 2094 interconnect-names = "ufs-ddr", "cpu-ufs"; 2095 2096 lanes-per-direction = <1>; 2097 #reset-cells = <1>; 2098 status = "disabled"; 2099 }; 2100 2101 ufsphy: phy@627000 { 2102 compatible = "qcom,msm8996-qmp-ufs-phy"; 2103 reg = <0x00627000 0x1c4>; 2104 #address-cells = <1>; 2105 #size-cells = <1>; 2106 ranges; 2107 2108 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 2109 clock-names = "ref"; 2110 2111 resets = <&ufshc 0>; 2112 reset-names = "ufsphy"; 2113 status = "disabled"; 2114 2115 ufsphy_lane: phy@627400 { 2116 reg = <0x627400 0x12c>, 2117 <0x627600 0x200>, 2118 <0x627c00 0x1b4>; 2119 #clock-cells = <1>; 2120 #phy-cells = <0>; 2121 }; 2122 }; 2123 2124 camss: camss@a34000 { 2125 compatible = "qcom,msm8996-camss"; 2126 reg = <0x00a34000 0x1000>, 2127 <0x00a00030 0x4>, 2128 <0x00a35000 0x1000>, 2129 <0x00a00038 0x4>, 2130 <0x00a36000 0x1000>, 2131 <0x00a00040 0x4>, 2132 <0x00a30000 0x100>, 2133 <0x00a30400 0x100>, 2134 <0x00a30800 0x100>, 2135 <0x00a30c00 0x100>, 2136 <0x00a31000 0x500>, 2137 <0x00a00020 0x10>, 2138 <0x00a10000 0x1000>, 2139 <0x00a14000 0x1000>; 2140 reg-names = "csiphy0", 2141 "csiphy0_clk_mux", 2142 "csiphy1", 2143 "csiphy1_clk_mux", 2144 "csiphy2", 2145 "csiphy2_clk_mux", 2146 "csid0", 2147 "csid1", 2148 "csid2", 2149 "csid3", 2150 "ispif", 2151 "csi_clk_mux", 2152 "vfe0", 2153 "vfe1"; 2154 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2155 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2156 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2157 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2158 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2159 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2160 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2161 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2162 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2163 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2164 interrupt-names = "csiphy0", 2165 "csiphy1", 2166 "csiphy2", 2167 "csid0", 2168 "csid1", 2169 "csid2", 2170 "csid3", 2171 "ispif", 2172 "vfe0", 2173 "vfe1"; 2174 power-domains = <&mmcc VFE0_GDSC>, 2175 <&mmcc VFE1_GDSC>; 2176 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2177 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2178 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2179 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2180 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2181 <&mmcc CAMSS_CSI0_AHB_CLK>, 2182 <&mmcc CAMSS_CSI0_CLK>, 2183 <&mmcc CAMSS_CSI0PHY_CLK>, 2184 <&mmcc CAMSS_CSI0PIX_CLK>, 2185 <&mmcc CAMSS_CSI0RDI_CLK>, 2186 <&mmcc CAMSS_CSI1_AHB_CLK>, 2187 <&mmcc CAMSS_CSI1_CLK>, 2188 <&mmcc CAMSS_CSI1PHY_CLK>, 2189 <&mmcc CAMSS_CSI1PIX_CLK>, 2190 <&mmcc CAMSS_CSI1RDI_CLK>, 2191 <&mmcc CAMSS_CSI2_AHB_CLK>, 2192 <&mmcc CAMSS_CSI2_CLK>, 2193 <&mmcc CAMSS_CSI2PHY_CLK>, 2194 <&mmcc CAMSS_CSI2PIX_CLK>, 2195 <&mmcc CAMSS_CSI2RDI_CLK>, 2196 <&mmcc CAMSS_CSI3_AHB_CLK>, 2197 <&mmcc CAMSS_CSI3_CLK>, 2198 <&mmcc CAMSS_CSI3PHY_CLK>, 2199 <&mmcc CAMSS_CSI3PIX_CLK>, 2200 <&mmcc CAMSS_CSI3RDI_CLK>, 2201 <&mmcc CAMSS_AHB_CLK>, 2202 <&mmcc CAMSS_VFE0_CLK>, 2203 <&mmcc CAMSS_CSI_VFE0_CLK>, 2204 <&mmcc CAMSS_VFE0_AHB_CLK>, 2205 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2206 <&mmcc CAMSS_VFE1_CLK>, 2207 <&mmcc CAMSS_CSI_VFE1_CLK>, 2208 <&mmcc CAMSS_VFE1_AHB_CLK>, 2209 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2210 <&mmcc CAMSS_VFE_AHB_CLK>, 2211 <&mmcc CAMSS_VFE_AXI_CLK>; 2212 clock-names = "top_ahb", 2213 "ispif_ahb", 2214 "csiphy0_timer", 2215 "csiphy1_timer", 2216 "csiphy2_timer", 2217 "csi0_ahb", 2218 "csi0", 2219 "csi0_phy", 2220 "csi0_pix", 2221 "csi0_rdi", 2222 "csi1_ahb", 2223 "csi1", 2224 "csi1_phy", 2225 "csi1_pix", 2226 "csi1_rdi", 2227 "csi2_ahb", 2228 "csi2", 2229 "csi2_phy", 2230 "csi2_pix", 2231 "csi2_rdi", 2232 "csi3_ahb", 2233 "csi3", 2234 "csi3_phy", 2235 "csi3_pix", 2236 "csi3_rdi", 2237 "ahb", 2238 "vfe0", 2239 "csi_vfe0", 2240 "vfe0_ahb", 2241 "vfe0_stream", 2242 "vfe1", 2243 "csi_vfe1", 2244 "vfe1_ahb", 2245 "vfe1_stream", 2246 "vfe_ahb", 2247 "vfe_axi"; 2248 iommus = <&vfe_smmu 0>, 2249 <&vfe_smmu 1>, 2250 <&vfe_smmu 2>, 2251 <&vfe_smmu 3>; 2252 status = "disabled"; 2253 ports { 2254 #address-cells = <1>; 2255 #size-cells = <0>; 2256 }; 2257 }; 2258 2259 cci: cci@a0c000 { 2260 compatible = "qcom,msm8996-cci"; 2261 #address-cells = <1>; 2262 #size-cells = <0>; 2263 reg = <0xa0c000 0x1000>; 2264 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2265 power-domains = <&mmcc CAMSS_GDSC>; 2266 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2267 <&mmcc CAMSS_CCI_AHB_CLK>, 2268 <&mmcc CAMSS_CCI_CLK>, 2269 <&mmcc CAMSS_AHB_CLK>; 2270 clock-names = "camss_top_ahb", 2271 "cci_ahb", 2272 "cci", 2273 "camss_ahb"; 2274 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2275 <&mmcc CAMSS_CCI_CLK>; 2276 assigned-clock-rates = <80000000>, <37500000>; 2277 pinctrl-names = "default"; 2278 pinctrl-0 = <&cci0_default &cci1_default>; 2279 status = "disabled"; 2280 2281 cci_i2c0: i2c-bus@0 { 2282 reg = <0>; 2283 clock-frequency = <400000>; 2284 #address-cells = <1>; 2285 #size-cells = <0>; 2286 }; 2287 2288 cci_i2c1: i2c-bus@1 { 2289 reg = <1>; 2290 clock-frequency = <400000>; 2291 #address-cells = <1>; 2292 #size-cells = <0>; 2293 }; 2294 }; 2295 2296 adreno_smmu: iommu@b40000 { 2297 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2298 reg = <0x00b40000 0x10000>; 2299 2300 #global-interrupts = <1>; 2301 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2302 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2303 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2304 #iommu-cells = <1>; 2305 2306 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, 2307 <&mmcc GPU_AHB_CLK>; 2308 clock-names = "bus", "iface"; 2309 2310 power-domains = <&mmcc GPU_GDSC>; 2311 }; 2312 2313 venus: video-codec@c00000 { 2314 compatible = "qcom,msm8996-venus"; 2315 reg = <0x00c00000 0xff000>; 2316 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2317 power-domains = <&mmcc VENUS_GDSC>; 2318 clocks = <&mmcc VIDEO_CORE_CLK>, 2319 <&mmcc VIDEO_AHB_CLK>, 2320 <&mmcc VIDEO_AXI_CLK>, 2321 <&mmcc VIDEO_MAXI_CLK>; 2322 clock-names = "core", "iface", "bus", "mbus"; 2323 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2324 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2325 interconnect-names = "video-mem", "cpu-cfg"; 2326 iommus = <&venus_smmu 0x00>, 2327 <&venus_smmu 0x01>, 2328 <&venus_smmu 0x0a>, 2329 <&venus_smmu 0x07>, 2330 <&venus_smmu 0x0e>, 2331 <&venus_smmu 0x0f>, 2332 <&venus_smmu 0x08>, 2333 <&venus_smmu 0x09>, 2334 <&venus_smmu 0x0b>, 2335 <&venus_smmu 0x0c>, 2336 <&venus_smmu 0x0d>, 2337 <&venus_smmu 0x10>, 2338 <&venus_smmu 0x11>, 2339 <&venus_smmu 0x21>, 2340 <&venus_smmu 0x28>, 2341 <&venus_smmu 0x29>, 2342 <&venus_smmu 0x2b>, 2343 <&venus_smmu 0x2c>, 2344 <&venus_smmu 0x2d>, 2345 <&venus_smmu 0x31>; 2346 memory-region = <&venus_mem>; 2347 status = "disabled"; 2348 2349 video-decoder { 2350 compatible = "venus-decoder"; 2351 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2352 clock-names = "core"; 2353 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2354 }; 2355 2356 video-encoder { 2357 compatible = "venus-encoder"; 2358 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2359 clock-names = "core"; 2360 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2361 }; 2362 }; 2363 2364 mdp_smmu: iommu@d00000 { 2365 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2366 reg = <0x00d00000 0x10000>; 2367 2368 #global-interrupts = <1>; 2369 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2370 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2371 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2372 #iommu-cells = <1>; 2373 clocks = <&mmcc SMMU_MDP_AXI_CLK>, 2374 <&mmcc SMMU_MDP_AHB_CLK>; 2375 clock-names = "bus", "iface"; 2376 2377 power-domains = <&mmcc MDSS_GDSC>; 2378 }; 2379 2380 venus_smmu: iommu@d40000 { 2381 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2382 reg = <0x00d40000 0x20000>; 2383 #global-interrupts = <1>; 2384 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2385 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2386 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2387 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2388 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2389 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2390 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2391 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2392 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2393 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, 2394 <&mmcc SMMU_VIDEO_AHB_CLK>; 2395 clock-names = "bus", "iface"; 2396 #iommu-cells = <1>; 2397 status = "okay"; 2398 }; 2399 2400 vfe_smmu: iommu@da0000 { 2401 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2402 reg = <0x00da0000 0x10000>; 2403 2404 #global-interrupts = <1>; 2405 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2406 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2407 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2408 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2409 clocks = <&mmcc SMMU_VFE_AXI_CLK>, 2410 <&mmcc SMMU_VFE_AHB_CLK>; 2411 clock-names = "bus", "iface"; 2412 #iommu-cells = <1>; 2413 }; 2414 2415 lpass_q6_smmu: iommu@1600000 { 2416 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2417 reg = <0x01600000 0x20000>; 2418 #iommu-cells = <1>; 2419 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2420 2421 #global-interrupts = <1>; 2422 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2423 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2424 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2426 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2427 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2428 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2429 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2430 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2435 2436 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, 2437 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; 2438 clock-names = "bus", "iface"; 2439 }; 2440 2441 slpi_pil: remoteproc@1c00000 { 2442 compatible = "qcom,msm8996-slpi-pil"; 2443 reg = <0x01c00000 0x4000>; 2444 2445 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2446 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2447 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2448 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2449 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2450 interrupt-names = "wdog", 2451 "fatal", 2452 "ready", 2453 "handover", 2454 "stop-ack"; 2455 2456 clocks = <&xo_board>, 2457 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 2458 clock-names = "xo", "aggre2"; 2459 2460 memory-region = <&slpi_mem>; 2461 2462 qcom,smem-states = <&slpi_smp2p_out 0>; 2463 qcom,smem-state-names = "stop"; 2464 2465 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2466 power-domain-names = "ssc_cx"; 2467 2468 status = "disabled"; 2469 2470 smd-edge { 2471 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2472 2473 label = "dsps"; 2474 mboxes = <&apcs_glb 25>; 2475 qcom,smd-edge = <3>; 2476 qcom,remote-pid = <3>; 2477 }; 2478 }; 2479 2480 mss_pil: remoteproc@2080000 { 2481 compatible = "qcom,msm8996-mss-pil"; 2482 reg = <0x2080000 0x100>, 2483 <0x2180000 0x020>; 2484 reg-names = "qdsp6", "rmb"; 2485 2486 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2487 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2488 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2489 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2490 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2491 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2492 interrupt-names = "wdog", "fatal", "ready", 2493 "handover", "stop-ack", 2494 "shutdown-ack"; 2495 2496 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2497 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2498 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2499 <&xo_board>, 2500 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2501 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2502 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2503 <&rpmcc RPM_SMD_PCNOC_CLK>, 2504 <&rpmcc RPM_SMD_QDSS_CLK>; 2505 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", 2506 "snoc_axi", "mnoc_axi", "pnoc", "qdss"; 2507 2508 resets = <&gcc GCC_MSS_RESTART>; 2509 reset-names = "mss_restart"; 2510 2511 power-domains = <&rpmpd MSM8996_VDDCX>, 2512 <&rpmpd MSM8996_VDDMX>; 2513 power-domain-names = "cx", "mx"; 2514 2515 qcom,smem-states = <&mpss_smp2p_out 0>; 2516 qcom,smem-state-names = "stop"; 2517 2518 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2519 2520 status = "disabled"; 2521 2522 mba { 2523 memory-region = <&mba_mem>; 2524 }; 2525 2526 mpss { 2527 memory-region = <&mpss_mem>; 2528 }; 2529 2530 metadata { 2531 memory-region = <&mdata_mem>; 2532 }; 2533 2534 smd-edge { 2535 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2536 2537 label = "mpss"; 2538 mboxes = <&apcs_glb 12>; 2539 qcom,smd-edge = <0>; 2540 qcom,remote-pid = <1>; 2541 }; 2542 }; 2543 2544 stm@3002000 { 2545 compatible = "arm,coresight-stm", "arm,primecell"; 2546 reg = <0x3002000 0x1000>, 2547 <0x8280000 0x180000>; 2548 reg-names = "stm-base", "stm-stimulus-base"; 2549 2550 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2551 clock-names = "apb_pclk", "atclk"; 2552 2553 out-ports { 2554 port { 2555 stm_out: endpoint { 2556 remote-endpoint = 2557 <&funnel0_in>; 2558 }; 2559 }; 2560 }; 2561 }; 2562 2563 tpiu@3020000 { 2564 compatible = "arm,coresight-tpiu", "arm,primecell"; 2565 reg = <0x3020000 0x1000>; 2566 2567 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2568 clock-names = "apb_pclk", "atclk"; 2569 2570 in-ports { 2571 port { 2572 tpiu_in: endpoint { 2573 remote-endpoint = 2574 <&replicator_out1>; 2575 }; 2576 }; 2577 }; 2578 }; 2579 2580 funnel@3021000 { 2581 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2582 reg = <0x3021000 0x1000>; 2583 2584 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2585 clock-names = "apb_pclk", "atclk"; 2586 2587 in-ports { 2588 #address-cells = <1>; 2589 #size-cells = <0>; 2590 2591 port@7 { 2592 reg = <7>; 2593 funnel0_in: endpoint { 2594 remote-endpoint = 2595 <&stm_out>; 2596 }; 2597 }; 2598 }; 2599 2600 out-ports { 2601 port { 2602 funnel0_out: endpoint { 2603 remote-endpoint = 2604 <&merge_funnel_in0>; 2605 }; 2606 }; 2607 }; 2608 }; 2609 2610 funnel@3022000 { 2611 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2612 reg = <0x3022000 0x1000>; 2613 2614 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2615 clock-names = "apb_pclk", "atclk"; 2616 2617 in-ports { 2618 #address-cells = <1>; 2619 #size-cells = <0>; 2620 2621 port@6 { 2622 reg = <6>; 2623 funnel1_in: endpoint { 2624 remote-endpoint = 2625 <&apss_merge_funnel_out>; 2626 }; 2627 }; 2628 }; 2629 2630 out-ports { 2631 port { 2632 funnel1_out: endpoint { 2633 remote-endpoint = 2634 <&merge_funnel_in1>; 2635 }; 2636 }; 2637 }; 2638 }; 2639 2640 funnel@3023000 { 2641 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2642 reg = <0x3023000 0x1000>; 2643 2644 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2645 clock-names = "apb_pclk", "atclk"; 2646 2647 2648 out-ports { 2649 port { 2650 funnel2_out: endpoint { 2651 remote-endpoint = 2652 <&merge_funnel_in2>; 2653 }; 2654 }; 2655 }; 2656 }; 2657 2658 funnel@3025000 { 2659 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2660 reg = <0x3025000 0x1000>; 2661 2662 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2663 clock-names = "apb_pclk", "atclk"; 2664 2665 in-ports { 2666 #address-cells = <1>; 2667 #size-cells = <0>; 2668 2669 port@0 { 2670 reg = <0>; 2671 merge_funnel_in0: endpoint { 2672 remote-endpoint = 2673 <&funnel0_out>; 2674 }; 2675 }; 2676 2677 port@1 { 2678 reg = <1>; 2679 merge_funnel_in1: endpoint { 2680 remote-endpoint = 2681 <&funnel1_out>; 2682 }; 2683 }; 2684 2685 port@2 { 2686 reg = <2>; 2687 merge_funnel_in2: endpoint { 2688 remote-endpoint = 2689 <&funnel2_out>; 2690 }; 2691 }; 2692 }; 2693 2694 out-ports { 2695 port { 2696 merge_funnel_out: endpoint { 2697 remote-endpoint = 2698 <&etf_in>; 2699 }; 2700 }; 2701 }; 2702 }; 2703 2704 replicator@3026000 { 2705 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2706 reg = <0x3026000 0x1000>; 2707 2708 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2709 clock-names = "apb_pclk", "atclk"; 2710 2711 in-ports { 2712 port { 2713 replicator_in: endpoint { 2714 remote-endpoint = 2715 <&etf_out>; 2716 }; 2717 }; 2718 }; 2719 2720 out-ports { 2721 #address-cells = <1>; 2722 #size-cells = <0>; 2723 2724 port@0 { 2725 reg = <0>; 2726 replicator_out0: endpoint { 2727 remote-endpoint = 2728 <&etr_in>; 2729 }; 2730 }; 2731 2732 port@1 { 2733 reg = <1>; 2734 replicator_out1: endpoint { 2735 remote-endpoint = 2736 <&tpiu_in>; 2737 }; 2738 }; 2739 }; 2740 }; 2741 2742 etf@3027000 { 2743 compatible = "arm,coresight-tmc", "arm,primecell"; 2744 reg = <0x3027000 0x1000>; 2745 2746 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2747 clock-names = "apb_pclk", "atclk"; 2748 2749 in-ports { 2750 port { 2751 etf_in: endpoint { 2752 remote-endpoint = 2753 <&merge_funnel_out>; 2754 }; 2755 }; 2756 }; 2757 2758 out-ports { 2759 port { 2760 etf_out: endpoint { 2761 remote-endpoint = 2762 <&replicator_in>; 2763 }; 2764 }; 2765 }; 2766 }; 2767 2768 etr@3028000 { 2769 compatible = "arm,coresight-tmc", "arm,primecell"; 2770 reg = <0x3028000 0x1000>; 2771 2772 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2773 clock-names = "apb_pclk", "atclk"; 2774 arm,scatter-gather; 2775 2776 in-ports { 2777 port { 2778 etr_in: endpoint { 2779 remote-endpoint = 2780 <&replicator_out0>; 2781 }; 2782 }; 2783 }; 2784 }; 2785 2786 debug@3810000 { 2787 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2788 reg = <0x3810000 0x1000>; 2789 2790 clocks = <&rpmcc RPM_QDSS_CLK>; 2791 clock-names = "apb_pclk"; 2792 2793 cpu = <&CPU0>; 2794 }; 2795 2796 etm@3840000 { 2797 compatible = "arm,coresight-etm4x", "arm,primecell"; 2798 reg = <0x3840000 0x1000>; 2799 2800 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2801 clock-names = "apb_pclk", "atclk"; 2802 2803 cpu = <&CPU0>; 2804 2805 out-ports { 2806 port { 2807 etm0_out: endpoint { 2808 remote-endpoint = 2809 <&apss_funnel0_in0>; 2810 }; 2811 }; 2812 }; 2813 }; 2814 2815 debug@3910000 { 2816 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2817 reg = <0x3910000 0x1000>; 2818 2819 clocks = <&rpmcc RPM_QDSS_CLK>; 2820 clock-names = "apb_pclk"; 2821 2822 cpu = <&CPU1>; 2823 }; 2824 2825 etm@3940000 { 2826 compatible = "arm,coresight-etm4x", "arm,primecell"; 2827 reg = <0x3940000 0x1000>; 2828 2829 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2830 clock-names = "apb_pclk", "atclk"; 2831 2832 cpu = <&CPU1>; 2833 2834 out-ports { 2835 port { 2836 etm1_out: endpoint { 2837 remote-endpoint = 2838 <&apss_funnel0_in1>; 2839 }; 2840 }; 2841 }; 2842 }; 2843 2844 funnel@39b0000 { /* APSS Funnel 0 */ 2845 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2846 reg = <0x39b0000 0x1000>; 2847 2848 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2849 clock-names = "apb_pclk", "atclk"; 2850 2851 in-ports { 2852 #address-cells = <1>; 2853 #size-cells = <0>; 2854 2855 port@0 { 2856 reg = <0>; 2857 apss_funnel0_in0: endpoint { 2858 remote-endpoint = <&etm0_out>; 2859 }; 2860 }; 2861 2862 port@1 { 2863 reg = <1>; 2864 apss_funnel0_in1: endpoint { 2865 remote-endpoint = <&etm1_out>; 2866 }; 2867 }; 2868 }; 2869 2870 out-ports { 2871 port { 2872 apss_funnel0_out: endpoint { 2873 remote-endpoint = 2874 <&apss_merge_funnel_in0>; 2875 }; 2876 }; 2877 }; 2878 }; 2879 2880 debug@3a10000 { 2881 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2882 reg = <0x3a10000 0x1000>; 2883 2884 clocks = <&rpmcc RPM_QDSS_CLK>; 2885 clock-names = "apb_pclk"; 2886 2887 cpu = <&CPU2>; 2888 }; 2889 2890 etm@3a40000 { 2891 compatible = "arm,coresight-etm4x", "arm,primecell"; 2892 reg = <0x3a40000 0x1000>; 2893 2894 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2895 clock-names = "apb_pclk", "atclk"; 2896 2897 cpu = <&CPU2>; 2898 2899 out-ports { 2900 port { 2901 etm2_out: endpoint { 2902 remote-endpoint = 2903 <&apss_funnel1_in0>; 2904 }; 2905 }; 2906 }; 2907 }; 2908 2909 debug@3b10000 { 2910 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2911 reg = <0x3b10000 0x1000>; 2912 2913 clocks = <&rpmcc RPM_QDSS_CLK>; 2914 clock-names = "apb_pclk"; 2915 2916 cpu = <&CPU3>; 2917 }; 2918 2919 etm@3b40000 { 2920 compatible = "arm,coresight-etm4x", "arm,primecell"; 2921 reg = <0x3b40000 0x1000>; 2922 2923 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2924 clock-names = "apb_pclk", "atclk"; 2925 2926 cpu = <&CPU3>; 2927 2928 out-ports { 2929 port { 2930 etm3_out: endpoint { 2931 remote-endpoint = 2932 <&apss_funnel1_in1>; 2933 }; 2934 }; 2935 }; 2936 }; 2937 2938 funnel@3bb0000 { /* APSS Funnel 1 */ 2939 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2940 reg = <0x3bb0000 0x1000>; 2941 2942 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2943 clock-names = "apb_pclk", "atclk"; 2944 2945 in-ports { 2946 #address-cells = <1>; 2947 #size-cells = <0>; 2948 2949 port@0 { 2950 reg = <0>; 2951 apss_funnel1_in0: endpoint { 2952 remote-endpoint = <&etm2_out>; 2953 }; 2954 }; 2955 2956 port@1 { 2957 reg = <1>; 2958 apss_funnel1_in1: endpoint { 2959 remote-endpoint = <&etm3_out>; 2960 }; 2961 }; 2962 }; 2963 2964 out-ports { 2965 port { 2966 apss_funnel1_out: endpoint { 2967 remote-endpoint = 2968 <&apss_merge_funnel_in1>; 2969 }; 2970 }; 2971 }; 2972 }; 2973 2974 funnel@3bc0000 { 2975 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2976 reg = <0x3bc0000 0x1000>; 2977 2978 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2979 clock-names = "apb_pclk", "atclk"; 2980 2981 in-ports { 2982 #address-cells = <1>; 2983 #size-cells = <0>; 2984 2985 port@0 { 2986 reg = <0>; 2987 apss_merge_funnel_in0: endpoint { 2988 remote-endpoint = 2989 <&apss_funnel0_out>; 2990 }; 2991 }; 2992 2993 port@1 { 2994 reg = <1>; 2995 apss_merge_funnel_in1: endpoint { 2996 remote-endpoint = 2997 <&apss_funnel1_out>; 2998 }; 2999 }; 3000 }; 3001 3002 out-ports { 3003 port { 3004 apss_merge_funnel_out: endpoint { 3005 remote-endpoint = 3006 <&funnel1_in>; 3007 }; 3008 }; 3009 }; 3010 }; 3011 3012 kryocc: clock-controller@6400000 { 3013 compatible = "qcom,msm8996-apcc"; 3014 reg = <0x06400000 0x90000>; 3015 3016 clock-names = "xo", "sys_apcs_aux"; 3017 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3018 3019 #clock-cells = <1>; 3020 }; 3021 3022 usb3: usb@6af8800 { 3023 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3024 reg = <0x06af8800 0x400>; 3025 #address-cells = <1>; 3026 #size-cells = <1>; 3027 ranges; 3028 3029 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 3030 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 3031 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 3032 3033 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 3034 <&gcc GCC_USB30_MASTER_CLK>, 3035 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 3036 <&gcc GCC_USB30_SLEEP_CLK>, 3037 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 3038 clock-names = "cfg_noc", 3039 "core", 3040 "iface", 3041 "sleep", 3042 "mock_utmi"; 3043 3044 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 3045 <&gcc GCC_USB30_MASTER_CLK>; 3046 assigned-clock-rates = <19200000>, <120000000>; 3047 3048 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 3049 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 3050 interconnect-names = "usb-ddr", "apps-usb"; 3051 3052 power-domains = <&gcc USB30_GDSC>; 3053 status = "disabled"; 3054 3055 usb3_dwc3: usb@6a00000 { 3056 compatible = "snps,dwc3"; 3057 reg = <0x06a00000 0xcc00>; 3058 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 3059 phys = <&hsusb_phy1>, <&ssusb_phy_0>; 3060 phy-names = "usb2-phy", "usb3-phy"; 3061 snps,hird-threshold = /bits/ 8 <0>; 3062 snps,dis_u2_susphy_quirk; 3063 snps,dis_enblslpm_quirk; 3064 snps,is-utmi-l1-suspend; 3065 tx-fifo-resize; 3066 }; 3067 }; 3068 3069 usb3phy: phy@7410000 { 3070 compatible = "qcom,msm8996-qmp-usb3-phy"; 3071 reg = <0x07410000 0x1c4>; 3072 #address-cells = <1>; 3073 #size-cells = <1>; 3074 ranges; 3075 3076 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 3077 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3078 <&gcc GCC_USB3_CLKREF_CLK>; 3079 clock-names = "aux", "cfg_ahb", "ref"; 3080 3081 resets = <&gcc GCC_USB3_PHY_BCR>, 3082 <&gcc GCC_USB3PHY_PHY_BCR>; 3083 reset-names = "phy", "common"; 3084 status = "disabled"; 3085 3086 ssusb_phy_0: phy@7410200 { 3087 reg = <0x07410200 0x200>, 3088 <0x07410400 0x130>, 3089 <0x07410600 0x1a8>; 3090 #phy-cells = <0>; 3091 3092 #clock-cells = <0>; 3093 clock-output-names = "usb3_phy_pipe_clk_src"; 3094 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; 3095 clock-names = "pipe0"; 3096 }; 3097 }; 3098 3099 hsusb_phy1: phy@7411000 { 3100 compatible = "qcom,msm8996-qusb2-phy"; 3101 reg = <0x07411000 0x180>; 3102 #phy-cells = <0>; 3103 3104 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3105 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3106 clock-names = "cfg_ahb", "ref"; 3107 3108 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3109 nvmem-cells = <&qusb2p_hstx_trim>; 3110 status = "disabled"; 3111 }; 3112 3113 hsusb_phy2: phy@7412000 { 3114 compatible = "qcom,msm8996-qusb2-phy"; 3115 reg = <0x07412000 0x180>; 3116 #phy-cells = <0>; 3117 3118 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3119 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3120 clock-names = "cfg_ahb", "ref"; 3121 3122 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3123 nvmem-cells = <&qusb2s_hstx_trim>; 3124 status = "disabled"; 3125 }; 3126 3127 sdhc1: mmc@7464900 { 3128 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3129 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3130 reg-names = "hc", "core"; 3131 3132 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3134 interrupt-names = "hc_irq", "pwr_irq"; 3135 3136 clock-names = "iface", "core", "xo"; 3137 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3138 <&gcc GCC_SDCC1_APPS_CLK>, 3139 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3140 resets = <&gcc GCC_SDCC1_BCR>; 3141 3142 pinctrl-names = "default", "sleep"; 3143 pinctrl-0 = <&sdc1_state_on>; 3144 pinctrl-1 = <&sdc1_state_off>; 3145 3146 bus-width = <8>; 3147 non-removable; 3148 status = "disabled"; 3149 }; 3150 3151 sdhc2: mmc@74a4900 { 3152 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3153 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3154 reg-names = "hc", "core"; 3155 3156 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3158 interrupt-names = "hc_irq", "pwr_irq"; 3159 3160 clock-names = "iface", "core", "xo"; 3161 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3162 <&gcc GCC_SDCC2_APPS_CLK>, 3163 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3164 resets = <&gcc GCC_SDCC2_BCR>; 3165 3166 pinctrl-names = "default", "sleep"; 3167 pinctrl-0 = <&sdc2_state_on>; 3168 pinctrl-1 = <&sdc2_state_off>; 3169 3170 bus-width = <4>; 3171 status = "disabled"; 3172 }; 3173 3174 blsp1_dma: dma-controller@7544000 { 3175 compatible = "qcom,bam-v1.7.0"; 3176 reg = <0x07544000 0x2b000>; 3177 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3178 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3179 clock-names = "bam_clk"; 3180 qcom,controlled-remotely; 3181 #dma-cells = <1>; 3182 qcom,ee = <0>; 3183 }; 3184 3185 blsp1_uart2: serial@7570000 { 3186 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3187 reg = <0x07570000 0x1000>; 3188 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3189 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3190 <&gcc GCC_BLSP1_AHB_CLK>; 3191 clock-names = "core", "iface"; 3192 pinctrl-names = "default", "sleep"; 3193 pinctrl-0 = <&blsp1_uart2_default>; 3194 pinctrl-1 = <&blsp1_uart2_sleep>; 3195 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3196 dma-names = "tx", "rx"; 3197 status = "disabled"; 3198 }; 3199 3200 blsp1_spi1: spi@7575000 { 3201 compatible = "qcom,spi-qup-v2.2.1"; 3202 reg = <0x07575000 0x600>; 3203 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3204 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3205 <&gcc GCC_BLSP1_AHB_CLK>; 3206 clock-names = "core", "iface"; 3207 pinctrl-names = "default", "sleep"; 3208 pinctrl-0 = <&blsp1_spi1_default>; 3209 pinctrl-1 = <&blsp1_spi1_sleep>; 3210 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3211 dma-names = "tx", "rx"; 3212 #address-cells = <1>; 3213 #size-cells = <0>; 3214 status = "disabled"; 3215 }; 3216 3217 blsp1_i2c3: i2c@7577000 { 3218 compatible = "qcom,i2c-qup-v2.2.1"; 3219 reg = <0x07577000 0x1000>; 3220 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3221 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3222 <&gcc GCC_BLSP1_AHB_CLK>; 3223 clock-names = "core", "iface"; 3224 pinctrl-names = "default", "sleep"; 3225 pinctrl-0 = <&blsp1_i2c3_default>; 3226 pinctrl-1 = <&blsp1_i2c3_sleep>; 3227 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3228 dma-names = "tx", "rx"; 3229 #address-cells = <1>; 3230 #size-cells = <0>; 3231 status = "disabled"; 3232 }; 3233 3234 blsp1_i2c6: i2c@757a000 { 3235 compatible = "qcom,i2c-qup-v2.2.1"; 3236 reg = <0x757a000 0x1000>; 3237 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3238 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 3239 <&gcc GCC_BLSP1_AHB_CLK>; 3240 clock-names = "core", "iface"; 3241 pinctrl-names = "default", "sleep"; 3242 pinctrl-0 = <&blsp1_i2c6_default>; 3243 pinctrl-1 = <&blsp1_i2c6_sleep>; 3244 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 3245 dma-names = "tx", "rx"; 3246 #address-cells = <1>; 3247 #size-cells = <0>; 3248 status = "disabled"; 3249 }; 3250 3251 blsp2_dma: dma-controller@7584000 { 3252 compatible = "qcom,bam-v1.7.0"; 3253 reg = <0x07584000 0x2b000>; 3254 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3255 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3256 clock-names = "bam_clk"; 3257 qcom,controlled-remotely; 3258 #dma-cells = <1>; 3259 qcom,ee = <0>; 3260 }; 3261 3262 blsp2_uart2: serial@75b0000 { 3263 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3264 reg = <0x075b0000 0x1000>; 3265 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3266 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3267 <&gcc GCC_BLSP2_AHB_CLK>; 3268 clock-names = "core", "iface"; 3269 status = "disabled"; 3270 }; 3271 3272 blsp2_uart3: serial@75b1000 { 3273 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3274 reg = <0x075b1000 0x1000>; 3275 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3276 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3277 <&gcc GCC_BLSP2_AHB_CLK>; 3278 clock-names = "core", "iface"; 3279 status = "disabled"; 3280 }; 3281 3282 blsp2_i2c1: i2c@75b5000 { 3283 compatible = "qcom,i2c-qup-v2.2.1"; 3284 reg = <0x075b5000 0x1000>; 3285 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3286 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3287 <&gcc GCC_BLSP2_AHB_CLK>; 3288 clock-names = "core", "iface"; 3289 pinctrl-names = "default", "sleep"; 3290 pinctrl-0 = <&blsp2_i2c1_default>; 3291 pinctrl-1 = <&blsp2_i2c1_sleep>; 3292 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3293 dma-names = "tx", "rx"; 3294 #address-cells = <1>; 3295 #size-cells = <0>; 3296 status = "disabled"; 3297 }; 3298 3299 blsp2_i2c2: i2c@75b6000 { 3300 compatible = "qcom,i2c-qup-v2.2.1"; 3301 reg = <0x075b6000 0x1000>; 3302 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3303 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3304 <&gcc GCC_BLSP2_AHB_CLK>; 3305 clock-names = "core", "iface"; 3306 pinctrl-names = "default", "sleep"; 3307 pinctrl-0 = <&blsp2_i2c2_default>; 3308 pinctrl-1 = <&blsp2_i2c2_sleep>; 3309 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3310 dma-names = "tx", "rx"; 3311 #address-cells = <1>; 3312 #size-cells = <0>; 3313 status = "disabled"; 3314 }; 3315 3316 blsp2_i2c3: i2c@75b7000 { 3317 compatible = "qcom,i2c-qup-v2.2.1"; 3318 reg = <0x075b7000 0x1000>; 3319 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3320 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3321 <&gcc GCC_BLSP2_AHB_CLK>; 3322 clock-names = "core", "iface"; 3323 clock-frequency = <400000>; 3324 pinctrl-names = "default", "sleep"; 3325 pinctrl-0 = <&blsp2_i2c3_default>; 3326 pinctrl-1 = <&blsp2_i2c3_sleep>; 3327 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3328 dma-names = "tx", "rx"; 3329 #address-cells = <1>; 3330 #size-cells = <0>; 3331 status = "disabled"; 3332 }; 3333 3334 blsp2_i2c5: i2c@75b9000 { 3335 compatible = "qcom,i2c-qup-v2.2.1"; 3336 reg = <0x75b9000 0x1000>; 3337 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3338 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3339 <&gcc GCC_BLSP2_AHB_CLK>; 3340 clock-names = "core", "iface"; 3341 pinctrl-names = "default"; 3342 pinctrl-0 = <&blsp2_i2c5_default>; 3343 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3344 dma-names = "tx", "rx"; 3345 #address-cells = <1>; 3346 #size-cells = <0>; 3347 status = "disabled"; 3348 }; 3349 3350 blsp2_i2c6: i2c@75ba000 { 3351 compatible = "qcom,i2c-qup-v2.2.1"; 3352 reg = <0x75ba000 0x1000>; 3353 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3354 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3355 <&gcc GCC_BLSP2_AHB_CLK>; 3356 clock-names = "core", "iface"; 3357 pinctrl-names = "default", "sleep"; 3358 pinctrl-0 = <&blsp2_i2c6_default>; 3359 pinctrl-1 = <&blsp2_i2c6_sleep>; 3360 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3361 dma-names = "tx", "rx"; 3362 #address-cells = <1>; 3363 #size-cells = <0>; 3364 status = "disabled"; 3365 }; 3366 3367 blsp2_spi6: spi@75ba000 { 3368 compatible = "qcom,spi-qup-v2.2.1"; 3369 reg = <0x075ba000 0x600>; 3370 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3371 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3372 <&gcc GCC_BLSP2_AHB_CLK>; 3373 clock-names = "core", "iface"; 3374 pinctrl-names = "default", "sleep"; 3375 pinctrl-0 = <&blsp2_spi6_default>; 3376 pinctrl-1 = <&blsp2_spi6_sleep>; 3377 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3378 dma-names = "tx", "rx"; 3379 #address-cells = <1>; 3380 #size-cells = <0>; 3381 status = "disabled"; 3382 }; 3383 3384 usb2: usb@76f8800 { 3385 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3386 reg = <0x076f8800 0x400>; 3387 #address-cells = <1>; 3388 #size-cells = <1>; 3389 ranges; 3390 3391 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 3392 interrupt-names = "hs_phy_irq"; 3393 3394 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3395 <&gcc GCC_USB20_MASTER_CLK>, 3396 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3397 <&gcc GCC_USB20_SLEEP_CLK>, 3398 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3399 clock-names = "cfg_noc", 3400 "core", 3401 "iface", 3402 "sleep", 3403 "mock_utmi"; 3404 3405 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3406 <&gcc GCC_USB20_MASTER_CLK>; 3407 assigned-clock-rates = <19200000>, <60000000>; 3408 3409 power-domains = <&gcc USB30_GDSC>; 3410 qcom,select-utmi-as-pipe-clk; 3411 status = "disabled"; 3412 3413 usb2_dwc3: usb@7600000 { 3414 compatible = "snps,dwc3"; 3415 reg = <0x07600000 0xcc00>; 3416 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3417 phys = <&hsusb_phy2>; 3418 phy-names = "usb2-phy"; 3419 maximum-speed = "high-speed"; 3420 snps,dis_u2_susphy_quirk; 3421 snps,dis_enblslpm_quirk; 3422 }; 3423 }; 3424 3425 slimbam: dma-controller@9184000 { 3426 compatible = "qcom,bam-v1.7.0"; 3427 qcom,controlled-remotely; 3428 reg = <0x09184000 0x32000>; 3429 num-channels = <31>; 3430 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 3431 #dma-cells = <1>; 3432 qcom,ee = <1>; 3433 qcom,num-ees = <2>; 3434 }; 3435 3436 slim_msm: slim-ngd@91c0000 { 3437 compatible = "qcom,slim-ngd-v1.5.0"; 3438 reg = <0x091c0000 0x2c000>; 3439 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3440 dmas = <&slimbam 3>, <&slimbam 4>; 3441 dma-names = "rx", "tx"; 3442 #address-cells = <1>; 3443 #size-cells = <0>; 3444 3445 status = "disabled"; 3446 }; 3447 3448 adsp_pil: remoteproc@9300000 { 3449 compatible = "qcom,msm8996-adsp-pil"; 3450 reg = <0x09300000 0x80000>; 3451 3452 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3453 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3454 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3455 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3456 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3457 interrupt-names = "wdog", "fatal", "ready", 3458 "handover", "stop-ack"; 3459 3460 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3461 clock-names = "xo"; 3462 3463 memory-region = <&adsp_mem>; 3464 3465 qcom,smem-states = <&adsp_smp2p_out 0>; 3466 qcom,smem-state-names = "stop"; 3467 3468 power-domains = <&rpmpd MSM8996_VDDCX>; 3469 power-domain-names = "cx"; 3470 3471 status = "disabled"; 3472 3473 smd-edge { 3474 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3475 3476 label = "lpass"; 3477 mboxes = <&apcs_glb 8>; 3478 qcom,smd-edge = <1>; 3479 qcom,remote-pid = <2>; 3480 3481 apr { 3482 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3483 compatible = "qcom,apr-v2"; 3484 qcom,smd-channels = "apr_audio_svc"; 3485 qcom,domain = <APR_DOMAIN_ADSP>; 3486 #address-cells = <1>; 3487 #size-cells = <0>; 3488 3489 service@3 { 3490 reg = <APR_SVC_ADSP_CORE>; 3491 compatible = "qcom,q6core"; 3492 }; 3493 3494 q6afe: service@4 { 3495 compatible = "qcom,q6afe"; 3496 reg = <APR_SVC_AFE>; 3497 q6afedai: dais { 3498 compatible = "qcom,q6afe-dais"; 3499 #address-cells = <1>; 3500 #size-cells = <0>; 3501 #sound-dai-cells = <1>; 3502 dai@1 { 3503 reg = <1>; 3504 }; 3505 }; 3506 }; 3507 3508 q6asm: service@7 { 3509 compatible = "qcom,q6asm"; 3510 reg = <APR_SVC_ASM>; 3511 q6asmdai: dais { 3512 compatible = "qcom,q6asm-dais"; 3513 #address-cells = <1>; 3514 #size-cells = <0>; 3515 #sound-dai-cells = <1>; 3516 iommus = <&lpass_q6_smmu 1>; 3517 }; 3518 }; 3519 3520 q6adm: service@8 { 3521 compatible = "qcom,q6adm"; 3522 reg = <APR_SVC_ADM>; 3523 q6routing: routing { 3524 compatible = "qcom,q6adm-routing"; 3525 #sound-dai-cells = <0>; 3526 }; 3527 }; 3528 }; 3529 }; 3530 }; 3531 3532 apcs_glb: mailbox@9820000 { 3533 compatible = "qcom,msm8996-apcs-hmss-global"; 3534 reg = <0x09820000 0x1000>; 3535 3536 #mbox-cells = <1>; 3537 #clock-cells = <0>; 3538 }; 3539 3540 timer@9840000 { 3541 #address-cells = <1>; 3542 #size-cells = <1>; 3543 ranges; 3544 compatible = "arm,armv7-timer-mem"; 3545 reg = <0x09840000 0x1000>; 3546 clock-frequency = <19200000>; 3547 3548 frame@9850000 { 3549 frame-number = <0>; 3550 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3551 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3552 reg = <0x09850000 0x1000>, 3553 <0x09860000 0x1000>; 3554 }; 3555 3556 frame@9870000 { 3557 frame-number = <1>; 3558 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3559 reg = <0x09870000 0x1000>; 3560 status = "disabled"; 3561 }; 3562 3563 frame@9880000 { 3564 frame-number = <2>; 3565 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3566 reg = <0x09880000 0x1000>; 3567 status = "disabled"; 3568 }; 3569 3570 frame@9890000 { 3571 frame-number = <3>; 3572 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3573 reg = <0x09890000 0x1000>; 3574 status = "disabled"; 3575 }; 3576 3577 frame@98a0000 { 3578 frame-number = <4>; 3579 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3580 reg = <0x098a0000 0x1000>; 3581 status = "disabled"; 3582 }; 3583 3584 frame@98b0000 { 3585 frame-number = <5>; 3586 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3587 reg = <0x098b0000 0x1000>; 3588 status = "disabled"; 3589 }; 3590 3591 frame@98c0000 { 3592 frame-number = <6>; 3593 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3594 reg = <0x098c0000 0x1000>; 3595 status = "disabled"; 3596 }; 3597 }; 3598 3599 saw3: syscon@9a10000 { 3600 compatible = "syscon"; 3601 reg = <0x09a10000 0x1000>; 3602 }; 3603 3604 cbf: clock-controller@9a11000 { 3605 compatible = "qcom,msm8996-cbf"; 3606 reg = <0x09a11000 0x10000>; 3607 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3608 #clock-cells = <0>; 3609 #interconnect-cells = <1>; 3610 }; 3611 3612 intc: interrupt-controller@9bc0000 { 3613 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3614 #interrupt-cells = <3>; 3615 interrupt-controller; 3616 #redistributor-regions = <1>; 3617 redistributor-stride = <0x0 0x40000>; 3618 reg = <0x09bc0000 0x10000>, 3619 <0x09c00000 0x100000>; 3620 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3621 }; 3622 }; 3623 3624 sound: sound { 3625 }; 3626 3627 thermal-zones { 3628 cpu0-thermal { 3629 polling-delay-passive = <250>; 3630 polling-delay = <1000>; 3631 3632 thermal-sensors = <&tsens0 3>; 3633 3634 trips { 3635 cpu0_alert0: trip-point0 { 3636 temperature = <75000>; 3637 hysteresis = <2000>; 3638 type = "passive"; 3639 }; 3640 3641 cpu0_crit: cpu-crit { 3642 temperature = <110000>; 3643 hysteresis = <2000>; 3644 type = "critical"; 3645 }; 3646 }; 3647 }; 3648 3649 cpu1-thermal { 3650 polling-delay-passive = <250>; 3651 polling-delay = <1000>; 3652 3653 thermal-sensors = <&tsens0 5>; 3654 3655 trips { 3656 cpu1_alert0: trip-point0 { 3657 temperature = <75000>; 3658 hysteresis = <2000>; 3659 type = "passive"; 3660 }; 3661 3662 cpu1_crit: cpu-crit { 3663 temperature = <110000>; 3664 hysteresis = <2000>; 3665 type = "critical"; 3666 }; 3667 }; 3668 }; 3669 3670 cpu2-thermal { 3671 polling-delay-passive = <250>; 3672 polling-delay = <1000>; 3673 3674 thermal-sensors = <&tsens0 8>; 3675 3676 trips { 3677 cpu2_alert0: trip-point0 { 3678 temperature = <75000>; 3679 hysteresis = <2000>; 3680 type = "passive"; 3681 }; 3682 3683 cpu2_crit: cpu-crit { 3684 temperature = <110000>; 3685 hysteresis = <2000>; 3686 type = "critical"; 3687 }; 3688 }; 3689 }; 3690 3691 cpu3-thermal { 3692 polling-delay-passive = <250>; 3693 polling-delay = <1000>; 3694 3695 thermal-sensors = <&tsens0 10>; 3696 3697 trips { 3698 cpu3_alert0: trip-point0 { 3699 temperature = <75000>; 3700 hysteresis = <2000>; 3701 type = "passive"; 3702 }; 3703 3704 cpu3_crit: cpu-crit { 3705 temperature = <110000>; 3706 hysteresis = <2000>; 3707 type = "critical"; 3708 }; 3709 }; 3710 }; 3711 3712 gpu-top-thermal { 3713 polling-delay-passive = <250>; 3714 polling-delay = <1000>; 3715 3716 thermal-sensors = <&tsens1 6>; 3717 3718 trips { 3719 gpu1_alert0: trip-point0 { 3720 temperature = <90000>; 3721 hysteresis = <2000>; 3722 type = "passive"; 3723 }; 3724 }; 3725 3726 cooling-maps { 3727 map0 { 3728 trip = <&gpu1_alert0>; 3729 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3730 }; 3731 }; 3732 }; 3733 3734 gpu-bottom-thermal { 3735 polling-delay-passive = <250>; 3736 polling-delay = <1000>; 3737 3738 thermal-sensors = <&tsens1 7>; 3739 3740 trips { 3741 gpu2_alert0: trip-point0 { 3742 temperature = <90000>; 3743 hysteresis = <2000>; 3744 type = "passive"; 3745 }; 3746 }; 3747 3748 cooling-maps { 3749 map0 { 3750 trip = <&gpu2_alert0>; 3751 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3752 }; 3753 }; 3754 }; 3755 3756 m4m-thermal { 3757 polling-delay-passive = <250>; 3758 polling-delay = <1000>; 3759 3760 thermal-sensors = <&tsens0 1>; 3761 3762 trips { 3763 m4m_alert0: trip-point0 { 3764 temperature = <90000>; 3765 hysteresis = <2000>; 3766 type = "hot"; 3767 }; 3768 }; 3769 }; 3770 3771 l3-or-venus-thermal { 3772 polling-delay-passive = <250>; 3773 polling-delay = <1000>; 3774 3775 thermal-sensors = <&tsens0 2>; 3776 3777 trips { 3778 l3_or_venus_alert0: trip-point0 { 3779 temperature = <90000>; 3780 hysteresis = <2000>; 3781 type = "hot"; 3782 }; 3783 }; 3784 }; 3785 3786 cluster0-l2-thermal { 3787 polling-delay-passive = <250>; 3788 polling-delay = <1000>; 3789 3790 thermal-sensors = <&tsens0 7>; 3791 3792 trips { 3793 cluster0_l2_alert0: trip-point0 { 3794 temperature = <90000>; 3795 hysteresis = <2000>; 3796 type = "hot"; 3797 }; 3798 }; 3799 }; 3800 3801 cluster1-l2-thermal { 3802 polling-delay-passive = <250>; 3803 polling-delay = <1000>; 3804 3805 thermal-sensors = <&tsens0 12>; 3806 3807 trips { 3808 cluster1_l2_alert0: trip-point0 { 3809 temperature = <90000>; 3810 hysteresis = <2000>; 3811 type = "hot"; 3812 }; 3813 }; 3814 }; 3815 3816 camera-thermal { 3817 polling-delay-passive = <250>; 3818 polling-delay = <1000>; 3819 3820 thermal-sensors = <&tsens1 1>; 3821 3822 trips { 3823 camera_alert0: trip-point0 { 3824 temperature = <90000>; 3825 hysteresis = <2000>; 3826 type = "hot"; 3827 }; 3828 }; 3829 }; 3830 3831 q6-dsp-thermal { 3832 polling-delay-passive = <250>; 3833 polling-delay = <1000>; 3834 3835 thermal-sensors = <&tsens1 2>; 3836 3837 trips { 3838 q6_dsp_alert0: trip-point0 { 3839 temperature = <90000>; 3840 hysteresis = <2000>; 3841 type = "hot"; 3842 }; 3843 }; 3844 }; 3845 3846 mem-thermal { 3847 polling-delay-passive = <250>; 3848 polling-delay = <1000>; 3849 3850 thermal-sensors = <&tsens1 3>; 3851 3852 trips { 3853 mem_alert0: trip-point0 { 3854 temperature = <90000>; 3855 hysteresis = <2000>; 3856 type = "hot"; 3857 }; 3858 }; 3859 }; 3860 3861 modemtx-thermal { 3862 polling-delay-passive = <250>; 3863 polling-delay = <1000>; 3864 3865 thermal-sensors = <&tsens1 4>; 3866 3867 trips { 3868 modemtx_alert0: trip-point0 { 3869 temperature = <90000>; 3870 hysteresis = <2000>; 3871 type = "hot"; 3872 }; 3873 }; 3874 }; 3875 }; 3876 3877 timer { 3878 compatible = "arm,armv8-timer"; 3879 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3880 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3881 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3882 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3883 }; 3884}; 3885