1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8996.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/interconnect/qcom,msm8996.h> 11#include <dt-bindings/interconnect/qcom,msm8996-cbf.h> 12#include <dt-bindings/firmware/qcom,scm.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,apr.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <19200000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32764>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "qcom,kryo"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 cpu-idle-states = <&CPU_SLEEP_0>; 52 capacity-dmips-mhz = <1024>; 53 clocks = <&kryocc 0>; 54 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 55 operating-points-v2 = <&cluster0_opp>; 56 #cooling-cells = <2>; 57 next-level-cache = <&L2_0>; 58 L2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 }; 63 }; 64 65 CPU1: cpu@1 { 66 device_type = "cpu"; 67 compatible = "qcom,kryo"; 68 reg = <0x0 0x1>; 69 enable-method = "psci"; 70 cpu-idle-states = <&CPU_SLEEP_0>; 71 capacity-dmips-mhz = <1024>; 72 clocks = <&kryocc 0>; 73 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 74 operating-points-v2 = <&cluster0_opp>; 75 #cooling-cells = <2>; 76 next-level-cache = <&L2_0>; 77 }; 78 79 CPU2: cpu@100 { 80 device_type = "cpu"; 81 compatible = "qcom,kryo"; 82 reg = <0x0 0x100>; 83 enable-method = "psci"; 84 cpu-idle-states = <&CPU_SLEEP_0>; 85 capacity-dmips-mhz = <1024>; 86 clocks = <&kryocc 1>; 87 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 88 operating-points-v2 = <&cluster1_opp>; 89 #cooling-cells = <2>; 90 next-level-cache = <&L2_1>; 91 L2_1: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 cache-unified; 95 }; 96 }; 97 98 CPU3: cpu@101 { 99 device_type = "cpu"; 100 compatible = "qcom,kryo"; 101 reg = <0x0 0x101>; 102 enable-method = "psci"; 103 cpu-idle-states = <&CPU_SLEEP_0>; 104 capacity-dmips-mhz = <1024>; 105 clocks = <&kryocc 1>; 106 interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; 107 operating-points-v2 = <&cluster1_opp>; 108 #cooling-cells = <2>; 109 next-level-cache = <&L2_1>; 110 }; 111 112 cpu-map { 113 cluster0 { 114 core0 { 115 cpu = <&CPU0>; 116 }; 117 118 core1 { 119 cpu = <&CPU1>; 120 }; 121 }; 122 123 cluster1 { 124 core0 { 125 cpu = <&CPU2>; 126 }; 127 128 core1 { 129 cpu = <&CPU3>; 130 }; 131 }; 132 }; 133 134 idle-states { 135 entry-method = "psci"; 136 137 CPU_SLEEP_0: cpu-sleep-0 { 138 compatible = "arm,idle-state"; 139 idle-state-name = "standalone-power-collapse"; 140 arm,psci-suspend-param = <0x00000004>; 141 entry-latency-us = <130>; 142 exit-latency-us = <80>; 143 min-residency-us = <300>; 144 }; 145 }; 146 }; 147 148 cluster0_opp: opp-table-cluster0 { 149 compatible = "operating-points-v2-kryo-cpu"; 150 nvmem-cells = <&speedbin_efuse>; 151 opp-shared; 152 153 /* Nominal fmax for now */ 154 opp-307200000 { 155 opp-hz = /bits/ 64 <307200000>; 156 opp-supported-hw = <0xf>; 157 clock-latency-ns = <200000>; 158 opp-peak-kBps = <307200>; 159 }; 160 opp-422400000 { 161 opp-hz = /bits/ 64 <422400000>; 162 opp-supported-hw = <0xf>; 163 clock-latency-ns = <200000>; 164 opp-peak-kBps = <307200>; 165 }; 166 opp-480000000 { 167 opp-hz = /bits/ 64 <480000000>; 168 opp-supported-hw = <0xf>; 169 clock-latency-ns = <200000>; 170 opp-peak-kBps = <307200>; 171 }; 172 opp-556800000 { 173 opp-hz = /bits/ 64 <556800000>; 174 opp-supported-hw = <0xf>; 175 clock-latency-ns = <200000>; 176 opp-peak-kBps = <307200>; 177 }; 178 opp-652800000 { 179 opp-hz = /bits/ 64 <652800000>; 180 opp-supported-hw = <0xf>; 181 clock-latency-ns = <200000>; 182 opp-peak-kBps = <384000>; 183 }; 184 opp-729600000 { 185 opp-hz = /bits/ 64 <729600000>; 186 opp-supported-hw = <0xf>; 187 clock-latency-ns = <200000>; 188 opp-peak-kBps = <460800>; 189 }; 190 opp-844800000 { 191 opp-hz = /bits/ 64 <844800000>; 192 opp-supported-hw = <0xf>; 193 clock-latency-ns = <200000>; 194 opp-peak-kBps = <537600>; 195 }; 196 opp-960000000 { 197 opp-hz = /bits/ 64 <960000000>; 198 opp-supported-hw = <0xf>; 199 clock-latency-ns = <200000>; 200 opp-peak-kBps = <672000>; 201 }; 202 opp-1036800000 { 203 opp-hz = /bits/ 64 <1036800000>; 204 opp-supported-hw = <0xf>; 205 clock-latency-ns = <200000>; 206 opp-peak-kBps = <672000>; 207 }; 208 opp-1113600000 { 209 opp-hz = /bits/ 64 <1113600000>; 210 opp-supported-hw = <0xf>; 211 clock-latency-ns = <200000>; 212 opp-peak-kBps = <825600>; 213 }; 214 opp-1190400000 { 215 opp-hz = /bits/ 64 <1190400000>; 216 opp-supported-hw = <0xf>; 217 clock-latency-ns = <200000>; 218 opp-peak-kBps = <825600>; 219 }; 220 opp-1228800000 { 221 opp-hz = /bits/ 64 <1228800000>; 222 opp-supported-hw = <0xf>; 223 clock-latency-ns = <200000>; 224 opp-peak-kBps = <902400>; 225 }; 226 opp-1324800000 { 227 opp-hz = /bits/ 64 <1324800000>; 228 opp-supported-hw = <0xd>; 229 clock-latency-ns = <200000>; 230 opp-peak-kBps = <1056000>; 231 }; 232 opp-1363200000 { 233 opp-hz = /bits/ 64 <1363200000>; 234 opp-supported-hw = <0x2>; 235 clock-latency-ns = <200000>; 236 opp-peak-kBps = <1132800>; 237 }; 238 opp-1401600000 { 239 opp-hz = /bits/ 64 <1401600000>; 240 opp-supported-hw = <0xd>; 241 clock-latency-ns = <200000>; 242 opp-peak-kBps = <1132800>; 243 }; 244 opp-1478400000 { 245 opp-hz = /bits/ 64 <1478400000>; 246 opp-supported-hw = <0x9>; 247 clock-latency-ns = <200000>; 248 opp-peak-kBps = <1190400>; 249 }; 250 opp-1497600000 { 251 opp-hz = /bits/ 64 <1497600000>; 252 opp-supported-hw = <0x04>; 253 clock-latency-ns = <200000>; 254 opp-peak-kBps = <1305600>; 255 }; 256 opp-1593600000 { 257 opp-hz = /bits/ 64 <1593600000>; 258 opp-supported-hw = <0x9>; 259 clock-latency-ns = <200000>; 260 opp-peak-kBps = <1382400>; 261 }; 262 }; 263 264 cluster1_opp: opp-table-cluster1 { 265 compatible = "operating-points-v2-kryo-cpu"; 266 nvmem-cells = <&speedbin_efuse>; 267 opp-shared; 268 269 /* Nominal fmax for now */ 270 opp-307200000 { 271 opp-hz = /bits/ 64 <307200000>; 272 opp-supported-hw = <0xf>; 273 clock-latency-ns = <200000>; 274 opp-peak-kBps = <307200>; 275 }; 276 opp-403200000 { 277 opp-hz = /bits/ 64 <403200000>; 278 opp-supported-hw = <0xf>; 279 clock-latency-ns = <200000>; 280 opp-peak-kBps = <307200>; 281 }; 282 opp-480000000 { 283 opp-hz = /bits/ 64 <480000000>; 284 opp-supported-hw = <0xf>; 285 clock-latency-ns = <200000>; 286 opp-peak-kBps = <307200>; 287 }; 288 opp-556800000 { 289 opp-hz = /bits/ 64 <556800000>; 290 opp-supported-hw = <0xf>; 291 clock-latency-ns = <200000>; 292 opp-peak-kBps = <307200>; 293 }; 294 opp-652800000 { 295 opp-hz = /bits/ 64 <652800000>; 296 opp-supported-hw = <0xf>; 297 clock-latency-ns = <200000>; 298 opp-peak-kBps = <307200>; 299 }; 300 opp-729600000 { 301 opp-hz = /bits/ 64 <729600000>; 302 opp-supported-hw = <0xf>; 303 clock-latency-ns = <200000>; 304 opp-peak-kBps = <307200>; 305 }; 306 opp-806400000 { 307 opp-hz = /bits/ 64 <806400000>; 308 opp-supported-hw = <0xf>; 309 clock-latency-ns = <200000>; 310 opp-peak-kBps = <384000>; 311 }; 312 opp-883200000 { 313 opp-hz = /bits/ 64 <883200000>; 314 opp-supported-hw = <0xf>; 315 clock-latency-ns = <200000>; 316 opp-peak-kBps = <460800>; 317 }; 318 opp-940800000 { 319 opp-hz = /bits/ 64 <940800000>; 320 opp-supported-hw = <0xf>; 321 clock-latency-ns = <200000>; 322 opp-peak-kBps = <537600>; 323 }; 324 opp-1036800000 { 325 opp-hz = /bits/ 64 <1036800000>; 326 opp-supported-hw = <0xf>; 327 clock-latency-ns = <200000>; 328 opp-peak-kBps = <595200>; 329 }; 330 opp-1113600000 { 331 opp-hz = /bits/ 64 <1113600000>; 332 opp-supported-hw = <0xf>; 333 clock-latency-ns = <200000>; 334 opp-peak-kBps = <672000>; 335 }; 336 opp-1190400000 { 337 opp-hz = /bits/ 64 <1190400000>; 338 opp-supported-hw = <0xf>; 339 clock-latency-ns = <200000>; 340 opp-peak-kBps = <672000>; 341 }; 342 opp-1248000000 { 343 opp-hz = /bits/ 64 <1248000000>; 344 opp-supported-hw = <0xf>; 345 clock-latency-ns = <200000>; 346 opp-peak-kBps = <748800>; 347 }; 348 opp-1324800000 { 349 opp-hz = /bits/ 64 <1324800000>; 350 opp-supported-hw = <0xf>; 351 clock-latency-ns = <200000>; 352 opp-peak-kBps = <825600>; 353 }; 354 opp-1401600000 { 355 opp-hz = /bits/ 64 <1401600000>; 356 opp-supported-hw = <0xf>; 357 clock-latency-ns = <200000>; 358 opp-peak-kBps = <902400>; 359 }; 360 opp-1478400000 { 361 opp-hz = /bits/ 64 <1478400000>; 362 opp-supported-hw = <0xf>; 363 clock-latency-ns = <200000>; 364 opp-peak-kBps = <979200>; 365 }; 366 opp-1555200000 { 367 opp-hz = /bits/ 64 <1555200000>; 368 opp-supported-hw = <0xf>; 369 clock-latency-ns = <200000>; 370 opp-peak-kBps = <1056000>; 371 }; 372 opp-1632000000 { 373 opp-hz = /bits/ 64 <1632000000>; 374 opp-supported-hw = <0xf>; 375 clock-latency-ns = <200000>; 376 opp-peak-kBps = <1190400>; 377 }; 378 opp-1708800000 { 379 opp-hz = /bits/ 64 <1708800000>; 380 opp-supported-hw = <0xf>; 381 clock-latency-ns = <200000>; 382 opp-peak-kBps = <1228800>; 383 }; 384 opp-1785600000 { 385 opp-hz = /bits/ 64 <1785600000>; 386 opp-supported-hw = <0xf>; 387 clock-latency-ns = <200000>; 388 opp-peak-kBps = <1305600>; 389 }; 390 opp-1804800000 { 391 opp-hz = /bits/ 64 <1804800000>; 392 opp-supported-hw = <0xe>; 393 clock-latency-ns = <200000>; 394 opp-peak-kBps = <1305600>; 395 }; 396 opp-1824000000 { 397 opp-hz = /bits/ 64 <1824000000>; 398 opp-supported-hw = <0x1>; 399 clock-latency-ns = <200000>; 400 opp-peak-kBps = <1382400>; 401 }; 402 opp-1900800000 { 403 opp-hz = /bits/ 64 <1900800000>; 404 opp-supported-hw = <0x4>; 405 clock-latency-ns = <200000>; 406 opp-peak-kBps = <1305600>; 407 }; 408 opp-1920000000 { 409 opp-hz = /bits/ 64 <1920000000>; 410 opp-supported-hw = <0x1>; 411 clock-latency-ns = <200000>; 412 opp-peak-kBps = <1459200>; 413 }; 414 opp-1996800000 { 415 opp-hz = /bits/ 64 <1996800000>; 416 opp-supported-hw = <0x1>; 417 clock-latency-ns = <200000>; 418 opp-peak-kBps = <1593600>; 419 }; 420 opp-2073600000 { 421 opp-hz = /bits/ 64 <2073600000>; 422 opp-supported-hw = <0x1>; 423 clock-latency-ns = <200000>; 424 opp-peak-kBps = <1593600>; 425 }; 426 opp-2150400000 { 427 opp-hz = /bits/ 64 <2150400000>; 428 opp-supported-hw = <0x1>; 429 clock-latency-ns = <200000>; 430 opp-peak-kBps = <1593600>; 431 }; 432 }; 433 434 firmware { 435 scm { 436 compatible = "qcom,scm-msm8996", "qcom,scm"; 437 qcom,dload-mode = <&tcsr_2 0x13000>; 438 }; 439 }; 440 441 memory@80000000 { 442 device_type = "memory"; 443 /* We expect the bootloader to fill in the reg */ 444 reg = <0x0 0x80000000 0x0 0x0>; 445 }; 446 447 etm { 448 compatible = "qcom,coresight-remote-etm"; 449 450 out-ports { 451 port { 452 modem_etm_out_funnel_in2: endpoint { 453 remote-endpoint = 454 <&funnel_in2_in_modem_etm>; 455 }; 456 }; 457 }; 458 }; 459 460 mpm: interrupt-controller { 461 compatible = "qcom,mpm"; 462 qcom,rpm-msg-ram = <&apss_mpm>; 463 interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>; 464 mboxes = <&apcs_glb 1>; 465 interrupt-controller; 466 #interrupt-cells = <2>; 467 #power-domain-cells = <0>; 468 interrupt-parent = <&intc>; 469 qcom,mpm-pin-count = <96>; 470 qcom,mpm-pin-map = <2 184>, /* TSENS1 upper_lower_int */ 471 <52 243>, /* DWC3_PRI ss_phy_irq */ 472 <79 347>, /* DWC3_PRI hs_phy_irq */ 473 <80 352>, /* DWC3_SEC hs_phy_irq */ 474 <81 347>, /* QUSB2_PHY_PRI DP+DM */ 475 <82 352>, /* QUSB2_PHY_SEC DP+DM */ 476 <87 326>; /* SPMI */ 477 }; 478 479 psci { 480 compatible = "arm,psci-1.0"; 481 method = "smc"; 482 }; 483 484 rpm: remoteproc { 485 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc"; 486 487 glink-edge { 488 compatible = "qcom,glink-rpm"; 489 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 490 qcom,rpm-msg-ram = <&rpm_msg_ram>; 491 mboxes = <&apcs_glb 0>; 492 493 rpm_requests: rpm-requests { 494 compatible = "qcom,rpm-msm8996"; 495 qcom,glink-channels = "rpm_requests"; 496 497 rpmcc: clock-controller { 498 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; 499 #clock-cells = <1>; 500 clocks = <&xo_board>; 501 clock-names = "xo"; 502 }; 503 504 rpmpd: power-controller { 505 compatible = "qcom,msm8996-rpmpd"; 506 #power-domain-cells = <1>; 507 operating-points-v2 = <&rpmpd_opp_table>; 508 509 rpmpd_opp_table: opp-table { 510 compatible = "operating-points-v2"; 511 512 rpmpd_opp1: opp1 { 513 opp-level = <1>; 514 }; 515 516 rpmpd_opp2: opp2 { 517 opp-level = <2>; 518 }; 519 520 rpmpd_opp3: opp3 { 521 opp-level = <3>; 522 }; 523 524 rpmpd_opp4: opp4 { 525 opp-level = <4>; 526 }; 527 528 rpmpd_opp5: opp5 { 529 opp-level = <5>; 530 }; 531 532 rpmpd_opp6: opp6 { 533 opp-level = <6>; 534 }; 535 }; 536 }; 537 }; 538 }; 539 }; 540 541 reserved-memory { 542 #address-cells = <2>; 543 #size-cells = <2>; 544 ranges; 545 546 hyp_mem: memory@85800000 { 547 reg = <0x0 0x85800000 0x0 0x600000>; 548 no-map; 549 }; 550 551 xbl_mem: memory@85e00000 { 552 reg = <0x0 0x85e00000 0x0 0x200000>; 553 no-map; 554 }; 555 556 smem_mem: smem-mem@86000000 { 557 reg = <0x0 0x86000000 0x0 0x200000>; 558 no-map; 559 }; 560 561 tz_mem: memory@86200000 { 562 reg = <0x0 0x86200000 0x0 0x2600000>; 563 no-map; 564 }; 565 566 rmtfs_mem: rmtfs { 567 compatible = "qcom,rmtfs-mem"; 568 569 size = <0x0 0x200000>; 570 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; 571 no-map; 572 573 qcom,client-id = <1>; 574 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 575 }; 576 577 mpss_mem: mpss@88800000 { 578 reg = <0x0 0x88800000 0x0 0x6200000>; 579 no-map; 580 }; 581 582 adsp_mem: adsp@8ea00000 { 583 reg = <0x0 0x8ea00000 0x0 0x1b00000>; 584 no-map; 585 }; 586 587 slpi_mem: slpi@90500000 { 588 reg = <0x0 0x90500000 0x0 0xa00000>; 589 no-map; 590 }; 591 592 gpu_mem: gpu@90f00000 { 593 compatible = "shared-dma-pool"; 594 reg = <0x0 0x90f00000 0x0 0x100000>; 595 no-map; 596 }; 597 598 venus_mem: venus@91000000 { 599 reg = <0x0 0x91000000 0x0 0x500000>; 600 no-map; 601 }; 602 603 mba_mem: mba@91500000 { 604 reg = <0x0 0x91500000 0x0 0x200000>; 605 no-map; 606 }; 607 608 mdata_mem: mpss-metadata { 609 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 610 size = <0x0 0x4000>; 611 no-map; 612 }; 613 }; 614 615 smem { 616 compatible = "qcom,smem"; 617 memory-region = <&smem_mem>; 618 hwlocks = <&tcsr_mutex 3>; 619 }; 620 621 smp2p-adsp { 622 compatible = "qcom,smp2p"; 623 qcom,smem = <443>, <429>; 624 625 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 626 627 mboxes = <&apcs_glb 10>; 628 629 qcom,local-pid = <0>; 630 qcom,remote-pid = <2>; 631 632 adsp_smp2p_out: master-kernel { 633 qcom,entry-name = "master-kernel"; 634 #qcom,smem-state-cells = <1>; 635 }; 636 637 adsp_smp2p_in: slave-kernel { 638 qcom,entry-name = "slave-kernel"; 639 640 interrupt-controller; 641 #interrupt-cells = <2>; 642 }; 643 }; 644 645 smp2p-mpss { 646 compatible = "qcom,smp2p"; 647 qcom,smem = <435>, <428>; 648 649 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 650 651 mboxes = <&apcs_glb 14>; 652 653 qcom,local-pid = <0>; 654 qcom,remote-pid = <1>; 655 656 mpss_smp2p_out: master-kernel { 657 qcom,entry-name = "master-kernel"; 658 #qcom,smem-state-cells = <1>; 659 }; 660 661 mpss_smp2p_in: slave-kernel { 662 qcom,entry-name = "slave-kernel"; 663 664 interrupt-controller; 665 #interrupt-cells = <2>; 666 }; 667 }; 668 669 smp2p-slpi { 670 compatible = "qcom,smp2p"; 671 qcom,smem = <481>, <430>; 672 673 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 674 675 mboxes = <&apcs_glb 26>; 676 677 qcom,local-pid = <0>; 678 qcom,remote-pid = <3>; 679 680 slpi_smp2p_out: master-kernel { 681 qcom,entry-name = "master-kernel"; 682 #qcom,smem-state-cells = <1>; 683 }; 684 685 slpi_smp2p_in: slave-kernel { 686 qcom,entry-name = "slave-kernel"; 687 688 interrupt-controller; 689 #interrupt-cells = <2>; 690 }; 691 }; 692 693 soc: soc@0 { 694 #address-cells = <1>; 695 #size-cells = <1>; 696 ranges = <0 0 0 0xffffffff>; 697 compatible = "simple-bus"; 698 699 pcie_phy: phy-wrapper@34000 { 700 compatible = "qcom,msm8996-qmp-pcie-phy"; 701 reg = <0x00034000 0x488>; 702 #address-cells = <1>; 703 #size-cells = <1>; 704 ranges = <0x0 0x00034000 0x4000>; 705 706 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 707 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 708 <&gcc GCC_PCIE_CLKREF_CLK>; 709 clock-names = "aux", "cfg_ahb", "ref"; 710 711 resets = <&gcc GCC_PCIE_PHY_BCR>, 712 <&gcc GCC_PCIE_PHY_COM_BCR>, 713 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 714 reset-names = "phy", "common", "cfg"; 715 716 status = "disabled"; 717 718 pciephy_0: phy@1000 { 719 reg = <0x1000 0x130>, 720 <0x1200 0x200>, 721 <0x1400 0x1dc>; 722 723 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 724 clock-names = "pipe0"; 725 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 726 reset-names = "lane0"; 727 728 #clock-cells = <0>; 729 clock-output-names = "pcie_0_pipe_clk_src"; 730 731 #phy-cells = <0>; 732 }; 733 734 pciephy_1: phy@2000 { 735 reg = <0x2000 0x130>, 736 <0x2200 0x200>, 737 <0x2400 0x1dc>; 738 739 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 740 clock-names = "pipe1"; 741 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 742 reset-names = "lane1"; 743 744 #clock-cells = <0>; 745 clock-output-names = "pcie_1_pipe_clk_src"; 746 747 #phy-cells = <0>; 748 }; 749 750 pciephy_2: phy@3000 { 751 reg = <0x3000 0x130>, 752 <0x3200 0x200>, 753 <0x3400 0x1dc>; 754 755 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 756 clock-names = "pipe2"; 757 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 758 reset-names = "lane2"; 759 760 #clock-cells = <0>; 761 clock-output-names = "pcie_2_pipe_clk_src"; 762 763 #phy-cells = <0>; 764 }; 765 }; 766 767 rpm_msg_ram: sram@68000 { 768 compatible = "qcom,rpm-msg-ram", "mmio-sram"; 769 reg = <0x00068000 0x6000>; 770 #address-cells = <1>; 771 #size-cells = <1>; 772 ranges = <0 0x00068000 0x7000>; 773 774 apss_mpm: sram@1b8 { 775 reg = <0x1b8 0x48>; 776 }; 777 }; 778 779 qfprom@74000 { 780 compatible = "qcom,msm8996-qfprom", "qcom,qfprom"; 781 reg = <0x00074000 0x8ff>; 782 #address-cells = <1>; 783 #size-cells = <1>; 784 785 qusb2p_hstx_trim: hstx_trim@24e { 786 reg = <0x24e 0x2>; 787 bits = <5 4>; 788 }; 789 790 qusb2s_hstx_trim: hstx_trim@24f { 791 reg = <0x24f 0x1>; 792 bits = <1 4>; 793 }; 794 795 speedbin_efuse: speedbin@133 { 796 reg = <0x133 0x1>; 797 bits = <5 3>; 798 }; 799 }; 800 801 rng: rng@83000 { 802 compatible = "qcom,prng-ee"; 803 reg = <0x00083000 0x1000>; 804 clocks = <&gcc GCC_PRNG_AHB_CLK>; 805 clock-names = "core"; 806 }; 807 808 gcc: clock-controller@300000 { 809 compatible = "qcom,gcc-msm8996"; 810 #clock-cells = <1>; 811 #reset-cells = <1>; 812 #power-domain-cells = <1>; 813 reg = <0x00300000 0x90000>; 814 815 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 816 <&rpmcc RPM_SMD_LN_BB_CLK>, 817 <&sleep_clk>, 818 <&pciephy_0>, 819 <&pciephy_1>, 820 <&pciephy_2>, 821 <&usb3phy>, 822 <&ufsphy 0>, 823 <&ufsphy 1>, 824 <&ufsphy 2>; 825 clock-names = "cxo", 826 "cxo2", 827 "sleep_clk", 828 "pcie_0_pipe_clk_src", 829 "pcie_1_pipe_clk_src", 830 "pcie_2_pipe_clk_src", 831 "usb3_phy_pipe_clk_src", 832 "ufs_rx_symbol_0_clk_src", 833 "ufs_rx_symbol_1_clk_src", 834 "ufs_tx_symbol_0_clk_src"; 835 }; 836 837 bimc: interconnect@408000 { 838 compatible = "qcom,msm8996-bimc"; 839 reg = <0x00408000 0x5a000>; 840 #interconnect-cells = <1>; 841 clock-names = "bus", "bus_a"; 842 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 843 <&rpmcc RPM_SMD_BIMC_A_CLK>; 844 }; 845 846 tsens0: thermal-sensor@4a9000 { 847 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 848 reg = <0x004a9000 0x1000>, /* TM */ 849 <0x004a8000 0x1000>; /* SROT */ 850 #qcom,sensors = <13>; 851 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 853 interrupt-names = "uplow", "critical"; 854 #thermal-sensor-cells = <1>; 855 }; 856 857 tsens1: thermal-sensor@4ad000 { 858 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; 859 reg = <0x004ad000 0x1000>, /* TM */ 860 <0x004ac000 0x1000>; /* SROT */ 861 #qcom,sensors = <8>; 862 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, 863 <&intc GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 864 interrupt-names = "uplow", "critical"; 865 #thermal-sensor-cells = <1>; 866 }; 867 868 cryptobam: dma-controller@644000 { 869 compatible = "qcom,bam-v1.7.0"; 870 reg = <0x00644000 0x24000>; 871 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&gcc GCC_CE1_CLK>; 873 clock-names = "bam_clk"; 874 #dma-cells = <1>; 875 qcom,ee = <0>; 876 qcom,controlled-remotely; 877 }; 878 879 crypto: crypto@67a000 { 880 compatible = "qcom,crypto-v5.4"; 881 reg = <0x0067a000 0x6000>; 882 clocks = <&gcc GCC_CE1_AHB_CLK>, 883 <&gcc GCC_CE1_AXI_CLK>, 884 <&gcc GCC_CE1_CLK>; 885 clock-names = "iface", "bus", "core"; 886 dmas = <&cryptobam 6>, <&cryptobam 7>; 887 dma-names = "rx", "tx"; 888 }; 889 890 cnoc: interconnect@500000 { 891 compatible = "qcom,msm8996-cnoc"; 892 reg = <0x00500000 0x1000>; 893 #interconnect-cells = <1>; 894 clock-names = "bus", "bus_a"; 895 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 896 <&rpmcc RPM_SMD_CNOC_A_CLK>; 897 }; 898 899 snoc: interconnect@524000 { 900 compatible = "qcom,msm8996-snoc"; 901 reg = <0x00524000 0x1c000>; 902 #interconnect-cells = <1>; 903 clock-names = "bus", "bus_a"; 904 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 905 <&rpmcc RPM_SMD_SNOC_A_CLK>; 906 }; 907 908 a0noc: interconnect@543000 { 909 compatible = "qcom,msm8996-a0noc"; 910 reg = <0x00543000 0x6000>; 911 #interconnect-cells = <1>; 912 clock-names = "aggre0_snoc_axi", 913 "aggre0_cnoc_ahb", 914 "aggre0_noc_mpu_cfg"; 915 clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>, 916 <&gcc GCC_AGGRE0_CNOC_AHB_CLK>, 917 <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>; 918 power-domains = <&gcc AGGRE0_NOC_GDSC>; 919 }; 920 921 a1noc: interconnect@562000 { 922 compatible = "qcom,msm8996-a1noc"; 923 reg = <0x00562000 0x5000>; 924 #interconnect-cells = <1>; 925 clock-names = "bus", "bus_a"; 926 clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>, 927 <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>; 928 }; 929 930 a2noc: interconnect@583000 { 931 compatible = "qcom,msm8996-a2noc"; 932 reg = <0x00583000 0x7000>; 933 #interconnect-cells = <1>; 934 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi"; 935 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 936 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 937 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 938 <&gcc GCC_UFS_AXI_CLK>; 939 }; 940 941 mnoc: interconnect@5a4000 { 942 compatible = "qcom,msm8996-mnoc"; 943 reg = <0x005a4000 0x1c000>; 944 #interconnect-cells = <1>; 945 clock-names = "bus", "bus_a", "iface"; 946 clocks = <&rpmcc RPM_SMD_MMAXI_CLK>, 947 <&rpmcc RPM_SMD_MMAXI_A_CLK>, 948 <&mmcc AHB_CLK_SRC>; 949 }; 950 951 pnoc: interconnect@5c0000 { 952 compatible = "qcom,msm8996-pnoc"; 953 reg = <0x005c0000 0x3000>; 954 #interconnect-cells = <1>; 955 clock-names = "bus", "bus_a"; 956 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 957 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 958 }; 959 960 tcsr_mutex: hwlock@740000 { 961 compatible = "qcom,tcsr-mutex"; 962 reg = <0x00740000 0x20000>; 963 #hwlock-cells = <1>; 964 }; 965 966 tcsr_1: syscon@760000 { 967 compatible = "qcom,tcsr-msm8996", "syscon"; 968 reg = <0x00760000 0x20000>; 969 }; 970 971 tcsr_2: syscon@7a0000 { 972 compatible = "qcom,tcsr-msm8996", "syscon"; 973 reg = <0x007a0000 0x18000>; 974 }; 975 976 mmcc: clock-controller@8c0000 { 977 compatible = "qcom,mmcc-msm8996"; 978 #clock-cells = <1>; 979 #reset-cells = <1>; 980 #power-domain-cells = <1>; 981 reg = <0x008c0000 0x40000>; 982 clocks = <&xo_board>, 983 <&gcc GPLL0>, 984 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>, 985 <&mdss_dsi0_phy 1>, 986 <&mdss_dsi0_phy 0>, 987 <&mdss_dsi1_phy 1>, 988 <&mdss_dsi1_phy 0>, 989 <&mdss_hdmi_phy>; 990 clock-names = "xo", 991 "gpll0", 992 "gcc_mmss_noc_cfg_ahb_clk", 993 "dsi0pll", 994 "dsi0pllbyte", 995 "dsi1pll", 996 "dsi1pllbyte", 997 "hdmipll"; 998 assigned-clocks = <&mmcc MMPLL9_PLL>, 999 <&mmcc MMPLL1_PLL>, 1000 <&mmcc MMPLL3_PLL>, 1001 <&mmcc MMPLL4_PLL>, 1002 <&mmcc MMPLL5_PLL>; 1003 assigned-clock-rates = <624000000>, 1004 <810000000>, 1005 <980000000>, 1006 <960000000>, 1007 <825000000>; 1008 }; 1009 1010 mdss: display-subsystem@900000 { 1011 compatible = "qcom,mdss"; 1012 1013 reg = <0x00900000 0x1000>, 1014 <0x009b0000 0x1040>, 1015 <0x009b8000 0x1040>; 1016 reg-names = "mdss_phys", 1017 "vbif_phys", 1018 "vbif_nrt_phys"; 1019 1020 power-domains = <&mmcc MDSS_GDSC>; 1021 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1022 1023 interrupt-controller; 1024 #interrupt-cells = <1>; 1025 1026 clocks = <&mmcc MDSS_AHB_CLK>, 1027 <&mmcc MDSS_MDP_CLK>; 1028 clock-names = "iface", "core"; 1029 1030 #address-cells = <1>; 1031 #size-cells = <1>; 1032 ranges; 1033 1034 status = "disabled"; 1035 1036 mdp: display-controller@901000 { 1037 compatible = "qcom,msm8996-mdp5", "qcom,mdp5"; 1038 reg = <0x00901000 0x90000>; 1039 reg-names = "mdp_phys"; 1040 1041 interrupt-parent = <&mdss>; 1042 interrupts = <0>; 1043 1044 clocks = <&mmcc MDSS_AHB_CLK>, 1045 <&mmcc MDSS_AXI_CLK>, 1046 <&mmcc MDSS_MDP_CLK>, 1047 <&mmcc SMMU_MDP_AXI_CLK>, 1048 <&mmcc MDSS_VSYNC_CLK>; 1049 clock-names = "iface", 1050 "bus", 1051 "core", 1052 "iommu", 1053 "vsync"; 1054 1055 iommus = <&mdp_smmu 0>; 1056 1057 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1058 <&mmcc MDSS_VSYNC_CLK>; 1059 assigned-clock-rates = <300000000>, 1060 <19200000>; 1061 1062 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 1063 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>, 1064 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>; 1065 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; 1066 1067 ports { 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 1071 port@0 { 1072 reg = <0>; 1073 mdp5_intf3_out: endpoint { 1074 remote-endpoint = <&mdss_hdmi_in>; 1075 }; 1076 }; 1077 1078 port@1 { 1079 reg = <1>; 1080 mdp5_intf1_out: endpoint { 1081 remote-endpoint = <&mdss_dsi0_in>; 1082 }; 1083 }; 1084 1085 port@2 { 1086 reg = <2>; 1087 mdp5_intf2_out: endpoint { 1088 remote-endpoint = <&mdss_dsi1_in>; 1089 }; 1090 }; 1091 }; 1092 }; 1093 1094 mdss_dsi0: dsi@994000 { 1095 compatible = "qcom,msm8996-dsi-ctrl", 1096 "qcom,mdss-dsi-ctrl"; 1097 reg = <0x00994000 0x400>; 1098 reg-names = "dsi_ctrl"; 1099 1100 interrupt-parent = <&mdss>; 1101 interrupts = <4>; 1102 1103 clocks = <&mmcc MDSS_MDP_CLK>, 1104 <&mmcc MDSS_BYTE0_CLK>, 1105 <&mmcc MDSS_AHB_CLK>, 1106 <&mmcc MDSS_AXI_CLK>, 1107 <&mmcc MMSS_MISC_AHB_CLK>, 1108 <&mmcc MDSS_PCLK0_CLK>, 1109 <&mmcc MDSS_ESC0_CLK>; 1110 clock-names = "mdp_core", 1111 "byte", 1112 "iface", 1113 "bus", 1114 "core_mmss", 1115 "pixel", 1116 "core"; 1117 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; 1118 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1119 1120 phys = <&mdss_dsi0_phy>; 1121 status = "disabled"; 1122 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 1126 ports { 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 1130 port@0 { 1131 reg = <0>; 1132 mdss_dsi0_in: endpoint { 1133 remote-endpoint = <&mdp5_intf1_out>; 1134 }; 1135 }; 1136 1137 port@1 { 1138 reg = <1>; 1139 mdss_dsi0_out: endpoint { 1140 }; 1141 }; 1142 }; 1143 }; 1144 1145 mdss_dsi0_phy: phy@994400 { 1146 compatible = "qcom,dsi-phy-14nm"; 1147 reg = <0x00994400 0x100>, 1148 <0x00994500 0x300>, 1149 <0x00994800 0x188>; 1150 reg-names = "dsi_phy", 1151 "dsi_phy_lane", 1152 "dsi_pll"; 1153 1154 #clock-cells = <1>; 1155 #phy-cells = <0>; 1156 1157 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1158 clock-names = "iface", "ref"; 1159 status = "disabled"; 1160 }; 1161 1162 mdss_dsi1: dsi@996000 { 1163 compatible = "qcom,msm8996-dsi-ctrl", 1164 "qcom,mdss-dsi-ctrl"; 1165 reg = <0x00996000 0x400>; 1166 reg-names = "dsi_ctrl"; 1167 1168 interrupt-parent = <&mdss>; 1169 interrupts = <5>; 1170 1171 clocks = <&mmcc MDSS_MDP_CLK>, 1172 <&mmcc MDSS_BYTE1_CLK>, 1173 <&mmcc MDSS_AHB_CLK>, 1174 <&mmcc MDSS_AXI_CLK>, 1175 <&mmcc MMSS_MISC_AHB_CLK>, 1176 <&mmcc MDSS_PCLK1_CLK>, 1177 <&mmcc MDSS_ESC1_CLK>; 1178 clock-names = "mdp_core", 1179 "byte", 1180 "iface", 1181 "bus", 1182 "core_mmss", 1183 "pixel", 1184 "core"; 1185 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; 1186 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 1187 1188 phys = <&mdss_dsi1_phy>; 1189 status = "disabled"; 1190 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 1194 ports { 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 1198 port@0 { 1199 reg = <0>; 1200 mdss_dsi1_in: endpoint { 1201 remote-endpoint = <&mdp5_intf2_out>; 1202 }; 1203 }; 1204 1205 port@1 { 1206 reg = <1>; 1207 mdss_dsi1_out: endpoint { 1208 }; 1209 }; 1210 }; 1211 }; 1212 1213 mdss_dsi1_phy: phy@996400 { 1214 compatible = "qcom,dsi-phy-14nm"; 1215 reg = <0x00996400 0x100>, 1216 <0x00996500 0x300>, 1217 <0x00996800 0x188>; 1218 reg-names = "dsi_phy", 1219 "dsi_phy_lane", 1220 "dsi_pll"; 1221 1222 #clock-cells = <1>; 1223 #phy-cells = <0>; 1224 1225 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1226 clock-names = "iface", "ref"; 1227 status = "disabled"; 1228 }; 1229 1230 mdss_hdmi: hdmi-tx@9a0000 { 1231 compatible = "qcom,hdmi-tx-8996"; 1232 reg = <0x009a0000 0x50c>, 1233 <0x00070000 0x6158>, 1234 <0x009e0000 0xfff>; 1235 reg-names = "core_physical", 1236 "qfprom_physical", 1237 "hdcp_physical"; 1238 1239 interrupt-parent = <&mdss>; 1240 interrupts = <8>; 1241 1242 clocks = <&mmcc MDSS_MDP_CLK>, 1243 <&mmcc MDSS_AHB_CLK>, 1244 <&mmcc MDSS_HDMI_CLK>, 1245 <&mmcc MDSS_HDMI_AHB_CLK>, 1246 <&mmcc MDSS_EXTPCLK_CLK>; 1247 clock-names = 1248 "mdp_core", 1249 "iface", 1250 "core", 1251 "alt_iface", 1252 "extp"; 1253 1254 phys = <&mdss_hdmi_phy>; 1255 #sound-dai-cells = <1>; 1256 1257 status = "disabled"; 1258 1259 ports { 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 1263 port@0 { 1264 reg = <0>; 1265 mdss_hdmi_in: endpoint { 1266 remote-endpoint = <&mdp5_intf3_out>; 1267 }; 1268 }; 1269 }; 1270 }; 1271 1272 mdss_hdmi_phy: phy@9a0600 { 1273 #phy-cells = <0>; 1274 compatible = "qcom,hdmi-phy-8996"; 1275 reg = <0x009a0600 0x1c4>, 1276 <0x009a0a00 0x124>, 1277 <0x009a0c00 0x124>, 1278 <0x009a0e00 0x124>, 1279 <0x009a1000 0x124>, 1280 <0x009a1200 0x0c8>; 1281 reg-names = "hdmi_pll", 1282 "hdmi_tx_l0", 1283 "hdmi_tx_l1", 1284 "hdmi_tx_l2", 1285 "hdmi_tx_l3", 1286 "hdmi_phy"; 1287 1288 clocks = <&mmcc MDSS_AHB_CLK>, 1289 <&gcc GCC_HDMI_CLKREF_CLK>, 1290 <&xo_board>; 1291 clock-names = "iface", 1292 "ref", 1293 "xo"; 1294 1295 #clock-cells = <0>; 1296 1297 status = "disabled"; 1298 }; 1299 }; 1300 1301 gpu: gpu@b00000 { 1302 compatible = "qcom,adreno-530.2", "qcom,adreno"; 1303 1304 reg = <0x00b00000 0x3f000>; 1305 reg-names = "kgsl_3d0_reg_memory"; 1306 1307 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1308 1309 clocks = <&mmcc GPU_GX_GFX3D_CLK>, 1310 <&mmcc GPU_AHB_CLK>, 1311 <&mmcc GPU_GX_RBBMTIMER_CLK>, 1312 <&gcc GCC_BIMC_GFX_CLK>, 1313 <&gcc GCC_MMSS_BIMC_GFX_CLK>; 1314 1315 clock-names = "core", 1316 "iface", 1317 "rbbmtimer", 1318 "mem", 1319 "mem_iface"; 1320 1321 interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; 1322 interconnect-names = "gfx-mem"; 1323 1324 power-domains = <&mmcc GPU_GX_GDSC>; 1325 iommus = <&adreno_smmu 0>; 1326 1327 nvmem-cells = <&speedbin_efuse>; 1328 nvmem-cell-names = "speed_bin"; 1329 1330 operating-points-v2 = <&gpu_opp_table>; 1331 1332 status = "disabled"; 1333 1334 #cooling-cells = <2>; 1335 1336 gpu_opp_table: opp-table { 1337 compatible = "operating-points-v2"; 1338 1339 /* 1340 * 624Mhz is only available on speed bins 0 and 3. 1341 * 560Mhz is only available on speed bins 0, 2 and 3. 1342 * All the rest are available on all bins of the hardware. 1343 */ 1344 opp-624000000 { 1345 opp-hz = /bits/ 64 <624000000>; 1346 opp-supported-hw = <0x09>; 1347 }; 1348 opp-560000000 { 1349 opp-hz = /bits/ 64 <560000000>; 1350 opp-supported-hw = <0x0d>; 1351 }; 1352 opp-510000000 { 1353 opp-hz = /bits/ 64 <510000000>; 1354 opp-supported-hw = <0xff>; 1355 }; 1356 opp-401800000 { 1357 opp-hz = /bits/ 64 <401800000>; 1358 opp-supported-hw = <0xff>; 1359 }; 1360 opp-315000000 { 1361 opp-hz = /bits/ 64 <315000000>; 1362 opp-supported-hw = <0xff>; 1363 }; 1364 opp-214000000 { 1365 opp-hz = /bits/ 64 <214000000>; 1366 opp-supported-hw = <0xff>; 1367 }; 1368 opp-133000000 { 1369 opp-hz = /bits/ 64 <133000000>; 1370 opp-supported-hw = <0xff>; 1371 }; 1372 }; 1373 1374 zap-shader { 1375 memory-region = <&gpu_mem>; 1376 }; 1377 }; 1378 1379 tlmm: pinctrl@1010000 { 1380 compatible = "qcom,msm8996-pinctrl"; 1381 reg = <0x01010000 0x300000>; 1382 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1383 gpio-controller; 1384 gpio-ranges = <&tlmm 0 0 150>; 1385 wakeup-parent = <&mpm>; 1386 #gpio-cells = <2>; 1387 interrupt-controller; 1388 #interrupt-cells = <2>; 1389 1390 blsp1_spi1_default: blsp1-spi1-default-state { 1391 spi-pins { 1392 pins = "gpio0", "gpio1", "gpio3"; 1393 function = "blsp_spi1"; 1394 drive-strength = <12>; 1395 bias-disable; 1396 }; 1397 1398 cs-pins { 1399 pins = "gpio2"; 1400 function = "gpio"; 1401 drive-strength = <16>; 1402 bias-disable; 1403 output-high; 1404 }; 1405 }; 1406 1407 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 1408 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1409 function = "gpio"; 1410 drive-strength = <2>; 1411 bias-pull-down; 1412 }; 1413 1414 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state { 1415 pins = "gpio4", "gpio5"; 1416 function = "blsp_uart8"; 1417 drive-strength = <16>; 1418 bias-disable; 1419 }; 1420 1421 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state { 1422 pins = "gpio4", "gpio5"; 1423 function = "gpio"; 1424 drive-strength = <2>; 1425 bias-disable; 1426 }; 1427 1428 blsp2_i2c2_default: blsp2-i2c2-state { 1429 pins = "gpio6", "gpio7"; 1430 function = "blsp_i2c8"; 1431 drive-strength = <16>; 1432 bias-disable; 1433 }; 1434 1435 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1436 pins = "gpio6", "gpio7"; 1437 function = "gpio"; 1438 drive-strength = <2>; 1439 bias-disable; 1440 }; 1441 1442 blsp1_i2c6_default: blsp1-i2c6-state { 1443 pins = "gpio27", "gpio28"; 1444 function = "blsp_i2c6"; 1445 drive-strength = <16>; 1446 bias-disable; 1447 }; 1448 1449 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1450 pins = "gpio27", "gpio28"; 1451 function = "gpio"; 1452 drive-strength = <2>; 1453 bias-pull-up; 1454 }; 1455 1456 cci0_default: cci0-default-state { 1457 pins = "gpio17", "gpio18"; 1458 function = "cci_i2c"; 1459 drive-strength = <16>; 1460 bias-disable; 1461 }; 1462 1463 camera0_state_on: 1464 camera_rear_default: camera-rear-default-state { 1465 camera0_mclk: mclk0-pins { 1466 pins = "gpio13"; 1467 function = "cam_mclk"; 1468 drive-strength = <16>; 1469 bias-disable; 1470 }; 1471 1472 camera0_rst: rst-pins { 1473 pins = "gpio25"; 1474 function = "gpio"; 1475 drive-strength = <16>; 1476 bias-disable; 1477 }; 1478 1479 camera0_pwdn: pwdn-pins { 1480 pins = "gpio26"; 1481 function = "gpio"; 1482 drive-strength = <16>; 1483 bias-disable; 1484 }; 1485 }; 1486 1487 cci1_default: cci1-default-state { 1488 pins = "gpio19", "gpio20"; 1489 function = "cci_i2c"; 1490 drive-strength = <16>; 1491 bias-disable; 1492 }; 1493 1494 camera1_state_on: 1495 camera_board_default: camera-board-default-state { 1496 mclk1-pins { 1497 pins = "gpio14"; 1498 function = "cam_mclk"; 1499 drive-strength = <16>; 1500 bias-disable; 1501 }; 1502 1503 pwdn-pins { 1504 pins = "gpio98"; 1505 function = "gpio"; 1506 drive-strength = <16>; 1507 bias-disable; 1508 }; 1509 1510 rst-pins { 1511 pins = "gpio104"; 1512 function = "gpio"; 1513 drive-strength = <16>; 1514 bias-disable; 1515 }; 1516 }; 1517 1518 camera2_state_on: 1519 camera_front_default: camera-front-default-state { 1520 camera2_mclk: mclk2-pins { 1521 pins = "gpio15"; 1522 function = "cam_mclk"; 1523 drive-strength = <16>; 1524 bias-disable; 1525 }; 1526 1527 camera2_rst: rst-pins { 1528 pins = "gpio23"; 1529 function = "gpio"; 1530 drive-strength = <16>; 1531 bias-disable; 1532 }; 1533 1534 pwdn-pins { 1535 pins = "gpio133"; 1536 function = "gpio"; 1537 drive-strength = <16>; 1538 bias-disable; 1539 }; 1540 }; 1541 1542 pcie0_state_on: pcie0-state-on-state { 1543 perst-pins { 1544 pins = "gpio35"; 1545 function = "gpio"; 1546 drive-strength = <2>; 1547 bias-pull-down; 1548 }; 1549 1550 clkreq-pins { 1551 pins = "gpio36"; 1552 function = "pci_e0"; 1553 drive-strength = <2>; 1554 bias-pull-up; 1555 }; 1556 1557 wake-pins { 1558 pins = "gpio37"; 1559 function = "gpio"; 1560 drive-strength = <2>; 1561 bias-pull-up; 1562 }; 1563 }; 1564 1565 pcie0_state_off: pcie0-state-off-state { 1566 perst-pins { 1567 pins = "gpio35"; 1568 function = "gpio"; 1569 drive-strength = <2>; 1570 bias-pull-down; 1571 }; 1572 1573 clkreq-pins { 1574 pins = "gpio36"; 1575 function = "gpio"; 1576 drive-strength = <2>; 1577 bias-disable; 1578 }; 1579 1580 wake-pins { 1581 pins = "gpio37"; 1582 function = "gpio"; 1583 drive-strength = <2>; 1584 bias-disable; 1585 }; 1586 }; 1587 1588 blsp1_uart2_default: blsp1-uart2-default-state { 1589 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1590 function = "blsp_uart2"; 1591 drive-strength = <16>; 1592 bias-disable; 1593 }; 1594 1595 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 1596 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1597 function = "gpio"; 1598 drive-strength = <2>; 1599 bias-disable; 1600 }; 1601 1602 blsp1_i2c3_default: blsp1-i2c3-default-state { 1603 pins = "gpio47", "gpio48"; 1604 function = "blsp_i2c3"; 1605 drive-strength = <16>; 1606 bias-disable; 1607 }; 1608 1609 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1610 pins = "gpio47", "gpio48"; 1611 function = "gpio"; 1612 drive-strength = <2>; 1613 bias-disable; 1614 }; 1615 1616 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state { 1617 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1618 function = "blsp_uart9"; 1619 drive-strength = <16>; 1620 bias-disable; 1621 }; 1622 1623 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state { 1624 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1625 function = "blsp_uart9"; 1626 drive-strength = <2>; 1627 bias-disable; 1628 }; 1629 1630 blsp2_i2c3_default: blsp2-i2c3-state-state { 1631 pins = "gpio51", "gpio52"; 1632 function = "blsp_i2c9"; 1633 drive-strength = <16>; 1634 bias-disable; 1635 }; 1636 1637 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1638 pins = "gpio51", "gpio52"; 1639 function = "gpio"; 1640 drive-strength = <2>; 1641 bias-disable; 1642 }; 1643 1644 wcd_intr_default: wcd-intr-default-state { 1645 pins = "gpio54"; 1646 function = "gpio"; 1647 drive-strength = <2>; 1648 bias-pull-down; 1649 }; 1650 1651 blsp2_i2c1_default: blsp2-i2c1-state { 1652 pins = "gpio55", "gpio56"; 1653 function = "blsp_i2c7"; 1654 drive-strength = <16>; 1655 bias-disable; 1656 }; 1657 1658 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1659 pins = "gpio55", "gpio56"; 1660 function = "gpio"; 1661 drive-strength = <2>; 1662 bias-disable; 1663 }; 1664 1665 blsp2_i2c5_default: blsp2-i2c5-state { 1666 pins = "gpio60", "gpio61"; 1667 function = "blsp_i2c11"; 1668 drive-strength = <2>; 1669 bias-disable; 1670 }; 1671 1672 /* Sleep state for BLSP2_I2C5 is missing.. */ 1673 1674 cdc_reset_active: cdc-reset-active-state { 1675 pins = "gpio64"; 1676 function = "gpio"; 1677 drive-strength = <16>; 1678 bias-pull-down; 1679 output-high; 1680 }; 1681 1682 cdc_reset_sleep: cdc-reset-sleep-state { 1683 pins = "gpio64"; 1684 function = "gpio"; 1685 drive-strength = <16>; 1686 bias-disable; 1687 output-low; 1688 }; 1689 1690 blsp2_spi6_default: blsp2-spi6-default-state { 1691 spi-pins { 1692 pins = "gpio85", "gpio86", "gpio88"; 1693 function = "blsp_spi12"; 1694 drive-strength = <12>; 1695 bias-disable; 1696 }; 1697 1698 cs-pins { 1699 pins = "gpio87"; 1700 function = "gpio"; 1701 drive-strength = <16>; 1702 bias-disable; 1703 output-high; 1704 }; 1705 }; 1706 1707 blsp2_spi6_sleep: blsp2-spi6-sleep-state { 1708 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1709 function = "gpio"; 1710 drive-strength = <2>; 1711 bias-pull-down; 1712 }; 1713 1714 blsp2_i2c6_default: blsp2-i2c6-state { 1715 pins = "gpio87", "gpio88"; 1716 function = "blsp_i2c12"; 1717 drive-strength = <16>; 1718 bias-disable; 1719 }; 1720 1721 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1722 pins = "gpio87", "gpio88"; 1723 function = "gpio"; 1724 drive-strength = <2>; 1725 bias-disable; 1726 }; 1727 1728 pcie1_state_on: pcie1-on-state { 1729 perst-pins { 1730 pins = "gpio130"; 1731 function = "gpio"; 1732 drive-strength = <2>; 1733 bias-pull-down; 1734 }; 1735 1736 clkreq-pins { 1737 pins = "gpio131"; 1738 function = "pci_e1"; 1739 drive-strength = <2>; 1740 bias-pull-up; 1741 }; 1742 1743 wake-pins { 1744 pins = "gpio132"; 1745 function = "gpio"; 1746 drive-strength = <2>; 1747 bias-pull-down; 1748 }; 1749 }; 1750 1751 pcie1_state_off: pcie1-off-state { 1752 /* Perst is missing? */ 1753 clkreq-pins { 1754 pins = "gpio131"; 1755 function = "gpio"; 1756 drive-strength = <2>; 1757 bias-disable; 1758 }; 1759 1760 wake-pins { 1761 pins = "gpio132"; 1762 function = "gpio"; 1763 drive-strength = <2>; 1764 bias-disable; 1765 }; 1766 }; 1767 1768 pcie2_state_on: pcie2-on-state { 1769 perst-pins { 1770 pins = "gpio114"; 1771 function = "gpio"; 1772 drive-strength = <2>; 1773 bias-pull-down; 1774 }; 1775 1776 clkreq-pins { 1777 pins = "gpio115"; 1778 function = "pci_e2"; 1779 drive-strength = <2>; 1780 bias-pull-up; 1781 }; 1782 1783 wake-pins { 1784 pins = "gpio116"; 1785 function = "gpio"; 1786 drive-strength = <2>; 1787 bias-pull-down; 1788 }; 1789 }; 1790 1791 pcie2_state_off: pcie2-off-state { 1792 /* Perst is missing? */ 1793 clkreq-pins { 1794 pins = "gpio115"; 1795 function = "gpio"; 1796 drive-strength = <2>; 1797 bias-disable; 1798 }; 1799 1800 wake-pins { 1801 pins = "gpio116"; 1802 function = "gpio"; 1803 drive-strength = <2>; 1804 bias-disable; 1805 }; 1806 }; 1807 1808 sdc1_state_on: sdc1-on-state { 1809 clk-pins { 1810 pins = "sdc1_clk"; 1811 bias-disable; 1812 drive-strength = <16>; 1813 }; 1814 1815 cmd-pins { 1816 pins = "sdc1_cmd"; 1817 bias-pull-up; 1818 drive-strength = <10>; 1819 }; 1820 1821 data-pins { 1822 pins = "sdc1_data"; 1823 bias-pull-up; 1824 drive-strength = <10>; 1825 }; 1826 1827 rclk-pins { 1828 pins = "sdc1_rclk"; 1829 bias-pull-down; 1830 }; 1831 }; 1832 1833 sdc1_state_off: sdc1-off-state { 1834 clk-pins { 1835 pins = "sdc1_clk"; 1836 bias-disable; 1837 drive-strength = <2>; 1838 }; 1839 1840 cmd-pins { 1841 pins = "sdc1_cmd"; 1842 bias-pull-up; 1843 drive-strength = <2>; 1844 }; 1845 1846 data-pins { 1847 pins = "sdc1_data"; 1848 bias-pull-up; 1849 drive-strength = <2>; 1850 }; 1851 1852 rclk-pins { 1853 pins = "sdc1_rclk"; 1854 bias-pull-down; 1855 }; 1856 }; 1857 1858 sdc2_state_on: sdc2-on-state { 1859 clk-pins { 1860 pins = "sdc2_clk"; 1861 bias-disable; 1862 drive-strength = <16>; 1863 }; 1864 1865 cmd-pins { 1866 pins = "sdc2_cmd"; 1867 bias-pull-up; 1868 drive-strength = <10>; 1869 }; 1870 1871 data-pins { 1872 pins = "sdc2_data"; 1873 bias-pull-up; 1874 drive-strength = <10>; 1875 }; 1876 }; 1877 1878 sdc2_state_off: sdc2-off-state { 1879 clk-pins { 1880 pins = "sdc2_clk"; 1881 bias-disable; 1882 drive-strength = <2>; 1883 }; 1884 1885 cmd-pins { 1886 pins = "sdc2_cmd"; 1887 bias-pull-up; 1888 drive-strength = <2>; 1889 }; 1890 1891 data-pins { 1892 pins = "sdc2_data"; 1893 bias-pull-up; 1894 drive-strength = <2>; 1895 }; 1896 }; 1897 }; 1898 1899 sram@290000 { 1900 compatible = "qcom,rpm-stats"; 1901 reg = <0x00290000 0x10000>; 1902 }; 1903 1904 spmi_bus: spmi@400f000 { 1905 compatible = "qcom,spmi-pmic-arb"; 1906 reg = <0x0400f000 0x1000>, 1907 <0x04400000 0x800000>, 1908 <0x04c00000 0x800000>, 1909 <0x05800000 0x200000>, 1910 <0x0400a000 0x002100>; 1911 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1912 interrupt-names = "periph_irq"; 1913 interrupts-extended = <&mpm 87 IRQ_TYPE_LEVEL_HIGH>; 1914 qcom,ee = <0>; 1915 qcom,channel = <0>; 1916 #address-cells = <2>; 1917 #size-cells = <0>; 1918 interrupt-controller; 1919 #interrupt-cells = <4>; 1920 }; 1921 1922 bus@0 { 1923 power-domains = <&gcc AGGRE0_NOC_GDSC>; 1924 compatible = "simple-pm-bus"; 1925 #address-cells = <1>; 1926 #size-cells = <1>; 1927 ranges = <0x0 0x0 0xffffffff>; 1928 1929 pcie0: pcie@600000 { 1930 compatible = "qcom,pcie-msm8996"; 1931 status = "disabled"; 1932 power-domains = <&gcc PCIE0_GDSC>; 1933 bus-range = <0x00 0xff>; 1934 num-lanes = <1>; 1935 1936 reg = <0x00600000 0x2000>, 1937 <0x0c000000 0xf1d>, 1938 <0x0c000f20 0xa8>, 1939 <0x0c100000 0x100000>; 1940 reg-names = "parf", "dbi", "elbi","config"; 1941 1942 phys = <&pciephy_0>; 1943 phy-names = "pciephy"; 1944 1945 #address-cells = <3>; 1946 #size-cells = <2>; 1947 ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, 1948 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; 1949 1950 device_type = "pci"; 1951 1952 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 1953 interrupt-names = "msi"; 1954 #interrupt-cells = <1>; 1955 interrupt-map-mask = <0 0 0 0x7>; 1956 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1957 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1958 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1959 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1960 1961 pinctrl-names = "default", "sleep"; 1962 pinctrl-0 = <&pcie0_state_on>; 1963 pinctrl-1 = <&pcie0_state_off>; 1964 1965 linux,pci-domain = <0>; 1966 1967 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1968 <&gcc GCC_PCIE_0_AUX_CLK>, 1969 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1970 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1971 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1972 1973 clock-names = "pipe", 1974 "aux", 1975 "cfg", 1976 "bus_master", 1977 "bus_slave"; 1978 }; 1979 1980 pcie1: pcie@608000 { 1981 compatible = "qcom,pcie-msm8996"; 1982 power-domains = <&gcc PCIE1_GDSC>; 1983 bus-range = <0x00 0xff>; 1984 num-lanes = <1>; 1985 1986 status = "disabled"; 1987 1988 reg = <0x00608000 0x2000>, 1989 <0x0d000000 0xf1d>, 1990 <0x0d000f20 0xa8>, 1991 <0x0d100000 0x100000>; 1992 1993 reg-names = "parf", "dbi", "elbi","config"; 1994 1995 phys = <&pciephy_1>; 1996 phy-names = "pciephy"; 1997 1998 #address-cells = <3>; 1999 #size-cells = <2>; 2000 ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, 2001 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; 2002 2003 device_type = "pci"; 2004 2005 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 2006 interrupt-names = "msi"; 2007 #interrupt-cells = <1>; 2008 interrupt-map-mask = <0 0 0 0x7>; 2009 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2010 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2011 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2012 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2013 2014 pinctrl-names = "default", "sleep"; 2015 pinctrl-0 = <&pcie1_state_on>; 2016 pinctrl-1 = <&pcie1_state_off>; 2017 2018 linux,pci-domain = <1>; 2019 2020 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2021 <&gcc GCC_PCIE_1_AUX_CLK>, 2022 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2023 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2024 <&gcc GCC_PCIE_1_SLV_AXI_CLK>; 2025 2026 clock-names = "pipe", 2027 "aux", 2028 "cfg", 2029 "bus_master", 2030 "bus_slave"; 2031 }; 2032 2033 pcie2: pcie@610000 { 2034 compatible = "qcom,pcie-msm8996"; 2035 power-domains = <&gcc PCIE2_GDSC>; 2036 bus-range = <0x00 0xff>; 2037 num-lanes = <1>; 2038 status = "disabled"; 2039 reg = <0x00610000 0x2000>, 2040 <0x0e000000 0xf1d>, 2041 <0x0e000f20 0xa8>, 2042 <0x0e100000 0x100000>; 2043 2044 reg-names = "parf", "dbi", "elbi","config"; 2045 2046 phys = <&pciephy_2>; 2047 phy-names = "pciephy"; 2048 2049 #address-cells = <3>; 2050 #size-cells = <2>; 2051 ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, 2052 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; 2053 2054 device_type = "pci"; 2055 2056 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 2057 interrupt-names = "msi"; 2058 #interrupt-cells = <1>; 2059 interrupt-map-mask = <0 0 0 0x7>; 2060 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2061 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2062 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2063 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2064 2065 pinctrl-names = "default", "sleep"; 2066 pinctrl-0 = <&pcie2_state_on>; 2067 pinctrl-1 = <&pcie2_state_off>; 2068 2069 linux,pci-domain = <2>; 2070 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2071 <&gcc GCC_PCIE_2_AUX_CLK>, 2072 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2073 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2074 <&gcc GCC_PCIE_2_SLV_AXI_CLK>; 2075 2076 clock-names = "pipe", 2077 "aux", 2078 "cfg", 2079 "bus_master", 2080 "bus_slave"; 2081 }; 2082 }; 2083 2084 ufshc: ufshc@624000 { 2085 compatible = "qcom,msm8996-ufshc", "qcom,ufshc", 2086 "jedec,ufs-2.0"; 2087 reg = <0x00624000 0x2500>; 2088 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2089 2090 phys = <&ufsphy>; 2091 phy-names = "ufsphy"; 2092 2093 power-domains = <&gcc UFS_GDSC>; 2094 2095 clock-names = 2096 "core_clk_src", 2097 "core_clk", 2098 "bus_clk", 2099 "bus_aggr_clk", 2100 "iface_clk", 2101 "core_clk_unipro_src", 2102 "core_clk_unipro", 2103 "core_clk_ice", 2104 "ref_clk", 2105 "tx_lane0_sync_clk", 2106 "rx_lane0_sync_clk"; 2107 clocks = 2108 <&gcc UFS_AXI_CLK_SRC>, 2109 <&gcc GCC_UFS_AXI_CLK>, 2110 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, 2111 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 2112 <&gcc GCC_UFS_AHB_CLK>, 2113 <&gcc UFS_ICE_CORE_CLK_SRC>, 2114 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 2115 <&gcc GCC_UFS_ICE_CORE_CLK>, 2116 <&rpmcc RPM_SMD_LN_BB_CLK>, 2117 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 2118 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; 2119 freq-table-hz = 2120 <100000000 200000000>, 2121 <0 0>, 2122 <0 0>, 2123 <0 0>, 2124 <0 0>, 2125 <150000000 300000000>, 2126 <0 0>, 2127 <0 0>, 2128 <0 0>, 2129 <0 0>, 2130 <0 0>; 2131 2132 interconnects = <&a2noc MASTER_UFS &bimc SLAVE_EBI_CH0>, 2133 <&bimc MASTER_AMPSS_M0 &cnoc SLAVE_UFS_CFG>; 2134 interconnect-names = "ufs-ddr", "cpu-ufs"; 2135 2136 lanes-per-direction = <1>; 2137 #reset-cells = <1>; 2138 status = "disabled"; 2139 }; 2140 2141 ufsphy: phy@627000 { 2142 compatible = "qcom,msm8996-qmp-ufs-phy"; 2143 reg = <0x00627000 0x1000>; 2144 2145 clocks = <&gcc GCC_UFS_CLKREF_CLK>; 2146 clock-names = "ref"; 2147 2148 resets = <&ufshc 0>; 2149 reset-names = "ufsphy"; 2150 2151 #clock-cells = <1>; 2152 #phy-cells = <0>; 2153 2154 status = "disabled"; 2155 }; 2156 2157 camss: camss@a34000 { 2158 compatible = "qcom,msm8996-camss"; 2159 reg = <0x00a34000 0x1000>, 2160 <0x00a00030 0x4>, 2161 <0x00a35000 0x1000>, 2162 <0x00a00038 0x4>, 2163 <0x00a36000 0x1000>, 2164 <0x00a00040 0x4>, 2165 <0x00a30000 0x100>, 2166 <0x00a30400 0x100>, 2167 <0x00a30800 0x100>, 2168 <0x00a30c00 0x100>, 2169 <0x00a31000 0x500>, 2170 <0x00a00020 0x10>, 2171 <0x00a10000 0x1000>, 2172 <0x00a14000 0x1000>; 2173 reg-names = "csiphy0", 2174 "csiphy0_clk_mux", 2175 "csiphy1", 2176 "csiphy1_clk_mux", 2177 "csiphy2", 2178 "csiphy2_clk_mux", 2179 "csid0", 2180 "csid1", 2181 "csid2", 2182 "csid3", 2183 "ispif", 2184 "csi_clk_mux", 2185 "vfe0", 2186 "vfe1"; 2187 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2188 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2189 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2190 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2191 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2192 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2193 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2194 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2195 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2196 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2197 interrupt-names = "csiphy0", 2198 "csiphy1", 2199 "csiphy2", 2200 "csid0", 2201 "csid1", 2202 "csid2", 2203 "csid3", 2204 "ispif", 2205 "vfe0", 2206 "vfe1"; 2207 power-domains = <&mmcc VFE0_GDSC>, 2208 <&mmcc VFE1_GDSC>; 2209 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2210 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2211 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2212 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2213 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2214 <&mmcc CAMSS_CSI0_AHB_CLK>, 2215 <&mmcc CAMSS_CSI0_CLK>, 2216 <&mmcc CAMSS_CSI0PHY_CLK>, 2217 <&mmcc CAMSS_CSI0PIX_CLK>, 2218 <&mmcc CAMSS_CSI0RDI_CLK>, 2219 <&mmcc CAMSS_CSI1_AHB_CLK>, 2220 <&mmcc CAMSS_CSI1_CLK>, 2221 <&mmcc CAMSS_CSI1PHY_CLK>, 2222 <&mmcc CAMSS_CSI1PIX_CLK>, 2223 <&mmcc CAMSS_CSI1RDI_CLK>, 2224 <&mmcc CAMSS_CSI2_AHB_CLK>, 2225 <&mmcc CAMSS_CSI2_CLK>, 2226 <&mmcc CAMSS_CSI2PHY_CLK>, 2227 <&mmcc CAMSS_CSI2PIX_CLK>, 2228 <&mmcc CAMSS_CSI2RDI_CLK>, 2229 <&mmcc CAMSS_CSI3_AHB_CLK>, 2230 <&mmcc CAMSS_CSI3_CLK>, 2231 <&mmcc CAMSS_CSI3PHY_CLK>, 2232 <&mmcc CAMSS_CSI3PIX_CLK>, 2233 <&mmcc CAMSS_CSI3RDI_CLK>, 2234 <&mmcc CAMSS_AHB_CLK>, 2235 <&mmcc CAMSS_VFE0_CLK>, 2236 <&mmcc CAMSS_CSI_VFE0_CLK>, 2237 <&mmcc CAMSS_VFE0_AHB_CLK>, 2238 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2239 <&mmcc CAMSS_VFE1_CLK>, 2240 <&mmcc CAMSS_CSI_VFE1_CLK>, 2241 <&mmcc CAMSS_VFE1_AHB_CLK>, 2242 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2243 <&mmcc CAMSS_VFE_AHB_CLK>, 2244 <&mmcc CAMSS_VFE_AXI_CLK>; 2245 clock-names = "top_ahb", 2246 "ispif_ahb", 2247 "csiphy0_timer", 2248 "csiphy1_timer", 2249 "csiphy2_timer", 2250 "csi0_ahb", 2251 "csi0", 2252 "csi0_phy", 2253 "csi0_pix", 2254 "csi0_rdi", 2255 "csi1_ahb", 2256 "csi1", 2257 "csi1_phy", 2258 "csi1_pix", 2259 "csi1_rdi", 2260 "csi2_ahb", 2261 "csi2", 2262 "csi2_phy", 2263 "csi2_pix", 2264 "csi2_rdi", 2265 "csi3_ahb", 2266 "csi3", 2267 "csi3_phy", 2268 "csi3_pix", 2269 "csi3_rdi", 2270 "ahb", 2271 "vfe0", 2272 "csi_vfe0", 2273 "vfe0_ahb", 2274 "vfe0_stream", 2275 "vfe1", 2276 "csi_vfe1", 2277 "vfe1_ahb", 2278 "vfe1_stream", 2279 "vfe_ahb", 2280 "vfe_axi"; 2281 iommus = <&vfe_smmu 0>, 2282 <&vfe_smmu 1>, 2283 <&vfe_smmu 2>, 2284 <&vfe_smmu 3>; 2285 status = "disabled"; 2286 ports { 2287 #address-cells = <1>; 2288 #size-cells = <0>; 2289 }; 2290 }; 2291 2292 cci: cci@a0c000 { 2293 compatible = "qcom,msm8996-cci"; 2294 #address-cells = <1>; 2295 #size-cells = <0>; 2296 reg = <0xa0c000 0x1000>; 2297 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2298 power-domains = <&mmcc CAMSS_GDSC>; 2299 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2300 <&mmcc CAMSS_CCI_AHB_CLK>, 2301 <&mmcc CAMSS_CCI_CLK>, 2302 <&mmcc CAMSS_AHB_CLK>; 2303 clock-names = "camss_top_ahb", 2304 "cci_ahb", 2305 "cci", 2306 "camss_ahb"; 2307 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2308 <&mmcc CAMSS_CCI_CLK>; 2309 assigned-clock-rates = <80000000>, <37500000>; 2310 pinctrl-names = "default"; 2311 pinctrl-0 = <&cci0_default &cci1_default>; 2312 status = "disabled"; 2313 2314 cci_i2c0: i2c-bus@0 { 2315 reg = <0>; 2316 clock-frequency = <400000>; 2317 #address-cells = <1>; 2318 #size-cells = <0>; 2319 }; 2320 2321 cci_i2c1: i2c-bus@1 { 2322 reg = <1>; 2323 clock-frequency = <400000>; 2324 #address-cells = <1>; 2325 #size-cells = <0>; 2326 }; 2327 }; 2328 2329 adreno_smmu: iommu@b40000 { 2330 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2331 reg = <0x00b40000 0x10000>; 2332 2333 #global-interrupts = <1>; 2334 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2335 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2336 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 2337 #iommu-cells = <1>; 2338 2339 clocks = <&gcc GCC_MMSS_BIMC_GFX_CLK>, 2340 <&mmcc GPU_AHB_CLK>; 2341 clock-names = "bus", "iface"; 2342 2343 power-domains = <&mmcc GPU_GDSC>; 2344 }; 2345 2346 venus: video-codec@c00000 { 2347 compatible = "qcom,msm8996-venus"; 2348 reg = <0x00c00000 0xff000>; 2349 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2350 power-domains = <&mmcc VENUS_GDSC>; 2351 clocks = <&mmcc VIDEO_CORE_CLK>, 2352 <&mmcc VIDEO_AHB_CLK>, 2353 <&mmcc VIDEO_AXI_CLK>, 2354 <&mmcc VIDEO_MAXI_CLK>; 2355 clock-names = "core", "iface", "bus", "mbus"; 2356 interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>, 2357 <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>; 2358 interconnect-names = "video-mem", "cpu-cfg"; 2359 iommus = <&venus_smmu 0x00>, 2360 <&venus_smmu 0x01>, 2361 <&venus_smmu 0x0a>, 2362 <&venus_smmu 0x07>, 2363 <&venus_smmu 0x0e>, 2364 <&venus_smmu 0x0f>, 2365 <&venus_smmu 0x08>, 2366 <&venus_smmu 0x09>, 2367 <&venus_smmu 0x0b>, 2368 <&venus_smmu 0x0c>, 2369 <&venus_smmu 0x0d>, 2370 <&venus_smmu 0x10>, 2371 <&venus_smmu 0x11>, 2372 <&venus_smmu 0x21>, 2373 <&venus_smmu 0x28>, 2374 <&venus_smmu 0x29>, 2375 <&venus_smmu 0x2b>, 2376 <&venus_smmu 0x2c>, 2377 <&venus_smmu 0x2d>, 2378 <&venus_smmu 0x31>; 2379 memory-region = <&venus_mem>; 2380 status = "disabled"; 2381 2382 video-decoder { 2383 compatible = "venus-decoder"; 2384 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2385 clock-names = "core"; 2386 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2387 }; 2388 2389 video-encoder { 2390 compatible = "venus-encoder"; 2391 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 2392 clock-names = "core"; 2393 power-domains = <&mmcc VENUS_CORE1_GDSC>; 2394 }; 2395 }; 2396 2397 mdp_smmu: iommu@d00000 { 2398 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2399 reg = <0x00d00000 0x10000>; 2400 2401 #global-interrupts = <1>; 2402 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 2405 #iommu-cells = <1>; 2406 clocks = <&mmcc SMMU_MDP_AXI_CLK>, 2407 <&mmcc SMMU_MDP_AHB_CLK>; 2408 clock-names = "bus", "iface"; 2409 2410 power-domains = <&mmcc MDSS_GDSC>; 2411 }; 2412 2413 venus_smmu: iommu@d40000 { 2414 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2415 reg = <0x00d40000 0x20000>; 2416 #global-interrupts = <1>; 2417 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 2418 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2419 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2420 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2421 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2422 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2423 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2424 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 2425 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; 2426 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>, 2427 <&mmcc SMMU_VIDEO_AHB_CLK>; 2428 clock-names = "bus", "iface"; 2429 #iommu-cells = <1>; 2430 status = "okay"; 2431 }; 2432 2433 vfe_smmu: iommu@da0000 { 2434 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2435 reg = <0x00da0000 0x10000>; 2436 2437 #global-interrupts = <1>; 2438 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2440 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2441 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; 2442 clocks = <&mmcc SMMU_VFE_AXI_CLK>, 2443 <&mmcc SMMU_VFE_AHB_CLK>; 2444 clock-names = "bus", "iface"; 2445 #iommu-cells = <1>; 2446 }; 2447 2448 lpass_q6_smmu: iommu@1600000 { 2449 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 2450 reg = <0x01600000 0x20000>; 2451 #iommu-cells = <1>; 2452 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; 2453 2454 #global-interrupts = <1>; 2455 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2456 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 2457 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 2458 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 2459 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2460 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2461 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2465 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2466 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2467 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; 2468 2469 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>, 2470 <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>; 2471 clock-names = "bus", "iface"; 2472 }; 2473 2474 slpi_pil: remoteproc@1c00000 { 2475 compatible = "qcom,msm8996-slpi-pil"; 2476 reg = <0x01c00000 0x4000>; 2477 2478 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, 2479 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2480 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2481 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2482 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2483 interrupt-names = "wdog", 2484 "fatal", 2485 "ready", 2486 "handover", 2487 "stop-ack"; 2488 2489 clocks = <&xo_board>, 2490 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 2491 clock-names = "xo", "aggre2"; 2492 2493 memory-region = <&slpi_mem>; 2494 2495 qcom,smem-states = <&slpi_smp2p_out 0>; 2496 qcom,smem-state-names = "stop"; 2497 2498 power-domains = <&rpmpd MSM8996_VDDSSCX>; 2499 power-domain-names = "ssc_cx"; 2500 2501 status = "disabled"; 2502 2503 smd-edge { 2504 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>; 2505 2506 label = "dsps"; 2507 mboxes = <&apcs_glb 25>; 2508 qcom,smd-edge = <3>; 2509 qcom,remote-pid = <3>; 2510 }; 2511 }; 2512 2513 mss_pil: remoteproc@2080000 { 2514 compatible = "qcom,msm8996-mss-pil"; 2515 reg = <0x2080000 0x100>, 2516 <0x2180000 0x020>; 2517 reg-names = "qdsp6", "rmb"; 2518 2519 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, 2520 <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2521 <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2522 <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2523 <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2524 <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2525 interrupt-names = "wdog", "fatal", "ready", 2526 "handover", "stop-ack", 2527 "shutdown-ack"; 2528 2529 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2530 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 2531 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2532 <&xo_board>, 2533 <&gcc GCC_MSS_GPLL0_DIV_CLK>, 2534 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2535 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 2536 <&rpmcc RPM_SMD_PCNOC_CLK>, 2537 <&rpmcc RPM_SMD_QDSS_CLK>; 2538 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", 2539 "snoc_axi", "mnoc_axi", "pnoc", "qdss"; 2540 2541 resets = <&gcc GCC_MSS_RESTART>; 2542 reset-names = "mss_restart"; 2543 2544 power-domains = <&rpmpd MSM8996_VDDCX>, 2545 <&rpmpd MSM8996_VDDMX>; 2546 power-domain-names = "cx", "mx"; 2547 2548 qcom,smem-states = <&mpss_smp2p_out 0>; 2549 qcom,smem-state-names = "stop"; 2550 2551 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>; 2552 2553 status = "disabled"; 2554 2555 mba { 2556 memory-region = <&mba_mem>; 2557 }; 2558 2559 mpss { 2560 memory-region = <&mpss_mem>; 2561 }; 2562 2563 metadata { 2564 memory-region = <&mdata_mem>; 2565 }; 2566 2567 smd-edge { 2568 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2569 2570 label = "mpss"; 2571 mboxes = <&apcs_glb 12>; 2572 qcom,smd-edge = <0>; 2573 qcom,remote-pid = <1>; 2574 }; 2575 }; 2576 2577 stm@3002000 { 2578 compatible = "arm,coresight-stm", "arm,primecell"; 2579 reg = <0x3002000 0x1000>, 2580 <0x8280000 0x180000>; 2581 reg-names = "stm-base", "stm-stimulus-base"; 2582 2583 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2584 clock-names = "apb_pclk", "atclk"; 2585 2586 out-ports { 2587 port { 2588 stm_out: endpoint { 2589 remote-endpoint = 2590 <&funnel0_in>; 2591 }; 2592 }; 2593 }; 2594 }; 2595 2596 tpiu@3020000 { 2597 compatible = "arm,coresight-tpiu", "arm,primecell"; 2598 reg = <0x3020000 0x1000>; 2599 2600 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2601 clock-names = "apb_pclk", "atclk"; 2602 2603 in-ports { 2604 port { 2605 tpiu_in: endpoint { 2606 remote-endpoint = 2607 <&replicator_out1>; 2608 }; 2609 }; 2610 }; 2611 }; 2612 2613 funnel@3021000 { 2614 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2615 reg = <0x3021000 0x1000>; 2616 2617 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2618 clock-names = "apb_pclk", "atclk"; 2619 2620 in-ports { 2621 #address-cells = <1>; 2622 #size-cells = <0>; 2623 2624 port@7 { 2625 reg = <7>; 2626 funnel0_in: endpoint { 2627 remote-endpoint = 2628 <&stm_out>; 2629 }; 2630 }; 2631 }; 2632 2633 out-ports { 2634 port { 2635 funnel0_out: endpoint { 2636 remote-endpoint = 2637 <&merge_funnel_in0>; 2638 }; 2639 }; 2640 }; 2641 }; 2642 2643 funnel@3022000 { 2644 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2645 reg = <0x3022000 0x1000>; 2646 2647 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2648 clock-names = "apb_pclk", "atclk"; 2649 2650 in-ports { 2651 #address-cells = <1>; 2652 #size-cells = <0>; 2653 2654 port@6 { 2655 reg = <6>; 2656 funnel1_in: endpoint { 2657 remote-endpoint = 2658 <&apss_merge_funnel_out>; 2659 }; 2660 }; 2661 }; 2662 2663 out-ports { 2664 port { 2665 funnel1_out: endpoint { 2666 remote-endpoint = 2667 <&merge_funnel_in1>; 2668 }; 2669 }; 2670 }; 2671 }; 2672 2673 funnel@3023000 { 2674 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2675 reg = <0x3023000 0x1000>; 2676 2677 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2678 clock-names = "apb_pclk", "atclk"; 2679 2680 in-ports { 2681 port { 2682 funnel_in2_in_modem_etm: endpoint { 2683 remote-endpoint = 2684 <&modem_etm_out_funnel_in2>; 2685 }; 2686 }; 2687 }; 2688 2689 out-ports { 2690 port { 2691 funnel2_out: endpoint { 2692 remote-endpoint = 2693 <&merge_funnel_in2>; 2694 }; 2695 }; 2696 }; 2697 }; 2698 2699 funnel@3025000 { 2700 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2701 reg = <0x3025000 0x1000>; 2702 2703 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2704 clock-names = "apb_pclk", "atclk"; 2705 2706 in-ports { 2707 #address-cells = <1>; 2708 #size-cells = <0>; 2709 2710 port@0 { 2711 reg = <0>; 2712 merge_funnel_in0: endpoint { 2713 remote-endpoint = 2714 <&funnel0_out>; 2715 }; 2716 }; 2717 2718 port@1 { 2719 reg = <1>; 2720 merge_funnel_in1: endpoint { 2721 remote-endpoint = 2722 <&funnel1_out>; 2723 }; 2724 }; 2725 2726 port@2 { 2727 reg = <2>; 2728 merge_funnel_in2: endpoint { 2729 remote-endpoint = 2730 <&funnel2_out>; 2731 }; 2732 }; 2733 }; 2734 2735 out-ports { 2736 port { 2737 merge_funnel_out: endpoint { 2738 remote-endpoint = 2739 <&etf_in>; 2740 }; 2741 }; 2742 }; 2743 }; 2744 2745 replicator@3026000 { 2746 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2747 reg = <0x3026000 0x1000>; 2748 2749 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2750 clock-names = "apb_pclk", "atclk"; 2751 2752 in-ports { 2753 port { 2754 replicator_in: endpoint { 2755 remote-endpoint = 2756 <&etf_out>; 2757 }; 2758 }; 2759 }; 2760 2761 out-ports { 2762 #address-cells = <1>; 2763 #size-cells = <0>; 2764 2765 port@0 { 2766 reg = <0>; 2767 replicator_out0: endpoint { 2768 remote-endpoint = 2769 <&etr_in>; 2770 }; 2771 }; 2772 2773 port@1 { 2774 reg = <1>; 2775 replicator_out1: endpoint { 2776 remote-endpoint = 2777 <&tpiu_in>; 2778 }; 2779 }; 2780 }; 2781 }; 2782 2783 etf@3027000 { 2784 compatible = "arm,coresight-tmc", "arm,primecell"; 2785 reg = <0x3027000 0x1000>; 2786 2787 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2788 clock-names = "apb_pclk", "atclk"; 2789 2790 in-ports { 2791 port { 2792 etf_in: endpoint { 2793 remote-endpoint = 2794 <&merge_funnel_out>; 2795 }; 2796 }; 2797 }; 2798 2799 out-ports { 2800 port { 2801 etf_out: endpoint { 2802 remote-endpoint = 2803 <&replicator_in>; 2804 }; 2805 }; 2806 }; 2807 }; 2808 2809 etr@3028000 { 2810 compatible = "arm,coresight-tmc", "arm,primecell"; 2811 reg = <0x3028000 0x1000>; 2812 2813 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2814 clock-names = "apb_pclk", "atclk"; 2815 arm,scatter-gather; 2816 2817 in-ports { 2818 port { 2819 etr_in: endpoint { 2820 remote-endpoint = 2821 <&replicator_out0>; 2822 }; 2823 }; 2824 }; 2825 }; 2826 2827 debug@3810000 { 2828 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2829 reg = <0x3810000 0x1000>; 2830 2831 clocks = <&rpmcc RPM_QDSS_CLK>; 2832 clock-names = "apb_pclk"; 2833 2834 cpu = <&CPU0>; 2835 }; 2836 2837 etm@3840000 { 2838 compatible = "arm,coresight-etm4x", "arm,primecell"; 2839 reg = <0x3840000 0x1000>; 2840 2841 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2842 clock-names = "apb_pclk", "atclk"; 2843 2844 cpu = <&CPU0>; 2845 2846 out-ports { 2847 port { 2848 etm0_out: endpoint { 2849 remote-endpoint = 2850 <&apss_funnel0_in0>; 2851 }; 2852 }; 2853 }; 2854 }; 2855 2856 debug@3910000 { 2857 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2858 reg = <0x3910000 0x1000>; 2859 2860 clocks = <&rpmcc RPM_QDSS_CLK>; 2861 clock-names = "apb_pclk"; 2862 2863 cpu = <&CPU1>; 2864 }; 2865 2866 etm@3940000 { 2867 compatible = "arm,coresight-etm4x", "arm,primecell"; 2868 reg = <0x3940000 0x1000>; 2869 2870 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2871 clock-names = "apb_pclk", "atclk"; 2872 2873 cpu = <&CPU1>; 2874 2875 out-ports { 2876 port { 2877 etm1_out: endpoint { 2878 remote-endpoint = 2879 <&apss_funnel0_in1>; 2880 }; 2881 }; 2882 }; 2883 }; 2884 2885 funnel@39b0000 { /* APSS Funnel 0 */ 2886 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2887 reg = <0x39b0000 0x1000>; 2888 2889 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2890 clock-names = "apb_pclk", "atclk"; 2891 2892 in-ports { 2893 #address-cells = <1>; 2894 #size-cells = <0>; 2895 2896 port@0 { 2897 reg = <0>; 2898 apss_funnel0_in0: endpoint { 2899 remote-endpoint = <&etm0_out>; 2900 }; 2901 }; 2902 2903 port@1 { 2904 reg = <1>; 2905 apss_funnel0_in1: endpoint { 2906 remote-endpoint = <&etm1_out>; 2907 }; 2908 }; 2909 }; 2910 2911 out-ports { 2912 port { 2913 apss_funnel0_out: endpoint { 2914 remote-endpoint = 2915 <&apss_merge_funnel_in0>; 2916 }; 2917 }; 2918 }; 2919 }; 2920 2921 debug@3a10000 { 2922 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2923 reg = <0x3a10000 0x1000>; 2924 2925 clocks = <&rpmcc RPM_QDSS_CLK>; 2926 clock-names = "apb_pclk"; 2927 2928 cpu = <&CPU2>; 2929 }; 2930 2931 etm@3a40000 { 2932 compatible = "arm,coresight-etm4x", "arm,primecell"; 2933 reg = <0x3a40000 0x1000>; 2934 2935 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2936 clock-names = "apb_pclk", "atclk"; 2937 2938 cpu = <&CPU2>; 2939 2940 out-ports { 2941 port { 2942 etm2_out: endpoint { 2943 remote-endpoint = 2944 <&apss_funnel1_in0>; 2945 }; 2946 }; 2947 }; 2948 }; 2949 2950 debug@3b10000 { 2951 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 2952 reg = <0x3b10000 0x1000>; 2953 2954 clocks = <&rpmcc RPM_QDSS_CLK>; 2955 clock-names = "apb_pclk"; 2956 2957 cpu = <&CPU3>; 2958 }; 2959 2960 etm@3b40000 { 2961 compatible = "arm,coresight-etm4x", "arm,primecell"; 2962 reg = <0x3b40000 0x1000>; 2963 2964 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2965 clock-names = "apb_pclk", "atclk"; 2966 2967 cpu = <&CPU3>; 2968 2969 out-ports { 2970 port { 2971 etm3_out: endpoint { 2972 remote-endpoint = 2973 <&apss_funnel1_in1>; 2974 }; 2975 }; 2976 }; 2977 }; 2978 2979 funnel@3bb0000 { /* APSS Funnel 1 */ 2980 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2981 reg = <0x3bb0000 0x1000>; 2982 2983 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 2984 clock-names = "apb_pclk", "atclk"; 2985 2986 in-ports { 2987 #address-cells = <1>; 2988 #size-cells = <0>; 2989 2990 port@0 { 2991 reg = <0>; 2992 apss_funnel1_in0: endpoint { 2993 remote-endpoint = <&etm2_out>; 2994 }; 2995 }; 2996 2997 port@1 { 2998 reg = <1>; 2999 apss_funnel1_in1: endpoint { 3000 remote-endpoint = <&etm3_out>; 3001 }; 3002 }; 3003 }; 3004 3005 out-ports { 3006 port { 3007 apss_funnel1_out: endpoint { 3008 remote-endpoint = 3009 <&apss_merge_funnel_in1>; 3010 }; 3011 }; 3012 }; 3013 }; 3014 3015 funnel@3bc0000 { 3016 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3017 reg = <0x3bc0000 0x1000>; 3018 3019 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 3020 clock-names = "apb_pclk", "atclk"; 3021 3022 in-ports { 3023 #address-cells = <1>; 3024 #size-cells = <0>; 3025 3026 port@0 { 3027 reg = <0>; 3028 apss_merge_funnel_in0: endpoint { 3029 remote-endpoint = 3030 <&apss_funnel0_out>; 3031 }; 3032 }; 3033 3034 port@1 { 3035 reg = <1>; 3036 apss_merge_funnel_in1: endpoint { 3037 remote-endpoint = 3038 <&apss_funnel1_out>; 3039 }; 3040 }; 3041 }; 3042 3043 out-ports { 3044 port { 3045 apss_merge_funnel_out: endpoint { 3046 remote-endpoint = 3047 <&funnel1_in>; 3048 }; 3049 }; 3050 }; 3051 }; 3052 3053 kryocc: clock-controller@6400000 { 3054 compatible = "qcom,msm8996-apcc"; 3055 reg = <0x06400000 0x90000>; 3056 3057 clock-names = "xo", "sys_apcs_aux"; 3058 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3059 3060 #clock-cells = <1>; 3061 }; 3062 3063 usb3: usb@6af8800 { 3064 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3065 reg = <0x06af8800 0x400>; 3066 #address-cells = <1>; 3067 #size-cells = <1>; 3068 ranges; 3069 3070 interrupts-extended = <&mpm 79 IRQ_TYPE_LEVEL_HIGH>, 3071 <&mpm 52 IRQ_TYPE_LEVEL_HIGH>; 3072 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 3073 3074 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 3075 <&gcc GCC_USB30_MASTER_CLK>, 3076 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 3077 <&gcc GCC_USB30_SLEEP_CLK>, 3078 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 3079 clock-names = "cfg_noc", 3080 "core", 3081 "iface", 3082 "sleep", 3083 "mock_utmi"; 3084 3085 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 3086 <&gcc GCC_USB30_MASTER_CLK>; 3087 assigned-clock-rates = <19200000>, <120000000>; 3088 3089 interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, 3090 <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>; 3091 interconnect-names = "usb-ddr", "apps-usb"; 3092 3093 power-domains = <&gcc USB30_GDSC>; 3094 status = "disabled"; 3095 3096 usb3_dwc3: usb@6a00000 { 3097 compatible = "snps,dwc3"; 3098 reg = <0x06a00000 0xcc00>; 3099 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 3100 phys = <&hsusb_phy1>, <&usb3phy>; 3101 phy-names = "usb2-phy", "usb3-phy"; 3102 snps,hird-threshold = /bits/ 8 <0>; 3103 snps,dis_u2_susphy_quirk; 3104 snps,dis_enblslpm_quirk; 3105 snps,is-utmi-l1-suspend; 3106 tx-fifo-resize; 3107 }; 3108 }; 3109 3110 usb3phy: phy@7410000 { 3111 compatible = "qcom,msm8996-qmp-usb3-phy"; 3112 reg = <0x07410000 0x1000>; 3113 3114 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 3115 <&gcc GCC_USB3_CLKREF_CLK>, 3116 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3117 <&gcc GCC_USB3_PHY_PIPE_CLK>; 3118 clock-names = "aux", 3119 "ref", 3120 "cfg_ahb", 3121 "pipe"; 3122 clock-output-names = "usb3_phy_pipe_clk_src"; 3123 #clock-cells = <0>; 3124 #phy-cells = <0>; 3125 3126 resets = <&gcc GCC_USB3_PHY_BCR>, 3127 <&gcc GCC_USB3PHY_PHY_BCR>; 3128 reset-names = "phy", 3129 "phy_phy"; 3130 3131 status = "disabled"; 3132 }; 3133 3134 hsusb_phy1: phy@7411000 { 3135 compatible = "qcom,msm8996-qusb2-phy"; 3136 reg = <0x07411000 0x180>; 3137 #phy-cells = <0>; 3138 3139 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3140 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 3141 clock-names = "cfg_ahb", "ref"; 3142 3143 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3144 nvmem-cells = <&qusb2p_hstx_trim>; 3145 status = "disabled"; 3146 }; 3147 3148 hsusb_phy2: phy@7412000 { 3149 compatible = "qcom,msm8996-qusb2-phy"; 3150 reg = <0x07412000 0x180>; 3151 #phy-cells = <0>; 3152 3153 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 3154 <&gcc GCC_RX2_USB2_CLKREF_CLK>; 3155 clock-names = "cfg_ahb", "ref"; 3156 3157 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3158 nvmem-cells = <&qusb2s_hstx_trim>; 3159 status = "disabled"; 3160 }; 3161 3162 sdhc1: mmc@7464900 { 3163 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3164 reg = <0x07464900 0x11c>, <0x07464000 0x800>; 3165 reg-names = "hc", "core"; 3166 3167 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 3169 interrupt-names = "hc_irq", "pwr_irq"; 3170 3171 clock-names = "iface", "core", "xo"; 3172 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3173 <&gcc GCC_SDCC1_APPS_CLK>, 3174 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3175 resets = <&gcc GCC_SDCC1_BCR>; 3176 3177 pinctrl-names = "default", "sleep"; 3178 pinctrl-0 = <&sdc1_state_on>; 3179 pinctrl-1 = <&sdc1_state_off>; 3180 3181 bus-width = <8>; 3182 non-removable; 3183 status = "disabled"; 3184 }; 3185 3186 sdhc2: mmc@74a4900 { 3187 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"; 3188 reg = <0x074a4900 0x314>, <0x074a4000 0x800>; 3189 reg-names = "hc", "core"; 3190 3191 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 3193 interrupt-names = "hc_irq", "pwr_irq"; 3194 3195 clock-names = "iface", "core", "xo"; 3196 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3197 <&gcc GCC_SDCC2_APPS_CLK>, 3198 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3199 resets = <&gcc GCC_SDCC2_BCR>; 3200 3201 pinctrl-names = "default", "sleep"; 3202 pinctrl-0 = <&sdc2_state_on>; 3203 pinctrl-1 = <&sdc2_state_off>; 3204 3205 bus-width = <4>; 3206 status = "disabled"; 3207 }; 3208 3209 blsp1_dma: dma-controller@7544000 { 3210 compatible = "qcom,bam-v1.7.0"; 3211 reg = <0x07544000 0x2b000>; 3212 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3213 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 3214 clock-names = "bam_clk"; 3215 qcom,controlled-remotely; 3216 #dma-cells = <1>; 3217 qcom,ee = <0>; 3218 }; 3219 3220 blsp1_uart2: serial@7570000 { 3221 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3222 reg = <0x07570000 0x1000>; 3223 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 3224 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 3225 <&gcc GCC_BLSP1_AHB_CLK>; 3226 clock-names = "core", "iface"; 3227 pinctrl-names = "default", "sleep"; 3228 pinctrl-0 = <&blsp1_uart2_default>; 3229 pinctrl-1 = <&blsp1_uart2_sleep>; 3230 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 3231 dma-names = "tx", "rx"; 3232 status = "disabled"; 3233 }; 3234 3235 blsp1_spi1: spi@7575000 { 3236 compatible = "qcom,spi-qup-v2.2.1"; 3237 reg = <0x07575000 0x600>; 3238 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 3239 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 3240 <&gcc GCC_BLSP1_AHB_CLK>; 3241 clock-names = "core", "iface"; 3242 pinctrl-names = "default", "sleep"; 3243 pinctrl-0 = <&blsp1_spi1_default>; 3244 pinctrl-1 = <&blsp1_spi1_sleep>; 3245 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 3246 dma-names = "tx", "rx"; 3247 #address-cells = <1>; 3248 #size-cells = <0>; 3249 status = "disabled"; 3250 }; 3251 3252 blsp1_i2c3: i2c@7577000 { 3253 compatible = "qcom,i2c-qup-v2.2.1"; 3254 reg = <0x07577000 0x1000>; 3255 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 3256 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 3257 <&gcc GCC_BLSP1_AHB_CLK>; 3258 clock-names = "core", "iface"; 3259 pinctrl-names = "default", "sleep"; 3260 pinctrl-0 = <&blsp1_i2c3_default>; 3261 pinctrl-1 = <&blsp1_i2c3_sleep>; 3262 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 3263 dma-names = "tx", "rx"; 3264 #address-cells = <1>; 3265 #size-cells = <0>; 3266 status = "disabled"; 3267 }; 3268 3269 blsp1_i2c6: i2c@757a000 { 3270 compatible = "qcom,i2c-qup-v2.2.1"; 3271 reg = <0x757a000 0x1000>; 3272 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 3273 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 3274 <&gcc GCC_BLSP1_AHB_CLK>; 3275 clock-names = "core", "iface"; 3276 pinctrl-names = "default", "sleep"; 3277 pinctrl-0 = <&blsp1_i2c6_default>; 3278 pinctrl-1 = <&blsp1_i2c6_sleep>; 3279 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 3280 dma-names = "tx", "rx"; 3281 #address-cells = <1>; 3282 #size-cells = <0>; 3283 status = "disabled"; 3284 }; 3285 3286 blsp2_dma: dma-controller@7584000 { 3287 compatible = "qcom,bam-v1.7.0"; 3288 reg = <0x07584000 0x2b000>; 3289 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 3290 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 3291 clock-names = "bam_clk"; 3292 qcom,controlled-remotely; 3293 #dma-cells = <1>; 3294 qcom,ee = <0>; 3295 }; 3296 3297 blsp2_uart2: serial@75b0000 { 3298 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3299 reg = <0x075b0000 0x1000>; 3300 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3301 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 3302 <&gcc GCC_BLSP2_AHB_CLK>; 3303 clock-names = "core", "iface"; 3304 status = "disabled"; 3305 }; 3306 3307 blsp2_uart3: serial@75b1000 { 3308 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 3309 reg = <0x075b1000 0x1000>; 3310 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3311 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, 3312 <&gcc GCC_BLSP2_AHB_CLK>; 3313 clock-names = "core", "iface"; 3314 status = "disabled"; 3315 }; 3316 3317 blsp2_i2c1: i2c@75b5000 { 3318 compatible = "qcom,i2c-qup-v2.2.1"; 3319 reg = <0x075b5000 0x1000>; 3320 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 3321 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 3322 <&gcc GCC_BLSP2_AHB_CLK>; 3323 clock-names = "core", "iface"; 3324 pinctrl-names = "default", "sleep"; 3325 pinctrl-0 = <&blsp2_i2c1_default>; 3326 pinctrl-1 = <&blsp2_i2c1_sleep>; 3327 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 3328 dma-names = "tx", "rx"; 3329 #address-cells = <1>; 3330 #size-cells = <0>; 3331 status = "disabled"; 3332 }; 3333 3334 blsp2_i2c2: i2c@75b6000 { 3335 compatible = "qcom,i2c-qup-v2.2.1"; 3336 reg = <0x075b6000 0x1000>; 3337 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 3338 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 3339 <&gcc GCC_BLSP2_AHB_CLK>; 3340 clock-names = "core", "iface"; 3341 pinctrl-names = "default", "sleep"; 3342 pinctrl-0 = <&blsp2_i2c2_default>; 3343 pinctrl-1 = <&blsp2_i2c2_sleep>; 3344 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 3345 dma-names = "tx", "rx"; 3346 #address-cells = <1>; 3347 #size-cells = <0>; 3348 status = "disabled"; 3349 }; 3350 3351 blsp2_i2c3: i2c@75b7000 { 3352 compatible = "qcom,i2c-qup-v2.2.1"; 3353 reg = <0x075b7000 0x1000>; 3354 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 3355 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 3356 <&gcc GCC_BLSP2_AHB_CLK>; 3357 clock-names = "core", "iface"; 3358 clock-frequency = <400000>; 3359 pinctrl-names = "default", "sleep"; 3360 pinctrl-0 = <&blsp2_i2c3_default>; 3361 pinctrl-1 = <&blsp2_i2c3_sleep>; 3362 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 3363 dma-names = "tx", "rx"; 3364 #address-cells = <1>; 3365 #size-cells = <0>; 3366 status = "disabled"; 3367 }; 3368 3369 blsp2_i2c5: i2c@75b9000 { 3370 compatible = "qcom,i2c-qup-v2.2.1"; 3371 reg = <0x75b9000 0x1000>; 3372 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 3373 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 3374 <&gcc GCC_BLSP2_AHB_CLK>; 3375 clock-names = "core", "iface"; 3376 pinctrl-names = "default"; 3377 pinctrl-0 = <&blsp2_i2c5_default>; 3378 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 3379 dma-names = "tx", "rx"; 3380 #address-cells = <1>; 3381 #size-cells = <0>; 3382 status = "disabled"; 3383 }; 3384 3385 blsp2_i2c6: i2c@75ba000 { 3386 compatible = "qcom,i2c-qup-v2.2.1"; 3387 reg = <0x75ba000 0x1000>; 3388 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3389 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 3390 <&gcc GCC_BLSP2_AHB_CLK>; 3391 clock-names = "core", "iface"; 3392 pinctrl-names = "default", "sleep"; 3393 pinctrl-0 = <&blsp2_i2c6_default>; 3394 pinctrl-1 = <&blsp2_i2c6_sleep>; 3395 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3396 dma-names = "tx", "rx"; 3397 #address-cells = <1>; 3398 #size-cells = <0>; 3399 status = "disabled"; 3400 }; 3401 3402 blsp2_spi6: spi@75ba000 { 3403 compatible = "qcom,spi-qup-v2.2.1"; 3404 reg = <0x075ba000 0x600>; 3405 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 3406 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 3407 <&gcc GCC_BLSP2_AHB_CLK>; 3408 clock-names = "core", "iface"; 3409 pinctrl-names = "default", "sleep"; 3410 pinctrl-0 = <&blsp2_spi6_default>; 3411 pinctrl-1 = <&blsp2_spi6_sleep>; 3412 dmas = <&blsp2_dma 22>, <&blsp2_dma 23>; 3413 dma-names = "tx", "rx"; 3414 #address-cells = <1>; 3415 #size-cells = <0>; 3416 status = "disabled"; 3417 }; 3418 3419 usb2: usb@76f8800 { 3420 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 3421 reg = <0x076f8800 0x400>; 3422 #address-cells = <1>; 3423 #size-cells = <1>; 3424 ranges; 3425 3426 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 3427 interrupt-names = "hs_phy_irq"; 3428 3429 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, 3430 <&gcc GCC_USB20_MASTER_CLK>, 3431 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3432 <&gcc GCC_USB20_SLEEP_CLK>, 3433 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 3434 clock-names = "cfg_noc", 3435 "core", 3436 "iface", 3437 "sleep", 3438 "mock_utmi"; 3439 3440 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3441 <&gcc GCC_USB20_MASTER_CLK>; 3442 assigned-clock-rates = <19200000>, <60000000>; 3443 3444 power-domains = <&gcc USB30_GDSC>; 3445 qcom,select-utmi-as-pipe-clk; 3446 status = "disabled"; 3447 3448 usb2_dwc3: usb@7600000 { 3449 compatible = "snps,dwc3"; 3450 reg = <0x07600000 0xcc00>; 3451 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3452 phys = <&hsusb_phy2>; 3453 phy-names = "usb2-phy"; 3454 maximum-speed = "high-speed"; 3455 snps,dis_u2_susphy_quirk; 3456 snps,dis_enblslpm_quirk; 3457 }; 3458 }; 3459 3460 slimbam: dma-controller@9184000 { 3461 compatible = "qcom,bam-v1.7.0"; 3462 qcom,controlled-remotely; 3463 reg = <0x09184000 0x32000>; 3464 num-channels = <31>; 3465 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 3466 #dma-cells = <1>; 3467 qcom,ee = <1>; 3468 qcom,num-ees = <2>; 3469 }; 3470 3471 slim_msm: slim-ngd@91c0000 { 3472 compatible = "qcom,slim-ngd-v1.5.0"; 3473 reg = <0x091c0000 0x2c000>; 3474 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 3475 dmas = <&slimbam 3>, <&slimbam 4>; 3476 dma-names = "rx", "tx"; 3477 #address-cells = <1>; 3478 #size-cells = <0>; 3479 3480 status = "disabled"; 3481 }; 3482 3483 adsp_pil: remoteproc@9300000 { 3484 compatible = "qcom,msm8996-adsp-pil"; 3485 reg = <0x09300000 0x80000>; 3486 3487 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, 3488 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3489 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3490 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3491 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3492 interrupt-names = "wdog", "fatal", "ready", 3493 "handover", "stop-ack"; 3494 3495 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3496 clock-names = "xo"; 3497 3498 memory-region = <&adsp_mem>; 3499 3500 qcom,smem-states = <&adsp_smp2p_out 0>; 3501 qcom,smem-state-names = "stop"; 3502 3503 power-domains = <&rpmpd MSM8996_VDDCX>; 3504 power-domain-names = "cx"; 3505 3506 status = "disabled"; 3507 3508 smd-edge { 3509 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3510 3511 label = "lpass"; 3512 mboxes = <&apcs_glb 8>; 3513 qcom,smd-edge = <1>; 3514 qcom,remote-pid = <2>; 3515 3516 apr { 3517 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 3518 compatible = "qcom,apr-v2"; 3519 qcom,smd-channels = "apr_audio_svc"; 3520 qcom,domain = <APR_DOMAIN_ADSP>; 3521 #address-cells = <1>; 3522 #size-cells = <0>; 3523 3524 service@3 { 3525 reg = <APR_SVC_ADSP_CORE>; 3526 compatible = "qcom,q6core"; 3527 }; 3528 3529 q6afe: service@4 { 3530 compatible = "qcom,q6afe"; 3531 reg = <APR_SVC_AFE>; 3532 q6afedai: dais { 3533 compatible = "qcom,q6afe-dais"; 3534 #address-cells = <1>; 3535 #size-cells = <0>; 3536 #sound-dai-cells = <1>; 3537 dai@1 { 3538 reg = <1>; 3539 }; 3540 }; 3541 }; 3542 3543 q6asm: service@7 { 3544 compatible = "qcom,q6asm"; 3545 reg = <APR_SVC_ASM>; 3546 q6asmdai: dais { 3547 compatible = "qcom,q6asm-dais"; 3548 #address-cells = <1>; 3549 #size-cells = <0>; 3550 #sound-dai-cells = <1>; 3551 iommus = <&lpass_q6_smmu 1>; 3552 }; 3553 }; 3554 3555 q6adm: service@8 { 3556 compatible = "qcom,q6adm"; 3557 reg = <APR_SVC_ADM>; 3558 q6routing: routing { 3559 compatible = "qcom,q6adm-routing"; 3560 #sound-dai-cells = <0>; 3561 }; 3562 }; 3563 }; 3564 }; 3565 }; 3566 3567 apcs_glb: mailbox@9820000 { 3568 compatible = "qcom,msm8996-apcs-hmss-global"; 3569 reg = <0x09820000 0x1000>; 3570 3571 #mbox-cells = <1>; 3572 #clock-cells = <0>; 3573 }; 3574 3575 timer@9840000 { 3576 #address-cells = <1>; 3577 #size-cells = <1>; 3578 ranges; 3579 compatible = "arm,armv7-timer-mem"; 3580 reg = <0x09840000 0x1000>; 3581 clock-frequency = <19200000>; 3582 3583 frame@9850000 { 3584 frame-number = <0>; 3585 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3586 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 3587 reg = <0x09850000 0x1000>, 3588 <0x09860000 0x1000>; 3589 }; 3590 3591 frame@9870000 { 3592 frame-number = <1>; 3593 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3594 reg = <0x09870000 0x1000>; 3595 status = "disabled"; 3596 }; 3597 3598 frame@9880000 { 3599 frame-number = <2>; 3600 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3601 reg = <0x09880000 0x1000>; 3602 status = "disabled"; 3603 }; 3604 3605 frame@9890000 { 3606 frame-number = <3>; 3607 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 3608 reg = <0x09890000 0x1000>; 3609 status = "disabled"; 3610 }; 3611 3612 frame@98a0000 { 3613 frame-number = <4>; 3614 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3615 reg = <0x098a0000 0x1000>; 3616 status = "disabled"; 3617 }; 3618 3619 frame@98b0000 { 3620 frame-number = <5>; 3621 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 3622 reg = <0x098b0000 0x1000>; 3623 status = "disabled"; 3624 }; 3625 3626 frame@98c0000 { 3627 frame-number = <6>; 3628 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3629 reg = <0x098c0000 0x1000>; 3630 status = "disabled"; 3631 }; 3632 }; 3633 3634 saw3: syscon@9a10000 { 3635 compatible = "syscon"; 3636 reg = <0x09a10000 0x1000>; 3637 }; 3638 3639 cbf: clock-controller@9a11000 { 3640 compatible = "qcom,msm8996-cbf"; 3641 reg = <0x09a11000 0x10000>; 3642 clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; 3643 #clock-cells = <0>; 3644 #interconnect-cells = <1>; 3645 }; 3646 3647 intc: interrupt-controller@9bc0000 { 3648 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; 3649 #interrupt-cells = <3>; 3650 interrupt-controller; 3651 #redistributor-regions = <1>; 3652 redistributor-stride = <0x0 0x40000>; 3653 reg = <0x09bc0000 0x10000>, 3654 <0x09c00000 0x100000>; 3655 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3656 }; 3657 }; 3658 3659 sound: sound { 3660 }; 3661 3662 thermal-zones { 3663 cpu0-thermal { 3664 polling-delay-passive = <250>; 3665 polling-delay = <1000>; 3666 3667 thermal-sensors = <&tsens0 3>; 3668 3669 trips { 3670 cpu0_alert0: trip-point0 { 3671 temperature = <75000>; 3672 hysteresis = <2000>; 3673 type = "passive"; 3674 }; 3675 3676 cpu0_crit: cpu-crit { 3677 temperature = <110000>; 3678 hysteresis = <2000>; 3679 type = "critical"; 3680 }; 3681 }; 3682 }; 3683 3684 cpu1-thermal { 3685 polling-delay-passive = <250>; 3686 polling-delay = <1000>; 3687 3688 thermal-sensors = <&tsens0 5>; 3689 3690 trips { 3691 cpu1_alert0: trip-point0 { 3692 temperature = <75000>; 3693 hysteresis = <2000>; 3694 type = "passive"; 3695 }; 3696 3697 cpu1_crit: cpu-crit { 3698 temperature = <110000>; 3699 hysteresis = <2000>; 3700 type = "critical"; 3701 }; 3702 }; 3703 }; 3704 3705 cpu2-thermal { 3706 polling-delay-passive = <250>; 3707 polling-delay = <1000>; 3708 3709 thermal-sensors = <&tsens0 8>; 3710 3711 trips { 3712 cpu2_alert0: trip-point0 { 3713 temperature = <75000>; 3714 hysteresis = <2000>; 3715 type = "passive"; 3716 }; 3717 3718 cpu2_crit: cpu-crit { 3719 temperature = <110000>; 3720 hysteresis = <2000>; 3721 type = "critical"; 3722 }; 3723 }; 3724 }; 3725 3726 cpu3-thermal { 3727 polling-delay-passive = <250>; 3728 polling-delay = <1000>; 3729 3730 thermal-sensors = <&tsens0 10>; 3731 3732 trips { 3733 cpu3_alert0: trip-point0 { 3734 temperature = <75000>; 3735 hysteresis = <2000>; 3736 type = "passive"; 3737 }; 3738 3739 cpu3_crit: cpu-crit { 3740 temperature = <110000>; 3741 hysteresis = <2000>; 3742 type = "critical"; 3743 }; 3744 }; 3745 }; 3746 3747 gpu-top-thermal { 3748 polling-delay-passive = <250>; 3749 polling-delay = <1000>; 3750 3751 thermal-sensors = <&tsens1 6>; 3752 3753 trips { 3754 gpu1_alert0: trip-point0 { 3755 temperature = <90000>; 3756 hysteresis = <2000>; 3757 type = "passive"; 3758 }; 3759 }; 3760 3761 cooling-maps { 3762 map0 { 3763 trip = <&gpu1_alert0>; 3764 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3765 }; 3766 }; 3767 }; 3768 3769 gpu-bottom-thermal { 3770 polling-delay-passive = <250>; 3771 polling-delay = <1000>; 3772 3773 thermal-sensors = <&tsens1 7>; 3774 3775 trips { 3776 gpu2_alert0: trip-point0 { 3777 temperature = <90000>; 3778 hysteresis = <2000>; 3779 type = "passive"; 3780 }; 3781 }; 3782 3783 cooling-maps { 3784 map0 { 3785 trip = <&gpu2_alert0>; 3786 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3787 }; 3788 }; 3789 }; 3790 3791 m4m-thermal { 3792 polling-delay-passive = <250>; 3793 polling-delay = <1000>; 3794 3795 thermal-sensors = <&tsens0 1>; 3796 3797 trips { 3798 m4m_alert0: trip-point0 { 3799 temperature = <90000>; 3800 hysteresis = <2000>; 3801 type = "hot"; 3802 }; 3803 }; 3804 }; 3805 3806 l3-or-venus-thermal { 3807 polling-delay-passive = <250>; 3808 polling-delay = <1000>; 3809 3810 thermal-sensors = <&tsens0 2>; 3811 3812 trips { 3813 l3_or_venus_alert0: trip-point0 { 3814 temperature = <90000>; 3815 hysteresis = <2000>; 3816 type = "hot"; 3817 }; 3818 }; 3819 }; 3820 3821 cluster0-l2-thermal { 3822 polling-delay-passive = <250>; 3823 polling-delay = <1000>; 3824 3825 thermal-sensors = <&tsens0 7>; 3826 3827 trips { 3828 cluster0_l2_alert0: trip-point0 { 3829 temperature = <90000>; 3830 hysteresis = <2000>; 3831 type = "hot"; 3832 }; 3833 }; 3834 }; 3835 3836 cluster1-l2-thermal { 3837 polling-delay-passive = <250>; 3838 polling-delay = <1000>; 3839 3840 thermal-sensors = <&tsens0 12>; 3841 3842 trips { 3843 cluster1_l2_alert0: trip-point0 { 3844 temperature = <90000>; 3845 hysteresis = <2000>; 3846 type = "hot"; 3847 }; 3848 }; 3849 }; 3850 3851 camera-thermal { 3852 polling-delay-passive = <250>; 3853 polling-delay = <1000>; 3854 3855 thermal-sensors = <&tsens1 1>; 3856 3857 trips { 3858 camera_alert0: trip-point0 { 3859 temperature = <90000>; 3860 hysteresis = <2000>; 3861 type = "hot"; 3862 }; 3863 }; 3864 }; 3865 3866 q6-dsp-thermal { 3867 polling-delay-passive = <250>; 3868 polling-delay = <1000>; 3869 3870 thermal-sensors = <&tsens1 2>; 3871 3872 trips { 3873 q6_dsp_alert0: trip-point0 { 3874 temperature = <90000>; 3875 hysteresis = <2000>; 3876 type = "hot"; 3877 }; 3878 }; 3879 }; 3880 3881 mem-thermal { 3882 polling-delay-passive = <250>; 3883 polling-delay = <1000>; 3884 3885 thermal-sensors = <&tsens1 3>; 3886 3887 trips { 3888 mem_alert0: trip-point0 { 3889 temperature = <90000>; 3890 hysteresis = <2000>; 3891 type = "hot"; 3892 }; 3893 }; 3894 }; 3895 3896 modemtx-thermal { 3897 polling-delay-passive = <250>; 3898 polling-delay = <1000>; 3899 3900 thermal-sensors = <&tsens1 4>; 3901 3902 trips { 3903 modemtx_alert0: trip-point0 { 3904 temperature = <90000>; 3905 hysteresis = <2000>; 3906 type = "hot"; 3907 }; 3908 }; 3909 }; 3910 }; 3911 3912 timer { 3913 compatible = "arm,armv8-timer"; 3914 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 3915 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 3916 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 3917 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 3918 }; 3919}; 3920