1/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 */ 12 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/clock/qcom,gcc-msm8994.h> 15 16/ { 17 model = "Qualcomm Technologies, Inc. MSM 8992"; 18 compatible = "qcom,msm8992"; 19 // msm-id needed by bootloader for selecting correct blob 20 qcom,msm-id = <251 0>, <252 0>; 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 chosen { }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 cpu-map { 32 cluster0 { 33 core0 { 34 cpu = <&CPU0>; 35 }; 36 }; 37 }; 38 39 CPU0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53", "arm,armv8"; 42 reg = <0x0 0x0>; 43 next-level-cache = <&L2_0>; 44 L2_0: l2-cache { 45 compatible = "cache"; 46 cache-level = <2>; 47 }; 48 }; 49 }; 50 51 timer { 52 compatible = "arm,armv8-timer"; 53 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 54 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 55 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 56 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 57 }; 58 59 xo_board: xo_board { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <19200000>; 63 }; 64 65 sleep_clk: sleep_clk { 66 compatible = "fixed-clock"; 67 #clock-cells = <0>; 68 clock-frequency = <32768>; 69 }; 70 71 soc { 72 #address-cells = <1>; 73 #size-cells = <1>; 74 ranges = <0 0 0 0xffffffff>; 75 compatible = "simple-bus"; 76 77 intc: interrupt-controller@f9000000 { 78 compatible = "qcom,msm-qgic2"; 79 interrupt-controller; 80 #interrupt-cells = <3>; 81 reg = <0xf9000000 0x1000>, 82 <0xf9002000 0x1000>; 83 }; 84 85 timer@f9020000 { 86 #address-cells = <1>; 87 #size-cells = <1>; 88 ranges; 89 compatible = "arm,armv7-timer-mem"; 90 reg = <0xf9020000 0x1000>; 91 92 frame@f9021000 { 93 frame-number = <0>; 94 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 96 reg = <0xf9021000 0x1000>, 97 <0xf9022000 0x1000>; 98 }; 99 100 frame@f9023000 { 101 frame-number = <1>; 102 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 103 reg = <0xf9023000 0x1000>; 104 status = "disabled"; 105 }; 106 107 frame@f9024000 { 108 frame-number = <2>; 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 reg = <0xf9024000 0x1000>; 111 status = "disabled"; 112 }; 113 114 frame@f9025000 { 115 frame-number = <3>; 116 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 117 reg = <0xf9025000 0x1000>; 118 status = "disabled"; 119 }; 120 121 frame@f9026000 { 122 frame-number = <4>; 123 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 124 reg = <0xf9026000 0x1000>; 125 status = "disabled"; 126 }; 127 128 frame@f9027000 { 129 frame-number = <5>; 130 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 131 reg = <0xf9027000 0x1000>; 132 status = "disabled"; 133 }; 134 135 frame@f9028000 { 136 frame-number = <6>; 137 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 138 reg = <0xf9028000 0x1000>; 139 status = "disabled"; 140 }; 141 }; 142 143 restart@fc4ab000 { 144 compatible = "qcom,pshold"; 145 reg = <0xfc4ab000 0x4>; 146 }; 147 148 msmgpio: pinctrl@fd510000 { 149 compatible = "qcom,msm8994-pinctrl"; 150 reg = <0xfd510000 0x4000>; 151 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 152 gpio-controller; 153 #gpio-cells = <2>; 154 interrupt-controller; 155 #interrupt-cells = <2>; 156 }; 157 158 blsp1_uart2: serial@f991e000 { 159 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 160 reg = <0xf991e000 0x1000>; 161 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>; 162 status = "disabled"; 163 clock-names = "core", "iface"; 164 clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, 165 <&clock_gcc GCC_BLSP1_AHB_CLK>; 166 }; 167 168 clock_gcc: clock-controller@fc400000 { 169 compatible = "qcom,gcc-msm8994"; 170 #clock-cells = <1>; 171 #reset-cells = <1>; 172 #power-domain-cells = <1>; 173 reg = <0xfc400000 0x2000>; 174 }; 175 }; 176 177 memory { 178 device_type = "memory"; 179 reg = <0 0 0 0>; // bootloader will update 180 }; 181}; 182 183 184#include "msm8992-pins.dtsi" 185