1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/arm/coresight-cti-dt.h> 7#include <dt-bindings/clock/qcom,gcc-msm8916.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8916.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8916.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 mmc0 = &sdhc_1; /* SDC1 eMMC slot */ 23 mmc1 = &sdhc_2; /* SDC2 SD card slot */ 24 }; 25 26 chosen { }; 27 28 memory@80000000 { 29 device_type = "memory"; 30 /* We expect the bootloader to fill in the reg */ 31 reg = <0 0x80000000 0 0>; 32 }; 33 34 reserved-memory { 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges; 38 39 tz-apps@86000000 { 40 reg = <0x0 0x86000000 0x0 0x300000>; 41 no-map; 42 }; 43 44 smem@86300000 { 45 compatible = "qcom,smem"; 46 reg = <0x0 0x86300000 0x0 0x100000>; 47 no-map; 48 49 hwlocks = <&tcsr_mutex 3>; 50 qcom,rpm-msg-ram = <&rpm_msg_ram>; 51 }; 52 53 hypervisor@86400000 { 54 reg = <0x0 0x86400000 0x0 0x100000>; 55 no-map; 56 }; 57 58 tz@86500000 { 59 reg = <0x0 0x86500000 0x0 0x180000>; 60 no-map; 61 }; 62 63 reserved@86680000 { 64 reg = <0x0 0x86680000 0x0 0x80000>; 65 no-map; 66 }; 67 68 rmtfs@86700000 { 69 compatible = "qcom,rmtfs-mem"; 70 reg = <0x0 0x86700000 0x0 0xe0000>; 71 no-map; 72 73 qcom,client-id = <1>; 74 }; 75 76 rfsa@867e0000 { 77 reg = <0x0 0x867e0000 0x0 0x20000>; 78 no-map; 79 }; 80 81 mpss_mem: mpss@86800000 { 82 reg = <0x0 0x86800000 0x0 0x2b00000>; 83 no-map; 84 }; 85 86 wcnss_mem: wcnss@89300000 { 87 reg = <0x0 0x89300000 0x0 0x600000>; 88 no-map; 89 }; 90 91 venus_mem: venus@89900000 { 92 reg = <0x0 0x89900000 0x0 0x600000>; 93 no-map; 94 }; 95 96 mba_mem: mba@8ea00000 { 97 no-map; 98 reg = <0 0x8ea00000 0 0x100000>; 99 }; 100 }; 101 102 clocks { 103 xo_board: xo-board { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 clock-frequency = <19200000>; 107 }; 108 109 sleep_clk: sleep-clk { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <32768>; 113 }; 114 }; 115 116 cpus { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 CPU0: cpu@0 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53"; 123 reg = <0x0>; 124 next-level-cache = <&L2_0>; 125 enable-method = "psci"; 126 clocks = <&apcs>; 127 operating-points-v2 = <&cpu_opp_table>; 128 #cooling-cells = <2>; 129 power-domains = <&CPU_PD0>; 130 power-domain-names = "psci"; 131 qcom,acc = <&cpu0_acc>; 132 qcom,saw = <&cpu0_saw>; 133 }; 134 135 CPU1: cpu@1 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a53"; 138 reg = <0x1>; 139 next-level-cache = <&L2_0>; 140 enable-method = "psci"; 141 clocks = <&apcs>; 142 operating-points-v2 = <&cpu_opp_table>; 143 #cooling-cells = <2>; 144 power-domains = <&CPU_PD1>; 145 power-domain-names = "psci"; 146 qcom,acc = <&cpu1_acc>; 147 qcom,saw = <&cpu1_saw>; 148 }; 149 150 CPU2: cpu@2 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a53"; 153 reg = <0x2>; 154 next-level-cache = <&L2_0>; 155 enable-method = "psci"; 156 clocks = <&apcs>; 157 operating-points-v2 = <&cpu_opp_table>; 158 #cooling-cells = <2>; 159 power-domains = <&CPU_PD2>; 160 power-domain-names = "psci"; 161 qcom,acc = <&cpu2_acc>; 162 qcom,saw = <&cpu2_saw>; 163 }; 164 165 CPU3: cpu@3 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a53"; 168 reg = <0x3>; 169 next-level-cache = <&L2_0>; 170 enable-method = "psci"; 171 clocks = <&apcs>; 172 operating-points-v2 = <&cpu_opp_table>; 173 #cooling-cells = <2>; 174 power-domains = <&CPU_PD3>; 175 power-domain-names = "psci"; 176 qcom,acc = <&cpu3_acc>; 177 qcom,saw = <&cpu3_saw>; 178 }; 179 180 L2_0: l2-cache { 181 compatible = "cache"; 182 cache-level = <2>; 183 cache-unified; 184 }; 185 186 idle-states { 187 entry-method = "psci"; 188 189 CPU_SLEEP_0: cpu-sleep-0 { 190 compatible = "arm,idle-state"; 191 idle-state-name = "standalone-power-collapse"; 192 arm,psci-suspend-param = <0x40000002>; 193 entry-latency-us = <130>; 194 exit-latency-us = <150>; 195 min-residency-us = <2000>; 196 local-timer-stop; 197 }; 198 }; 199 200 domain-idle-states { 201 202 CLUSTER_RET: cluster-retention { 203 compatible = "domain-idle-state"; 204 arm,psci-suspend-param = <0x41000012>; 205 entry-latency-us = <500>; 206 exit-latency-us = <500>; 207 min-residency-us = <2000>; 208 }; 209 210 CLUSTER_PWRDN: cluster-gdhs { 211 compatible = "domain-idle-state"; 212 arm,psci-suspend-param = <0x41000032>; 213 entry-latency-us = <2000>; 214 exit-latency-us = <2000>; 215 min-residency-us = <6000>; 216 }; 217 }; 218 }; 219 220 cpu_opp_table: opp-table-cpu { 221 compatible = "operating-points-v2"; 222 opp-shared; 223 224 opp-200000000 { 225 opp-hz = /bits/ 64 <200000000>; 226 }; 227 opp-400000000 { 228 opp-hz = /bits/ 64 <400000000>; 229 }; 230 opp-800000000 { 231 opp-hz = /bits/ 64 <800000000>; 232 }; 233 opp-998400000 { 234 opp-hz = /bits/ 64 <998400000>; 235 }; 236 }; 237 238 firmware { 239 scm: scm { 240 compatible = "qcom,scm-msm8916", "qcom,scm"; 241 clocks = <&gcc GCC_CRYPTO_CLK>, 242 <&gcc GCC_CRYPTO_AXI_CLK>, 243 <&gcc GCC_CRYPTO_AHB_CLK>; 244 clock-names = "core", "bus", "iface"; 245 #reset-cells = <1>; 246 247 qcom,dload-mode = <&tcsr 0x6100>; 248 }; 249 }; 250 251 pmu { 252 compatible = "arm,cortex-a53-pmu"; 253 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 254 }; 255 256 psci { 257 compatible = "arm,psci-1.0"; 258 method = "smc"; 259 260 CPU_PD0: power-domain-cpu0 { 261 #power-domain-cells = <0>; 262 power-domains = <&CLUSTER_PD>; 263 domain-idle-states = <&CPU_SLEEP_0>; 264 }; 265 266 CPU_PD1: power-domain-cpu1 { 267 #power-domain-cells = <0>; 268 power-domains = <&CLUSTER_PD>; 269 domain-idle-states = <&CPU_SLEEP_0>; 270 }; 271 272 CPU_PD2: power-domain-cpu2 { 273 #power-domain-cells = <0>; 274 power-domains = <&CLUSTER_PD>; 275 domain-idle-states = <&CPU_SLEEP_0>; 276 }; 277 278 CPU_PD3: power-domain-cpu3 { 279 #power-domain-cells = <0>; 280 power-domains = <&CLUSTER_PD>; 281 domain-idle-states = <&CPU_SLEEP_0>; 282 }; 283 284 CLUSTER_PD: power-domain-cluster { 285 #power-domain-cells = <0>; 286 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; 287 }; 288 }; 289 290 smd { 291 compatible = "qcom,smd"; 292 293 rpm { 294 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 295 qcom,ipc = <&apcs 8 0>; 296 qcom,smd-edge = <15>; 297 298 rpm_requests: rpm-requests { 299 compatible = "qcom,rpm-msm8916"; 300 qcom,smd-channels = "rpm_requests"; 301 302 rpmcc: clock-controller { 303 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; 304 #clock-cells = <1>; 305 clocks = <&xo_board>; 306 clock-names = "xo"; 307 }; 308 309 rpmpd: power-controller { 310 compatible = "qcom,msm8916-rpmpd"; 311 #power-domain-cells = <1>; 312 operating-points-v2 = <&rpmpd_opp_table>; 313 314 rpmpd_opp_table: opp-table { 315 compatible = "operating-points-v2"; 316 317 rpmpd_opp_ret: opp1 { 318 opp-level = <1>; 319 }; 320 rpmpd_opp_svs_krait: opp2 { 321 opp-level = <2>; 322 }; 323 rpmpd_opp_svs_soc: opp3 { 324 opp-level = <3>; 325 }; 326 rpmpd_opp_nom: opp4 { 327 opp-level = <4>; 328 }; 329 rpmpd_opp_turbo: opp5 { 330 opp-level = <5>; 331 }; 332 rpmpd_opp_super_turbo: opp6 { 333 opp-level = <6>; 334 }; 335 }; 336 }; 337 }; 338 }; 339 }; 340 341 smp2p-hexagon { 342 compatible = "qcom,smp2p"; 343 qcom,smem = <435>, <428>; 344 345 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 346 347 qcom,ipc = <&apcs 8 14>; 348 349 qcom,local-pid = <0>; 350 qcom,remote-pid = <1>; 351 352 hexagon_smp2p_out: master-kernel { 353 qcom,entry-name = "master-kernel"; 354 355 #qcom,smem-state-cells = <1>; 356 }; 357 358 hexagon_smp2p_in: slave-kernel { 359 qcom,entry-name = "slave-kernel"; 360 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 }; 364 }; 365 366 smp2p-wcnss { 367 compatible = "qcom,smp2p"; 368 qcom,smem = <451>, <431>; 369 370 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 371 372 qcom,ipc = <&apcs 8 18>; 373 374 qcom,local-pid = <0>; 375 qcom,remote-pid = <4>; 376 377 wcnss_smp2p_out: master-kernel { 378 qcom,entry-name = "master-kernel"; 379 380 #qcom,smem-state-cells = <1>; 381 }; 382 383 wcnss_smp2p_in: slave-kernel { 384 qcom,entry-name = "slave-kernel"; 385 386 interrupt-controller; 387 #interrupt-cells = <2>; 388 }; 389 }; 390 391 smsm { 392 compatible = "qcom,smsm"; 393 394 #address-cells = <1>; 395 #size-cells = <0>; 396 397 qcom,ipc-1 = <&apcs 8 13>; 398 qcom,ipc-3 = <&apcs 8 19>; 399 400 apps_smsm: apps@0 { 401 reg = <0>; 402 403 #qcom,smem-state-cells = <1>; 404 }; 405 406 hexagon_smsm: hexagon@1 { 407 reg = <1>; 408 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 409 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 }; 413 414 wcnss_smsm: wcnss@6 { 415 reg = <6>; 416 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 417 418 interrupt-controller; 419 #interrupt-cells = <2>; 420 }; 421 }; 422 423 soc: soc@0 { 424 #address-cells = <1>; 425 #size-cells = <1>; 426 ranges = <0 0 0 0xffffffff>; 427 compatible = "simple-bus"; 428 429 rng@22000 { 430 compatible = "qcom,prng"; 431 reg = <0x00022000 0x200>; 432 clocks = <&gcc GCC_PRNG_AHB_CLK>; 433 clock-names = "core"; 434 }; 435 436 restart@4ab000 { 437 compatible = "qcom,pshold"; 438 reg = <0x004ab000 0x4>; 439 }; 440 441 qfprom: qfprom@5c000 { 442 compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 443 reg = <0x0005c000 0x1000>; 444 #address-cells = <1>; 445 #size-cells = <1>; 446 447 tsens_base1: base1@d0 { 448 reg = <0xd0 0x1>; 449 bits = <0 7>; 450 }; 451 452 tsens_s0_p1: s0-p1@d0 { 453 reg = <0xd0 0x2>; 454 bits = <7 5>; 455 }; 456 457 tsens_s0_p2: s0-p2@d1 { 458 reg = <0xd1 0x2>; 459 bits = <4 5>; 460 }; 461 462 tsens_s1_p1: s1-p1@d2 { 463 reg = <0xd2 0x1>; 464 bits = <1 5>; 465 }; 466 tsens_s1_p2: s1-p2@d2 { 467 reg = <0xd2 0x2>; 468 bits = <6 5>; 469 }; 470 tsens_s2_p1: s2-p1@d3 { 471 reg = <0xd3 0x1>; 472 bits = <3 5>; 473 }; 474 475 tsens_s2_p2: s2-p2@d4 { 476 reg = <0xd4 0x1>; 477 bits = <0 5>; 478 }; 479 480 // no tsens with hw_id 3 481 482 tsens_s4_p1: s4-p1@d4 { 483 reg = <0xd4 0x2>; 484 bits = <5 5>; 485 }; 486 487 tsens_s4_p2: s4-p2@d5 { 488 reg = <0xd5 0x1>; 489 bits = <2 5>; 490 }; 491 492 tsens_s5_p1: s5-p1@d5 { 493 reg = <0xd5 0x2>; 494 bits = <7 5>; 495 }; 496 497 tsens_s5_p2: s5-p2@d6 { 498 reg = <0xd6 0x2>; 499 bits = <4 5>; 500 }; 501 502 tsens_base2: base2@d7 { 503 reg = <0xd7 0x1>; 504 bits = <1 7>; 505 }; 506 507 tsens_mode: mode@ef { 508 reg = <0xef 0x1>; 509 bits = <5 3>; 510 }; 511 }; 512 513 rpm_msg_ram: sram@60000 { 514 compatible = "qcom,rpm-msg-ram"; 515 reg = <0x00060000 0x8000>; 516 }; 517 518 sram@290000 { 519 compatible = "qcom,msm8916-rpm-stats"; 520 reg = <0x00290000 0x10000>; 521 }; 522 523 bimc: interconnect@400000 { 524 compatible = "qcom,msm8916-bimc"; 525 reg = <0x00400000 0x62000>; 526 #interconnect-cells = <1>; 527 clock-names = "bus", "bus_a"; 528 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 529 <&rpmcc RPM_SMD_BIMC_A_CLK>; 530 }; 531 532 tsens: thermal-sensor@4a9000 { 533 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 534 reg = <0x004a9000 0x1000>, /* TM */ 535 <0x004a8000 0x1000>; /* SROT */ 536 537 // no hw_id 3 538 nvmem-cells = <&tsens_mode>, 539 <&tsens_base1>, <&tsens_base2>, 540 <&tsens_s0_p1>, <&tsens_s0_p2>, 541 <&tsens_s1_p1>, <&tsens_s1_p2>, 542 <&tsens_s2_p1>, <&tsens_s2_p2>, 543 <&tsens_s4_p1>, <&tsens_s4_p2>, 544 <&tsens_s5_p1>, <&tsens_s5_p2>; 545 nvmem-cell-names = "mode", 546 "base1", "base2", 547 "s0_p1", "s0_p2", 548 "s1_p1", "s1_p2", 549 "s2_p1", "s2_p2", 550 "s4_p1", "s4_p2", 551 "s5_p1", "s5_p2"; 552 #qcom,sensors = <5>; 553 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 554 interrupt-names = "uplow"; 555 #thermal-sensor-cells = <1>; 556 }; 557 558 pcnoc: interconnect@500000 { 559 compatible = "qcom,msm8916-pcnoc"; 560 reg = <0x00500000 0x11000>; 561 #interconnect-cells = <1>; 562 clock-names = "bus", "bus_a"; 563 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 564 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 565 }; 566 567 snoc: interconnect@580000 { 568 compatible = "qcom,msm8916-snoc"; 569 reg = <0x00580000 0x14000>; 570 #interconnect-cells = <1>; 571 clock-names = "bus", "bus_a"; 572 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 573 <&rpmcc RPM_SMD_SNOC_A_CLK>; 574 }; 575 576 stm: stm@802000 { 577 compatible = "arm,coresight-stm", "arm,primecell"; 578 reg = <0x00802000 0x1000>, 579 <0x09280000 0x180000>; 580 reg-names = "stm-base", "stm-stimulus-base"; 581 582 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 583 clock-names = "apb_pclk", "atclk"; 584 585 status = "disabled"; 586 587 out-ports { 588 port { 589 stm_out: endpoint { 590 remote-endpoint = <&funnel0_in7>; 591 }; 592 }; 593 }; 594 }; 595 596 /* System CTIs */ 597 /* CTI 0 - TMC connections */ 598 cti0: cti@810000 { 599 compatible = "arm,coresight-cti", "arm,primecell"; 600 reg = <0x00810000 0x1000>; 601 602 clocks = <&rpmcc RPM_QDSS_CLK>; 603 clock-names = "apb_pclk"; 604 605 status = "disabled"; 606 }; 607 608 /* CTI 1 - TPIU connections */ 609 cti1: cti@811000 { 610 compatible = "arm,coresight-cti", "arm,primecell"; 611 reg = <0x00811000 0x1000>; 612 613 clocks = <&rpmcc RPM_QDSS_CLK>; 614 clock-names = "apb_pclk"; 615 616 status = "disabled"; 617 }; 618 619 /* CTIs 2-11 - no information - not instantiated */ 620 621 tpiu: tpiu@820000 { 622 compatible = "arm,coresight-tpiu", "arm,primecell"; 623 reg = <0x00820000 0x1000>; 624 625 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 626 clock-names = "apb_pclk", "atclk"; 627 628 status = "disabled"; 629 630 in-ports { 631 port { 632 tpiu_in: endpoint { 633 remote-endpoint = <&replicator_out1>; 634 }; 635 }; 636 }; 637 }; 638 639 funnel0: funnel@821000 { 640 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 641 reg = <0x00821000 0x1000>; 642 643 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 644 clock-names = "apb_pclk", "atclk"; 645 646 status = "disabled"; 647 648 in-ports { 649 #address-cells = <1>; 650 #size-cells = <0>; 651 652 /* 653 * Not described input ports: 654 * 0 - connected to Resource and Power Manger CPU ETM 655 * 1 - not-connected 656 * 2 - connected to Modem CPU ETM 657 * 3 - not-connected 658 * 5 - not-connected 659 * 6 - connected trought funnel to Wireless CPU ETM 660 * 7 - connected to STM component 661 */ 662 663 port@4 { 664 reg = <4>; 665 funnel0_in4: endpoint { 666 remote-endpoint = <&funnel1_out>; 667 }; 668 }; 669 670 port@7 { 671 reg = <7>; 672 funnel0_in7: endpoint { 673 remote-endpoint = <&stm_out>; 674 }; 675 }; 676 }; 677 678 out-ports { 679 port { 680 funnel0_out: endpoint { 681 remote-endpoint = <&etf_in>; 682 }; 683 }; 684 }; 685 }; 686 687 replicator: replicator@824000 { 688 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 689 reg = <0x00824000 0x1000>; 690 691 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 692 clock-names = "apb_pclk", "atclk"; 693 694 status = "disabled"; 695 696 out-ports { 697 #address-cells = <1>; 698 #size-cells = <0>; 699 700 port@0 { 701 reg = <0>; 702 replicator_out0: endpoint { 703 remote-endpoint = <&etr_in>; 704 }; 705 }; 706 port@1 { 707 reg = <1>; 708 replicator_out1: endpoint { 709 remote-endpoint = <&tpiu_in>; 710 }; 711 }; 712 }; 713 714 in-ports { 715 port { 716 replicator_in: endpoint { 717 remote-endpoint = <&etf_out>; 718 }; 719 }; 720 }; 721 }; 722 723 etf: etf@825000 { 724 compatible = "arm,coresight-tmc", "arm,primecell"; 725 reg = <0x00825000 0x1000>; 726 727 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 728 clock-names = "apb_pclk", "atclk"; 729 730 status = "disabled"; 731 732 in-ports { 733 port { 734 etf_in: endpoint { 735 remote-endpoint = <&funnel0_out>; 736 }; 737 }; 738 }; 739 740 out-ports { 741 port { 742 etf_out: endpoint { 743 remote-endpoint = <&replicator_in>; 744 }; 745 }; 746 }; 747 }; 748 749 etr: etr@826000 { 750 compatible = "arm,coresight-tmc", "arm,primecell"; 751 reg = <0x00826000 0x1000>; 752 753 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 754 clock-names = "apb_pclk", "atclk"; 755 756 status = "disabled"; 757 758 in-ports { 759 port { 760 etr_in: endpoint { 761 remote-endpoint = <&replicator_out0>; 762 }; 763 }; 764 }; 765 }; 766 767 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ 768 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 769 reg = <0x00841000 0x1000>; 770 771 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 772 clock-names = "apb_pclk", "atclk"; 773 774 status = "disabled"; 775 776 in-ports { 777 #address-cells = <1>; 778 #size-cells = <0>; 779 780 port@0 { 781 reg = <0>; 782 funnel1_in0: endpoint { 783 remote-endpoint = <&etm0_out>; 784 }; 785 }; 786 port@1 { 787 reg = <1>; 788 funnel1_in1: endpoint { 789 remote-endpoint = <&etm1_out>; 790 }; 791 }; 792 port@2 { 793 reg = <2>; 794 funnel1_in2: endpoint { 795 remote-endpoint = <&etm2_out>; 796 }; 797 }; 798 port@3 { 799 reg = <3>; 800 funnel1_in3: endpoint { 801 remote-endpoint = <&etm3_out>; 802 }; 803 }; 804 }; 805 806 out-ports { 807 port { 808 funnel1_out: endpoint { 809 remote-endpoint = <&funnel0_in4>; 810 }; 811 }; 812 }; 813 }; 814 815 debug0: debug@850000 { 816 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 817 reg = <0x00850000 0x1000>; 818 clocks = <&rpmcc RPM_QDSS_CLK>; 819 clock-names = "apb_pclk"; 820 cpu = <&CPU0>; 821 status = "disabled"; 822 }; 823 824 debug1: debug@852000 { 825 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 826 reg = <0x00852000 0x1000>; 827 clocks = <&rpmcc RPM_QDSS_CLK>; 828 clock-names = "apb_pclk"; 829 cpu = <&CPU1>; 830 status = "disabled"; 831 }; 832 833 debug2: debug@854000 { 834 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 835 reg = <0x00854000 0x1000>; 836 clocks = <&rpmcc RPM_QDSS_CLK>; 837 clock-names = "apb_pclk"; 838 cpu = <&CPU2>; 839 status = "disabled"; 840 }; 841 842 debug3: debug@856000 { 843 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 844 reg = <0x00856000 0x1000>; 845 clocks = <&rpmcc RPM_QDSS_CLK>; 846 clock-names = "apb_pclk"; 847 cpu = <&CPU3>; 848 status = "disabled"; 849 }; 850 851 /* Core CTIs; CTIs 12-15 */ 852 /* CTI - CPU-0 */ 853 cti12: cti@858000 { 854 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 855 "arm,primecell"; 856 reg = <0x00858000 0x1000>; 857 858 clocks = <&rpmcc RPM_QDSS_CLK>; 859 clock-names = "apb_pclk"; 860 861 cpu = <&CPU0>; 862 arm,cs-dev-assoc = <&etm0>; 863 864 status = "disabled"; 865 }; 866 867 /* CTI - CPU-1 */ 868 cti13: cti@859000 { 869 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 870 "arm,primecell"; 871 reg = <0x00859000 0x1000>; 872 873 clocks = <&rpmcc RPM_QDSS_CLK>; 874 clock-names = "apb_pclk"; 875 876 cpu = <&CPU1>; 877 arm,cs-dev-assoc = <&etm1>; 878 879 status = "disabled"; 880 }; 881 882 /* CTI - CPU-2 */ 883 cti14: cti@85a000 { 884 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 885 "arm,primecell"; 886 reg = <0x0085a000 0x1000>; 887 888 clocks = <&rpmcc RPM_QDSS_CLK>; 889 clock-names = "apb_pclk"; 890 891 cpu = <&CPU2>; 892 arm,cs-dev-assoc = <&etm2>; 893 894 status = "disabled"; 895 }; 896 897 /* CTI - CPU-3 */ 898 cti15: cti@85b000 { 899 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 900 "arm,primecell"; 901 reg = <0x0085b000 0x1000>; 902 903 clocks = <&rpmcc RPM_QDSS_CLK>; 904 clock-names = "apb_pclk"; 905 906 cpu = <&CPU3>; 907 arm,cs-dev-assoc = <&etm3>; 908 909 status = "disabled"; 910 }; 911 912 etm0: etm@85c000 { 913 compatible = "arm,coresight-etm4x", "arm,primecell"; 914 reg = <0x0085c000 0x1000>; 915 916 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 917 clock-names = "apb_pclk", "atclk"; 918 arm,coresight-loses-context-with-cpu; 919 920 cpu = <&CPU0>; 921 922 status = "disabled"; 923 924 out-ports { 925 port { 926 etm0_out: endpoint { 927 remote-endpoint = <&funnel1_in0>; 928 }; 929 }; 930 }; 931 }; 932 933 etm1: etm@85d000 { 934 compatible = "arm,coresight-etm4x", "arm,primecell"; 935 reg = <0x0085d000 0x1000>; 936 937 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 938 clock-names = "apb_pclk", "atclk"; 939 arm,coresight-loses-context-with-cpu; 940 941 cpu = <&CPU1>; 942 943 status = "disabled"; 944 945 out-ports { 946 port { 947 etm1_out: endpoint { 948 remote-endpoint = <&funnel1_in1>; 949 }; 950 }; 951 }; 952 }; 953 954 etm2: etm@85e000 { 955 compatible = "arm,coresight-etm4x", "arm,primecell"; 956 reg = <0x0085e000 0x1000>; 957 958 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 959 clock-names = "apb_pclk", "atclk"; 960 arm,coresight-loses-context-with-cpu; 961 962 cpu = <&CPU2>; 963 964 status = "disabled"; 965 966 out-ports { 967 port { 968 etm2_out: endpoint { 969 remote-endpoint = <&funnel1_in2>; 970 }; 971 }; 972 }; 973 }; 974 975 etm3: etm@85f000 { 976 compatible = "arm,coresight-etm4x", "arm,primecell"; 977 reg = <0x0085f000 0x1000>; 978 979 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 980 clock-names = "apb_pclk", "atclk"; 981 arm,coresight-loses-context-with-cpu; 982 983 cpu = <&CPU3>; 984 985 status = "disabled"; 986 987 out-ports { 988 port { 989 etm3_out: endpoint { 990 remote-endpoint = <&funnel1_in3>; 991 }; 992 }; 993 }; 994 }; 995 996 msmgpio: pinctrl@1000000 { 997 compatible = "qcom,msm8916-pinctrl"; 998 reg = <0x01000000 0x300000>; 999 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1000 gpio-controller; 1001 gpio-ranges = <&msmgpio 0 0 122>; 1002 #gpio-cells = <2>; 1003 interrupt-controller; 1004 #interrupt-cells = <2>; 1005 }; 1006 1007 gcc: clock-controller@1800000 { 1008 compatible = "qcom,gcc-msm8916"; 1009 #clock-cells = <1>; 1010 #reset-cells = <1>; 1011 #power-domain-cells = <1>; 1012 reg = <0x01800000 0x80000>; 1013 clocks = <&xo_board>, 1014 <&sleep_clk>, 1015 <&dsi_phy0 1>, 1016 <&dsi_phy0 0>, 1017 <0>, 1018 <0>, 1019 <0>; 1020 clock-names = "xo", 1021 "sleep_clk", 1022 "dsi0pll", 1023 "dsi0pllbyte", 1024 "ext_mclk", 1025 "ext_pri_i2s", 1026 "ext_sec_i2s"; 1027 }; 1028 1029 tcsr_mutex: hwlock@1905000 { 1030 compatible = "qcom,tcsr-mutex"; 1031 reg = <0x01905000 0x20000>; 1032 #hwlock-cells = <1>; 1033 }; 1034 1035 tcsr: syscon@1937000 { 1036 compatible = "qcom,tcsr-msm8916", "syscon"; 1037 reg = <0x01937000 0x30000>; 1038 }; 1039 1040 mdss: display-subsystem@1a00000 { 1041 status = "disabled"; 1042 compatible = "qcom,mdss"; 1043 reg = <0x01a00000 0x1000>, 1044 <0x01ac8000 0x3000>; 1045 reg-names = "mdss_phys", "vbif_phys"; 1046 1047 power-domains = <&gcc MDSS_GDSC>; 1048 1049 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1050 <&gcc GCC_MDSS_AXI_CLK>, 1051 <&gcc GCC_MDSS_VSYNC_CLK>; 1052 clock-names = "iface", 1053 "bus", 1054 "vsync"; 1055 1056 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1057 1058 interrupt-controller; 1059 #interrupt-cells = <1>; 1060 1061 #address-cells = <1>; 1062 #size-cells = <1>; 1063 ranges; 1064 1065 mdp: display-controller@1a01000 { 1066 compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; 1067 reg = <0x01a01000 0x89000>; 1068 reg-names = "mdp_phys"; 1069 1070 interrupt-parent = <&mdss>; 1071 interrupts = <0>; 1072 1073 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1074 <&gcc GCC_MDSS_AXI_CLK>, 1075 <&gcc GCC_MDSS_MDP_CLK>, 1076 <&gcc GCC_MDSS_VSYNC_CLK>; 1077 clock-names = "iface", 1078 "bus", 1079 "core", 1080 "vsync"; 1081 1082 iommus = <&apps_iommu 4>; 1083 1084 ports { 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 1088 port@0 { 1089 reg = <0>; 1090 mdp5_intf1_out: endpoint { 1091 remote-endpoint = <&dsi0_in>; 1092 }; 1093 }; 1094 }; 1095 }; 1096 1097 dsi0: dsi@1a98000 { 1098 compatible = "qcom,msm8916-dsi-ctrl", 1099 "qcom,mdss-dsi-ctrl"; 1100 reg = <0x01a98000 0x25c>; 1101 reg-names = "dsi_ctrl"; 1102 1103 interrupt-parent = <&mdss>; 1104 interrupts = <4>; 1105 1106 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1107 <&gcc PCLK0_CLK_SRC>; 1108 assigned-clock-parents = <&dsi_phy0 0>, 1109 <&dsi_phy0 1>; 1110 1111 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1112 <&gcc GCC_MDSS_AHB_CLK>, 1113 <&gcc GCC_MDSS_AXI_CLK>, 1114 <&gcc GCC_MDSS_BYTE0_CLK>, 1115 <&gcc GCC_MDSS_PCLK0_CLK>, 1116 <&gcc GCC_MDSS_ESC0_CLK>; 1117 clock-names = "mdp_core", 1118 "iface", 1119 "bus", 1120 "byte", 1121 "pixel", 1122 "core"; 1123 phys = <&dsi_phy0>; 1124 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 1128 ports { 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 1132 port@0 { 1133 reg = <0>; 1134 dsi0_in: endpoint { 1135 remote-endpoint = <&mdp5_intf1_out>; 1136 }; 1137 }; 1138 1139 port@1 { 1140 reg = <1>; 1141 dsi0_out: endpoint { 1142 }; 1143 }; 1144 }; 1145 }; 1146 1147 dsi_phy0: phy@1a98300 { 1148 compatible = "qcom,dsi-phy-28nm-lp"; 1149 reg = <0x01a98300 0xd4>, 1150 <0x01a98500 0x280>, 1151 <0x01a98780 0x30>; 1152 reg-names = "dsi_pll", 1153 "dsi_phy", 1154 "dsi_phy_regulator"; 1155 1156 #clock-cells = <1>; 1157 #phy-cells = <0>; 1158 1159 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1160 <&xo_board>; 1161 clock-names = "iface", "ref"; 1162 }; 1163 }; 1164 1165 camss: camss@1b00000 { 1166 compatible = "qcom,msm8916-camss"; 1167 reg = <0x01b0ac00 0x200>, 1168 <0x01b00030 0x4>, 1169 <0x01b0b000 0x200>, 1170 <0x01b00038 0x4>, 1171 <0x01b08000 0x100>, 1172 <0x01b08400 0x100>, 1173 <0x01b0a000 0x500>, 1174 <0x01b00020 0x10>, 1175 <0x01b10000 0x1000>; 1176 reg-names = "csiphy0", 1177 "csiphy0_clk_mux", 1178 "csiphy1", 1179 "csiphy1_clk_mux", 1180 "csid0", 1181 "csid1", 1182 "ispif", 1183 "csi_clk_mux", 1184 "vfe0"; 1185 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1186 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1187 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1188 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1189 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1190 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1191 interrupt-names = "csiphy0", 1192 "csiphy1", 1193 "csid0", 1194 "csid1", 1195 "ispif", 1196 "vfe0"; 1197 power-domains = <&gcc VFE_GDSC>; 1198 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1199 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1200 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1201 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1202 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1203 <&gcc GCC_CAMSS_CSI0_CLK>, 1204 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1205 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1206 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1207 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1208 <&gcc GCC_CAMSS_CSI1_CLK>, 1209 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1210 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1211 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1212 <&gcc GCC_CAMSS_AHB_CLK>, 1213 <&gcc GCC_CAMSS_VFE0_CLK>, 1214 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1215 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1216 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1217 clock-names = "top_ahb", 1218 "ispif_ahb", 1219 "csiphy0_timer", 1220 "csiphy1_timer", 1221 "csi0_ahb", 1222 "csi0", 1223 "csi0_phy", 1224 "csi0_pix", 1225 "csi0_rdi", 1226 "csi1_ahb", 1227 "csi1", 1228 "csi1_phy", 1229 "csi1_pix", 1230 "csi1_rdi", 1231 "ahb", 1232 "vfe0", 1233 "csi_vfe0", 1234 "vfe_ahb", 1235 "vfe_axi"; 1236 iommus = <&apps_iommu 3>; 1237 status = "disabled"; 1238 ports { 1239 #address-cells = <1>; 1240 #size-cells = <0>; 1241 }; 1242 }; 1243 1244 cci: cci@1b0c000 { 1245 compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 reg = <0x01b0c000 0x1000>; 1249 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1250 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1251 <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1252 <&gcc GCC_CAMSS_CCI_CLK>, 1253 <&gcc GCC_CAMSS_AHB_CLK>; 1254 clock-names = "camss_top_ahb", "cci_ahb", 1255 "cci", "camss_ahb"; 1256 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1257 <&gcc GCC_CAMSS_CCI_CLK>; 1258 assigned-clock-rates = <80000000>, <19200000>; 1259 pinctrl-names = "default"; 1260 pinctrl-0 = <&cci0_default>; 1261 status = "disabled"; 1262 1263 cci_i2c0: i2c-bus@0 { 1264 reg = <0>; 1265 clock-frequency = <400000>; 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 }; 1269 }; 1270 1271 gpu@1c00000 { 1272 compatible = "qcom,adreno-306.0", "qcom,adreno"; 1273 reg = <0x01c00000 0x20000>; 1274 reg-names = "kgsl_3d0_reg_memory"; 1275 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1276 interrupt-names = "kgsl_3d0_irq"; 1277 clock-names = 1278 "core", 1279 "iface", 1280 "mem", 1281 "mem_iface", 1282 "alt_mem_iface", 1283 "gfx3d"; 1284 clocks = 1285 <&gcc GCC_OXILI_GFX3D_CLK>, 1286 <&gcc GCC_OXILI_AHB_CLK>, 1287 <&gcc GCC_OXILI_GMEM_CLK>, 1288 <&gcc GCC_BIMC_GFX_CLK>, 1289 <&gcc GCC_BIMC_GPU_CLK>, 1290 <&gcc GFX3D_CLK_SRC>; 1291 power-domains = <&gcc OXILI_GDSC>; 1292 operating-points-v2 = <&gpu_opp_table>; 1293 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1294 1295 gpu_opp_table: opp-table { 1296 compatible = "operating-points-v2"; 1297 1298 opp-400000000 { 1299 opp-hz = /bits/ 64 <400000000>; 1300 }; 1301 opp-19200000 { 1302 opp-hz = /bits/ 64 <19200000>; 1303 }; 1304 }; 1305 }; 1306 1307 venus: video-codec@1d00000 { 1308 compatible = "qcom,msm8916-venus"; 1309 reg = <0x01d00000 0xff000>; 1310 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1311 power-domains = <&gcc VENUS_GDSC>; 1312 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1313 <&gcc GCC_VENUS0_AHB_CLK>, 1314 <&gcc GCC_VENUS0_AXI_CLK>; 1315 clock-names = "core", "iface", "bus"; 1316 iommus = <&apps_iommu 5>; 1317 memory-region = <&venus_mem>; 1318 status = "okay"; 1319 1320 video-decoder { 1321 compatible = "venus-decoder"; 1322 }; 1323 1324 video-encoder { 1325 compatible = "venus-encoder"; 1326 }; 1327 }; 1328 1329 apps_iommu: iommu@1ef0000 { 1330 #address-cells = <1>; 1331 #size-cells = <1>; 1332 #iommu-cells = <1>; 1333 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1334 ranges = <0 0x01e20000 0x40000>; 1335 reg = <0x01ef0000 0x3000>; 1336 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1337 <&gcc GCC_APSS_TCU_CLK>; 1338 clock-names = "iface", "bus"; 1339 qcom,iommu-secure-id = <17>; 1340 1341 /* VFE */ 1342 iommu-ctx@3000 { 1343 compatible = "qcom,msm-iommu-v1-sec"; 1344 reg = <0x3000 0x1000>; 1345 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1346 }; 1347 1348 /* MDP_0 */ 1349 iommu-ctx@4000 { 1350 compatible = "qcom,msm-iommu-v1-ns"; 1351 reg = <0x4000 0x1000>; 1352 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1353 }; 1354 1355 /* VENUS_NS */ 1356 iommu-ctx@5000 { 1357 compatible = "qcom,msm-iommu-v1-sec"; 1358 reg = <0x5000 0x1000>; 1359 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1360 }; 1361 }; 1362 1363 gpu_iommu: iommu@1f08000 { 1364 #address-cells = <1>; 1365 #size-cells = <1>; 1366 #iommu-cells = <1>; 1367 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1368 ranges = <0 0x01f08000 0x10000>; 1369 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1370 <&gcc GCC_GFX_TCU_CLK>; 1371 clock-names = "iface", "bus"; 1372 qcom,iommu-secure-id = <18>; 1373 1374 /* GFX3D_USER */ 1375 iommu-ctx@1000 { 1376 compatible = "qcom,msm-iommu-v1-ns"; 1377 reg = <0x1000 0x1000>; 1378 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1379 }; 1380 1381 /* GFX3D_PRIV */ 1382 iommu-ctx@2000 { 1383 compatible = "qcom,msm-iommu-v1-ns"; 1384 reg = <0x2000 0x1000>; 1385 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1386 }; 1387 }; 1388 1389 spmi_bus: spmi@200f000 { 1390 compatible = "qcom,spmi-pmic-arb"; 1391 reg = <0x0200f000 0x001000>, 1392 <0x02400000 0x400000>, 1393 <0x02c00000 0x400000>, 1394 <0x03800000 0x200000>, 1395 <0x0200a000 0x002100>; 1396 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1397 interrupt-names = "periph_irq"; 1398 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1399 qcom,ee = <0>; 1400 qcom,channel = <0>; 1401 #address-cells = <2>; 1402 #size-cells = <0>; 1403 interrupt-controller; 1404 #interrupt-cells = <4>; 1405 }; 1406 1407 bam_dmux_dma: dma-controller@4044000 { 1408 compatible = "qcom,bam-v1.7.0"; 1409 reg = <0x04044000 0x19000>; 1410 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1411 #dma-cells = <1>; 1412 qcom,ee = <0>; 1413 1414 num-channels = <6>; 1415 qcom,num-ees = <1>; 1416 qcom,powered-remotely; 1417 1418 status = "disabled"; 1419 }; 1420 1421 mpss: remoteproc@4080000 { 1422 compatible = "qcom,msm8916-mss-pil"; 1423 reg = <0x04080000 0x100>, 1424 <0x04020000 0x040>; 1425 1426 reg-names = "qdsp6", "rmb"; 1427 1428 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1429 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1430 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1431 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1432 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1433 interrupt-names = "wdog", "fatal", "ready", 1434 "handover", "stop-ack"; 1435 1436 power-domains = <&rpmpd MSM8916_VDDCX>, 1437 <&rpmpd MSM8916_VDDMX>; 1438 power-domain-names = "cx", "mx"; 1439 1440 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1441 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1442 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1443 <&xo_board>; 1444 clock-names = "iface", "bus", "mem", "xo"; 1445 1446 qcom,smem-states = <&hexagon_smp2p_out 0>; 1447 qcom,smem-state-names = "stop"; 1448 1449 resets = <&scm 0>; 1450 reset-names = "mss_restart"; 1451 1452 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1453 1454 status = "disabled"; 1455 1456 mba { 1457 memory-region = <&mba_mem>; 1458 }; 1459 1460 mpss { 1461 memory-region = <&mpss_mem>; 1462 }; 1463 1464 bam_dmux: bam-dmux { 1465 compatible = "qcom,bam-dmux"; 1466 1467 interrupt-parent = <&hexagon_smsm>; 1468 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1469 interrupt-names = "pc", "pc-ack"; 1470 1471 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1472 qcom,smem-state-names = "pc", "pc-ack"; 1473 1474 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1475 dma-names = "tx", "rx"; 1476 1477 status = "disabled"; 1478 }; 1479 1480 smd-edge { 1481 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1482 1483 qcom,smd-edge = <0>; 1484 qcom,ipc = <&apcs 8 12>; 1485 qcom,remote-pid = <1>; 1486 1487 label = "hexagon"; 1488 1489 fastrpc { 1490 compatible = "qcom,fastrpc"; 1491 qcom,smd-channels = "fastrpcsmd-apps-dsp"; 1492 label = "adsp"; 1493 qcom,non-secure-domain; 1494 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 1498 cb@1 { 1499 compatible = "qcom,fastrpc-compute-cb"; 1500 reg = <1>; 1501 }; 1502 }; 1503 }; 1504 }; 1505 1506 sound: sound@7702000 { 1507 status = "disabled"; 1508 compatible = "qcom,apq8016-sbc-sndcard"; 1509 reg = <0x07702000 0x4>, <0x07702004 0x4>; 1510 reg-names = "mic-iomux", "spkr-iomux"; 1511 }; 1512 1513 lpass: audio-controller@7708000 { 1514 status = "disabled"; 1515 compatible = "qcom,apq8016-lpass-cpu"; 1516 1517 /* 1518 * Note: Unlike the name would suggest, the SEC_I2S_CLK 1519 * is actually only used by Tertiary MI2S while 1520 * Primary/Secondary MI2S both use the PRI_I2S_CLK. 1521 */ 1522 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1523 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 1524 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, 1525 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1526 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1527 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 1528 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; 1529 1530 clock-names = "ahbix-clk", 1531 "pcnoc-mport-clk", 1532 "pcnoc-sway-clk", 1533 "mi2s-bit-clk0", 1534 "mi2s-bit-clk1", 1535 "mi2s-bit-clk2", 1536 "mi2s-bit-clk3"; 1537 #sound-dai-cells = <1>; 1538 1539 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1540 interrupt-names = "lpass-irq-lpaif"; 1541 reg = <0x07708000 0x10000>; 1542 reg-names = "lpass-lpaif"; 1543 1544 #address-cells = <1>; 1545 #size-cells = <0>; 1546 }; 1547 1548 lpass_codec: audio-codec@771c000 { 1549 compatible = "qcom,msm8916-wcd-digital-codec"; 1550 reg = <0x0771c000 0x400>; 1551 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1552 <&gcc GCC_CODEC_DIGCODEC_CLK>; 1553 clock-names = "ahbix-clk", "mclk"; 1554 #sound-dai-cells = <1>; 1555 }; 1556 1557 sdhc_1: mmc@7824000 { 1558 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1559 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 1560 reg-names = "hc", "core"; 1561 1562 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1563 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1564 interrupt-names = "hc_irq", "pwr_irq"; 1565 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1566 <&gcc GCC_SDCC1_APPS_CLK>, 1567 <&xo_board>; 1568 clock-names = "iface", "core", "xo"; 1569 mmc-ddr-1_8v; 1570 bus-width = <8>; 1571 non-removable; 1572 status = "disabled"; 1573 }; 1574 1575 sdhc_2: mmc@7864000 { 1576 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1577 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 1578 reg-names = "hc", "core"; 1579 1580 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1582 interrupt-names = "hc_irq", "pwr_irq"; 1583 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1584 <&gcc GCC_SDCC2_APPS_CLK>, 1585 <&xo_board>; 1586 clock-names = "iface", "core", "xo"; 1587 bus-width = <4>; 1588 status = "disabled"; 1589 }; 1590 1591 blsp_dma: dma-controller@7884000 { 1592 compatible = "qcom,bam-v1.7.0"; 1593 reg = <0x07884000 0x23000>; 1594 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1595 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1596 clock-names = "bam_clk"; 1597 #dma-cells = <1>; 1598 qcom,ee = <0>; 1599 }; 1600 1601 blsp1_uart1: serial@78af000 { 1602 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1603 reg = <0x078af000 0x200>; 1604 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1605 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1606 clock-names = "core", "iface"; 1607 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 1608 dma-names = "tx", "rx"; 1609 pinctrl-names = "default", "sleep"; 1610 pinctrl-0 = <&blsp1_uart1_default>; 1611 pinctrl-1 = <&blsp1_uart1_sleep>; 1612 status = "disabled"; 1613 }; 1614 1615 blsp1_uart2: serial@78b0000 { 1616 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1617 reg = <0x078b0000 0x200>; 1618 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1619 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1620 clock-names = "core", "iface"; 1621 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 1622 dma-names = "tx", "rx"; 1623 pinctrl-names = "default", "sleep"; 1624 pinctrl-0 = <&blsp1_uart2_default>; 1625 pinctrl-1 = <&blsp1_uart2_sleep>; 1626 status = "disabled"; 1627 }; 1628 1629 blsp_i2c1: i2c@78b5000 { 1630 compatible = "qcom,i2c-qup-v2.2.1"; 1631 reg = <0x078b5000 0x500>; 1632 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1633 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1634 <&gcc GCC_BLSP1_AHB_CLK>; 1635 clock-names = "core", "iface"; 1636 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1637 dma-names = "tx", "rx"; 1638 pinctrl-names = "default", "sleep"; 1639 pinctrl-0 = <&i2c1_default>; 1640 pinctrl-1 = <&i2c1_sleep>; 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 status = "disabled"; 1644 }; 1645 1646 blsp_spi1: spi@78b5000 { 1647 compatible = "qcom,spi-qup-v2.2.1"; 1648 reg = <0x078b5000 0x500>; 1649 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1650 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1651 <&gcc GCC_BLSP1_AHB_CLK>; 1652 clock-names = "core", "iface"; 1653 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1654 dma-names = "tx", "rx"; 1655 pinctrl-names = "default", "sleep"; 1656 pinctrl-0 = <&spi1_default>; 1657 pinctrl-1 = <&spi1_sleep>; 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 status = "disabled"; 1661 }; 1662 1663 blsp_i2c2: i2c@78b6000 { 1664 compatible = "qcom,i2c-qup-v2.2.1"; 1665 reg = <0x078b6000 0x500>; 1666 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1667 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1668 <&gcc GCC_BLSP1_AHB_CLK>; 1669 clock-names = "core", "iface"; 1670 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1671 dma-names = "tx", "rx"; 1672 pinctrl-names = "default", "sleep"; 1673 pinctrl-0 = <&i2c2_default>; 1674 pinctrl-1 = <&i2c2_sleep>; 1675 #address-cells = <1>; 1676 #size-cells = <0>; 1677 status = "disabled"; 1678 }; 1679 1680 blsp_spi2: spi@78b6000 { 1681 compatible = "qcom,spi-qup-v2.2.1"; 1682 reg = <0x078b6000 0x500>; 1683 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1684 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1685 <&gcc GCC_BLSP1_AHB_CLK>; 1686 clock-names = "core", "iface"; 1687 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1688 dma-names = "tx", "rx"; 1689 pinctrl-names = "default", "sleep"; 1690 pinctrl-0 = <&spi2_default>; 1691 pinctrl-1 = <&spi2_sleep>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 status = "disabled"; 1695 }; 1696 1697 blsp_i2c3: i2c@78b7000 { 1698 compatible = "qcom,i2c-qup-v2.2.1"; 1699 reg = <0x078b7000 0x500>; 1700 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1701 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1702 <&gcc GCC_BLSP1_AHB_CLK>; 1703 clock-names = "core", "iface"; 1704 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1705 dma-names = "tx", "rx"; 1706 pinctrl-names = "default", "sleep"; 1707 pinctrl-0 = <&i2c3_default>; 1708 pinctrl-1 = <&i2c3_sleep>; 1709 #address-cells = <1>; 1710 #size-cells = <0>; 1711 status = "disabled"; 1712 }; 1713 1714 blsp_spi3: spi@78b7000 { 1715 compatible = "qcom,spi-qup-v2.2.1"; 1716 reg = <0x078b7000 0x500>; 1717 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1718 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1719 <&gcc GCC_BLSP1_AHB_CLK>; 1720 clock-names = "core", "iface"; 1721 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1722 dma-names = "tx", "rx"; 1723 pinctrl-names = "default", "sleep"; 1724 pinctrl-0 = <&spi3_default>; 1725 pinctrl-1 = <&spi3_sleep>; 1726 #address-cells = <1>; 1727 #size-cells = <0>; 1728 status = "disabled"; 1729 }; 1730 1731 blsp_i2c4: i2c@78b8000 { 1732 compatible = "qcom,i2c-qup-v2.2.1"; 1733 reg = <0x078b8000 0x500>; 1734 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1735 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1736 <&gcc GCC_BLSP1_AHB_CLK>; 1737 clock-names = "core", "iface"; 1738 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1739 dma-names = "tx", "rx"; 1740 pinctrl-names = "default", "sleep"; 1741 pinctrl-0 = <&i2c4_default>; 1742 pinctrl-1 = <&i2c4_sleep>; 1743 #address-cells = <1>; 1744 #size-cells = <0>; 1745 status = "disabled"; 1746 }; 1747 1748 blsp_spi4: spi@78b8000 { 1749 compatible = "qcom,spi-qup-v2.2.1"; 1750 reg = <0x078b8000 0x500>; 1751 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1752 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1753 <&gcc GCC_BLSP1_AHB_CLK>; 1754 clock-names = "core", "iface"; 1755 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1756 dma-names = "tx", "rx"; 1757 pinctrl-names = "default", "sleep"; 1758 pinctrl-0 = <&spi4_default>; 1759 pinctrl-1 = <&spi4_sleep>; 1760 #address-cells = <1>; 1761 #size-cells = <0>; 1762 status = "disabled"; 1763 }; 1764 1765 blsp_i2c5: i2c@78b9000 { 1766 compatible = "qcom,i2c-qup-v2.2.1"; 1767 reg = <0x078b9000 0x500>; 1768 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1769 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1770 <&gcc GCC_BLSP1_AHB_CLK>; 1771 clock-names = "core", "iface"; 1772 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1773 dma-names = "tx", "rx"; 1774 pinctrl-names = "default", "sleep"; 1775 pinctrl-0 = <&i2c5_default>; 1776 pinctrl-1 = <&i2c5_sleep>; 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 status = "disabled"; 1780 }; 1781 1782 blsp_spi5: spi@78b9000 { 1783 compatible = "qcom,spi-qup-v2.2.1"; 1784 reg = <0x078b9000 0x500>; 1785 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1786 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 1787 <&gcc GCC_BLSP1_AHB_CLK>; 1788 clock-names = "core", "iface"; 1789 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1790 dma-names = "tx", "rx"; 1791 pinctrl-names = "default", "sleep"; 1792 pinctrl-0 = <&spi5_default>; 1793 pinctrl-1 = <&spi5_sleep>; 1794 #address-cells = <1>; 1795 #size-cells = <0>; 1796 status = "disabled"; 1797 }; 1798 1799 blsp_i2c6: i2c@78ba000 { 1800 compatible = "qcom,i2c-qup-v2.2.1"; 1801 reg = <0x078ba000 0x500>; 1802 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1803 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1804 <&gcc GCC_BLSP1_AHB_CLK>; 1805 clock-names = "core", "iface"; 1806 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1807 dma-names = "tx", "rx"; 1808 pinctrl-names = "default", "sleep"; 1809 pinctrl-0 = <&i2c6_default>; 1810 pinctrl-1 = <&i2c6_sleep>; 1811 #address-cells = <1>; 1812 #size-cells = <0>; 1813 status = "disabled"; 1814 }; 1815 1816 blsp_spi6: spi@78ba000 { 1817 compatible = "qcom,spi-qup-v2.2.1"; 1818 reg = <0x078ba000 0x500>; 1819 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1820 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 1821 <&gcc GCC_BLSP1_AHB_CLK>; 1822 clock-names = "core", "iface"; 1823 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1824 dma-names = "tx", "rx"; 1825 pinctrl-names = "default", "sleep"; 1826 pinctrl-0 = <&spi6_default>; 1827 pinctrl-1 = <&spi6_sleep>; 1828 #address-cells = <1>; 1829 #size-cells = <0>; 1830 status = "disabled"; 1831 }; 1832 1833 usb: usb@78d9000 { 1834 compatible = "qcom,ci-hdrc"; 1835 reg = <0x078d9000 0x200>, 1836 <0x078d9200 0x200>; 1837 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1839 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 1840 <&gcc GCC_USB_HS_SYSTEM_CLK>; 1841 clock-names = "iface", "core"; 1842 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1843 assigned-clock-rates = <80000000>; 1844 resets = <&gcc GCC_USB_HS_BCR>; 1845 reset-names = "core"; 1846 phy_type = "ulpi"; 1847 dr_mode = "otg"; 1848 hnp-disable; 1849 srp-disable; 1850 adp-disable; 1851 ahb-burst-config = <0>; 1852 phy-names = "usb-phy"; 1853 phys = <&usb_hs_phy>; 1854 status = "disabled"; 1855 #reset-cells = <1>; 1856 1857 ulpi { 1858 usb_hs_phy: phy { 1859 compatible = "qcom,usb-hs-phy-msm8916", 1860 "qcom,usb-hs-phy"; 1861 #phy-cells = <0>; 1862 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 1863 clock-names = "ref", "sleep"; 1864 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 1865 reset-names = "phy", "por"; 1866 qcom,init-seq = /bits/ 8 <0x0 0x44>, 1867 <0x1 0x6b>, 1868 <0x2 0x24>, 1869 <0x3 0x13>; 1870 }; 1871 }; 1872 }; 1873 1874 wcnss: remoteproc@a21b000 { 1875 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 1876 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1877 reg-names = "ccu", "dxe", "pmu"; 1878 1879 memory-region = <&wcnss_mem>; 1880 1881 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1882 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1883 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1884 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1885 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1886 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1887 1888 power-domains = <&rpmpd MSM8916_VDDCX>, 1889 <&rpmpd MSM8916_VDDMX>; 1890 power-domain-names = "cx", "mx"; 1891 1892 qcom,smem-states = <&wcnss_smp2p_out 0>; 1893 qcom,smem-state-names = "stop"; 1894 1895 pinctrl-names = "default"; 1896 pinctrl-0 = <&wcnss_pin_a>; 1897 1898 status = "disabled"; 1899 1900 wcnss_iris: iris { 1901 /* Separate chip, compatible is board-specific */ 1902 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1903 clock-names = "xo"; 1904 }; 1905 1906 smd-edge { 1907 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1908 1909 qcom,ipc = <&apcs 8 17>; 1910 qcom,smd-edge = <6>; 1911 qcom,remote-pid = <4>; 1912 1913 label = "pronto"; 1914 1915 wcnss_ctrl: wcnss { 1916 compatible = "qcom,wcnss"; 1917 qcom,smd-channels = "WCNSS_CTRL"; 1918 1919 qcom,mmio = <&wcnss>; 1920 1921 wcnss_bt: bluetooth { 1922 compatible = "qcom,wcnss-bt"; 1923 }; 1924 1925 wcnss_wifi: wifi { 1926 compatible = "qcom,wcnss-wlan"; 1927 1928 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1930 interrupt-names = "tx", "rx"; 1931 1932 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1933 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1934 }; 1935 }; 1936 }; 1937 }; 1938 1939 intc: interrupt-controller@b000000 { 1940 compatible = "qcom,msm-qgic2"; 1941 interrupt-controller; 1942 #interrupt-cells = <3>; 1943 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 1944 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 1945 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1946 }; 1947 1948 apcs: mailbox@b011000 { 1949 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 1950 reg = <0x0b011000 0x1000>; 1951 #mbox-cells = <1>; 1952 clocks = <&a53pll>, <&gcc GPLL0_VOTE>; 1953 clock-names = "pll", "aux"; 1954 #clock-cells = <0>; 1955 }; 1956 1957 a53pll: clock@b016000 { 1958 compatible = "qcom,msm8916-a53pll"; 1959 reg = <0x0b016000 0x40>; 1960 #clock-cells = <0>; 1961 clocks = <&xo_board>; 1962 clock-names = "xo"; 1963 }; 1964 1965 timer@b020000 { 1966 #address-cells = <1>; 1967 #size-cells = <1>; 1968 ranges; 1969 compatible = "arm,armv7-timer-mem"; 1970 reg = <0x0b020000 0x1000>; 1971 clock-frequency = <19200000>; 1972 1973 frame@b021000 { 1974 frame-number = <0>; 1975 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1977 reg = <0x0b021000 0x1000>, 1978 <0x0b022000 0x1000>; 1979 }; 1980 1981 frame@b023000 { 1982 frame-number = <1>; 1983 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1984 reg = <0x0b023000 0x1000>; 1985 status = "disabled"; 1986 }; 1987 1988 frame@b024000 { 1989 frame-number = <2>; 1990 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1991 reg = <0x0b024000 0x1000>; 1992 status = "disabled"; 1993 }; 1994 1995 frame@b025000 { 1996 frame-number = <3>; 1997 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1998 reg = <0x0b025000 0x1000>; 1999 status = "disabled"; 2000 }; 2001 2002 frame@b026000 { 2003 frame-number = <4>; 2004 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2005 reg = <0x0b026000 0x1000>; 2006 status = "disabled"; 2007 }; 2008 2009 frame@b027000 { 2010 frame-number = <5>; 2011 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2012 reg = <0x0b027000 0x1000>; 2013 status = "disabled"; 2014 }; 2015 2016 frame@b028000 { 2017 frame-number = <6>; 2018 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2019 reg = <0x0b028000 0x1000>; 2020 status = "disabled"; 2021 }; 2022 }; 2023 2024 cpu0_acc: power-manager@b088000 { 2025 compatible = "qcom,msm8916-acc"; 2026 reg = <0x0b088000 0x1000>; 2027 status = "reserved"; /* Controlled by PSCI firmware */ 2028 }; 2029 2030 cpu0_saw: power-manager@b089000 { 2031 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2032 reg = <0x0b089000 0x1000>; 2033 status = "reserved"; /* Controlled by PSCI firmware */ 2034 }; 2035 2036 cpu1_acc: power-manager@b098000 { 2037 compatible = "qcom,msm8916-acc"; 2038 reg = <0x0b098000 0x1000>; 2039 status = "reserved"; /* Controlled by PSCI firmware */ 2040 }; 2041 2042 cpu1_saw: power-manager@b099000 { 2043 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2044 reg = <0x0b099000 0x1000>; 2045 status = "reserved"; /* Controlled by PSCI firmware */ 2046 }; 2047 2048 cpu2_acc: power-manager@b0a8000 { 2049 compatible = "qcom,msm8916-acc"; 2050 reg = <0x0b0a8000 0x1000>; 2051 status = "reserved"; /* Controlled by PSCI firmware */ 2052 }; 2053 2054 cpu2_saw: power-manager@b0a9000 { 2055 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2056 reg = <0x0b0a9000 0x1000>; 2057 status = "reserved"; /* Controlled by PSCI firmware */ 2058 }; 2059 2060 cpu3_acc: power-manager@b0b8000 { 2061 compatible = "qcom,msm8916-acc"; 2062 reg = <0x0b0b8000 0x1000>; 2063 status = "reserved"; /* Controlled by PSCI firmware */ 2064 }; 2065 2066 cpu3_saw: power-manager@b0b9000 { 2067 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2068 reg = <0x0b0b9000 0x1000>; 2069 status = "reserved"; /* Controlled by PSCI firmware */ 2070 }; 2071 }; 2072 2073 thermal-zones { 2074 cpu0-1-thermal { 2075 polling-delay-passive = <250>; 2076 polling-delay = <1000>; 2077 2078 thermal-sensors = <&tsens 5>; 2079 2080 trips { 2081 cpu0_1_alert0: trip-point0 { 2082 temperature = <75000>; 2083 hysteresis = <2000>; 2084 type = "passive"; 2085 }; 2086 cpu0_1_crit: cpu-crit { 2087 temperature = <110000>; 2088 hysteresis = <2000>; 2089 type = "critical"; 2090 }; 2091 }; 2092 2093 cooling-maps { 2094 map0 { 2095 trip = <&cpu0_1_alert0>; 2096 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2097 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2098 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2099 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2100 }; 2101 }; 2102 }; 2103 2104 cpu2-3-thermal { 2105 polling-delay-passive = <250>; 2106 polling-delay = <1000>; 2107 2108 thermal-sensors = <&tsens 4>; 2109 2110 trips { 2111 cpu2_3_alert0: trip-point0 { 2112 temperature = <75000>; 2113 hysteresis = <2000>; 2114 type = "passive"; 2115 }; 2116 cpu2_3_crit: cpu-crit { 2117 temperature = <110000>; 2118 hysteresis = <2000>; 2119 type = "critical"; 2120 }; 2121 }; 2122 2123 cooling-maps { 2124 map0 { 2125 trip = <&cpu2_3_alert0>; 2126 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2127 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2128 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2129 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2130 }; 2131 }; 2132 }; 2133 2134 gpu-thermal { 2135 polling-delay-passive = <250>; 2136 polling-delay = <1000>; 2137 2138 thermal-sensors = <&tsens 2>; 2139 2140 trips { 2141 gpu_alert0: trip-point0 { 2142 temperature = <75000>; 2143 hysteresis = <2000>; 2144 type = "passive"; 2145 }; 2146 gpu_crit: gpu-crit { 2147 temperature = <95000>; 2148 hysteresis = <2000>; 2149 type = "critical"; 2150 }; 2151 }; 2152 }; 2153 2154 camera-thermal { 2155 polling-delay-passive = <250>; 2156 polling-delay = <1000>; 2157 2158 thermal-sensors = <&tsens 1>; 2159 2160 trips { 2161 cam_alert0: trip-point0 { 2162 temperature = <75000>; 2163 hysteresis = <2000>; 2164 type = "hot"; 2165 }; 2166 }; 2167 }; 2168 2169 modem-thermal { 2170 polling-delay-passive = <250>; 2171 polling-delay = <1000>; 2172 2173 thermal-sensors = <&tsens 0>; 2174 2175 trips { 2176 modem_alert0: trip-point0 { 2177 temperature = <85000>; 2178 hysteresis = <2000>; 2179 type = "hot"; 2180 }; 2181 }; 2182 }; 2183 }; 2184 2185 timer { 2186 compatible = "arm,armv8-timer"; 2187 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2188 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2189 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2190 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2191 }; 2192}; 2193 2194#include "msm8916-pins.dtsi" 2195