1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/arm/coresight-cti-dt.h> 7#include <dt-bindings/clock/qcom,gcc-msm8916.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8916.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8916.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 chosen { }; 22 23 memory@80000000 { 24 device_type = "memory"; 25 /* We expect the bootloader to fill in the reg */ 26 reg = <0 0x80000000 0 0>; 27 }; 28 29 reserved-memory { 30 #address-cells = <2>; 31 #size-cells = <2>; 32 ranges; 33 34 tz-apps@86000000 { 35 reg = <0x0 0x86000000 0x0 0x300000>; 36 no-map; 37 }; 38 39 smem@86300000 { 40 compatible = "qcom,smem"; 41 reg = <0x0 0x86300000 0x0 0x100000>; 42 no-map; 43 44 hwlocks = <&tcsr_mutex 3>; 45 qcom,rpm-msg-ram = <&rpm_msg_ram>; 46 }; 47 48 hypervisor@86400000 { 49 reg = <0x0 0x86400000 0x0 0x100000>; 50 no-map; 51 }; 52 53 tz@86500000 { 54 reg = <0x0 0x86500000 0x0 0x180000>; 55 no-map; 56 }; 57 58 reserved@86680000 { 59 reg = <0x0 0x86680000 0x0 0x80000>; 60 no-map; 61 }; 62 63 rmtfs@86700000 { 64 compatible = "qcom,rmtfs-mem"; 65 reg = <0x0 0x86700000 0x0 0xe0000>; 66 no-map; 67 68 qcom,client-id = <1>; 69 }; 70 71 rfsa@867e0000 { 72 reg = <0x0 0x867e0000 0x0 0x20000>; 73 no-map; 74 }; 75 76 mpss_mem: mpss@86800000 { 77 /* 78 * The memory region for the mpss firmware is generally 79 * relocatable and could be allocated dynamically. 80 * However, many firmware versions tend to fail when 81 * loaded to some special addresses, so it is hard to 82 * define reliable alloc-ranges. 83 * 84 * alignment = <0x0 0x400000>; 85 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 86 */ 87 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */ 88 no-map; 89 status = "disabled"; 90 }; 91 92 wcnss_mem: wcnss { 93 size = <0x0 0x600000>; 94 alignment = <0x0 0x100000>; 95 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 96 no-map; 97 status = "disabled"; 98 }; 99 100 venus_mem: venus { 101 size = <0x0 0x500000>; 102 alignment = <0x0 0x100000>; 103 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 104 no-map; 105 status = "disabled"; 106 }; 107 108 mba_mem: mba { 109 size = <0x0 0x100000>; 110 alignment = <0x0 0x100000>; 111 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 112 no-map; 113 status = "disabled"; 114 }; 115 }; 116 117 clocks { 118 xo_board: xo-board { 119 compatible = "fixed-clock"; 120 #clock-cells = <0>; 121 clock-frequency = <19200000>; 122 }; 123 124 sleep_clk: sleep-clk { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <32768>; 128 }; 129 }; 130 131 cpus { 132 #address-cells = <1>; 133 #size-cells = <0>; 134 135 CPU0: cpu@0 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a53"; 138 reg = <0x0>; 139 next-level-cache = <&L2_0>; 140 enable-method = "psci"; 141 clocks = <&apcs>; 142 operating-points-v2 = <&cpu_opp_table>; 143 #cooling-cells = <2>; 144 power-domains = <&CPU_PD0>; 145 power-domain-names = "psci"; 146 qcom,acc = <&cpu0_acc>; 147 qcom,saw = <&cpu0_saw>; 148 }; 149 150 CPU1: cpu@1 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a53"; 153 reg = <0x1>; 154 next-level-cache = <&L2_0>; 155 enable-method = "psci"; 156 clocks = <&apcs>; 157 operating-points-v2 = <&cpu_opp_table>; 158 #cooling-cells = <2>; 159 power-domains = <&CPU_PD1>; 160 power-domain-names = "psci"; 161 qcom,acc = <&cpu1_acc>; 162 qcom,saw = <&cpu1_saw>; 163 }; 164 165 CPU2: cpu@2 { 166 device_type = "cpu"; 167 compatible = "arm,cortex-a53"; 168 reg = <0x2>; 169 next-level-cache = <&L2_0>; 170 enable-method = "psci"; 171 clocks = <&apcs>; 172 operating-points-v2 = <&cpu_opp_table>; 173 #cooling-cells = <2>; 174 power-domains = <&CPU_PD2>; 175 power-domain-names = "psci"; 176 qcom,acc = <&cpu2_acc>; 177 qcom,saw = <&cpu2_saw>; 178 }; 179 180 CPU3: cpu@3 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a53"; 183 reg = <0x3>; 184 next-level-cache = <&L2_0>; 185 enable-method = "psci"; 186 clocks = <&apcs>; 187 operating-points-v2 = <&cpu_opp_table>; 188 #cooling-cells = <2>; 189 power-domains = <&CPU_PD3>; 190 power-domain-names = "psci"; 191 qcom,acc = <&cpu3_acc>; 192 qcom,saw = <&cpu3_saw>; 193 }; 194 195 L2_0: l2-cache { 196 compatible = "cache"; 197 cache-level = <2>; 198 cache-unified; 199 }; 200 201 idle-states { 202 entry-method = "psci"; 203 204 CPU_SLEEP_0: cpu-sleep-0 { 205 compatible = "arm,idle-state"; 206 idle-state-name = "standalone-power-collapse"; 207 arm,psci-suspend-param = <0x40000002>; 208 entry-latency-us = <130>; 209 exit-latency-us = <150>; 210 min-residency-us = <2000>; 211 local-timer-stop; 212 }; 213 }; 214 215 domain-idle-states { 216 217 CLUSTER_RET: cluster-retention { 218 compatible = "domain-idle-state"; 219 arm,psci-suspend-param = <0x41000012>; 220 entry-latency-us = <500>; 221 exit-latency-us = <500>; 222 min-residency-us = <2000>; 223 }; 224 225 CLUSTER_PWRDN: cluster-gdhs { 226 compatible = "domain-idle-state"; 227 arm,psci-suspend-param = <0x41000032>; 228 entry-latency-us = <2000>; 229 exit-latency-us = <2000>; 230 min-residency-us = <6000>; 231 }; 232 }; 233 }; 234 235 cpu_opp_table: opp-table-cpu { 236 compatible = "operating-points-v2"; 237 opp-shared; 238 239 opp-200000000 { 240 opp-hz = /bits/ 64 <200000000>; 241 }; 242 opp-400000000 { 243 opp-hz = /bits/ 64 <400000000>; 244 }; 245 opp-800000000 { 246 opp-hz = /bits/ 64 <800000000>; 247 }; 248 opp-998400000 { 249 opp-hz = /bits/ 64 <998400000>; 250 }; 251 }; 252 253 firmware { 254 scm: scm { 255 compatible = "qcom,scm-msm8916", "qcom,scm"; 256 clocks = <&gcc GCC_CRYPTO_CLK>, 257 <&gcc GCC_CRYPTO_AXI_CLK>, 258 <&gcc GCC_CRYPTO_AHB_CLK>; 259 clock-names = "core", "bus", "iface"; 260 #reset-cells = <1>; 261 262 qcom,dload-mode = <&tcsr 0x6100>; 263 }; 264 }; 265 266 pmu { 267 compatible = "arm,cortex-a53-pmu"; 268 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 269 }; 270 271 psci { 272 compatible = "arm,psci-1.0"; 273 method = "smc"; 274 275 CPU_PD0: power-domain-cpu0 { 276 #power-domain-cells = <0>; 277 power-domains = <&CLUSTER_PD>; 278 domain-idle-states = <&CPU_SLEEP_0>; 279 }; 280 281 CPU_PD1: power-domain-cpu1 { 282 #power-domain-cells = <0>; 283 power-domains = <&CLUSTER_PD>; 284 domain-idle-states = <&CPU_SLEEP_0>; 285 }; 286 287 CPU_PD2: power-domain-cpu2 { 288 #power-domain-cells = <0>; 289 power-domains = <&CLUSTER_PD>; 290 domain-idle-states = <&CPU_SLEEP_0>; 291 }; 292 293 CPU_PD3: power-domain-cpu3 { 294 #power-domain-cells = <0>; 295 power-domains = <&CLUSTER_PD>; 296 domain-idle-states = <&CPU_SLEEP_0>; 297 }; 298 299 CLUSTER_PD: power-domain-cluster { 300 #power-domain-cells = <0>; 301 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; 302 }; 303 }; 304 305 rpm: remoteproc { 306 compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc"; 307 308 smd-edge { 309 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 310 qcom,ipc = <&apcs 8 0>; 311 qcom,smd-edge = <15>; 312 313 rpm_requests: rpm-requests { 314 compatible = "qcom,rpm-msm8916"; 315 qcom,smd-channels = "rpm_requests"; 316 317 rpmcc: clock-controller { 318 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; 319 #clock-cells = <1>; 320 clocks = <&xo_board>; 321 clock-names = "xo"; 322 }; 323 324 rpmpd: power-controller { 325 compatible = "qcom,msm8916-rpmpd"; 326 #power-domain-cells = <1>; 327 operating-points-v2 = <&rpmpd_opp_table>; 328 329 rpmpd_opp_table: opp-table { 330 compatible = "operating-points-v2"; 331 332 rpmpd_opp_ret: opp1 { 333 opp-level = <1>; 334 }; 335 rpmpd_opp_svs_krait: opp2 { 336 opp-level = <2>; 337 }; 338 rpmpd_opp_svs_soc: opp3 { 339 opp-level = <3>; 340 }; 341 rpmpd_opp_nom: opp4 { 342 opp-level = <4>; 343 }; 344 rpmpd_opp_turbo: opp5 { 345 opp-level = <5>; 346 }; 347 rpmpd_opp_super_turbo: opp6 { 348 opp-level = <6>; 349 }; 350 }; 351 }; 352 }; 353 }; 354 }; 355 356 smp2p-hexagon { 357 compatible = "qcom,smp2p"; 358 qcom,smem = <435>, <428>; 359 360 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 361 362 qcom,ipc = <&apcs 8 14>; 363 364 qcom,local-pid = <0>; 365 qcom,remote-pid = <1>; 366 367 hexagon_smp2p_out: master-kernel { 368 qcom,entry-name = "master-kernel"; 369 370 #qcom,smem-state-cells = <1>; 371 }; 372 373 hexagon_smp2p_in: slave-kernel { 374 qcom,entry-name = "slave-kernel"; 375 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 }; 379 }; 380 381 smp2p-wcnss { 382 compatible = "qcom,smp2p"; 383 qcom,smem = <451>, <431>; 384 385 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 386 387 qcom,ipc = <&apcs 8 18>; 388 389 qcom,local-pid = <0>; 390 qcom,remote-pid = <4>; 391 392 wcnss_smp2p_out: master-kernel { 393 qcom,entry-name = "master-kernel"; 394 395 #qcom,smem-state-cells = <1>; 396 }; 397 398 wcnss_smp2p_in: slave-kernel { 399 qcom,entry-name = "slave-kernel"; 400 401 interrupt-controller; 402 #interrupt-cells = <2>; 403 }; 404 }; 405 406 smsm { 407 compatible = "qcom,smsm"; 408 409 #address-cells = <1>; 410 #size-cells = <0>; 411 412 qcom,ipc-1 = <&apcs 8 13>; 413 qcom,ipc-3 = <&apcs 8 19>; 414 415 apps_smsm: apps@0 { 416 reg = <0>; 417 418 #qcom,smem-state-cells = <1>; 419 }; 420 421 hexagon_smsm: hexagon@1 { 422 reg = <1>; 423 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 424 425 interrupt-controller; 426 #interrupt-cells = <2>; 427 }; 428 429 wcnss_smsm: wcnss@6 { 430 reg = <6>; 431 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 432 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 }; 436 }; 437 438 soc: soc@0 { 439 #address-cells = <1>; 440 #size-cells = <1>; 441 ranges = <0 0 0 0xffffffff>; 442 compatible = "simple-bus"; 443 444 rng@22000 { 445 compatible = "qcom,prng"; 446 reg = <0x00022000 0x200>; 447 clocks = <&gcc GCC_PRNG_AHB_CLK>; 448 clock-names = "core"; 449 }; 450 451 restart@4ab000 { 452 compatible = "qcom,pshold"; 453 reg = <0x004ab000 0x4>; 454 }; 455 456 qfprom: qfprom@5c000 { 457 compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 458 reg = <0x0005c000 0x1000>; 459 #address-cells = <1>; 460 #size-cells = <1>; 461 462 tsens_base1: base1@d0 { 463 reg = <0xd0 0x1>; 464 bits = <0 7>; 465 }; 466 467 tsens_s0_p1: s0-p1@d0 { 468 reg = <0xd0 0x2>; 469 bits = <7 5>; 470 }; 471 472 tsens_s0_p2: s0-p2@d1 { 473 reg = <0xd1 0x2>; 474 bits = <4 5>; 475 }; 476 477 tsens_s1_p1: s1-p1@d2 { 478 reg = <0xd2 0x1>; 479 bits = <1 5>; 480 }; 481 tsens_s1_p2: s1-p2@d2 { 482 reg = <0xd2 0x2>; 483 bits = <6 5>; 484 }; 485 tsens_s2_p1: s2-p1@d3 { 486 reg = <0xd3 0x1>; 487 bits = <3 5>; 488 }; 489 490 tsens_s2_p2: s2-p2@d4 { 491 reg = <0xd4 0x1>; 492 bits = <0 5>; 493 }; 494 495 // no tsens with hw_id 3 496 497 tsens_s4_p1: s4-p1@d4 { 498 reg = <0xd4 0x2>; 499 bits = <5 5>; 500 }; 501 502 tsens_s4_p2: s4-p2@d5 { 503 reg = <0xd5 0x1>; 504 bits = <2 5>; 505 }; 506 507 tsens_s5_p1: s5-p1@d5 { 508 reg = <0xd5 0x2>; 509 bits = <7 5>; 510 }; 511 512 tsens_s5_p2: s5-p2@d6 { 513 reg = <0xd6 0x2>; 514 bits = <4 5>; 515 }; 516 517 tsens_base2: base2@d7 { 518 reg = <0xd7 0x1>; 519 bits = <1 7>; 520 }; 521 522 tsens_mode: mode@ef { 523 reg = <0xef 0x1>; 524 bits = <5 3>; 525 }; 526 }; 527 528 rpm_msg_ram: sram@60000 { 529 compatible = "qcom,rpm-msg-ram"; 530 reg = <0x00060000 0x8000>; 531 }; 532 533 sram@290000 { 534 compatible = "qcom,msm8916-rpm-stats"; 535 reg = <0x00290000 0x10000>; 536 }; 537 538 bimc: interconnect@400000 { 539 compatible = "qcom,msm8916-bimc"; 540 reg = <0x00400000 0x62000>; 541 #interconnect-cells = <1>; 542 clock-names = "bus", "bus_a"; 543 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 544 <&rpmcc RPM_SMD_BIMC_A_CLK>; 545 }; 546 547 tsens: thermal-sensor@4a9000 { 548 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 549 reg = <0x004a9000 0x1000>, /* TM */ 550 <0x004a8000 0x1000>; /* SROT */ 551 552 // no hw_id 3 553 nvmem-cells = <&tsens_mode>, 554 <&tsens_base1>, <&tsens_base2>, 555 <&tsens_s0_p1>, <&tsens_s0_p2>, 556 <&tsens_s1_p1>, <&tsens_s1_p2>, 557 <&tsens_s2_p1>, <&tsens_s2_p2>, 558 <&tsens_s4_p1>, <&tsens_s4_p2>, 559 <&tsens_s5_p1>, <&tsens_s5_p2>; 560 nvmem-cell-names = "mode", 561 "base1", "base2", 562 "s0_p1", "s0_p2", 563 "s1_p1", "s1_p2", 564 "s2_p1", "s2_p2", 565 "s4_p1", "s4_p2", 566 "s5_p1", "s5_p2"; 567 #qcom,sensors = <5>; 568 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 569 interrupt-names = "uplow"; 570 #thermal-sensor-cells = <1>; 571 }; 572 573 pcnoc: interconnect@500000 { 574 compatible = "qcom,msm8916-pcnoc"; 575 reg = <0x00500000 0x11000>; 576 #interconnect-cells = <1>; 577 clock-names = "bus", "bus_a"; 578 clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, 579 <&rpmcc RPM_SMD_PCNOC_A_CLK>; 580 }; 581 582 snoc: interconnect@580000 { 583 compatible = "qcom,msm8916-snoc"; 584 reg = <0x00580000 0x14000>; 585 #interconnect-cells = <1>; 586 clock-names = "bus", "bus_a"; 587 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 588 <&rpmcc RPM_SMD_SNOC_A_CLK>; 589 }; 590 591 stm: stm@802000 { 592 compatible = "arm,coresight-stm", "arm,primecell"; 593 reg = <0x00802000 0x1000>, 594 <0x09280000 0x180000>; 595 reg-names = "stm-base", "stm-stimulus-base"; 596 597 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 598 clock-names = "apb_pclk", "atclk"; 599 600 status = "disabled"; 601 602 out-ports { 603 port { 604 stm_out: endpoint { 605 remote-endpoint = <&funnel0_in7>; 606 }; 607 }; 608 }; 609 }; 610 611 /* System CTIs */ 612 /* CTI 0 - TMC connections */ 613 cti0: cti@810000 { 614 compatible = "arm,coresight-cti", "arm,primecell"; 615 reg = <0x00810000 0x1000>; 616 617 clocks = <&rpmcc RPM_QDSS_CLK>; 618 clock-names = "apb_pclk"; 619 620 status = "disabled"; 621 }; 622 623 /* CTI 1 - TPIU connections */ 624 cti1: cti@811000 { 625 compatible = "arm,coresight-cti", "arm,primecell"; 626 reg = <0x00811000 0x1000>; 627 628 clocks = <&rpmcc RPM_QDSS_CLK>; 629 clock-names = "apb_pclk"; 630 631 status = "disabled"; 632 }; 633 634 /* CTIs 2-11 - no information - not instantiated */ 635 636 tpiu: tpiu@820000 { 637 compatible = "arm,coresight-tpiu", "arm,primecell"; 638 reg = <0x00820000 0x1000>; 639 640 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 641 clock-names = "apb_pclk", "atclk"; 642 643 status = "disabled"; 644 645 in-ports { 646 port { 647 tpiu_in: endpoint { 648 remote-endpoint = <&replicator_out1>; 649 }; 650 }; 651 }; 652 }; 653 654 funnel0: funnel@821000 { 655 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 656 reg = <0x00821000 0x1000>; 657 658 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 659 clock-names = "apb_pclk", "atclk"; 660 661 status = "disabled"; 662 663 in-ports { 664 #address-cells = <1>; 665 #size-cells = <0>; 666 667 /* 668 * Not described input ports: 669 * 0 - connected to Resource and Power Manger CPU ETM 670 * 1 - not-connected 671 * 2 - connected to Modem CPU ETM 672 * 3 - not-connected 673 * 5 - not-connected 674 * 6 - connected trought funnel to Wireless CPU ETM 675 * 7 - connected to STM component 676 */ 677 678 port@4 { 679 reg = <4>; 680 funnel0_in4: endpoint { 681 remote-endpoint = <&funnel1_out>; 682 }; 683 }; 684 685 port@7 { 686 reg = <7>; 687 funnel0_in7: endpoint { 688 remote-endpoint = <&stm_out>; 689 }; 690 }; 691 }; 692 693 out-ports { 694 port { 695 funnel0_out: endpoint { 696 remote-endpoint = <&etf_in>; 697 }; 698 }; 699 }; 700 }; 701 702 replicator: replicator@824000 { 703 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 704 reg = <0x00824000 0x1000>; 705 706 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 707 clock-names = "apb_pclk", "atclk"; 708 709 status = "disabled"; 710 711 out-ports { 712 #address-cells = <1>; 713 #size-cells = <0>; 714 715 port@0 { 716 reg = <0>; 717 replicator_out0: endpoint { 718 remote-endpoint = <&etr_in>; 719 }; 720 }; 721 port@1 { 722 reg = <1>; 723 replicator_out1: endpoint { 724 remote-endpoint = <&tpiu_in>; 725 }; 726 }; 727 }; 728 729 in-ports { 730 port { 731 replicator_in: endpoint { 732 remote-endpoint = <&etf_out>; 733 }; 734 }; 735 }; 736 }; 737 738 etf: etf@825000 { 739 compatible = "arm,coresight-tmc", "arm,primecell"; 740 reg = <0x00825000 0x1000>; 741 742 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 743 clock-names = "apb_pclk", "atclk"; 744 745 status = "disabled"; 746 747 in-ports { 748 port { 749 etf_in: endpoint { 750 remote-endpoint = <&funnel0_out>; 751 }; 752 }; 753 }; 754 755 out-ports { 756 port { 757 etf_out: endpoint { 758 remote-endpoint = <&replicator_in>; 759 }; 760 }; 761 }; 762 }; 763 764 etr: etr@826000 { 765 compatible = "arm,coresight-tmc", "arm,primecell"; 766 reg = <0x00826000 0x1000>; 767 768 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 769 clock-names = "apb_pclk", "atclk"; 770 771 status = "disabled"; 772 773 in-ports { 774 port { 775 etr_in: endpoint { 776 remote-endpoint = <&replicator_out0>; 777 }; 778 }; 779 }; 780 }; 781 782 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ 783 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 784 reg = <0x00841000 0x1000>; 785 786 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 787 clock-names = "apb_pclk", "atclk"; 788 789 status = "disabled"; 790 791 in-ports { 792 #address-cells = <1>; 793 #size-cells = <0>; 794 795 port@0 { 796 reg = <0>; 797 funnel1_in0: endpoint { 798 remote-endpoint = <&etm0_out>; 799 }; 800 }; 801 port@1 { 802 reg = <1>; 803 funnel1_in1: endpoint { 804 remote-endpoint = <&etm1_out>; 805 }; 806 }; 807 port@2 { 808 reg = <2>; 809 funnel1_in2: endpoint { 810 remote-endpoint = <&etm2_out>; 811 }; 812 }; 813 port@3 { 814 reg = <3>; 815 funnel1_in3: endpoint { 816 remote-endpoint = <&etm3_out>; 817 }; 818 }; 819 }; 820 821 out-ports { 822 port { 823 funnel1_out: endpoint { 824 remote-endpoint = <&funnel0_in4>; 825 }; 826 }; 827 }; 828 }; 829 830 debug0: debug@850000 { 831 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 832 reg = <0x00850000 0x1000>; 833 clocks = <&rpmcc RPM_QDSS_CLK>; 834 clock-names = "apb_pclk"; 835 cpu = <&CPU0>; 836 status = "disabled"; 837 }; 838 839 debug1: debug@852000 { 840 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 841 reg = <0x00852000 0x1000>; 842 clocks = <&rpmcc RPM_QDSS_CLK>; 843 clock-names = "apb_pclk"; 844 cpu = <&CPU1>; 845 status = "disabled"; 846 }; 847 848 debug2: debug@854000 { 849 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 850 reg = <0x00854000 0x1000>; 851 clocks = <&rpmcc RPM_QDSS_CLK>; 852 clock-names = "apb_pclk"; 853 cpu = <&CPU2>; 854 status = "disabled"; 855 }; 856 857 debug3: debug@856000 { 858 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 859 reg = <0x00856000 0x1000>; 860 clocks = <&rpmcc RPM_QDSS_CLK>; 861 clock-names = "apb_pclk"; 862 cpu = <&CPU3>; 863 status = "disabled"; 864 }; 865 866 /* Core CTIs; CTIs 12-15 */ 867 /* CTI - CPU-0 */ 868 cti12: cti@858000 { 869 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 870 "arm,primecell"; 871 reg = <0x00858000 0x1000>; 872 873 clocks = <&rpmcc RPM_QDSS_CLK>; 874 clock-names = "apb_pclk"; 875 876 cpu = <&CPU0>; 877 arm,cs-dev-assoc = <&etm0>; 878 879 status = "disabled"; 880 }; 881 882 /* CTI - CPU-1 */ 883 cti13: cti@859000 { 884 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 885 "arm,primecell"; 886 reg = <0x00859000 0x1000>; 887 888 clocks = <&rpmcc RPM_QDSS_CLK>; 889 clock-names = "apb_pclk"; 890 891 cpu = <&CPU1>; 892 arm,cs-dev-assoc = <&etm1>; 893 894 status = "disabled"; 895 }; 896 897 /* CTI - CPU-2 */ 898 cti14: cti@85a000 { 899 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 900 "arm,primecell"; 901 reg = <0x0085a000 0x1000>; 902 903 clocks = <&rpmcc RPM_QDSS_CLK>; 904 clock-names = "apb_pclk"; 905 906 cpu = <&CPU2>; 907 arm,cs-dev-assoc = <&etm2>; 908 909 status = "disabled"; 910 }; 911 912 /* CTI - CPU-3 */ 913 cti15: cti@85b000 { 914 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 915 "arm,primecell"; 916 reg = <0x0085b000 0x1000>; 917 918 clocks = <&rpmcc RPM_QDSS_CLK>; 919 clock-names = "apb_pclk"; 920 921 cpu = <&CPU3>; 922 arm,cs-dev-assoc = <&etm3>; 923 924 status = "disabled"; 925 }; 926 927 etm0: etm@85c000 { 928 compatible = "arm,coresight-etm4x", "arm,primecell"; 929 reg = <0x0085c000 0x1000>; 930 931 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 932 clock-names = "apb_pclk", "atclk"; 933 arm,coresight-loses-context-with-cpu; 934 935 cpu = <&CPU0>; 936 937 status = "disabled"; 938 939 out-ports { 940 port { 941 etm0_out: endpoint { 942 remote-endpoint = <&funnel1_in0>; 943 }; 944 }; 945 }; 946 }; 947 948 etm1: etm@85d000 { 949 compatible = "arm,coresight-etm4x", "arm,primecell"; 950 reg = <0x0085d000 0x1000>; 951 952 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 953 clock-names = "apb_pclk", "atclk"; 954 arm,coresight-loses-context-with-cpu; 955 956 cpu = <&CPU1>; 957 958 status = "disabled"; 959 960 out-ports { 961 port { 962 etm1_out: endpoint { 963 remote-endpoint = <&funnel1_in1>; 964 }; 965 }; 966 }; 967 }; 968 969 etm2: etm@85e000 { 970 compatible = "arm,coresight-etm4x", "arm,primecell"; 971 reg = <0x0085e000 0x1000>; 972 973 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 974 clock-names = "apb_pclk", "atclk"; 975 arm,coresight-loses-context-with-cpu; 976 977 cpu = <&CPU2>; 978 979 status = "disabled"; 980 981 out-ports { 982 port { 983 etm2_out: endpoint { 984 remote-endpoint = <&funnel1_in2>; 985 }; 986 }; 987 }; 988 }; 989 990 etm3: etm@85f000 { 991 compatible = "arm,coresight-etm4x", "arm,primecell"; 992 reg = <0x0085f000 0x1000>; 993 994 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 995 clock-names = "apb_pclk", "atclk"; 996 arm,coresight-loses-context-with-cpu; 997 998 cpu = <&CPU3>; 999 1000 status = "disabled"; 1001 1002 out-ports { 1003 port { 1004 etm3_out: endpoint { 1005 remote-endpoint = <&funnel1_in3>; 1006 }; 1007 }; 1008 }; 1009 }; 1010 1011 tlmm: pinctrl@1000000 { 1012 compatible = "qcom,msm8916-pinctrl"; 1013 reg = <0x01000000 0x300000>; 1014 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1015 gpio-controller; 1016 gpio-ranges = <&tlmm 0 0 122>; 1017 #gpio-cells = <2>; 1018 interrupt-controller; 1019 #interrupt-cells = <2>; 1020 1021 blsp_i2c1_default: blsp-i2c1-default-state { 1022 pins = "gpio2", "gpio3"; 1023 function = "blsp_i2c1"; 1024 drive-strength = <2>; 1025 bias-disable; 1026 }; 1027 1028 blsp_i2c1_sleep: blsp-i2c1-sleep-state { 1029 pins = "gpio2", "gpio3"; 1030 function = "gpio"; 1031 drive-strength = <2>; 1032 bias-disable; 1033 }; 1034 1035 blsp_i2c2_default: blsp-i2c2-default-state { 1036 pins = "gpio6", "gpio7"; 1037 function = "blsp_i2c2"; 1038 drive-strength = <2>; 1039 bias-disable; 1040 }; 1041 1042 blsp_i2c2_sleep: blsp-i2c2-sleep-state { 1043 pins = "gpio6", "gpio7"; 1044 function = "gpio"; 1045 drive-strength = <2>; 1046 bias-disable; 1047 }; 1048 1049 blsp_i2c3_default: blsp-i2c3-default-state { 1050 pins = "gpio10", "gpio11"; 1051 function = "blsp_i2c3"; 1052 drive-strength = <2>; 1053 bias-disable; 1054 }; 1055 1056 blsp_i2c3_sleep: blsp-i2c3-sleep-state { 1057 pins = "gpio10", "gpio11"; 1058 function = "gpio"; 1059 drive-strength = <2>; 1060 bias-disable; 1061 }; 1062 1063 blsp_i2c4_default: blsp-i2c4-default-state { 1064 pins = "gpio14", "gpio15"; 1065 function = "blsp_i2c4"; 1066 drive-strength = <2>; 1067 bias-disable; 1068 }; 1069 1070 blsp_i2c4_sleep: blsp-i2c4-sleep-state { 1071 pins = "gpio14", "gpio15"; 1072 function = "gpio"; 1073 drive-strength = <2>; 1074 bias-disable; 1075 }; 1076 1077 blsp_i2c5_default: blsp-i2c5-default-state { 1078 pins = "gpio18", "gpio19"; 1079 function = "blsp_i2c5"; 1080 drive-strength = <2>; 1081 bias-disable; 1082 }; 1083 1084 blsp_i2c5_sleep: blsp-i2c5-sleep-state { 1085 pins = "gpio18", "gpio19"; 1086 function = "gpio"; 1087 drive-strength = <2>; 1088 bias-disable; 1089 }; 1090 1091 blsp_i2c6_default: blsp-i2c6-default-state { 1092 pins = "gpio22", "gpio23"; 1093 function = "blsp_i2c6"; 1094 drive-strength = <2>; 1095 bias-disable; 1096 }; 1097 1098 blsp_i2c6_sleep: blsp-i2c6-sleep-state { 1099 pins = "gpio22", "gpio23"; 1100 function = "gpio"; 1101 drive-strength = <2>; 1102 bias-disable; 1103 }; 1104 1105 blsp_spi1_default: blsp-spi1-default-state { 1106 spi-pins { 1107 pins = "gpio0", "gpio1", "gpio3"; 1108 function = "blsp_spi1"; 1109 drive-strength = <12>; 1110 bias-disable; 1111 }; 1112 cs-pins { 1113 pins = "gpio2"; 1114 function = "gpio"; 1115 drive-strength = <16>; 1116 bias-disable; 1117 output-high; 1118 }; 1119 }; 1120 1121 blsp_spi1_sleep: blsp-spi1-sleep-state { 1122 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1123 function = "gpio"; 1124 drive-strength = <2>; 1125 bias-pull-down; 1126 }; 1127 1128 blsp_spi2_default: blsp-spi2-default-state { 1129 spi-pins { 1130 pins = "gpio4", "gpio5", "gpio7"; 1131 function = "blsp_spi2"; 1132 drive-strength = <12>; 1133 bias-disable; 1134 }; 1135 cs-pins { 1136 pins = "gpio6"; 1137 function = "gpio"; 1138 drive-strength = <16>; 1139 bias-disable; 1140 output-high; 1141 }; 1142 }; 1143 1144 blsp_spi2_sleep: blsp-spi2-sleep-state { 1145 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 1146 function = "gpio"; 1147 drive-strength = <2>; 1148 bias-pull-down; 1149 }; 1150 1151 blsp_spi3_default: blsp-spi3-default-state { 1152 spi-pins { 1153 pins = "gpio8", "gpio9", "gpio11"; 1154 function = "blsp_spi3"; 1155 drive-strength = <12>; 1156 bias-disable; 1157 }; 1158 cs-pins { 1159 pins = "gpio10"; 1160 function = "gpio"; 1161 drive-strength = <16>; 1162 bias-disable; 1163 output-high; 1164 }; 1165 }; 1166 1167 blsp_spi3_sleep: blsp-spi3-sleep-state { 1168 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 1169 function = "gpio"; 1170 drive-strength = <2>; 1171 bias-pull-down; 1172 }; 1173 1174 blsp_spi4_default: blsp-spi4-default-state { 1175 spi-pins { 1176 pins = "gpio12", "gpio13", "gpio15"; 1177 function = "blsp_spi4"; 1178 drive-strength = <12>; 1179 bias-disable; 1180 }; 1181 cs-pins { 1182 pins = "gpio14"; 1183 function = "gpio"; 1184 drive-strength = <16>; 1185 bias-disable; 1186 output-high; 1187 }; 1188 }; 1189 1190 blsp_spi4_sleep: blsp-spi4-sleep-state { 1191 pins = "gpio12", "gpio13", "gpio14", "gpio15"; 1192 function = "gpio"; 1193 drive-strength = <2>; 1194 bias-pull-down; 1195 }; 1196 1197 blsp_spi5_default: blsp-spi5-default-state { 1198 spi-pins { 1199 pins = "gpio16", "gpio17", "gpio19"; 1200 function = "blsp_spi5"; 1201 drive-strength = <12>; 1202 bias-disable; 1203 }; 1204 cs-pins { 1205 pins = "gpio18"; 1206 function = "gpio"; 1207 drive-strength = <16>; 1208 bias-disable; 1209 output-high; 1210 }; 1211 }; 1212 1213 blsp_spi5_sleep: blsp-spi5-sleep-state { 1214 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 1215 function = "gpio"; 1216 drive-strength = <2>; 1217 bias-pull-down; 1218 }; 1219 1220 blsp_spi6_default: blsp-spi6-default-state { 1221 spi-pins { 1222 pins = "gpio20", "gpio21", "gpio23"; 1223 function = "blsp_spi6"; 1224 drive-strength = <12>; 1225 bias-disable; 1226 }; 1227 cs-pins { 1228 pins = "gpio22"; 1229 function = "gpio"; 1230 drive-strength = <16>; 1231 bias-disable; 1232 output-high; 1233 }; 1234 }; 1235 1236 blsp_spi6_sleep: blsp-spi6-sleep-state { 1237 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 1238 function = "gpio"; 1239 drive-strength = <2>; 1240 bias-pull-down; 1241 }; 1242 1243 blsp_uart1_default: blsp-uart1-default-state { 1244 /* TX, RX, CTS_N, RTS_N */ 1245 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1246 function = "blsp_uart1"; 1247 drive-strength = <16>; 1248 bias-disable; 1249 }; 1250 1251 blsp_uart1_sleep: blsp-uart1-sleep-state { 1252 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1253 function = "gpio"; 1254 drive-strength = <2>; 1255 bias-pull-down; 1256 }; 1257 1258 blsp_uart2_default: blsp-uart2-default-state { 1259 pins = "gpio4", "gpio5"; 1260 function = "blsp_uart2"; 1261 drive-strength = <16>; 1262 bias-disable; 1263 }; 1264 1265 blsp_uart2_sleep: blsp-uart2-sleep-state { 1266 pins = "gpio4", "gpio5"; 1267 function = "gpio"; 1268 drive-strength = <2>; 1269 bias-pull-down; 1270 }; 1271 1272 camera_front_default: camera-front-default-state { 1273 pwdn-pins { 1274 pins = "gpio33"; 1275 function = "gpio"; 1276 drive-strength = <16>; 1277 bias-disable; 1278 }; 1279 rst-pins { 1280 pins = "gpio28"; 1281 function = "gpio"; 1282 drive-strength = <16>; 1283 bias-disable; 1284 }; 1285 mclk1-pins { 1286 pins = "gpio27"; 1287 function = "cam_mclk1"; 1288 drive-strength = <16>; 1289 bias-disable; 1290 }; 1291 }; 1292 1293 camera_rear_default: camera-rear-default-state { 1294 pwdn-pins { 1295 pins = "gpio34"; 1296 function = "gpio"; 1297 drive-strength = <16>; 1298 bias-disable; 1299 }; 1300 rst-pins { 1301 pins = "gpio35"; 1302 function = "gpio"; 1303 drive-strength = <16>; 1304 bias-disable; 1305 }; 1306 mclk0-pins { 1307 pins = "gpio26"; 1308 function = "cam_mclk0"; 1309 drive-strength = <16>; 1310 bias-disable; 1311 }; 1312 }; 1313 1314 cci0_default: cci0-default-state { 1315 pins = "gpio29", "gpio30"; 1316 function = "cci_i2c"; 1317 drive-strength = <16>; 1318 bias-disable; 1319 }; 1320 1321 cdc_dmic_default: cdc-dmic-default-state { 1322 clk-pins { 1323 pins = "gpio0"; 1324 function = "dmic0_clk"; 1325 drive-strength = <8>; 1326 }; 1327 data-pins { 1328 pins = "gpio1"; 1329 function = "dmic0_data"; 1330 drive-strength = <8>; 1331 }; 1332 }; 1333 1334 cdc_dmic_sleep: cdc-dmic-sleep-state { 1335 clk-pins { 1336 pins = "gpio0"; 1337 function = "dmic0_clk"; 1338 drive-strength = <2>; 1339 bias-disable; 1340 }; 1341 data-pins { 1342 pins = "gpio1"; 1343 function = "dmic0_data"; 1344 drive-strength = <2>; 1345 bias-disable; 1346 }; 1347 }; 1348 1349 cdc_pdm_default: cdc-pdm-default-state { 1350 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1351 "gpio67", "gpio68"; 1352 function = "cdc_pdm0"; 1353 drive-strength = <8>; 1354 bias-disable; 1355 }; 1356 1357 cdc_pdm_sleep: cdc-pdm-sleep-state { 1358 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1359 "gpio67", "gpio68"; 1360 function = "cdc_pdm0"; 1361 drive-strength = <2>; 1362 bias-pull-down; 1363 }; 1364 1365 pri_mi2s_default: mi2s-pri-default-state { 1366 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1367 function = "pri_mi2s"; 1368 drive-strength = <8>; 1369 bias-disable; 1370 }; 1371 1372 pri_mi2s_sleep: mi2s-pri-sleep-state { 1373 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1374 function = "pri_mi2s"; 1375 drive-strength = <2>; 1376 bias-disable; 1377 }; 1378 1379 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { 1380 pins = "gpio116"; 1381 function = "pri_mi2s"; 1382 drive-strength = <8>; 1383 bias-disable; 1384 }; 1385 1386 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { 1387 pins = "gpio116"; 1388 function = "pri_mi2s"; 1389 drive-strength = <2>; 1390 bias-disable; 1391 }; 1392 1393 pri_mi2s_ws_default: mi2s-pri-ws-default-state { 1394 pins = "gpio110"; 1395 function = "pri_mi2s_ws"; 1396 drive-strength = <8>; 1397 bias-disable; 1398 }; 1399 1400 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { 1401 pins = "gpio110"; 1402 function = "pri_mi2s_ws"; 1403 drive-strength = <2>; 1404 bias-disable; 1405 }; 1406 1407 sec_mi2s_default: mi2s-sec-default-state { 1408 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1409 function = "sec_mi2s"; 1410 drive-strength = <8>; 1411 bias-disable; 1412 }; 1413 1414 sec_mi2s_sleep: mi2s-sec-sleep-state { 1415 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1416 function = "sec_mi2s"; 1417 drive-strength = <2>; 1418 bias-disable; 1419 }; 1420 1421 sdc1_default: sdc1-default-state { 1422 clk-pins { 1423 pins = "sdc1_clk"; 1424 bias-disable; 1425 drive-strength = <16>; 1426 }; 1427 cmd-pins { 1428 pins = "sdc1_cmd"; 1429 bias-pull-up; 1430 drive-strength = <10>; 1431 }; 1432 data-pins { 1433 pins = "sdc1_data"; 1434 bias-pull-up; 1435 drive-strength = <10>; 1436 }; 1437 }; 1438 1439 sdc1_sleep: sdc1-sleep-state { 1440 clk-pins { 1441 pins = "sdc1_clk"; 1442 bias-disable; 1443 drive-strength = <2>; 1444 }; 1445 cmd-pins { 1446 pins = "sdc1_cmd"; 1447 bias-pull-up; 1448 drive-strength = <2>; 1449 }; 1450 data-pins { 1451 pins = "sdc1_data"; 1452 bias-pull-up; 1453 drive-strength = <2>; 1454 }; 1455 }; 1456 1457 sdc2_default: sdc2-default-state { 1458 clk-pins { 1459 pins = "sdc2_clk"; 1460 bias-disable; 1461 drive-strength = <16>; 1462 }; 1463 cmd-pins { 1464 pins = "sdc2_cmd"; 1465 bias-pull-up; 1466 drive-strength = <10>; 1467 }; 1468 data-pins { 1469 pins = "sdc2_data"; 1470 bias-pull-up; 1471 drive-strength = <10>; 1472 }; 1473 }; 1474 1475 sdc2_sleep: sdc2-sleep-state { 1476 clk-pins { 1477 pins = "sdc2_clk"; 1478 bias-disable; 1479 drive-strength = <2>; 1480 }; 1481 cmd-pins { 1482 pins = "sdc2_cmd"; 1483 bias-pull-up; 1484 drive-strength = <2>; 1485 }; 1486 data-pins { 1487 pins = "sdc2_data"; 1488 bias-pull-up; 1489 drive-strength = <2>; 1490 }; 1491 }; 1492 1493 wcss_wlan_default: wcss-wlan-default-state { 1494 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; 1495 function = "wcss_wlan"; 1496 drive-strength = <6>; 1497 bias-pull-up; 1498 }; 1499 }; 1500 1501 gcc: clock-controller@1800000 { 1502 compatible = "qcom,gcc-msm8916"; 1503 #clock-cells = <1>; 1504 #reset-cells = <1>; 1505 #power-domain-cells = <1>; 1506 reg = <0x01800000 0x80000>; 1507 clocks = <&xo_board>, 1508 <&sleep_clk>, 1509 <&mdss_dsi0_phy 1>, 1510 <&mdss_dsi0_phy 0>, 1511 <0>, 1512 <0>, 1513 <0>; 1514 clock-names = "xo", 1515 "sleep_clk", 1516 "dsi0pll", 1517 "dsi0pllbyte", 1518 "ext_mclk", 1519 "ext_pri_i2s", 1520 "ext_sec_i2s"; 1521 }; 1522 1523 tcsr_mutex: hwlock@1905000 { 1524 compatible = "qcom,tcsr-mutex"; 1525 reg = <0x01905000 0x20000>; 1526 #hwlock-cells = <1>; 1527 }; 1528 1529 tcsr: syscon@1937000 { 1530 compatible = "qcom,tcsr-msm8916", "syscon"; 1531 reg = <0x01937000 0x30000>; 1532 }; 1533 1534 mdss: display-subsystem@1a00000 { 1535 status = "disabled"; 1536 compatible = "qcom,mdss"; 1537 reg = <0x01a00000 0x1000>, 1538 <0x01ac8000 0x3000>; 1539 reg-names = "mdss_phys", "vbif_phys"; 1540 1541 power-domains = <&gcc MDSS_GDSC>; 1542 1543 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1544 <&gcc GCC_MDSS_AXI_CLK>, 1545 <&gcc GCC_MDSS_VSYNC_CLK>; 1546 clock-names = "iface", 1547 "bus", 1548 "vsync"; 1549 1550 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1551 1552 interrupt-controller; 1553 #interrupt-cells = <1>; 1554 1555 #address-cells = <1>; 1556 #size-cells = <1>; 1557 ranges; 1558 1559 mdss_mdp: display-controller@1a01000 { 1560 compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; 1561 reg = <0x01a01000 0x89000>; 1562 reg-names = "mdp_phys"; 1563 1564 interrupt-parent = <&mdss>; 1565 interrupts = <0>; 1566 1567 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1568 <&gcc GCC_MDSS_AXI_CLK>, 1569 <&gcc GCC_MDSS_MDP_CLK>, 1570 <&gcc GCC_MDSS_VSYNC_CLK>; 1571 clock-names = "iface", 1572 "bus", 1573 "core", 1574 "vsync"; 1575 1576 iommus = <&apps_iommu 4>; 1577 1578 ports { 1579 #address-cells = <1>; 1580 #size-cells = <0>; 1581 1582 port@0 { 1583 reg = <0>; 1584 mdss_mdp_intf1_out: endpoint { 1585 remote-endpoint = <&mdss_dsi0_in>; 1586 }; 1587 }; 1588 }; 1589 }; 1590 1591 mdss_dsi0: dsi@1a98000 { 1592 compatible = "qcom,msm8916-dsi-ctrl", 1593 "qcom,mdss-dsi-ctrl"; 1594 reg = <0x01a98000 0x25c>; 1595 reg-names = "dsi_ctrl"; 1596 1597 interrupt-parent = <&mdss>; 1598 interrupts = <4>; 1599 1600 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1601 <&gcc PCLK0_CLK_SRC>; 1602 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1603 <&mdss_dsi0_phy 1>; 1604 1605 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1606 <&gcc GCC_MDSS_AHB_CLK>, 1607 <&gcc GCC_MDSS_AXI_CLK>, 1608 <&gcc GCC_MDSS_BYTE0_CLK>, 1609 <&gcc GCC_MDSS_PCLK0_CLK>, 1610 <&gcc GCC_MDSS_ESC0_CLK>; 1611 clock-names = "mdp_core", 1612 "iface", 1613 "bus", 1614 "byte", 1615 "pixel", 1616 "core"; 1617 phys = <&mdss_dsi0_phy>; 1618 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 1622 ports { 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 1626 port@0 { 1627 reg = <0>; 1628 mdss_dsi0_in: endpoint { 1629 remote-endpoint = <&mdss_mdp_intf1_out>; 1630 }; 1631 }; 1632 1633 port@1 { 1634 reg = <1>; 1635 mdss_dsi0_out: endpoint { 1636 }; 1637 }; 1638 }; 1639 }; 1640 1641 mdss_dsi0_phy: phy@1a98300 { 1642 compatible = "qcom,dsi-phy-28nm-lp"; 1643 reg = <0x01a98300 0xd4>, 1644 <0x01a98500 0x280>, 1645 <0x01a98780 0x30>; 1646 reg-names = "dsi_pll", 1647 "dsi_phy", 1648 "dsi_phy_regulator"; 1649 1650 #clock-cells = <1>; 1651 #phy-cells = <0>; 1652 1653 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1654 <&xo_board>; 1655 clock-names = "iface", "ref"; 1656 }; 1657 }; 1658 1659 camss: camss@1b0ac00 { 1660 compatible = "qcom,msm8916-camss"; 1661 reg = <0x01b0ac00 0x200>, 1662 <0x01b00030 0x4>, 1663 <0x01b0b000 0x200>, 1664 <0x01b00038 0x4>, 1665 <0x01b08000 0x100>, 1666 <0x01b08400 0x100>, 1667 <0x01b0a000 0x500>, 1668 <0x01b00020 0x10>, 1669 <0x01b10000 0x1000>; 1670 reg-names = "csiphy0", 1671 "csiphy0_clk_mux", 1672 "csiphy1", 1673 "csiphy1_clk_mux", 1674 "csid0", 1675 "csid1", 1676 "ispif", 1677 "csi_clk_mux", 1678 "vfe0"; 1679 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1680 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1681 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1682 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1683 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1684 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1685 interrupt-names = "csiphy0", 1686 "csiphy1", 1687 "csid0", 1688 "csid1", 1689 "ispif", 1690 "vfe0"; 1691 power-domains = <&gcc VFE_GDSC>; 1692 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1693 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1694 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1695 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1696 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1697 <&gcc GCC_CAMSS_CSI0_CLK>, 1698 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1699 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1700 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1701 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1702 <&gcc GCC_CAMSS_CSI1_CLK>, 1703 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1704 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1705 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1706 <&gcc GCC_CAMSS_AHB_CLK>, 1707 <&gcc GCC_CAMSS_VFE0_CLK>, 1708 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1709 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1710 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1711 clock-names = "top_ahb", 1712 "ispif_ahb", 1713 "csiphy0_timer", 1714 "csiphy1_timer", 1715 "csi0_ahb", 1716 "csi0", 1717 "csi0_phy", 1718 "csi0_pix", 1719 "csi0_rdi", 1720 "csi1_ahb", 1721 "csi1", 1722 "csi1_phy", 1723 "csi1_pix", 1724 "csi1_rdi", 1725 "ahb", 1726 "vfe0", 1727 "csi_vfe0", 1728 "vfe_ahb", 1729 "vfe_axi"; 1730 iommus = <&apps_iommu 3>; 1731 status = "disabled"; 1732 ports { 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 port@0 { 1737 reg = <0>; 1738 }; 1739 1740 port@1 { 1741 reg = <1>; 1742 }; 1743 }; 1744 }; 1745 1746 cci: cci@1b0c000 { 1747 compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; 1748 #address-cells = <1>; 1749 #size-cells = <0>; 1750 reg = <0x01b0c000 0x1000>; 1751 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1752 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1753 <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1754 <&gcc GCC_CAMSS_CCI_CLK>, 1755 <&gcc GCC_CAMSS_AHB_CLK>; 1756 clock-names = "camss_top_ahb", "cci_ahb", 1757 "cci", "camss_ahb"; 1758 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1759 <&gcc GCC_CAMSS_CCI_CLK>; 1760 assigned-clock-rates = <80000000>, <19200000>; 1761 pinctrl-names = "default"; 1762 pinctrl-0 = <&cci0_default>; 1763 status = "disabled"; 1764 1765 cci_i2c0: i2c-bus@0 { 1766 reg = <0>; 1767 clock-frequency = <400000>; 1768 #address-cells = <1>; 1769 #size-cells = <0>; 1770 }; 1771 }; 1772 1773 gpu: gpu@1c00000 { 1774 compatible = "qcom,adreno-306.0", "qcom,adreno"; 1775 reg = <0x01c00000 0x20000>; 1776 reg-names = "kgsl_3d0_reg_memory"; 1777 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1778 interrupt-names = "kgsl_3d0_irq"; 1779 clock-names = 1780 "core", 1781 "iface", 1782 "mem", 1783 "mem_iface", 1784 "alt_mem_iface", 1785 "gfx3d"; 1786 clocks = 1787 <&gcc GCC_OXILI_GFX3D_CLK>, 1788 <&gcc GCC_OXILI_AHB_CLK>, 1789 <&gcc GCC_OXILI_GMEM_CLK>, 1790 <&gcc GCC_BIMC_GFX_CLK>, 1791 <&gcc GCC_BIMC_GPU_CLK>, 1792 <&gcc GFX3D_CLK_SRC>; 1793 power-domains = <&gcc OXILI_GDSC>; 1794 operating-points-v2 = <&gpu_opp_table>; 1795 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1796 status = "disabled"; 1797 1798 gpu_opp_table: opp-table { 1799 compatible = "operating-points-v2"; 1800 1801 opp-400000000 { 1802 opp-hz = /bits/ 64 <400000000>; 1803 }; 1804 opp-19200000 { 1805 opp-hz = /bits/ 64 <19200000>; 1806 }; 1807 }; 1808 }; 1809 1810 venus: video-codec@1d00000 { 1811 compatible = "qcom,msm8916-venus"; 1812 reg = <0x01d00000 0xff000>; 1813 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1814 power-domains = <&gcc VENUS_GDSC>; 1815 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1816 <&gcc GCC_VENUS0_AHB_CLK>, 1817 <&gcc GCC_VENUS0_AXI_CLK>; 1818 clock-names = "core", "iface", "bus"; 1819 iommus = <&apps_iommu 5>; 1820 memory-region = <&venus_mem>; 1821 status = "disabled"; 1822 1823 video-decoder { 1824 compatible = "venus-decoder"; 1825 }; 1826 1827 video-encoder { 1828 compatible = "venus-encoder"; 1829 }; 1830 }; 1831 1832 apps_iommu: iommu@1ef0000 { 1833 #address-cells = <1>; 1834 #size-cells = <1>; 1835 #iommu-cells = <1>; 1836 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1837 ranges = <0 0x01e20000 0x20000>; 1838 reg = <0x01ef0000 0x3000>; 1839 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1840 <&gcc GCC_APSS_TCU_CLK>; 1841 clock-names = "iface", "bus"; 1842 qcom,iommu-secure-id = <17>; 1843 1844 /* VFE */ 1845 iommu-ctx@3000 { 1846 compatible = "qcom,msm-iommu-v1-sec"; 1847 reg = <0x3000 0x1000>; 1848 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1849 }; 1850 1851 /* MDP_0 */ 1852 iommu-ctx@4000 { 1853 compatible = "qcom,msm-iommu-v1-ns"; 1854 reg = <0x4000 0x1000>; 1855 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1856 }; 1857 1858 /* VENUS_NS */ 1859 iommu-ctx@5000 { 1860 compatible = "qcom,msm-iommu-v1-sec"; 1861 reg = <0x5000 0x1000>; 1862 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1863 }; 1864 }; 1865 1866 gpu_iommu: iommu@1f08000 { 1867 #address-cells = <1>; 1868 #size-cells = <1>; 1869 #iommu-cells = <1>; 1870 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1871 ranges = <0 0x01f08000 0x10000>; 1872 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1873 <&gcc GCC_GFX_TCU_CLK>; 1874 clock-names = "iface", "bus"; 1875 qcom,iommu-secure-id = <18>; 1876 1877 /* GFX3D_USER */ 1878 iommu-ctx@1000 { 1879 compatible = "qcom,msm-iommu-v1-ns"; 1880 reg = <0x1000 0x1000>; 1881 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1882 }; 1883 1884 /* GFX3D_PRIV */ 1885 iommu-ctx@2000 { 1886 compatible = "qcom,msm-iommu-v1-ns"; 1887 reg = <0x2000 0x1000>; 1888 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1889 }; 1890 }; 1891 1892 spmi_bus: spmi@200f000 { 1893 compatible = "qcom,spmi-pmic-arb"; 1894 reg = <0x0200f000 0x001000>, 1895 <0x02400000 0x400000>, 1896 <0x02c00000 0x400000>, 1897 <0x03800000 0x200000>, 1898 <0x0200a000 0x002100>; 1899 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1900 interrupt-names = "periph_irq"; 1901 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1902 qcom,ee = <0>; 1903 qcom,channel = <0>; 1904 #address-cells = <2>; 1905 #size-cells = <0>; 1906 interrupt-controller; 1907 #interrupt-cells = <4>; 1908 }; 1909 1910 bam_dmux_dma: dma-controller@4044000 { 1911 compatible = "qcom,bam-v1.7.0"; 1912 reg = <0x04044000 0x19000>; 1913 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1914 #dma-cells = <1>; 1915 qcom,ee = <0>; 1916 1917 num-channels = <6>; 1918 qcom,num-ees = <1>; 1919 qcom,powered-remotely; 1920 1921 status = "disabled"; 1922 }; 1923 1924 mpss: remoteproc@4080000 { 1925 compatible = "qcom,msm8916-mss-pil"; 1926 reg = <0x04080000 0x100>, 1927 <0x04020000 0x040>; 1928 1929 reg-names = "qdsp6", "rmb"; 1930 1931 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1932 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1933 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1934 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1935 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1936 interrupt-names = "wdog", "fatal", "ready", 1937 "handover", "stop-ack"; 1938 1939 power-domains = <&rpmpd MSM8916_VDDCX>, 1940 <&rpmpd MSM8916_VDDMX>; 1941 power-domain-names = "cx", "mx"; 1942 1943 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1944 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1945 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1946 <&xo_board>; 1947 clock-names = "iface", "bus", "mem", "xo"; 1948 1949 qcom,smem-states = <&hexagon_smp2p_out 0>; 1950 qcom,smem-state-names = "stop"; 1951 1952 resets = <&scm 0>; 1953 reset-names = "mss_restart"; 1954 1955 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1956 1957 status = "disabled"; 1958 1959 mba { 1960 memory-region = <&mba_mem>; 1961 }; 1962 1963 mpss { 1964 memory-region = <&mpss_mem>; 1965 }; 1966 1967 bam_dmux: bam-dmux { 1968 compatible = "qcom,bam-dmux"; 1969 1970 interrupt-parent = <&hexagon_smsm>; 1971 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1972 interrupt-names = "pc", "pc-ack"; 1973 1974 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1975 qcom,smem-state-names = "pc", "pc-ack"; 1976 1977 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1978 dma-names = "tx", "rx"; 1979 1980 status = "disabled"; 1981 }; 1982 1983 smd-edge { 1984 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1985 1986 qcom,smd-edge = <0>; 1987 qcom,ipc = <&apcs 8 12>; 1988 qcom,remote-pid = <1>; 1989 1990 label = "hexagon"; 1991 1992 fastrpc { 1993 compatible = "qcom,fastrpc"; 1994 qcom,smd-channels = "fastrpcsmd-apps-dsp"; 1995 label = "adsp"; 1996 qcom,non-secure-domain; 1997 1998 #address-cells = <1>; 1999 #size-cells = <0>; 2000 2001 cb@1 { 2002 compatible = "qcom,fastrpc-compute-cb"; 2003 reg = <1>; 2004 }; 2005 }; 2006 }; 2007 }; 2008 2009 sound: sound@7702000 { 2010 status = "disabled"; 2011 compatible = "qcom,apq8016-sbc-sndcard"; 2012 reg = <0x07702000 0x4>, <0x07702004 0x4>; 2013 reg-names = "mic-iomux", "spkr-iomux"; 2014 }; 2015 2016 lpass: audio-controller@7708000 { 2017 status = "disabled"; 2018 compatible = "qcom,apq8016-lpass-cpu"; 2019 2020 /* 2021 * Note: Unlike the name would suggest, the SEC_I2S_CLK 2022 * is actually only used by Tertiary MI2S while 2023 * Primary/Secondary MI2S both use the PRI_I2S_CLK. 2024 */ 2025 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 2026 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 2027 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 2028 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 2029 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, 2030 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 2031 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; 2032 2033 clock-names = "ahbix-clk", 2034 "mi2s-bit-clk0", 2035 "mi2s-bit-clk1", 2036 "mi2s-bit-clk2", 2037 "mi2s-bit-clk3", 2038 "pcnoc-mport-clk", 2039 "pcnoc-sway-clk"; 2040 #sound-dai-cells = <1>; 2041 2042 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2043 interrupt-names = "lpass-irq-lpaif"; 2044 reg = <0x07708000 0x10000>; 2045 reg-names = "lpass-lpaif"; 2046 2047 #address-cells = <1>; 2048 #size-cells = <0>; 2049 }; 2050 2051 lpass_codec: audio-codec@771c000 { 2052 compatible = "qcom,msm8916-wcd-digital-codec"; 2053 reg = <0x0771c000 0x400>; 2054 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 2055 <&gcc GCC_CODEC_DIGCODEC_CLK>; 2056 clock-names = "ahbix-clk", "mclk"; 2057 #sound-dai-cells = <1>; 2058 status = "disabled"; 2059 }; 2060 2061 sdhc_1: mmc@7824900 { 2062 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 2063 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 2064 reg-names = "hc", "core"; 2065 2066 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2067 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2068 interrupt-names = "hc_irq", "pwr_irq"; 2069 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 2070 <&gcc GCC_SDCC1_APPS_CLK>, 2071 <&xo_board>; 2072 clock-names = "iface", "core", "xo"; 2073 pinctrl-0 = <&sdc1_default>; 2074 pinctrl-1 = <&sdc1_sleep>; 2075 pinctrl-names = "default", "sleep"; 2076 mmc-ddr-1_8v; 2077 bus-width = <8>; 2078 non-removable; 2079 status = "disabled"; 2080 }; 2081 2082 sdhc_2: mmc@7864900 { 2083 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 2084 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 2085 reg-names = "hc", "core"; 2086 2087 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2089 interrupt-names = "hc_irq", "pwr_irq"; 2090 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2091 <&gcc GCC_SDCC2_APPS_CLK>, 2092 <&xo_board>; 2093 clock-names = "iface", "core", "xo"; 2094 pinctrl-0 = <&sdc2_default>; 2095 pinctrl-1 = <&sdc2_sleep>; 2096 pinctrl-names = "default", "sleep"; 2097 bus-width = <4>; 2098 status = "disabled"; 2099 }; 2100 2101 blsp_dma: dma-controller@7884000 { 2102 compatible = "qcom,bam-v1.7.0"; 2103 reg = <0x07884000 0x23000>; 2104 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2105 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2106 clock-names = "bam_clk"; 2107 #dma-cells = <1>; 2108 qcom,ee = <0>; 2109 }; 2110 2111 blsp_uart1: serial@78af000 { 2112 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2113 reg = <0x078af000 0x200>; 2114 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 2115 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 2116 clock-names = "core", "iface"; 2117 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 2118 dma-names = "tx", "rx"; 2119 pinctrl-names = "default", "sleep"; 2120 pinctrl-0 = <&blsp_uart1_default>; 2121 pinctrl-1 = <&blsp_uart1_sleep>; 2122 status = "disabled"; 2123 }; 2124 2125 blsp_uart2: serial@78b0000 { 2126 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2127 reg = <0x078b0000 0x200>; 2128 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2129 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 2130 clock-names = "core", "iface"; 2131 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 2132 dma-names = "tx", "rx"; 2133 pinctrl-names = "default", "sleep"; 2134 pinctrl-0 = <&blsp_uart2_default>; 2135 pinctrl-1 = <&blsp_uart2_sleep>; 2136 status = "disabled"; 2137 }; 2138 2139 blsp_i2c1: i2c@78b5000 { 2140 compatible = "qcom,i2c-qup-v2.2.1"; 2141 reg = <0x078b5000 0x500>; 2142 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2143 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2144 <&gcc GCC_BLSP1_AHB_CLK>; 2145 clock-names = "core", "iface"; 2146 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 2147 dma-names = "tx", "rx"; 2148 pinctrl-names = "default", "sleep"; 2149 pinctrl-0 = <&blsp_i2c1_default>; 2150 pinctrl-1 = <&blsp_i2c1_sleep>; 2151 #address-cells = <1>; 2152 #size-cells = <0>; 2153 status = "disabled"; 2154 }; 2155 2156 blsp_spi1: spi@78b5000 { 2157 compatible = "qcom,spi-qup-v2.2.1"; 2158 reg = <0x078b5000 0x500>; 2159 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2160 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2161 <&gcc GCC_BLSP1_AHB_CLK>; 2162 clock-names = "core", "iface"; 2163 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 2164 dma-names = "tx", "rx"; 2165 pinctrl-names = "default", "sleep"; 2166 pinctrl-0 = <&blsp_spi1_default>; 2167 pinctrl-1 = <&blsp_spi1_sleep>; 2168 #address-cells = <1>; 2169 #size-cells = <0>; 2170 status = "disabled"; 2171 }; 2172 2173 blsp_i2c2: i2c@78b6000 { 2174 compatible = "qcom,i2c-qup-v2.2.1"; 2175 reg = <0x078b6000 0x500>; 2176 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2177 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2178 <&gcc GCC_BLSP1_AHB_CLK>; 2179 clock-names = "core", "iface"; 2180 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 2181 dma-names = "tx", "rx"; 2182 pinctrl-names = "default", "sleep"; 2183 pinctrl-0 = <&blsp_i2c2_default>; 2184 pinctrl-1 = <&blsp_i2c2_sleep>; 2185 #address-cells = <1>; 2186 #size-cells = <0>; 2187 status = "disabled"; 2188 }; 2189 2190 blsp_spi2: spi@78b6000 { 2191 compatible = "qcom,spi-qup-v2.2.1"; 2192 reg = <0x078b6000 0x500>; 2193 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2194 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 2195 <&gcc GCC_BLSP1_AHB_CLK>; 2196 clock-names = "core", "iface"; 2197 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 2198 dma-names = "tx", "rx"; 2199 pinctrl-names = "default", "sleep"; 2200 pinctrl-0 = <&blsp_spi2_default>; 2201 pinctrl-1 = <&blsp_spi2_sleep>; 2202 #address-cells = <1>; 2203 #size-cells = <0>; 2204 status = "disabled"; 2205 }; 2206 2207 blsp_i2c3: i2c@78b7000 { 2208 compatible = "qcom,i2c-qup-v2.2.1"; 2209 reg = <0x078b7000 0x500>; 2210 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2211 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2212 <&gcc GCC_BLSP1_AHB_CLK>; 2213 clock-names = "core", "iface"; 2214 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 2215 dma-names = "tx", "rx"; 2216 pinctrl-names = "default", "sleep"; 2217 pinctrl-0 = <&blsp_i2c3_default>; 2218 pinctrl-1 = <&blsp_i2c3_sleep>; 2219 #address-cells = <1>; 2220 #size-cells = <0>; 2221 status = "disabled"; 2222 }; 2223 2224 blsp_spi3: spi@78b7000 { 2225 compatible = "qcom,spi-qup-v2.2.1"; 2226 reg = <0x078b7000 0x500>; 2227 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2228 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 2229 <&gcc GCC_BLSP1_AHB_CLK>; 2230 clock-names = "core", "iface"; 2231 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 2232 dma-names = "tx", "rx"; 2233 pinctrl-names = "default", "sleep"; 2234 pinctrl-0 = <&blsp_spi3_default>; 2235 pinctrl-1 = <&blsp_spi3_sleep>; 2236 #address-cells = <1>; 2237 #size-cells = <0>; 2238 status = "disabled"; 2239 }; 2240 2241 blsp_i2c4: i2c@78b8000 { 2242 compatible = "qcom,i2c-qup-v2.2.1"; 2243 reg = <0x078b8000 0x500>; 2244 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2245 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2246 <&gcc GCC_BLSP1_AHB_CLK>; 2247 clock-names = "core", "iface"; 2248 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 2249 dma-names = "tx", "rx"; 2250 pinctrl-names = "default", "sleep"; 2251 pinctrl-0 = <&blsp_i2c4_default>; 2252 pinctrl-1 = <&blsp_i2c4_sleep>; 2253 #address-cells = <1>; 2254 #size-cells = <0>; 2255 status = "disabled"; 2256 }; 2257 2258 blsp_spi4: spi@78b8000 { 2259 compatible = "qcom,spi-qup-v2.2.1"; 2260 reg = <0x078b8000 0x500>; 2261 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2262 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 2263 <&gcc GCC_BLSP1_AHB_CLK>; 2264 clock-names = "core", "iface"; 2265 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 2266 dma-names = "tx", "rx"; 2267 pinctrl-names = "default", "sleep"; 2268 pinctrl-0 = <&blsp_spi4_default>; 2269 pinctrl-1 = <&blsp_spi4_sleep>; 2270 #address-cells = <1>; 2271 #size-cells = <0>; 2272 status = "disabled"; 2273 }; 2274 2275 blsp_i2c5: i2c@78b9000 { 2276 compatible = "qcom,i2c-qup-v2.2.1"; 2277 reg = <0x078b9000 0x500>; 2278 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2279 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2280 <&gcc GCC_BLSP1_AHB_CLK>; 2281 clock-names = "core", "iface"; 2282 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 2283 dma-names = "tx", "rx"; 2284 pinctrl-names = "default", "sleep"; 2285 pinctrl-0 = <&blsp_i2c5_default>; 2286 pinctrl-1 = <&blsp_i2c5_sleep>; 2287 #address-cells = <1>; 2288 #size-cells = <0>; 2289 status = "disabled"; 2290 }; 2291 2292 blsp_spi5: spi@78b9000 { 2293 compatible = "qcom,spi-qup-v2.2.1"; 2294 reg = <0x078b9000 0x500>; 2295 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2296 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 2297 <&gcc GCC_BLSP1_AHB_CLK>; 2298 clock-names = "core", "iface"; 2299 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 2300 dma-names = "tx", "rx"; 2301 pinctrl-names = "default", "sleep"; 2302 pinctrl-0 = <&blsp_spi5_default>; 2303 pinctrl-1 = <&blsp_spi5_sleep>; 2304 #address-cells = <1>; 2305 #size-cells = <0>; 2306 status = "disabled"; 2307 }; 2308 2309 blsp_i2c6: i2c@78ba000 { 2310 compatible = "qcom,i2c-qup-v2.2.1"; 2311 reg = <0x078ba000 0x500>; 2312 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2313 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2314 <&gcc GCC_BLSP1_AHB_CLK>; 2315 clock-names = "core", "iface"; 2316 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 2317 dma-names = "tx", "rx"; 2318 pinctrl-names = "default", "sleep"; 2319 pinctrl-0 = <&blsp_i2c6_default>; 2320 pinctrl-1 = <&blsp_i2c6_sleep>; 2321 #address-cells = <1>; 2322 #size-cells = <0>; 2323 status = "disabled"; 2324 }; 2325 2326 blsp_spi6: spi@78ba000 { 2327 compatible = "qcom,spi-qup-v2.2.1"; 2328 reg = <0x078ba000 0x500>; 2329 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2330 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 2331 <&gcc GCC_BLSP1_AHB_CLK>; 2332 clock-names = "core", "iface"; 2333 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 2334 dma-names = "tx", "rx"; 2335 pinctrl-names = "default", "sleep"; 2336 pinctrl-0 = <&blsp_spi6_default>; 2337 pinctrl-1 = <&blsp_spi6_sleep>; 2338 #address-cells = <1>; 2339 #size-cells = <0>; 2340 status = "disabled"; 2341 }; 2342 2343 usb: usb@78d9000 { 2344 compatible = "qcom,ci-hdrc"; 2345 reg = <0x078d9000 0x200>, 2346 <0x078d9200 0x200>; 2347 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2348 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2349 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 2350 <&gcc GCC_USB_HS_SYSTEM_CLK>; 2351 clock-names = "iface", "core"; 2352 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 2353 assigned-clock-rates = <80000000>; 2354 resets = <&gcc GCC_USB_HS_BCR>; 2355 reset-names = "core"; 2356 phy_type = "ulpi"; 2357 dr_mode = "otg"; 2358 hnp-disable; 2359 srp-disable; 2360 adp-disable; 2361 ahb-burst-config = <0>; 2362 phy-names = "usb-phy"; 2363 phys = <&usb_hs_phy>; 2364 status = "disabled"; 2365 #reset-cells = <1>; 2366 2367 ulpi { 2368 usb_hs_phy: phy { 2369 compatible = "qcom,usb-hs-phy-msm8916", 2370 "qcom,usb-hs-phy"; 2371 #phy-cells = <0>; 2372 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 2373 clock-names = "ref", "sleep"; 2374 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 2375 reset-names = "phy", "por"; 2376 qcom,init-seq = /bits/ 8 <0x0 0x44>, 2377 <0x1 0x6b>, 2378 <0x2 0x24>, 2379 <0x3 0x13>; 2380 }; 2381 }; 2382 }; 2383 2384 wcnss: remoteproc@a204000 { 2385 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 2386 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 2387 reg-names = "ccu", "dxe", "pmu"; 2388 2389 memory-region = <&wcnss_mem>; 2390 2391 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 2392 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2393 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2394 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2395 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2396 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2397 2398 power-domains = <&rpmpd MSM8916_VDDCX>, 2399 <&rpmpd MSM8916_VDDMX>; 2400 power-domain-names = "cx", "mx"; 2401 2402 qcom,smem-states = <&wcnss_smp2p_out 0>; 2403 qcom,smem-state-names = "stop"; 2404 2405 pinctrl-names = "default"; 2406 pinctrl-0 = <&wcss_wlan_default>; 2407 2408 status = "disabled"; 2409 2410 wcnss_iris: iris { 2411 /* Separate chip, compatible is board-specific */ 2412 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 2413 clock-names = "xo"; 2414 }; 2415 2416 smd-edge { 2417 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 2418 2419 qcom,ipc = <&apcs 8 17>; 2420 qcom,smd-edge = <6>; 2421 qcom,remote-pid = <4>; 2422 2423 label = "pronto"; 2424 2425 wcnss_ctrl: wcnss { 2426 compatible = "qcom,wcnss"; 2427 qcom,smd-channels = "WCNSS_CTRL"; 2428 2429 qcom,mmio = <&wcnss>; 2430 2431 wcnss_bt: bluetooth { 2432 compatible = "qcom,wcnss-bt"; 2433 }; 2434 2435 wcnss_wifi: wifi { 2436 compatible = "qcom,wcnss-wlan"; 2437 2438 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2440 interrupt-names = "tx", "rx"; 2441 2442 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 2443 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 2444 }; 2445 }; 2446 }; 2447 }; 2448 2449 intc: interrupt-controller@b000000 { 2450 compatible = "qcom,msm-qgic2"; 2451 interrupt-controller; 2452 #interrupt-cells = <3>; 2453 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 2454 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 2455 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 2456 }; 2457 2458 apcs: mailbox@b011000 { 2459 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 2460 reg = <0x0b011000 0x1000>; 2461 #mbox-cells = <1>; 2462 clocks = <&a53pll>, <&gcc GPLL0_VOTE>; 2463 clock-names = "pll", "aux"; 2464 #clock-cells = <0>; 2465 }; 2466 2467 a53pll: clock@b016000 { 2468 compatible = "qcom,msm8916-a53pll"; 2469 reg = <0x0b016000 0x40>; 2470 #clock-cells = <0>; 2471 clocks = <&xo_board>; 2472 clock-names = "xo"; 2473 }; 2474 2475 timer@b020000 { 2476 #address-cells = <1>; 2477 #size-cells = <1>; 2478 ranges; 2479 compatible = "arm,armv7-timer-mem"; 2480 reg = <0x0b020000 0x1000>; 2481 clock-frequency = <19200000>; 2482 2483 frame@b021000 { 2484 frame-number = <0>; 2485 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2487 reg = <0x0b021000 0x1000>, 2488 <0x0b022000 0x1000>; 2489 }; 2490 2491 frame@b023000 { 2492 frame-number = <1>; 2493 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2494 reg = <0x0b023000 0x1000>; 2495 status = "disabled"; 2496 }; 2497 2498 frame@b024000 { 2499 frame-number = <2>; 2500 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2501 reg = <0x0b024000 0x1000>; 2502 status = "disabled"; 2503 }; 2504 2505 frame@b025000 { 2506 frame-number = <3>; 2507 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2508 reg = <0x0b025000 0x1000>; 2509 status = "disabled"; 2510 }; 2511 2512 frame@b026000 { 2513 frame-number = <4>; 2514 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2515 reg = <0x0b026000 0x1000>; 2516 status = "disabled"; 2517 }; 2518 2519 frame@b027000 { 2520 frame-number = <5>; 2521 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2522 reg = <0x0b027000 0x1000>; 2523 status = "disabled"; 2524 }; 2525 2526 frame@b028000 { 2527 frame-number = <6>; 2528 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2529 reg = <0x0b028000 0x1000>; 2530 status = "disabled"; 2531 }; 2532 }; 2533 2534 cpu0_acc: power-manager@b088000 { 2535 compatible = "qcom,msm8916-acc"; 2536 reg = <0x0b088000 0x1000>; 2537 status = "reserved"; /* Controlled by PSCI firmware */ 2538 }; 2539 2540 cpu0_saw: power-manager@b089000 { 2541 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2542 reg = <0x0b089000 0x1000>; 2543 status = "reserved"; /* Controlled by PSCI firmware */ 2544 }; 2545 2546 cpu1_acc: power-manager@b098000 { 2547 compatible = "qcom,msm8916-acc"; 2548 reg = <0x0b098000 0x1000>; 2549 status = "reserved"; /* Controlled by PSCI firmware */ 2550 }; 2551 2552 cpu1_saw: power-manager@b099000 { 2553 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2554 reg = <0x0b099000 0x1000>; 2555 status = "reserved"; /* Controlled by PSCI firmware */ 2556 }; 2557 2558 cpu2_acc: power-manager@b0a8000 { 2559 compatible = "qcom,msm8916-acc"; 2560 reg = <0x0b0a8000 0x1000>; 2561 status = "reserved"; /* Controlled by PSCI firmware */ 2562 }; 2563 2564 cpu2_saw: power-manager@b0a9000 { 2565 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2566 reg = <0x0b0a9000 0x1000>; 2567 status = "reserved"; /* Controlled by PSCI firmware */ 2568 }; 2569 2570 cpu3_acc: power-manager@b0b8000 { 2571 compatible = "qcom,msm8916-acc"; 2572 reg = <0x0b0b8000 0x1000>; 2573 status = "reserved"; /* Controlled by PSCI firmware */ 2574 }; 2575 2576 cpu3_saw: power-manager@b0b9000 { 2577 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2578 reg = <0x0b0b9000 0x1000>; 2579 status = "reserved"; /* Controlled by PSCI firmware */ 2580 }; 2581 }; 2582 2583 thermal-zones { 2584 cpu0-1-thermal { 2585 polling-delay-passive = <250>; 2586 polling-delay = <1000>; 2587 2588 thermal-sensors = <&tsens 5>; 2589 2590 trips { 2591 cpu0_1_alert0: trip-point0 { 2592 temperature = <75000>; 2593 hysteresis = <2000>; 2594 type = "passive"; 2595 }; 2596 cpu0_1_crit: cpu-crit { 2597 temperature = <110000>; 2598 hysteresis = <2000>; 2599 type = "critical"; 2600 }; 2601 }; 2602 2603 cooling-maps { 2604 map0 { 2605 trip = <&cpu0_1_alert0>; 2606 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2607 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2608 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2609 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2610 }; 2611 }; 2612 }; 2613 2614 cpu2-3-thermal { 2615 polling-delay-passive = <250>; 2616 polling-delay = <1000>; 2617 2618 thermal-sensors = <&tsens 4>; 2619 2620 trips { 2621 cpu2_3_alert0: trip-point0 { 2622 temperature = <75000>; 2623 hysteresis = <2000>; 2624 type = "passive"; 2625 }; 2626 cpu2_3_crit: cpu-crit { 2627 temperature = <110000>; 2628 hysteresis = <2000>; 2629 type = "critical"; 2630 }; 2631 }; 2632 2633 cooling-maps { 2634 map0 { 2635 trip = <&cpu2_3_alert0>; 2636 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2637 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2638 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2639 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2640 }; 2641 }; 2642 }; 2643 2644 gpu-thermal { 2645 polling-delay-passive = <250>; 2646 polling-delay = <1000>; 2647 2648 thermal-sensors = <&tsens 2>; 2649 2650 trips { 2651 gpu_alert0: trip-point0 { 2652 temperature = <75000>; 2653 hysteresis = <2000>; 2654 type = "passive"; 2655 }; 2656 gpu_crit: gpu-crit { 2657 temperature = <95000>; 2658 hysteresis = <2000>; 2659 type = "critical"; 2660 }; 2661 }; 2662 }; 2663 2664 camera-thermal { 2665 polling-delay-passive = <250>; 2666 polling-delay = <1000>; 2667 2668 thermal-sensors = <&tsens 1>; 2669 2670 trips { 2671 cam_alert0: trip-point0 { 2672 temperature = <75000>; 2673 hysteresis = <2000>; 2674 type = "hot"; 2675 }; 2676 }; 2677 }; 2678 2679 modem-thermal { 2680 polling-delay-passive = <250>; 2681 polling-delay = <1000>; 2682 2683 thermal-sensors = <&tsens 0>; 2684 2685 trips { 2686 modem_alert0: trip-point0 { 2687 temperature = <85000>; 2688 hysteresis = <2000>; 2689 type = "hot"; 2690 }; 2691 }; 2692 }; 2693 }; 2694 2695 timer { 2696 compatible = "arm,armv8-timer"; 2697 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2698 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2699 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2700 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2701 }; 2702}; 2703