1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/arm/coresight-cti-dt.h> 7#include <dt-bindings/clock/qcom,gcc-msm8916.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8916.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8916.h> 13#include <dt-bindings/soc/qcom,apr.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* We expect the bootloader to fill in the reg */ 27 reg = <0 0x80000000 0 0>; 28 }; 29 30 reserved-memory { 31 #address-cells = <2>; 32 #size-cells = <2>; 33 ranges; 34 35 tz-apps@86000000 { 36 reg = <0x0 0x86000000 0x0 0x300000>; 37 no-map; 38 }; 39 40 smem@86300000 { 41 compatible = "qcom,smem"; 42 reg = <0x0 0x86300000 0x0 0x100000>; 43 no-map; 44 45 hwlocks = <&tcsr_mutex 3>; 46 qcom,rpm-msg-ram = <&rpm_msg_ram>; 47 }; 48 49 hypervisor@86400000 { 50 reg = <0x0 0x86400000 0x0 0x100000>; 51 no-map; 52 }; 53 54 tz@86500000 { 55 reg = <0x0 0x86500000 0x0 0x180000>; 56 no-map; 57 }; 58 59 reserved@86680000 { 60 reg = <0x0 0x86680000 0x0 0x80000>; 61 no-map; 62 }; 63 64 rmtfs@86700000 { 65 compatible = "qcom,rmtfs-mem"; 66 reg = <0x0 0x86700000 0x0 0xe0000>; 67 no-map; 68 69 qcom,client-id = <1>; 70 }; 71 72 rfsa@867e0000 { 73 reg = <0x0 0x867e0000 0x0 0x20000>; 74 no-map; 75 }; 76 77 mpss_mem: mpss@86800000 { 78 /* 79 * The memory region for the mpss firmware is generally 80 * relocatable and could be allocated dynamically. 81 * However, many firmware versions tend to fail when 82 * loaded to some special addresses, so it is hard to 83 * define reliable alloc-ranges. 84 * 85 * alignment = <0x0 0x400000>; 86 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 87 */ 88 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */ 89 no-map; 90 status = "disabled"; 91 }; 92 93 wcnss_mem: wcnss { 94 size = <0x0 0x600000>; 95 alignment = <0x0 0x100000>; 96 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 97 no-map; 98 status = "disabled"; 99 }; 100 101 venus_mem: venus { 102 size = <0x0 0x500000>; 103 alignment = <0x0 0x100000>; 104 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 105 no-map; 106 status = "disabled"; 107 }; 108 109 mba_mem: mba { 110 size = <0x0 0x100000>; 111 alignment = <0x0 0x100000>; 112 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 113 no-map; 114 status = "disabled"; 115 }; 116 }; 117 118 clocks { 119 xo_board: xo-board { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 clock-frequency = <19200000>; 123 }; 124 125 sleep_clk: sleep-clk { 126 compatible = "fixed-clock"; 127 #clock-cells = <0>; 128 clock-frequency = <32768>; 129 }; 130 }; 131 132 cpus { 133 #address-cells = <1>; 134 #size-cells = <0>; 135 136 CPU0: cpu@0 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a53"; 139 reg = <0x0>; 140 next-level-cache = <&L2_0>; 141 enable-method = "psci"; 142 clocks = <&apcs>; 143 operating-points-v2 = <&cpu_opp_table>; 144 #cooling-cells = <2>; 145 power-domains = <&CPU_PD0>; 146 power-domain-names = "psci"; 147 qcom,acc = <&cpu0_acc>; 148 qcom,saw = <&cpu0_saw>; 149 }; 150 151 CPU1: cpu@1 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a53"; 154 reg = <0x1>; 155 next-level-cache = <&L2_0>; 156 enable-method = "psci"; 157 clocks = <&apcs>; 158 operating-points-v2 = <&cpu_opp_table>; 159 #cooling-cells = <2>; 160 power-domains = <&CPU_PD1>; 161 power-domain-names = "psci"; 162 qcom,acc = <&cpu1_acc>; 163 qcom,saw = <&cpu1_saw>; 164 }; 165 166 CPU2: cpu@2 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a53"; 169 reg = <0x2>; 170 next-level-cache = <&L2_0>; 171 enable-method = "psci"; 172 clocks = <&apcs>; 173 operating-points-v2 = <&cpu_opp_table>; 174 #cooling-cells = <2>; 175 power-domains = <&CPU_PD2>; 176 power-domain-names = "psci"; 177 qcom,acc = <&cpu2_acc>; 178 qcom,saw = <&cpu2_saw>; 179 }; 180 181 CPU3: cpu@3 { 182 device_type = "cpu"; 183 compatible = "arm,cortex-a53"; 184 reg = <0x3>; 185 next-level-cache = <&L2_0>; 186 enable-method = "psci"; 187 clocks = <&apcs>; 188 operating-points-v2 = <&cpu_opp_table>; 189 #cooling-cells = <2>; 190 power-domains = <&CPU_PD3>; 191 power-domain-names = "psci"; 192 qcom,acc = <&cpu3_acc>; 193 qcom,saw = <&cpu3_saw>; 194 }; 195 196 L2_0: l2-cache { 197 compatible = "cache"; 198 cache-level = <2>; 199 cache-unified; 200 }; 201 202 idle-states { 203 entry-method = "psci"; 204 205 CPU_SLEEP_0: cpu-sleep-0 { 206 compatible = "arm,idle-state"; 207 idle-state-name = "standalone-power-collapse"; 208 arm,psci-suspend-param = <0x40000002>; 209 entry-latency-us = <130>; 210 exit-latency-us = <150>; 211 min-residency-us = <2000>; 212 local-timer-stop; 213 }; 214 }; 215 216 domain-idle-states { 217 218 CLUSTER_RET: cluster-retention { 219 compatible = "domain-idle-state"; 220 arm,psci-suspend-param = <0x41000012>; 221 entry-latency-us = <500>; 222 exit-latency-us = <500>; 223 min-residency-us = <2000>; 224 }; 225 226 CLUSTER_PWRDN: cluster-gdhs { 227 compatible = "domain-idle-state"; 228 arm,psci-suspend-param = <0x41000032>; 229 entry-latency-us = <2000>; 230 exit-latency-us = <2000>; 231 min-residency-us = <6000>; 232 }; 233 }; 234 }; 235 236 cpu_opp_table: opp-table-cpu { 237 compatible = "operating-points-v2"; 238 opp-shared; 239 240 opp-200000000 { 241 opp-hz = /bits/ 64 <200000000>; 242 }; 243 opp-400000000 { 244 opp-hz = /bits/ 64 <400000000>; 245 }; 246 opp-800000000 { 247 opp-hz = /bits/ 64 <800000000>; 248 }; 249 opp-998400000 { 250 opp-hz = /bits/ 64 <998400000>; 251 }; 252 }; 253 254 firmware { 255 scm: scm { 256 compatible = "qcom,scm-msm8916", "qcom,scm"; 257 clocks = <&gcc GCC_CRYPTO_CLK>, 258 <&gcc GCC_CRYPTO_AXI_CLK>, 259 <&gcc GCC_CRYPTO_AHB_CLK>; 260 clock-names = "core", "bus", "iface"; 261 #reset-cells = <1>; 262 263 qcom,dload-mode = <&tcsr 0x6100>; 264 }; 265 }; 266 267 pmu { 268 compatible = "arm,cortex-a53-pmu"; 269 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 270 }; 271 272 psci { 273 compatible = "arm,psci-1.0"; 274 method = "smc"; 275 276 CPU_PD0: power-domain-cpu0 { 277 #power-domain-cells = <0>; 278 power-domains = <&CLUSTER_PD>; 279 domain-idle-states = <&CPU_SLEEP_0>; 280 }; 281 282 CPU_PD1: power-domain-cpu1 { 283 #power-domain-cells = <0>; 284 power-domains = <&CLUSTER_PD>; 285 domain-idle-states = <&CPU_SLEEP_0>; 286 }; 287 288 CPU_PD2: power-domain-cpu2 { 289 #power-domain-cells = <0>; 290 power-domains = <&CLUSTER_PD>; 291 domain-idle-states = <&CPU_SLEEP_0>; 292 }; 293 294 CPU_PD3: power-domain-cpu3 { 295 #power-domain-cells = <0>; 296 power-domains = <&CLUSTER_PD>; 297 domain-idle-states = <&CPU_SLEEP_0>; 298 }; 299 300 CLUSTER_PD: power-domain-cluster { 301 #power-domain-cells = <0>; 302 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; 303 }; 304 }; 305 306 rpm: remoteproc { 307 compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc"; 308 309 smd-edge { 310 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 311 mboxes = <&apcs 0>; 312 qcom,smd-edge = <15>; 313 314 rpm_requests: rpm-requests { 315 compatible = "qcom,rpm-msm8916", "qcom,smd-rpm"; 316 qcom,smd-channels = "rpm_requests"; 317 318 rpmcc: clock-controller { 319 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; 320 #clock-cells = <1>; 321 clocks = <&xo_board>; 322 clock-names = "xo"; 323 }; 324 325 rpmpd: power-controller { 326 compatible = "qcom,msm8916-rpmpd"; 327 #power-domain-cells = <1>; 328 operating-points-v2 = <&rpmpd_opp_table>; 329 330 rpmpd_opp_table: opp-table { 331 compatible = "operating-points-v2"; 332 333 rpmpd_opp_ret: opp1 { 334 opp-level = <1>; 335 }; 336 rpmpd_opp_svs_krait: opp2 { 337 opp-level = <2>; 338 }; 339 rpmpd_opp_svs_soc: opp3 { 340 opp-level = <3>; 341 }; 342 rpmpd_opp_nom: opp4 { 343 opp-level = <4>; 344 }; 345 rpmpd_opp_turbo: opp5 { 346 opp-level = <5>; 347 }; 348 rpmpd_opp_super_turbo: opp6 { 349 opp-level = <6>; 350 }; 351 }; 352 }; 353 }; 354 }; 355 }; 356 357 smp2p-hexagon { 358 compatible = "qcom,smp2p"; 359 qcom,smem = <435>, <428>; 360 361 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 362 363 mboxes = <&apcs 14>; 364 365 qcom,local-pid = <0>; 366 qcom,remote-pid = <1>; 367 368 hexagon_smp2p_out: master-kernel { 369 qcom,entry-name = "master-kernel"; 370 371 #qcom,smem-state-cells = <1>; 372 }; 373 374 hexagon_smp2p_in: slave-kernel { 375 qcom,entry-name = "slave-kernel"; 376 377 interrupt-controller; 378 #interrupt-cells = <2>; 379 }; 380 }; 381 382 smp2p-wcnss { 383 compatible = "qcom,smp2p"; 384 qcom,smem = <451>, <431>; 385 386 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 387 388 mboxes = <&apcs 18>; 389 390 qcom,local-pid = <0>; 391 qcom,remote-pid = <4>; 392 393 wcnss_smp2p_out: master-kernel { 394 qcom,entry-name = "master-kernel"; 395 396 #qcom,smem-state-cells = <1>; 397 }; 398 399 wcnss_smp2p_in: slave-kernel { 400 qcom,entry-name = "slave-kernel"; 401 402 interrupt-controller; 403 #interrupt-cells = <2>; 404 }; 405 }; 406 407 smsm { 408 compatible = "qcom,smsm"; 409 410 #address-cells = <1>; 411 #size-cells = <0>; 412 413 mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>; 414 415 apps_smsm: apps@0 { 416 reg = <0>; 417 418 #qcom,smem-state-cells = <1>; 419 }; 420 421 hexagon_smsm: hexagon@1 { 422 reg = <1>; 423 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 424 425 interrupt-controller; 426 #interrupt-cells = <2>; 427 }; 428 429 wcnss_smsm: wcnss@6 { 430 reg = <6>; 431 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 432 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 }; 436 }; 437 438 soc: soc@0 { 439 #address-cells = <1>; 440 #size-cells = <1>; 441 ranges = <0 0 0 0xffffffff>; 442 compatible = "simple-bus"; 443 444 rng@22000 { 445 compatible = "qcom,prng"; 446 reg = <0x00022000 0x200>; 447 clocks = <&gcc GCC_PRNG_AHB_CLK>; 448 clock-names = "core"; 449 }; 450 451 restart@4ab000 { 452 compatible = "qcom,pshold"; 453 reg = <0x004ab000 0x4>; 454 }; 455 456 qfprom: qfprom@5c000 { 457 compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 458 reg = <0x0005c000 0x1000>; 459 #address-cells = <1>; 460 #size-cells = <1>; 461 462 tsens_base1: base1@d0 { 463 reg = <0xd0 0x1>; 464 bits = <0 7>; 465 }; 466 467 tsens_s0_p1: s0-p1@d0 { 468 reg = <0xd0 0x2>; 469 bits = <7 5>; 470 }; 471 472 tsens_s0_p2: s0-p2@d1 { 473 reg = <0xd1 0x2>; 474 bits = <4 5>; 475 }; 476 477 tsens_s1_p1: s1-p1@d2 { 478 reg = <0xd2 0x1>; 479 bits = <1 5>; 480 }; 481 tsens_s1_p2: s1-p2@d2 { 482 reg = <0xd2 0x2>; 483 bits = <6 5>; 484 }; 485 tsens_s2_p1: s2-p1@d3 { 486 reg = <0xd3 0x1>; 487 bits = <3 5>; 488 }; 489 490 tsens_s2_p2: s2-p2@d4 { 491 reg = <0xd4 0x1>; 492 bits = <0 5>; 493 }; 494 495 // no tsens with hw_id 3 496 497 tsens_s4_p1: s4-p1@d4 { 498 reg = <0xd4 0x2>; 499 bits = <5 5>; 500 }; 501 502 tsens_s4_p2: s4-p2@d5 { 503 reg = <0xd5 0x1>; 504 bits = <2 5>; 505 }; 506 507 tsens_s5_p1: s5-p1@d5 { 508 reg = <0xd5 0x2>; 509 bits = <7 5>; 510 }; 511 512 tsens_s5_p2: s5-p2@d6 { 513 reg = <0xd6 0x2>; 514 bits = <4 5>; 515 }; 516 517 tsens_base2: base2@d7 { 518 reg = <0xd7 0x1>; 519 bits = <1 7>; 520 }; 521 522 tsens_mode: mode@ef { 523 reg = <0xef 0x1>; 524 bits = <5 3>; 525 }; 526 }; 527 528 rpm_msg_ram: sram@60000 { 529 compatible = "qcom,rpm-msg-ram"; 530 reg = <0x00060000 0x8000>; 531 }; 532 533 sram@290000 { 534 compatible = "qcom,msm8916-rpm-stats"; 535 reg = <0x00290000 0x10000>; 536 }; 537 538 bimc: interconnect@400000 { 539 compatible = "qcom,msm8916-bimc"; 540 reg = <0x00400000 0x62000>; 541 #interconnect-cells = <1>; 542 }; 543 544 tsens: thermal-sensor@4a9000 { 545 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 546 reg = <0x004a9000 0x1000>, /* TM */ 547 <0x004a8000 0x1000>; /* SROT */ 548 549 // no hw_id 3 550 nvmem-cells = <&tsens_mode>, 551 <&tsens_base1>, <&tsens_base2>, 552 <&tsens_s0_p1>, <&tsens_s0_p2>, 553 <&tsens_s1_p1>, <&tsens_s1_p2>, 554 <&tsens_s2_p1>, <&tsens_s2_p2>, 555 <&tsens_s4_p1>, <&tsens_s4_p2>, 556 <&tsens_s5_p1>, <&tsens_s5_p2>; 557 nvmem-cell-names = "mode", 558 "base1", "base2", 559 "s0_p1", "s0_p2", 560 "s1_p1", "s1_p2", 561 "s2_p1", "s2_p2", 562 "s4_p1", "s4_p2", 563 "s5_p1", "s5_p2"; 564 #qcom,sensors = <5>; 565 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 566 interrupt-names = "uplow"; 567 #thermal-sensor-cells = <1>; 568 }; 569 570 pcnoc: interconnect@500000 { 571 compatible = "qcom,msm8916-pcnoc"; 572 reg = <0x00500000 0x11000>; 573 #interconnect-cells = <1>; 574 }; 575 576 snoc: interconnect@580000 { 577 compatible = "qcom,msm8916-snoc"; 578 reg = <0x00580000 0x14000>; 579 #interconnect-cells = <1>; 580 }; 581 582 stm: stm@802000 { 583 compatible = "arm,coresight-stm", "arm,primecell"; 584 reg = <0x00802000 0x1000>, 585 <0x09280000 0x180000>; 586 reg-names = "stm-base", "stm-stimulus-base"; 587 588 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 589 clock-names = "apb_pclk", "atclk"; 590 591 status = "disabled"; 592 593 out-ports { 594 port { 595 stm_out: endpoint { 596 remote-endpoint = <&funnel0_in7>; 597 }; 598 }; 599 }; 600 }; 601 602 /* System CTIs */ 603 /* CTI 0 - TMC connections */ 604 cti0: cti@810000 { 605 compatible = "arm,coresight-cti", "arm,primecell"; 606 reg = <0x00810000 0x1000>; 607 608 clocks = <&rpmcc RPM_QDSS_CLK>; 609 clock-names = "apb_pclk"; 610 611 status = "disabled"; 612 }; 613 614 /* CTI 1 - TPIU connections */ 615 cti1: cti@811000 { 616 compatible = "arm,coresight-cti", "arm,primecell"; 617 reg = <0x00811000 0x1000>; 618 619 clocks = <&rpmcc RPM_QDSS_CLK>; 620 clock-names = "apb_pclk"; 621 622 status = "disabled"; 623 }; 624 625 /* CTIs 2-11 - no information - not instantiated */ 626 627 tpiu: tpiu@820000 { 628 compatible = "arm,coresight-tpiu", "arm,primecell"; 629 reg = <0x00820000 0x1000>; 630 631 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 632 clock-names = "apb_pclk", "atclk"; 633 634 status = "disabled"; 635 636 in-ports { 637 port { 638 tpiu_in: endpoint { 639 remote-endpoint = <&replicator_out1>; 640 }; 641 }; 642 }; 643 }; 644 645 funnel0: funnel@821000 { 646 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 647 reg = <0x00821000 0x1000>; 648 649 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 650 clock-names = "apb_pclk", "atclk"; 651 652 status = "disabled"; 653 654 in-ports { 655 #address-cells = <1>; 656 #size-cells = <0>; 657 658 /* 659 * Not described input ports: 660 * 0 - connected to Resource and Power Manger CPU ETM 661 * 1 - not-connected 662 * 2 - connected to Modem CPU ETM 663 * 3 - not-connected 664 * 5 - not-connected 665 * 6 - connected trought funnel to Wireless CPU ETM 666 * 7 - connected to STM component 667 */ 668 669 port@4 { 670 reg = <4>; 671 funnel0_in4: endpoint { 672 remote-endpoint = <&funnel1_out>; 673 }; 674 }; 675 676 port@7 { 677 reg = <7>; 678 funnel0_in7: endpoint { 679 remote-endpoint = <&stm_out>; 680 }; 681 }; 682 }; 683 684 out-ports { 685 port { 686 funnel0_out: endpoint { 687 remote-endpoint = <&etf_in>; 688 }; 689 }; 690 }; 691 }; 692 693 replicator: replicator@824000 { 694 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 695 reg = <0x00824000 0x1000>; 696 697 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 698 clock-names = "apb_pclk", "atclk"; 699 700 status = "disabled"; 701 702 out-ports { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 706 port@0 { 707 reg = <0>; 708 replicator_out0: endpoint { 709 remote-endpoint = <&etr_in>; 710 }; 711 }; 712 port@1 { 713 reg = <1>; 714 replicator_out1: endpoint { 715 remote-endpoint = <&tpiu_in>; 716 }; 717 }; 718 }; 719 720 in-ports { 721 port { 722 replicator_in: endpoint { 723 remote-endpoint = <&etf_out>; 724 }; 725 }; 726 }; 727 }; 728 729 etf: etf@825000 { 730 compatible = "arm,coresight-tmc", "arm,primecell"; 731 reg = <0x00825000 0x1000>; 732 733 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 734 clock-names = "apb_pclk", "atclk"; 735 736 status = "disabled"; 737 738 in-ports { 739 port { 740 etf_in: endpoint { 741 remote-endpoint = <&funnel0_out>; 742 }; 743 }; 744 }; 745 746 out-ports { 747 port { 748 etf_out: endpoint { 749 remote-endpoint = <&replicator_in>; 750 }; 751 }; 752 }; 753 }; 754 755 etr: etr@826000 { 756 compatible = "arm,coresight-tmc", "arm,primecell"; 757 reg = <0x00826000 0x1000>; 758 759 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 760 clock-names = "apb_pclk", "atclk"; 761 762 status = "disabled"; 763 764 in-ports { 765 port { 766 etr_in: endpoint { 767 remote-endpoint = <&replicator_out0>; 768 }; 769 }; 770 }; 771 }; 772 773 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ 774 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 775 reg = <0x00841000 0x1000>; 776 777 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 778 clock-names = "apb_pclk", "atclk"; 779 780 status = "disabled"; 781 782 in-ports { 783 #address-cells = <1>; 784 #size-cells = <0>; 785 786 port@0 { 787 reg = <0>; 788 funnel1_in0: endpoint { 789 remote-endpoint = <&etm0_out>; 790 }; 791 }; 792 port@1 { 793 reg = <1>; 794 funnel1_in1: endpoint { 795 remote-endpoint = <&etm1_out>; 796 }; 797 }; 798 port@2 { 799 reg = <2>; 800 funnel1_in2: endpoint { 801 remote-endpoint = <&etm2_out>; 802 }; 803 }; 804 port@3 { 805 reg = <3>; 806 funnel1_in3: endpoint { 807 remote-endpoint = <&etm3_out>; 808 }; 809 }; 810 }; 811 812 out-ports { 813 port { 814 funnel1_out: endpoint { 815 remote-endpoint = <&funnel0_in4>; 816 }; 817 }; 818 }; 819 }; 820 821 debug0: debug@850000 { 822 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 823 reg = <0x00850000 0x1000>; 824 clocks = <&rpmcc RPM_QDSS_CLK>; 825 clock-names = "apb_pclk"; 826 cpu = <&CPU0>; 827 status = "disabled"; 828 }; 829 830 debug1: debug@852000 { 831 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 832 reg = <0x00852000 0x1000>; 833 clocks = <&rpmcc RPM_QDSS_CLK>; 834 clock-names = "apb_pclk"; 835 cpu = <&CPU1>; 836 status = "disabled"; 837 }; 838 839 debug2: debug@854000 { 840 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 841 reg = <0x00854000 0x1000>; 842 clocks = <&rpmcc RPM_QDSS_CLK>; 843 clock-names = "apb_pclk"; 844 cpu = <&CPU2>; 845 status = "disabled"; 846 }; 847 848 debug3: debug@856000 { 849 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 850 reg = <0x00856000 0x1000>; 851 clocks = <&rpmcc RPM_QDSS_CLK>; 852 clock-names = "apb_pclk"; 853 cpu = <&CPU3>; 854 status = "disabled"; 855 }; 856 857 /* Core CTIs; CTIs 12-15 */ 858 /* CTI - CPU-0 */ 859 cti12: cti@858000 { 860 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 861 "arm,primecell"; 862 reg = <0x00858000 0x1000>; 863 864 clocks = <&rpmcc RPM_QDSS_CLK>; 865 clock-names = "apb_pclk"; 866 867 cpu = <&CPU0>; 868 arm,cs-dev-assoc = <&etm0>; 869 870 status = "disabled"; 871 }; 872 873 /* CTI - CPU-1 */ 874 cti13: cti@859000 { 875 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 876 "arm,primecell"; 877 reg = <0x00859000 0x1000>; 878 879 clocks = <&rpmcc RPM_QDSS_CLK>; 880 clock-names = "apb_pclk"; 881 882 cpu = <&CPU1>; 883 arm,cs-dev-assoc = <&etm1>; 884 885 status = "disabled"; 886 }; 887 888 /* CTI - CPU-2 */ 889 cti14: cti@85a000 { 890 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 891 "arm,primecell"; 892 reg = <0x0085a000 0x1000>; 893 894 clocks = <&rpmcc RPM_QDSS_CLK>; 895 clock-names = "apb_pclk"; 896 897 cpu = <&CPU2>; 898 arm,cs-dev-assoc = <&etm2>; 899 900 status = "disabled"; 901 }; 902 903 /* CTI - CPU-3 */ 904 cti15: cti@85b000 { 905 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 906 "arm,primecell"; 907 reg = <0x0085b000 0x1000>; 908 909 clocks = <&rpmcc RPM_QDSS_CLK>; 910 clock-names = "apb_pclk"; 911 912 cpu = <&CPU3>; 913 arm,cs-dev-assoc = <&etm3>; 914 915 status = "disabled"; 916 }; 917 918 etm0: etm@85c000 { 919 compatible = "arm,coresight-etm4x", "arm,primecell"; 920 reg = <0x0085c000 0x1000>; 921 922 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 923 clock-names = "apb_pclk", "atclk"; 924 arm,coresight-loses-context-with-cpu; 925 926 cpu = <&CPU0>; 927 928 status = "disabled"; 929 930 out-ports { 931 port { 932 etm0_out: endpoint { 933 remote-endpoint = <&funnel1_in0>; 934 }; 935 }; 936 }; 937 }; 938 939 etm1: etm@85d000 { 940 compatible = "arm,coresight-etm4x", "arm,primecell"; 941 reg = <0x0085d000 0x1000>; 942 943 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 944 clock-names = "apb_pclk", "atclk"; 945 arm,coresight-loses-context-with-cpu; 946 947 cpu = <&CPU1>; 948 949 status = "disabled"; 950 951 out-ports { 952 port { 953 etm1_out: endpoint { 954 remote-endpoint = <&funnel1_in1>; 955 }; 956 }; 957 }; 958 }; 959 960 etm2: etm@85e000 { 961 compatible = "arm,coresight-etm4x", "arm,primecell"; 962 reg = <0x0085e000 0x1000>; 963 964 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 965 clock-names = "apb_pclk", "atclk"; 966 arm,coresight-loses-context-with-cpu; 967 968 cpu = <&CPU2>; 969 970 status = "disabled"; 971 972 out-ports { 973 port { 974 etm2_out: endpoint { 975 remote-endpoint = <&funnel1_in2>; 976 }; 977 }; 978 }; 979 }; 980 981 etm3: etm@85f000 { 982 compatible = "arm,coresight-etm4x", "arm,primecell"; 983 reg = <0x0085f000 0x1000>; 984 985 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 986 clock-names = "apb_pclk", "atclk"; 987 arm,coresight-loses-context-with-cpu; 988 989 cpu = <&CPU3>; 990 991 status = "disabled"; 992 993 out-ports { 994 port { 995 etm3_out: endpoint { 996 remote-endpoint = <&funnel1_in3>; 997 }; 998 }; 999 }; 1000 }; 1001 1002 tlmm: pinctrl@1000000 { 1003 compatible = "qcom,msm8916-pinctrl"; 1004 reg = <0x01000000 0x300000>; 1005 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1006 gpio-controller; 1007 gpio-ranges = <&tlmm 0 0 122>; 1008 #gpio-cells = <2>; 1009 interrupt-controller; 1010 #interrupt-cells = <2>; 1011 1012 blsp_i2c1_default: blsp-i2c1-default-state { 1013 pins = "gpio2", "gpio3"; 1014 function = "blsp_i2c1"; 1015 drive-strength = <2>; 1016 bias-disable; 1017 }; 1018 1019 blsp_i2c1_sleep: blsp-i2c1-sleep-state { 1020 pins = "gpio2", "gpio3"; 1021 function = "gpio"; 1022 drive-strength = <2>; 1023 bias-disable; 1024 }; 1025 1026 blsp_i2c2_default: blsp-i2c2-default-state { 1027 pins = "gpio6", "gpio7"; 1028 function = "blsp_i2c2"; 1029 drive-strength = <2>; 1030 bias-disable; 1031 }; 1032 1033 blsp_i2c2_sleep: blsp-i2c2-sleep-state { 1034 pins = "gpio6", "gpio7"; 1035 function = "gpio"; 1036 drive-strength = <2>; 1037 bias-disable; 1038 }; 1039 1040 blsp_i2c3_default: blsp-i2c3-default-state { 1041 pins = "gpio10", "gpio11"; 1042 function = "blsp_i2c3"; 1043 drive-strength = <2>; 1044 bias-disable; 1045 }; 1046 1047 blsp_i2c3_sleep: blsp-i2c3-sleep-state { 1048 pins = "gpio10", "gpio11"; 1049 function = "gpio"; 1050 drive-strength = <2>; 1051 bias-disable; 1052 }; 1053 1054 blsp_i2c4_default: blsp-i2c4-default-state { 1055 pins = "gpio14", "gpio15"; 1056 function = "blsp_i2c4"; 1057 drive-strength = <2>; 1058 bias-disable; 1059 }; 1060 1061 blsp_i2c4_sleep: blsp-i2c4-sleep-state { 1062 pins = "gpio14", "gpio15"; 1063 function = "gpio"; 1064 drive-strength = <2>; 1065 bias-disable; 1066 }; 1067 1068 blsp_i2c5_default: blsp-i2c5-default-state { 1069 pins = "gpio18", "gpio19"; 1070 function = "blsp_i2c5"; 1071 drive-strength = <2>; 1072 bias-disable; 1073 }; 1074 1075 blsp_i2c5_sleep: blsp-i2c5-sleep-state { 1076 pins = "gpio18", "gpio19"; 1077 function = "gpio"; 1078 drive-strength = <2>; 1079 bias-disable; 1080 }; 1081 1082 blsp_i2c6_default: blsp-i2c6-default-state { 1083 pins = "gpio22", "gpio23"; 1084 function = "blsp_i2c6"; 1085 drive-strength = <2>; 1086 bias-disable; 1087 }; 1088 1089 blsp_i2c6_sleep: blsp-i2c6-sleep-state { 1090 pins = "gpio22", "gpio23"; 1091 function = "gpio"; 1092 drive-strength = <2>; 1093 bias-disable; 1094 }; 1095 1096 blsp_spi1_default: blsp-spi1-default-state { 1097 spi-pins { 1098 pins = "gpio0", "gpio1", "gpio3"; 1099 function = "blsp_spi1"; 1100 drive-strength = <12>; 1101 bias-disable; 1102 }; 1103 cs-pins { 1104 pins = "gpio2"; 1105 function = "gpio"; 1106 drive-strength = <16>; 1107 bias-disable; 1108 output-high; 1109 }; 1110 }; 1111 1112 blsp_spi1_sleep: blsp-spi1-sleep-state { 1113 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1114 function = "gpio"; 1115 drive-strength = <2>; 1116 bias-pull-down; 1117 }; 1118 1119 blsp_spi2_default: blsp-spi2-default-state { 1120 spi-pins { 1121 pins = "gpio4", "gpio5", "gpio7"; 1122 function = "blsp_spi2"; 1123 drive-strength = <12>; 1124 bias-disable; 1125 }; 1126 cs-pins { 1127 pins = "gpio6"; 1128 function = "gpio"; 1129 drive-strength = <16>; 1130 bias-disable; 1131 output-high; 1132 }; 1133 }; 1134 1135 blsp_spi2_sleep: blsp-spi2-sleep-state { 1136 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 1137 function = "gpio"; 1138 drive-strength = <2>; 1139 bias-pull-down; 1140 }; 1141 1142 blsp_spi3_default: blsp-spi3-default-state { 1143 spi-pins { 1144 pins = "gpio8", "gpio9", "gpio11"; 1145 function = "blsp_spi3"; 1146 drive-strength = <12>; 1147 bias-disable; 1148 }; 1149 cs-pins { 1150 pins = "gpio10"; 1151 function = "gpio"; 1152 drive-strength = <16>; 1153 bias-disable; 1154 output-high; 1155 }; 1156 }; 1157 1158 blsp_spi3_sleep: blsp-spi3-sleep-state { 1159 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 1160 function = "gpio"; 1161 drive-strength = <2>; 1162 bias-pull-down; 1163 }; 1164 1165 blsp_spi4_default: blsp-spi4-default-state { 1166 spi-pins { 1167 pins = "gpio12", "gpio13", "gpio15"; 1168 function = "blsp_spi4"; 1169 drive-strength = <12>; 1170 bias-disable; 1171 }; 1172 cs-pins { 1173 pins = "gpio14"; 1174 function = "gpio"; 1175 drive-strength = <16>; 1176 bias-disable; 1177 output-high; 1178 }; 1179 }; 1180 1181 blsp_spi4_sleep: blsp-spi4-sleep-state { 1182 pins = "gpio12", "gpio13", "gpio14", "gpio15"; 1183 function = "gpio"; 1184 drive-strength = <2>; 1185 bias-pull-down; 1186 }; 1187 1188 blsp_spi5_default: blsp-spi5-default-state { 1189 spi-pins { 1190 pins = "gpio16", "gpio17", "gpio19"; 1191 function = "blsp_spi5"; 1192 drive-strength = <12>; 1193 bias-disable; 1194 }; 1195 cs-pins { 1196 pins = "gpio18"; 1197 function = "gpio"; 1198 drive-strength = <16>; 1199 bias-disable; 1200 output-high; 1201 }; 1202 }; 1203 1204 blsp_spi5_sleep: blsp-spi5-sleep-state { 1205 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 1206 function = "gpio"; 1207 drive-strength = <2>; 1208 bias-pull-down; 1209 }; 1210 1211 blsp_spi6_default: blsp-spi6-default-state { 1212 spi-pins { 1213 pins = "gpio20", "gpio21", "gpio23"; 1214 function = "blsp_spi6"; 1215 drive-strength = <12>; 1216 bias-disable; 1217 }; 1218 cs-pins { 1219 pins = "gpio22"; 1220 function = "gpio"; 1221 drive-strength = <16>; 1222 bias-disable; 1223 output-high; 1224 }; 1225 }; 1226 1227 blsp_spi6_sleep: blsp-spi6-sleep-state { 1228 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 1229 function = "gpio"; 1230 drive-strength = <2>; 1231 bias-pull-down; 1232 }; 1233 1234 blsp_uart1_default: blsp-uart1-default-state { 1235 /* TX, RX, CTS_N, RTS_N */ 1236 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1237 function = "blsp_uart1"; 1238 drive-strength = <16>; 1239 bias-disable; 1240 }; 1241 1242 blsp_uart1_sleep: blsp-uart1-sleep-state { 1243 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1244 function = "gpio"; 1245 drive-strength = <2>; 1246 bias-pull-down; 1247 }; 1248 1249 blsp_uart2_default: blsp-uart2-default-state { 1250 pins = "gpio4", "gpio5"; 1251 function = "blsp_uart2"; 1252 drive-strength = <16>; 1253 bias-disable; 1254 }; 1255 1256 blsp_uart2_sleep: blsp-uart2-sleep-state { 1257 pins = "gpio4", "gpio5"; 1258 function = "gpio"; 1259 drive-strength = <2>; 1260 bias-pull-down; 1261 }; 1262 1263 camera_front_default: camera-front-default-state { 1264 pwdn-pins { 1265 pins = "gpio33"; 1266 function = "gpio"; 1267 drive-strength = <16>; 1268 bias-disable; 1269 }; 1270 rst-pins { 1271 pins = "gpio28"; 1272 function = "gpio"; 1273 drive-strength = <16>; 1274 bias-disable; 1275 }; 1276 mclk1-pins { 1277 pins = "gpio27"; 1278 function = "cam_mclk1"; 1279 drive-strength = <16>; 1280 bias-disable; 1281 }; 1282 }; 1283 1284 camera_rear_default: camera-rear-default-state { 1285 pwdn-pins { 1286 pins = "gpio34"; 1287 function = "gpio"; 1288 drive-strength = <16>; 1289 bias-disable; 1290 }; 1291 rst-pins { 1292 pins = "gpio35"; 1293 function = "gpio"; 1294 drive-strength = <16>; 1295 bias-disable; 1296 }; 1297 mclk0-pins { 1298 pins = "gpio26"; 1299 function = "cam_mclk0"; 1300 drive-strength = <16>; 1301 bias-disable; 1302 }; 1303 }; 1304 1305 cci0_default: cci0-default-state { 1306 pins = "gpio29", "gpio30"; 1307 function = "cci_i2c"; 1308 drive-strength = <16>; 1309 bias-disable; 1310 }; 1311 1312 cdc_dmic_default: cdc-dmic-default-state { 1313 clk-pins { 1314 pins = "gpio0"; 1315 function = "dmic0_clk"; 1316 drive-strength = <8>; 1317 }; 1318 data-pins { 1319 pins = "gpio1"; 1320 function = "dmic0_data"; 1321 drive-strength = <8>; 1322 }; 1323 }; 1324 1325 cdc_dmic_sleep: cdc-dmic-sleep-state { 1326 clk-pins { 1327 pins = "gpio0"; 1328 function = "dmic0_clk"; 1329 drive-strength = <2>; 1330 bias-disable; 1331 }; 1332 data-pins { 1333 pins = "gpio1"; 1334 function = "dmic0_data"; 1335 drive-strength = <2>; 1336 bias-disable; 1337 }; 1338 }; 1339 1340 cdc_pdm_default: cdc-pdm-default-state { 1341 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1342 "gpio67", "gpio68"; 1343 function = "cdc_pdm0"; 1344 drive-strength = <8>; 1345 bias-disable; 1346 }; 1347 1348 cdc_pdm_sleep: cdc-pdm-sleep-state { 1349 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1350 "gpio67", "gpio68"; 1351 function = "cdc_pdm0"; 1352 drive-strength = <2>; 1353 bias-pull-down; 1354 }; 1355 1356 pri_mi2s_default: mi2s-pri-default-state { 1357 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1358 function = "pri_mi2s"; 1359 drive-strength = <8>; 1360 bias-disable; 1361 }; 1362 1363 pri_mi2s_sleep: mi2s-pri-sleep-state { 1364 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1365 function = "pri_mi2s"; 1366 drive-strength = <2>; 1367 bias-disable; 1368 }; 1369 1370 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { 1371 pins = "gpio116"; 1372 function = "pri_mi2s"; 1373 drive-strength = <8>; 1374 bias-disable; 1375 }; 1376 1377 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { 1378 pins = "gpio116"; 1379 function = "pri_mi2s"; 1380 drive-strength = <2>; 1381 bias-disable; 1382 }; 1383 1384 pri_mi2s_ws_default: mi2s-pri-ws-default-state { 1385 pins = "gpio110"; 1386 function = "pri_mi2s_ws"; 1387 drive-strength = <8>; 1388 bias-disable; 1389 }; 1390 1391 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { 1392 pins = "gpio110"; 1393 function = "pri_mi2s_ws"; 1394 drive-strength = <2>; 1395 bias-disable; 1396 }; 1397 1398 sec_mi2s_default: mi2s-sec-default-state { 1399 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1400 function = "sec_mi2s"; 1401 drive-strength = <8>; 1402 bias-disable; 1403 }; 1404 1405 sec_mi2s_sleep: mi2s-sec-sleep-state { 1406 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1407 function = "sec_mi2s"; 1408 drive-strength = <2>; 1409 bias-disable; 1410 }; 1411 1412 sdc1_default: sdc1-default-state { 1413 clk-pins { 1414 pins = "sdc1_clk"; 1415 bias-disable; 1416 drive-strength = <16>; 1417 }; 1418 cmd-pins { 1419 pins = "sdc1_cmd"; 1420 bias-pull-up; 1421 drive-strength = <10>; 1422 }; 1423 data-pins { 1424 pins = "sdc1_data"; 1425 bias-pull-up; 1426 drive-strength = <10>; 1427 }; 1428 }; 1429 1430 sdc1_sleep: sdc1-sleep-state { 1431 clk-pins { 1432 pins = "sdc1_clk"; 1433 bias-disable; 1434 drive-strength = <2>; 1435 }; 1436 cmd-pins { 1437 pins = "sdc1_cmd"; 1438 bias-pull-up; 1439 drive-strength = <2>; 1440 }; 1441 data-pins { 1442 pins = "sdc1_data"; 1443 bias-pull-up; 1444 drive-strength = <2>; 1445 }; 1446 }; 1447 1448 sdc2_default: sdc2-default-state { 1449 clk-pins { 1450 pins = "sdc2_clk"; 1451 bias-disable; 1452 drive-strength = <16>; 1453 }; 1454 cmd-pins { 1455 pins = "sdc2_cmd"; 1456 bias-pull-up; 1457 drive-strength = <10>; 1458 }; 1459 data-pins { 1460 pins = "sdc2_data"; 1461 bias-pull-up; 1462 drive-strength = <10>; 1463 }; 1464 }; 1465 1466 sdc2_sleep: sdc2-sleep-state { 1467 clk-pins { 1468 pins = "sdc2_clk"; 1469 bias-disable; 1470 drive-strength = <2>; 1471 }; 1472 cmd-pins { 1473 pins = "sdc2_cmd"; 1474 bias-pull-up; 1475 drive-strength = <2>; 1476 }; 1477 data-pins { 1478 pins = "sdc2_data"; 1479 bias-pull-up; 1480 drive-strength = <2>; 1481 }; 1482 }; 1483 1484 wcss_wlan_default: wcss-wlan-default-state { 1485 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; 1486 function = "wcss_wlan"; 1487 drive-strength = <6>; 1488 bias-pull-up; 1489 }; 1490 }; 1491 1492 gcc: clock-controller@1800000 { 1493 compatible = "qcom,gcc-msm8916"; 1494 #clock-cells = <1>; 1495 #reset-cells = <1>; 1496 #power-domain-cells = <1>; 1497 reg = <0x01800000 0x80000>; 1498 clocks = <&xo_board>, 1499 <&sleep_clk>, 1500 <&mdss_dsi0_phy 1>, 1501 <&mdss_dsi0_phy 0>, 1502 <0>, 1503 <0>, 1504 <0>; 1505 clock-names = "xo", 1506 "sleep_clk", 1507 "dsi0pll", 1508 "dsi0pllbyte", 1509 "ext_mclk", 1510 "ext_pri_i2s", 1511 "ext_sec_i2s"; 1512 }; 1513 1514 tcsr_mutex: hwlock@1905000 { 1515 compatible = "qcom,tcsr-mutex"; 1516 reg = <0x01905000 0x20000>; 1517 #hwlock-cells = <1>; 1518 }; 1519 1520 tcsr: syscon@1937000 { 1521 compatible = "qcom,tcsr-msm8916", "syscon"; 1522 reg = <0x01937000 0x30000>; 1523 }; 1524 1525 mdss: display-subsystem@1a00000 { 1526 status = "disabled"; 1527 compatible = "qcom,mdss"; 1528 reg = <0x01a00000 0x1000>, 1529 <0x01ac8000 0x3000>; 1530 reg-names = "mdss_phys", "vbif_phys"; 1531 1532 power-domains = <&gcc MDSS_GDSC>; 1533 1534 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1535 <&gcc GCC_MDSS_AXI_CLK>, 1536 <&gcc GCC_MDSS_VSYNC_CLK>; 1537 clock-names = "iface", 1538 "bus", 1539 "vsync"; 1540 1541 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1542 1543 interrupt-controller; 1544 #interrupt-cells = <1>; 1545 1546 #address-cells = <1>; 1547 #size-cells = <1>; 1548 ranges; 1549 1550 mdss_mdp: display-controller@1a01000 { 1551 compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; 1552 reg = <0x01a01000 0x89000>; 1553 reg-names = "mdp_phys"; 1554 1555 interrupt-parent = <&mdss>; 1556 interrupts = <0>; 1557 1558 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1559 <&gcc GCC_MDSS_AXI_CLK>, 1560 <&gcc GCC_MDSS_MDP_CLK>, 1561 <&gcc GCC_MDSS_VSYNC_CLK>; 1562 clock-names = "iface", 1563 "bus", 1564 "core", 1565 "vsync"; 1566 1567 iommus = <&apps_iommu 4>; 1568 1569 ports { 1570 #address-cells = <1>; 1571 #size-cells = <0>; 1572 1573 port@0 { 1574 reg = <0>; 1575 mdss_mdp_intf1_out: endpoint { 1576 remote-endpoint = <&mdss_dsi0_in>; 1577 }; 1578 }; 1579 }; 1580 }; 1581 1582 mdss_dsi0: dsi@1a98000 { 1583 compatible = "qcom,msm8916-dsi-ctrl", 1584 "qcom,mdss-dsi-ctrl"; 1585 reg = <0x01a98000 0x25c>; 1586 reg-names = "dsi_ctrl"; 1587 1588 interrupt-parent = <&mdss>; 1589 interrupts = <4>; 1590 1591 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1592 <&gcc PCLK0_CLK_SRC>; 1593 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1594 <&mdss_dsi0_phy 1>; 1595 1596 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1597 <&gcc GCC_MDSS_AHB_CLK>, 1598 <&gcc GCC_MDSS_AXI_CLK>, 1599 <&gcc GCC_MDSS_BYTE0_CLK>, 1600 <&gcc GCC_MDSS_PCLK0_CLK>, 1601 <&gcc GCC_MDSS_ESC0_CLK>; 1602 clock-names = "mdp_core", 1603 "iface", 1604 "bus", 1605 "byte", 1606 "pixel", 1607 "core"; 1608 phys = <&mdss_dsi0_phy>; 1609 1610 #address-cells = <1>; 1611 #size-cells = <0>; 1612 1613 ports { 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 1617 port@0 { 1618 reg = <0>; 1619 mdss_dsi0_in: endpoint { 1620 remote-endpoint = <&mdss_mdp_intf1_out>; 1621 }; 1622 }; 1623 1624 port@1 { 1625 reg = <1>; 1626 mdss_dsi0_out: endpoint { 1627 }; 1628 }; 1629 }; 1630 }; 1631 1632 mdss_dsi0_phy: phy@1a98300 { 1633 compatible = "qcom,dsi-phy-28nm-lp"; 1634 reg = <0x01a98300 0xd4>, 1635 <0x01a98500 0x280>, 1636 <0x01a98780 0x30>; 1637 reg-names = "dsi_pll", 1638 "dsi_phy", 1639 "dsi_phy_regulator"; 1640 1641 #clock-cells = <1>; 1642 #phy-cells = <0>; 1643 1644 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1645 <&xo_board>; 1646 clock-names = "iface", "ref"; 1647 }; 1648 }; 1649 1650 camss: camss@1b0ac00 { 1651 compatible = "qcom,msm8916-camss"; 1652 reg = <0x01b0ac00 0x200>, 1653 <0x01b00030 0x4>, 1654 <0x01b0b000 0x200>, 1655 <0x01b00038 0x4>, 1656 <0x01b08000 0x100>, 1657 <0x01b08400 0x100>, 1658 <0x01b0a000 0x500>, 1659 <0x01b00020 0x10>, 1660 <0x01b10000 0x1000>; 1661 reg-names = "csiphy0", 1662 "csiphy0_clk_mux", 1663 "csiphy1", 1664 "csiphy1_clk_mux", 1665 "csid0", 1666 "csid1", 1667 "ispif", 1668 "csi_clk_mux", 1669 "vfe0"; 1670 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1671 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1672 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1673 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1674 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1675 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1676 interrupt-names = "csiphy0", 1677 "csiphy1", 1678 "csid0", 1679 "csid1", 1680 "ispif", 1681 "vfe0"; 1682 power-domains = <&gcc VFE_GDSC>; 1683 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1684 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1685 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1686 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1687 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1688 <&gcc GCC_CAMSS_CSI0_CLK>, 1689 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1690 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1691 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1692 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1693 <&gcc GCC_CAMSS_CSI1_CLK>, 1694 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1695 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1696 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1697 <&gcc GCC_CAMSS_AHB_CLK>, 1698 <&gcc GCC_CAMSS_VFE0_CLK>, 1699 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1700 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1701 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1702 clock-names = "top_ahb", 1703 "ispif_ahb", 1704 "csiphy0_timer", 1705 "csiphy1_timer", 1706 "csi0_ahb", 1707 "csi0", 1708 "csi0_phy", 1709 "csi0_pix", 1710 "csi0_rdi", 1711 "csi1_ahb", 1712 "csi1", 1713 "csi1_phy", 1714 "csi1_pix", 1715 "csi1_rdi", 1716 "ahb", 1717 "vfe0", 1718 "csi_vfe0", 1719 "vfe_ahb", 1720 "vfe_axi"; 1721 iommus = <&apps_iommu 3>; 1722 status = "disabled"; 1723 ports { 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 1727 port@0 { 1728 reg = <0>; 1729 }; 1730 1731 port@1 { 1732 reg = <1>; 1733 }; 1734 }; 1735 }; 1736 1737 cci: cci@1b0c000 { 1738 compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; 1739 #address-cells = <1>; 1740 #size-cells = <0>; 1741 reg = <0x01b0c000 0x1000>; 1742 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1743 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1744 <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1745 <&gcc GCC_CAMSS_CCI_CLK>, 1746 <&gcc GCC_CAMSS_AHB_CLK>; 1747 clock-names = "camss_top_ahb", "cci_ahb", 1748 "cci", "camss_ahb"; 1749 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1750 <&gcc GCC_CAMSS_CCI_CLK>; 1751 assigned-clock-rates = <80000000>, <19200000>; 1752 pinctrl-names = "default"; 1753 pinctrl-0 = <&cci0_default>; 1754 status = "disabled"; 1755 1756 cci_i2c0: i2c-bus@0 { 1757 reg = <0>; 1758 clock-frequency = <400000>; 1759 #address-cells = <1>; 1760 #size-cells = <0>; 1761 }; 1762 }; 1763 1764 gpu: gpu@1c00000 { 1765 compatible = "qcom,adreno-306.0", "qcom,adreno"; 1766 reg = <0x01c00000 0x20000>; 1767 reg-names = "kgsl_3d0_reg_memory"; 1768 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1769 interrupt-names = "kgsl_3d0_irq"; 1770 clock-names = 1771 "core", 1772 "iface", 1773 "mem", 1774 "mem_iface", 1775 "alt_mem_iface", 1776 "gfx3d"; 1777 clocks = 1778 <&gcc GCC_OXILI_GFX3D_CLK>, 1779 <&gcc GCC_OXILI_AHB_CLK>, 1780 <&gcc GCC_OXILI_GMEM_CLK>, 1781 <&gcc GCC_BIMC_GFX_CLK>, 1782 <&gcc GCC_BIMC_GPU_CLK>, 1783 <&gcc GFX3D_CLK_SRC>; 1784 power-domains = <&gcc OXILI_GDSC>; 1785 operating-points-v2 = <&gpu_opp_table>; 1786 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1787 #cooling-cells = <2>; 1788 1789 status = "disabled"; 1790 1791 gpu_opp_table: opp-table { 1792 compatible = "operating-points-v2"; 1793 1794 opp-400000000 { 1795 opp-hz = /bits/ 64 <400000000>; 1796 }; 1797 opp-19200000 { 1798 opp-hz = /bits/ 64 <19200000>; 1799 }; 1800 }; 1801 }; 1802 1803 venus: video-codec@1d00000 { 1804 compatible = "qcom,msm8916-venus"; 1805 reg = <0x01d00000 0xff000>; 1806 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1807 power-domains = <&gcc VENUS_GDSC>; 1808 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1809 <&gcc GCC_VENUS0_AHB_CLK>, 1810 <&gcc GCC_VENUS0_AXI_CLK>; 1811 clock-names = "core", "iface", "bus"; 1812 iommus = <&apps_iommu 5>; 1813 memory-region = <&venus_mem>; 1814 status = "disabled"; 1815 1816 video-decoder { 1817 compatible = "venus-decoder"; 1818 }; 1819 1820 video-encoder { 1821 compatible = "venus-encoder"; 1822 }; 1823 }; 1824 1825 apps_iommu: iommu@1ef0000 { 1826 #address-cells = <1>; 1827 #size-cells = <1>; 1828 #iommu-cells = <1>; 1829 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1830 ranges = <0 0x01e20000 0x20000>; 1831 reg = <0x01ef0000 0x3000>; 1832 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1833 <&gcc GCC_APSS_TCU_CLK>; 1834 clock-names = "iface", "bus"; 1835 qcom,iommu-secure-id = <17>; 1836 1837 /* VFE */ 1838 iommu-ctx@3000 { 1839 compatible = "qcom,msm-iommu-v1-sec"; 1840 reg = <0x3000 0x1000>; 1841 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1842 }; 1843 1844 /* MDP_0 */ 1845 iommu-ctx@4000 { 1846 compatible = "qcom,msm-iommu-v1-ns"; 1847 reg = <0x4000 0x1000>; 1848 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1849 }; 1850 1851 /* VENUS_NS */ 1852 iommu-ctx@5000 { 1853 compatible = "qcom,msm-iommu-v1-sec"; 1854 reg = <0x5000 0x1000>; 1855 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1856 }; 1857 }; 1858 1859 gpu_iommu: iommu@1f08000 { 1860 #address-cells = <1>; 1861 #size-cells = <1>; 1862 #iommu-cells = <1>; 1863 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1864 ranges = <0 0x01f08000 0x10000>; 1865 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1866 <&gcc GCC_GFX_TCU_CLK>; 1867 clock-names = "iface", "bus"; 1868 qcom,iommu-secure-id = <18>; 1869 1870 /* GFX3D_USER */ 1871 iommu-ctx@1000 { 1872 compatible = "qcom,msm-iommu-v1-ns"; 1873 reg = <0x1000 0x1000>; 1874 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1875 }; 1876 1877 /* GFX3D_PRIV */ 1878 iommu-ctx@2000 { 1879 compatible = "qcom,msm-iommu-v1-ns"; 1880 reg = <0x2000 0x1000>; 1881 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1882 }; 1883 }; 1884 1885 spmi_bus: spmi@200f000 { 1886 compatible = "qcom,spmi-pmic-arb"; 1887 reg = <0x0200f000 0x001000>, 1888 <0x02400000 0x400000>, 1889 <0x02c00000 0x400000>, 1890 <0x03800000 0x200000>, 1891 <0x0200a000 0x002100>; 1892 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1893 interrupt-names = "periph_irq"; 1894 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1895 qcom,ee = <0>; 1896 qcom,channel = <0>; 1897 #address-cells = <2>; 1898 #size-cells = <0>; 1899 interrupt-controller; 1900 #interrupt-cells = <4>; 1901 }; 1902 1903 bam_dmux_dma: dma-controller@4044000 { 1904 compatible = "qcom,bam-v1.7.0"; 1905 reg = <0x04044000 0x19000>; 1906 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1907 #dma-cells = <1>; 1908 qcom,ee = <0>; 1909 1910 num-channels = <6>; 1911 qcom,num-ees = <1>; 1912 qcom,powered-remotely; 1913 1914 status = "disabled"; 1915 }; 1916 1917 mpss: remoteproc@4080000 { 1918 compatible = "qcom,msm8916-mss-pil"; 1919 reg = <0x04080000 0x100>, 1920 <0x04020000 0x040>; 1921 1922 reg-names = "qdsp6", "rmb"; 1923 1924 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1925 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1926 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1927 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1928 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1929 interrupt-names = "wdog", "fatal", "ready", 1930 "handover", "stop-ack"; 1931 1932 power-domains = <&rpmpd MSM8916_VDDCX>, 1933 <&rpmpd MSM8916_VDDMX>; 1934 power-domain-names = "cx", "mx"; 1935 1936 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1937 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1938 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1939 <&xo_board>; 1940 clock-names = "iface", "bus", "mem", "xo"; 1941 1942 qcom,smem-states = <&hexagon_smp2p_out 0>; 1943 qcom,smem-state-names = "stop"; 1944 1945 resets = <&scm 0>; 1946 reset-names = "mss_restart"; 1947 1948 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1949 1950 status = "disabled"; 1951 1952 mba { 1953 memory-region = <&mba_mem>; 1954 }; 1955 1956 mpss { 1957 memory-region = <&mpss_mem>; 1958 }; 1959 1960 bam_dmux: bam-dmux { 1961 compatible = "qcom,bam-dmux"; 1962 1963 interrupt-parent = <&hexagon_smsm>; 1964 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1965 interrupt-names = "pc", "pc-ack"; 1966 1967 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1968 qcom,smem-state-names = "pc", "pc-ack"; 1969 1970 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1971 dma-names = "tx", "rx"; 1972 1973 status = "disabled"; 1974 }; 1975 1976 smd-edge { 1977 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1978 1979 qcom,smd-edge = <0>; 1980 mboxes = <&apcs 12>; 1981 qcom,remote-pid = <1>; 1982 1983 label = "hexagon"; 1984 1985 apr: apr { 1986 compatible = "qcom,apr-v2"; 1987 qcom,smd-channels = "apr_audio_svc"; 1988 qcom,domain = <APR_DOMAIN_ADSP>; 1989 #address-cells = <1>; 1990 #size-cells = <0>; 1991 status = "disabled"; 1992 1993 q6core: service@3 { 1994 compatible = "qcom,q6core"; 1995 reg = <APR_SVC_ADSP_CORE>; 1996 }; 1997 1998 q6afe: service@4 { 1999 compatible = "qcom,q6afe"; 2000 reg = <APR_SVC_AFE>; 2001 2002 q6afedai: dais { 2003 compatible = "qcom,q6afe-dais"; 2004 #address-cells = <1>; 2005 #size-cells = <0>; 2006 #sound-dai-cells = <1>; 2007 }; 2008 }; 2009 2010 q6asm: service@7 { 2011 compatible = "qcom,q6asm"; 2012 reg = <APR_SVC_ASM>; 2013 2014 q6asmdai: dais { 2015 compatible = "qcom,q6asm-dais"; 2016 #address-cells = <1>; 2017 #size-cells = <0>; 2018 #sound-dai-cells = <1>; 2019 }; 2020 }; 2021 2022 q6adm: service@8 { 2023 compatible = "qcom,q6adm"; 2024 reg = <APR_SVC_ADM>; 2025 2026 q6routing: routing { 2027 compatible = "qcom,q6adm-routing"; 2028 #sound-dai-cells = <0>; 2029 }; 2030 }; 2031 }; 2032 2033 fastrpc { 2034 compatible = "qcom,fastrpc"; 2035 qcom,smd-channels = "fastrpcsmd-apps-dsp"; 2036 label = "adsp"; 2037 qcom,non-secure-domain; 2038 2039 #address-cells = <1>; 2040 #size-cells = <0>; 2041 2042 cb@1 { 2043 compatible = "qcom,fastrpc-compute-cb"; 2044 reg = <1>; 2045 }; 2046 }; 2047 }; 2048 }; 2049 2050 sound: sound@7702000 { 2051 status = "disabled"; 2052 compatible = "qcom,apq8016-sbc-sndcard"; 2053 reg = <0x07702000 0x4>, <0x07702004 0x4>; 2054 reg-names = "mic-iomux", "spkr-iomux"; 2055 }; 2056 2057 lpass: audio-controller@7708000 { 2058 status = "disabled"; 2059 compatible = "qcom,apq8016-lpass-cpu"; 2060 2061 /* 2062 * Note: Unlike the name would suggest, the SEC_I2S_CLK 2063 * is actually only used by Tertiary MI2S while 2064 * Primary/Secondary MI2S both use the PRI_I2S_CLK. 2065 */ 2066 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 2067 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 2068 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 2069 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 2070 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, 2071 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 2072 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; 2073 2074 clock-names = "ahbix-clk", 2075 "mi2s-bit-clk0", 2076 "mi2s-bit-clk1", 2077 "mi2s-bit-clk2", 2078 "mi2s-bit-clk3", 2079 "pcnoc-mport-clk", 2080 "pcnoc-sway-clk"; 2081 #sound-dai-cells = <1>; 2082 2083 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2084 interrupt-names = "lpass-irq-lpaif"; 2085 reg = <0x07708000 0x10000>; 2086 reg-names = "lpass-lpaif"; 2087 2088 #address-cells = <1>; 2089 #size-cells = <0>; 2090 }; 2091 2092 lpass_codec: audio-codec@771c000 { 2093 compatible = "qcom,msm8916-wcd-digital-codec"; 2094 reg = <0x0771c000 0x400>; 2095 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 2096 <&gcc GCC_CODEC_DIGCODEC_CLK>; 2097 clock-names = "ahbix-clk", "mclk"; 2098 #sound-dai-cells = <1>; 2099 status = "disabled"; 2100 }; 2101 2102 sdhc_1: mmc@7824900 { 2103 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 2104 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 2105 reg-names = "hc", "core"; 2106 2107 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2109 interrupt-names = "hc_irq", "pwr_irq"; 2110 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 2111 <&gcc GCC_SDCC1_APPS_CLK>, 2112 <&xo_board>; 2113 clock-names = "iface", "core", "xo"; 2114 pinctrl-0 = <&sdc1_default>; 2115 pinctrl-1 = <&sdc1_sleep>; 2116 pinctrl-names = "default", "sleep"; 2117 mmc-ddr-1_8v; 2118 bus-width = <8>; 2119 non-removable; 2120 status = "disabled"; 2121 }; 2122 2123 sdhc_2: mmc@7864900 { 2124 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 2125 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 2126 reg-names = "hc", "core"; 2127 2128 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2130 interrupt-names = "hc_irq", "pwr_irq"; 2131 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2132 <&gcc GCC_SDCC2_APPS_CLK>, 2133 <&xo_board>; 2134 clock-names = "iface", "core", "xo"; 2135 pinctrl-0 = <&sdc2_default>; 2136 pinctrl-1 = <&sdc2_sleep>; 2137 pinctrl-names = "default", "sleep"; 2138 bus-width = <4>; 2139 status = "disabled"; 2140 }; 2141 2142 blsp_dma: dma-controller@7884000 { 2143 compatible = "qcom,bam-v1.7.0"; 2144 reg = <0x07884000 0x23000>; 2145 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2146 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2147 clock-names = "bam_clk"; 2148 #dma-cells = <1>; 2149 qcom,ee = <0>; 2150 qcom,controlled-remotely; 2151 }; 2152 2153 blsp_uart1: serial@78af000 { 2154 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2155 reg = <0x078af000 0x200>; 2156 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 2157 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 2158 clock-names = "core", "iface"; 2159 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 2160 dma-names = "tx", "rx"; 2161 pinctrl-names = "default", "sleep"; 2162 pinctrl-0 = <&blsp_uart1_default>; 2163 pinctrl-1 = <&blsp_uart1_sleep>; 2164 status = "disabled"; 2165 }; 2166 2167 blsp_uart2: serial@78b0000 { 2168 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2169 reg = <0x078b0000 0x200>; 2170 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2171 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 2172 clock-names = "core", "iface"; 2173 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 2174 dma-names = "tx", "rx"; 2175 pinctrl-names = "default", "sleep"; 2176 pinctrl-0 = <&blsp_uart2_default>; 2177 pinctrl-1 = <&blsp_uart2_sleep>; 2178 status = "disabled"; 2179 }; 2180 2181 blsp_i2c1: i2c@78b5000 { 2182 compatible = "qcom,i2c-qup-v2.2.1"; 2183 reg = <0x078b5000 0x500>; 2184 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2185 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2186 <&gcc GCC_BLSP1_AHB_CLK>; 2187 clock-names = "core", "iface"; 2188 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 2189 dma-names = "tx", "rx"; 2190 pinctrl-names = "default", "sleep"; 2191 pinctrl-0 = <&blsp_i2c1_default>; 2192 pinctrl-1 = <&blsp_i2c1_sleep>; 2193 #address-cells = <1>; 2194 #size-cells = <0>; 2195 status = "disabled"; 2196 }; 2197 2198 blsp_spi1: spi@78b5000 { 2199 compatible = "qcom,spi-qup-v2.2.1"; 2200 reg = <0x078b5000 0x500>; 2201 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2202 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2203 <&gcc GCC_BLSP1_AHB_CLK>; 2204 clock-names = "core", "iface"; 2205 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 2206 dma-names = "tx", "rx"; 2207 pinctrl-names = "default", "sleep"; 2208 pinctrl-0 = <&blsp_spi1_default>; 2209 pinctrl-1 = <&blsp_spi1_sleep>; 2210 #address-cells = <1>; 2211 #size-cells = <0>; 2212 status = "disabled"; 2213 }; 2214 2215 blsp_i2c2: i2c@78b6000 { 2216 compatible = "qcom,i2c-qup-v2.2.1"; 2217 reg = <0x078b6000 0x500>; 2218 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2219 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2220 <&gcc GCC_BLSP1_AHB_CLK>; 2221 clock-names = "core", "iface"; 2222 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 2223 dma-names = "tx", "rx"; 2224 pinctrl-names = "default", "sleep"; 2225 pinctrl-0 = <&blsp_i2c2_default>; 2226 pinctrl-1 = <&blsp_i2c2_sleep>; 2227 #address-cells = <1>; 2228 #size-cells = <0>; 2229 status = "disabled"; 2230 }; 2231 2232 blsp_spi2: spi@78b6000 { 2233 compatible = "qcom,spi-qup-v2.2.1"; 2234 reg = <0x078b6000 0x500>; 2235 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2236 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 2237 <&gcc GCC_BLSP1_AHB_CLK>; 2238 clock-names = "core", "iface"; 2239 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 2240 dma-names = "tx", "rx"; 2241 pinctrl-names = "default", "sleep"; 2242 pinctrl-0 = <&blsp_spi2_default>; 2243 pinctrl-1 = <&blsp_spi2_sleep>; 2244 #address-cells = <1>; 2245 #size-cells = <0>; 2246 status = "disabled"; 2247 }; 2248 2249 blsp_i2c3: i2c@78b7000 { 2250 compatible = "qcom,i2c-qup-v2.2.1"; 2251 reg = <0x078b7000 0x500>; 2252 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2253 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2254 <&gcc GCC_BLSP1_AHB_CLK>; 2255 clock-names = "core", "iface"; 2256 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 2257 dma-names = "tx", "rx"; 2258 pinctrl-names = "default", "sleep"; 2259 pinctrl-0 = <&blsp_i2c3_default>; 2260 pinctrl-1 = <&blsp_i2c3_sleep>; 2261 #address-cells = <1>; 2262 #size-cells = <0>; 2263 status = "disabled"; 2264 }; 2265 2266 blsp_spi3: spi@78b7000 { 2267 compatible = "qcom,spi-qup-v2.2.1"; 2268 reg = <0x078b7000 0x500>; 2269 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2270 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 2271 <&gcc GCC_BLSP1_AHB_CLK>; 2272 clock-names = "core", "iface"; 2273 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 2274 dma-names = "tx", "rx"; 2275 pinctrl-names = "default", "sleep"; 2276 pinctrl-0 = <&blsp_spi3_default>; 2277 pinctrl-1 = <&blsp_spi3_sleep>; 2278 #address-cells = <1>; 2279 #size-cells = <0>; 2280 status = "disabled"; 2281 }; 2282 2283 blsp_i2c4: i2c@78b8000 { 2284 compatible = "qcom,i2c-qup-v2.2.1"; 2285 reg = <0x078b8000 0x500>; 2286 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2287 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2288 <&gcc GCC_BLSP1_AHB_CLK>; 2289 clock-names = "core", "iface"; 2290 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 2291 dma-names = "tx", "rx"; 2292 pinctrl-names = "default", "sleep"; 2293 pinctrl-0 = <&blsp_i2c4_default>; 2294 pinctrl-1 = <&blsp_i2c4_sleep>; 2295 #address-cells = <1>; 2296 #size-cells = <0>; 2297 status = "disabled"; 2298 }; 2299 2300 blsp_spi4: spi@78b8000 { 2301 compatible = "qcom,spi-qup-v2.2.1"; 2302 reg = <0x078b8000 0x500>; 2303 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2304 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 2305 <&gcc GCC_BLSP1_AHB_CLK>; 2306 clock-names = "core", "iface"; 2307 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 2308 dma-names = "tx", "rx"; 2309 pinctrl-names = "default", "sleep"; 2310 pinctrl-0 = <&blsp_spi4_default>; 2311 pinctrl-1 = <&blsp_spi4_sleep>; 2312 #address-cells = <1>; 2313 #size-cells = <0>; 2314 status = "disabled"; 2315 }; 2316 2317 blsp_i2c5: i2c@78b9000 { 2318 compatible = "qcom,i2c-qup-v2.2.1"; 2319 reg = <0x078b9000 0x500>; 2320 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2321 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2322 <&gcc GCC_BLSP1_AHB_CLK>; 2323 clock-names = "core", "iface"; 2324 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 2325 dma-names = "tx", "rx"; 2326 pinctrl-names = "default", "sleep"; 2327 pinctrl-0 = <&blsp_i2c5_default>; 2328 pinctrl-1 = <&blsp_i2c5_sleep>; 2329 #address-cells = <1>; 2330 #size-cells = <0>; 2331 status = "disabled"; 2332 }; 2333 2334 blsp_spi5: spi@78b9000 { 2335 compatible = "qcom,spi-qup-v2.2.1"; 2336 reg = <0x078b9000 0x500>; 2337 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2338 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 2339 <&gcc GCC_BLSP1_AHB_CLK>; 2340 clock-names = "core", "iface"; 2341 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 2342 dma-names = "tx", "rx"; 2343 pinctrl-names = "default", "sleep"; 2344 pinctrl-0 = <&blsp_spi5_default>; 2345 pinctrl-1 = <&blsp_spi5_sleep>; 2346 #address-cells = <1>; 2347 #size-cells = <0>; 2348 status = "disabled"; 2349 }; 2350 2351 blsp_i2c6: i2c@78ba000 { 2352 compatible = "qcom,i2c-qup-v2.2.1"; 2353 reg = <0x078ba000 0x500>; 2354 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2355 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2356 <&gcc GCC_BLSP1_AHB_CLK>; 2357 clock-names = "core", "iface"; 2358 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 2359 dma-names = "tx", "rx"; 2360 pinctrl-names = "default", "sleep"; 2361 pinctrl-0 = <&blsp_i2c6_default>; 2362 pinctrl-1 = <&blsp_i2c6_sleep>; 2363 #address-cells = <1>; 2364 #size-cells = <0>; 2365 status = "disabled"; 2366 }; 2367 2368 blsp_spi6: spi@78ba000 { 2369 compatible = "qcom,spi-qup-v2.2.1"; 2370 reg = <0x078ba000 0x500>; 2371 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2372 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 2373 <&gcc GCC_BLSP1_AHB_CLK>; 2374 clock-names = "core", "iface"; 2375 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 2376 dma-names = "tx", "rx"; 2377 pinctrl-names = "default", "sleep"; 2378 pinctrl-0 = <&blsp_spi6_default>; 2379 pinctrl-1 = <&blsp_spi6_sleep>; 2380 #address-cells = <1>; 2381 #size-cells = <0>; 2382 status = "disabled"; 2383 }; 2384 2385 usb: usb@78d9000 { 2386 compatible = "qcom,ci-hdrc"; 2387 reg = <0x078d9000 0x200>, 2388 <0x078d9200 0x200>; 2389 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2390 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2391 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 2392 <&gcc GCC_USB_HS_SYSTEM_CLK>; 2393 clock-names = "iface", "core"; 2394 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 2395 assigned-clock-rates = <80000000>; 2396 resets = <&gcc GCC_USB_HS_BCR>; 2397 reset-names = "core"; 2398 phy_type = "ulpi"; 2399 dr_mode = "otg"; 2400 hnp-disable; 2401 srp-disable; 2402 adp-disable; 2403 ahb-burst-config = <0>; 2404 phy-names = "usb-phy"; 2405 phys = <&usb_hs_phy>; 2406 status = "disabled"; 2407 #reset-cells = <1>; 2408 2409 ulpi { 2410 usb_hs_phy: phy { 2411 compatible = "qcom,usb-hs-phy-msm8916", 2412 "qcom,usb-hs-phy"; 2413 #phy-cells = <0>; 2414 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 2415 clock-names = "ref", "sleep"; 2416 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 2417 reset-names = "phy", "por"; 2418 qcom,init-seq = /bits/ 8 <0x0 0x44>, 2419 <0x1 0x6b>, 2420 <0x2 0x24>, 2421 <0x3 0x13>; 2422 }; 2423 }; 2424 }; 2425 2426 wcnss: remoteproc@a204000 { 2427 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 2428 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 2429 reg-names = "ccu", "dxe", "pmu"; 2430 2431 memory-region = <&wcnss_mem>; 2432 2433 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 2434 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2435 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2436 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2437 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2438 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2439 2440 power-domains = <&rpmpd MSM8916_VDDCX>, 2441 <&rpmpd MSM8916_VDDMX>; 2442 power-domain-names = "cx", "mx"; 2443 2444 qcom,smem-states = <&wcnss_smp2p_out 0>; 2445 qcom,smem-state-names = "stop"; 2446 2447 pinctrl-names = "default"; 2448 pinctrl-0 = <&wcss_wlan_default>; 2449 2450 status = "disabled"; 2451 2452 wcnss_iris: iris { 2453 /* Separate chip, compatible is board-specific */ 2454 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 2455 clock-names = "xo"; 2456 }; 2457 2458 smd-edge { 2459 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 2460 2461 mboxes = <&apcs 17>; 2462 qcom,smd-edge = <6>; 2463 qcom,remote-pid = <4>; 2464 2465 label = "pronto"; 2466 2467 wcnss_ctrl: wcnss { 2468 compatible = "qcom,wcnss"; 2469 qcom,smd-channels = "WCNSS_CTRL"; 2470 2471 qcom,mmio = <&wcnss>; 2472 2473 wcnss_bt: bluetooth { 2474 compatible = "qcom,wcnss-bt"; 2475 }; 2476 2477 wcnss_wifi: wifi { 2478 compatible = "qcom,wcnss-wlan"; 2479 2480 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2482 interrupt-names = "tx", "rx"; 2483 2484 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 2485 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 2486 }; 2487 }; 2488 }; 2489 }; 2490 2491 intc: interrupt-controller@b000000 { 2492 compatible = "qcom,msm-qgic2"; 2493 interrupt-controller; 2494 #interrupt-cells = <3>; 2495 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 2496 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 2497 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 2498 }; 2499 2500 apcs: mailbox@b011000 { 2501 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 2502 reg = <0x0b011000 0x1000>; 2503 #mbox-cells = <1>; 2504 clocks = <&a53pll>, <&gcc GPLL0_VOTE>; 2505 clock-names = "pll", "aux"; 2506 #clock-cells = <0>; 2507 }; 2508 2509 a53pll: clock@b016000 { 2510 compatible = "qcom,msm8916-a53pll"; 2511 reg = <0x0b016000 0x40>; 2512 #clock-cells = <0>; 2513 clocks = <&xo_board>; 2514 clock-names = "xo"; 2515 }; 2516 2517 timer@b020000 { 2518 #address-cells = <1>; 2519 #size-cells = <1>; 2520 ranges; 2521 compatible = "arm,armv7-timer-mem"; 2522 reg = <0x0b020000 0x1000>; 2523 clock-frequency = <19200000>; 2524 2525 frame@b021000 { 2526 frame-number = <0>; 2527 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2528 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2529 reg = <0x0b021000 0x1000>, 2530 <0x0b022000 0x1000>; 2531 }; 2532 2533 frame@b023000 { 2534 frame-number = <1>; 2535 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2536 reg = <0x0b023000 0x1000>; 2537 status = "disabled"; 2538 }; 2539 2540 frame@b024000 { 2541 frame-number = <2>; 2542 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2543 reg = <0x0b024000 0x1000>; 2544 status = "disabled"; 2545 }; 2546 2547 frame@b025000 { 2548 frame-number = <3>; 2549 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2550 reg = <0x0b025000 0x1000>; 2551 status = "disabled"; 2552 }; 2553 2554 frame@b026000 { 2555 frame-number = <4>; 2556 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2557 reg = <0x0b026000 0x1000>; 2558 status = "disabled"; 2559 }; 2560 2561 frame@b027000 { 2562 frame-number = <5>; 2563 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2564 reg = <0x0b027000 0x1000>; 2565 status = "disabled"; 2566 }; 2567 2568 frame@b028000 { 2569 frame-number = <6>; 2570 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2571 reg = <0x0b028000 0x1000>; 2572 status = "disabled"; 2573 }; 2574 }; 2575 2576 cpu0_acc: power-manager@b088000 { 2577 compatible = "qcom,msm8916-acc"; 2578 reg = <0x0b088000 0x1000>; 2579 status = "reserved"; /* Controlled by PSCI firmware */ 2580 }; 2581 2582 cpu0_saw: power-manager@b089000 { 2583 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2584 reg = <0x0b089000 0x1000>; 2585 status = "reserved"; /* Controlled by PSCI firmware */ 2586 }; 2587 2588 cpu1_acc: power-manager@b098000 { 2589 compatible = "qcom,msm8916-acc"; 2590 reg = <0x0b098000 0x1000>; 2591 status = "reserved"; /* Controlled by PSCI firmware */ 2592 }; 2593 2594 cpu1_saw: power-manager@b099000 { 2595 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2596 reg = <0x0b099000 0x1000>; 2597 status = "reserved"; /* Controlled by PSCI firmware */ 2598 }; 2599 2600 cpu2_acc: power-manager@b0a8000 { 2601 compatible = "qcom,msm8916-acc"; 2602 reg = <0x0b0a8000 0x1000>; 2603 status = "reserved"; /* Controlled by PSCI firmware */ 2604 }; 2605 2606 cpu2_saw: power-manager@b0a9000 { 2607 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2608 reg = <0x0b0a9000 0x1000>; 2609 status = "reserved"; /* Controlled by PSCI firmware */ 2610 }; 2611 2612 cpu3_acc: power-manager@b0b8000 { 2613 compatible = "qcom,msm8916-acc"; 2614 reg = <0x0b0b8000 0x1000>; 2615 status = "reserved"; /* Controlled by PSCI firmware */ 2616 }; 2617 2618 cpu3_saw: power-manager@b0b9000 { 2619 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2620 reg = <0x0b0b9000 0x1000>; 2621 status = "reserved"; /* Controlled by PSCI firmware */ 2622 }; 2623 }; 2624 2625 thermal-zones { 2626 cpu0-1-thermal { 2627 polling-delay-passive = <250>; 2628 2629 thermal-sensors = <&tsens 5>; 2630 2631 trips { 2632 cpu0_1_alert0: trip-point0 { 2633 temperature = <75000>; 2634 hysteresis = <2000>; 2635 type = "passive"; 2636 }; 2637 cpu0_1_crit: cpu-crit { 2638 temperature = <110000>; 2639 hysteresis = <2000>; 2640 type = "critical"; 2641 }; 2642 }; 2643 2644 cooling-maps { 2645 map0 { 2646 trip = <&cpu0_1_alert0>; 2647 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2648 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2649 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2650 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2651 }; 2652 }; 2653 }; 2654 2655 cpu2-3-thermal { 2656 polling-delay-passive = <250>; 2657 2658 thermal-sensors = <&tsens 4>; 2659 2660 trips { 2661 cpu2_3_alert0: trip-point0 { 2662 temperature = <75000>; 2663 hysteresis = <2000>; 2664 type = "passive"; 2665 }; 2666 cpu2_3_crit: cpu-crit { 2667 temperature = <110000>; 2668 hysteresis = <2000>; 2669 type = "critical"; 2670 }; 2671 }; 2672 2673 cooling-maps { 2674 map0 { 2675 trip = <&cpu2_3_alert0>; 2676 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2677 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2678 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2679 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2680 }; 2681 }; 2682 }; 2683 2684 gpu-thermal { 2685 polling-delay-passive = <250>; 2686 2687 thermal-sensors = <&tsens 2>; 2688 2689 cooling-maps { 2690 map0 { 2691 trip = <&gpu_alert0>; 2692 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2693 }; 2694 }; 2695 2696 trips { 2697 gpu_alert0: trip-point0 { 2698 temperature = <75000>; 2699 hysteresis = <2000>; 2700 type = "passive"; 2701 }; 2702 gpu_crit: gpu-crit { 2703 temperature = <95000>; 2704 hysteresis = <2000>; 2705 type = "critical"; 2706 }; 2707 }; 2708 }; 2709 2710 camera-thermal { 2711 polling-delay-passive = <250>; 2712 2713 thermal-sensors = <&tsens 1>; 2714 2715 trips { 2716 cam_alert0: trip-point0 { 2717 temperature = <75000>; 2718 hysteresis = <2000>; 2719 type = "hot"; 2720 }; 2721 }; 2722 }; 2723 2724 modem-thermal { 2725 polling-delay-passive = <250>; 2726 2727 thermal-sensors = <&tsens 0>; 2728 2729 trips { 2730 modem_alert0: trip-point0 { 2731 temperature = <85000>; 2732 hysteresis = <2000>; 2733 type = "hot"; 2734 }; 2735 }; 2736 }; 2737 }; 2738 2739 timer { 2740 compatible = "arm,armv8-timer"; 2741 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2742 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2743 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2744 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2745 }; 2746}; 2747