1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/arm/coresight-cti-dt.h> 7#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 8#include <dt-bindings/clock/qcom,gcc-msm8916.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/interconnect/qcom,msm8916.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/reset/qcom,gcc-msm8916.h> 14#include <dt-bindings/soc/qcom,apr.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 chosen { }; 24 25 memory@80000000 { 26 device_type = "memory"; 27 /* We expect the bootloader to fill in the reg */ 28 reg = <0 0x80000000 0 0>; 29 }; 30 31 reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 tz-apps@86000000 { 37 reg = <0x0 0x86000000 0x0 0x300000>; 38 no-map; 39 }; 40 41 smem@86300000 { 42 compatible = "qcom,smem"; 43 reg = <0x0 0x86300000 0x0 0x100000>; 44 no-map; 45 46 hwlocks = <&tcsr_mutex 3>; 47 qcom,rpm-msg-ram = <&rpm_msg_ram>; 48 }; 49 50 hypervisor@86400000 { 51 reg = <0x0 0x86400000 0x0 0x100000>; 52 no-map; 53 }; 54 55 tz@86500000 { 56 reg = <0x0 0x86500000 0x0 0x180000>; 57 no-map; 58 }; 59 60 reserved@86680000 { 61 reg = <0x0 0x86680000 0x0 0x80000>; 62 no-map; 63 }; 64 65 rmtfs@86700000 { 66 compatible = "qcom,rmtfs-mem"; 67 reg = <0x0 0x86700000 0x0 0xe0000>; 68 no-map; 69 70 qcom,client-id = <1>; 71 }; 72 73 rfsa@867e0000 { 74 reg = <0x0 0x867e0000 0x0 0x20000>; 75 no-map; 76 }; 77 78 mpss_mem: mpss@86800000 { 79 /* 80 * The memory region for the mpss firmware is generally 81 * relocatable and could be allocated dynamically. 82 * However, many firmware versions tend to fail when 83 * loaded to some special addresses, so it is hard to 84 * define reliable alloc-ranges. 85 * 86 * alignment = <0x0 0x400000>; 87 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 88 */ 89 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */ 90 no-map; 91 status = "disabled"; 92 }; 93 94 wcnss_mem: wcnss { 95 size = <0x0 0x600000>; 96 alignment = <0x0 0x100000>; 97 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 98 no-map; 99 status = "disabled"; 100 }; 101 102 venus_mem: venus { 103 size = <0x0 0x500000>; 104 alignment = <0x0 0x100000>; 105 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 106 no-map; 107 status = "disabled"; 108 }; 109 110 mba_mem: mba { 111 size = <0x0 0x100000>; 112 alignment = <0x0 0x100000>; 113 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 114 no-map; 115 status = "disabled"; 116 }; 117 }; 118 119 clocks { 120 xo_board: xo-board { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 clock-frequency = <19200000>; 124 }; 125 126 sleep_clk: sleep-clk { 127 compatible = "fixed-clock"; 128 #clock-cells = <0>; 129 clock-frequency = <32764>; 130 }; 131 }; 132 133 cpus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 137 cpu0: cpu@0 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a53"; 140 reg = <0x0>; 141 next-level-cache = <&l2_0>; 142 enable-method = "psci"; 143 clocks = <&apcs>; 144 operating-points-v2 = <&cpu_opp_table>; 145 #cooling-cells = <2>; 146 power-domains = <&cpu_pd0>; 147 power-domain-names = "psci"; 148 qcom,acc = <&cpu0_acc>; 149 qcom,saw = <&cpu0_saw>; 150 }; 151 152 cpu1: cpu@1 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a53"; 155 reg = <0x1>; 156 next-level-cache = <&l2_0>; 157 enable-method = "psci"; 158 clocks = <&apcs>; 159 operating-points-v2 = <&cpu_opp_table>; 160 #cooling-cells = <2>; 161 power-domains = <&cpu_pd1>; 162 power-domain-names = "psci"; 163 qcom,acc = <&cpu1_acc>; 164 qcom,saw = <&cpu1_saw>; 165 }; 166 167 cpu2: cpu@2 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a53"; 170 reg = <0x2>; 171 next-level-cache = <&l2_0>; 172 enable-method = "psci"; 173 clocks = <&apcs>; 174 operating-points-v2 = <&cpu_opp_table>; 175 #cooling-cells = <2>; 176 power-domains = <&cpu_pd2>; 177 power-domain-names = "psci"; 178 qcom,acc = <&cpu2_acc>; 179 qcom,saw = <&cpu2_saw>; 180 }; 181 182 cpu3: cpu@3 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a53"; 185 reg = <0x3>; 186 next-level-cache = <&l2_0>; 187 enable-method = "psci"; 188 clocks = <&apcs>; 189 operating-points-v2 = <&cpu_opp_table>; 190 #cooling-cells = <2>; 191 power-domains = <&cpu_pd3>; 192 power-domain-names = "psci"; 193 qcom,acc = <&cpu3_acc>; 194 qcom,saw = <&cpu3_saw>; 195 }; 196 197 l2_0: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 cache-unified; 201 }; 202 203 idle-states { 204 entry-method = "psci"; 205 206 cpu_sleep_0: cpu-sleep-0 { 207 compatible = "arm,idle-state"; 208 idle-state-name = "standalone-power-collapse"; 209 arm,psci-suspend-param = <0x40000002>; 210 entry-latency-us = <130>; 211 exit-latency-us = <150>; 212 min-residency-us = <2000>; 213 local-timer-stop; 214 }; 215 }; 216 217 domain-idle-states { 218 219 cluster_ret: cluster-retention { 220 compatible = "domain-idle-state"; 221 arm,psci-suspend-param = <0x41000012>; 222 entry-latency-us = <500>; 223 exit-latency-us = <500>; 224 min-residency-us = <2000>; 225 }; 226 227 cluster_pwrdn: cluster-gdhs { 228 compatible = "domain-idle-state"; 229 arm,psci-suspend-param = <0x41000032>; 230 entry-latency-us = <2000>; 231 exit-latency-us = <2000>; 232 min-residency-us = <6000>; 233 }; 234 }; 235 }; 236 237 cpu_opp_table: opp-table-cpu { 238 compatible = "operating-points-v2"; 239 opp-shared; 240 241 opp-200000000 { 242 opp-hz = /bits/ 64 <200000000>; 243 }; 244 opp-400000000 { 245 opp-hz = /bits/ 64 <400000000>; 246 }; 247 opp-800000000 { 248 opp-hz = /bits/ 64 <800000000>; 249 }; 250 opp-998400000 { 251 opp-hz = /bits/ 64 <998400000>; 252 }; 253 }; 254 255 firmware { 256 scm: scm { 257 compatible = "qcom,scm-msm8916", "qcom,scm"; 258 clocks = <&gcc GCC_CRYPTO_CLK>, 259 <&gcc GCC_CRYPTO_AXI_CLK>, 260 <&gcc GCC_CRYPTO_AHB_CLK>; 261 clock-names = "core", "bus", "iface"; 262 #reset-cells = <1>; 263 264 qcom,dload-mode = <&tcsr 0x6100>; 265 }; 266 }; 267 268 pmu { 269 compatible = "arm,cortex-a53-pmu"; 270 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 271 }; 272 273 psci { 274 compatible = "arm,psci-1.0"; 275 method = "smc"; 276 277 cpu_pd0: power-domain-cpu0 { 278 #power-domain-cells = <0>; 279 power-domains = <&cluster_pd>; 280 domain-idle-states = <&cpu_sleep_0>; 281 }; 282 283 cpu_pd1: power-domain-cpu1 { 284 #power-domain-cells = <0>; 285 power-domains = <&cluster_pd>; 286 domain-idle-states = <&cpu_sleep_0>; 287 }; 288 289 cpu_pd2: power-domain-cpu2 { 290 #power-domain-cells = <0>; 291 power-domains = <&cluster_pd>; 292 domain-idle-states = <&cpu_sleep_0>; 293 }; 294 295 cpu_pd3: power-domain-cpu3 { 296 #power-domain-cells = <0>; 297 power-domains = <&cluster_pd>; 298 domain-idle-states = <&cpu_sleep_0>; 299 }; 300 301 cluster_pd: power-domain-cluster { 302 #power-domain-cells = <0>; 303 domain-idle-states = <&cluster_ret>, <&cluster_pwrdn>; 304 }; 305 }; 306 307 rpm: remoteproc { 308 compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc"; 309 310 smd-edge { 311 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 312 mboxes = <&apcs 0>; 313 qcom,smd-edge = <15>; 314 315 rpm_requests: rpm-requests { 316 compatible = "qcom,rpm-msm8916", "qcom,smd-rpm"; 317 qcom,smd-channels = "rpm_requests"; 318 319 rpmcc: clock-controller { 320 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; 321 #clock-cells = <1>; 322 clocks = <&xo_board>; 323 clock-names = "xo"; 324 }; 325 326 rpmpd: power-controller { 327 compatible = "qcom,msm8916-rpmpd"; 328 #power-domain-cells = <1>; 329 operating-points-v2 = <&rpmpd_opp_table>; 330 331 rpmpd_opp_table: opp-table { 332 compatible = "operating-points-v2"; 333 334 rpmpd_opp_ret: opp1 { 335 opp-level = <1>; 336 }; 337 rpmpd_opp_svs_krait: opp2 { 338 opp-level = <2>; 339 }; 340 rpmpd_opp_svs_soc: opp3 { 341 opp-level = <3>; 342 }; 343 rpmpd_opp_nom: opp4 { 344 opp-level = <4>; 345 }; 346 rpmpd_opp_turbo: opp5 { 347 opp-level = <5>; 348 }; 349 rpmpd_opp_super_turbo: opp6 { 350 opp-level = <6>; 351 }; 352 }; 353 }; 354 }; 355 }; 356 }; 357 358 smp2p-hexagon { 359 compatible = "qcom,smp2p"; 360 qcom,smem = <435>, <428>; 361 362 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 363 364 mboxes = <&apcs 14>; 365 366 qcom,local-pid = <0>; 367 qcom,remote-pid = <1>; 368 369 hexagon_smp2p_out: master-kernel { 370 qcom,entry-name = "master-kernel"; 371 372 #qcom,smem-state-cells = <1>; 373 }; 374 375 hexagon_smp2p_in: slave-kernel { 376 qcom,entry-name = "slave-kernel"; 377 378 interrupt-controller; 379 #interrupt-cells = <2>; 380 }; 381 }; 382 383 smp2p-wcnss { 384 compatible = "qcom,smp2p"; 385 qcom,smem = <451>, <431>; 386 387 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 388 389 mboxes = <&apcs 18>; 390 391 qcom,local-pid = <0>; 392 qcom,remote-pid = <4>; 393 394 wcnss_smp2p_out: master-kernel { 395 qcom,entry-name = "master-kernel"; 396 397 #qcom,smem-state-cells = <1>; 398 }; 399 400 wcnss_smp2p_in: slave-kernel { 401 qcom,entry-name = "slave-kernel"; 402 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 }; 406 }; 407 408 smsm { 409 compatible = "qcom,smsm"; 410 411 #address-cells = <1>; 412 #size-cells = <0>; 413 414 mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>; 415 416 apps_smsm: apps@0 { 417 reg = <0>; 418 419 #qcom,smem-state-cells = <1>; 420 }; 421 422 hexagon_smsm: hexagon@1 { 423 reg = <1>; 424 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 425 426 interrupt-controller; 427 #interrupt-cells = <2>; 428 }; 429 430 wcnss_smsm: wcnss@6 { 431 reg = <6>; 432 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 433 434 interrupt-controller; 435 #interrupt-cells = <2>; 436 }; 437 }; 438 439 soc: soc@0 { 440 #address-cells = <1>; 441 #size-cells = <1>; 442 ranges = <0 0 0 0xffffffff>; 443 compatible = "simple-bus"; 444 445 rng@22000 { 446 compatible = "qcom,prng"; 447 reg = <0x00022000 0x200>; 448 clocks = <&gcc GCC_PRNG_AHB_CLK>; 449 clock-names = "core"; 450 }; 451 452 restart@4ab000 { 453 compatible = "qcom,pshold"; 454 reg = <0x004ab000 0x4>; 455 }; 456 457 qfprom: qfprom@5c000 { 458 compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 459 reg = <0x0005c000 0x1000>; 460 #address-cells = <1>; 461 #size-cells = <1>; 462 463 tsens_base1: base1@d0 { 464 reg = <0xd0 0x1>; 465 bits = <0 7>; 466 }; 467 468 tsens_s0_p1: s0-p1@d0 { 469 reg = <0xd0 0x2>; 470 bits = <7 5>; 471 }; 472 473 tsens_s0_p2: s0-p2@d1 { 474 reg = <0xd1 0x2>; 475 bits = <4 5>; 476 }; 477 478 tsens_s1_p1: s1-p1@d2 { 479 reg = <0xd2 0x1>; 480 bits = <1 5>; 481 }; 482 tsens_s1_p2: s1-p2@d2 { 483 reg = <0xd2 0x2>; 484 bits = <6 5>; 485 }; 486 tsens_s2_p1: s2-p1@d3 { 487 reg = <0xd3 0x1>; 488 bits = <3 5>; 489 }; 490 491 tsens_s2_p2: s2-p2@d4 { 492 reg = <0xd4 0x1>; 493 bits = <0 5>; 494 }; 495 496 // no tsens with hw_id 3 497 498 tsens_s4_p1: s4-p1@d4 { 499 reg = <0xd4 0x2>; 500 bits = <5 5>; 501 }; 502 503 tsens_s4_p2: s4-p2@d5 { 504 reg = <0xd5 0x1>; 505 bits = <2 5>; 506 }; 507 508 tsens_s5_p1: s5-p1@d5 { 509 reg = <0xd5 0x2>; 510 bits = <7 5>; 511 }; 512 513 tsens_s5_p2: s5-p2@d6 { 514 reg = <0xd6 0x2>; 515 bits = <4 5>; 516 }; 517 518 tsens_base2: base2@d7 { 519 reg = <0xd7 0x1>; 520 bits = <1 7>; 521 }; 522 523 tsens_mode: mode@ef { 524 reg = <0xef 0x1>; 525 bits = <5 3>; 526 }; 527 }; 528 529 rpm_msg_ram: sram@60000 { 530 compatible = "qcom,rpm-msg-ram"; 531 reg = <0x00060000 0x8000>; 532 }; 533 534 sram@290000 { 535 compatible = "qcom,msm8916-rpm-stats"; 536 reg = <0x00290000 0x10000>; 537 }; 538 539 bimc: interconnect@400000 { 540 compatible = "qcom,msm8916-bimc"; 541 reg = <0x00400000 0x62000>; 542 #interconnect-cells = <1>; 543 }; 544 545 tsens: thermal-sensor@4a9000 { 546 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 547 reg = <0x004a9000 0x1000>, /* TM */ 548 <0x004a8000 0x1000>; /* SROT */ 549 550 // no hw_id 3 551 nvmem-cells = <&tsens_mode>, 552 <&tsens_base1>, <&tsens_base2>, 553 <&tsens_s0_p1>, <&tsens_s0_p2>, 554 <&tsens_s1_p1>, <&tsens_s1_p2>, 555 <&tsens_s2_p1>, <&tsens_s2_p2>, 556 <&tsens_s4_p1>, <&tsens_s4_p2>, 557 <&tsens_s5_p1>, <&tsens_s5_p2>; 558 nvmem-cell-names = "mode", 559 "base1", "base2", 560 "s0_p1", "s0_p2", 561 "s1_p1", "s1_p2", 562 "s2_p1", "s2_p2", 563 "s4_p1", "s4_p2", 564 "s5_p1", "s5_p2"; 565 #qcom,sensors = <5>; 566 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 567 interrupt-names = "uplow"; 568 #thermal-sensor-cells = <1>; 569 }; 570 571 pcnoc: interconnect@500000 { 572 compatible = "qcom,msm8916-pcnoc"; 573 reg = <0x00500000 0x11000>; 574 #interconnect-cells = <1>; 575 }; 576 577 snoc: interconnect@580000 { 578 compatible = "qcom,msm8916-snoc"; 579 reg = <0x00580000 0x14000>; 580 #interconnect-cells = <1>; 581 }; 582 583 stm: stm@802000 { 584 compatible = "arm,coresight-stm", "arm,primecell"; 585 reg = <0x00802000 0x1000>, 586 <0x09280000 0x180000>; 587 reg-names = "stm-base", "stm-stimulus-base"; 588 589 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 590 clock-names = "apb_pclk", "atclk"; 591 592 status = "disabled"; 593 594 out-ports { 595 port { 596 stm_out: endpoint { 597 remote-endpoint = <&funnel0_in7>; 598 }; 599 }; 600 }; 601 }; 602 603 /* System CTIs */ 604 /* CTI 0 - TMC connections */ 605 cti0: cti@810000 { 606 compatible = "arm,coresight-cti", "arm,primecell"; 607 reg = <0x00810000 0x1000>; 608 609 clocks = <&rpmcc RPM_QDSS_CLK>; 610 clock-names = "apb_pclk"; 611 612 status = "disabled"; 613 }; 614 615 /* CTI 1 - TPIU connections */ 616 cti1: cti@811000 { 617 compatible = "arm,coresight-cti", "arm,primecell"; 618 reg = <0x00811000 0x1000>; 619 620 clocks = <&rpmcc RPM_QDSS_CLK>; 621 clock-names = "apb_pclk"; 622 623 status = "disabled"; 624 }; 625 626 /* CTIs 2-11 - no information - not instantiated */ 627 628 tpiu: tpiu@820000 { 629 compatible = "arm,coresight-tpiu", "arm,primecell"; 630 reg = <0x00820000 0x1000>; 631 632 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 633 clock-names = "apb_pclk", "atclk"; 634 635 status = "disabled"; 636 637 in-ports { 638 port { 639 tpiu_in: endpoint { 640 remote-endpoint = <&replicator_out1>; 641 }; 642 }; 643 }; 644 }; 645 646 funnel0: funnel@821000 { 647 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 648 reg = <0x00821000 0x1000>; 649 650 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 651 clock-names = "apb_pclk", "atclk"; 652 653 status = "disabled"; 654 655 in-ports { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 659 /* 660 * Not described input ports: 661 * 0 - connected to Resource and Power Manger CPU ETM 662 * 1 - not-connected 663 * 2 - connected to Modem CPU ETM 664 * 3 - not-connected 665 * 5 - not-connected 666 * 6 - connected trought funnel to Wireless CPU ETM 667 * 7 - connected to STM component 668 */ 669 670 port@4 { 671 reg = <4>; 672 funnel0_in4: endpoint { 673 remote-endpoint = <&funnel1_out>; 674 }; 675 }; 676 677 port@7 { 678 reg = <7>; 679 funnel0_in7: endpoint { 680 remote-endpoint = <&stm_out>; 681 }; 682 }; 683 }; 684 685 out-ports { 686 port { 687 funnel0_out: endpoint { 688 remote-endpoint = <&etf_in>; 689 }; 690 }; 691 }; 692 }; 693 694 replicator: replicator@824000 { 695 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 696 reg = <0x00824000 0x1000>; 697 698 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 699 clock-names = "apb_pclk", "atclk"; 700 701 status = "disabled"; 702 703 out-ports { 704 #address-cells = <1>; 705 #size-cells = <0>; 706 707 port@0 { 708 reg = <0>; 709 replicator_out0: endpoint { 710 remote-endpoint = <&etr_in>; 711 }; 712 }; 713 port@1 { 714 reg = <1>; 715 replicator_out1: endpoint { 716 remote-endpoint = <&tpiu_in>; 717 }; 718 }; 719 }; 720 721 in-ports { 722 port { 723 replicator_in: endpoint { 724 remote-endpoint = <&etf_out>; 725 }; 726 }; 727 }; 728 }; 729 730 etf: etf@825000 { 731 compatible = "arm,coresight-tmc", "arm,primecell"; 732 reg = <0x00825000 0x1000>; 733 734 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 735 clock-names = "apb_pclk", "atclk"; 736 737 status = "disabled"; 738 739 in-ports { 740 port { 741 etf_in: endpoint { 742 remote-endpoint = <&funnel0_out>; 743 }; 744 }; 745 }; 746 747 out-ports { 748 port { 749 etf_out: endpoint { 750 remote-endpoint = <&replicator_in>; 751 }; 752 }; 753 }; 754 }; 755 756 etr: etr@826000 { 757 compatible = "arm,coresight-tmc", "arm,primecell"; 758 reg = <0x00826000 0x1000>; 759 760 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 761 clock-names = "apb_pclk", "atclk"; 762 763 status = "disabled"; 764 765 in-ports { 766 port { 767 etr_in: endpoint { 768 remote-endpoint = <&replicator_out0>; 769 }; 770 }; 771 }; 772 }; 773 774 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ 775 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 776 reg = <0x00841000 0x1000>; 777 778 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 779 clock-names = "apb_pclk", "atclk"; 780 781 status = "disabled"; 782 783 in-ports { 784 #address-cells = <1>; 785 #size-cells = <0>; 786 787 port@0 { 788 reg = <0>; 789 funnel1_in0: endpoint { 790 remote-endpoint = <&etm0_out>; 791 }; 792 }; 793 port@1 { 794 reg = <1>; 795 funnel1_in1: endpoint { 796 remote-endpoint = <&etm1_out>; 797 }; 798 }; 799 port@2 { 800 reg = <2>; 801 funnel1_in2: endpoint { 802 remote-endpoint = <&etm2_out>; 803 }; 804 }; 805 port@3 { 806 reg = <3>; 807 funnel1_in3: endpoint { 808 remote-endpoint = <&etm3_out>; 809 }; 810 }; 811 }; 812 813 out-ports { 814 port { 815 funnel1_out: endpoint { 816 remote-endpoint = <&funnel0_in4>; 817 }; 818 }; 819 }; 820 }; 821 822 debug0: debug@850000 { 823 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 824 reg = <0x00850000 0x1000>; 825 clocks = <&rpmcc RPM_QDSS_CLK>; 826 clock-names = "apb_pclk"; 827 cpu = <&cpu0>; 828 status = "disabled"; 829 }; 830 831 debug1: debug@852000 { 832 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 833 reg = <0x00852000 0x1000>; 834 clocks = <&rpmcc RPM_QDSS_CLK>; 835 clock-names = "apb_pclk"; 836 cpu = <&cpu1>; 837 status = "disabled"; 838 }; 839 840 debug2: debug@854000 { 841 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 842 reg = <0x00854000 0x1000>; 843 clocks = <&rpmcc RPM_QDSS_CLK>; 844 clock-names = "apb_pclk"; 845 cpu = <&cpu2>; 846 status = "disabled"; 847 }; 848 849 debug3: debug@856000 { 850 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 851 reg = <0x00856000 0x1000>; 852 clocks = <&rpmcc RPM_QDSS_CLK>; 853 clock-names = "apb_pclk"; 854 cpu = <&cpu3>; 855 status = "disabled"; 856 }; 857 858 /* Core CTIs; CTIs 12-15 */ 859 /* CTI - CPU-0 */ 860 cti12: cti@858000 { 861 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 862 "arm,primecell"; 863 reg = <0x00858000 0x1000>; 864 865 clocks = <&rpmcc RPM_QDSS_CLK>; 866 clock-names = "apb_pclk"; 867 868 cpu = <&cpu0>; 869 arm,cs-dev-assoc = <&etm0>; 870 871 status = "disabled"; 872 }; 873 874 /* CTI - CPU-1 */ 875 cti13: cti@859000 { 876 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 877 "arm,primecell"; 878 reg = <0x00859000 0x1000>; 879 880 clocks = <&rpmcc RPM_QDSS_CLK>; 881 clock-names = "apb_pclk"; 882 883 cpu = <&cpu1>; 884 arm,cs-dev-assoc = <&etm1>; 885 886 status = "disabled"; 887 }; 888 889 /* CTI - CPU-2 */ 890 cti14: cti@85a000 { 891 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 892 "arm,primecell"; 893 reg = <0x0085a000 0x1000>; 894 895 clocks = <&rpmcc RPM_QDSS_CLK>; 896 clock-names = "apb_pclk"; 897 898 cpu = <&cpu2>; 899 arm,cs-dev-assoc = <&etm2>; 900 901 status = "disabled"; 902 }; 903 904 /* CTI - CPU-3 */ 905 cti15: cti@85b000 { 906 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 907 "arm,primecell"; 908 reg = <0x0085b000 0x1000>; 909 910 clocks = <&rpmcc RPM_QDSS_CLK>; 911 clock-names = "apb_pclk"; 912 913 cpu = <&cpu3>; 914 arm,cs-dev-assoc = <&etm3>; 915 916 status = "disabled"; 917 }; 918 919 etm0: etm@85c000 { 920 compatible = "arm,coresight-etm4x", "arm,primecell"; 921 reg = <0x0085c000 0x1000>; 922 923 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 924 clock-names = "apb_pclk", "atclk"; 925 arm,coresight-loses-context-with-cpu; 926 927 cpu = <&cpu0>; 928 929 status = "disabled"; 930 931 out-ports { 932 port { 933 etm0_out: endpoint { 934 remote-endpoint = <&funnel1_in0>; 935 }; 936 }; 937 }; 938 }; 939 940 etm1: etm@85d000 { 941 compatible = "arm,coresight-etm4x", "arm,primecell"; 942 reg = <0x0085d000 0x1000>; 943 944 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 945 clock-names = "apb_pclk", "atclk"; 946 arm,coresight-loses-context-with-cpu; 947 948 cpu = <&cpu1>; 949 950 status = "disabled"; 951 952 out-ports { 953 port { 954 etm1_out: endpoint { 955 remote-endpoint = <&funnel1_in1>; 956 }; 957 }; 958 }; 959 }; 960 961 etm2: etm@85e000 { 962 compatible = "arm,coresight-etm4x", "arm,primecell"; 963 reg = <0x0085e000 0x1000>; 964 965 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 966 clock-names = "apb_pclk", "atclk"; 967 arm,coresight-loses-context-with-cpu; 968 969 cpu = <&cpu2>; 970 971 status = "disabled"; 972 973 out-ports { 974 port { 975 etm2_out: endpoint { 976 remote-endpoint = <&funnel1_in2>; 977 }; 978 }; 979 }; 980 }; 981 982 etm3: etm@85f000 { 983 compatible = "arm,coresight-etm4x", "arm,primecell"; 984 reg = <0x0085f000 0x1000>; 985 986 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 987 clock-names = "apb_pclk", "atclk"; 988 arm,coresight-loses-context-with-cpu; 989 990 cpu = <&cpu3>; 991 992 status = "disabled"; 993 994 out-ports { 995 port { 996 etm3_out: endpoint { 997 remote-endpoint = <&funnel1_in3>; 998 }; 999 }; 1000 }; 1001 }; 1002 1003 tlmm: pinctrl@1000000 { 1004 compatible = "qcom,msm8916-pinctrl"; 1005 reg = <0x01000000 0x300000>; 1006 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1007 gpio-controller; 1008 gpio-ranges = <&tlmm 0 0 122>; 1009 #gpio-cells = <2>; 1010 interrupt-controller; 1011 #interrupt-cells = <2>; 1012 1013 blsp_i2c1_default: blsp-i2c1-default-state { 1014 pins = "gpio2", "gpio3"; 1015 function = "blsp_i2c1"; 1016 drive-strength = <2>; 1017 bias-disable; 1018 }; 1019 1020 blsp_i2c1_sleep: blsp-i2c1-sleep-state { 1021 pins = "gpio2", "gpio3"; 1022 function = "gpio"; 1023 drive-strength = <2>; 1024 bias-disable; 1025 }; 1026 1027 blsp_i2c2_default: blsp-i2c2-default-state { 1028 pins = "gpio6", "gpio7"; 1029 function = "blsp_i2c2"; 1030 drive-strength = <2>; 1031 bias-disable; 1032 }; 1033 1034 blsp_i2c2_sleep: blsp-i2c2-sleep-state { 1035 pins = "gpio6", "gpio7"; 1036 function = "gpio"; 1037 drive-strength = <2>; 1038 bias-disable; 1039 }; 1040 1041 blsp_i2c3_default: blsp-i2c3-default-state { 1042 pins = "gpio10", "gpio11"; 1043 function = "blsp_i2c3"; 1044 drive-strength = <2>; 1045 bias-disable; 1046 }; 1047 1048 blsp_i2c3_sleep: blsp-i2c3-sleep-state { 1049 pins = "gpio10", "gpio11"; 1050 function = "gpio"; 1051 drive-strength = <2>; 1052 bias-disable; 1053 }; 1054 1055 blsp_i2c4_default: blsp-i2c4-default-state { 1056 pins = "gpio14", "gpio15"; 1057 function = "blsp_i2c4"; 1058 drive-strength = <2>; 1059 bias-disable; 1060 }; 1061 1062 blsp_i2c4_sleep: blsp-i2c4-sleep-state { 1063 pins = "gpio14", "gpio15"; 1064 function = "gpio"; 1065 drive-strength = <2>; 1066 bias-disable; 1067 }; 1068 1069 blsp_i2c5_default: blsp-i2c5-default-state { 1070 pins = "gpio18", "gpio19"; 1071 function = "blsp_i2c5"; 1072 drive-strength = <2>; 1073 bias-disable; 1074 }; 1075 1076 blsp_i2c5_sleep: blsp-i2c5-sleep-state { 1077 pins = "gpio18", "gpio19"; 1078 function = "gpio"; 1079 drive-strength = <2>; 1080 bias-disable; 1081 }; 1082 1083 blsp_i2c6_default: blsp-i2c6-default-state { 1084 pins = "gpio22", "gpio23"; 1085 function = "blsp_i2c6"; 1086 drive-strength = <2>; 1087 bias-disable; 1088 }; 1089 1090 blsp_i2c6_sleep: blsp-i2c6-sleep-state { 1091 pins = "gpio22", "gpio23"; 1092 function = "gpio"; 1093 drive-strength = <2>; 1094 bias-disable; 1095 }; 1096 1097 blsp_spi1_default: blsp-spi1-default-state { 1098 spi-pins { 1099 pins = "gpio0", "gpio1", "gpio3"; 1100 function = "blsp_spi1"; 1101 drive-strength = <12>; 1102 bias-disable; 1103 }; 1104 cs-pins { 1105 pins = "gpio2"; 1106 function = "gpio"; 1107 drive-strength = <16>; 1108 bias-disable; 1109 output-high; 1110 }; 1111 }; 1112 1113 blsp_spi1_sleep: blsp-spi1-sleep-state { 1114 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1115 function = "gpio"; 1116 drive-strength = <2>; 1117 bias-pull-down; 1118 }; 1119 1120 blsp_spi2_default: blsp-spi2-default-state { 1121 spi-pins { 1122 pins = "gpio4", "gpio5", "gpio7"; 1123 function = "blsp_spi2"; 1124 drive-strength = <12>; 1125 bias-disable; 1126 }; 1127 cs-pins { 1128 pins = "gpio6"; 1129 function = "gpio"; 1130 drive-strength = <16>; 1131 bias-disable; 1132 output-high; 1133 }; 1134 }; 1135 1136 blsp_spi2_sleep: blsp-spi2-sleep-state { 1137 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 1138 function = "gpio"; 1139 drive-strength = <2>; 1140 bias-pull-down; 1141 }; 1142 1143 blsp_spi3_default: blsp-spi3-default-state { 1144 spi-pins { 1145 pins = "gpio8", "gpio9", "gpio11"; 1146 function = "blsp_spi3"; 1147 drive-strength = <12>; 1148 bias-disable; 1149 }; 1150 cs-pins { 1151 pins = "gpio10"; 1152 function = "gpio"; 1153 drive-strength = <16>; 1154 bias-disable; 1155 output-high; 1156 }; 1157 }; 1158 1159 blsp_spi3_sleep: blsp-spi3-sleep-state { 1160 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 1161 function = "gpio"; 1162 drive-strength = <2>; 1163 bias-pull-down; 1164 }; 1165 1166 blsp_spi4_default: blsp-spi4-default-state { 1167 spi-pins { 1168 pins = "gpio12", "gpio13", "gpio15"; 1169 function = "blsp_spi4"; 1170 drive-strength = <12>; 1171 bias-disable; 1172 }; 1173 cs-pins { 1174 pins = "gpio14"; 1175 function = "gpio"; 1176 drive-strength = <16>; 1177 bias-disable; 1178 output-high; 1179 }; 1180 }; 1181 1182 blsp_spi4_sleep: blsp-spi4-sleep-state { 1183 pins = "gpio12", "gpio13", "gpio14", "gpio15"; 1184 function = "gpio"; 1185 drive-strength = <2>; 1186 bias-pull-down; 1187 }; 1188 1189 blsp_spi5_default: blsp-spi5-default-state { 1190 spi-pins { 1191 pins = "gpio16", "gpio17", "gpio19"; 1192 function = "blsp_spi5"; 1193 drive-strength = <12>; 1194 bias-disable; 1195 }; 1196 cs-pins { 1197 pins = "gpio18"; 1198 function = "gpio"; 1199 drive-strength = <16>; 1200 bias-disable; 1201 output-high; 1202 }; 1203 }; 1204 1205 blsp_spi5_sleep: blsp-spi5-sleep-state { 1206 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 1207 function = "gpio"; 1208 drive-strength = <2>; 1209 bias-pull-down; 1210 }; 1211 1212 blsp_spi6_default: blsp-spi6-default-state { 1213 spi-pins { 1214 pins = "gpio20", "gpio21", "gpio23"; 1215 function = "blsp_spi6"; 1216 drive-strength = <12>; 1217 bias-disable; 1218 }; 1219 cs-pins { 1220 pins = "gpio22"; 1221 function = "gpio"; 1222 drive-strength = <16>; 1223 bias-disable; 1224 output-high; 1225 }; 1226 }; 1227 1228 blsp_spi6_sleep: blsp-spi6-sleep-state { 1229 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 1230 function = "gpio"; 1231 drive-strength = <2>; 1232 bias-pull-down; 1233 }; 1234 1235 blsp_uart1_console_default: blsp-uart1-console-default-state { 1236 tx-pins { 1237 pins = "gpio0"; 1238 function = "blsp_uart1"; 1239 drive-strength = <16>; 1240 bias-disable; 1241 bootph-all; 1242 }; 1243 1244 rx-pins { 1245 pins = "gpio1"; 1246 function = "blsp_uart1"; 1247 drive-strength = <16>; 1248 bias-pull-up; 1249 bootph-all; 1250 }; 1251 }; 1252 1253 blsp_uart1_console_sleep: blsp-uart1-console-sleep-state { 1254 pins = "gpio0", "gpio1"; 1255 function = "gpio"; 1256 drive-strength = <2>; 1257 bias-pull-down; 1258 }; 1259 1260 blsp_uart2_console_default: blsp-uart2-console-default-state { 1261 tx-pins { 1262 pins = "gpio4"; 1263 function = "blsp_uart2"; 1264 drive-strength = <16>; 1265 bias-disable; 1266 bootph-all; 1267 }; 1268 1269 rx-pins { 1270 pins = "gpio5"; 1271 function = "blsp_uart2"; 1272 drive-strength = <16>; 1273 bias-pull-up; 1274 bootph-all; 1275 }; 1276 }; 1277 1278 blsp_uart2_console_sleep: blsp-uart2-console-sleep-state { 1279 pins = "gpio4", "gpio5"; 1280 function = "gpio"; 1281 drive-strength = <2>; 1282 bias-pull-down; 1283 }; 1284 1285 camera_front_default: camera-front-default-state { 1286 pwdn-pins { 1287 pins = "gpio33"; 1288 function = "gpio"; 1289 drive-strength = <16>; 1290 bias-disable; 1291 }; 1292 rst-pins { 1293 pins = "gpio28"; 1294 function = "gpio"; 1295 drive-strength = <16>; 1296 bias-disable; 1297 }; 1298 mclk1-pins { 1299 pins = "gpio27"; 1300 function = "cam_mclk1"; 1301 drive-strength = <16>; 1302 bias-disable; 1303 }; 1304 }; 1305 1306 camera_rear_default: camera-rear-default-state { 1307 pwdn-pins { 1308 pins = "gpio34"; 1309 function = "gpio"; 1310 drive-strength = <16>; 1311 bias-disable; 1312 }; 1313 rst-pins { 1314 pins = "gpio35"; 1315 function = "gpio"; 1316 drive-strength = <16>; 1317 bias-disable; 1318 }; 1319 mclk0-pins { 1320 pins = "gpio26"; 1321 function = "cam_mclk0"; 1322 drive-strength = <16>; 1323 bias-disable; 1324 }; 1325 }; 1326 1327 cci0_default: cci0-default-state { 1328 pins = "gpio29", "gpio30"; 1329 function = "cci_i2c"; 1330 drive-strength = <16>; 1331 bias-disable; 1332 }; 1333 1334 cdc_dmic_default: cdc-dmic-default-state { 1335 clk-pins { 1336 pins = "gpio0"; 1337 function = "dmic0_clk"; 1338 drive-strength = <8>; 1339 }; 1340 data-pins { 1341 pins = "gpio1"; 1342 function = "dmic0_data"; 1343 drive-strength = <8>; 1344 }; 1345 }; 1346 1347 cdc_dmic_sleep: cdc-dmic-sleep-state { 1348 clk-pins { 1349 pins = "gpio0"; 1350 function = "dmic0_clk"; 1351 drive-strength = <2>; 1352 bias-disable; 1353 }; 1354 data-pins { 1355 pins = "gpio1"; 1356 function = "dmic0_data"; 1357 drive-strength = <2>; 1358 bias-disable; 1359 }; 1360 }; 1361 1362 cdc_pdm_default: cdc-pdm-default-state { 1363 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1364 "gpio67", "gpio68"; 1365 function = "cdc_pdm0"; 1366 drive-strength = <8>; 1367 bias-disable; 1368 }; 1369 1370 cdc_pdm_sleep: cdc-pdm-sleep-state { 1371 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1372 "gpio67", "gpio68"; 1373 function = "cdc_pdm0"; 1374 drive-strength = <2>; 1375 bias-pull-down; 1376 }; 1377 1378 pri_mi2s_default: mi2s-pri-default-state { 1379 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1380 function = "pri_mi2s"; 1381 drive-strength = <8>; 1382 bias-disable; 1383 }; 1384 1385 pri_mi2s_sleep: mi2s-pri-sleep-state { 1386 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1387 function = "pri_mi2s"; 1388 drive-strength = <2>; 1389 bias-disable; 1390 }; 1391 1392 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { 1393 pins = "gpio116"; 1394 function = "pri_mi2s"; 1395 drive-strength = <8>; 1396 bias-disable; 1397 }; 1398 1399 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { 1400 pins = "gpio116"; 1401 function = "pri_mi2s"; 1402 drive-strength = <2>; 1403 bias-disable; 1404 }; 1405 1406 pri_mi2s_ws_default: mi2s-pri-ws-default-state { 1407 pins = "gpio110"; 1408 function = "pri_mi2s_ws"; 1409 drive-strength = <8>; 1410 bias-disable; 1411 }; 1412 1413 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { 1414 pins = "gpio110"; 1415 function = "pri_mi2s_ws"; 1416 drive-strength = <2>; 1417 bias-disable; 1418 }; 1419 1420 sec_mi2s_default: mi2s-sec-default-state { 1421 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1422 function = "sec_mi2s"; 1423 drive-strength = <8>; 1424 bias-disable; 1425 }; 1426 1427 sec_mi2s_sleep: mi2s-sec-sleep-state { 1428 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1429 function = "sec_mi2s"; 1430 drive-strength = <2>; 1431 bias-disable; 1432 }; 1433 1434 sdc1_default: sdc1-default-state { 1435 clk-pins { 1436 pins = "sdc1_clk"; 1437 bias-disable; 1438 drive-strength = <16>; 1439 }; 1440 cmd-pins { 1441 pins = "sdc1_cmd"; 1442 bias-pull-up; 1443 drive-strength = <10>; 1444 }; 1445 data-pins { 1446 pins = "sdc1_data"; 1447 bias-pull-up; 1448 drive-strength = <10>; 1449 }; 1450 }; 1451 1452 sdc1_sleep: sdc1-sleep-state { 1453 clk-pins { 1454 pins = "sdc1_clk"; 1455 bias-disable; 1456 drive-strength = <2>; 1457 }; 1458 cmd-pins { 1459 pins = "sdc1_cmd"; 1460 bias-pull-up; 1461 drive-strength = <2>; 1462 }; 1463 data-pins { 1464 pins = "sdc1_data"; 1465 bias-pull-up; 1466 drive-strength = <2>; 1467 }; 1468 }; 1469 1470 sdc2_default: sdc2-default-state { 1471 clk-pins { 1472 pins = "sdc2_clk"; 1473 bias-disable; 1474 drive-strength = <16>; 1475 }; 1476 cmd-pins { 1477 pins = "sdc2_cmd"; 1478 bias-pull-up; 1479 drive-strength = <10>; 1480 }; 1481 data-pins { 1482 pins = "sdc2_data"; 1483 bias-pull-up; 1484 drive-strength = <10>; 1485 }; 1486 }; 1487 1488 sdc2_sleep: sdc2-sleep-state { 1489 clk-pins { 1490 pins = "sdc2_clk"; 1491 bias-disable; 1492 drive-strength = <2>; 1493 }; 1494 cmd-pins { 1495 pins = "sdc2_cmd"; 1496 bias-pull-up; 1497 drive-strength = <2>; 1498 }; 1499 data-pins { 1500 pins = "sdc2_data"; 1501 bias-pull-up; 1502 drive-strength = <2>; 1503 }; 1504 }; 1505 1506 wcss_wlan_default: wcss-wlan-default-state { 1507 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; 1508 function = "wcss_wlan"; 1509 drive-strength = <6>; 1510 bias-pull-up; 1511 }; 1512 }; 1513 1514 gcc: clock-controller@1800000 { 1515 compatible = "qcom,gcc-msm8916"; 1516 #clock-cells = <1>; 1517 #reset-cells = <1>; 1518 #power-domain-cells = <1>; 1519 reg = <0x01800000 0x80000>; 1520 clocks = <&xo_board>, 1521 <&sleep_clk>, 1522 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 1523 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1524 <0>, 1525 <0>, 1526 <0>; 1527 clock-names = "xo", 1528 "sleep_clk", 1529 "dsi0pll", 1530 "dsi0pllbyte", 1531 "ext_mclk", 1532 "ext_pri_i2s", 1533 "ext_sec_i2s"; 1534 }; 1535 1536 tcsr_mutex: hwlock@1905000 { 1537 compatible = "qcom,tcsr-mutex"; 1538 reg = <0x01905000 0x20000>; 1539 #hwlock-cells = <1>; 1540 }; 1541 1542 tcsr: syscon@1937000 { 1543 compatible = "qcom,tcsr-msm8916", "syscon"; 1544 reg = <0x01937000 0x30000>; 1545 }; 1546 1547 mdss: display-subsystem@1a00000 { 1548 status = "disabled"; 1549 compatible = "qcom,mdss"; 1550 reg = <0x01a00000 0x1000>, 1551 <0x01ac8000 0x3000>; 1552 reg-names = "mdss_phys", "vbif_phys"; 1553 1554 power-domains = <&gcc MDSS_GDSC>; 1555 1556 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1557 <&gcc GCC_MDSS_AXI_CLK>, 1558 <&gcc GCC_MDSS_VSYNC_CLK>; 1559 clock-names = "iface", 1560 "bus", 1561 "vsync"; 1562 1563 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1564 1565 resets = <&gcc GCC_MDSS_BCR>; 1566 1567 interrupt-controller; 1568 #interrupt-cells = <1>; 1569 1570 #address-cells = <1>; 1571 #size-cells = <1>; 1572 ranges; 1573 1574 mdss_mdp: display-controller@1a01000 { 1575 compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; 1576 reg = <0x01a01000 0x89000>; 1577 reg-names = "mdp_phys"; 1578 1579 interrupt-parent = <&mdss>; 1580 interrupts = <0>; 1581 1582 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1583 <&gcc GCC_MDSS_AXI_CLK>, 1584 <&gcc GCC_MDSS_MDP_CLK>, 1585 <&gcc GCC_MDSS_VSYNC_CLK>; 1586 clock-names = "iface", 1587 "bus", 1588 "core", 1589 "vsync"; 1590 1591 iommus = <&apps_iommu 4>; 1592 1593 ports { 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 1597 port@0 { 1598 reg = <0>; 1599 mdss_mdp_intf1_out: endpoint { 1600 remote-endpoint = <&mdss_dsi0_in>; 1601 }; 1602 }; 1603 }; 1604 }; 1605 1606 mdss_dsi0: dsi@1a98000 { 1607 compatible = "qcom,msm8916-dsi-ctrl", 1608 "qcom,mdss-dsi-ctrl"; 1609 reg = <0x01a98000 0x25c>; 1610 reg-names = "dsi_ctrl"; 1611 1612 interrupt-parent = <&mdss>; 1613 interrupts = <4>; 1614 1615 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1616 <&gcc PCLK0_CLK_SRC>; 1617 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1618 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1619 1620 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1621 <&gcc GCC_MDSS_AHB_CLK>, 1622 <&gcc GCC_MDSS_AXI_CLK>, 1623 <&gcc GCC_MDSS_BYTE0_CLK>, 1624 <&gcc GCC_MDSS_PCLK0_CLK>, 1625 <&gcc GCC_MDSS_ESC0_CLK>; 1626 clock-names = "mdp_core", 1627 "iface", 1628 "bus", 1629 "byte", 1630 "pixel", 1631 "core"; 1632 phys = <&mdss_dsi0_phy>; 1633 1634 #address-cells = <1>; 1635 #size-cells = <0>; 1636 1637 ports { 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 1641 port@0 { 1642 reg = <0>; 1643 mdss_dsi0_in: endpoint { 1644 remote-endpoint = <&mdss_mdp_intf1_out>; 1645 }; 1646 }; 1647 1648 port@1 { 1649 reg = <1>; 1650 mdss_dsi0_out: endpoint { 1651 }; 1652 }; 1653 }; 1654 }; 1655 1656 mdss_dsi0_phy: phy@1a98300 { 1657 compatible = "qcom,dsi-phy-28nm-lp"; 1658 reg = <0x01a98300 0xd4>, 1659 <0x01a98500 0x280>, 1660 <0x01a98780 0x30>; 1661 reg-names = "dsi_pll", 1662 "dsi_phy", 1663 "dsi_phy_regulator"; 1664 1665 #clock-cells = <1>; 1666 #phy-cells = <0>; 1667 1668 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1669 <&xo_board>; 1670 clock-names = "iface", "ref"; 1671 }; 1672 }; 1673 1674 camss: camss@1b0ac00 { 1675 compatible = "qcom,msm8916-camss"; 1676 reg = <0x01b0ac00 0x200>, 1677 <0x01b00030 0x4>, 1678 <0x01b0b000 0x200>, 1679 <0x01b00038 0x4>, 1680 <0x01b08000 0x100>, 1681 <0x01b08400 0x100>, 1682 <0x01b0a000 0x500>, 1683 <0x01b00020 0x10>, 1684 <0x01b10000 0x1000>; 1685 reg-names = "csiphy0", 1686 "csiphy0_clk_mux", 1687 "csiphy1", 1688 "csiphy1_clk_mux", 1689 "csid0", 1690 "csid1", 1691 "ispif", 1692 "csi_clk_mux", 1693 "vfe0"; 1694 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1695 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1696 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1697 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1698 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1699 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1700 interrupt-names = "csiphy0", 1701 "csiphy1", 1702 "csid0", 1703 "csid1", 1704 "ispif", 1705 "vfe0"; 1706 power-domains = <&gcc VFE_GDSC>; 1707 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1708 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1709 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1710 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1711 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1712 <&gcc GCC_CAMSS_CSI0_CLK>, 1713 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1714 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1715 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1716 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1717 <&gcc GCC_CAMSS_CSI1_CLK>, 1718 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1719 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1720 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1721 <&gcc GCC_CAMSS_AHB_CLK>, 1722 <&gcc GCC_CAMSS_VFE0_CLK>, 1723 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1724 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1725 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1726 clock-names = "top_ahb", 1727 "ispif_ahb", 1728 "csiphy0_timer", 1729 "csiphy1_timer", 1730 "csi0_ahb", 1731 "csi0", 1732 "csi0_phy", 1733 "csi0_pix", 1734 "csi0_rdi", 1735 "csi1_ahb", 1736 "csi1", 1737 "csi1_phy", 1738 "csi1_pix", 1739 "csi1_rdi", 1740 "ahb", 1741 "vfe0", 1742 "csi_vfe0", 1743 "vfe_ahb", 1744 "vfe_axi"; 1745 iommus = <&apps_iommu 3>; 1746 status = "disabled"; 1747 ports { 1748 #address-cells = <1>; 1749 #size-cells = <0>; 1750 1751 port@0 { 1752 reg = <0>; 1753 }; 1754 1755 port@1 { 1756 reg = <1>; 1757 }; 1758 }; 1759 }; 1760 1761 cci: cci@1b0c000 { 1762 compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; 1763 #address-cells = <1>; 1764 #size-cells = <0>; 1765 reg = <0x01b0c000 0x1000>; 1766 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1767 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1768 <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1769 <&gcc GCC_CAMSS_CCI_CLK>, 1770 <&gcc GCC_CAMSS_AHB_CLK>; 1771 clock-names = "camss_top_ahb", "cci_ahb", 1772 "cci", "camss_ahb"; 1773 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1774 <&gcc GCC_CAMSS_CCI_CLK>; 1775 assigned-clock-rates = <80000000>, <19200000>; 1776 pinctrl-names = "default"; 1777 pinctrl-0 = <&cci0_default>; 1778 status = "disabled"; 1779 1780 cci_i2c0: i2c-bus@0 { 1781 reg = <0>; 1782 clock-frequency = <400000>; 1783 #address-cells = <1>; 1784 #size-cells = <0>; 1785 }; 1786 }; 1787 1788 gpu: gpu@1c00000 { 1789 compatible = "qcom,adreno-306.0", "qcom,adreno"; 1790 reg = <0x01c00000 0x20000>; 1791 reg-names = "kgsl_3d0_reg_memory"; 1792 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1793 interrupt-names = "kgsl_3d0_irq"; 1794 clock-names = 1795 "core", 1796 "iface", 1797 "mem", 1798 "mem_iface", 1799 "alt_mem_iface", 1800 "gfx3d"; 1801 clocks = 1802 <&gcc GCC_OXILI_GFX3D_CLK>, 1803 <&gcc GCC_OXILI_AHB_CLK>, 1804 <&gcc GCC_OXILI_GMEM_CLK>, 1805 <&gcc GCC_BIMC_GFX_CLK>, 1806 <&gcc GCC_BIMC_GPU_CLK>, 1807 <&gcc GFX3D_CLK_SRC>; 1808 power-domains = <&gcc OXILI_GDSC>; 1809 operating-points-v2 = <&gpu_opp_table>; 1810 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1811 #cooling-cells = <2>; 1812 1813 status = "disabled"; 1814 1815 gpu_opp_table: opp-table { 1816 compatible = "operating-points-v2"; 1817 1818 opp-400000000 { 1819 opp-hz = /bits/ 64 <400000000>; 1820 }; 1821 opp-19200000 { 1822 opp-hz = /bits/ 64 <19200000>; 1823 }; 1824 }; 1825 }; 1826 1827 venus: video-codec@1d00000 { 1828 compatible = "qcom,msm8916-venus"; 1829 reg = <0x01d00000 0xff000>; 1830 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1831 power-domains = <&gcc VENUS_GDSC>; 1832 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1833 <&gcc GCC_VENUS0_AHB_CLK>, 1834 <&gcc GCC_VENUS0_AXI_CLK>; 1835 clock-names = "core", "iface", "bus"; 1836 iommus = <&apps_iommu 5>; 1837 memory-region = <&venus_mem>; 1838 status = "disabled"; 1839 }; 1840 1841 apps_iommu: iommu@1ef0000 { 1842 #address-cells = <1>; 1843 #size-cells = <1>; 1844 #iommu-cells = <1>; 1845 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1846 ranges = <0 0x01e20000 0x20000>; 1847 reg = <0x01ef0000 0x3000>; 1848 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1849 <&gcc GCC_APSS_TCU_CLK>; 1850 clock-names = "iface", "bus"; 1851 qcom,iommu-secure-id = <17>; 1852 1853 /* VFE */ 1854 iommu-ctx@3000 { 1855 compatible = "qcom,msm-iommu-v1-sec"; 1856 reg = <0x3000 0x1000>; 1857 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1858 }; 1859 1860 /* MDP_0 */ 1861 iommu-ctx@4000 { 1862 compatible = "qcom,msm-iommu-v1-ns"; 1863 reg = <0x4000 0x1000>; 1864 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1865 }; 1866 1867 /* VENUS_NS */ 1868 iommu-ctx@5000 { 1869 compatible = "qcom,msm-iommu-v1-sec"; 1870 reg = <0x5000 0x1000>; 1871 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1872 }; 1873 }; 1874 1875 gpu_iommu: iommu@1f08000 { 1876 #address-cells = <1>; 1877 #size-cells = <1>; 1878 #iommu-cells = <1>; 1879 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1880 ranges = <0 0x01f08000 0x10000>; 1881 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1882 <&gcc GCC_GFX_TCU_CLK>; 1883 clock-names = "iface", "bus"; 1884 qcom,iommu-secure-id = <18>; 1885 1886 /* GFX3D_USER */ 1887 iommu-ctx@1000 { 1888 compatible = "qcom,msm-iommu-v1-ns"; 1889 reg = <0x1000 0x1000>; 1890 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1891 }; 1892 1893 /* GFX3D_PRIV */ 1894 iommu-ctx@2000 { 1895 compatible = "qcom,msm-iommu-v1-ns"; 1896 reg = <0x2000 0x1000>; 1897 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1898 }; 1899 }; 1900 1901 spmi_bus: spmi@200f000 { 1902 compatible = "qcom,spmi-pmic-arb"; 1903 reg = <0x0200f000 0x001000>, 1904 <0x02400000 0x400000>, 1905 <0x02c00000 0x400000>, 1906 <0x03800000 0x200000>, 1907 <0x0200a000 0x002100>; 1908 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1909 interrupt-names = "periph_irq"; 1910 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1911 qcom,ee = <0>; 1912 qcom,channel = <0>; 1913 #address-cells = <2>; 1914 #size-cells = <0>; 1915 interrupt-controller; 1916 #interrupt-cells = <4>; 1917 }; 1918 1919 bam_dmux_dma: dma-controller@4044000 { 1920 compatible = "qcom,bam-v1.7.0"; 1921 reg = <0x04044000 0x19000>; 1922 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1923 #dma-cells = <1>; 1924 qcom,ee = <0>; 1925 1926 num-channels = <6>; 1927 qcom,num-ees = <1>; 1928 qcom,powered-remotely; 1929 1930 status = "disabled"; 1931 }; 1932 1933 mpss: remoteproc@4080000 { 1934 compatible = "qcom,msm8916-mss-pil"; 1935 reg = <0x04080000 0x100>, 1936 <0x04020000 0x040>; 1937 1938 reg-names = "qdsp6", "rmb"; 1939 1940 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1941 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1942 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1943 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1944 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1945 interrupt-names = "wdog", "fatal", "ready", 1946 "handover", "stop-ack"; 1947 1948 power-domains = <&rpmpd MSM8916_VDDCX>, 1949 <&rpmpd MSM8916_VDDMX>; 1950 power-domain-names = "cx", "mx"; 1951 1952 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1953 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1954 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1955 <&xo_board>; 1956 clock-names = "iface", "bus", "mem", "xo"; 1957 1958 qcom,smem-states = <&hexagon_smp2p_out 0>; 1959 qcom,smem-state-names = "stop"; 1960 1961 resets = <&scm 0>; 1962 reset-names = "mss_restart"; 1963 1964 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1965 1966 status = "disabled"; 1967 1968 mba { 1969 memory-region = <&mba_mem>; 1970 }; 1971 1972 mpss { 1973 memory-region = <&mpss_mem>; 1974 }; 1975 1976 bam_dmux: bam-dmux { 1977 compatible = "qcom,bam-dmux"; 1978 1979 interrupt-parent = <&hexagon_smsm>; 1980 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1981 interrupt-names = "pc", "pc-ack"; 1982 1983 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1984 qcom,smem-state-names = "pc", "pc-ack"; 1985 1986 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1987 dma-names = "tx", "rx"; 1988 1989 status = "disabled"; 1990 }; 1991 1992 smd-edge { 1993 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1994 1995 qcom,smd-edge = <0>; 1996 mboxes = <&apcs 12>; 1997 qcom,remote-pid = <1>; 1998 1999 label = "hexagon"; 2000 2001 apr: apr { 2002 compatible = "qcom,apr-v2"; 2003 qcom,smd-channels = "apr_audio_svc"; 2004 qcom,domain = <APR_DOMAIN_ADSP>; 2005 #address-cells = <1>; 2006 #size-cells = <0>; 2007 status = "disabled"; 2008 2009 q6core: service@3 { 2010 compatible = "qcom,q6core"; 2011 reg = <APR_SVC_ADSP_CORE>; 2012 }; 2013 2014 q6afe: service@4 { 2015 compatible = "qcom,q6afe"; 2016 reg = <APR_SVC_AFE>; 2017 2018 q6afedai: dais { 2019 compatible = "qcom,q6afe-dais"; 2020 #address-cells = <1>; 2021 #size-cells = <0>; 2022 #sound-dai-cells = <1>; 2023 }; 2024 }; 2025 2026 q6asm: service@7 { 2027 compatible = "qcom,q6asm"; 2028 reg = <APR_SVC_ASM>; 2029 2030 q6asmdai: dais { 2031 compatible = "qcom,q6asm-dais"; 2032 #address-cells = <1>; 2033 #size-cells = <0>; 2034 #sound-dai-cells = <1>; 2035 }; 2036 }; 2037 2038 q6adm: service@8 { 2039 compatible = "qcom,q6adm"; 2040 reg = <APR_SVC_ADM>; 2041 2042 q6routing: routing { 2043 compatible = "qcom,q6adm-routing"; 2044 #sound-dai-cells = <0>; 2045 }; 2046 }; 2047 }; 2048 2049 fastrpc { 2050 compatible = "qcom,fastrpc"; 2051 qcom,smd-channels = "fastrpcsmd-apps-dsp"; 2052 label = "adsp"; 2053 qcom,non-secure-domain; 2054 2055 #address-cells = <1>; 2056 #size-cells = <0>; 2057 2058 cb@1 { 2059 compatible = "qcom,fastrpc-compute-cb"; 2060 reg = <1>; 2061 }; 2062 }; 2063 }; 2064 }; 2065 2066 sound: sound@7702000 { 2067 status = "disabled"; 2068 compatible = "qcom,apq8016-sbc-sndcard"; 2069 reg = <0x07702000 0x4>, <0x07702004 0x4>; 2070 reg-names = "mic-iomux", "spkr-iomux"; 2071 }; 2072 2073 lpass: audio-controller@7708000 { 2074 status = "disabled"; 2075 compatible = "qcom,apq8016-lpass-cpu"; 2076 2077 /* 2078 * Note: Unlike the name would suggest, the SEC_I2S_CLK 2079 * is actually only used by Tertiary MI2S while 2080 * Primary/Secondary MI2S both use the PRI_I2S_CLK. 2081 */ 2082 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 2083 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 2084 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 2085 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 2086 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, 2087 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 2088 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; 2089 2090 clock-names = "ahbix-clk", 2091 "mi2s-bit-clk0", 2092 "mi2s-bit-clk1", 2093 "mi2s-bit-clk2", 2094 "mi2s-bit-clk3", 2095 "pcnoc-mport-clk", 2096 "pcnoc-sway-clk"; 2097 #sound-dai-cells = <1>; 2098 2099 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2100 interrupt-names = "lpass-irq-lpaif"; 2101 reg = <0x07708000 0x10000>; 2102 reg-names = "lpass-lpaif"; 2103 2104 #address-cells = <1>; 2105 #size-cells = <0>; 2106 }; 2107 2108 lpass_codec: audio-codec@771c000 { 2109 compatible = "qcom,msm8916-wcd-digital-codec"; 2110 reg = <0x0771c000 0x400>; 2111 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 2112 <&gcc GCC_CODEC_DIGCODEC_CLK>; 2113 clock-names = "ahbix-clk", "mclk"; 2114 #sound-dai-cells = <1>; 2115 status = "disabled"; 2116 }; 2117 2118 sdhc_1: mmc@7824900 { 2119 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 2120 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 2121 reg-names = "hc", "core"; 2122 2123 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2125 interrupt-names = "hc_irq", "pwr_irq"; 2126 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 2127 <&gcc GCC_SDCC1_APPS_CLK>, 2128 <&xo_board>; 2129 clock-names = "iface", "core", "xo"; 2130 resets = <&gcc GCC_SDCC1_BCR>; 2131 pinctrl-0 = <&sdc1_default>; 2132 pinctrl-1 = <&sdc1_sleep>; 2133 pinctrl-names = "default", "sleep"; 2134 mmc-ddr-1_8v; 2135 bus-width = <8>; 2136 non-removable; 2137 status = "disabled"; 2138 }; 2139 2140 sdhc_2: mmc@7864900 { 2141 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 2142 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 2143 reg-names = "hc", "core"; 2144 2145 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2147 interrupt-names = "hc_irq", "pwr_irq"; 2148 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2149 <&gcc GCC_SDCC2_APPS_CLK>, 2150 <&xo_board>; 2151 clock-names = "iface", "core", "xo"; 2152 resets = <&gcc GCC_SDCC2_BCR>; 2153 pinctrl-0 = <&sdc2_default>; 2154 pinctrl-1 = <&sdc2_sleep>; 2155 pinctrl-names = "default", "sleep"; 2156 bus-width = <4>; 2157 status = "disabled"; 2158 }; 2159 2160 blsp_dma: dma-controller@7884000 { 2161 compatible = "qcom,bam-v1.7.0"; 2162 reg = <0x07884000 0x23000>; 2163 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2164 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2165 clock-names = "bam_clk"; 2166 #dma-cells = <1>; 2167 qcom,ee = <0>; 2168 qcom,controlled-remotely; 2169 }; 2170 2171 blsp_uart1: serial@78af000 { 2172 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2173 reg = <0x078af000 0x200>; 2174 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 2175 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 2176 clock-names = "core", "iface"; 2177 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 2178 dma-names = "tx", "rx"; 2179 status = "disabled"; 2180 }; 2181 2182 blsp_uart2: serial@78b0000 { 2183 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2184 reg = <0x078b0000 0x200>; 2185 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2186 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 2187 clock-names = "core", "iface"; 2188 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 2189 dma-names = "tx", "rx"; 2190 status = "disabled"; 2191 }; 2192 2193 blsp_i2c1: i2c@78b5000 { 2194 compatible = "qcom,i2c-qup-v2.2.1"; 2195 reg = <0x078b5000 0x500>; 2196 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2197 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2198 <&gcc GCC_BLSP1_AHB_CLK>; 2199 clock-names = "core", "iface"; 2200 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 2201 dma-names = "tx", "rx"; 2202 pinctrl-names = "default", "sleep"; 2203 pinctrl-0 = <&blsp_i2c1_default>; 2204 pinctrl-1 = <&blsp_i2c1_sleep>; 2205 #address-cells = <1>; 2206 #size-cells = <0>; 2207 status = "disabled"; 2208 }; 2209 2210 blsp_spi1: spi@78b5000 { 2211 compatible = "qcom,spi-qup-v2.2.1"; 2212 reg = <0x078b5000 0x500>; 2213 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2214 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2215 <&gcc GCC_BLSP1_AHB_CLK>; 2216 clock-names = "core", "iface"; 2217 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 2218 dma-names = "tx", "rx"; 2219 pinctrl-names = "default", "sleep"; 2220 pinctrl-0 = <&blsp_spi1_default>; 2221 pinctrl-1 = <&blsp_spi1_sleep>; 2222 #address-cells = <1>; 2223 #size-cells = <0>; 2224 status = "disabled"; 2225 }; 2226 2227 blsp_i2c2: i2c@78b6000 { 2228 compatible = "qcom,i2c-qup-v2.2.1"; 2229 reg = <0x078b6000 0x500>; 2230 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2231 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2232 <&gcc GCC_BLSP1_AHB_CLK>; 2233 clock-names = "core", "iface"; 2234 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 2235 dma-names = "tx", "rx"; 2236 pinctrl-names = "default", "sleep"; 2237 pinctrl-0 = <&blsp_i2c2_default>; 2238 pinctrl-1 = <&blsp_i2c2_sleep>; 2239 #address-cells = <1>; 2240 #size-cells = <0>; 2241 status = "disabled"; 2242 }; 2243 2244 blsp_spi2: spi@78b6000 { 2245 compatible = "qcom,spi-qup-v2.2.1"; 2246 reg = <0x078b6000 0x500>; 2247 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2248 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 2249 <&gcc GCC_BLSP1_AHB_CLK>; 2250 clock-names = "core", "iface"; 2251 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 2252 dma-names = "tx", "rx"; 2253 pinctrl-names = "default", "sleep"; 2254 pinctrl-0 = <&blsp_spi2_default>; 2255 pinctrl-1 = <&blsp_spi2_sleep>; 2256 #address-cells = <1>; 2257 #size-cells = <0>; 2258 status = "disabled"; 2259 }; 2260 2261 blsp_i2c3: i2c@78b7000 { 2262 compatible = "qcom,i2c-qup-v2.2.1"; 2263 reg = <0x078b7000 0x500>; 2264 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2265 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2266 <&gcc GCC_BLSP1_AHB_CLK>; 2267 clock-names = "core", "iface"; 2268 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 2269 dma-names = "tx", "rx"; 2270 pinctrl-names = "default", "sleep"; 2271 pinctrl-0 = <&blsp_i2c3_default>; 2272 pinctrl-1 = <&blsp_i2c3_sleep>; 2273 #address-cells = <1>; 2274 #size-cells = <0>; 2275 status = "disabled"; 2276 }; 2277 2278 blsp_spi3: spi@78b7000 { 2279 compatible = "qcom,spi-qup-v2.2.1"; 2280 reg = <0x078b7000 0x500>; 2281 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2282 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 2283 <&gcc GCC_BLSP1_AHB_CLK>; 2284 clock-names = "core", "iface"; 2285 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 2286 dma-names = "tx", "rx"; 2287 pinctrl-names = "default", "sleep"; 2288 pinctrl-0 = <&blsp_spi3_default>; 2289 pinctrl-1 = <&blsp_spi3_sleep>; 2290 #address-cells = <1>; 2291 #size-cells = <0>; 2292 status = "disabled"; 2293 }; 2294 2295 blsp_i2c4: i2c@78b8000 { 2296 compatible = "qcom,i2c-qup-v2.2.1"; 2297 reg = <0x078b8000 0x500>; 2298 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2299 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2300 <&gcc GCC_BLSP1_AHB_CLK>; 2301 clock-names = "core", "iface"; 2302 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 2303 dma-names = "tx", "rx"; 2304 pinctrl-names = "default", "sleep"; 2305 pinctrl-0 = <&blsp_i2c4_default>; 2306 pinctrl-1 = <&blsp_i2c4_sleep>; 2307 #address-cells = <1>; 2308 #size-cells = <0>; 2309 status = "disabled"; 2310 }; 2311 2312 blsp_spi4: spi@78b8000 { 2313 compatible = "qcom,spi-qup-v2.2.1"; 2314 reg = <0x078b8000 0x500>; 2315 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2316 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 2317 <&gcc GCC_BLSP1_AHB_CLK>; 2318 clock-names = "core", "iface"; 2319 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 2320 dma-names = "tx", "rx"; 2321 pinctrl-names = "default", "sleep"; 2322 pinctrl-0 = <&blsp_spi4_default>; 2323 pinctrl-1 = <&blsp_spi4_sleep>; 2324 #address-cells = <1>; 2325 #size-cells = <0>; 2326 status = "disabled"; 2327 }; 2328 2329 blsp_i2c5: i2c@78b9000 { 2330 compatible = "qcom,i2c-qup-v2.2.1"; 2331 reg = <0x078b9000 0x500>; 2332 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2333 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2334 <&gcc GCC_BLSP1_AHB_CLK>; 2335 clock-names = "core", "iface"; 2336 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 2337 dma-names = "tx", "rx"; 2338 pinctrl-names = "default", "sleep"; 2339 pinctrl-0 = <&blsp_i2c5_default>; 2340 pinctrl-1 = <&blsp_i2c5_sleep>; 2341 #address-cells = <1>; 2342 #size-cells = <0>; 2343 status = "disabled"; 2344 }; 2345 2346 blsp_spi5: spi@78b9000 { 2347 compatible = "qcom,spi-qup-v2.2.1"; 2348 reg = <0x078b9000 0x500>; 2349 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2350 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 2351 <&gcc GCC_BLSP1_AHB_CLK>; 2352 clock-names = "core", "iface"; 2353 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 2354 dma-names = "tx", "rx"; 2355 pinctrl-names = "default", "sleep"; 2356 pinctrl-0 = <&blsp_spi5_default>; 2357 pinctrl-1 = <&blsp_spi5_sleep>; 2358 #address-cells = <1>; 2359 #size-cells = <0>; 2360 status = "disabled"; 2361 }; 2362 2363 blsp_i2c6: i2c@78ba000 { 2364 compatible = "qcom,i2c-qup-v2.2.1"; 2365 reg = <0x078ba000 0x500>; 2366 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2367 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2368 <&gcc GCC_BLSP1_AHB_CLK>; 2369 clock-names = "core", "iface"; 2370 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 2371 dma-names = "tx", "rx"; 2372 pinctrl-names = "default", "sleep"; 2373 pinctrl-0 = <&blsp_i2c6_default>; 2374 pinctrl-1 = <&blsp_i2c6_sleep>; 2375 #address-cells = <1>; 2376 #size-cells = <0>; 2377 status = "disabled"; 2378 }; 2379 2380 blsp_spi6: spi@78ba000 { 2381 compatible = "qcom,spi-qup-v2.2.1"; 2382 reg = <0x078ba000 0x500>; 2383 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2384 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 2385 <&gcc GCC_BLSP1_AHB_CLK>; 2386 clock-names = "core", "iface"; 2387 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 2388 dma-names = "tx", "rx"; 2389 pinctrl-names = "default", "sleep"; 2390 pinctrl-0 = <&blsp_spi6_default>; 2391 pinctrl-1 = <&blsp_spi6_sleep>; 2392 #address-cells = <1>; 2393 #size-cells = <0>; 2394 status = "disabled"; 2395 }; 2396 2397 usb: usb@78d9000 { 2398 compatible = "qcom,ci-hdrc"; 2399 reg = <0x078d9000 0x200>, 2400 <0x078d9200 0x200>; 2401 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2403 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 2404 <&gcc GCC_USB_HS_SYSTEM_CLK>; 2405 clock-names = "iface", "core"; 2406 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 2407 assigned-clock-rates = <80000000>; 2408 resets = <&gcc GCC_USB_HS_BCR>; 2409 reset-names = "core"; 2410 phy_type = "ulpi"; 2411 dr_mode = "otg"; 2412 hnp-disable; 2413 srp-disable; 2414 adp-disable; 2415 ahb-burst-config = <0>; 2416 phy-names = "usb-phy"; 2417 phys = <&usb_hs_phy>; 2418 status = "disabled"; 2419 #reset-cells = <1>; 2420 2421 ulpi { 2422 usb_hs_phy: phy { 2423 compatible = "qcom,usb-hs-phy-msm8916", 2424 "qcom,usb-hs-phy"; 2425 #phy-cells = <0>; 2426 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 2427 clock-names = "ref", "sleep"; 2428 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 2429 reset-names = "phy", "por"; 2430 qcom,init-seq = /bits/ 8 <0x0 0x44>, 2431 <0x1 0x6b>, 2432 <0x2 0x24>, 2433 <0x3 0x13>; 2434 }; 2435 }; 2436 }; 2437 2438 wcnss: remoteproc@a204000 { 2439 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 2440 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 2441 reg-names = "ccu", "dxe", "pmu"; 2442 2443 memory-region = <&wcnss_mem>; 2444 2445 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 2446 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2447 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2448 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2449 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2450 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2451 2452 power-domains = <&rpmpd MSM8916_VDDCX>, 2453 <&rpmpd MSM8916_VDDMX>; 2454 power-domain-names = "cx", "mx"; 2455 2456 qcom,smem-states = <&wcnss_smp2p_out 0>; 2457 qcom,smem-state-names = "stop"; 2458 2459 pinctrl-names = "default"; 2460 pinctrl-0 = <&wcss_wlan_default>; 2461 2462 status = "disabled"; 2463 2464 wcnss_iris: iris { 2465 /* Separate chip, compatible is board-specific */ 2466 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 2467 clock-names = "xo"; 2468 }; 2469 2470 smd-edge { 2471 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 2472 2473 mboxes = <&apcs 17>; 2474 qcom,smd-edge = <6>; 2475 qcom,remote-pid = <4>; 2476 2477 label = "pronto"; 2478 2479 wcnss_ctrl: wcnss { 2480 compatible = "qcom,wcnss"; 2481 qcom,smd-channels = "WCNSS_CTRL"; 2482 2483 qcom,mmio = <&wcnss>; 2484 2485 wcnss_bt: bluetooth { 2486 compatible = "qcom,wcnss-bt"; 2487 }; 2488 2489 wcnss_wifi: wifi { 2490 compatible = "qcom,wcnss-wlan"; 2491 2492 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2494 interrupt-names = "tx", "rx"; 2495 2496 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 2497 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 2498 }; 2499 }; 2500 }; 2501 }; 2502 2503 intc: interrupt-controller@b000000 { 2504 compatible = "qcom,msm-qgic2"; 2505 interrupt-controller; 2506 #interrupt-cells = <3>; 2507 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 2508 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 2509 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 2510 }; 2511 2512 apcs: mailbox@b011000 { 2513 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 2514 reg = <0x0b011000 0x1000>; 2515 #mbox-cells = <1>; 2516 clocks = <&a53pll>, <&gcc GPLL0_VOTE>; 2517 clock-names = "pll", "aux"; 2518 #clock-cells = <0>; 2519 }; 2520 2521 a53pll: clock@b016000 { 2522 compatible = "qcom,msm8916-a53pll"; 2523 reg = <0x0b016000 0x40>; 2524 #clock-cells = <0>; 2525 clocks = <&xo_board>; 2526 clock-names = "xo"; 2527 }; 2528 2529 timer@b020000 { 2530 #address-cells = <1>; 2531 #size-cells = <1>; 2532 ranges; 2533 compatible = "arm,armv7-timer-mem"; 2534 reg = <0x0b020000 0x1000>; 2535 clock-frequency = <19200000>; 2536 2537 frame@b021000 { 2538 frame-number = <0>; 2539 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2540 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2541 reg = <0x0b021000 0x1000>, 2542 <0x0b022000 0x1000>; 2543 }; 2544 2545 frame@b023000 { 2546 frame-number = <1>; 2547 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2548 reg = <0x0b023000 0x1000>; 2549 status = "disabled"; 2550 }; 2551 2552 frame@b024000 { 2553 frame-number = <2>; 2554 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2555 reg = <0x0b024000 0x1000>; 2556 status = "disabled"; 2557 }; 2558 2559 frame@b025000 { 2560 frame-number = <3>; 2561 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2562 reg = <0x0b025000 0x1000>; 2563 status = "disabled"; 2564 }; 2565 2566 frame@b026000 { 2567 frame-number = <4>; 2568 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2569 reg = <0x0b026000 0x1000>; 2570 status = "disabled"; 2571 }; 2572 2573 frame@b027000 { 2574 frame-number = <5>; 2575 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2576 reg = <0x0b027000 0x1000>; 2577 status = "disabled"; 2578 }; 2579 2580 frame@b028000 { 2581 frame-number = <6>; 2582 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2583 reg = <0x0b028000 0x1000>; 2584 status = "disabled"; 2585 }; 2586 }; 2587 2588 cpu0_acc: power-manager@b088000 { 2589 compatible = "qcom,msm8916-acc"; 2590 reg = <0x0b088000 0x1000>; 2591 status = "reserved"; /* Controlled by PSCI firmware */ 2592 }; 2593 2594 cpu0_saw: power-manager@b089000 { 2595 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2596 reg = <0x0b089000 0x1000>; 2597 status = "reserved"; /* Controlled by PSCI firmware */ 2598 }; 2599 2600 cpu1_acc: power-manager@b098000 { 2601 compatible = "qcom,msm8916-acc"; 2602 reg = <0x0b098000 0x1000>; 2603 status = "reserved"; /* Controlled by PSCI firmware */ 2604 }; 2605 2606 cpu1_saw: power-manager@b099000 { 2607 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2608 reg = <0x0b099000 0x1000>; 2609 status = "reserved"; /* Controlled by PSCI firmware */ 2610 }; 2611 2612 cpu2_acc: power-manager@b0a8000 { 2613 compatible = "qcom,msm8916-acc"; 2614 reg = <0x0b0a8000 0x1000>; 2615 status = "reserved"; /* Controlled by PSCI firmware */ 2616 }; 2617 2618 cpu2_saw: power-manager@b0a9000 { 2619 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2620 reg = <0x0b0a9000 0x1000>; 2621 status = "reserved"; /* Controlled by PSCI firmware */ 2622 }; 2623 2624 cpu3_acc: power-manager@b0b8000 { 2625 compatible = "qcom,msm8916-acc"; 2626 reg = <0x0b0b8000 0x1000>; 2627 status = "reserved"; /* Controlled by PSCI firmware */ 2628 }; 2629 2630 cpu3_saw: power-manager@b0b9000 { 2631 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2632 reg = <0x0b0b9000 0x1000>; 2633 status = "reserved"; /* Controlled by PSCI firmware */ 2634 }; 2635 }; 2636 2637 thermal-zones { 2638 cpu0-1-thermal { 2639 polling-delay-passive = <250>; 2640 2641 thermal-sensors = <&tsens 5>; 2642 2643 trips { 2644 cpu0_1_alert0: trip-point0 { 2645 temperature = <75000>; 2646 hysteresis = <2000>; 2647 type = "passive"; 2648 }; 2649 cpu0_1_crit: cpu-crit { 2650 temperature = <110000>; 2651 hysteresis = <2000>; 2652 type = "critical"; 2653 }; 2654 }; 2655 2656 cooling-maps { 2657 map0 { 2658 trip = <&cpu0_1_alert0>; 2659 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2660 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2661 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2662 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2663 }; 2664 }; 2665 }; 2666 2667 cpu2-3-thermal { 2668 polling-delay-passive = <250>; 2669 2670 thermal-sensors = <&tsens 4>; 2671 2672 trips { 2673 cpu2_3_alert0: trip-point0 { 2674 temperature = <75000>; 2675 hysteresis = <2000>; 2676 type = "passive"; 2677 }; 2678 cpu2_3_crit: cpu-crit { 2679 temperature = <110000>; 2680 hysteresis = <2000>; 2681 type = "critical"; 2682 }; 2683 }; 2684 2685 cooling-maps { 2686 map0 { 2687 trip = <&cpu2_3_alert0>; 2688 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2689 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2690 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2691 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2692 }; 2693 }; 2694 }; 2695 2696 gpu-thermal { 2697 polling-delay-passive = <250>; 2698 2699 thermal-sensors = <&tsens 2>; 2700 2701 cooling-maps { 2702 map0 { 2703 trip = <&gpu_alert0>; 2704 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2705 }; 2706 }; 2707 2708 trips { 2709 gpu_alert0: trip-point0 { 2710 temperature = <75000>; 2711 hysteresis = <2000>; 2712 type = "passive"; 2713 }; 2714 gpu_crit: gpu-crit { 2715 temperature = <95000>; 2716 hysteresis = <2000>; 2717 type = "critical"; 2718 }; 2719 }; 2720 }; 2721 2722 camera-thermal { 2723 polling-delay-passive = <250>; 2724 2725 thermal-sensors = <&tsens 1>; 2726 2727 trips { 2728 cam_alert0: trip-point0 { 2729 temperature = <75000>; 2730 hysteresis = <2000>; 2731 type = "hot"; 2732 }; 2733 }; 2734 }; 2735 2736 modem-thermal { 2737 polling-delay-passive = <250>; 2738 2739 thermal-sensors = <&tsens 0>; 2740 2741 trips { 2742 modem_alert0: trip-point0 { 2743 temperature = <85000>; 2744 hysteresis = <2000>; 2745 type = "hot"; 2746 }; 2747 }; 2748 }; 2749 }; 2750 2751 timer { 2752 compatible = "arm,armv8-timer"; 2753 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2754 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2755 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2756 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2757 }; 2758}; 2759