1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/arm/coresight-cti-dt.h> 7#include <dt-bindings/clock/qcom,gcc-msm8916.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interconnect/qcom,msm8916.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/reset/qcom,gcc-msm8916.h> 13#include <dt-bindings/soc/qcom,apr.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* We expect the bootloader to fill in the reg */ 27 reg = <0 0x80000000 0 0>; 28 }; 29 30 reserved-memory { 31 #address-cells = <2>; 32 #size-cells = <2>; 33 ranges; 34 35 tz-apps@86000000 { 36 reg = <0x0 0x86000000 0x0 0x300000>; 37 no-map; 38 }; 39 40 smem@86300000 { 41 compatible = "qcom,smem"; 42 reg = <0x0 0x86300000 0x0 0x100000>; 43 no-map; 44 45 hwlocks = <&tcsr_mutex 3>; 46 qcom,rpm-msg-ram = <&rpm_msg_ram>; 47 }; 48 49 hypervisor@86400000 { 50 reg = <0x0 0x86400000 0x0 0x100000>; 51 no-map; 52 }; 53 54 tz@86500000 { 55 reg = <0x0 0x86500000 0x0 0x180000>; 56 no-map; 57 }; 58 59 reserved@86680000 { 60 reg = <0x0 0x86680000 0x0 0x80000>; 61 no-map; 62 }; 63 64 rmtfs@86700000 { 65 compatible = "qcom,rmtfs-mem"; 66 reg = <0x0 0x86700000 0x0 0xe0000>; 67 no-map; 68 69 qcom,client-id = <1>; 70 }; 71 72 rfsa@867e0000 { 73 reg = <0x0 0x867e0000 0x0 0x20000>; 74 no-map; 75 }; 76 77 mpss_mem: mpss@86800000 { 78 /* 79 * The memory region for the mpss firmware is generally 80 * relocatable and could be allocated dynamically. 81 * However, many firmware versions tend to fail when 82 * loaded to some special addresses, so it is hard to 83 * define reliable alloc-ranges. 84 * 85 * alignment = <0x0 0x400000>; 86 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 87 */ 88 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */ 89 no-map; 90 status = "disabled"; 91 }; 92 93 wcnss_mem: wcnss { 94 size = <0x0 0x600000>; 95 alignment = <0x0 0x100000>; 96 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 97 no-map; 98 status = "disabled"; 99 }; 100 101 venus_mem: venus { 102 size = <0x0 0x500000>; 103 alignment = <0x0 0x100000>; 104 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 105 no-map; 106 status = "disabled"; 107 }; 108 109 mba_mem: mba { 110 size = <0x0 0x100000>; 111 alignment = <0x0 0x100000>; 112 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 113 no-map; 114 status = "disabled"; 115 }; 116 }; 117 118 clocks { 119 xo_board: xo-board { 120 compatible = "fixed-clock"; 121 #clock-cells = <0>; 122 clock-frequency = <19200000>; 123 }; 124 125 sleep_clk: sleep-clk { 126 compatible = "fixed-clock"; 127 #clock-cells = <0>; 128 clock-frequency = <32768>; 129 }; 130 }; 131 132 cpus { 133 #address-cells = <1>; 134 #size-cells = <0>; 135 136 CPU0: cpu@0 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a53"; 139 reg = <0x0>; 140 next-level-cache = <&L2_0>; 141 enable-method = "psci"; 142 clocks = <&apcs>; 143 operating-points-v2 = <&cpu_opp_table>; 144 #cooling-cells = <2>; 145 power-domains = <&CPU_PD0>; 146 power-domain-names = "psci"; 147 qcom,acc = <&cpu0_acc>; 148 qcom,saw = <&cpu0_saw>; 149 }; 150 151 CPU1: cpu@1 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a53"; 154 reg = <0x1>; 155 next-level-cache = <&L2_0>; 156 enable-method = "psci"; 157 clocks = <&apcs>; 158 operating-points-v2 = <&cpu_opp_table>; 159 #cooling-cells = <2>; 160 power-domains = <&CPU_PD1>; 161 power-domain-names = "psci"; 162 qcom,acc = <&cpu1_acc>; 163 qcom,saw = <&cpu1_saw>; 164 }; 165 166 CPU2: cpu@2 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a53"; 169 reg = <0x2>; 170 next-level-cache = <&L2_0>; 171 enable-method = "psci"; 172 clocks = <&apcs>; 173 operating-points-v2 = <&cpu_opp_table>; 174 #cooling-cells = <2>; 175 power-domains = <&CPU_PD2>; 176 power-domain-names = "psci"; 177 qcom,acc = <&cpu2_acc>; 178 qcom,saw = <&cpu2_saw>; 179 }; 180 181 CPU3: cpu@3 { 182 device_type = "cpu"; 183 compatible = "arm,cortex-a53"; 184 reg = <0x3>; 185 next-level-cache = <&L2_0>; 186 enable-method = "psci"; 187 clocks = <&apcs>; 188 operating-points-v2 = <&cpu_opp_table>; 189 #cooling-cells = <2>; 190 power-domains = <&CPU_PD3>; 191 power-domain-names = "psci"; 192 qcom,acc = <&cpu3_acc>; 193 qcom,saw = <&cpu3_saw>; 194 }; 195 196 L2_0: l2-cache { 197 compatible = "cache"; 198 cache-level = <2>; 199 cache-unified; 200 }; 201 202 idle-states { 203 entry-method = "psci"; 204 205 CPU_SLEEP_0: cpu-sleep-0 { 206 compatible = "arm,idle-state"; 207 idle-state-name = "standalone-power-collapse"; 208 arm,psci-suspend-param = <0x40000002>; 209 entry-latency-us = <130>; 210 exit-latency-us = <150>; 211 min-residency-us = <2000>; 212 local-timer-stop; 213 }; 214 }; 215 216 domain-idle-states { 217 218 CLUSTER_RET: cluster-retention { 219 compatible = "domain-idle-state"; 220 arm,psci-suspend-param = <0x41000012>; 221 entry-latency-us = <500>; 222 exit-latency-us = <500>; 223 min-residency-us = <2000>; 224 }; 225 226 CLUSTER_PWRDN: cluster-gdhs { 227 compatible = "domain-idle-state"; 228 arm,psci-suspend-param = <0x41000032>; 229 entry-latency-us = <2000>; 230 exit-latency-us = <2000>; 231 min-residency-us = <6000>; 232 }; 233 }; 234 }; 235 236 cpu_opp_table: opp-table-cpu { 237 compatible = "operating-points-v2"; 238 opp-shared; 239 240 opp-200000000 { 241 opp-hz = /bits/ 64 <200000000>; 242 }; 243 opp-400000000 { 244 opp-hz = /bits/ 64 <400000000>; 245 }; 246 opp-800000000 { 247 opp-hz = /bits/ 64 <800000000>; 248 }; 249 opp-998400000 { 250 opp-hz = /bits/ 64 <998400000>; 251 }; 252 }; 253 254 firmware { 255 scm: scm { 256 compatible = "qcom,scm-msm8916", "qcom,scm"; 257 clocks = <&gcc GCC_CRYPTO_CLK>, 258 <&gcc GCC_CRYPTO_AXI_CLK>, 259 <&gcc GCC_CRYPTO_AHB_CLK>; 260 clock-names = "core", "bus", "iface"; 261 #reset-cells = <1>; 262 263 qcom,dload-mode = <&tcsr 0x6100>; 264 }; 265 }; 266 267 pmu { 268 compatible = "arm,cortex-a53-pmu"; 269 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 270 }; 271 272 psci { 273 compatible = "arm,psci-1.0"; 274 method = "smc"; 275 276 CPU_PD0: power-domain-cpu0 { 277 #power-domain-cells = <0>; 278 power-domains = <&CLUSTER_PD>; 279 domain-idle-states = <&CPU_SLEEP_0>; 280 }; 281 282 CPU_PD1: power-domain-cpu1 { 283 #power-domain-cells = <0>; 284 power-domains = <&CLUSTER_PD>; 285 domain-idle-states = <&CPU_SLEEP_0>; 286 }; 287 288 CPU_PD2: power-domain-cpu2 { 289 #power-domain-cells = <0>; 290 power-domains = <&CLUSTER_PD>; 291 domain-idle-states = <&CPU_SLEEP_0>; 292 }; 293 294 CPU_PD3: power-domain-cpu3 { 295 #power-domain-cells = <0>; 296 power-domains = <&CLUSTER_PD>; 297 domain-idle-states = <&CPU_SLEEP_0>; 298 }; 299 300 CLUSTER_PD: power-domain-cluster { 301 #power-domain-cells = <0>; 302 domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>; 303 }; 304 }; 305 306 rpm: remoteproc { 307 compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc"; 308 309 smd-edge { 310 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 311 qcom,ipc = <&apcs 8 0>; 312 qcom,smd-edge = <15>; 313 314 rpm_requests: rpm-requests { 315 compatible = "qcom,rpm-msm8916"; 316 qcom,smd-channels = "rpm_requests"; 317 318 rpmcc: clock-controller { 319 compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; 320 #clock-cells = <1>; 321 clocks = <&xo_board>; 322 clock-names = "xo"; 323 }; 324 325 rpmpd: power-controller { 326 compatible = "qcom,msm8916-rpmpd"; 327 #power-domain-cells = <1>; 328 operating-points-v2 = <&rpmpd_opp_table>; 329 330 rpmpd_opp_table: opp-table { 331 compatible = "operating-points-v2"; 332 333 rpmpd_opp_ret: opp1 { 334 opp-level = <1>; 335 }; 336 rpmpd_opp_svs_krait: opp2 { 337 opp-level = <2>; 338 }; 339 rpmpd_opp_svs_soc: opp3 { 340 opp-level = <3>; 341 }; 342 rpmpd_opp_nom: opp4 { 343 opp-level = <4>; 344 }; 345 rpmpd_opp_turbo: opp5 { 346 opp-level = <5>; 347 }; 348 rpmpd_opp_super_turbo: opp6 { 349 opp-level = <6>; 350 }; 351 }; 352 }; 353 }; 354 }; 355 }; 356 357 smp2p-hexagon { 358 compatible = "qcom,smp2p"; 359 qcom,smem = <435>, <428>; 360 361 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 362 363 qcom,ipc = <&apcs 8 14>; 364 365 qcom,local-pid = <0>; 366 qcom,remote-pid = <1>; 367 368 hexagon_smp2p_out: master-kernel { 369 qcom,entry-name = "master-kernel"; 370 371 #qcom,smem-state-cells = <1>; 372 }; 373 374 hexagon_smp2p_in: slave-kernel { 375 qcom,entry-name = "slave-kernel"; 376 377 interrupt-controller; 378 #interrupt-cells = <2>; 379 }; 380 }; 381 382 smp2p-wcnss { 383 compatible = "qcom,smp2p"; 384 qcom,smem = <451>, <431>; 385 386 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 387 388 qcom,ipc = <&apcs 8 18>; 389 390 qcom,local-pid = <0>; 391 qcom,remote-pid = <4>; 392 393 wcnss_smp2p_out: master-kernel { 394 qcom,entry-name = "master-kernel"; 395 396 #qcom,smem-state-cells = <1>; 397 }; 398 399 wcnss_smp2p_in: slave-kernel { 400 qcom,entry-name = "slave-kernel"; 401 402 interrupt-controller; 403 #interrupt-cells = <2>; 404 }; 405 }; 406 407 smsm { 408 compatible = "qcom,smsm"; 409 410 #address-cells = <1>; 411 #size-cells = <0>; 412 413 qcom,ipc-1 = <&apcs 8 13>; 414 qcom,ipc-3 = <&apcs 8 19>; 415 416 apps_smsm: apps@0 { 417 reg = <0>; 418 419 #qcom,smem-state-cells = <1>; 420 }; 421 422 hexagon_smsm: hexagon@1 { 423 reg = <1>; 424 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 425 426 interrupt-controller; 427 #interrupt-cells = <2>; 428 }; 429 430 wcnss_smsm: wcnss@6 { 431 reg = <6>; 432 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 433 434 interrupt-controller; 435 #interrupt-cells = <2>; 436 }; 437 }; 438 439 soc: soc@0 { 440 #address-cells = <1>; 441 #size-cells = <1>; 442 ranges = <0 0 0 0xffffffff>; 443 compatible = "simple-bus"; 444 445 rng@22000 { 446 compatible = "qcom,prng"; 447 reg = <0x00022000 0x200>; 448 clocks = <&gcc GCC_PRNG_AHB_CLK>; 449 clock-names = "core"; 450 }; 451 452 restart@4ab000 { 453 compatible = "qcom,pshold"; 454 reg = <0x004ab000 0x4>; 455 }; 456 457 qfprom: qfprom@5c000 { 458 compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 459 reg = <0x0005c000 0x1000>; 460 #address-cells = <1>; 461 #size-cells = <1>; 462 463 tsens_base1: base1@d0 { 464 reg = <0xd0 0x1>; 465 bits = <0 7>; 466 }; 467 468 tsens_s0_p1: s0-p1@d0 { 469 reg = <0xd0 0x2>; 470 bits = <7 5>; 471 }; 472 473 tsens_s0_p2: s0-p2@d1 { 474 reg = <0xd1 0x2>; 475 bits = <4 5>; 476 }; 477 478 tsens_s1_p1: s1-p1@d2 { 479 reg = <0xd2 0x1>; 480 bits = <1 5>; 481 }; 482 tsens_s1_p2: s1-p2@d2 { 483 reg = <0xd2 0x2>; 484 bits = <6 5>; 485 }; 486 tsens_s2_p1: s2-p1@d3 { 487 reg = <0xd3 0x1>; 488 bits = <3 5>; 489 }; 490 491 tsens_s2_p2: s2-p2@d4 { 492 reg = <0xd4 0x1>; 493 bits = <0 5>; 494 }; 495 496 // no tsens with hw_id 3 497 498 tsens_s4_p1: s4-p1@d4 { 499 reg = <0xd4 0x2>; 500 bits = <5 5>; 501 }; 502 503 tsens_s4_p2: s4-p2@d5 { 504 reg = <0xd5 0x1>; 505 bits = <2 5>; 506 }; 507 508 tsens_s5_p1: s5-p1@d5 { 509 reg = <0xd5 0x2>; 510 bits = <7 5>; 511 }; 512 513 tsens_s5_p2: s5-p2@d6 { 514 reg = <0xd6 0x2>; 515 bits = <4 5>; 516 }; 517 518 tsens_base2: base2@d7 { 519 reg = <0xd7 0x1>; 520 bits = <1 7>; 521 }; 522 523 tsens_mode: mode@ef { 524 reg = <0xef 0x1>; 525 bits = <5 3>; 526 }; 527 }; 528 529 rpm_msg_ram: sram@60000 { 530 compatible = "qcom,rpm-msg-ram"; 531 reg = <0x00060000 0x8000>; 532 }; 533 534 sram@290000 { 535 compatible = "qcom,msm8916-rpm-stats"; 536 reg = <0x00290000 0x10000>; 537 }; 538 539 bimc: interconnect@400000 { 540 compatible = "qcom,msm8916-bimc"; 541 reg = <0x00400000 0x62000>; 542 #interconnect-cells = <1>; 543 }; 544 545 tsens: thermal-sensor@4a9000 { 546 compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; 547 reg = <0x004a9000 0x1000>, /* TM */ 548 <0x004a8000 0x1000>; /* SROT */ 549 550 // no hw_id 3 551 nvmem-cells = <&tsens_mode>, 552 <&tsens_base1>, <&tsens_base2>, 553 <&tsens_s0_p1>, <&tsens_s0_p2>, 554 <&tsens_s1_p1>, <&tsens_s1_p2>, 555 <&tsens_s2_p1>, <&tsens_s2_p2>, 556 <&tsens_s4_p1>, <&tsens_s4_p2>, 557 <&tsens_s5_p1>, <&tsens_s5_p2>; 558 nvmem-cell-names = "mode", 559 "base1", "base2", 560 "s0_p1", "s0_p2", 561 "s1_p1", "s1_p2", 562 "s2_p1", "s2_p2", 563 "s4_p1", "s4_p2", 564 "s5_p1", "s5_p2"; 565 #qcom,sensors = <5>; 566 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 567 interrupt-names = "uplow"; 568 #thermal-sensor-cells = <1>; 569 }; 570 571 pcnoc: interconnect@500000 { 572 compatible = "qcom,msm8916-pcnoc"; 573 reg = <0x00500000 0x11000>; 574 #interconnect-cells = <1>; 575 }; 576 577 snoc: interconnect@580000 { 578 compatible = "qcom,msm8916-snoc"; 579 reg = <0x00580000 0x14000>; 580 #interconnect-cells = <1>; 581 }; 582 583 stm: stm@802000 { 584 compatible = "arm,coresight-stm", "arm,primecell"; 585 reg = <0x00802000 0x1000>, 586 <0x09280000 0x180000>; 587 reg-names = "stm-base", "stm-stimulus-base"; 588 589 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 590 clock-names = "apb_pclk", "atclk"; 591 592 status = "disabled"; 593 594 out-ports { 595 port { 596 stm_out: endpoint { 597 remote-endpoint = <&funnel0_in7>; 598 }; 599 }; 600 }; 601 }; 602 603 /* System CTIs */ 604 /* CTI 0 - TMC connections */ 605 cti0: cti@810000 { 606 compatible = "arm,coresight-cti", "arm,primecell"; 607 reg = <0x00810000 0x1000>; 608 609 clocks = <&rpmcc RPM_QDSS_CLK>; 610 clock-names = "apb_pclk"; 611 612 status = "disabled"; 613 }; 614 615 /* CTI 1 - TPIU connections */ 616 cti1: cti@811000 { 617 compatible = "arm,coresight-cti", "arm,primecell"; 618 reg = <0x00811000 0x1000>; 619 620 clocks = <&rpmcc RPM_QDSS_CLK>; 621 clock-names = "apb_pclk"; 622 623 status = "disabled"; 624 }; 625 626 /* CTIs 2-11 - no information - not instantiated */ 627 628 tpiu: tpiu@820000 { 629 compatible = "arm,coresight-tpiu", "arm,primecell"; 630 reg = <0x00820000 0x1000>; 631 632 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 633 clock-names = "apb_pclk", "atclk"; 634 635 status = "disabled"; 636 637 in-ports { 638 port { 639 tpiu_in: endpoint { 640 remote-endpoint = <&replicator_out1>; 641 }; 642 }; 643 }; 644 }; 645 646 funnel0: funnel@821000 { 647 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 648 reg = <0x00821000 0x1000>; 649 650 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 651 clock-names = "apb_pclk", "atclk"; 652 653 status = "disabled"; 654 655 in-ports { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 659 /* 660 * Not described input ports: 661 * 0 - connected to Resource and Power Manger CPU ETM 662 * 1 - not-connected 663 * 2 - connected to Modem CPU ETM 664 * 3 - not-connected 665 * 5 - not-connected 666 * 6 - connected trought funnel to Wireless CPU ETM 667 * 7 - connected to STM component 668 */ 669 670 port@4 { 671 reg = <4>; 672 funnel0_in4: endpoint { 673 remote-endpoint = <&funnel1_out>; 674 }; 675 }; 676 677 port@7 { 678 reg = <7>; 679 funnel0_in7: endpoint { 680 remote-endpoint = <&stm_out>; 681 }; 682 }; 683 }; 684 685 out-ports { 686 port { 687 funnel0_out: endpoint { 688 remote-endpoint = <&etf_in>; 689 }; 690 }; 691 }; 692 }; 693 694 replicator: replicator@824000 { 695 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 696 reg = <0x00824000 0x1000>; 697 698 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 699 clock-names = "apb_pclk", "atclk"; 700 701 status = "disabled"; 702 703 out-ports { 704 #address-cells = <1>; 705 #size-cells = <0>; 706 707 port@0 { 708 reg = <0>; 709 replicator_out0: endpoint { 710 remote-endpoint = <&etr_in>; 711 }; 712 }; 713 port@1 { 714 reg = <1>; 715 replicator_out1: endpoint { 716 remote-endpoint = <&tpiu_in>; 717 }; 718 }; 719 }; 720 721 in-ports { 722 port { 723 replicator_in: endpoint { 724 remote-endpoint = <&etf_out>; 725 }; 726 }; 727 }; 728 }; 729 730 etf: etf@825000 { 731 compatible = "arm,coresight-tmc", "arm,primecell"; 732 reg = <0x00825000 0x1000>; 733 734 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 735 clock-names = "apb_pclk", "atclk"; 736 737 status = "disabled"; 738 739 in-ports { 740 port { 741 etf_in: endpoint { 742 remote-endpoint = <&funnel0_out>; 743 }; 744 }; 745 }; 746 747 out-ports { 748 port { 749 etf_out: endpoint { 750 remote-endpoint = <&replicator_in>; 751 }; 752 }; 753 }; 754 }; 755 756 etr: etr@826000 { 757 compatible = "arm,coresight-tmc", "arm,primecell"; 758 reg = <0x00826000 0x1000>; 759 760 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 761 clock-names = "apb_pclk", "atclk"; 762 763 status = "disabled"; 764 765 in-ports { 766 port { 767 etr_in: endpoint { 768 remote-endpoint = <&replicator_out0>; 769 }; 770 }; 771 }; 772 }; 773 774 funnel1: funnel@841000 { /* APSS funnel only 4 inputs are used */ 775 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 776 reg = <0x00841000 0x1000>; 777 778 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 779 clock-names = "apb_pclk", "atclk"; 780 781 status = "disabled"; 782 783 in-ports { 784 #address-cells = <1>; 785 #size-cells = <0>; 786 787 port@0 { 788 reg = <0>; 789 funnel1_in0: endpoint { 790 remote-endpoint = <&etm0_out>; 791 }; 792 }; 793 port@1 { 794 reg = <1>; 795 funnel1_in1: endpoint { 796 remote-endpoint = <&etm1_out>; 797 }; 798 }; 799 port@2 { 800 reg = <2>; 801 funnel1_in2: endpoint { 802 remote-endpoint = <&etm2_out>; 803 }; 804 }; 805 port@3 { 806 reg = <3>; 807 funnel1_in3: endpoint { 808 remote-endpoint = <&etm3_out>; 809 }; 810 }; 811 }; 812 813 out-ports { 814 port { 815 funnel1_out: endpoint { 816 remote-endpoint = <&funnel0_in4>; 817 }; 818 }; 819 }; 820 }; 821 822 debug0: debug@850000 { 823 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 824 reg = <0x00850000 0x1000>; 825 clocks = <&rpmcc RPM_QDSS_CLK>; 826 clock-names = "apb_pclk"; 827 cpu = <&CPU0>; 828 status = "disabled"; 829 }; 830 831 debug1: debug@852000 { 832 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 833 reg = <0x00852000 0x1000>; 834 clocks = <&rpmcc RPM_QDSS_CLK>; 835 clock-names = "apb_pclk"; 836 cpu = <&CPU1>; 837 status = "disabled"; 838 }; 839 840 debug2: debug@854000 { 841 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 842 reg = <0x00854000 0x1000>; 843 clocks = <&rpmcc RPM_QDSS_CLK>; 844 clock-names = "apb_pclk"; 845 cpu = <&CPU2>; 846 status = "disabled"; 847 }; 848 849 debug3: debug@856000 { 850 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 851 reg = <0x00856000 0x1000>; 852 clocks = <&rpmcc RPM_QDSS_CLK>; 853 clock-names = "apb_pclk"; 854 cpu = <&CPU3>; 855 status = "disabled"; 856 }; 857 858 /* Core CTIs; CTIs 12-15 */ 859 /* CTI - CPU-0 */ 860 cti12: cti@858000 { 861 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 862 "arm,primecell"; 863 reg = <0x00858000 0x1000>; 864 865 clocks = <&rpmcc RPM_QDSS_CLK>; 866 clock-names = "apb_pclk"; 867 868 cpu = <&CPU0>; 869 arm,cs-dev-assoc = <&etm0>; 870 871 status = "disabled"; 872 }; 873 874 /* CTI - CPU-1 */ 875 cti13: cti@859000 { 876 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 877 "arm,primecell"; 878 reg = <0x00859000 0x1000>; 879 880 clocks = <&rpmcc RPM_QDSS_CLK>; 881 clock-names = "apb_pclk"; 882 883 cpu = <&CPU1>; 884 arm,cs-dev-assoc = <&etm1>; 885 886 status = "disabled"; 887 }; 888 889 /* CTI - CPU-2 */ 890 cti14: cti@85a000 { 891 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 892 "arm,primecell"; 893 reg = <0x0085a000 0x1000>; 894 895 clocks = <&rpmcc RPM_QDSS_CLK>; 896 clock-names = "apb_pclk"; 897 898 cpu = <&CPU2>; 899 arm,cs-dev-assoc = <&etm2>; 900 901 status = "disabled"; 902 }; 903 904 /* CTI - CPU-3 */ 905 cti15: cti@85b000 { 906 compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", 907 "arm,primecell"; 908 reg = <0x0085b000 0x1000>; 909 910 clocks = <&rpmcc RPM_QDSS_CLK>; 911 clock-names = "apb_pclk"; 912 913 cpu = <&CPU3>; 914 arm,cs-dev-assoc = <&etm3>; 915 916 status = "disabled"; 917 }; 918 919 etm0: etm@85c000 { 920 compatible = "arm,coresight-etm4x", "arm,primecell"; 921 reg = <0x0085c000 0x1000>; 922 923 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 924 clock-names = "apb_pclk", "atclk"; 925 arm,coresight-loses-context-with-cpu; 926 927 cpu = <&CPU0>; 928 929 status = "disabled"; 930 931 out-ports { 932 port { 933 etm0_out: endpoint { 934 remote-endpoint = <&funnel1_in0>; 935 }; 936 }; 937 }; 938 }; 939 940 etm1: etm@85d000 { 941 compatible = "arm,coresight-etm4x", "arm,primecell"; 942 reg = <0x0085d000 0x1000>; 943 944 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 945 clock-names = "apb_pclk", "atclk"; 946 arm,coresight-loses-context-with-cpu; 947 948 cpu = <&CPU1>; 949 950 status = "disabled"; 951 952 out-ports { 953 port { 954 etm1_out: endpoint { 955 remote-endpoint = <&funnel1_in1>; 956 }; 957 }; 958 }; 959 }; 960 961 etm2: etm@85e000 { 962 compatible = "arm,coresight-etm4x", "arm,primecell"; 963 reg = <0x0085e000 0x1000>; 964 965 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 966 clock-names = "apb_pclk", "atclk"; 967 arm,coresight-loses-context-with-cpu; 968 969 cpu = <&CPU2>; 970 971 status = "disabled"; 972 973 out-ports { 974 port { 975 etm2_out: endpoint { 976 remote-endpoint = <&funnel1_in2>; 977 }; 978 }; 979 }; 980 }; 981 982 etm3: etm@85f000 { 983 compatible = "arm,coresight-etm4x", "arm,primecell"; 984 reg = <0x0085f000 0x1000>; 985 986 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; 987 clock-names = "apb_pclk", "atclk"; 988 arm,coresight-loses-context-with-cpu; 989 990 cpu = <&CPU3>; 991 992 status = "disabled"; 993 994 out-ports { 995 port { 996 etm3_out: endpoint { 997 remote-endpoint = <&funnel1_in3>; 998 }; 999 }; 1000 }; 1001 }; 1002 1003 tlmm: pinctrl@1000000 { 1004 compatible = "qcom,msm8916-pinctrl"; 1005 reg = <0x01000000 0x300000>; 1006 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1007 gpio-controller; 1008 gpio-ranges = <&tlmm 0 0 122>; 1009 #gpio-cells = <2>; 1010 interrupt-controller; 1011 #interrupt-cells = <2>; 1012 1013 blsp_i2c1_default: blsp-i2c1-default-state { 1014 pins = "gpio2", "gpio3"; 1015 function = "blsp_i2c1"; 1016 drive-strength = <2>; 1017 bias-disable; 1018 }; 1019 1020 blsp_i2c1_sleep: blsp-i2c1-sleep-state { 1021 pins = "gpio2", "gpio3"; 1022 function = "gpio"; 1023 drive-strength = <2>; 1024 bias-disable; 1025 }; 1026 1027 blsp_i2c2_default: blsp-i2c2-default-state { 1028 pins = "gpio6", "gpio7"; 1029 function = "blsp_i2c2"; 1030 drive-strength = <2>; 1031 bias-disable; 1032 }; 1033 1034 blsp_i2c2_sleep: blsp-i2c2-sleep-state { 1035 pins = "gpio6", "gpio7"; 1036 function = "gpio"; 1037 drive-strength = <2>; 1038 bias-disable; 1039 }; 1040 1041 blsp_i2c3_default: blsp-i2c3-default-state { 1042 pins = "gpio10", "gpio11"; 1043 function = "blsp_i2c3"; 1044 drive-strength = <2>; 1045 bias-disable; 1046 }; 1047 1048 blsp_i2c3_sleep: blsp-i2c3-sleep-state { 1049 pins = "gpio10", "gpio11"; 1050 function = "gpio"; 1051 drive-strength = <2>; 1052 bias-disable; 1053 }; 1054 1055 blsp_i2c4_default: blsp-i2c4-default-state { 1056 pins = "gpio14", "gpio15"; 1057 function = "blsp_i2c4"; 1058 drive-strength = <2>; 1059 bias-disable; 1060 }; 1061 1062 blsp_i2c4_sleep: blsp-i2c4-sleep-state { 1063 pins = "gpio14", "gpio15"; 1064 function = "gpio"; 1065 drive-strength = <2>; 1066 bias-disable; 1067 }; 1068 1069 blsp_i2c5_default: blsp-i2c5-default-state { 1070 pins = "gpio18", "gpio19"; 1071 function = "blsp_i2c5"; 1072 drive-strength = <2>; 1073 bias-disable; 1074 }; 1075 1076 blsp_i2c5_sleep: blsp-i2c5-sleep-state { 1077 pins = "gpio18", "gpio19"; 1078 function = "gpio"; 1079 drive-strength = <2>; 1080 bias-disable; 1081 }; 1082 1083 blsp_i2c6_default: blsp-i2c6-default-state { 1084 pins = "gpio22", "gpio23"; 1085 function = "blsp_i2c6"; 1086 drive-strength = <2>; 1087 bias-disable; 1088 }; 1089 1090 blsp_i2c6_sleep: blsp-i2c6-sleep-state { 1091 pins = "gpio22", "gpio23"; 1092 function = "gpio"; 1093 drive-strength = <2>; 1094 bias-disable; 1095 }; 1096 1097 blsp_spi1_default: blsp-spi1-default-state { 1098 spi-pins { 1099 pins = "gpio0", "gpio1", "gpio3"; 1100 function = "blsp_spi1"; 1101 drive-strength = <12>; 1102 bias-disable; 1103 }; 1104 cs-pins { 1105 pins = "gpio2"; 1106 function = "gpio"; 1107 drive-strength = <16>; 1108 bias-disable; 1109 output-high; 1110 }; 1111 }; 1112 1113 blsp_spi1_sleep: blsp-spi1-sleep-state { 1114 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1115 function = "gpio"; 1116 drive-strength = <2>; 1117 bias-pull-down; 1118 }; 1119 1120 blsp_spi2_default: blsp-spi2-default-state { 1121 spi-pins { 1122 pins = "gpio4", "gpio5", "gpio7"; 1123 function = "blsp_spi2"; 1124 drive-strength = <12>; 1125 bias-disable; 1126 }; 1127 cs-pins { 1128 pins = "gpio6"; 1129 function = "gpio"; 1130 drive-strength = <16>; 1131 bias-disable; 1132 output-high; 1133 }; 1134 }; 1135 1136 blsp_spi2_sleep: blsp-spi2-sleep-state { 1137 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 1138 function = "gpio"; 1139 drive-strength = <2>; 1140 bias-pull-down; 1141 }; 1142 1143 blsp_spi3_default: blsp-spi3-default-state { 1144 spi-pins { 1145 pins = "gpio8", "gpio9", "gpio11"; 1146 function = "blsp_spi3"; 1147 drive-strength = <12>; 1148 bias-disable; 1149 }; 1150 cs-pins { 1151 pins = "gpio10"; 1152 function = "gpio"; 1153 drive-strength = <16>; 1154 bias-disable; 1155 output-high; 1156 }; 1157 }; 1158 1159 blsp_spi3_sleep: blsp-spi3-sleep-state { 1160 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 1161 function = "gpio"; 1162 drive-strength = <2>; 1163 bias-pull-down; 1164 }; 1165 1166 blsp_spi4_default: blsp-spi4-default-state { 1167 spi-pins { 1168 pins = "gpio12", "gpio13", "gpio15"; 1169 function = "blsp_spi4"; 1170 drive-strength = <12>; 1171 bias-disable; 1172 }; 1173 cs-pins { 1174 pins = "gpio14"; 1175 function = "gpio"; 1176 drive-strength = <16>; 1177 bias-disable; 1178 output-high; 1179 }; 1180 }; 1181 1182 blsp_spi4_sleep: blsp-spi4-sleep-state { 1183 pins = "gpio12", "gpio13", "gpio14", "gpio15"; 1184 function = "gpio"; 1185 drive-strength = <2>; 1186 bias-pull-down; 1187 }; 1188 1189 blsp_spi5_default: blsp-spi5-default-state { 1190 spi-pins { 1191 pins = "gpio16", "gpio17", "gpio19"; 1192 function = "blsp_spi5"; 1193 drive-strength = <12>; 1194 bias-disable; 1195 }; 1196 cs-pins { 1197 pins = "gpio18"; 1198 function = "gpio"; 1199 drive-strength = <16>; 1200 bias-disable; 1201 output-high; 1202 }; 1203 }; 1204 1205 blsp_spi5_sleep: blsp-spi5-sleep-state { 1206 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 1207 function = "gpio"; 1208 drive-strength = <2>; 1209 bias-pull-down; 1210 }; 1211 1212 blsp_spi6_default: blsp-spi6-default-state { 1213 spi-pins { 1214 pins = "gpio20", "gpio21", "gpio23"; 1215 function = "blsp_spi6"; 1216 drive-strength = <12>; 1217 bias-disable; 1218 }; 1219 cs-pins { 1220 pins = "gpio22"; 1221 function = "gpio"; 1222 drive-strength = <16>; 1223 bias-disable; 1224 output-high; 1225 }; 1226 }; 1227 1228 blsp_spi6_sleep: blsp-spi6-sleep-state { 1229 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 1230 function = "gpio"; 1231 drive-strength = <2>; 1232 bias-pull-down; 1233 }; 1234 1235 blsp_uart1_default: blsp-uart1-default-state { 1236 /* TX, RX, CTS_N, RTS_N */ 1237 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1238 function = "blsp_uart1"; 1239 drive-strength = <16>; 1240 bias-disable; 1241 }; 1242 1243 blsp_uart1_sleep: blsp-uart1-sleep-state { 1244 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1245 function = "gpio"; 1246 drive-strength = <2>; 1247 bias-pull-down; 1248 }; 1249 1250 blsp_uart2_default: blsp-uart2-default-state { 1251 pins = "gpio4", "gpio5"; 1252 function = "blsp_uart2"; 1253 drive-strength = <16>; 1254 bias-disable; 1255 }; 1256 1257 blsp_uart2_sleep: blsp-uart2-sleep-state { 1258 pins = "gpio4", "gpio5"; 1259 function = "gpio"; 1260 drive-strength = <2>; 1261 bias-pull-down; 1262 }; 1263 1264 camera_front_default: camera-front-default-state { 1265 pwdn-pins { 1266 pins = "gpio33"; 1267 function = "gpio"; 1268 drive-strength = <16>; 1269 bias-disable; 1270 }; 1271 rst-pins { 1272 pins = "gpio28"; 1273 function = "gpio"; 1274 drive-strength = <16>; 1275 bias-disable; 1276 }; 1277 mclk1-pins { 1278 pins = "gpio27"; 1279 function = "cam_mclk1"; 1280 drive-strength = <16>; 1281 bias-disable; 1282 }; 1283 }; 1284 1285 camera_rear_default: camera-rear-default-state { 1286 pwdn-pins { 1287 pins = "gpio34"; 1288 function = "gpio"; 1289 drive-strength = <16>; 1290 bias-disable; 1291 }; 1292 rst-pins { 1293 pins = "gpio35"; 1294 function = "gpio"; 1295 drive-strength = <16>; 1296 bias-disable; 1297 }; 1298 mclk0-pins { 1299 pins = "gpio26"; 1300 function = "cam_mclk0"; 1301 drive-strength = <16>; 1302 bias-disable; 1303 }; 1304 }; 1305 1306 cci0_default: cci0-default-state { 1307 pins = "gpio29", "gpio30"; 1308 function = "cci_i2c"; 1309 drive-strength = <16>; 1310 bias-disable; 1311 }; 1312 1313 cdc_dmic_default: cdc-dmic-default-state { 1314 clk-pins { 1315 pins = "gpio0"; 1316 function = "dmic0_clk"; 1317 drive-strength = <8>; 1318 }; 1319 data-pins { 1320 pins = "gpio1"; 1321 function = "dmic0_data"; 1322 drive-strength = <8>; 1323 }; 1324 }; 1325 1326 cdc_dmic_sleep: cdc-dmic-sleep-state { 1327 clk-pins { 1328 pins = "gpio0"; 1329 function = "dmic0_clk"; 1330 drive-strength = <2>; 1331 bias-disable; 1332 }; 1333 data-pins { 1334 pins = "gpio1"; 1335 function = "dmic0_data"; 1336 drive-strength = <2>; 1337 bias-disable; 1338 }; 1339 }; 1340 1341 cdc_pdm_default: cdc-pdm-default-state { 1342 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1343 "gpio67", "gpio68"; 1344 function = "cdc_pdm0"; 1345 drive-strength = <8>; 1346 bias-disable; 1347 }; 1348 1349 cdc_pdm_sleep: cdc-pdm-sleep-state { 1350 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1351 "gpio67", "gpio68"; 1352 function = "cdc_pdm0"; 1353 drive-strength = <2>; 1354 bias-pull-down; 1355 }; 1356 1357 pri_mi2s_default: mi2s-pri-default-state { 1358 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1359 function = "pri_mi2s"; 1360 drive-strength = <8>; 1361 bias-disable; 1362 }; 1363 1364 pri_mi2s_sleep: mi2s-pri-sleep-state { 1365 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1366 function = "pri_mi2s"; 1367 drive-strength = <2>; 1368 bias-disable; 1369 }; 1370 1371 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { 1372 pins = "gpio116"; 1373 function = "pri_mi2s"; 1374 drive-strength = <8>; 1375 bias-disable; 1376 }; 1377 1378 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { 1379 pins = "gpio116"; 1380 function = "pri_mi2s"; 1381 drive-strength = <2>; 1382 bias-disable; 1383 }; 1384 1385 pri_mi2s_ws_default: mi2s-pri-ws-default-state { 1386 pins = "gpio110"; 1387 function = "pri_mi2s_ws"; 1388 drive-strength = <8>; 1389 bias-disable; 1390 }; 1391 1392 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { 1393 pins = "gpio110"; 1394 function = "pri_mi2s_ws"; 1395 drive-strength = <2>; 1396 bias-disable; 1397 }; 1398 1399 sec_mi2s_default: mi2s-sec-default-state { 1400 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1401 function = "sec_mi2s"; 1402 drive-strength = <8>; 1403 bias-disable; 1404 }; 1405 1406 sec_mi2s_sleep: mi2s-sec-sleep-state { 1407 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1408 function = "sec_mi2s"; 1409 drive-strength = <2>; 1410 bias-disable; 1411 }; 1412 1413 sdc1_default: sdc1-default-state { 1414 clk-pins { 1415 pins = "sdc1_clk"; 1416 bias-disable; 1417 drive-strength = <16>; 1418 }; 1419 cmd-pins { 1420 pins = "sdc1_cmd"; 1421 bias-pull-up; 1422 drive-strength = <10>; 1423 }; 1424 data-pins { 1425 pins = "sdc1_data"; 1426 bias-pull-up; 1427 drive-strength = <10>; 1428 }; 1429 }; 1430 1431 sdc1_sleep: sdc1-sleep-state { 1432 clk-pins { 1433 pins = "sdc1_clk"; 1434 bias-disable; 1435 drive-strength = <2>; 1436 }; 1437 cmd-pins { 1438 pins = "sdc1_cmd"; 1439 bias-pull-up; 1440 drive-strength = <2>; 1441 }; 1442 data-pins { 1443 pins = "sdc1_data"; 1444 bias-pull-up; 1445 drive-strength = <2>; 1446 }; 1447 }; 1448 1449 sdc2_default: sdc2-default-state { 1450 clk-pins { 1451 pins = "sdc2_clk"; 1452 bias-disable; 1453 drive-strength = <16>; 1454 }; 1455 cmd-pins { 1456 pins = "sdc2_cmd"; 1457 bias-pull-up; 1458 drive-strength = <10>; 1459 }; 1460 data-pins { 1461 pins = "sdc2_data"; 1462 bias-pull-up; 1463 drive-strength = <10>; 1464 }; 1465 }; 1466 1467 sdc2_sleep: sdc2-sleep-state { 1468 clk-pins { 1469 pins = "sdc2_clk"; 1470 bias-disable; 1471 drive-strength = <2>; 1472 }; 1473 cmd-pins { 1474 pins = "sdc2_cmd"; 1475 bias-pull-up; 1476 drive-strength = <2>; 1477 }; 1478 data-pins { 1479 pins = "sdc2_data"; 1480 bias-pull-up; 1481 drive-strength = <2>; 1482 }; 1483 }; 1484 1485 wcss_wlan_default: wcss-wlan-default-state { 1486 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; 1487 function = "wcss_wlan"; 1488 drive-strength = <6>; 1489 bias-pull-up; 1490 }; 1491 }; 1492 1493 gcc: clock-controller@1800000 { 1494 compatible = "qcom,gcc-msm8916"; 1495 #clock-cells = <1>; 1496 #reset-cells = <1>; 1497 #power-domain-cells = <1>; 1498 reg = <0x01800000 0x80000>; 1499 clocks = <&xo_board>, 1500 <&sleep_clk>, 1501 <&mdss_dsi0_phy 1>, 1502 <&mdss_dsi0_phy 0>, 1503 <0>, 1504 <0>, 1505 <0>; 1506 clock-names = "xo", 1507 "sleep_clk", 1508 "dsi0pll", 1509 "dsi0pllbyte", 1510 "ext_mclk", 1511 "ext_pri_i2s", 1512 "ext_sec_i2s"; 1513 }; 1514 1515 tcsr_mutex: hwlock@1905000 { 1516 compatible = "qcom,tcsr-mutex"; 1517 reg = <0x01905000 0x20000>; 1518 #hwlock-cells = <1>; 1519 }; 1520 1521 tcsr: syscon@1937000 { 1522 compatible = "qcom,tcsr-msm8916", "syscon"; 1523 reg = <0x01937000 0x30000>; 1524 }; 1525 1526 mdss: display-subsystem@1a00000 { 1527 status = "disabled"; 1528 compatible = "qcom,mdss"; 1529 reg = <0x01a00000 0x1000>, 1530 <0x01ac8000 0x3000>; 1531 reg-names = "mdss_phys", "vbif_phys"; 1532 1533 power-domains = <&gcc MDSS_GDSC>; 1534 1535 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1536 <&gcc GCC_MDSS_AXI_CLK>, 1537 <&gcc GCC_MDSS_VSYNC_CLK>; 1538 clock-names = "iface", 1539 "bus", 1540 "vsync"; 1541 1542 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1543 1544 interrupt-controller; 1545 #interrupt-cells = <1>; 1546 1547 #address-cells = <1>; 1548 #size-cells = <1>; 1549 ranges; 1550 1551 mdss_mdp: display-controller@1a01000 { 1552 compatible = "qcom,msm8916-mdp5", "qcom,mdp5"; 1553 reg = <0x01a01000 0x89000>; 1554 reg-names = "mdp_phys"; 1555 1556 interrupt-parent = <&mdss>; 1557 interrupts = <0>; 1558 1559 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1560 <&gcc GCC_MDSS_AXI_CLK>, 1561 <&gcc GCC_MDSS_MDP_CLK>, 1562 <&gcc GCC_MDSS_VSYNC_CLK>; 1563 clock-names = "iface", 1564 "bus", 1565 "core", 1566 "vsync"; 1567 1568 iommus = <&apps_iommu 4>; 1569 1570 ports { 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 1574 port@0 { 1575 reg = <0>; 1576 mdss_mdp_intf1_out: endpoint { 1577 remote-endpoint = <&mdss_dsi0_in>; 1578 }; 1579 }; 1580 }; 1581 }; 1582 1583 mdss_dsi0: dsi@1a98000 { 1584 compatible = "qcom,msm8916-dsi-ctrl", 1585 "qcom,mdss-dsi-ctrl"; 1586 reg = <0x01a98000 0x25c>; 1587 reg-names = "dsi_ctrl"; 1588 1589 interrupt-parent = <&mdss>; 1590 interrupts = <4>; 1591 1592 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1593 <&gcc PCLK0_CLK_SRC>; 1594 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1595 <&mdss_dsi0_phy 1>; 1596 1597 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1598 <&gcc GCC_MDSS_AHB_CLK>, 1599 <&gcc GCC_MDSS_AXI_CLK>, 1600 <&gcc GCC_MDSS_BYTE0_CLK>, 1601 <&gcc GCC_MDSS_PCLK0_CLK>, 1602 <&gcc GCC_MDSS_ESC0_CLK>; 1603 clock-names = "mdp_core", 1604 "iface", 1605 "bus", 1606 "byte", 1607 "pixel", 1608 "core"; 1609 phys = <&mdss_dsi0_phy>; 1610 1611 #address-cells = <1>; 1612 #size-cells = <0>; 1613 1614 ports { 1615 #address-cells = <1>; 1616 #size-cells = <0>; 1617 1618 port@0 { 1619 reg = <0>; 1620 mdss_dsi0_in: endpoint { 1621 remote-endpoint = <&mdss_mdp_intf1_out>; 1622 }; 1623 }; 1624 1625 port@1 { 1626 reg = <1>; 1627 mdss_dsi0_out: endpoint { 1628 }; 1629 }; 1630 }; 1631 }; 1632 1633 mdss_dsi0_phy: phy@1a98300 { 1634 compatible = "qcom,dsi-phy-28nm-lp"; 1635 reg = <0x01a98300 0xd4>, 1636 <0x01a98500 0x280>, 1637 <0x01a98780 0x30>; 1638 reg-names = "dsi_pll", 1639 "dsi_phy", 1640 "dsi_phy_regulator"; 1641 1642 #clock-cells = <1>; 1643 #phy-cells = <0>; 1644 1645 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1646 <&xo_board>; 1647 clock-names = "iface", "ref"; 1648 }; 1649 }; 1650 1651 camss: camss@1b0ac00 { 1652 compatible = "qcom,msm8916-camss"; 1653 reg = <0x01b0ac00 0x200>, 1654 <0x01b00030 0x4>, 1655 <0x01b0b000 0x200>, 1656 <0x01b00038 0x4>, 1657 <0x01b08000 0x100>, 1658 <0x01b08400 0x100>, 1659 <0x01b0a000 0x500>, 1660 <0x01b00020 0x10>, 1661 <0x01b10000 0x1000>; 1662 reg-names = "csiphy0", 1663 "csiphy0_clk_mux", 1664 "csiphy1", 1665 "csiphy1_clk_mux", 1666 "csid0", 1667 "csid1", 1668 "ispif", 1669 "csi_clk_mux", 1670 "vfe0"; 1671 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1672 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1673 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 1674 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 1675 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 1676 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 1677 interrupt-names = "csiphy0", 1678 "csiphy1", 1679 "csid0", 1680 "csid1", 1681 "ispif", 1682 "vfe0"; 1683 power-domains = <&gcc VFE_GDSC>; 1684 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1685 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 1686 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1687 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1688 <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 1689 <&gcc GCC_CAMSS_CSI0_CLK>, 1690 <&gcc GCC_CAMSS_CSI0PHY_CLK>, 1691 <&gcc GCC_CAMSS_CSI0PIX_CLK>, 1692 <&gcc GCC_CAMSS_CSI0RDI_CLK>, 1693 <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 1694 <&gcc GCC_CAMSS_CSI1_CLK>, 1695 <&gcc GCC_CAMSS_CSI1PHY_CLK>, 1696 <&gcc GCC_CAMSS_CSI1PIX_CLK>, 1697 <&gcc GCC_CAMSS_CSI1RDI_CLK>, 1698 <&gcc GCC_CAMSS_AHB_CLK>, 1699 <&gcc GCC_CAMSS_VFE0_CLK>, 1700 <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 1701 <&gcc GCC_CAMSS_VFE_AHB_CLK>, 1702 <&gcc GCC_CAMSS_VFE_AXI_CLK>; 1703 clock-names = "top_ahb", 1704 "ispif_ahb", 1705 "csiphy0_timer", 1706 "csiphy1_timer", 1707 "csi0_ahb", 1708 "csi0", 1709 "csi0_phy", 1710 "csi0_pix", 1711 "csi0_rdi", 1712 "csi1_ahb", 1713 "csi1", 1714 "csi1_phy", 1715 "csi1_pix", 1716 "csi1_rdi", 1717 "ahb", 1718 "vfe0", 1719 "csi_vfe0", 1720 "vfe_ahb", 1721 "vfe_axi"; 1722 iommus = <&apps_iommu 3>; 1723 status = "disabled"; 1724 ports { 1725 #address-cells = <1>; 1726 #size-cells = <0>; 1727 1728 port@0 { 1729 reg = <0>; 1730 }; 1731 1732 port@1 { 1733 reg = <1>; 1734 }; 1735 }; 1736 }; 1737 1738 cci: cci@1b0c000 { 1739 compatible = "qcom,msm8916-cci", "qcom,msm8226-cci"; 1740 #address-cells = <1>; 1741 #size-cells = <0>; 1742 reg = <0x01b0c000 0x1000>; 1743 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 1744 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1745 <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1746 <&gcc GCC_CAMSS_CCI_CLK>, 1747 <&gcc GCC_CAMSS_AHB_CLK>; 1748 clock-names = "camss_top_ahb", "cci_ahb", 1749 "cci", "camss_ahb"; 1750 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>, 1751 <&gcc GCC_CAMSS_CCI_CLK>; 1752 assigned-clock-rates = <80000000>, <19200000>; 1753 pinctrl-names = "default"; 1754 pinctrl-0 = <&cci0_default>; 1755 status = "disabled"; 1756 1757 cci_i2c0: i2c-bus@0 { 1758 reg = <0>; 1759 clock-frequency = <400000>; 1760 #address-cells = <1>; 1761 #size-cells = <0>; 1762 }; 1763 }; 1764 1765 gpu: gpu@1c00000 { 1766 compatible = "qcom,adreno-306.0", "qcom,adreno"; 1767 reg = <0x01c00000 0x20000>; 1768 reg-names = "kgsl_3d0_reg_memory"; 1769 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1770 interrupt-names = "kgsl_3d0_irq"; 1771 clock-names = 1772 "core", 1773 "iface", 1774 "mem", 1775 "mem_iface", 1776 "alt_mem_iface", 1777 "gfx3d"; 1778 clocks = 1779 <&gcc GCC_OXILI_GFX3D_CLK>, 1780 <&gcc GCC_OXILI_AHB_CLK>, 1781 <&gcc GCC_OXILI_GMEM_CLK>, 1782 <&gcc GCC_BIMC_GFX_CLK>, 1783 <&gcc GCC_BIMC_GPU_CLK>, 1784 <&gcc GFX3D_CLK_SRC>; 1785 power-domains = <&gcc OXILI_GDSC>; 1786 operating-points-v2 = <&gpu_opp_table>; 1787 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1788 #cooling-cells = <2>; 1789 1790 status = "disabled"; 1791 1792 gpu_opp_table: opp-table { 1793 compatible = "operating-points-v2"; 1794 1795 opp-400000000 { 1796 opp-hz = /bits/ 64 <400000000>; 1797 }; 1798 opp-19200000 { 1799 opp-hz = /bits/ 64 <19200000>; 1800 }; 1801 }; 1802 }; 1803 1804 venus: video-codec@1d00000 { 1805 compatible = "qcom,msm8916-venus"; 1806 reg = <0x01d00000 0xff000>; 1807 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1808 power-domains = <&gcc VENUS_GDSC>; 1809 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, 1810 <&gcc GCC_VENUS0_AHB_CLK>, 1811 <&gcc GCC_VENUS0_AXI_CLK>; 1812 clock-names = "core", "iface", "bus"; 1813 iommus = <&apps_iommu 5>; 1814 memory-region = <&venus_mem>; 1815 status = "disabled"; 1816 1817 video-decoder { 1818 compatible = "venus-decoder"; 1819 }; 1820 1821 video-encoder { 1822 compatible = "venus-encoder"; 1823 }; 1824 }; 1825 1826 apps_iommu: iommu@1ef0000 { 1827 #address-cells = <1>; 1828 #size-cells = <1>; 1829 #iommu-cells = <1>; 1830 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1831 ranges = <0 0x01e20000 0x20000>; 1832 reg = <0x01ef0000 0x3000>; 1833 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1834 <&gcc GCC_APSS_TCU_CLK>; 1835 clock-names = "iface", "bus"; 1836 qcom,iommu-secure-id = <17>; 1837 1838 /* VFE */ 1839 iommu-ctx@3000 { 1840 compatible = "qcom,msm-iommu-v1-sec"; 1841 reg = <0x3000 0x1000>; 1842 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1843 }; 1844 1845 /* MDP_0 */ 1846 iommu-ctx@4000 { 1847 compatible = "qcom,msm-iommu-v1-ns"; 1848 reg = <0x4000 0x1000>; 1849 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1850 }; 1851 1852 /* VENUS_NS */ 1853 iommu-ctx@5000 { 1854 compatible = "qcom,msm-iommu-v1-sec"; 1855 reg = <0x5000 0x1000>; 1856 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1857 }; 1858 }; 1859 1860 gpu_iommu: iommu@1f08000 { 1861 #address-cells = <1>; 1862 #size-cells = <1>; 1863 #iommu-cells = <1>; 1864 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1865 ranges = <0 0x01f08000 0x10000>; 1866 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1867 <&gcc GCC_GFX_TCU_CLK>; 1868 clock-names = "iface", "bus"; 1869 qcom,iommu-secure-id = <18>; 1870 1871 /* GFX3D_USER */ 1872 iommu-ctx@1000 { 1873 compatible = "qcom,msm-iommu-v1-ns"; 1874 reg = <0x1000 0x1000>; 1875 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1876 }; 1877 1878 /* GFX3D_PRIV */ 1879 iommu-ctx@2000 { 1880 compatible = "qcom,msm-iommu-v1-ns"; 1881 reg = <0x2000 0x1000>; 1882 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1883 }; 1884 }; 1885 1886 spmi_bus: spmi@200f000 { 1887 compatible = "qcom,spmi-pmic-arb"; 1888 reg = <0x0200f000 0x001000>, 1889 <0x02400000 0x400000>, 1890 <0x02c00000 0x400000>, 1891 <0x03800000 0x200000>, 1892 <0x0200a000 0x002100>; 1893 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1894 interrupt-names = "periph_irq"; 1895 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1896 qcom,ee = <0>; 1897 qcom,channel = <0>; 1898 #address-cells = <2>; 1899 #size-cells = <0>; 1900 interrupt-controller; 1901 #interrupt-cells = <4>; 1902 }; 1903 1904 bam_dmux_dma: dma-controller@4044000 { 1905 compatible = "qcom,bam-v1.7.0"; 1906 reg = <0x04044000 0x19000>; 1907 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1908 #dma-cells = <1>; 1909 qcom,ee = <0>; 1910 1911 num-channels = <6>; 1912 qcom,num-ees = <1>; 1913 qcom,powered-remotely; 1914 1915 status = "disabled"; 1916 }; 1917 1918 mpss: remoteproc@4080000 { 1919 compatible = "qcom,msm8916-mss-pil"; 1920 reg = <0x04080000 0x100>, 1921 <0x04020000 0x040>; 1922 1923 reg-names = "qdsp6", "rmb"; 1924 1925 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1926 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1927 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1928 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1929 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1930 interrupt-names = "wdog", "fatal", "ready", 1931 "handover", "stop-ack"; 1932 1933 power-domains = <&rpmpd MSM8916_VDDCX>, 1934 <&rpmpd MSM8916_VDDMX>; 1935 power-domain-names = "cx", "mx"; 1936 1937 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1938 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1939 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1940 <&xo_board>; 1941 clock-names = "iface", "bus", "mem", "xo"; 1942 1943 qcom,smem-states = <&hexagon_smp2p_out 0>; 1944 qcom,smem-state-names = "stop"; 1945 1946 resets = <&scm 0>; 1947 reset-names = "mss_restart"; 1948 1949 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1950 1951 status = "disabled"; 1952 1953 mba { 1954 memory-region = <&mba_mem>; 1955 }; 1956 1957 mpss { 1958 memory-region = <&mpss_mem>; 1959 }; 1960 1961 bam_dmux: bam-dmux { 1962 compatible = "qcom,bam-dmux"; 1963 1964 interrupt-parent = <&hexagon_smsm>; 1965 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1966 interrupt-names = "pc", "pc-ack"; 1967 1968 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1969 qcom,smem-state-names = "pc", "pc-ack"; 1970 1971 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1972 dma-names = "tx", "rx"; 1973 1974 status = "disabled"; 1975 }; 1976 1977 smd-edge { 1978 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1979 1980 qcom,smd-edge = <0>; 1981 qcom,ipc = <&apcs 8 12>; 1982 qcom,remote-pid = <1>; 1983 1984 label = "hexagon"; 1985 1986 apr: apr { 1987 compatible = "qcom,apr-v2"; 1988 qcom,smd-channels = "apr_audio_svc"; 1989 qcom,domain = <APR_DOMAIN_ADSP>; 1990 #address-cells = <1>; 1991 #size-cells = <0>; 1992 status = "disabled"; 1993 1994 q6core: service@3 { 1995 compatible = "qcom,q6core"; 1996 reg = <APR_SVC_ADSP_CORE>; 1997 }; 1998 1999 q6afe: service@4 { 2000 compatible = "qcom,q6afe"; 2001 reg = <APR_SVC_AFE>; 2002 2003 q6afedai: dais { 2004 compatible = "qcom,q6afe-dais"; 2005 #address-cells = <1>; 2006 #size-cells = <0>; 2007 #sound-dai-cells = <1>; 2008 }; 2009 }; 2010 2011 q6asm: service@7 { 2012 compatible = "qcom,q6asm"; 2013 reg = <APR_SVC_ASM>; 2014 2015 q6asmdai: dais { 2016 compatible = "qcom,q6asm-dais"; 2017 #address-cells = <1>; 2018 #size-cells = <0>; 2019 #sound-dai-cells = <1>; 2020 }; 2021 }; 2022 2023 q6adm: service@8 { 2024 compatible = "qcom,q6adm"; 2025 reg = <APR_SVC_ADM>; 2026 2027 q6routing: routing { 2028 compatible = "qcom,q6adm-routing"; 2029 #sound-dai-cells = <0>; 2030 }; 2031 }; 2032 }; 2033 2034 fastrpc { 2035 compatible = "qcom,fastrpc"; 2036 qcom,smd-channels = "fastrpcsmd-apps-dsp"; 2037 label = "adsp"; 2038 qcom,non-secure-domain; 2039 2040 #address-cells = <1>; 2041 #size-cells = <0>; 2042 2043 cb@1 { 2044 compatible = "qcom,fastrpc-compute-cb"; 2045 reg = <1>; 2046 }; 2047 }; 2048 }; 2049 }; 2050 2051 sound: sound@7702000 { 2052 status = "disabled"; 2053 compatible = "qcom,apq8016-sbc-sndcard"; 2054 reg = <0x07702000 0x4>, <0x07702004 0x4>; 2055 reg-names = "mic-iomux", "spkr-iomux"; 2056 }; 2057 2058 lpass: audio-controller@7708000 { 2059 status = "disabled"; 2060 compatible = "qcom,apq8016-lpass-cpu"; 2061 2062 /* 2063 * Note: Unlike the name would suggest, the SEC_I2S_CLK 2064 * is actually only used by Tertiary MI2S while 2065 * Primary/Secondary MI2S both use the PRI_I2S_CLK. 2066 */ 2067 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 2068 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 2069 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 2070 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 2071 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, 2072 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 2073 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; 2074 2075 clock-names = "ahbix-clk", 2076 "mi2s-bit-clk0", 2077 "mi2s-bit-clk1", 2078 "mi2s-bit-clk2", 2079 "mi2s-bit-clk3", 2080 "pcnoc-mport-clk", 2081 "pcnoc-sway-clk"; 2082 #sound-dai-cells = <1>; 2083 2084 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2085 interrupt-names = "lpass-irq-lpaif"; 2086 reg = <0x07708000 0x10000>; 2087 reg-names = "lpass-lpaif"; 2088 2089 #address-cells = <1>; 2090 #size-cells = <0>; 2091 }; 2092 2093 lpass_codec: audio-codec@771c000 { 2094 compatible = "qcom,msm8916-wcd-digital-codec"; 2095 reg = <0x0771c000 0x400>; 2096 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 2097 <&gcc GCC_CODEC_DIGCODEC_CLK>; 2098 clock-names = "ahbix-clk", "mclk"; 2099 #sound-dai-cells = <1>; 2100 status = "disabled"; 2101 }; 2102 2103 sdhc_1: mmc@7824900 { 2104 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 2105 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 2106 reg-names = "hc", "core"; 2107 2108 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2110 interrupt-names = "hc_irq", "pwr_irq"; 2111 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 2112 <&gcc GCC_SDCC1_APPS_CLK>, 2113 <&xo_board>; 2114 clock-names = "iface", "core", "xo"; 2115 pinctrl-0 = <&sdc1_default>; 2116 pinctrl-1 = <&sdc1_sleep>; 2117 pinctrl-names = "default", "sleep"; 2118 mmc-ddr-1_8v; 2119 bus-width = <8>; 2120 non-removable; 2121 status = "disabled"; 2122 }; 2123 2124 sdhc_2: mmc@7864900 { 2125 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 2126 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 2127 reg-names = "hc", "core"; 2128 2129 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2131 interrupt-names = "hc_irq", "pwr_irq"; 2132 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2133 <&gcc GCC_SDCC2_APPS_CLK>, 2134 <&xo_board>; 2135 clock-names = "iface", "core", "xo"; 2136 pinctrl-0 = <&sdc2_default>; 2137 pinctrl-1 = <&sdc2_sleep>; 2138 pinctrl-names = "default", "sleep"; 2139 bus-width = <4>; 2140 status = "disabled"; 2141 }; 2142 2143 blsp_dma: dma-controller@7884000 { 2144 compatible = "qcom,bam-v1.7.0"; 2145 reg = <0x07884000 0x23000>; 2146 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2147 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2148 clock-names = "bam_clk"; 2149 #dma-cells = <1>; 2150 qcom,ee = <0>; 2151 qcom,controlled-remotely; 2152 }; 2153 2154 blsp_uart1: serial@78af000 { 2155 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2156 reg = <0x078af000 0x200>; 2157 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 2158 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 2159 clock-names = "core", "iface"; 2160 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 2161 dma-names = "tx", "rx"; 2162 pinctrl-names = "default", "sleep"; 2163 pinctrl-0 = <&blsp_uart1_default>; 2164 pinctrl-1 = <&blsp_uart1_sleep>; 2165 status = "disabled"; 2166 }; 2167 2168 blsp_uart2: serial@78b0000 { 2169 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2170 reg = <0x078b0000 0x200>; 2171 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2172 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 2173 clock-names = "core", "iface"; 2174 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 2175 dma-names = "tx", "rx"; 2176 pinctrl-names = "default", "sleep"; 2177 pinctrl-0 = <&blsp_uart2_default>; 2178 pinctrl-1 = <&blsp_uart2_sleep>; 2179 status = "disabled"; 2180 }; 2181 2182 blsp_i2c1: i2c@78b5000 { 2183 compatible = "qcom,i2c-qup-v2.2.1"; 2184 reg = <0x078b5000 0x500>; 2185 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2186 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2187 <&gcc GCC_BLSP1_AHB_CLK>; 2188 clock-names = "core", "iface"; 2189 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 2190 dma-names = "tx", "rx"; 2191 pinctrl-names = "default", "sleep"; 2192 pinctrl-0 = <&blsp_i2c1_default>; 2193 pinctrl-1 = <&blsp_i2c1_sleep>; 2194 #address-cells = <1>; 2195 #size-cells = <0>; 2196 status = "disabled"; 2197 }; 2198 2199 blsp_spi1: spi@78b5000 { 2200 compatible = "qcom,spi-qup-v2.2.1"; 2201 reg = <0x078b5000 0x500>; 2202 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2203 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2204 <&gcc GCC_BLSP1_AHB_CLK>; 2205 clock-names = "core", "iface"; 2206 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 2207 dma-names = "tx", "rx"; 2208 pinctrl-names = "default", "sleep"; 2209 pinctrl-0 = <&blsp_spi1_default>; 2210 pinctrl-1 = <&blsp_spi1_sleep>; 2211 #address-cells = <1>; 2212 #size-cells = <0>; 2213 status = "disabled"; 2214 }; 2215 2216 blsp_i2c2: i2c@78b6000 { 2217 compatible = "qcom,i2c-qup-v2.2.1"; 2218 reg = <0x078b6000 0x500>; 2219 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2220 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2221 <&gcc GCC_BLSP1_AHB_CLK>; 2222 clock-names = "core", "iface"; 2223 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 2224 dma-names = "tx", "rx"; 2225 pinctrl-names = "default", "sleep"; 2226 pinctrl-0 = <&blsp_i2c2_default>; 2227 pinctrl-1 = <&blsp_i2c2_sleep>; 2228 #address-cells = <1>; 2229 #size-cells = <0>; 2230 status = "disabled"; 2231 }; 2232 2233 blsp_spi2: spi@78b6000 { 2234 compatible = "qcom,spi-qup-v2.2.1"; 2235 reg = <0x078b6000 0x500>; 2236 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2237 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 2238 <&gcc GCC_BLSP1_AHB_CLK>; 2239 clock-names = "core", "iface"; 2240 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 2241 dma-names = "tx", "rx"; 2242 pinctrl-names = "default", "sleep"; 2243 pinctrl-0 = <&blsp_spi2_default>; 2244 pinctrl-1 = <&blsp_spi2_sleep>; 2245 #address-cells = <1>; 2246 #size-cells = <0>; 2247 status = "disabled"; 2248 }; 2249 2250 blsp_i2c3: i2c@78b7000 { 2251 compatible = "qcom,i2c-qup-v2.2.1"; 2252 reg = <0x078b7000 0x500>; 2253 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2254 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2255 <&gcc GCC_BLSP1_AHB_CLK>; 2256 clock-names = "core", "iface"; 2257 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 2258 dma-names = "tx", "rx"; 2259 pinctrl-names = "default", "sleep"; 2260 pinctrl-0 = <&blsp_i2c3_default>; 2261 pinctrl-1 = <&blsp_i2c3_sleep>; 2262 #address-cells = <1>; 2263 #size-cells = <0>; 2264 status = "disabled"; 2265 }; 2266 2267 blsp_spi3: spi@78b7000 { 2268 compatible = "qcom,spi-qup-v2.2.1"; 2269 reg = <0x078b7000 0x500>; 2270 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2271 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 2272 <&gcc GCC_BLSP1_AHB_CLK>; 2273 clock-names = "core", "iface"; 2274 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 2275 dma-names = "tx", "rx"; 2276 pinctrl-names = "default", "sleep"; 2277 pinctrl-0 = <&blsp_spi3_default>; 2278 pinctrl-1 = <&blsp_spi3_sleep>; 2279 #address-cells = <1>; 2280 #size-cells = <0>; 2281 status = "disabled"; 2282 }; 2283 2284 blsp_i2c4: i2c@78b8000 { 2285 compatible = "qcom,i2c-qup-v2.2.1"; 2286 reg = <0x078b8000 0x500>; 2287 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2288 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2289 <&gcc GCC_BLSP1_AHB_CLK>; 2290 clock-names = "core", "iface"; 2291 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 2292 dma-names = "tx", "rx"; 2293 pinctrl-names = "default", "sleep"; 2294 pinctrl-0 = <&blsp_i2c4_default>; 2295 pinctrl-1 = <&blsp_i2c4_sleep>; 2296 #address-cells = <1>; 2297 #size-cells = <0>; 2298 status = "disabled"; 2299 }; 2300 2301 blsp_spi4: spi@78b8000 { 2302 compatible = "qcom,spi-qup-v2.2.1"; 2303 reg = <0x078b8000 0x500>; 2304 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2305 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 2306 <&gcc GCC_BLSP1_AHB_CLK>; 2307 clock-names = "core", "iface"; 2308 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 2309 dma-names = "tx", "rx"; 2310 pinctrl-names = "default", "sleep"; 2311 pinctrl-0 = <&blsp_spi4_default>; 2312 pinctrl-1 = <&blsp_spi4_sleep>; 2313 #address-cells = <1>; 2314 #size-cells = <0>; 2315 status = "disabled"; 2316 }; 2317 2318 blsp_i2c5: i2c@78b9000 { 2319 compatible = "qcom,i2c-qup-v2.2.1"; 2320 reg = <0x078b9000 0x500>; 2321 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2322 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2323 <&gcc GCC_BLSP1_AHB_CLK>; 2324 clock-names = "core", "iface"; 2325 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 2326 dma-names = "tx", "rx"; 2327 pinctrl-names = "default", "sleep"; 2328 pinctrl-0 = <&blsp_i2c5_default>; 2329 pinctrl-1 = <&blsp_i2c5_sleep>; 2330 #address-cells = <1>; 2331 #size-cells = <0>; 2332 status = "disabled"; 2333 }; 2334 2335 blsp_spi5: spi@78b9000 { 2336 compatible = "qcom,spi-qup-v2.2.1"; 2337 reg = <0x078b9000 0x500>; 2338 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2339 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 2340 <&gcc GCC_BLSP1_AHB_CLK>; 2341 clock-names = "core", "iface"; 2342 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 2343 dma-names = "tx", "rx"; 2344 pinctrl-names = "default", "sleep"; 2345 pinctrl-0 = <&blsp_spi5_default>; 2346 pinctrl-1 = <&blsp_spi5_sleep>; 2347 #address-cells = <1>; 2348 #size-cells = <0>; 2349 status = "disabled"; 2350 }; 2351 2352 blsp_i2c6: i2c@78ba000 { 2353 compatible = "qcom,i2c-qup-v2.2.1"; 2354 reg = <0x078ba000 0x500>; 2355 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2356 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2357 <&gcc GCC_BLSP1_AHB_CLK>; 2358 clock-names = "core", "iface"; 2359 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 2360 dma-names = "tx", "rx"; 2361 pinctrl-names = "default", "sleep"; 2362 pinctrl-0 = <&blsp_i2c6_default>; 2363 pinctrl-1 = <&blsp_i2c6_sleep>; 2364 #address-cells = <1>; 2365 #size-cells = <0>; 2366 status = "disabled"; 2367 }; 2368 2369 blsp_spi6: spi@78ba000 { 2370 compatible = "qcom,spi-qup-v2.2.1"; 2371 reg = <0x078ba000 0x500>; 2372 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2373 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 2374 <&gcc GCC_BLSP1_AHB_CLK>; 2375 clock-names = "core", "iface"; 2376 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 2377 dma-names = "tx", "rx"; 2378 pinctrl-names = "default", "sleep"; 2379 pinctrl-0 = <&blsp_spi6_default>; 2380 pinctrl-1 = <&blsp_spi6_sleep>; 2381 #address-cells = <1>; 2382 #size-cells = <0>; 2383 status = "disabled"; 2384 }; 2385 2386 usb: usb@78d9000 { 2387 compatible = "qcom,ci-hdrc"; 2388 reg = <0x078d9000 0x200>, 2389 <0x078d9200 0x200>; 2390 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2391 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2392 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 2393 <&gcc GCC_USB_HS_SYSTEM_CLK>; 2394 clock-names = "iface", "core"; 2395 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 2396 assigned-clock-rates = <80000000>; 2397 resets = <&gcc GCC_USB_HS_BCR>; 2398 reset-names = "core"; 2399 phy_type = "ulpi"; 2400 dr_mode = "otg"; 2401 hnp-disable; 2402 srp-disable; 2403 adp-disable; 2404 ahb-burst-config = <0>; 2405 phy-names = "usb-phy"; 2406 phys = <&usb_hs_phy>; 2407 status = "disabled"; 2408 #reset-cells = <1>; 2409 2410 ulpi { 2411 usb_hs_phy: phy { 2412 compatible = "qcom,usb-hs-phy-msm8916", 2413 "qcom,usb-hs-phy"; 2414 #phy-cells = <0>; 2415 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 2416 clock-names = "ref", "sleep"; 2417 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 2418 reset-names = "phy", "por"; 2419 qcom,init-seq = /bits/ 8 <0x0 0x44>, 2420 <0x1 0x6b>, 2421 <0x2 0x24>, 2422 <0x3 0x13>; 2423 }; 2424 }; 2425 }; 2426 2427 wcnss: remoteproc@a204000 { 2428 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 2429 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 2430 reg-names = "ccu", "dxe", "pmu"; 2431 2432 memory-region = <&wcnss_mem>; 2433 2434 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 2435 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2436 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2437 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2438 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2439 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 2440 2441 power-domains = <&rpmpd MSM8916_VDDCX>, 2442 <&rpmpd MSM8916_VDDMX>; 2443 power-domain-names = "cx", "mx"; 2444 2445 qcom,smem-states = <&wcnss_smp2p_out 0>; 2446 qcom,smem-state-names = "stop"; 2447 2448 pinctrl-names = "default"; 2449 pinctrl-0 = <&wcss_wlan_default>; 2450 2451 status = "disabled"; 2452 2453 wcnss_iris: iris { 2454 /* Separate chip, compatible is board-specific */ 2455 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 2456 clock-names = "xo"; 2457 }; 2458 2459 smd-edge { 2460 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 2461 2462 qcom,ipc = <&apcs 8 17>; 2463 qcom,smd-edge = <6>; 2464 qcom,remote-pid = <4>; 2465 2466 label = "pronto"; 2467 2468 wcnss_ctrl: wcnss { 2469 compatible = "qcom,wcnss"; 2470 qcom,smd-channels = "WCNSS_CTRL"; 2471 2472 qcom,mmio = <&wcnss>; 2473 2474 wcnss_bt: bluetooth { 2475 compatible = "qcom,wcnss-bt"; 2476 }; 2477 2478 wcnss_wifi: wifi { 2479 compatible = "qcom,wcnss-wlan"; 2480 2481 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2483 interrupt-names = "tx", "rx"; 2484 2485 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 2486 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 2487 }; 2488 }; 2489 }; 2490 }; 2491 2492 intc: interrupt-controller@b000000 { 2493 compatible = "qcom,msm-qgic2"; 2494 interrupt-controller; 2495 #interrupt-cells = <3>; 2496 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 2497 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 2498 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 2499 }; 2500 2501 apcs: mailbox@b011000 { 2502 compatible = "qcom,msm8916-apcs-kpss-global", "syscon"; 2503 reg = <0x0b011000 0x1000>; 2504 #mbox-cells = <1>; 2505 clocks = <&a53pll>, <&gcc GPLL0_VOTE>; 2506 clock-names = "pll", "aux"; 2507 #clock-cells = <0>; 2508 }; 2509 2510 a53pll: clock@b016000 { 2511 compatible = "qcom,msm8916-a53pll"; 2512 reg = <0x0b016000 0x40>; 2513 #clock-cells = <0>; 2514 clocks = <&xo_board>; 2515 clock-names = "xo"; 2516 }; 2517 2518 timer@b020000 { 2519 #address-cells = <1>; 2520 #size-cells = <1>; 2521 ranges; 2522 compatible = "arm,armv7-timer-mem"; 2523 reg = <0x0b020000 0x1000>; 2524 clock-frequency = <19200000>; 2525 2526 frame@b021000 { 2527 frame-number = <0>; 2528 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2529 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2530 reg = <0x0b021000 0x1000>, 2531 <0x0b022000 0x1000>; 2532 }; 2533 2534 frame@b023000 { 2535 frame-number = <1>; 2536 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2537 reg = <0x0b023000 0x1000>; 2538 status = "disabled"; 2539 }; 2540 2541 frame@b024000 { 2542 frame-number = <2>; 2543 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2544 reg = <0x0b024000 0x1000>; 2545 status = "disabled"; 2546 }; 2547 2548 frame@b025000 { 2549 frame-number = <3>; 2550 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2551 reg = <0x0b025000 0x1000>; 2552 status = "disabled"; 2553 }; 2554 2555 frame@b026000 { 2556 frame-number = <4>; 2557 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2558 reg = <0x0b026000 0x1000>; 2559 status = "disabled"; 2560 }; 2561 2562 frame@b027000 { 2563 frame-number = <5>; 2564 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2565 reg = <0x0b027000 0x1000>; 2566 status = "disabled"; 2567 }; 2568 2569 frame@b028000 { 2570 frame-number = <6>; 2571 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2572 reg = <0x0b028000 0x1000>; 2573 status = "disabled"; 2574 }; 2575 }; 2576 2577 cpu0_acc: power-manager@b088000 { 2578 compatible = "qcom,msm8916-acc"; 2579 reg = <0x0b088000 0x1000>; 2580 status = "reserved"; /* Controlled by PSCI firmware */ 2581 }; 2582 2583 cpu0_saw: power-manager@b089000 { 2584 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2585 reg = <0x0b089000 0x1000>; 2586 status = "reserved"; /* Controlled by PSCI firmware */ 2587 }; 2588 2589 cpu1_acc: power-manager@b098000 { 2590 compatible = "qcom,msm8916-acc"; 2591 reg = <0x0b098000 0x1000>; 2592 status = "reserved"; /* Controlled by PSCI firmware */ 2593 }; 2594 2595 cpu1_saw: power-manager@b099000 { 2596 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2597 reg = <0x0b099000 0x1000>; 2598 status = "reserved"; /* Controlled by PSCI firmware */ 2599 }; 2600 2601 cpu2_acc: power-manager@b0a8000 { 2602 compatible = "qcom,msm8916-acc"; 2603 reg = <0x0b0a8000 0x1000>; 2604 status = "reserved"; /* Controlled by PSCI firmware */ 2605 }; 2606 2607 cpu2_saw: power-manager@b0a9000 { 2608 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2609 reg = <0x0b0a9000 0x1000>; 2610 status = "reserved"; /* Controlled by PSCI firmware */ 2611 }; 2612 2613 cpu3_acc: power-manager@b0b8000 { 2614 compatible = "qcom,msm8916-acc"; 2615 reg = <0x0b0b8000 0x1000>; 2616 status = "reserved"; /* Controlled by PSCI firmware */ 2617 }; 2618 2619 cpu3_saw: power-manager@b0b9000 { 2620 compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2"; 2621 reg = <0x0b0b9000 0x1000>; 2622 status = "reserved"; /* Controlled by PSCI firmware */ 2623 }; 2624 }; 2625 2626 thermal-zones { 2627 cpu0-1-thermal { 2628 polling-delay-passive = <250>; 2629 polling-delay = <1000>; 2630 2631 thermal-sensors = <&tsens 5>; 2632 2633 trips { 2634 cpu0_1_alert0: trip-point0 { 2635 temperature = <75000>; 2636 hysteresis = <2000>; 2637 type = "passive"; 2638 }; 2639 cpu0_1_crit: cpu-crit { 2640 temperature = <110000>; 2641 hysteresis = <2000>; 2642 type = "critical"; 2643 }; 2644 }; 2645 2646 cooling-maps { 2647 map0 { 2648 trip = <&cpu0_1_alert0>; 2649 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2650 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2651 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2652 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2653 }; 2654 }; 2655 }; 2656 2657 cpu2-3-thermal { 2658 polling-delay-passive = <250>; 2659 polling-delay = <1000>; 2660 2661 thermal-sensors = <&tsens 4>; 2662 2663 trips { 2664 cpu2_3_alert0: trip-point0 { 2665 temperature = <75000>; 2666 hysteresis = <2000>; 2667 type = "passive"; 2668 }; 2669 cpu2_3_crit: cpu-crit { 2670 temperature = <110000>; 2671 hysteresis = <2000>; 2672 type = "critical"; 2673 }; 2674 }; 2675 2676 cooling-maps { 2677 map0 { 2678 trip = <&cpu2_3_alert0>; 2679 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2680 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2681 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2682 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2683 }; 2684 }; 2685 }; 2686 2687 gpu-thermal { 2688 polling-delay-passive = <250>; 2689 polling-delay = <1000>; 2690 2691 thermal-sensors = <&tsens 2>; 2692 2693 cooling-maps { 2694 map0 { 2695 trip = <&gpu_alert0>; 2696 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2697 }; 2698 }; 2699 2700 trips { 2701 gpu_alert0: trip-point0 { 2702 temperature = <75000>; 2703 hysteresis = <2000>; 2704 type = "passive"; 2705 }; 2706 gpu_crit: gpu-crit { 2707 temperature = <95000>; 2708 hysteresis = <2000>; 2709 type = "critical"; 2710 }; 2711 }; 2712 }; 2713 2714 camera-thermal { 2715 polling-delay-passive = <250>; 2716 polling-delay = <1000>; 2717 2718 thermal-sensors = <&tsens 1>; 2719 2720 trips { 2721 cam_alert0: trip-point0 { 2722 temperature = <75000>; 2723 hysteresis = <2000>; 2724 type = "hot"; 2725 }; 2726 }; 2727 }; 2728 2729 modem-thermal { 2730 polling-delay-passive = <250>; 2731 polling-delay = <1000>; 2732 2733 thermal-sensors = <&tsens 0>; 2734 2735 trips { 2736 modem_alert0: trip-point0 { 2737 temperature = <85000>; 2738 hysteresis = <2000>; 2739 type = "hot"; 2740 }; 2741 }; 2742 }; 2743 }; 2744 2745 timer { 2746 compatible = "arm,armv8-timer"; 2747 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2748 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2749 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2750 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2751 }; 2752}; 2753