1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com> 4 */ 5 6#include <dt-bindings/clock/qcom,milos-camcc.h> 7#include <dt-bindings/clock/qcom,milos-dispcc.h> 8#include <dt-bindings/clock/qcom,milos-gcc.h> 9#include <dt-bindings/clock/qcom,milos-gpucc.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm8650-tcsr.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,milos-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <76800000>; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32764>; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a520"; 54 reg = <0x0 0x0>; 55 56 clocks = <&cpufreq_hw 0>; 57 58 power-domains = <&cpu_pd0>; 59 power-domain-names = "psci"; 60 61 enable-method = "psci"; 62 next-level-cache = <&l2_0>; 63 capacity-dmips-mhz = <1024>; 64 dynamic-power-coefficient = <100>; 65 66 qcom,freq-domain = <&cpufreq_hw 0>; 67 68 #cooling-cells = <2>; 69 70 l2_0: l2-cache { 71 compatible = "cache"; 72 cache-level = <2>; 73 cache-unified; 74 next-level-cache = <&l3_0>; 75 76 l3_0: l3-cache { 77 compatible = "cache"; 78 cache-level = <3>; 79 cache-unified; 80 }; 81 }; 82 }; 83 84 cpu1: cpu@100 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a520"; 87 reg = <0x0 0x100>; 88 89 clocks = <&cpufreq_hw 0>; 90 91 power-domains = <&cpu_pd1>; 92 power-domain-names = "psci"; 93 94 enable-method = "psci"; 95 next-level-cache = <&l2_0>; 96 capacity-dmips-mhz = <1024>; 97 dynamic-power-coefficient = <100>; 98 99 qcom,freq-domain = <&cpufreq_hw 0>; 100 101 #cooling-cells = <2>; 102 }; 103 104 cpu2: cpu@200 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a520"; 107 reg = <0x0 0x200>; 108 109 clocks = <&cpufreq_hw 0>; 110 111 power-domains = <&cpu_pd2>; 112 power-domain-names = "psci"; 113 114 enable-method = "psci"; 115 next-level-cache = <&l2_2>; 116 capacity-dmips-mhz = <1024>; 117 dynamic-power-coefficient = <100>; 118 119 qcom,freq-domain = <&cpufreq_hw 0>; 120 121 #cooling-cells = <2>; 122 123 l2_2: l2-cache { 124 compatible = "cache"; 125 cache-level = <2>; 126 cache-unified; 127 next-level-cache = <&l3_0>; 128 }; 129 }; 130 131 cpu3: cpu@300 { 132 device_type = "cpu"; 133 compatible = "arm,cortex-a520"; 134 reg = <0x0 0x300>; 135 136 clocks = <&cpufreq_hw 0>; 137 138 power-domains = <&cpu_pd3>; 139 power-domain-names = "psci"; 140 141 enable-method = "psci"; 142 next-level-cache = <&l2_2>; 143 capacity-dmips-mhz = <1024>; 144 dynamic-power-coefficient = <100>; 145 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 148 #cooling-cells = <2>; 149 }; 150 151 cpu4: cpu@400 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a720"; 154 reg = <0x0 0x400>; 155 156 clocks = <&cpufreq_hw 1>; 157 158 power-domains = <&cpu_pd4>; 159 power-domain-names = "psci"; 160 161 enable-method = "psci"; 162 next-level-cache = <&l2_4>; 163 capacity-dmips-mhz = <1670>; 164 dynamic-power-coefficient = <264>; 165 166 qcom,freq-domain = <&cpufreq_hw 1>; 167 168 #cooling-cells = <2>; 169 170 l2_4: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_0>; 175 }; 176 }; 177 178 cpu5: cpu@500 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a720"; 181 reg = <0x0 0x500>; 182 183 clocks = <&cpufreq_hw 1>; 184 185 power-domains = <&cpu_pd5>; 186 power-domain-names = "psci"; 187 188 enable-method = "psci"; 189 next-level-cache = <&l2_5>; 190 capacity-dmips-mhz = <1670>; 191 dynamic-power-coefficient = <264>; 192 193 qcom,freq-domain = <&cpufreq_hw 1>; 194 195 #cooling-cells = <2>; 196 197 l2_5: l2-cache { 198 compatible = "cache"; 199 cache-level = <2>; 200 cache-unified; 201 next-level-cache = <&l3_0>; 202 }; 203 }; 204 205 cpu6: cpu@600 { 206 device_type = "cpu"; 207 compatible = "arm,cortex-a720"; 208 reg = <0x0 0x600>; 209 210 clocks = <&cpufreq_hw 1>; 211 212 power-domains = <&cpu_pd6>; 213 power-domain-names = "psci"; 214 215 enable-method = "psci"; 216 next-level-cache = <&l2_6>; 217 capacity-dmips-mhz = <1670>; 218 dynamic-power-coefficient = <264>; 219 220 qcom,freq-domain = <&cpufreq_hw 1>; 221 222 #cooling-cells = <2>; 223 224 l2_6: l2-cache { 225 compatible = "cache"; 226 cache-level = <2>; 227 cache-unified; 228 next-level-cache = <&l3_0>; 229 }; 230 }; 231 232 cpu7: cpu@700 { 233 device_type = "cpu"; 234 compatible = "arm,cortex-a720"; 235 reg = <0x0 0x700>; 236 237 clocks = <&cpufreq_hw 2>; 238 239 power-domains = <&cpu_pd7>; 240 power-domain-names = "psci"; 241 242 enable-method = "psci"; 243 next-level-cache = <&l2_7>; 244 capacity-dmips-mhz = <1670>; 245 dynamic-power-coefficient = <287>; 246 247 qcom,freq-domain = <&cpufreq_hw 2>; 248 249 #cooling-cells = <2>; 250 251 l2_7: l2-cache { 252 compatible = "cache"; 253 cache-level = <2>; 254 cache-unified; 255 next-level-cache = <&l3_0>; 256 }; 257 }; 258 259 cpu-map { 260 cluster0 { 261 core0 { 262 cpu = <&cpu0>; 263 }; 264 265 core1 { 266 cpu = <&cpu1>; 267 }; 268 269 core2 { 270 cpu = <&cpu2>; 271 }; 272 273 core3 { 274 cpu = <&cpu3>; 275 }; 276 }; 277 278 cluster1 { 279 core0 { 280 cpu = <&cpu4>; 281 }; 282 283 core1 { 284 cpu = <&cpu5>; 285 }; 286 287 core2 { 288 cpu = <&cpu6>; 289 }; 290 }; 291 292 cluster2 { 293 core0 { 294 cpu = <&cpu7>; 295 }; 296 }; 297 }; 298 299 idle-states { 300 entry-method = "psci"; 301 302 silver_cpu_sleep_0: cpu-sleep-0-0 { 303 compatible = "arm,idle-state"; 304 idle-state-name = "pc"; 305 arm,psci-suspend-param = <0x40000003>; 306 entry-latency-us = <250>; 307 exit-latency-us = <700>; 308 min-residency-us = <5200>; 309 local-timer-stop; 310 }; 311 312 silver_cpu_sleep_1: cpu-sleep-0-1 { 313 compatible = "arm,idle-state"; 314 idle-state-name = "silver-rail-power-collapse"; 315 arm,psci-suspend-param = <0x40000004>; 316 entry-latency-us = <550>; 317 exit-latency-us = <750>; 318 min-residency-us = <6700>; 319 local-timer-stop; 320 }; 321 322 gold_cpu_sleep_0: cpu-sleep-1-0 { 323 compatible = "arm,idle-state"; 324 idle-state-name = "silver-power-collapse"; 325 arm,psci-suspend-param = <0x40000003>; 326 entry-latency-us = <400>; 327 exit-latency-us = <900>; 328 min-residency-us = <5511>; 329 local-timer-stop; 330 }; 331 332 gold_cpu_sleep_1: cpu-sleep-1-1 { 333 compatible = "arm,idle-state"; 334 idle-state-name = "gold-rail-power-collapse"; 335 arm,psci-suspend-param = <0x40000004>; 336 entry-latency-us = <600>; 337 exit-latency-us = <1300>; 338 min-residency-us = <8136>; 339 local-timer-stop; 340 }; 341 342 gold_plus_cpu_sleep_0: cpu-sleep-2-0 { 343 compatible = "arm,idle-state"; 344 idle-state-name = "gold-plus-rail-power-collapse"; 345 arm,psci-suspend-param = <0x40000004>; 346 entry-latency-us = <600>; 347 exit-latency-us = <1500>; 348 min-residency-us = <8551>; 349 local-timer-stop; 350 }; 351 }; 352 353 domain-idle-states { 354 cluster_sleep_0: cluster-sleep-0 { 355 compatible = "domain-idle-state"; 356 arm,psci-suspend-param = <0x41000044>; 357 entry-latency-us = <750>; 358 exit-latency-us = <2350>; 359 min-residency-us = <9144>; 360 }; 361 362 cluster_sleep_1: cluster-sleep-1 { 363 compatible = "domain-idle-state"; 364 arm,psci-suspend-param = <0x41003344>; 365 entry-latency-us = <2800>; 366 exit-latency-us = <4400>; 367 min-residency-us = <10150>; 368 }; 369 }; 370 }; 371 372 firmware { 373 scm: scm { 374 compatible = "qcom,scm-milos", "qcom,scm"; 375 qcom,dload-mode = <&tcsr 0x19000>; 376 }; 377 }; 378 379 clk_virt: interconnect-0 { 380 compatible = "qcom,milos-clk-virt"; 381 #interconnect-cells = <2>; 382 qcom,bcm-voters = <&apps_bcm_voter>; 383 }; 384 385 mc_virt: interconnect-1 { 386 compatible = "qcom,milos-mc-virt"; 387 #interconnect-cells = <2>; 388 qcom,bcm-voters = <&apps_bcm_voter>; 389 }; 390 391 memory@0 { 392 device_type = "memory"; 393 /* We expect the bootloader to fill in the size */ 394 reg = <0 0 0 0>; 395 }; 396 397 pmu-a520 { 398 compatible = "arm,cortex-a520-pmu"; 399 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 400 }; 401 402 pmu-a720 { 403 compatible = "arm,cortex-a720-pmu"; 404 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 405 }; 406 407 psci { 408 compatible = "arm,psci-1.0"; 409 method = "smc"; 410 411 cpu_pd0: power-domain-cpu0 { 412 #power-domain-cells = <0>; 413 power-domains = <&cluster_pd>; 414 domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; 415 }; 416 417 cpu_pd1: power-domain-cpu1 { 418 #power-domain-cells = <0>; 419 power-domains = <&cluster_pd>; 420 domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; 421 }; 422 423 cpu_pd2: power-domain-cpu2 { 424 #power-domain-cells = <0>; 425 power-domains = <&cluster_pd>; 426 domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; 427 }; 428 429 cpu_pd3: power-domain-cpu3 { 430 #power-domain-cells = <0>; 431 power-domains = <&cluster_pd>; 432 domain-idle-states = <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; 433 }; 434 435 cpu_pd4: power-domain-cpu4 { 436 #power-domain-cells = <0>; 437 power-domains = <&cluster_pd>; 438 domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; 439 }; 440 441 cpu_pd5: power-domain-cpu5 { 442 #power-domain-cells = <0>; 443 power-domains = <&cluster_pd>; 444 domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; 445 }; 446 447 cpu_pd6: power-domain-cpu6 { 448 #power-domain-cells = <0>; 449 power-domains = <&cluster_pd>; 450 domain-idle-states = <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; 451 }; 452 453 cpu_pd7: power-domain-cpu7 { 454 #power-domain-cells = <0>; 455 power-domains = <&cluster_pd>; 456 domain-idle-states = <&gold_plus_cpu_sleep_0>; 457 }; 458 459 cluster_pd: power-domain-cluster { 460 #power-domain-cells = <0>; 461 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 462 }; 463 }; 464 465 reserved-memory { 466 #address-cells = <2>; 467 #size-cells = <2>; 468 ranges; 469 470 gunyah_hyp_mem: gunyah-hyp-region@80000000 { 471 reg = <0x0 0x80000000 0x0 0xe00000>; 472 no-map; 473 }; 474 475 xbl_sc_mem: xbl-sc-region@81800000 { 476 reg = <0x0 0x81800000 0x0 0x40000>; 477 no-map; 478 }; 479 480 cpucp_fw_mem: cpucp-fw-region@81840000 { 481 reg = <0x0 0x81840000 0x0 0x1c0000>; 482 no-map; 483 }; 484 485 xbl_dtlog_mem: xbl-dtlog-region@81a00000 { 486 reg = <0x0 0x81a00000 0x0 0x40000>; 487 no-map; 488 }; 489 490 xbl_ramdump_mem: xbl-ramdump-region@81a40000 { 491 reg = <0x0 0x81a40000 0x0 0x1c0000>; 492 no-map; 493 }; 494 495 aop_image_mem: aop-image-region@81c00000 { 496 reg = <0x0 0x81c00000 0x0 0x60000>; 497 no-map; 498 }; 499 500 aop_cmd_db_mem: aop-cmd-db-region@81c60000 { 501 compatible = "qcom,cmd-db"; 502 reg = <0x0 0x81c60000 0x0 0x20000>; 503 no-map; 504 }; 505 506 aop_config_mem: aop-config-region@81c80000 { 507 reg = <0x0 0x81c80000 0x0 0x20000>; 508 no-map; 509 }; 510 511 tme_crash_dump_mem: tme-crash-dump-region@81ca0000 { 512 reg = <0x0 0x81ca0000 0x0 0x40000>; 513 no-map; 514 }; 515 516 tme_log_mem: tme-log-region@81ce0000 { 517 reg = <0x0 0x81ce0000 0x0 0x4000>; 518 no-map; 519 }; 520 521 uefi_log_mem: uefi-log-region@81ce4000 { 522 reg = <0x0 0x81ce4000 0x0 0x10000>; 523 no-map; 524 }; 525 526 chipinfo_mem: chipinfo-region@81cf4000 { 527 reg = <0x0 0x81cf4000 0x0 0x1000>; 528 no-map; 529 }; 530 531 secdata_apss_mem: secdata-apss-region@81cff000 { 532 reg = <0x0 0x81cff000 0x0 0x1000>; 533 no-map; 534 }; 535 536 smem_mem: smem-region@81d00000 { 537 compatible = "qcom,smem"; 538 reg = <0x0 0x81d00000 0x0 0x200000>; 539 hwlocks = <&tcsr_mutex 3>; 540 no-map; 541 }; 542 543 adsp_mhi_mem: adsp-mhi-region@81f00000 { 544 reg = <0x0 0x81f00000 0x0 0x20000>; 545 no-map; 546 }; 547 548 pvm_fw_mem: pvm-fw-region@824a0000 { 549 reg = <0x0 0x824a0000 0x0 0x100000>; 550 no-map; 551 }; 552 553 hyp_mem_database_mem: hyp-mem-database-region@825a0000 { 554 reg = <0x0 0x825a0000 0x0 0x60000>; 555 no-map; 556 }; 557 558 global_sync_mem: global-sync-region@82600000 { 559 reg = <0x0 0x82600000 0x0 0x100000>; 560 no-map; 561 }; 562 563 tz_stat_mem: tz-stat-region@82700000 { 564 reg = <0x0 0x82700000 0x0 0x100000>; 565 no-map; 566 }; 567 568 qdss_apps_mem: qdss-apps-region@82800000 { 569 reg = <0x0 0x82800000 0x0 0x2000000>; 570 reusable; 571 }; 572 573 mpss_mem: mpss-region@8ac00000 { 574 reg = <0x0 0x8ac00000 0x0 0xe600000>; 575 no-map; 576 }; 577 578 q6_mpss_dtb_mem: q6-mpss-dtb-region@99200000 { 579 reg = <0x0 0x99200000 0x0 0x80000>; 580 no-map; 581 }; 582 583 q6_adsp_dtb_mem: q6-adsp-dtb-region@99280000 { 584 reg = <0x0 0x99280000 0x0 0x80000>; 585 no-map; 586 }; 587 588 adspslpi_mem: adspslpi-region@99300000 { 589 reg = <0x0 0x99300000 0x0 0x2800000>; 590 no-map; 591 }; 592 593 wpss_mem: wpss-region@9bb00000 { 594 reg = <0x0 0x9bb00000 0x0 0x1900000>; 595 no-map; 596 }; 597 598 video_mem: video-region@9d400000 { 599 reg = <0x0 0x9d400000 0x0 0x700000>; 600 no-map; 601 }; 602 603 cdsp_mem: cdsp-region@9db00000 { 604 reg = <0x0 0x9db00000 0x0 0xf00000>; 605 no-map; 606 }; 607 608 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9ea00000 { 609 reg = <0x0 0x9ea00000 0x0 0x80000>; 610 no-map; 611 }; 612 613 ipa_fw_mem: ipa-fw-region@9ea80000 { 614 reg = <0x0 0x9ea80000 0x0 0x10000>; 615 no-map; 616 }; 617 618 ipa_gsi_mem: ipa-gsi-region@9ea90000 { 619 reg = <0x0 0x9ea90000 0x0 0xa000>; 620 no-map; 621 }; 622 623 gpu_microcode_mem: gpu-microcode-region@9ea9a000 { 624 reg = <0x0 0x9ea9a000 0x0 0x2000>; 625 no-map; 626 }; 627 628 camera_mem: camera-region@9eb00000 { 629 reg = <0x0 0x9eb00000 0x0 0x800000>; 630 no-map; 631 }; 632 633 wlan_msa_mem: wlan-msa-region@a6400000 { 634 reg = <0x0 0xa6400000 0x0 0xc00000>; 635 no-map; 636 }; 637 638 cpusys_vm_mem: cpusys-vm-region@e0600000 { 639 reg = <0x0 0xe0600000 0x0 0x400000>; 640 no-map; 641 }; 642 643 rmtfs_mem: rmtfs@e1f00000 { 644 compatible = "qcom,rmtfs-mem"; 645 reg = <0x0 0xe1f00000 0x0 0x600000>; 646 no-map; 647 648 qcom,client-id = <1>; 649 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 650 }; 651 652 qtee_mem: qtee-region@e8900000 { 653 reg = <0x0 0xe8900000 0x0 0x500000>; 654 no-map; 655 }; 656 657 tags_mem: tags-region@e8e00000 { 658 reg = <0x0 0xe8e00000 0x0 0x700000>; 659 no-map; 660 }; 661 662 trusted_apps_mem: trusted-apps-region@e9500000 { 663 reg = <0x0 0xe9500000 0x0 0x1200000>; 664 no-map; 665 }; 666 }; 667 668 smp2p-adsp { 669 compatible = "qcom,smp2p"; 670 qcom,smem = <443>, <429>; 671 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 672 IPCC_MPROC_SIGNAL_SMP2P 673 IRQ_TYPE_EDGE_RISING>; 674 mboxes = <&ipcc IPCC_CLIENT_LPASS 675 IPCC_MPROC_SIGNAL_SMP2P>; 676 677 qcom,local-pid = <0>; 678 qcom,remote-pid = <2>; 679 680 smp2p_adsp_out: master-kernel { 681 qcom,entry-name = "master-kernel"; 682 #qcom,smem-state-cells = <1>; 683 }; 684 685 smp2p_adsp_in: slave-kernel { 686 qcom,entry-name = "slave-kernel"; 687 interrupt-controller; 688 #interrupt-cells = <2>; 689 }; 690 }; 691 692 smp2p-cdsp { 693 compatible = "qcom,smp2p"; 694 qcom,smem = <94>, <432>; 695 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 696 IPCC_MPROC_SIGNAL_SMP2P 697 IRQ_TYPE_EDGE_RISING>; 698 mboxes = <&ipcc IPCC_CLIENT_CDSP 699 IPCC_MPROC_SIGNAL_SMP2P>; 700 701 qcom,local-pid = <0>; 702 qcom,remote-pid = <5>; 703 704 smp2p_cdsp_out: master-kernel { 705 qcom,entry-name = "master-kernel"; 706 #qcom,smem-state-cells = <1>; 707 }; 708 709 smp2p_cdsp_in: slave-kernel { 710 qcom,entry-name = "slave-kernel"; 711 interrupt-controller; 712 #interrupt-cells = <2>; 713 }; 714 }; 715 716 smp2p-modem { 717 compatible = "qcom,smp2p"; 718 qcom,smem = <435>, <428>; 719 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 720 IPCC_MPROC_SIGNAL_SMP2P 721 IRQ_TYPE_EDGE_RISING>; 722 mboxes = <&ipcc IPCC_CLIENT_MPSS 723 IPCC_MPROC_SIGNAL_SMP2P>; 724 725 qcom,local-pid = <0>; 726 qcom,remote-pid = <1>; 727 728 smp2p_modem_out: master-kernel { 729 qcom,entry-name = "master-kernel"; 730 #qcom,smem-state-cells = <1>; 731 }; 732 733 smp2p_modem_in: slave-kernel { 734 qcom,entry-name = "slave-kernel"; 735 interrupt-controller; 736 #interrupt-cells = <2>; 737 }; 738 739 smp2p_ipa_out: ipa-ap-to-modem { 740 qcom,entry-name = "ipa"; 741 #qcom,smem-state-cells = <1>; 742 }; 743 744 smp2p_ipa_in: ipa-modem-to-ap { 745 qcom,entry-name = "ipa"; 746 interrupt-controller; 747 #interrupt-cells = <2>; 748 }; 749 }; 750 751 smp2p-wpss { 752 compatible = "qcom,smp2p"; 753 qcom,smem = <617>, <616>; 754 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 755 IPCC_MPROC_SIGNAL_SMP2P 756 IRQ_TYPE_EDGE_RISING>; 757 mboxes = <&ipcc IPCC_CLIENT_WPSS 758 IPCC_MPROC_SIGNAL_SMP2P>; 759 760 qcom,local-pid = <0>; 761 qcom,remote-pid = <13>; 762 763 smp2p_wpss_out: master-kernel { 764 qcom,entry-name = "master-kernel"; 765 #qcom,smem-state-cells = <1>; 766 }; 767 768 smp2p_wpss_in: slave-kernel { 769 qcom,entry-name = "slave-kernel"; 770 interrupt-controller; 771 #interrupt-cells = <2>; 772 }; 773 774 smp2p_wlan_out: wlan-ap-to-wpss { 775 qcom,entry-name = "wlan"; 776 #qcom,smem-state-cells = <1>; 777 }; 778 779 smp2p_wlan_in: wlan-wpss-to-ap { 780 qcom,entry-name = "wlan"; 781 interrupt-controller; 782 #interrupt-cells = <2>; 783 }; 784 }; 785 786 soc: soc@0 { 787 compatible = "simple-bus"; 788 789 #address-cells = <2>; 790 #size-cells = <2>; 791 dma-ranges = <0 0 0 0 0x10 0>; 792 ranges = <0 0 0 0 0x10 0>; 793 794 gcc: clock-controller@100000 { 795 compatible = "qcom,milos-gcc"; 796 reg = <0x0 0x00100000 0x0 0x1f4200>; 797 798 clocks = <&rpmhcc RPMH_CXO_CLK>, 799 <&sleep_clk>, 800 <0>, /* pcie_0_pipe_clk */ 801 <0>, /* pcie_1_pipe_clk */ 802 <&ufs_mem_phy 0>, 803 <&ufs_mem_phy 1>, 804 <&ufs_mem_phy 2>, 805 <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */ 806 807 power-domains = <&rpmhpd RPMHPD_CX>; 808 809 #clock-cells = <1>; 810 #reset-cells = <1>; 811 #power-domain-cells = <1>; 812 }; 813 814 ipcc: mailbox@405000 { 815 compatible = "qcom,milos-ipcc", "qcom,ipcc"; 816 reg = <0x0 0x00405000 0x0 0x1000>; 817 818 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH 0>; 819 interrupt-controller; 820 #interrupt-cells = <3>; 821 822 #mbox-cells = <2>; 823 }; 824 825 gpi_dma1: dma-controller@800000 { 826 compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; 827 reg = <0x0 0x00800000 0x0 0x60000>; 828 829 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>, 830 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>, 831 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, 832 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, 833 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, 834 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, 835 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, 836 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 0>, 837 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH 0>, 838 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>, 839 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>, 840 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; 841 842 dma-channels = <12>; 843 dma-channel-mask = <0x3f>; 844 #dma-cells = <3>; 845 846 iommus = <&apps_smmu 0x36 0x0>; 847 dma-coherent; 848 }; 849 850 qupv3_id_1: geniqup@8c0000 { 851 compatible = "qcom,geni-se-qup"; 852 reg = <0x0 0x008c0000 0x0 0x2000>; 853 854 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 855 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 856 clock-names = "m-ahb", 857 "s-ahb"; 858 859 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 860 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; 861 interconnect-names = "qup-core"; 862 863 iommus = <&apps_smmu 0x23 0>; 864 865 dma-coherent; 866 867 #address-cells = <2>; 868 #size-cells = <2>; 869 ranges; 870 871 status = "disabled"; 872 873 i2c7: i2c@880000 { 874 compatible = "qcom,geni-i2c"; 875 reg = <0x0 0x00880000 0x0 0x4000>; 876 877 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH 0>; 878 879 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 880 clock-names = "se"; 881 882 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 883 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 884 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 885 &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 886 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 887 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 888 interconnect-names = "qup-core", 889 "qup-config", 890 "qup-memory"; 891 892 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 893 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 894 dma-names = "tx", 895 "rx"; 896 897 pinctrl-0 = <&qup_i2c7_data_clk>; 898 pinctrl-names = "default"; 899 900 #address-cells = <1>; 901 #size-cells = <0>; 902 903 status = "disabled"; 904 }; 905 906 uart11: serial@890000 { 907 compatible = "qcom,geni-uart"; 908 reg = <0x0 0x00890000 0x0 0x4000>; 909 910 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 911 912 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 913 clock-names = "se"; 914 915 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 916 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 917 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 918 &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 919 interconnect-names = "qup-core", 920 "qup-config"; 921 922 pinctrl-0 = <&qup_uart11_default>, <&qup_uart11_cts_rts>; 923 pinctrl-names = "default"; 924 925 status = "disabled"; 926 }; 927 }; 928 929 gpi_dma0: dma-controller@a00000 { 930 compatible = "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; 931 reg = <0x0 0x00a00000 0x0 0x60000>; 932 933 interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH 0>, 934 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, 935 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, 936 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, 937 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, 938 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, 939 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>, 940 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, 941 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, 942 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>, 943 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH 0>, 944 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH 0>; 945 946 dma-channels = <12>; 947 dma-channel-mask = <0x3e>; 948 #dma-cells = <3>; 949 950 iommus = <&apps_smmu 0x576 0x0>; 951 dma-coherent; 952 }; 953 954 qupv3_id_0: geniqup@ac0000 { 955 compatible = "qcom,geni-se-qup"; 956 reg = <0x0 0x00ac0000 0x0 0x2000>; 957 958 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 959 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 960 clock-names = "m-ahb", 961 "s-ahb"; 962 963 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 964 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; 965 interconnect-names = "qup-core"; 966 967 iommus = <&apps_smmu 0x563 0>; 968 969 dma-coherent; 970 971 #address-cells = <2>; 972 #size-cells = <2>; 973 ranges; 974 975 status = "disabled"; 976 977 spi0: spi@a80000 { 978 compatible = "qcom,geni-spi"; 979 reg = <0x0 0x00a80000 0x0 0x4000>; 980 981 interrupts = <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>; 982 983 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 984 clock-names = "se"; 985 986 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 987 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 988 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 989 &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 990 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 991 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 992 interconnect-names = "qup-core", 993 "qup-config", 994 "qup-memory"; 995 996 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 997 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 998 dma-names = "tx", 999 "rx"; 1000 1001 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1002 pinctrl-names = "default"; 1003 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 1007 status = "disabled"; 1008 }; 1009 1010 i2c1: i2c@a84000 { 1011 compatible = "qcom,geni-i2c"; 1012 reg = <0x0 0x00a84000 0x0 0x4000>; 1013 1014 interrupts = <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH 0>; 1015 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1017 clock-names = "se"; 1018 1019 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1020 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1021 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1022 &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 1023 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1024 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1025 interconnect-names = "qup-core", 1026 "qup-config", 1027 "qup-memory"; 1028 1029 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1030 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1031 dma-names = "tx", 1032 "rx"; 1033 1034 pinctrl-0 = <&qup_i2c1_data_clk>; 1035 pinctrl-names = "default"; 1036 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 1040 status = "disabled"; 1041 }; 1042 1043 i2c3: i2c@a8c000 { 1044 compatible = "qcom,geni-i2c"; 1045 reg = <0x0 0x00a8c000 0x0 0x4000>; 1046 1047 interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH 0>; 1048 1049 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1050 clock-names = "se"; 1051 1052 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1053 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1054 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1055 &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, 1056 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1057 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1058 interconnect-names = "qup-core", 1059 "qup-config", 1060 "qup-memory"; 1061 1062 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1063 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1064 dma-names = "tx", 1065 "rx"; 1066 1067 pinctrl-0 = <&qup_i2c3_data_clk>; 1068 pinctrl-names = "default"; 1069 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 1073 status = "disabled"; 1074 }; 1075 1076 uart5: serial@a94000 { 1077 compatible = "qcom,geni-debug-uart"; 1078 reg = <0x0 0x00a94000 0x0 0x4000>; 1079 1080 interrupts = <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH 0>; 1081 1082 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1083 clock-names = "se"; 1084 1085 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1086 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1087 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1088 &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1089 interconnect-names = "qup-core", 1090 "qup-config"; 1091 1092 pinctrl-0 = <&qup_uart5_default>; 1093 pinctrl-names = "default"; 1094 1095 status = "disabled"; 1096 }; 1097 }; 1098 1099 rng: rng@10c3000 { 1100 compatible = "qcom,milos-trng", "qcom,trng"; 1101 reg = <0x0 0x010c3000 0x0 0x1000>; 1102 }; 1103 1104 mmss_noc: interconnect@1400000 { 1105 compatible = "qcom,milos-mmss-noc"; 1106 reg = <0x0 0x01400000 0x0 0xdb800>; 1107 #interconnect-cells = <2>; 1108 qcom,bcm-voters = <&apps_bcm_voter>; 1109 }; 1110 1111 cnoc_main: interconnect@1500000 { 1112 compatible = "qcom,milos-cnoc-main"; 1113 reg = <0x0 0x01500000 0x0 0x14400>; 1114 #interconnect-cells = <2>; 1115 qcom,bcm-voters = <&apps_bcm_voter>; 1116 }; 1117 1118 cnoc_cfg: interconnect@1600000 { 1119 compatible = "qcom,milos-cnoc-cfg"; 1120 reg = <0x0 0x01600000 0x0 0x6e00>; 1121 #interconnect-cells = <2>; 1122 qcom,bcm-voters = <&apps_bcm_voter>; 1123 }; 1124 1125 system_noc: interconnect@1680000 { 1126 compatible = "qcom,milos-system-noc"; 1127 reg = <0x0 0x01680000 0x0 0x40000>; 1128 #interconnect-cells = <2>; 1129 qcom,bcm-voters = <&apps_bcm_voter>; 1130 }; 1131 1132 pcie_anoc: interconnect@16c0000 { 1133 compatible = "qcom,milos-pcie-anoc"; 1134 reg = <0x0 0x016c0000 0x0 0x12400>; 1135 #interconnect-cells = <2>; 1136 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1137 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1138 qcom,bcm-voters = <&apps_bcm_voter>; 1139 }; 1140 1141 aggre1_noc: interconnect@16e0000 { 1142 compatible = "qcom,milos-aggre1-noc"; 1143 reg = <0x0 0x016e0000 0x0 0x16400>; 1144 #interconnect-cells = <2>; 1145 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1146 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 1147 qcom,bcm-voters = <&apps_bcm_voter>; 1148 }; 1149 1150 aggre2_noc: interconnect@1700000 { 1151 compatible = "qcom,milos-aggre2-noc"; 1152 reg = <0x0 0x01700000 0x0 0x1f400>; 1153 #interconnect-cells = <2>; 1154 clocks = <&rpmhcc RPMH_IPA_CLK>; 1155 qcom,bcm-voters = <&apps_bcm_voter>; 1156 }; 1157 1158 ufs_mem_phy: phy@1d80000 { 1159 compatible = "qcom,milos-qmp-ufs-phy"; 1160 reg = <0x0 0x01d80000 0x0 0x2000>; 1161 1162 clocks = <&rpmhcc RPMH_CXO_CLK>, 1163 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1164 <&tcsr TCSR_UFS_CLKREF_EN>; 1165 clock-names = "ref", 1166 "ref_aux", 1167 "qref"; 1168 1169 resets = <&ufs_mem_hc 0>; 1170 reset-names = "ufsphy"; 1171 1172 power-domains = <&gcc UFS_MEM_PHY_GDSC>; 1173 1174 #clock-cells = <1>; 1175 #phy-cells = <0>; 1176 1177 status = "disabled"; 1178 }; 1179 1180 ufs_mem_hc: ufshc@1d84000 { 1181 compatible = "qcom,milos-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1182 reg = <0x0 0x01d84000 0x0 0x3000>; 1183 1184 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 1185 1186 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1187 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1188 <&gcc GCC_UFS_PHY_AHB_CLK>, 1189 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1190 <&tcsr TCSR_UFS_PAD_CLKREF_EN>, 1191 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1192 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1193 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1194 clock-names = "core_clk", 1195 "bus_aggr_clk", 1196 "iface_clk", 1197 "core_clk_unipro", 1198 "ref_clk", 1199 "tx_lane0_sync_clk", 1200 "rx_lane0_sync_clk", 1201 "rx_lane1_sync_clk"; 1202 1203 resets = <&gcc GCC_UFS_PHY_BCR>; 1204 reset-names = "rst"; 1205 1206 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1207 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1208 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1209 &cnoc_cfg SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1210 interconnect-names = "ufs-ddr", 1211 "cpu-ufs"; 1212 1213 power-domains = <&gcc UFS_PHY_GDSC>; 1214 required-opps = <&rpmhpd_opp_nom>; 1215 1216 operating-points-v2 = <&ufs_opp_table>; 1217 1218 iommus = <&apps_smmu 0x60 0>; 1219 1220 dma-coherent; 1221 1222 lanes-per-direction = <2>; 1223 qcom,ice = <&ice>; 1224 1225 phys = <&ufs_mem_phy>; 1226 phy-names = "ufsphy"; 1227 1228 #reset-cells = <1>; 1229 1230 status = "disabled"; 1231 1232 ufs_opp_table: opp-table { 1233 compatible = "operating-points-v2"; 1234 1235 opp-75000000 { 1236 opp-hz = /bits/ 64 <75000000>, 1237 /bits/ 64 <0>, 1238 /bits/ 64 <0>, 1239 /bits/ 64 <75000000>, 1240 /bits/ 64 <0>, 1241 /bits/ 64 <0>, 1242 /bits/ 64 <0>, 1243 /bits/ 64 <0>; 1244 required-opps = <&rpmhpd_opp_low_svs>; 1245 }; 1246 1247 opp-150000000 { 1248 opp-hz = /bits/ 64 <150000000>, 1249 /bits/ 64 <0>, 1250 /bits/ 64 <0>, 1251 /bits/ 64 <150000000>, 1252 /bits/ 64 <0>, 1253 /bits/ 64 <0>, 1254 /bits/ 64 <0>, 1255 /bits/ 64 <0>; 1256 required-opps = <&rpmhpd_opp_svs>; 1257 }; 1258 1259 opp-300000000 { 1260 opp-hz = /bits/ 64 <300000000>, 1261 /bits/ 64 <0>, 1262 /bits/ 64 <0>, 1263 /bits/ 64 <300000000>, 1264 /bits/ 64 <0>, 1265 /bits/ 64 <0>, 1266 /bits/ 64 <0>, 1267 /bits/ 64 <0>; 1268 required-opps = <&rpmhpd_opp_nom>; 1269 }; 1270 }; 1271 }; 1272 1273 ice: crypto@1d88000 { 1274 compatible = "qcom,milos-inline-crypto-engine", 1275 "qcom,inline-crypto-engine"; 1276 reg = <0x0 0x01d88000 0x0 0x18000>; 1277 1278 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1279 }; 1280 1281 tcsr_mutex: hwlock@1f40000 { 1282 compatible = "qcom,tcsr-mutex"; 1283 reg = <0x0 0x01f40000 0x0 0x20000>; 1284 1285 #hwlock-cells = <1>; 1286 }; 1287 1288 tcsr: clock-controller@1fc0000 { 1289 compatible = "qcom,milos-tcsr", "syscon"; 1290 reg = <0x0 0x01fc0000 0x0 0xa0000>; 1291 1292 clocks = <&rpmhcc RPMH_CXO_CLK>; 1293 1294 #clock-cells = <1>; 1295 #reset-cells = <1>; 1296 }; 1297 1298 remoteproc_adsp: remoteproc@3000000 { 1299 compatible = "qcom,milos-adsp-pas"; 1300 reg = <0x0 0x03000000 0x0 0x10000>; 1301 1302 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1303 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1304 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1305 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1306 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 1307 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 1308 interrupt-names = "wdog", 1309 "fatal", 1310 "ready", 1311 "handover", 1312 "stop-ack", 1313 "shutdown-ack"; 1314 1315 clocks = <&rpmhcc RPMH_CXO_CLK>; 1316 clock-names = "xo"; 1317 1318 power-domains = <&rpmhpd RPMHPD_LCX>, 1319 <&rpmhpd RPMHPD_LMX>; 1320 power-domain-names = "lcx", 1321 "lmx"; 1322 1323 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 1324 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1325 1326 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 1327 1328 qcom,qmp = <&aoss_qmp>; 1329 1330 qcom,smem-states = <&smp2p_adsp_out 0>; 1331 qcom,smem-state-names = "stop"; 1332 1333 status = "disabled"; 1334 1335 glink-edge { 1336 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1337 IPCC_MPROC_SIGNAL_GLINK_QMP 1338 IRQ_TYPE_EDGE_RISING>; 1339 mboxes = <&ipcc IPCC_CLIENT_LPASS 1340 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1341 1342 label = "lpass"; 1343 qcom,remote-pid = <2>; 1344 1345 fastrpc { 1346 compatible = "qcom,fastrpc"; 1347 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1348 label = "adsp"; 1349 qcom,non-secure-domain; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 1353 compute-cb@3 { 1354 compatible = "qcom,fastrpc-compute-cb"; 1355 reg = <3>; 1356 iommus = <&apps_smmu 0x1003 0x0>, 1357 <&apps_smmu 0x1063 0x0>; 1358 dma-coherent; 1359 }; 1360 1361 compute-cb@4 { 1362 compatible = "qcom,fastrpc-compute-cb"; 1363 reg = <4>; 1364 iommus = <&apps_smmu 0x1004 0x0>, 1365 <&apps_smmu 0x1064 0x0>; 1366 dma-coherent; 1367 }; 1368 1369 compute-cb@5 { 1370 compatible = "qcom,fastrpc-compute-cb"; 1371 reg = <5>; 1372 iommus = <&apps_smmu 0x1005 0x0>, 1373 <&apps_smmu 0x1065 0x0>; 1374 dma-coherent; 1375 }; 1376 1377 compute-cb@6 { 1378 compatible = "qcom,fastrpc-compute-cb"; 1379 reg = <6>; 1380 iommus = <&apps_smmu 0x1006 0x0>, 1381 <&apps_smmu 0x1066 0x0>; 1382 dma-coherent; 1383 }; 1384 1385 compute-cb@7 { 1386 compatible = "qcom,fastrpc-compute-cb"; 1387 reg = <7>; 1388 iommus = <&apps_smmu 0x1007 0x0>, 1389 <&apps_smmu 0x1067 0x0>; 1390 dma-coherent; 1391 }; 1392 }; 1393 1394 gpr { 1395 compatible = "qcom,gpr"; 1396 qcom,glink-channels = "adsp_apps"; 1397 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 1398 qcom,intents = <512 20>; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 1402 q6apm: service@1 { 1403 compatible = "qcom,q6apm"; 1404 reg = <GPR_APM_MODULE_IID>; 1405 #sound-dai-cells = <0>; 1406 qcom,protection-domain = "avs/audio", 1407 "msm/adsp/audio_pd"; 1408 1409 q6apmbedai: bedais { 1410 compatible = "qcom,q6apm-lpass-dais"; 1411 #sound-dai-cells = <1>; 1412 }; 1413 1414 q6apmdai: dais { 1415 compatible = "qcom,q6apm-dais"; 1416 iommus = <&apps_smmu 0x1001 0x0>, 1417 <&apps_smmu 0x1061 0x0>; 1418 }; 1419 }; 1420 1421 q6prm: service@2 { 1422 compatible = "qcom,q6prm"; 1423 reg = <GPR_PRM_MODULE_IID>; 1424 qcom,protection-domain = "avs/audio", 1425 "msm/adsp/audio_pd"; 1426 1427 q6prmcc: clock-controller { 1428 compatible = "qcom,q6prm-lpass-clocks"; 1429 #clock-cells = <2>; 1430 }; 1431 }; 1432 }; 1433 }; 1434 }; 1435 1436 lpass_tlmm: pinctrl@3440000 { 1437 compatible = "qcom,milos-lpass-lpi-pinctrl"; 1438 reg = <0x0 0x03440000 0x0 0x20000>, 1439 <0x0 0x034d0000 0x0 0x10000>; 1440 gpio-controller; 1441 #gpio-cells = <2>; 1442 gpio-ranges = <&lpass_tlmm 0 0 23>; 1443 1444 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1445 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1446 clock-names = "core", 1447 "audio"; 1448 1449 tx_swr_active: tx-swr-active-state { 1450 clk-pins { 1451 pins = "gpio0"; 1452 function = "swr_tx_clk"; 1453 drive-strength = <4>; 1454 slew-rate = <1>; 1455 bias-disable; 1456 }; 1457 1458 data-pins { 1459 pins = "gpio1", "gpio2", "gpio14"; 1460 function = "swr_tx_data"; 1461 drive-strength = <4>; 1462 slew-rate = <1>; 1463 bias-bus-hold; 1464 }; 1465 }; 1466 1467 rx_swr_active: rx-swr-active-state { 1468 clk-pins { 1469 pins = "gpio3"; 1470 function = "swr_rx_clk"; 1471 drive-strength = <2>; 1472 slew-rate = <1>; 1473 bias-disable; 1474 }; 1475 1476 data-pins { 1477 pins = "gpio4", "gpio5"; 1478 function = "swr_rx_data"; 1479 drive-strength = <2>; 1480 slew-rate = <1>; 1481 bias-bus-hold; 1482 }; 1483 }; 1484 1485 lpi_i2s2_active: lpi-i2s2-active-state { 1486 clk-pins { 1487 pins = "gpio10"; 1488 function = "i2s2_clk"; 1489 drive-strength = <8>; 1490 bias-disable; 1491 output-high; 1492 }; 1493 1494 ws-pins { 1495 pins = "gpio11"; 1496 function = "i2s2_ws"; 1497 drive-strength = <8>; 1498 bias-disable; 1499 output-high; 1500 }; 1501 1502 data-pins { 1503 pins = "gpio12", "gpio13"; 1504 function = "i2s2_data"; 1505 drive-strength = <8>; 1506 bias-disable; 1507 output-high; 1508 }; 1509 }; 1510 1511 lpi_i2s2_sleep: lpi-i2s2-sleep-state { 1512 clk-pins { 1513 pins = "gpio10"; 1514 function = "i2s2_clk"; 1515 drive-strength = <2>; 1516 bias-pull-down; 1517 input-enable; 1518 }; 1519 1520 ws-pins { 1521 pins = "gpio11"; 1522 function = "i2s2_ws"; 1523 drive-strength = <2>; 1524 bias-pull-down; 1525 input-enable; 1526 }; 1527 1528 data-pins { 1529 pins = "gpio12", "gpio13"; 1530 function = "i2s2_data"; 1531 drive-strength = <2>; 1532 bias-pull-down; 1533 input-enable; 1534 }; 1535 }; 1536 }; 1537 1538 lpass_ag_noc: interconnect@3c40000 { 1539 compatible = "qcom,milos-lpass-ag-noc"; 1540 reg = <0x0 0x03c40000 0x0 0x17200>; 1541 #interconnect-cells = <2>; 1542 qcom,bcm-voters = <&apps_bcm_voter>; 1543 }; 1544 1545 gpucc: clock-controller@3d90000 { 1546 compatible = "qcom,milos-gpucc"; 1547 reg = <0x0 0x03d90000 0x0 0x9800>; 1548 1549 clocks = <&rpmhcc RPMH_CXO_CLK>, 1550 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1551 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1552 1553 #clock-cells = <1>; 1554 #reset-cells = <1>; 1555 #power-domain-cells = <1>; 1556 }; 1557 1558 adreno_smmu: iommu@3da0000 { 1559 compatible = "qcom,milos-smmu-500", "qcom,adreno-smmu", 1560 "qcom,smmu-500", "arm,mmu-500"; 1561 reg = <0x0 0x03da0000 0x0 0x40000>; 1562 #iommu-cells = <2>; 1563 #global-interrupts = <1>; 1564 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>, 1565 <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>, 1566 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH 0>, 1567 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>, 1568 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>, 1569 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>, 1570 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>, 1571 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>, 1572 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>, 1573 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>, 1574 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>, 1575 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>, 1576 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH 0>, 1577 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH 0>, 1578 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH 0>, 1579 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH 0>, 1580 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH 0>, 1581 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH 0>, 1582 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH 0>, 1583 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>, 1584 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH 0>, 1585 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH 0>, 1586 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH 0>, 1587 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH 0>, 1588 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>, 1589 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH 0>; 1590 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1591 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1592 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1593 <&gpucc GPU_CC_AHB_CLK>; 1594 clock-names = "hlos", 1595 "bus", 1596 "iface", 1597 "ahb"; 1598 power-domains = <&gpucc GPU_CC_CX_GDSC>; 1599 dma-coherent; 1600 }; 1601 1602 remoteproc_mpss: remoteproc@4080000 { 1603 compatible = "qcom,milos-mpss-pas"; 1604 reg = <0x0 0x04080000 0x0 0x10000>; 1605 1606 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, 1607 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1608 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1609 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1610 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1611 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1612 interrupt-names = "wdog", 1613 "fatal", 1614 "ready", 1615 "handover", 1616 "stop-ack", 1617 "shutdown-ack"; 1618 1619 clocks = <&rpmhcc RPMH_CXO_CLK>; 1620 clock-names = "xo"; 1621 1622 power-domains = <&rpmhpd RPMHPD_CX>, 1623 <&rpmhpd RPMHPD_MSS>; 1624 power-domain-names = "cx", 1625 "mss"; 1626 1627 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 1628 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1629 1630 memory-region = <&mpss_mem>; 1631 1632 qcom,qmp = <&aoss_qmp>; 1633 1634 qcom,smem-states = <&smp2p_modem_out 0>; 1635 qcom,smem-state-names = "stop"; 1636 1637 status = "disabled"; 1638 1639 glink-edge { 1640 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1641 IPCC_MPROC_SIGNAL_GLINK_QMP 1642 IRQ_TYPE_EDGE_RISING>; 1643 mboxes = <&ipcc IPCC_CLIENT_MPSS 1644 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1645 1646 label = "mpss"; 1647 qcom,remote-pid = <1>; 1648 }; 1649 }; 1650 1651 sdhc_2: mmc@8804000 { 1652 compatible = "qcom,milos-sdhci", "qcom,sdhci-msm-v5"; 1653 reg = <0x0 0x08804000 0x0 0x1000>; 1654 1655 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>, 1656 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH 0>; 1657 interrupt-names = "hc_irq", 1658 "pwr_irq"; 1659 1660 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1661 <&gcc GCC_SDCC2_APPS_CLK>, 1662 <&rpmhcc RPMH_CXO_CLK>; 1663 clock-names = "iface", 1664 "core", 1665 "xo"; 1666 1667 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 1668 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1669 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1670 &cnoc_cfg SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1671 interconnect-names = "sdhc-ddr", 1672 "cpu-sdhc"; 1673 1674 power-domains = <&rpmhpd RPMHPD_CX>; 1675 operating-points-v2 = <&sdhc2_opp_table>; 1676 1677 iommus = <&apps_smmu 0x540 0>; 1678 1679 bus-width = <4>; 1680 1681 qcom,dll-config = <0x0007442c>; 1682 qcom,ddr-config = <0x80040868>; 1683 1684 dma-coherent; 1685 1686 status = "disabled"; 1687 1688 sdhc2_opp_table: opp-table { 1689 compatible = "operating-points-v2"; 1690 1691 opp-100000000 { 1692 opp-hz = /bits/ 64 <100000000>; 1693 required-opps = <&rpmhpd_opp_low_svs>; 1694 }; 1695 1696 opp-202000000 { 1697 opp-hz = /bits/ 64 <202000000>; 1698 required-opps = <&rpmhpd_opp_svs_l1>; 1699 }; 1700 }; 1701 }; 1702 1703 usb_1_hsphy: phy@88e3000 { 1704 compatible = "qcom,milos-snps-eusb2-phy", 1705 "qcom,sm8550-snps-eusb2-phy"; 1706 reg = <0x0 0x088e3000 0x0 0x154>; 1707 #phy-cells = <0>; 1708 1709 clocks = <&rpmhcc RPMH_CXO_CLK>; 1710 clock-names = "ref"; 1711 1712 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1713 1714 status = "disabled"; 1715 }; 1716 1717 remoteproc_wpss: remoteproc@8a00000 { 1718 compatible = "qcom,milos-wpss-pas"; 1719 reg = <0x0 0x08a00000 0x0 0x10000>; 1720 1721 interrupts-extended = <&intc GIC_SPI 579 IRQ_TYPE_EDGE_RISING 0>, 1722 <&smp2p_wpss_in 0 IRQ_TYPE_EDGE_RISING>, 1723 <&smp2p_wpss_in 1 IRQ_TYPE_EDGE_RISING>, 1724 <&smp2p_wpss_in 2 IRQ_TYPE_EDGE_RISING>, 1725 <&smp2p_wpss_in 3 IRQ_TYPE_EDGE_RISING>, 1726 <&smp2p_wpss_in 7 IRQ_TYPE_EDGE_RISING>; 1727 interrupt-names = "wdog", 1728 "fatal", 1729 "ready", 1730 "handover", 1731 "stop-ack", 1732 "shutdown-ack"; 1733 1734 clocks = <&rpmhcc RPMH_CXO_CLK>; 1735 clock-names = "xo"; 1736 1737 power-domains = <&rpmhpd RPMHPD_CX>, 1738 <&rpmhpd RPMHPD_MX>; 1739 power-domain-names = "cx", 1740 "mx"; 1741 1742 memory-region = <&wpss_mem>; 1743 1744 qcom,qmp = <&aoss_qmp>; 1745 1746 qcom,smem-states = <&smp2p_wpss_out 0>; 1747 qcom,smem-state-names = "stop"; 1748 1749 status = "disabled"; 1750 1751 glink-edge { 1752 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 1753 IPCC_MPROC_SIGNAL_GLINK_QMP 1754 IRQ_TYPE_EDGE_RISING>; 1755 mboxes = <&ipcc IPCC_CLIENT_WPSS 1756 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1757 1758 label = "wpss"; 1759 qcom,remote-pid = <13>; 1760 }; 1761 }; 1762 1763 usb_1: usb@a600000 { 1764 compatible = "qcom,milos-dwc3", "qcom,snps-dwc3"; 1765 reg = <0x0 0x0a600000 0x0 0xfc000>; 1766 1767 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1768 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1769 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1770 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1771 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1772 <&rpmhcc RPMH_CXO_CLK>; 1773 clock-names = "cfg_noc", 1774 "core", 1775 "iface", 1776 "sleep", 1777 "mock_utmi", 1778 "xo"; 1779 1780 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1781 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1782 assigned-clock-rates = <19200000>, <200000000>; 1783 1784 interrupts-extended = <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH 0>, 1785 <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH 0>, 1786 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1787 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1788 <&pdc 25 IRQ_TYPE_LEVEL_HIGH>; 1789 interrupt-names = "dwc_usb3", 1790 "pwr_event", 1791 "dp_hs_phy_irq", 1792 "dm_hs_phy_irq", 1793 "ss_phy_irq"; 1794 1795 iommus = <&apps_smmu 0x40 0x0>; 1796 power-domains = <&gcc USB30_PRIM_GDSC>; 1797 required-opps = <&rpmhpd_opp_nom>; 1798 1799 resets = <&gcc GCC_USB30_PRIM_BCR>; 1800 1801 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 1802 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1803 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1804 &cnoc_cfg SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1805 interconnect-names = "usb-ddr", "apps-usb"; 1806 1807 phys = <&usb_1_hsphy>; 1808 phy-names = "usb2-phy"; 1809 1810 snps,dis-u1-entry-quirk; 1811 snps,dis-u2-entry-quirk; 1812 snps,dis_enblslpm_quirk; 1813 snps,dis_u2_susphy_quirk; 1814 snps,dis_u3_susphy_quirk; 1815 snps,has-lpm-erratum; 1816 snps,hird-threshold = /bits/ 8 <0x0>; 1817 snps,is-utmi-l1-suspend; 1818 snps,parkmode-disable-ss-quirk; 1819 tx-fifo-resize; 1820 dma-coherent; 1821 usb-role-switch; 1822 1823 status = "disabled"; 1824 1825 ports { 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 1829 port@0 { 1830 reg = <0>; 1831 1832 usb_1_dwc3_hs: endpoint { 1833 }; 1834 }; 1835 }; 1836 }; 1837 1838 videocc: clock-controller@aaf0000 { 1839 compatible = "qcom,milos-videocc"; 1840 reg = <0x0 0x0aaf0000 0x0 0x10000>; 1841 1842 clocks = <&rpmhcc RPMH_CXO_CLK>, 1843 <&rpmhcc RPMH_CXO_CLK_A>, 1844 <&sleep_clk>, 1845 <&gcc GCC_VIDEO_AHB_CLK>; 1846 1847 #clock-cells = <1>; 1848 #reset-cells = <1>; 1849 #power-domain-cells = <1>; 1850 }; 1851 1852 cci0: cci@ac15000 { 1853 compatible = "qcom,milos-cci", "qcom,msm8996-cci"; 1854 reg = <0x0 0x0ac15000 0x0 0x1000>; 1855 interrupts = <GIC_SPI 426 IRQ_TYPE_EDGE_RISING 0>; 1856 power-domains = <&camcc CAM_CC_CAMSS_TOP_GDSC>; 1857 clocks = <&camcc CAM_CC_SOC_AHB_CLK>, 1858 <&camcc CAM_CC_CPAS_AHB_CLK>, 1859 <&camcc CAM_CC_CCI_0_CLK>; 1860 clock-names = "soc_ahb", 1861 "cpas_ahb", 1862 "cci"; 1863 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 1864 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 1865 pinctrl-names = "default", "sleep"; 1866 status = "disabled"; 1867 #address-cells = <1>; 1868 #size-cells = <0>; 1869 1870 cci0_i2c0: i2c-bus@0 { 1871 reg = <0>; 1872 clock-frequency = <1000000>; 1873 #address-cells = <1>; 1874 #size-cells = <0>; 1875 }; 1876 1877 cci0_i2c1: i2c-bus@1 { 1878 reg = <1>; 1879 clock-frequency = <1000000>; 1880 #address-cells = <1>; 1881 #size-cells = <0>; 1882 }; 1883 }; 1884 1885 cci1: cci@ac16000 { 1886 compatible = "qcom,milos-cci", "qcom,msm8996-cci"; 1887 reg = <0x0 0x0ac16000 0x0 0x1000>; 1888 interrupts = <GIC_SPI 427 IRQ_TYPE_EDGE_RISING 0>; 1889 power-domains = <&camcc CAM_CC_CAMSS_TOP_GDSC>; 1890 clocks = <&camcc CAM_CC_SOC_AHB_CLK>, 1891 <&camcc CAM_CC_CPAS_AHB_CLK>, 1892 <&camcc CAM_CC_CCI_1_CLK>; 1893 clock-names = "soc_ahb", 1894 "cpas_ahb", 1895 "cci"; 1896 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 1897 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 1898 pinctrl-names = "default", "sleep"; 1899 status = "disabled"; 1900 #address-cells = <1>; 1901 #size-cells = <0>; 1902 1903 cci1_i2c0: i2c-bus@0 { 1904 reg = <0>; 1905 clock-frequency = <1000000>; 1906 #address-cells = <1>; 1907 #size-cells = <0>; 1908 }; 1909 1910 cci1_i2c1: i2c-bus@1 { 1911 reg = <1>; 1912 clock-frequency = <1000000>; 1913 #address-cells = <1>; 1914 #size-cells = <0>; 1915 }; 1916 }; 1917 1918 camcc: clock-controller@adb0000 { 1919 compatible = "qcom,milos-camcc"; 1920 reg = <0x0 0x0adb0000 0x0 0x40000>; 1921 1922 clocks = <&rpmhcc RPMH_CXO_CLK>, 1923 <&sleep_clk>, 1924 <&gcc GCC_CAMERA_AHB_CLK>; 1925 1926 #clock-cells = <1>; 1927 #reset-cells = <1>; 1928 #power-domain-cells = <1>; 1929 }; 1930 1931 dispcc: clock-controller@af00000 { 1932 compatible = "qcom,milos-dispcc"; 1933 reg = <0x0 0x0af00000 0x0 0x20000>; 1934 1935 clocks = <&rpmhcc RPMH_CXO_CLK>, 1936 <&sleep_clk>, 1937 <&gcc GCC_DISP_AHB_CLK>, 1938 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 1939 <0>, /* dsi0_phy_pll_out_byteclk */ 1940 <0>, /* dsi0_phy_pll_out_dsiclk */ 1941 <0>, /* dp0_phy_pll_link_clk */ 1942 <0>; /* dp0_phy_pll_vco_div_clk */ 1943 1944 #clock-cells = <1>; 1945 #reset-cells = <1>; 1946 #power-domain-cells = <1>; 1947 }; 1948 1949 pdc: interrupt-controller@b220000 { 1950 compatible = "qcom,milos-pdc", "qcom,pdc"; 1951 reg = <0x0 0x0b220000 0x0 0x30000>, 1952 <0x0 0x174000f0 0x0 0x64>; 1953 interrupt-parent = <&intc>; 1954 1955 qcom,pdc-ranges = <0 480 40>, <40 140 11>, <51 527 47>, 1956 <98 609 31>, <129 63 1>, <130 716 12>, 1957 <142 251 5>; 1958 1959 #interrupt-cells = <2>; 1960 interrupt-controller; 1961 }; 1962 1963 tsens0: thermal-sensor@c228000 { 1964 compatible = "qcom,milos-tsens", "qcom,tsens-v2"; 1965 reg = <0x0 0x0c228000 0x0 0x1000>, 1966 <0x0 0x0c222000 0x0 0x1000>; 1967 1968 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1969 <&intc GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 1970 interrupt-names = "uplow", 1971 "critical"; 1972 1973 #qcom,sensors = <15>; 1974 1975 #thermal-sensor-cells = <1>; 1976 }; 1977 1978 tsens1: thermal-sensor@c229000 { 1979 compatible = "qcom,milos-tsens", "qcom,tsens-v2"; 1980 reg = <0x0 0x0c229000 0x0 0x1000>, 1981 <0x0 0x0c223000 0x0 0x1000>; 1982 1983 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1984 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 1985 interrupt-names = "uplow", 1986 "critical"; 1987 1988 #qcom,sensors = <14>; 1989 1990 #thermal-sensor-cells = <1>; 1991 }; 1992 1993 aoss_qmp: power-management@c300000 { 1994 compatible = "qcom,milos-aoss-qmp", "qcom,aoss-qmp"; 1995 reg = <0x0 0x0c300000 0x0 0x400>; 1996 1997 interrupt-parent = <&ipcc>; 1998 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1999 IRQ_TYPE_EDGE_RISING>; 2000 2001 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2002 2003 #clock-cells = <0>; 2004 }; 2005 2006 sram@c3f0000 { 2007 compatible = "qcom,rpmh-stats"; 2008 reg = <0x0 0x0c3f0000 0x0 0x400>; 2009 }; 2010 2011 spmi_bus: spmi@c400000 { 2012 compatible = "qcom,spmi-pmic-arb"; 2013 reg = <0x0 0x0c400000 0x0 0x3000>, 2014 <0x0 0x0c500000 0x0 0x400000>, 2015 <0x0 0x0c440000 0x0 0x80000>, 2016 <0x0 0x0c4c0000 0x0 0x10000>, 2017 <0x0 0x0c42d000 0x0 0x4000>; 2018 reg-names = "core", 2019 "chnls", 2020 "obsrvr", 2021 "intr", 2022 "cnfg"; 2023 2024 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2025 interrupt-names = "periph_irq"; 2026 2027 qcom,ee = <0>; 2028 qcom,channel = <0>; 2029 qcom,bus-id = <0>; 2030 2031 interrupt-controller; 2032 #interrupt-cells = <4>; 2033 2034 #address-cells = <2>; 2035 #size-cells = <0>; 2036 }; 2037 2038 tlmm: pinctrl@f100000 { 2039 compatible = "qcom,milos-tlmm"; 2040 reg = <0x0 0x0f100000 0x0 0x300000>; 2041 2042 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH 0>; 2043 2044 gpio-controller; 2045 #gpio-cells = <2>; 2046 2047 interrupt-controller; 2048 #interrupt-cells = <2>; 2049 2050 gpio-ranges = <&tlmm 0 0 168>; 2051 2052 wakeup-parent = <&pdc>; 2053 2054 qup_spi0_data_clk: qup-spi0-data-clk-state { 2055 /* MISO, MOSI, CLK */ 2056 pins = "gpio0", "gpio1", "gpio2"; 2057 function = "qup0_se0"; 2058 drive-strength = <6>; 2059 bias-disable; 2060 }; 2061 2062 qup_spi0_cs: qup-spi0-cs-state { 2063 pins = "gpio3"; 2064 function = "qup0_se0"; 2065 drive-strength = <6>; 2066 bias-disable; 2067 }; 2068 2069 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2070 /* SDA, SCL */ 2071 pins = "gpio4", "gpio5"; 2072 function = "qup0_se1"; 2073 drive-strength = <2>; 2074 bias-pull-up; 2075 }; 2076 2077 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2078 /* SDA, SCL */ 2079 pins = "gpio15", "gpio16"; 2080 function = "qup0_se3"; 2081 drive-strength = <2>; 2082 bias-pull-up = <2200>; 2083 }; 2084 2085 qup_uart5_default: qup-uart5-default-state { 2086 /* TX, RX */ 2087 pins = "gpio25", "gpio26"; 2088 function = "qup0_se5"; 2089 drive-strength = <2>; 2090 bias-disable; 2091 }; 2092 2093 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 2094 /* SDA, SCL */ 2095 pins = "gpio32", "gpio33"; 2096 function = "qup1_se0"; 2097 drive-strength = <2>; 2098 bias-pull-up; 2099 }; 2100 2101 qup_uart11_cts_rts: qup-uart11-cts-rts-state { 2102 /* CTS, RTS */ 2103 pins = "gpio48", "gpio49"; 2104 function = "qup1_se4"; 2105 drive-strength = <2>; 2106 bias-pull-down; 2107 }; 2108 2109 qup_uart11_default: qup-uart11-default-state { 2110 /* TX, RX */ 2111 pins = "gpio50", "gpio51"; 2112 function = "qup1_se4"; 2113 drive-strength = <2>; 2114 bias-pull-up; 2115 }; 2116 2117 sdc2_default: sdc2-default-state { 2118 clk-pins { 2119 pins = "gpio62"; 2120 function = "sdc2_clk"; 2121 drive-strength = <16>; 2122 bias-disable; 2123 }; 2124 2125 cmd-pins { 2126 pins = "gpio61"; 2127 function = "sdc2_cmd"; 2128 drive-strength = <10>; 2129 bias-pull-up; 2130 }; 2131 2132 data-pins { 2133 pins = "gpio58", "gpio57", "gpio35", "gpio34"; 2134 function = "sdc2_data"; 2135 drive-strength = <10>; 2136 bias-pull-up; 2137 }; 2138 }; 2139 2140 sdc2_sleep: sdc2-sleep-state { 2141 clk-pins { 2142 pins = "gpio62"; 2143 function = "gpio"; 2144 drive-strength = <2>; 2145 bias-disable; 2146 }; 2147 2148 cmd-pins { 2149 pins = "gpio61"; 2150 function = "gpio"; 2151 drive-strength = <2>; 2152 bias-pull-up; 2153 }; 2154 2155 data-pins { 2156 pins = "gpio58", "gpio57", "gpio35", "gpio34"; 2157 function = "gpio"; 2158 drive-strength = <2>; 2159 bias-pull-up; 2160 }; 2161 }; 2162 2163 cci0_0_default: cci0-0-default-state { 2164 sda-pins { 2165 pins = "gpio88"; 2166 function = "cci_i2c_sda"; 2167 drive-strength = <2>; 2168 bias-pull-up = <2200>; 2169 }; 2170 2171 scl-pins { 2172 pins = "gpio89"; 2173 function = "cci_i2c_scl"; 2174 drive-strength = <2>; 2175 bias-pull-up = <2200>; 2176 }; 2177 }; 2178 2179 cci0_0_sleep: cci0-0-sleep-state { 2180 sda-pins { 2181 pins = "gpio88"; 2182 function = "cci_i2c_sda"; 2183 drive-strength = <2>; 2184 bias-pull-down; 2185 }; 2186 2187 scl-pins { 2188 pins = "gpio89"; 2189 function = "cci_i2c_scl"; 2190 drive-strength = <2>; 2191 bias-pull-down; 2192 }; 2193 }; 2194 2195 cci0_1_default: cci0-1-default-state { 2196 sda-pins { 2197 pins = "gpio90"; 2198 function = "cci_i2c_sda"; 2199 drive-strength = <2>; 2200 bias-pull-up = <2200>; 2201 }; 2202 2203 scl-pins { 2204 pins = "gpio91"; 2205 function = "cci_i2c_scl"; 2206 drive-strength = <2>; 2207 bias-pull-up = <2200>; 2208 }; 2209 }; 2210 2211 cci0_1_sleep: cci0-1-sleep-state { 2212 sda-pins { 2213 pins = "gpio90"; 2214 function = "cci_i2c_sda"; 2215 drive-strength = <2>; 2216 bias-pull-down; 2217 }; 2218 2219 scl-pins { 2220 pins = "gpio91"; 2221 function = "cci_i2c_scl"; 2222 drive-strength = <2>; 2223 bias-pull-down; 2224 }; 2225 }; 2226 2227 cci1_0_default: cci1-0-default-state { 2228 sda-pins { 2229 pins = "gpio92"; 2230 function = "cci_i2c_sda"; 2231 drive-strength = <2>; 2232 bias-pull-up = <2200>; 2233 }; 2234 2235 scl-pins { 2236 pins = "gpio93"; 2237 function = "cci_i2c_scl"; 2238 drive-strength = <2>; 2239 bias-pull-up = <2200>; 2240 }; 2241 }; 2242 2243 cci1_0_sleep: cci1-0-sleep-state { 2244 sda-pins { 2245 pins = "gpio92"; 2246 function = "cci_i2c_sda"; 2247 drive-strength = <2>; 2248 bias-pull-down; 2249 }; 2250 2251 scl-pins { 2252 pins = "gpio93"; 2253 function = "cci_i2c_scl"; 2254 drive-strength = <2>; 2255 bias-pull-down; 2256 }; 2257 }; 2258 2259 cci1_1_default: cci1-1-default-state { 2260 sda-pins { 2261 pins = "gpio94"; 2262 function = "cci_i2c_sda"; 2263 drive-strength = <2>; 2264 bias-pull-up = <2200>; 2265 }; 2266 2267 scl-pins { 2268 pins = "gpio95"; 2269 function = "cci_i2c_scl"; 2270 drive-strength = <2>; 2271 bias-pull-up = <2200>; 2272 }; 2273 }; 2274 2275 cci1_1_sleep: cci1-1-sleep-state { 2276 sda-pins { 2277 pins = "gpio94"; 2278 function = "cci_i2c_sda"; 2279 drive-strength = <2>; 2280 bias-pull-down; 2281 }; 2282 2283 scl-pins { 2284 pins = "gpio95"; 2285 function = "cci_i2c_scl"; 2286 drive-strength = <2>; 2287 bias-pull-down; 2288 }; 2289 }; 2290 }; 2291 2292 apps_smmu: iommu@15000000 { 2293 compatible = "qcom,milos-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2294 reg = <0x0 0x15000000 0x0 0x100000>; 2295 #iommu-cells = <2>; 2296 #global-interrupts = <1>; 2297 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>, 2298 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, 2299 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>, 2300 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>, 2301 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>, 2302 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, 2303 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>, 2304 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 2305 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 2306 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>, 2307 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>, 2308 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH 0>, 2309 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 2310 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 2311 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>, 2312 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>, 2313 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>, 2314 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>, 2315 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 2316 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>, 2317 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>, 2318 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>, 2319 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>, 2320 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>, 2321 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>, 2322 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>, 2323 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>, 2324 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>, 2325 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>, 2326 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>, 2327 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>, 2328 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>, 2329 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>, 2330 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>, 2331 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>, 2332 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>, 2333 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH 0>, 2334 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>, 2335 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>, 2336 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>, 2337 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>, 2338 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>, 2339 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>, 2340 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>, 2341 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>, 2342 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>, 2343 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>, 2344 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>, 2345 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>, 2346 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>, 2347 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>, 2348 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>, 2349 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>, 2350 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>, 2351 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>, 2352 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>, 2353 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>, 2354 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>, 2355 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>, 2356 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>, 2357 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>, 2358 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>, 2359 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>, 2360 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>, 2361 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>, 2362 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH 0>, 2363 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>, 2364 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 2365 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 2366 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>, 2367 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH 0>, 2368 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>, 2369 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH 0>, 2370 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH 0>, 2371 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH 0>, 2372 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH 0>, 2373 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH 0>, 2374 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH 0>, 2375 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, 2376 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, 2377 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, 2378 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, 2379 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, 2380 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH 0>, 2381 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH 0>, 2382 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>, 2383 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH 0>, 2384 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH 0>, 2385 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>, 2386 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH 0>, 2387 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH 0>, 2388 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH 0>, 2389 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH 0>, 2390 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH 0>, 2391 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH 0>, 2392 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH 0>, 2393 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH 0>; 2394 dma-coherent; 2395 }; 2396 2397 intc: interrupt-controller@17100000 { 2398 compatible = "arm,gic-v3"; 2399 reg = <0x0 0x17100000 0x0 0x10000>, 2400 <0x0 0x17180000 0x0 0x200000>; 2401 2402 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 2403 2404 #interrupt-cells = <4>; 2405 interrupt-controller; 2406 2407 #redistributor-regions = <1>; 2408 redistributor-stride = <0 0x40000>; 2409 2410 #address-cells = <2>; 2411 #size-cells = <2>; 2412 ranges; 2413 2414 ppi-partitions { 2415 ppi_cluster0: interrupt-partition-0 { 2416 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 2417 }; 2418 2419 ppi_cluster1: interrupt-partition-1 { 2420 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 2421 }; 2422 }; 2423 2424 gic_its: msi-controller@17140000 { 2425 compatible = "arm,gic-v3-its"; 2426 reg = <0x0 0x17140000 0x0 0x40000>; 2427 2428 msi-controller; 2429 #msi-cells = <1>; 2430 }; 2431 }; 2432 2433 timer@17420000 { 2434 compatible = "arm,armv7-timer-mem"; 2435 reg = <0x0 0x17420000 0x0 0x1000>; 2436 2437 ranges = <0 0 0 0x20000000>; 2438 #address-cells = <1>; 2439 #size-cells = <1>; 2440 2441 frame@17421000 { 2442 reg = <0x17421000 0x1000>, 2443 <0x17422000 0x1000>; 2444 2445 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>, 2446 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 2447 2448 frame-number = <0>; 2449 }; 2450 2451 frame@17423000 { 2452 reg = <0x17423000 0x1000>; 2453 2454 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 2455 2456 frame-number = <1>; 2457 2458 status = "disabled"; 2459 }; 2460 2461 frame@17425000 { 2462 reg = <0x17425000 0x1000>; 2463 2464 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 2465 2466 frame-number = <2>; 2467 2468 status = "disabled"; 2469 }; 2470 2471 frame@17427000 { 2472 reg = <0x17427000 0x1000>; 2473 2474 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 2475 2476 frame-number = <3>; 2477 2478 status = "disabled"; 2479 }; 2480 2481 frame@17429000 { 2482 reg = <0x17429000 0x1000>; 2483 2484 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 2485 2486 frame-number = <4>; 2487 2488 status = "disabled"; 2489 }; 2490 2491 frame@1742b000 { 2492 reg = <0x1742b000 0x1000>; 2493 2494 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH 0>; 2495 2496 frame-number = <5>; 2497 2498 status = "disabled"; 2499 }; 2500 2501 frame@1742d000 { 2502 reg = <0x1742d000 0x1000>; 2503 2504 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 2505 2506 frame-number = <6>; 2507 2508 status = "disabled"; 2509 }; 2510 }; 2511 2512 apps_rsc: rsc@17a00000 { 2513 compatible = "qcom,rpmh-rsc"; 2514 reg = <0x0 0x17a00000 0x0 0x10000>, 2515 <0x0 0x17a10000 0x0 0x10000>, 2516 <0x0 0x17a20000 0x0 0x10000>; 2517 reg-names = "drv-0", 2518 "drv-1", 2519 "drv-2"; 2520 2521 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH 0>, 2522 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH 0>, 2523 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>; 2524 2525 power-domains = <&cluster_pd>; 2526 2527 qcom,tcs-offset = <0xd00>; 2528 qcom,drv-id = <2>; 2529 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 2530 <WAKE_TCS 2>, <CONTROL_TCS 0>; 2531 2532 label = "apps_rsc"; 2533 2534 apps_bcm_voter: bcm-voter { 2535 compatible = "qcom,bcm-voter"; 2536 }; 2537 2538 rpmhcc: clock-controller { 2539 compatible = "qcom,milos-rpmh-clk"; 2540 2541 clocks = <&xo_board>; 2542 clock-names = "xo"; 2543 2544 #clock-cells = <1>; 2545 }; 2546 2547 rpmhpd: power-controller { 2548 compatible = "qcom,milos-rpmhpd"; 2549 #power-domain-cells = <1>; 2550 operating-points-v2 = <&rpmhpd_opp_table>; 2551 2552 rpmhpd_opp_table: opp-table { 2553 compatible = "operating-points-v2"; 2554 2555 rpmhpd_opp_ret: opp-16 { 2556 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2557 }; 2558 2559 rpmhpd_opp_low_svs_d1: opp-56 { 2560 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2561 }; 2562 2563 rpmhpd_opp_low_svs: opp-64 { 2564 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2565 }; 2566 2567 rpmhpd_opp_svs: opp-128 { 2568 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2569 }; 2570 2571 rpmhpd_opp_svs_l1: opp-192 { 2572 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2573 }; 2574 2575 rpmhpd_opp_nom: opp-256 { 2576 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2577 }; 2578 2579 rpmhpd_opp_nom_l1: opp-320 { 2580 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2581 }; 2582 2583 rpmhpd_opp_turbo: opp-384 { 2584 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2585 }; 2586 2587 rpmhpd_opp_turbo_l1: opp-416 { 2588 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2589 }; 2590 }; 2591 }; 2592 }; 2593 2594 cpufreq_hw: cpufreq@17d91000 { 2595 compatible = "qcom,milos-cpufreq-epss", "qcom,cpufreq-epss"; 2596 reg = <0x0 0x17d91000 0x0 0x1000>, 2597 <0x0 0x17d92000 0x0 0x1000>, 2598 <0x0 0x17d93000 0x0 0x1000>; 2599 reg-names = "freq-domain0", 2600 "freq-domain1", 2601 "freq-domain2"; 2602 2603 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>, 2604 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>, 2605 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 2606 interrupt-names = "dcvsh-irq-0", 2607 "dcvsh-irq-1", 2608 "dcvsh-irq-2"; 2609 2610 clocks = <&rpmhcc RPMH_CXO_CLK>, 2611 <&gcc GCC_GPLL0>; 2612 clock-names = "xo", 2613 "alternate"; 2614 2615 #freq-domain-cells = <1>; 2616 #clock-cells = <1>; 2617 }; 2618 2619 gem_noc: interconnect@24100000 { 2620 compatible = "qcom,milos-gem-noc"; 2621 reg = <0x0 0x24100000 0x0 0xff080>; 2622 #interconnect-cells = <2>; 2623 qcom,bcm-voters = <&apps_bcm_voter>; 2624 }; 2625 2626 nsp_noc: interconnect@320c0000 { 2627 compatible = "qcom,milos-nsp-noc"; 2628 reg = <0x0 0x320c0000 0x0 0xe080>; 2629 #interconnect-cells = <2>; 2630 qcom,bcm-voters = <&apps_bcm_voter>; 2631 }; 2632 2633 remoteproc_cdsp: remoteproc@32300000 { 2634 compatible = "qcom,milos-cdsp-pas"; 2635 reg = <0x0 0x32300000 0x0 0x10000>; 2636 2637 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, 2638 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2639 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2640 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2641 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, 2642 <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; 2643 interrupt-names = "wdog", 2644 "fatal", 2645 "ready", 2646 "handover", 2647 "stop-ack", 2648 "shutdown-ack"; 2649 2650 clocks = <&rpmhcc RPMH_CXO_CLK>; 2651 clock-names = "xo"; 2652 2653 power-domains = <&rpmhpd RPMHPD_CX>, 2654 <&rpmhpd RPMHPD_MX>; 2655 power-domain-names = "cx", 2656 "mx"; 2657 2658 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 2659 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2660 2661 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 2662 2663 qcom,qmp = <&aoss_qmp>; 2664 2665 qcom,smem-states = <&smp2p_cdsp_out 0>; 2666 qcom,smem-state-names = "stop"; 2667 2668 status = "disabled"; 2669 2670 glink-edge { 2671 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2672 IPCC_MPROC_SIGNAL_GLINK_QMP 2673 IRQ_TYPE_EDGE_RISING>; 2674 mboxes = <&ipcc IPCC_CLIENT_CDSP 2675 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2676 2677 label = "cdsp"; 2678 qcom,remote-pid = <5>; 2679 2680 fastrpc { 2681 compatible = "qcom,fastrpc"; 2682 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2683 label = "cdsp"; 2684 qcom,non-secure-domain; 2685 #address-cells = <1>; 2686 #size-cells = <0>; 2687 2688 compute-cb@1 { 2689 compatible = "qcom,fastrpc-compute-cb"; 2690 reg = <1>; 2691 iommus = <&apps_smmu 0x0c01 0x0>; 2692 dma-coherent; 2693 }; 2694 2695 compute-cb@2 { 2696 compatible = "qcom,fastrpc-compute-cb"; 2697 reg = <2>; 2698 iommus = <&apps_smmu 0x0c02 0x0>; 2699 dma-coherent; 2700 }; 2701 2702 compute-cb@3 { 2703 compatible = "qcom,fastrpc-compute-cb"; 2704 reg = <3>; 2705 iommus = <&apps_smmu 0x0c03 0x0>; 2706 dma-coherent; 2707 }; 2708 2709 compute-cb@4 { 2710 compatible = "qcom,fastrpc-compute-cb"; 2711 reg = <4>; 2712 iommus = <&apps_smmu 0x0c04 0x0>; 2713 dma-coherent; 2714 }; 2715 2716 compute-cb@5 { 2717 compatible = "qcom,fastrpc-compute-cb"; 2718 reg = <5>; 2719 iommus = <&apps_smmu 0x0c05 0x0>; 2720 dma-coherent; 2721 }; 2722 2723 compute-cb@6 { 2724 compatible = "qcom,fastrpc-compute-cb"; 2725 reg = <6>; 2726 iommus = <&apps_smmu 0x0c06 0x0>; 2727 dma-coherent; 2728 }; 2729 2730 compute-cb@7 { 2731 compatible = "qcom,fastrpc-compute-cb"; 2732 reg = <7>; 2733 iommus = <&apps_smmu 0x0c07 0x0>; 2734 dma-coherent; 2735 }; 2736 2737 compute-cb@8 { 2738 compatible = "qcom,fastrpc-compute-cb"; 2739 reg = <8>; 2740 iommus = <&apps_smmu 0x0c08 0x0>; 2741 dma-coherent; 2742 }; 2743 2744 /* note: secure cb9 in downstream */ 2745 2746 compute-cb@12 { 2747 compatible = "qcom,fastrpc-compute-cb"; 2748 reg = <12>; 2749 iommus = <&apps_smmu 0x0c0c 0x0>; 2750 dma-coherent; 2751 }; 2752 2753 compute-cb@13 { 2754 compatible = "qcom,fastrpc-compute-cb"; 2755 reg = <13>; 2756 iommus = <&apps_smmu 0x0c0d 0x0>; 2757 dma-coherent; 2758 }; 2759 2760 compute-cb@14 { 2761 compatible = "qcom,fastrpc-compute-cb"; 2762 reg = <14>; 2763 iommus = <&apps_smmu 0x0c0e 0x0>; 2764 dma-coherent; 2765 }; 2766 2767 compute-cb@15 { 2768 compatible = "qcom,fastrpc-compute-cb"; 2769 reg = <15>; 2770 iommus = <&apps_smmu 0x0c0f 0x0>; 2771 dma-coherent; 2772 }; 2773 }; 2774 }; 2775 }; 2776 }; 2777 2778 thermal-zones { 2779 aoss0-thermal { 2780 thermal-sensors = <&tsens0 0>; 2781 2782 trips { 2783 aoss0-hot { 2784 temperature = <110000>; 2785 hysteresis = <1000>; 2786 type = "hot"; 2787 }; 2788 2789 aoss0-critical { 2790 temperature = <115000>; 2791 hysteresis = <0>; 2792 type = "critical"; 2793 }; 2794 }; 2795 }; 2796 2797 cpuss0-thermal { 2798 thermal-sensors = <&tsens0 1>; 2799 2800 trips { 2801 cpuss0-critical { 2802 temperature = <115000>; 2803 hysteresis = <0>; 2804 type = "critical"; 2805 }; 2806 }; 2807 }; 2808 2809 cpuss1-thermal { 2810 thermal-sensors = <&tsens0 2>; 2811 2812 trips { 2813 cpuss1-critical { 2814 temperature = <115000>; 2815 hysteresis = <0>; 2816 type = "critical"; 2817 }; 2818 }; 2819 }; 2820 2821 cpu4-left-thermal { 2822 thermal-sensors = <&tsens0 3>; 2823 2824 trips { 2825 cpu4-left-critical { 2826 temperature = <110000>; 2827 hysteresis = <1000>; 2828 type = "critical"; 2829 }; 2830 }; 2831 }; 2832 2833 cpu4-right-thermal { 2834 thermal-sensors = <&tsens0 4>; 2835 2836 trips { 2837 cpu4-right-critical { 2838 temperature = <110000>; 2839 hysteresis = <1000>; 2840 type = "critical"; 2841 }; 2842 }; 2843 }; 2844 2845 cpu5-left-thermal { 2846 thermal-sensors = <&tsens0 5>; 2847 2848 trips { 2849 cpu5-left-critical { 2850 temperature = <110000>; 2851 hysteresis = <1000>; 2852 type = "critical"; 2853 }; 2854 }; 2855 }; 2856 2857 cpu5-right-thermal { 2858 thermal-sensors = <&tsens0 6>; 2859 2860 trips { 2861 cpu5-right-critical { 2862 temperature = <110000>; 2863 hysteresis = <1000>; 2864 type = "critical"; 2865 }; 2866 }; 2867 }; 2868 2869 cpu6-left-thermal { 2870 thermal-sensors = <&tsens0 7>; 2871 2872 trips { 2873 cpu6-left-critical { 2874 temperature = <110000>; 2875 hysteresis = <1000>; 2876 type = "critical"; 2877 }; 2878 }; 2879 }; 2880 2881 cpu6-right-thermal { 2882 thermal-sensors = <&tsens0 8>; 2883 2884 trips { 2885 cpu6-right-critical { 2886 temperature = <110000>; 2887 hysteresis = <1000>; 2888 type = "critical"; 2889 }; 2890 }; 2891 }; 2892 2893 cpu7-left-thermal { 2894 thermal-sensors = <&tsens0 9>; 2895 2896 trips { 2897 cpu7-left-critical { 2898 temperature = <110000>; 2899 hysteresis = <1000>; 2900 type = "critical"; 2901 }; 2902 }; 2903 }; 2904 2905 cpu7-right-thermal { 2906 thermal-sensors = <&tsens0 10>; 2907 2908 trips { 2909 cpu7-right-critical { 2910 temperature = <110000>; 2911 hysteresis = <1000>; 2912 type = "critical"; 2913 }; 2914 }; 2915 }; 2916 2917 cpu0-thermal { 2918 thermal-sensors = <&tsens0 11>; 2919 2920 trips { 2921 cpu0-critical { 2922 temperature = <110000>; 2923 hysteresis = <1000>; 2924 type = "critical"; 2925 }; 2926 }; 2927 }; 2928 2929 cpu1-thermal { 2930 thermal-sensors = <&tsens0 12>; 2931 2932 trips { 2933 cpu1-critical { 2934 temperature = <110000>; 2935 hysteresis = <1000>; 2936 type = "critical"; 2937 }; 2938 }; 2939 }; 2940 2941 cpu2-thermal { 2942 thermal-sensors = <&tsens0 13>; 2943 2944 trips { 2945 cpu2-critical { 2946 temperature = <110000>; 2947 hysteresis = <1000>; 2948 type = "critical"; 2949 }; 2950 }; 2951 }; 2952 2953 cpu3-thermal { 2954 thermal-sensors = <&tsens0 14>; 2955 2956 trips { 2957 cpu3-critical { 2958 temperature = <110000>; 2959 hysteresis = <1000>; 2960 type = "critical"; 2961 }; 2962 }; 2963 }; 2964 2965 aoss1-thermal { 2966 thermal-sensors = <&tsens1 0>; 2967 2968 trips { 2969 aoss1-hot { 2970 temperature = <110000>; 2971 hysteresis = <1000>; 2972 type = "hot"; 2973 }; 2974 2975 aoss1-critical { 2976 temperature = <115000>; 2977 hysteresis = <0>; 2978 type = "critical"; 2979 }; 2980 }; 2981 }; 2982 2983 nsphvx0-thermal { 2984 polling-delay-passive = <10>; 2985 2986 thermal-sensors = <&tsens1 1>; 2987 2988 trips { 2989 nsphvx0-hot { 2990 temperature = <110000>; 2991 hysteresis = <1000>; 2992 type = "hot"; 2993 }; 2994 2995 nsphvx0-critical { 2996 temperature = <115000>; 2997 hysteresis = <0>; 2998 type = "critical"; 2999 }; 3000 }; 3001 }; 3002 3003 nsphmx1-thermal { 3004 polling-delay-passive = <10>; 3005 3006 thermal-sensors = <&tsens1 2>; 3007 3008 trips { 3009 nsphmx1-hot { 3010 temperature = <110000>; 3011 hysteresis = <1000>; 3012 type = "hot"; 3013 }; 3014 3015 nsphmx1-critical { 3016 temperature = <115000>; 3017 hysteresis = <0>; 3018 type = "critical"; 3019 }; 3020 }; 3021 }; 3022 3023 nsphmx0-thermal { 3024 polling-delay-passive = <10>; 3025 3026 thermal-sensors = <&tsens1 3>; 3027 3028 trips { 3029 nsphmx0-hot { 3030 temperature = <110000>; 3031 hysteresis = <1000>; 3032 type = "hot"; 3033 }; 3034 3035 nsphmx0-critical { 3036 temperature = <115000>; 3037 hysteresis = <0>; 3038 type = "critical"; 3039 }; 3040 }; 3041 }; 3042 3043 gpuss0-thermal { 3044 polling-delay-passive = <10>; 3045 3046 thermal-sensors = <&tsens1 4>; 3047 3048 trips { 3049 gpu0_alert0: trip-point0 { 3050 temperature = <85000>; 3051 hysteresis = <1000>; 3052 type = "passive"; 3053 }; 3054 3055 trip-point1 { 3056 temperature = <90000>; 3057 hysteresis = <1000>; 3058 type = "hot"; 3059 }; 3060 3061 gpuss0-critical { 3062 temperature = <110000>; 3063 hysteresis = <1000>; 3064 type = "critical"; 3065 }; 3066 }; 3067 }; 3068 3069 gpuss1-thermal { 3070 polling-delay-passive = <10>; 3071 3072 thermal-sensors = <&tsens1 5>; 3073 3074 trips { 3075 gpu1_alert0: trip-point0 { 3076 temperature = <85000>; 3077 hysteresis = <1000>; 3078 type = "passive"; 3079 }; 3080 3081 trip-point1 { 3082 temperature = <90000>; 3083 hysteresis = <1000>; 3084 type = "hot"; 3085 }; 3086 3087 gpuss1-critical { 3088 temperature = <110000>; 3089 hysteresis = <1000>; 3090 type = "critical"; 3091 }; 3092 }; 3093 }; 3094 3095 video-thermal { 3096 thermal-sensors = <&tsens1 7>; 3097 3098 trips { 3099 video-hot { 3100 temperature = <110000>; 3101 hysteresis = <1000>; 3102 type = "hot"; 3103 }; 3104 3105 video-critical { 3106 temperature = <115000>; 3107 hysteresis = <0>; 3108 type = "critical"; 3109 }; 3110 }; 3111 }; 3112 3113 ddr-thermal { 3114 polling-delay-passive = <10>; 3115 3116 thermal-sensors = <&tsens1 8>; 3117 3118 trips { 3119 ddr-hot { 3120 temperature = <110000>; 3121 hysteresis = <1000>; 3122 type = "hot"; 3123 }; 3124 3125 ddr-critical { 3126 temperature = <115000>; 3127 hysteresis = <0>; 3128 type = "critical"; 3129 }; 3130 }; 3131 }; 3132 3133 camera0-thermal { 3134 thermal-sensors = <&tsens1 9>; 3135 3136 trips { 3137 camera0-hot { 3138 temperature = <110000>; 3139 hysteresis = <1000>; 3140 type = "hot"; 3141 }; 3142 3143 camera0-critical { 3144 temperature = <115000>; 3145 hysteresis = <0>; 3146 type = "critical"; 3147 }; 3148 }; 3149 }; 3150 3151 modem0-thermal { 3152 polling-delay-passive = <100>; 3153 3154 thermal-sensors = <&tsens1 10>; 3155 3156 trips { 3157 modem0-hot { 3158 temperature = <110000>; 3159 hysteresis = <1000>; 3160 type = "hot"; 3161 }; 3162 3163 modem0-critical { 3164 temperature = <115000>; 3165 hysteresis = <0>; 3166 type = "critical"; 3167 }; 3168 }; 3169 }; 3170 3171 modem1-thermal { 3172 polling-delay-passive = <100>; 3173 3174 thermal-sensors = <&tsens1 11>; 3175 3176 trips { 3177 modem1-hot { 3178 temperature = <110000>; 3179 hysteresis = <1000>; 3180 type = "hot"; 3181 }; 3182 3183 modem1-critical { 3184 temperature = <115000>; 3185 hysteresis = <0>; 3186 type = "critical"; 3187 }; 3188 }; 3189 }; 3190 3191 modem2-thermal { 3192 polling-delay-passive = <100>; 3193 3194 thermal-sensors = <&tsens1 12>; 3195 3196 trips { 3197 modem2-hot { 3198 temperature = <110000>; 3199 hysteresis = <1000>; 3200 type = "hot"; 3201 }; 3202 3203 modem2-critical { 3204 temperature = <115000>; 3205 hysteresis = <0>; 3206 type = "critical"; 3207 }; 3208 }; 3209 }; 3210 3211 modem3-thermal { 3212 polling-delay-passive = <100>; 3213 3214 thermal-sensors = <&tsens1 13>; 3215 3216 trips { 3217 modem3-hot { 3218 temperature = <110000>; 3219 hysteresis = <1000>; 3220 type = "hot"; 3221 }; 3222 3223 modem3-critical { 3224 temperature = <115000>; 3225 hysteresis = <0>; 3226 type = "critical"; 3227 }; 3228 }; 3229 }; 3230 }; 3231 3232 timer { 3233 compatible = "arm,armv8-timer"; 3234 3235 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 3236 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 3237 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 3238 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW 0>; 3239 }; 3240}; 3241