1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#include <dt-bindings/interconnect/qcom,icc.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 12#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 13#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 14#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 15#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/firmware/qcom,scm.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 clocks { 33 xo_board_clk: xo-board-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "qcom,kryo"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 power-domains = <&cpu_pd0>; 54 power-domain-names = "psci"; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 next-level-cache = <&l2_0>; 57 capacity-dmips-mhz = <1024>; 58 #cooling-cells = <2>; 59 dynamic-power-coefficient = <100>; 60 operating-points-v2 = <&cpu0_opp_table>; 61 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 62 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 63 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 64 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 65 l2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&l3_0>; 70 l3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 cpu1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo"; 81 reg = <0x0 0x100>; 82 enable-method = "psci"; 83 power-domains = <&cpu_pd1>; 84 power-domain-names = "psci"; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 next-level-cache = <&l2_1>; 87 capacity-dmips-mhz = <1024>; 88 #cooling-cells = <2>; 89 dynamic-power-coefficient = <100>; 90 operating-points-v2 = <&cpu0_opp_table>; 91 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 92 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 93 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 94 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 95 l2_1: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 next-level-cache = <&l3_0>; 100 }; 101 }; 102 103 cpu2: cpu@200 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo"; 106 reg = <0x0 0x200>; 107 enable-method = "psci"; 108 power-domains = <&cpu_pd2>; 109 power-domain-names = "psci"; 110 qcom,freq-domain = <&cpufreq_hw 0>; 111 next-level-cache = <&l2_2>; 112 capacity-dmips-mhz = <1024>; 113 #cooling-cells = <2>; 114 dynamic-power-coefficient = <100>; 115 operating-points-v2 = <&cpu0_opp_table>; 116 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 117 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 118 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 119 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 120 l2_2: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 cache-unified; 124 next-level-cache = <&l3_0>; 125 }; 126 }; 127 128 cpu3: cpu@300 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo"; 131 reg = <0x0 0x300>; 132 enable-method = "psci"; 133 power-domains = <&cpu_pd3>; 134 power-domain-names = "psci"; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 next-level-cache = <&l2_3>; 137 capacity-dmips-mhz = <1024>; 138 #cooling-cells = <2>; 139 dynamic-power-coefficient = <100>; 140 operating-points-v2 = <&cpu0_opp_table>; 141 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 143 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 144 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 145 l2_3: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&l3_0>; 150 }; 151 }; 152 153 cpu4: cpu@10000 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo"; 156 reg = <0x0 0x10000>; 157 enable-method = "psci"; 158 power-domains = <&cpu_pd4>; 159 power-domain-names = "psci"; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 next-level-cache = <&l2_4>; 162 capacity-dmips-mhz = <1024>; 163 #cooling-cells = <2>; 164 dynamic-power-coefficient = <100>; 165 operating-points-v2 = <&cpu4_opp_table>; 166 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 167 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 168 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 169 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 170 l2_4: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_1>; 175 l3_1: l3-cache { 176 compatible = "cache"; 177 cache-level = <3>; 178 cache-unified; 179 }; 180 181 }; 182 }; 183 184 cpu5: cpu@10100 { 185 device_type = "cpu"; 186 compatible = "qcom,kryo"; 187 reg = <0x0 0x10100>; 188 enable-method = "psci"; 189 power-domains = <&cpu_pd5>; 190 power-domain-names = "psci"; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 next-level-cache = <&l2_5>; 193 capacity-dmips-mhz = <1024>; 194 #cooling-cells = <2>; 195 dynamic-power-coefficient = <100>; 196 operating-points-v2 = <&cpu4_opp_table>; 197 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 198 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 199 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 200 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 201 l2_5: l2-cache { 202 compatible = "cache"; 203 cache-level = <2>; 204 cache-unified; 205 next-level-cache = <&l3_1>; 206 }; 207 }; 208 209 cpu6: cpu@10200 { 210 device_type = "cpu"; 211 compatible = "qcom,kryo"; 212 reg = <0x0 0x10200>; 213 enable-method = "psci"; 214 power-domains = <&cpu_pd6>; 215 power-domain-names = "psci"; 216 qcom,freq-domain = <&cpufreq_hw 1>; 217 next-level-cache = <&l2_6>; 218 capacity-dmips-mhz = <1024>; 219 #cooling-cells = <2>; 220 dynamic-power-coefficient = <100>; 221 operating-points-v2 = <&cpu4_opp_table>; 222 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 223 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 224 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 225 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 226 l2_6: l2-cache { 227 compatible = "cache"; 228 cache-level = <2>; 229 cache-unified; 230 next-level-cache = <&l3_1>; 231 }; 232 }; 233 234 cpu7: cpu@10300 { 235 device_type = "cpu"; 236 compatible = "qcom,kryo"; 237 reg = <0x0 0x10300>; 238 enable-method = "psci"; 239 power-domains = <&cpu_pd7>; 240 power-domain-names = "psci"; 241 qcom,freq-domain = <&cpufreq_hw 1>; 242 next-level-cache = <&l2_7>; 243 capacity-dmips-mhz = <1024>; 244 #cooling-cells = <2>; 245 dynamic-power-coefficient = <100>; 246 operating-points-v2 = <&cpu4_opp_table>; 247 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 248 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 249 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 250 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 251 l2_7: l2-cache { 252 compatible = "cache"; 253 cache-level = <2>; 254 cache-unified; 255 next-level-cache = <&l3_1>; 256 }; 257 }; 258 259 cpu-map { 260 cluster0 { 261 core0 { 262 cpu = <&cpu0>; 263 }; 264 265 core1 { 266 cpu = <&cpu1>; 267 }; 268 269 core2 { 270 cpu = <&cpu2>; 271 }; 272 273 core3 { 274 cpu = <&cpu3>; 275 }; 276 }; 277 278 cluster1 { 279 core0 { 280 cpu = <&cpu4>; 281 }; 282 283 core1 { 284 cpu = <&cpu5>; 285 }; 286 287 core2 { 288 cpu = <&cpu6>; 289 }; 290 291 core3 { 292 cpu = <&cpu7>; 293 }; 294 }; 295 }; 296 297 idle-states { 298 entry-method = "psci"; 299 300 gold_cpu_sleep_0: cpu-sleep-0 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "gold-power-collapse"; 303 arm,psci-suspend-param = <0x40000003>; 304 entry-latency-us = <549>; 305 exit-latency-us = <901>; 306 min-residency-us = <1774>; 307 local-timer-stop; 308 }; 309 310 gold_rail_cpu_sleep_0: cpu-sleep-1 { 311 compatible = "arm,idle-state"; 312 idle-state-name = "gold-rail-power-collapse"; 313 arm,psci-suspend-param = <0x40000004>; 314 entry-latency-us = <702>; 315 exit-latency-us = <1061>; 316 min-residency-us = <4488>; 317 local-timer-stop; 318 }; 319 }; 320 321 domain-idle-states { 322 cluster_sleep_gold: cluster-sleep-0 { 323 compatible = "domain-idle-state"; 324 arm,psci-suspend-param = <0x41000044>; 325 entry-latency-us = <2752>; 326 exit-latency-us = <3048>; 327 min-residency-us = <6118>; 328 }; 329 330 cluster_sleep_apss_rsc_pc: cluster-sleep-1 { 331 compatible = "domain-idle-state"; 332 arm,psci-suspend-param = <0x42000144>; 333 entry-latency-us = <3263>; 334 exit-latency-us = <6562>; 335 min-residency-us = <9987>; 336 }; 337 }; 338 }; 339 340 cpu0_opp_table: opp-table-cpu0 { 341 compatible = "operating-points-v2"; 342 opp-shared; 343 344 opp-1267200000 { 345 opp-hz = /bits/ 64 <1267200000>; 346 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 347 }; 348 349 opp-1363200000 { 350 opp-hz = /bits/ 64 <1363200000>; 351 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 352 }; 353 354 opp-1459200000 { 355 opp-hz = /bits/ 64 <1459200000>; 356 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 357 }; 358 359 opp-1536000000 { 360 opp-hz = /bits/ 64 <1536000000>; 361 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 362 }; 363 364 opp-1632000000 { 365 opp-hz = /bits/ 64 <1632000000>; 366 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 367 }; 368 369 opp-1708800000 { 370 opp-hz = /bits/ 64 <1708800000>; 371 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 372 }; 373 374 opp-1785600000 { 375 opp-hz = /bits/ 64 <1785600000>; 376 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 377 }; 378 379 opp-1862400000 { 380 opp-hz = /bits/ 64 <1862400000>; 381 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 382 }; 383 384 opp-1939200000 { 385 opp-hz = /bits/ 64 <1939200000>; 386 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 387 }; 388 389 opp-2016000000 { 390 opp-hz = /bits/ 64 <2016000000>; 391 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 392 }; 393 394 opp-2112000000 { 395 opp-hz = /bits/ 64 <2112000000>; 396 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 397 }; 398 399 opp-2188800000 { 400 opp-hz = /bits/ 64 <2188800000>; 401 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 402 }; 403 404 opp-2265600000 { 405 opp-hz = /bits/ 64 <2265600000>; 406 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 407 }; 408 409 opp-2361600000 { 410 opp-hz = /bits/ 64 <2361600000>; 411 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 412 }; 413 414 opp-2457600000 { 415 opp-hz = /bits/ 64 <2457600000>; 416 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 417 }; 418 419 opp-2553600000 { 420 opp-hz = /bits/ 64 <2553600000>; 421 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 422 }; 423 }; 424 425 cpu4_opp_table: opp-table-cpu4 { 426 compatible = "operating-points-v2"; 427 opp-shared; 428 429 opp-1267200000 { 430 opp-hz = /bits/ 64 <1267200000>; 431 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 432 }; 433 434 opp-1363200000 { 435 opp-hz = /bits/ 64 <1363200000>; 436 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 437 }; 438 439 opp-1459200000 { 440 opp-hz = /bits/ 64 <1459200000>; 441 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 442 }; 443 444 opp-1536000000 { 445 opp-hz = /bits/ 64 <1536000000>; 446 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 447 }; 448 449 opp-1632000000 { 450 opp-hz = /bits/ 64 <1632000000>; 451 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 452 }; 453 454 opp-1708800000 { 455 opp-hz = /bits/ 64 <1708800000>; 456 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 457 }; 458 459 opp-1785600000 { 460 opp-hz = /bits/ 64 <1785600000>; 461 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 462 }; 463 464 opp-1862400000 { 465 opp-hz = /bits/ 64 <1862400000>; 466 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 467 }; 468 469 opp-1939200000 { 470 opp-hz = /bits/ 64 <1939200000>; 471 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 472 }; 473 474 opp-2016000000 { 475 opp-hz = /bits/ 64 <2016000000>; 476 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 477 }; 478 479 opp-2112000000 { 480 opp-hz = /bits/ 64 <2112000000>; 481 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 482 }; 483 484 opp-2188800000 { 485 opp-hz = /bits/ 64 <2188800000>; 486 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 487 }; 488 489 opp-2265600000 { 490 opp-hz = /bits/ 64 <2265600000>; 491 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 492 }; 493 494 opp-2361600000 { 495 opp-hz = /bits/ 64 <2361600000>; 496 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 497 }; 498 499 opp-2457600000 { 500 opp-hz = /bits/ 64 <2457600000>; 501 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 502 }; 503 504 opp-2553600000 { 505 opp-hz = /bits/ 64 <2553600000>; 506 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 507 }; 508 }; 509 510 dummy-sink { 511 compatible = "arm,coresight-dummy-sink"; 512 513 in-ports { 514 port { 515 eud_in: endpoint { 516 remote-endpoint = 517 <&swao_rep_out1>; 518 }; 519 }; 520 }; 521 }; 522 523 firmware { 524 scm { 525 compatible = "qcom,scm-sa8775p", "qcom,scm"; 526 qcom,dload-mode = <&tcsr 0x13000>; 527 }; 528 }; 529 530 clk_virt: interconnect-clk-virt { 531 compatible = "qcom,sa8775p-clk-virt"; 532 #interconnect-cells = <2>; 533 qcom,bcm-voters = <&apps_bcm_voter>; 534 }; 535 536 mc_virt: interconnect-mc-virt { 537 compatible = "qcom,sa8775p-mc-virt"; 538 #interconnect-cells = <2>; 539 qcom,bcm-voters = <&apps_bcm_voter>; 540 }; 541 542 /* Will be updated by the bootloader. */ 543 memory@80000000 { 544 device_type = "memory"; 545 reg = <0x0 0x80000000 0x0 0x0>; 546 }; 547 548 qup_opp_table_100mhz: opp-table-qup100mhz { 549 compatible = "operating-points-v2"; 550 551 opp-100000000 { 552 opp-hz = /bits/ 64 <100000000>; 553 required-opps = <&rpmhpd_opp_svs_l1>; 554 }; 555 }; 556 557 pmu { 558 compatible = "arm,armv8-pmuv3"; 559 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 560 }; 561 562 psci { 563 compatible = "arm,psci-1.0"; 564 method = "smc"; 565 566 cpu_pd0: power-domain-cpu0 { 567 #power-domain-cells = <0>; 568 power-domains = <&cluster_0_pd>; 569 domain-idle-states = <&gold_cpu_sleep_0>, 570 <&gold_rail_cpu_sleep_0>; 571 }; 572 573 cpu_pd1: power-domain-cpu1 { 574 #power-domain-cells = <0>; 575 power-domains = <&cluster_0_pd>; 576 domain-idle-states = <&gold_cpu_sleep_0>, 577 <&gold_rail_cpu_sleep_0>; 578 }; 579 580 cpu_pd2: power-domain-cpu2 { 581 #power-domain-cells = <0>; 582 power-domains = <&cluster_0_pd>; 583 domain-idle-states = <&gold_cpu_sleep_0>, 584 <&gold_rail_cpu_sleep_0>; 585 }; 586 587 cpu_pd3: power-domain-cpu3 { 588 #power-domain-cells = <0>; 589 power-domains = <&cluster_0_pd>; 590 domain-idle-states = <&gold_cpu_sleep_0>, 591 <&gold_rail_cpu_sleep_0>; 592 }; 593 594 cpu_pd4: power-domain-cpu4 { 595 #power-domain-cells = <0>; 596 power-domains = <&cluster_1_pd>; 597 domain-idle-states = <&gold_cpu_sleep_0>, 598 <&gold_rail_cpu_sleep_0>; 599 }; 600 601 cpu_pd5: power-domain-cpu5 { 602 #power-domain-cells = <0>; 603 power-domains = <&cluster_1_pd>; 604 domain-idle-states = <&gold_cpu_sleep_0>, 605 <&gold_rail_cpu_sleep_0>; 606 }; 607 608 cpu_pd6: power-domain-cpu6 { 609 #power-domain-cells = <0>; 610 power-domains = <&cluster_1_pd>; 611 domain-idle-states = <&gold_cpu_sleep_0>, 612 <&gold_rail_cpu_sleep_0>; 613 }; 614 615 cpu_pd7: power-domain-cpu7 { 616 #power-domain-cells = <0>; 617 power-domains = <&cluster_1_pd>; 618 domain-idle-states = <&gold_cpu_sleep_0>, 619 <&gold_rail_cpu_sleep_0>; 620 }; 621 622 cluster_0_pd: power-domain-cluster0 { 623 #power-domain-cells = <0>; 624 domain-idle-states = <&cluster_sleep_gold>; 625 power-domains = <&system_pd>; 626 }; 627 628 cluster_1_pd: power-domain-cluster1 { 629 #power-domain-cells = <0>; 630 domain-idle-states = <&cluster_sleep_gold>; 631 power-domains = <&system_pd>; 632 }; 633 634 system_pd: power-domain-system { 635 #power-domain-cells = <0>; 636 domain-idle-states = <&cluster_sleep_apss_rsc_pc>; 637 }; 638 }; 639 640 reserved-memory { 641 #address-cells = <2>; 642 #size-cells = <2>; 643 ranges; 644 645 sail_ss_mem: sail-ss@80000000 { 646 reg = <0x0 0x80000000 0x0 0x10000000>; 647 no-map; 648 }; 649 650 hyp_mem: hyp@90000000 { 651 reg = <0x0 0x90000000 0x0 0x600000>; 652 no-map; 653 }; 654 655 xbl_boot_mem: xbl-boot@90600000 { 656 reg = <0x0 0x90600000 0x0 0x200000>; 657 no-map; 658 }; 659 660 aop_image_mem: aop-image@90800000 { 661 reg = <0x0 0x90800000 0x0 0x60000>; 662 no-map; 663 }; 664 665 aop_cmd_db_mem: aop-cmd-db@90860000 { 666 compatible = "qcom,cmd-db"; 667 reg = <0x0 0x90860000 0x0 0x20000>; 668 no-map; 669 }; 670 671 uefi_log: uefi-log@908b0000 { 672 reg = <0x0 0x908b0000 0x0 0x10000>; 673 no-map; 674 }; 675 676 ddr_training_checksum: ddr-training-checksum@908c0000 { 677 reg = <0x0 0x908c0000 0x0 0x1000>; 678 no-map; 679 }; 680 681 reserved_mem: reserved@908f0000 { 682 reg = <0x0 0x908f0000 0x0 0xe000>; 683 no-map; 684 }; 685 686 secdata_apss_mem: secdata-apss@908fe000 { 687 reg = <0x0 0x908fe000 0x0 0x2000>; 688 no-map; 689 }; 690 691 smem_mem: smem@90900000 { 692 compatible = "qcom,smem"; 693 reg = <0x0 0x90900000 0x0 0x200000>; 694 no-map; 695 hwlocks = <&tcsr_mutex 3>; 696 }; 697 698 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { 699 reg = <0x0 0x90c00000 0x0 0x100000>; 700 no-map; 701 }; 702 703 sail_mailbox_mem: sail-ss@90d00000 { 704 reg = <0x0 0x90d00000 0x0 0x100000>; 705 no-map; 706 }; 707 708 sail_ota_mem: sail-ss@90e00000 { 709 reg = <0x0 0x90e00000 0x0 0x300000>; 710 no-map; 711 }; 712 713 gunyah_md_mem: gunyah-md@91a80000 { 714 reg = <0x0 0x91a80000 0x0 0x80000>; 715 no-map; 716 }; 717 718 aoss_backup_mem: aoss-backup@91b00000 { 719 reg = <0x0 0x91b00000 0x0 0x40000>; 720 no-map; 721 }; 722 723 cpucp_backup_mem: cpucp-backup@91b40000 { 724 reg = <0x0 0x91b40000 0x0 0x40000>; 725 no-map; 726 }; 727 728 tz_config_backup_mem: tz-config-backup@91b80000 { 729 reg = <0x0 0x91b80000 0x0 0x10000>; 730 no-map; 731 }; 732 733 ddr_training_data_mem: ddr-training-data@91b90000 { 734 reg = <0x0 0x91b90000 0x0 0x10000>; 735 no-map; 736 }; 737 738 cdt_data_backup_mem: cdt-data-backup@91ba0000 { 739 reg = <0x0 0x91ba0000 0x0 0x1000>; 740 no-map; 741 }; 742 743 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 744 reg = <0x0 0x93b00000 0x0 0xf00000>; 745 no-map; 746 }; 747 748 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 749 reg = <0x0 0x94a00000 0x0 0x800000>; 750 no-map; 751 }; 752 753 pil_camera_mem: pil-camera@95200000 { 754 reg = <0x0 0x95200000 0x0 0x700000>; 755 no-map; 756 }; 757 758 pil_adsp_mem: pil-adsp@95900000 { 759 reg = <0x0 0x95900000 0x0 0x1e00000>; 760 no-map; 761 }; 762 763 q6_adsp_dtb_mem: q6-adsp-dtb@97700000 { 764 reg = <0x0 0x97700000 0x0 0x80000>; 765 no-map; 766 }; 767 768 q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 { 769 reg = <0x0 0x97780000 0x0 0x80000>; 770 no-map; 771 }; 772 773 pil_gdsp0_mem: pil-gdsp0@97800000 { 774 reg = <0x0 0x97800000 0x0 0x1e00000>; 775 no-map; 776 }; 777 778 pil_gdsp1_mem: pil-gdsp1@99600000 { 779 reg = <0x0 0x99600000 0x0 0x1e00000>; 780 no-map; 781 }; 782 783 q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 { 784 reg = <0x0 0x9b400000 0x0 0x80000>; 785 no-map; 786 }; 787 788 q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 { 789 reg = <0x0 0x9b480000 0x0 0x80000>; 790 no-map; 791 }; 792 793 pil_cdsp0_mem: pil-cdsp0@9b500000 { 794 reg = <0x0 0x9b500000 0x0 0x1e00000>; 795 no-map; 796 }; 797 798 pil_gpu_mem: pil-gpu@9d300000 { 799 reg = <0x0 0x9d300000 0x0 0x2000>; 800 no-map; 801 }; 802 803 q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 { 804 reg = <0x0 0x9d380000 0x0 0x80000>; 805 no-map; 806 }; 807 808 pil_cdsp1_mem: pil-cdsp1@9d400000 { 809 reg = <0x0 0x9d400000 0x0 0x1e00000>; 810 no-map; 811 }; 812 813 pil_cvp_mem: pil-cvp@9f200000 { 814 reg = <0x0 0x9f200000 0x0 0x700000>; 815 no-map; 816 }; 817 818 pil_video_mem: pil-video@9f900000 { 819 reg = <0x0 0x9f900000 0x0 0x1000000>; 820 no-map; 821 }; 822 823 firmware_mem: firmware-region@b0000000 { 824 reg = <0x0 0xb0000000 0x0 0x800000>; 825 no-map; 826 }; 827 828 scmi_mem: scmi-region@d0000000 { 829 reg = <0x0 0xd0000000 0x0 0x40000>; 830 no-map; 831 }; 832 833 firmware_logs_mem: firmware-logs@d0040000 { 834 reg = <0x0 0xd0040000 0x0 0x10000>; 835 no-map; 836 }; 837 838 firmware_audio_mem: firmware-audio@d0050000 { 839 reg = <0x0 0xd0050000 0x0 0x4000>; 840 no-map; 841 }; 842 843 firmware_reserved_mem: firmware-reserved@d0054000 { 844 reg = <0x0 0xd0054000 0x0 0x9c000>; 845 no-map; 846 }; 847 848 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { 849 reg = <0x0 0xd00f0000 0x0 0x10000>; 850 no-map; 851 }; 852 853 tags_mem: tags@d0100000 { 854 reg = <0x0 0xd0100000 0x0 0x1200000>; 855 no-map; 856 }; 857 858 qtee_mem: qtee@d1300000 { 859 reg = <0x0 0xd1300000 0x0 0x500000>; 860 no-map; 861 }; 862 863 deepsleep_backup_mem: deepsleep-backup@d1800000 { 864 reg = <0x0 0xd1800000 0x0 0x100000>; 865 no-map; 866 }; 867 868 trusted_apps_mem: trusted-apps@d1900000 { 869 reg = <0x0 0xd1900000 0x0 0x1c00000>; 870 no-map; 871 }; 872 873 tz_stat_mem: tz-stat@db100000 { 874 reg = <0x0 0xdb100000 0x0 0x100000>; 875 no-map; 876 }; 877 878 cpucp_fw_mem: cpucp-fw@db200000 { 879 reg = <0x0 0xdb200000 0x0 0x100000>; 880 no-map; 881 }; 882 }; 883 884 smp2p-adsp { 885 compatible = "qcom,smp2p"; 886 qcom,smem = <443>, <429>; 887 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 888 IPCC_MPROC_SIGNAL_SMP2P 889 IRQ_TYPE_EDGE_RISING>; 890 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 891 892 qcom,local-pid = <0>; 893 qcom,remote-pid = <2>; 894 895 smp2p_adsp_out: master-kernel { 896 qcom,entry-name = "master-kernel"; 897 #qcom,smem-state-cells = <1>; 898 }; 899 900 smp2p_adsp_in: slave-kernel { 901 qcom,entry-name = "slave-kernel"; 902 interrupt-controller; 903 #interrupt-cells = <2>; 904 }; 905 }; 906 907 smp2p-cdsp0 { 908 compatible = "qcom,smp2p"; 909 qcom,smem = <94>, <432>; 910 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 911 IPCC_MPROC_SIGNAL_SMP2P 912 IRQ_TYPE_EDGE_RISING>; 913 mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 914 915 qcom,local-pid = <0>; 916 qcom,remote-pid = <5>; 917 918 smp2p_cdsp0_out: master-kernel { 919 qcom,entry-name = "master-kernel"; 920 #qcom,smem-state-cells = <1>; 921 }; 922 923 smp2p_cdsp0_in: slave-kernel { 924 qcom,entry-name = "slave-kernel"; 925 interrupt-controller; 926 #interrupt-cells = <2>; 927 }; 928 }; 929 930 smp2p-cdsp1 { 931 compatible = "qcom,smp2p"; 932 qcom,smem = <617>, <616>; 933 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 934 IPCC_MPROC_SIGNAL_SMP2P 935 IRQ_TYPE_EDGE_RISING>; 936 mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; 937 938 qcom,local-pid = <0>; 939 qcom,remote-pid = <12>; 940 941 smp2p_cdsp1_out: master-kernel { 942 qcom,entry-name = "master-kernel"; 943 #qcom,smem-state-cells = <1>; 944 }; 945 946 smp2p_cdsp1_in: slave-kernel { 947 qcom,entry-name = "slave-kernel"; 948 interrupt-controller; 949 #interrupt-cells = <2>; 950 }; 951 }; 952 953 smp2p-gpdsp0 { 954 compatible = "qcom,smp2p"; 955 qcom,smem = <617>, <616>; 956 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 957 IPCC_MPROC_SIGNAL_SMP2P 958 IRQ_TYPE_EDGE_RISING>; 959 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; 960 961 qcom,local-pid = <0>; 962 qcom,remote-pid = <17>; 963 964 smp2p_gpdsp0_out: master-kernel { 965 qcom,entry-name = "master-kernel"; 966 #qcom,smem-state-cells = <1>; 967 }; 968 969 smp2p_gpdsp0_in: slave-kernel { 970 qcom,entry-name = "slave-kernel"; 971 interrupt-controller; 972 #interrupt-cells = <2>; 973 }; 974 }; 975 976 smp2p-gpdsp1 { 977 compatible = "qcom,smp2p"; 978 qcom,smem = <617>, <616>; 979 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 980 IPCC_MPROC_SIGNAL_SMP2P 981 IRQ_TYPE_EDGE_RISING>; 982 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>; 983 984 qcom,local-pid = <0>; 985 qcom,remote-pid = <18>; 986 987 smp2p_gpdsp1_out: master-kernel { 988 qcom,entry-name = "master-kernel"; 989 #qcom,smem-state-cells = <1>; 990 }; 991 992 smp2p_gpdsp1_in: slave-kernel { 993 qcom,entry-name = "slave-kernel"; 994 interrupt-controller; 995 #interrupt-cells = <2>; 996 }; 997 }; 998 999 soc: soc@0 { 1000 compatible = "simple-bus"; 1001 #address-cells = <2>; 1002 #size-cells = <2>; 1003 ranges = <0 0 0 0 0x10 0>; 1004 1005 gcc: clock-controller@100000 { 1006 compatible = "qcom,sa8775p-gcc"; 1007 reg = <0x0 0x00100000 0x0 0xc7018>; 1008 #clock-cells = <1>; 1009 #reset-cells = <1>; 1010 #power-domain-cells = <1>; 1011 clocks = <&rpmhcc RPMH_CXO_CLK>, 1012 <&sleep_clk>, 1013 <0>, 1014 <0>, 1015 <0>, 1016 <&usb_0_qmpphy>, 1017 <&usb_1_qmpphy>, 1018 <0>, 1019 <0>, 1020 <0>, 1021 <&pcie0_phy>, 1022 <&pcie1_phy>, 1023 <0>, 1024 <0>, 1025 <0>; 1026 power-domains = <&rpmhpd SA8775P_CX>; 1027 }; 1028 1029 ipcc: mailbox@408000 { 1030 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 1031 reg = <0x0 0x00408000 0x0 0x1000>; 1032 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1033 interrupt-controller; 1034 #interrupt-cells = <3>; 1035 #mbox-cells = <2>; 1036 }; 1037 1038 qfprom: efuse@784000 { 1039 compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; 1040 reg = <0x0 0x00784000 0x0 0x3000>; 1041 #address-cells = <1>; 1042 #size-cells = <1>; 1043 1044 gpu_speed_bin: gpu_speed_bin@240c { 1045 reg = <0x240c 0x1>; 1046 bits = <0 8>; 1047 }; 1048 }; 1049 1050 gpi_dma2: dma-controller@800000 { 1051 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1052 reg = <0x0 0x00800000 0x0 0x60000>; 1053 #dma-cells = <3>; 1054 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1066 dma-channels = <12>; 1067 dma-channel-mask = <0xfff>; 1068 iommus = <&apps_smmu 0x5b6 0x0>; 1069 status = "disabled"; 1070 }; 1071 1072 qupv3_id_2: geniqup@8c0000 { 1073 compatible = "qcom,geni-se-qup"; 1074 reg = <0x0 0x008c0000 0x0 0x6000>; 1075 ranges; 1076 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1077 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1078 clock-names = "m-ahb", "s-ahb"; 1079 iommus = <&apps_smmu 0x5a3 0x0>; 1080 #address-cells = <2>; 1081 #size-cells = <2>; 1082 status = "disabled"; 1083 1084 i2c14: i2c@880000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0x0 0x880000 0x0 0x4000>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1091 clock-names = "se"; 1092 pinctrl-0 = <&qup_i2c14_default>; 1093 pinctrl-names = "default"; 1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1095 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1096 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1097 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1098 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1099 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1100 interconnect-names = "qup-core", 1101 "qup-config", 1102 "qup-memory"; 1103 power-domains = <&rpmhpd SA8775P_CX>; 1104 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1105 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1106 dma-names = "tx", 1107 "rx"; 1108 status = "disabled"; 1109 }; 1110 1111 spi14: spi@880000 { 1112 compatible = "qcom,geni-spi"; 1113 reg = <0x0 0x880000 0x0 0x4000>; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1118 clock-names = "se"; 1119 pinctrl-0 = <&qup_spi14_default>; 1120 pinctrl-names = "default"; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1122 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1123 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1124 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1125 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1126 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1127 interconnect-names = "qup-core", 1128 "qup-config", 1129 "qup-memory"; 1130 power-domains = <&rpmhpd SA8775P_CX>; 1131 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1132 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1133 dma-names = "tx", 1134 "rx"; 1135 status = "disabled"; 1136 }; 1137 1138 uart14: serial@880000 { 1139 compatible = "qcom,geni-uart"; 1140 reg = <0x0 0x00880000 0x0 0x4000>; 1141 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1143 clock-names = "se"; 1144 pinctrl-0 = <&qup_uart14_default>; 1145 pinctrl-names = "default"; 1146 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1147 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1148 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1149 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1150 interconnect-names = "qup-core", "qup-config"; 1151 power-domains = <&rpmhpd SA8775P_CX>; 1152 status = "disabled"; 1153 }; 1154 1155 i2c15: i2c@884000 { 1156 compatible = "qcom,geni-i2c"; 1157 reg = <0x0 0x884000 0x0 0x4000>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1162 clock-names = "se"; 1163 pinctrl-0 = <&qup_i2c15_default>; 1164 pinctrl-names = "default"; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1166 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1167 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1168 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1169 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1170 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1171 interconnect-names = "qup-core", 1172 "qup-config", 1173 "qup-memory"; 1174 power-domains = <&rpmhpd SA8775P_CX>; 1175 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1176 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1177 dma-names = "tx", 1178 "rx"; 1179 status = "disabled"; 1180 }; 1181 1182 spi15: spi@884000 { 1183 compatible = "qcom,geni-spi"; 1184 reg = <0x0 0x884000 0x0 0x4000>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1189 clock-names = "se"; 1190 pinctrl-0 = <&qup_spi15_default>; 1191 pinctrl-names = "default"; 1192 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1193 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1194 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1195 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1196 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1197 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1198 interconnect-names = "qup-core", 1199 "qup-config", 1200 "qup-memory"; 1201 power-domains = <&rpmhpd SA8775P_CX>; 1202 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1203 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1204 dma-names = "tx", 1205 "rx"; 1206 status = "disabled"; 1207 }; 1208 1209 uart15: serial@884000 { 1210 compatible = "qcom,geni-uart"; 1211 reg = <0x0 0x00884000 0x0 0x4000>; 1212 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1213 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1214 clock-names = "se"; 1215 pinctrl-0 = <&qup_uart15_default>; 1216 pinctrl-names = "default"; 1217 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1218 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1219 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1220 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1221 interconnect-names = "qup-core", "qup-config"; 1222 power-domains = <&rpmhpd SA8775P_CX>; 1223 status = "disabled"; 1224 }; 1225 1226 i2c16: i2c@888000 { 1227 compatible = "qcom,geni-i2c"; 1228 reg = <0x0 0x888000 0x0 0x4000>; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1233 clock-names = "se"; 1234 pinctrl-0 = <&qup_i2c16_default>; 1235 pinctrl-names = "default"; 1236 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1237 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1238 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1239 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1240 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1241 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1242 interconnect-names = "qup-core", 1243 "qup-config", 1244 "qup-memory"; 1245 power-domains = <&rpmhpd SA8775P_CX>; 1246 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1247 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1248 dma-names = "tx", 1249 "rx"; 1250 status = "disabled"; 1251 }; 1252 1253 spi16: spi@888000 { 1254 compatible = "qcom,geni-spi"; 1255 reg = <0x0 0x00888000 0x0 0x4000>; 1256 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1258 clock-names = "se"; 1259 pinctrl-0 = <&qup_spi16_default>; 1260 pinctrl-names = "default"; 1261 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1262 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1263 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1264 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1265 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1266 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1267 interconnect-names = "qup-core", 1268 "qup-config", 1269 "qup-memory"; 1270 power-domains = <&rpmhpd SA8775P_CX>; 1271 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1272 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1273 dma-names = "tx", 1274 "rx"; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 status = "disabled"; 1278 }; 1279 1280 uart16: serial@888000 { 1281 compatible = "qcom,geni-uart"; 1282 reg = <0x0 0x00888000 0x0 0x4000>; 1283 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1284 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1285 clock-names = "se"; 1286 pinctrl-0 = <&qup_uart16_default>; 1287 pinctrl-names = "default"; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1289 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1290 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1291 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1292 interconnect-names = "qup-core", "qup-config"; 1293 power-domains = <&rpmhpd SA8775P_CX>; 1294 status = "disabled"; 1295 }; 1296 1297 i2c17: i2c@88c000 { 1298 compatible = "qcom,geni-i2c"; 1299 reg = <0x0 0x88c000 0x0 0x4000>; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1304 clock-names = "se"; 1305 pinctrl-0 = <&qup_i2c17_default>; 1306 pinctrl-names = "default"; 1307 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1308 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1309 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1310 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1311 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1313 interconnect-names = "qup-core", 1314 "qup-config", 1315 "qup-memory"; 1316 power-domains = <&rpmhpd SA8775P_CX>; 1317 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1318 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1319 dma-names = "tx", 1320 "rx"; 1321 status = "disabled"; 1322 }; 1323 1324 spi17: spi@88c000 { 1325 compatible = "qcom,geni-spi"; 1326 reg = <0x0 0x88c000 0x0 0x4000>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1330 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1331 clock-names = "se"; 1332 pinctrl-0 = <&qup_spi17_default>; 1333 pinctrl-names = "default"; 1334 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1335 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1336 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1337 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1338 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1339 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1340 interconnect-names = "qup-core", 1341 "qup-config", 1342 "qup-memory"; 1343 power-domains = <&rpmhpd SA8775P_CX>; 1344 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1345 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1346 dma-names = "tx", 1347 "rx"; 1348 status = "disabled"; 1349 }; 1350 1351 uart17: serial@88c000 { 1352 compatible = "qcom,geni-uart"; 1353 reg = <0x0 0x0088c000 0x0 0x4000>; 1354 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1355 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1356 clock-names = "se"; 1357 pinctrl-0 = <&qup_uart17_default>; 1358 pinctrl-names = "default"; 1359 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1360 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1361 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1362 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1363 interconnect-names = "qup-core", "qup-config"; 1364 power-domains = <&rpmhpd SA8775P_CX>; 1365 status = "disabled"; 1366 }; 1367 1368 i2c18: i2c@890000 { 1369 compatible = "qcom,geni-i2c"; 1370 reg = <0x0 0x00890000 0x0 0x4000>; 1371 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1372 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1373 clock-names = "se"; 1374 pinctrl-0 = <&qup_i2c18_default>; 1375 pinctrl-names = "default"; 1376 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1377 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1378 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1379 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1380 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1381 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1382 interconnect-names = "qup-core", 1383 "qup-config", 1384 "qup-memory"; 1385 power-domains = <&rpmhpd SA8775P_CX>; 1386 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1387 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1388 dma-names = "tx", 1389 "rx"; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 status = "disabled"; 1393 }; 1394 1395 spi18: spi@890000 { 1396 compatible = "qcom,geni-spi"; 1397 reg = <0x0 0x890000 0x0 0x4000>; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1401 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1402 clock-names = "se"; 1403 pinctrl-0 = <&qup_spi18_default>; 1404 pinctrl-names = "default"; 1405 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1406 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1407 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1408 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1409 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1410 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1411 interconnect-names = "qup-core", 1412 "qup-config", 1413 "qup-memory"; 1414 power-domains = <&rpmhpd SA8775P_CX>; 1415 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1416 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1417 dma-names = "tx", 1418 "rx"; 1419 status = "disabled"; 1420 }; 1421 1422 uart18: serial@890000 { 1423 compatible = "qcom,geni-uart"; 1424 reg = <0x0 0x00890000 0x0 0x4000>; 1425 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1426 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1427 clock-names = "se"; 1428 pinctrl-0 = <&qup_uart18_default>; 1429 pinctrl-names = "default"; 1430 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1431 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1432 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1433 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1434 interconnect-names = "qup-core", "qup-config"; 1435 power-domains = <&rpmhpd SA8775P_CX>; 1436 status = "disabled"; 1437 }; 1438 1439 i2c19: i2c@894000 { 1440 compatible = "qcom,geni-i2c"; 1441 reg = <0x0 0x894000 0x0 0x4000>; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1445 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1446 clock-names = "se"; 1447 pinctrl-0 = <&qup_i2c19_default>; 1448 pinctrl-names = "default"; 1449 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1450 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1451 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1452 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1453 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1454 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1455 interconnect-names = "qup-core", 1456 "qup-config", 1457 "qup-memory"; 1458 power-domains = <&rpmhpd SA8775P_CX>; 1459 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1460 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1461 dma-names = "tx", 1462 "rx"; 1463 status = "disabled"; 1464 }; 1465 1466 spi19: spi@894000 { 1467 compatible = "qcom,geni-spi"; 1468 reg = <0x0 0x894000 0x0 0x4000>; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1472 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1473 clock-names = "se"; 1474 pinctrl-0 = <&qup_spi19_default>; 1475 pinctrl-names = "default"; 1476 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1477 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1478 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1479 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1480 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1481 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1482 interconnect-names = "qup-core", 1483 "qup-config", 1484 "qup-memory"; 1485 power-domains = <&rpmhpd SA8775P_CX>; 1486 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1487 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1488 dma-names = "tx", 1489 "rx"; 1490 status = "disabled"; 1491 }; 1492 1493 uart19: serial@894000 { 1494 compatible = "qcom,geni-uart"; 1495 reg = <0x0 0x00894000 0x0 0x4000>; 1496 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1497 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1498 clock-names = "se"; 1499 pinctrl-0 = <&qup_uart19_default>; 1500 pinctrl-names = "default"; 1501 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1502 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1503 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1504 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1505 interconnect-names = "qup-core", "qup-config"; 1506 power-domains = <&rpmhpd SA8775P_CX>; 1507 status = "disabled"; 1508 }; 1509 1510 i2c20: i2c@898000 { 1511 compatible = "qcom,geni-i2c"; 1512 reg = <0x0 0x898000 0x0 0x4000>; 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1516 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1517 clock-names = "se"; 1518 pinctrl-0 = <&qup_i2c20_default>; 1519 pinctrl-names = "default"; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1521 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1522 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1523 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1524 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1525 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1526 interconnect-names = "qup-core", 1527 "qup-config", 1528 "qup-memory"; 1529 power-domains = <&rpmhpd SA8775P_CX>; 1530 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1531 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1532 dma-names = "tx", 1533 "rx"; 1534 status = "disabled"; 1535 }; 1536 1537 spi20: spi@898000 { 1538 compatible = "qcom,geni-spi"; 1539 reg = <0x0 0x898000 0x0 0x4000>; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1543 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1544 clock-names = "se"; 1545 pinctrl-0 = <&qup_spi20_default>; 1546 pinctrl-names = "default"; 1547 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1548 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1549 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1550 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1551 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1552 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1553 interconnect-names = "qup-core", 1554 "qup-config", 1555 "qup-memory"; 1556 power-domains = <&rpmhpd SA8775P_CX>; 1557 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1558 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1559 dma-names = "tx", 1560 "rx"; 1561 status = "disabled"; 1562 }; 1563 1564 uart20: serial@898000 { 1565 compatible = "qcom,geni-uart"; 1566 reg = <0x0 0x00898000 0x0 0x4000>; 1567 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1568 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1569 clock-names = "se"; 1570 pinctrl-0 = <&qup_uart20_default>; 1571 pinctrl-names = "default"; 1572 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1573 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1574 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1575 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1576 interconnect-names = "qup-core", "qup-config"; 1577 power-domains = <&rpmhpd SA8775P_CX>; 1578 status = "disabled"; 1579 }; 1580 1581 }; 1582 1583 gpi_dma0: dma-controller@900000 { 1584 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1585 reg = <0x0 0x00900000 0x0 0x60000>; 1586 #dma-cells = <3>; 1587 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1599 dma-channels = <12>; 1600 dma-channel-mask = <0xfff>; 1601 iommus = <&apps_smmu 0x416 0x0>; 1602 status = "disabled"; 1603 }; 1604 1605 qupv3_id_0: geniqup@9c0000 { 1606 compatible = "qcom,geni-se-qup"; 1607 reg = <0x0 0x9c0000 0x0 0x6000>; 1608 #address-cells = <2>; 1609 #size-cells = <2>; 1610 ranges; 1611 clock-names = "m-ahb", "s-ahb"; 1612 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1613 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1614 iommus = <&apps_smmu 0x403 0x0>; 1615 status = "disabled"; 1616 1617 i2c0: i2c@980000 { 1618 compatible = "qcom,geni-i2c"; 1619 reg = <0x0 0x980000 0x0 0x4000>; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1624 clock-names = "se"; 1625 pinctrl-0 = <&qup_i2c0_default>; 1626 pinctrl-names = "default"; 1627 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1628 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1629 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1630 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1631 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1632 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1633 interconnect-names = "qup-core", 1634 "qup-config", 1635 "qup-memory"; 1636 power-domains = <&rpmhpd SA8775P_CX>; 1637 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1638 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1639 dma-names = "tx", 1640 "rx"; 1641 status = "disabled"; 1642 }; 1643 1644 spi0: spi@980000 { 1645 compatible = "qcom,geni-spi"; 1646 reg = <0x0 0x980000 0x0 0x4000>; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1650 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1651 clock-names = "se"; 1652 pinctrl-0 = <&qup_spi0_default>; 1653 pinctrl-names = "default"; 1654 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1655 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1656 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1657 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1658 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1659 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1660 interconnect-names = "qup-core", 1661 "qup-config", 1662 "qup-memory"; 1663 power-domains = <&rpmhpd SA8775P_CX>; 1664 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1665 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1666 dma-names = "tx", 1667 "rx"; 1668 status = "disabled"; 1669 }; 1670 1671 uart0: serial@980000 { 1672 compatible = "qcom,geni-uart"; 1673 reg = <0x0 0x980000 0x0 0x4000>; 1674 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1675 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1676 clock-names = "se"; 1677 pinctrl-0 = <&qup_uart0_default>; 1678 pinctrl-names = "default"; 1679 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1680 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1681 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1682 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1683 interconnect-names = "qup-core", "qup-config"; 1684 power-domains = <&rpmhpd SA8775P_CX>; 1685 status = "disabled"; 1686 }; 1687 1688 i2c1: i2c@984000 { 1689 compatible = "qcom,geni-i2c"; 1690 reg = <0x0 0x984000 0x0 0x4000>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1694 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1695 clock-names = "se"; 1696 pinctrl-0 = <&qup_i2c1_default>; 1697 pinctrl-names = "default"; 1698 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1699 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1700 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1701 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1702 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1703 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1704 interconnect-names = "qup-core", 1705 "qup-config", 1706 "qup-memory"; 1707 power-domains = <&rpmhpd SA8775P_CX>; 1708 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1709 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1710 dma-names = "tx", 1711 "rx"; 1712 status = "disabled"; 1713 }; 1714 1715 spi1: spi@984000 { 1716 compatible = "qcom,geni-spi"; 1717 reg = <0x0 0x984000 0x0 0x4000>; 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1721 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1722 clock-names = "se"; 1723 pinctrl-0 = <&qup_spi1_default>; 1724 pinctrl-names = "default"; 1725 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1726 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1727 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1728 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1729 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1730 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1731 interconnect-names = "qup-core", 1732 "qup-config", 1733 "qup-memory"; 1734 power-domains = <&rpmhpd SA8775P_CX>; 1735 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1736 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1737 dma-names = "tx", 1738 "rx"; 1739 status = "disabled"; 1740 }; 1741 1742 uart1: serial@984000 { 1743 compatible = "qcom,geni-uart"; 1744 reg = <0x0 0x984000 0x0 0x4000>; 1745 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1746 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1747 clock-names = "se"; 1748 pinctrl-0 = <&qup_uart1_default>; 1749 pinctrl-names = "default"; 1750 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1751 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1752 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1753 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1754 interconnect-names = "qup-core", "qup-config"; 1755 power-domains = <&rpmhpd SA8775P_CX>; 1756 status = "disabled"; 1757 }; 1758 1759 i2c2: i2c@988000 { 1760 compatible = "qcom,geni-i2c"; 1761 reg = <0x0 0x988000 0x0 0x4000>; 1762 #address-cells = <1>; 1763 #size-cells = <0>; 1764 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1765 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1766 clock-names = "se"; 1767 pinctrl-0 = <&qup_i2c2_default>; 1768 pinctrl-names = "default"; 1769 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1770 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1771 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1772 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1773 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1774 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1775 interconnect-names = "qup-core", 1776 "qup-config", 1777 "qup-memory"; 1778 power-domains = <&rpmhpd SA8775P_CX>; 1779 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1780 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1781 dma-names = "tx", 1782 "rx"; 1783 status = "disabled"; 1784 }; 1785 1786 spi2: spi@988000 { 1787 compatible = "qcom,geni-spi"; 1788 reg = <0x0 0x988000 0x0 0x4000>; 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1792 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1793 clock-names = "se"; 1794 pinctrl-0 = <&qup_spi2_default>; 1795 pinctrl-names = "default"; 1796 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1797 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1798 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1799 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1800 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1801 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1802 interconnect-names = "qup-core", 1803 "qup-config", 1804 "qup-memory"; 1805 power-domains = <&rpmhpd SA8775P_CX>; 1806 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1807 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1808 dma-names = "tx", 1809 "rx"; 1810 status = "disabled"; 1811 }; 1812 1813 uart2: serial@988000 { 1814 compatible = "qcom,geni-uart"; 1815 reg = <0x0 0x988000 0x0 0x4000>; 1816 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1817 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1818 clock-names = "se"; 1819 pinctrl-0 = <&qup_uart2_default>; 1820 pinctrl-names = "default"; 1821 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1822 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1823 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1824 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1825 interconnect-names = "qup-core", "qup-config"; 1826 power-domains = <&rpmhpd SA8775P_CX>; 1827 status = "disabled"; 1828 }; 1829 1830 i2c3: i2c@98c000 { 1831 compatible = "qcom,geni-i2c"; 1832 reg = <0x0 0x98c000 0x0 0x4000>; 1833 #address-cells = <1>; 1834 #size-cells = <0>; 1835 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1836 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1837 clock-names = "se"; 1838 pinctrl-0 = <&qup_i2c3_default>; 1839 pinctrl-names = "default"; 1840 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1841 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1842 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1843 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1844 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1845 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1846 interconnect-names = "qup-core", 1847 "qup-config", 1848 "qup-memory"; 1849 power-domains = <&rpmhpd SA8775P_CX>; 1850 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1851 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1852 dma-names = "tx", 1853 "rx"; 1854 status = "disabled"; 1855 }; 1856 1857 spi3: spi@98c000 { 1858 compatible = "qcom,geni-spi"; 1859 reg = <0x0 0x98c000 0x0 0x4000>; 1860 #address-cells = <1>; 1861 #size-cells = <0>; 1862 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1863 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1864 clock-names = "se"; 1865 pinctrl-0 = <&qup_spi3_default>; 1866 pinctrl-names = "default"; 1867 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1868 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1869 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1870 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1871 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1872 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1873 interconnect-names = "qup-core", 1874 "qup-config", 1875 "qup-memory"; 1876 power-domains = <&rpmhpd SA8775P_CX>; 1877 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1878 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1879 dma-names = "tx", 1880 "rx"; 1881 status = "disabled"; 1882 }; 1883 1884 uart3: serial@98c000 { 1885 compatible = "qcom,geni-uart"; 1886 reg = <0x0 0x98c000 0x0 0x4000>; 1887 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1888 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1889 clock-names = "se"; 1890 pinctrl-0 = <&qup_uart3_default>; 1891 pinctrl-names = "default"; 1892 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1893 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1894 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1895 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1896 interconnect-names = "qup-core", "qup-config"; 1897 power-domains = <&rpmhpd SA8775P_CX>; 1898 status = "disabled"; 1899 }; 1900 1901 i2c4: i2c@990000 { 1902 compatible = "qcom,geni-i2c"; 1903 reg = <0x0 0x990000 0x0 0x4000>; 1904 #address-cells = <1>; 1905 #size-cells = <0>; 1906 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1907 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1908 clock-names = "se"; 1909 pinctrl-0 = <&qup_i2c4_default>; 1910 pinctrl-names = "default"; 1911 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1912 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1913 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1914 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1915 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1916 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1917 interconnect-names = "qup-core", 1918 "qup-config", 1919 "qup-memory"; 1920 power-domains = <&rpmhpd SA8775P_CX>; 1921 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1922 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1923 dma-names = "tx", 1924 "rx"; 1925 status = "disabled"; 1926 }; 1927 1928 spi4: spi@990000 { 1929 compatible = "qcom,geni-spi"; 1930 reg = <0x0 0x990000 0x0 0x4000>; 1931 #address-cells = <1>; 1932 #size-cells = <0>; 1933 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1934 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1935 clock-names = "se"; 1936 pinctrl-0 = <&qup_spi4_default>; 1937 pinctrl-names = "default"; 1938 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1939 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1940 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1941 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1942 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1943 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1944 interconnect-names = "qup-core", 1945 "qup-config", 1946 "qup-memory"; 1947 power-domains = <&rpmhpd SA8775P_CX>; 1948 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1949 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1950 dma-names = "tx", 1951 "rx"; 1952 status = "disabled"; 1953 }; 1954 1955 uart4: serial@990000 { 1956 compatible = "qcom,geni-uart"; 1957 reg = <0x0 0x990000 0x0 0x4000>; 1958 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1959 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1960 clock-names = "se"; 1961 pinctrl-0 = <&qup_uart4_default>; 1962 pinctrl-names = "default"; 1963 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1964 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1965 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1966 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1967 interconnect-names = "qup-core", "qup-config"; 1968 power-domains = <&rpmhpd SA8775P_CX>; 1969 status = "disabled"; 1970 }; 1971 1972 i2c5: i2c@994000 { 1973 compatible = "qcom,geni-i2c"; 1974 reg = <0x0 0x994000 0x0 0x4000>; 1975 #address-cells = <1>; 1976 #size-cells = <0>; 1977 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1978 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1979 clock-names = "se"; 1980 pinctrl-0 = <&qup_i2c5_default>; 1981 pinctrl-names = "default"; 1982 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1983 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1984 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1985 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1986 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1987 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1988 interconnect-names = "qup-core", 1989 "qup-config", 1990 "qup-memory"; 1991 power-domains = <&rpmhpd SA8775P_CX>; 1992 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1993 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1994 dma-names = "tx", 1995 "rx"; 1996 status = "disabled"; 1997 }; 1998 1999 spi5: spi@994000 { 2000 compatible = "qcom,geni-spi"; 2001 reg = <0x0 0x994000 0x0 0x4000>; 2002 #address-cells = <1>; 2003 #size-cells = <0>; 2004 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2005 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2006 clock-names = "se"; 2007 pinctrl-0 = <&qup_spi5_default>; 2008 pinctrl-names = "default"; 2009 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2010 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2011 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2012 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2013 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2014 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2015 interconnect-names = "qup-core", 2016 "qup-config", 2017 "qup-memory"; 2018 power-domains = <&rpmhpd SA8775P_CX>; 2019 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2020 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2021 dma-names = "tx", 2022 "rx"; 2023 status = "disabled"; 2024 }; 2025 2026 uart5: serial@994000 { 2027 compatible = "qcom,geni-uart"; 2028 reg = <0x0 0x994000 0x0 0x4000>; 2029 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2030 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2031 clock-names = "se"; 2032 pinctrl-0 = <&qup_uart5_default>; 2033 pinctrl-names = "default"; 2034 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2035 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2036 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2037 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2038 interconnect-names = "qup-core", "qup-config"; 2039 power-domains = <&rpmhpd SA8775P_CX>; 2040 status = "disabled"; 2041 }; 2042 }; 2043 2044 gpi_dma1: dma-controller@a00000 { 2045 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2046 reg = <0x0 0x00a00000 0x0 0x60000>; 2047 #dma-cells = <3>; 2048 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2060 iommus = <&apps_smmu 0x456 0x0>; 2061 dma-channels = <12>; 2062 dma-channel-mask = <0xfff>; 2063 status = "disabled"; 2064 }; 2065 2066 qupv3_id_1: geniqup@ac0000 { 2067 compatible = "qcom,geni-se-qup"; 2068 reg = <0x0 0x00ac0000 0x0 0x6000>; 2069 #address-cells = <2>; 2070 #size-cells = <2>; 2071 ranges; 2072 clock-names = "m-ahb", "s-ahb"; 2073 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 2074 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 2075 iommus = <&apps_smmu 0x443 0x0>; 2076 status = "disabled"; 2077 2078 i2c7: i2c@a80000 { 2079 compatible = "qcom,geni-i2c"; 2080 reg = <0x0 0xa80000 0x0 0x4000>; 2081 #address-cells = <1>; 2082 #size-cells = <0>; 2083 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2084 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2085 clock-names = "se"; 2086 pinctrl-0 = <&qup_i2c7_default>; 2087 pinctrl-names = "default"; 2088 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2089 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2090 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2091 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2092 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2093 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2094 interconnect-names = "qup-core", 2095 "qup-config", 2096 "qup-memory"; 2097 power-domains = <&rpmhpd SA8775P_CX>; 2098 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 2099 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 2100 dma-names = "tx", 2101 "rx"; 2102 status = "disabled"; 2103 }; 2104 2105 spi7: spi@a80000 { 2106 compatible = "qcom,geni-spi"; 2107 reg = <0x0 0xa80000 0x0 0x4000>; 2108 #address-cells = <1>; 2109 #size-cells = <0>; 2110 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2111 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2112 clock-names = "se"; 2113 pinctrl-0 = <&qup_spi7_default>; 2114 pinctrl-names = "default"; 2115 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2116 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2117 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2118 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2119 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2120 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2121 interconnect-names = "qup-core", 2122 "qup-config", 2123 "qup-memory"; 2124 power-domains = <&rpmhpd SA8775P_CX>; 2125 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 2126 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 2127 dma-names = "tx", 2128 "rx"; 2129 status = "disabled"; 2130 }; 2131 2132 uart7: serial@a80000 { 2133 compatible = "qcom,geni-uart"; 2134 reg = <0x0 0x00a80000 0x0 0x4000>; 2135 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2136 clock-names = "se"; 2137 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2138 pinctrl-0 = <&qup_uart7_default>; 2139 pinctrl-names = "default"; 2140 interconnect-names = "qup-core", "qup-config"; 2141 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2142 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2143 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2144 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2145 power-domains = <&rpmhpd SA8775P_CX>; 2146 operating-points-v2 = <&qup_opp_table_100mhz>; 2147 status = "disabled"; 2148 }; 2149 2150 i2c8: i2c@a84000 { 2151 compatible = "qcom,geni-i2c"; 2152 reg = <0x0 0xa84000 0x0 0x4000>; 2153 #address-cells = <1>; 2154 #size-cells = <0>; 2155 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2156 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2157 clock-names = "se"; 2158 pinctrl-0 = <&qup_i2c8_default>; 2159 pinctrl-names = "default"; 2160 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2161 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2162 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2163 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2164 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2165 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2166 interconnect-names = "qup-core", 2167 "qup-config", 2168 "qup-memory"; 2169 power-domains = <&rpmhpd SA8775P_CX>; 2170 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 2171 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 2172 dma-names = "tx", 2173 "rx"; 2174 status = "disabled"; 2175 }; 2176 2177 spi8: spi@a84000 { 2178 compatible = "qcom,geni-spi"; 2179 reg = <0x0 0xa84000 0x0 0x4000>; 2180 #address-cells = <1>; 2181 #size-cells = <0>; 2182 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2183 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2184 clock-names = "se"; 2185 pinctrl-0 = <&qup_spi8_default>; 2186 pinctrl-names = "default"; 2187 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2188 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2189 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2190 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2191 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2193 interconnect-names = "qup-core", 2194 "qup-config", 2195 "qup-memory"; 2196 power-domains = <&rpmhpd SA8775P_CX>; 2197 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 2198 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 2199 dma-names = "tx", 2200 "rx"; 2201 status = "disabled"; 2202 }; 2203 2204 uart8: serial@a84000 { 2205 compatible = "qcom,geni-uart"; 2206 reg = <0x0 0x00a84000 0x0 0x4000>; 2207 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2208 clock-names = "se"; 2209 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2210 pinctrl-0 = <&qup_uart8_default>; 2211 pinctrl-names = "default"; 2212 interconnect-names = "qup-core", "qup-config"; 2213 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2214 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2215 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2216 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2217 power-domains = <&rpmhpd SA8775P_CX>; 2218 operating-points-v2 = <&qup_opp_table_100mhz>; 2219 status = "disabled"; 2220 }; 2221 2222 i2c9: i2c@a88000 { 2223 compatible = "qcom,geni-i2c"; 2224 reg = <0x0 0xa88000 0x0 0x4000>; 2225 #address-cells = <1>; 2226 #size-cells = <0>; 2227 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2228 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2229 clock-names = "se"; 2230 pinctrl-0 = <&qup_i2c9_default>; 2231 pinctrl-names = "default"; 2232 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2233 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2234 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2235 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2236 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2237 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2238 interconnect-names = "qup-core", 2239 "qup-config", 2240 "qup-memory"; 2241 power-domains = <&rpmhpd SA8775P_CX>; 2242 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 2243 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 2244 dma-names = "tx", 2245 "rx"; 2246 status = "disabled"; 2247 }; 2248 2249 spi9: spi@a88000 { 2250 compatible = "qcom,geni-spi"; 2251 reg = <0x0 0xa88000 0x0 0x4000>; 2252 #address-cells = <1>; 2253 #size-cells = <0>; 2254 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2255 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2256 clock-names = "se"; 2257 pinctrl-0 = <&qup_spi9_default>; 2258 pinctrl-names = "default"; 2259 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2260 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2261 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2262 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2263 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2264 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2265 interconnect-names = "qup-core", 2266 "qup-config", 2267 "qup-memory"; 2268 power-domains = <&rpmhpd SA8775P_CX>; 2269 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 2270 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 2271 dma-names = "tx", 2272 "rx"; 2273 status = "disabled"; 2274 }; 2275 2276 uart9: serial@a88000 { 2277 compatible = "qcom,geni-uart"; 2278 reg = <0x0 0xa88000 0x0 0x4000>; 2279 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2280 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2281 clock-names = "se"; 2282 pinctrl-0 = <&qup_uart9_default>; 2283 pinctrl-names = "default"; 2284 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2285 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2286 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2287 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2288 interconnect-names = "qup-core", "qup-config"; 2289 power-domains = <&rpmhpd SA8775P_CX>; 2290 status = "disabled"; 2291 }; 2292 2293 i2c10: i2c@a8c000 { 2294 compatible = "qcom,geni-i2c"; 2295 reg = <0x0 0xa8c000 0x0 0x4000>; 2296 #address-cells = <1>; 2297 #size-cells = <0>; 2298 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2299 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2300 clock-names = "se"; 2301 pinctrl-0 = <&qup_i2c10_default>; 2302 pinctrl-names = "default"; 2303 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2304 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2305 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2306 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2307 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2308 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2309 interconnect-names = "qup-core", 2310 "qup-config", 2311 "qup-memory"; 2312 power-domains = <&rpmhpd SA8775P_CX>; 2313 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 2314 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 2315 dma-names = "tx", 2316 "rx"; 2317 status = "disabled"; 2318 }; 2319 2320 spi10: spi@a8c000 { 2321 compatible = "qcom,geni-spi"; 2322 reg = <0x0 0xa8c000 0x0 0x4000>; 2323 #address-cells = <1>; 2324 #size-cells = <0>; 2325 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2326 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2327 clock-names = "se"; 2328 pinctrl-0 = <&qup_spi10_default>; 2329 pinctrl-names = "default"; 2330 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2331 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2332 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2333 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2334 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2335 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2336 interconnect-names = "qup-core", 2337 "qup-config", 2338 "qup-memory"; 2339 power-domains = <&rpmhpd SA8775P_CX>; 2340 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 2341 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 2342 dma-names = "tx", 2343 "rx"; 2344 status = "disabled"; 2345 }; 2346 2347 uart10: serial@a8c000 { 2348 compatible = "qcom,geni-uart"; 2349 reg = <0x0 0x00a8c000 0x0 0x4000>; 2350 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2351 clock-names = "se"; 2352 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2353 pinctrl-0 = <&qup_uart10_default>; 2354 pinctrl-names = "default"; 2355 interconnect-names = "qup-core", "qup-config"; 2356 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 2357 &clk_virt SLAVE_QUP_CORE_1 0>, 2358 <&gem_noc MASTER_APPSS_PROC 0 2359 &config_noc SLAVE_QUP_1 0>; 2360 power-domains = <&rpmhpd SA8775P_CX>; 2361 operating-points-v2 = <&qup_opp_table_100mhz>; 2362 status = "disabled"; 2363 }; 2364 2365 i2c11: i2c@a90000 { 2366 compatible = "qcom,geni-i2c"; 2367 reg = <0x0 0xa90000 0x0 0x4000>; 2368 #address-cells = <1>; 2369 #size-cells = <0>; 2370 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2371 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2372 clock-names = "se"; 2373 pinctrl-0 = <&qup_i2c11_default>; 2374 pinctrl-names = "default"; 2375 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2376 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2377 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2378 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2379 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2380 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2381 interconnect-names = "qup-core", 2382 "qup-config", 2383 "qup-memory"; 2384 power-domains = <&rpmhpd SA8775P_CX>; 2385 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2386 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2387 dma-names = "tx", 2388 "rx"; 2389 status = "disabled"; 2390 }; 2391 2392 spi11: spi@a90000 { 2393 compatible = "qcom,geni-spi"; 2394 reg = <0x0 0xa90000 0x0 0x4000>; 2395 #address-cells = <1>; 2396 #size-cells = <0>; 2397 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2398 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2399 clock-names = "se"; 2400 pinctrl-0 = <&qup_spi11_default>; 2401 pinctrl-names = "default"; 2402 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2403 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2404 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2405 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2406 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2407 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2408 interconnect-names = "qup-core", 2409 "qup-config", 2410 "qup-memory"; 2411 power-domains = <&rpmhpd SA8775P_CX>; 2412 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2413 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2414 dma-names = "tx", 2415 "rx"; 2416 status = "disabled"; 2417 }; 2418 2419 uart11: serial@a90000 { 2420 compatible = "qcom,geni-uart"; 2421 reg = <0x0 0x00a90000 0x0 0x4000>; 2422 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2423 clock-names = "se"; 2424 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2425 pinctrl-0 = <&qup_uart11_default>; 2426 pinctrl-names = "default"; 2427 interconnect-names = "qup-core", "qup-config"; 2428 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2429 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2430 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2431 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2432 power-domains = <&rpmhpd SA8775P_CX>; 2433 operating-points-v2 = <&qup_opp_table_100mhz>; 2434 status = "disabled"; 2435 }; 2436 2437 i2c12: i2c@a94000 { 2438 compatible = "qcom,geni-i2c"; 2439 reg = <0x0 0xa94000 0x0 0x4000>; 2440 #address-cells = <1>; 2441 #size-cells = <0>; 2442 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2443 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2444 clock-names = "se"; 2445 pinctrl-0 = <&qup_i2c12_default>; 2446 pinctrl-names = "default"; 2447 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2448 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2449 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2450 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2451 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2452 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2453 interconnect-names = "qup-core", 2454 "qup-config", 2455 "qup-memory"; 2456 power-domains = <&rpmhpd SA8775P_CX>; 2457 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2458 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2459 dma-names = "tx", 2460 "rx"; 2461 status = "disabled"; 2462 }; 2463 2464 spi12: spi@a94000 { 2465 compatible = "qcom,geni-spi"; 2466 reg = <0x0 0xa94000 0x0 0x4000>; 2467 #address-cells = <1>; 2468 #size-cells = <0>; 2469 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2470 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2471 clock-names = "se"; 2472 pinctrl-0 = <&qup_spi12_default>; 2473 pinctrl-names = "default"; 2474 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2475 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2476 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2477 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2478 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2479 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2480 interconnect-names = "qup-core", 2481 "qup-config", 2482 "qup-memory"; 2483 power-domains = <&rpmhpd SA8775P_CX>; 2484 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2485 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2486 dma-names = "tx", 2487 "rx"; 2488 status = "disabled"; 2489 }; 2490 2491 uart12: serial@a94000 { 2492 compatible = "qcom,geni-uart"; 2493 reg = <0x0 0x00a94000 0x0 0x4000>; 2494 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2495 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2496 clock-names = "se"; 2497 pinctrl-0 = <&qup_uart12_default>; 2498 pinctrl-names = "default"; 2499 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2500 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2501 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2502 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2503 interconnect-names = "qup-core", "qup-config"; 2504 power-domains = <&rpmhpd SA8775P_CX>; 2505 status = "disabled"; 2506 }; 2507 2508 i2c13: i2c@a98000 { 2509 compatible = "qcom,geni-i2c"; 2510 reg = <0x0 0xa98000 0x0 0x4000>; 2511 #address-cells = <1>; 2512 #size-cells = <0>; 2513 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2514 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2515 clock-names = "se"; 2516 pinctrl-0 = <&qup_i2c13_default>; 2517 pinctrl-names = "default"; 2518 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2519 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2520 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2521 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2522 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2523 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2524 interconnect-names = "qup-core", 2525 "qup-config", 2526 "qup-memory"; 2527 power-domains = <&rpmhpd SA8775P_CX>; 2528 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2529 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2530 dma-names = "tx", 2531 "rx"; 2532 status = "disabled"; 2533 2534 }; 2535 }; 2536 2537 gpi_dma3: dma-controller@b00000 { 2538 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2539 reg = <0x0 0x00b00000 0x0 0x58000>; 2540 #dma-cells = <3>; 2541 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2542 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2543 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2544 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2545 iommus = <&apps_smmu 0x056 0x0>; 2546 dma-channels = <4>; 2547 dma-channel-mask = <0xf>; 2548 status = "disabled"; 2549 }; 2550 2551 qupv3_id_3: geniqup@bc0000 { 2552 compatible = "qcom,geni-se-qup"; 2553 reg = <0x0 0xbc0000 0x0 0x6000>; 2554 #address-cells = <2>; 2555 #size-cells = <2>; 2556 ranges; 2557 clock-names = "m-ahb", "s-ahb"; 2558 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2559 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2560 iommus = <&apps_smmu 0x43 0x0>; 2561 status = "disabled"; 2562 2563 i2c21: i2c@b80000 { 2564 compatible = "qcom,geni-i2c"; 2565 reg = <0x0 0xb80000 0x0 0x4000>; 2566 #address-cells = <1>; 2567 #size-cells = <0>; 2568 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2569 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2570 clock-names = "se"; 2571 pinctrl-0 = <&qup_i2c21_default>; 2572 pinctrl-names = "default"; 2573 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2574 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2575 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2576 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2577 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2578 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2579 interconnect-names = "qup-core", 2580 "qup-config", 2581 "qup-memory"; 2582 power-domains = <&rpmhpd SA8775P_CX>; 2583 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2584 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2585 dma-names = "tx", 2586 "rx"; 2587 status = "disabled"; 2588 }; 2589 2590 spi21: spi@b80000 { 2591 compatible = "qcom,geni-spi"; 2592 reg = <0x0 0xb80000 0x0 0x4000>; 2593 #address-cells = <1>; 2594 #size-cells = <0>; 2595 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2596 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2597 clock-names = "se"; 2598 pinctrl-0 = <&qup_spi21_default>; 2599 pinctrl-names = "default"; 2600 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2601 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2602 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2603 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2604 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2605 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2606 interconnect-names = "qup-core", 2607 "qup-config", 2608 "qup-memory"; 2609 power-domains = <&rpmhpd SA8775P_CX>; 2610 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2611 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2612 dma-names = "tx", 2613 "rx"; 2614 status = "disabled"; 2615 }; 2616 2617 uart21: serial@b80000 { 2618 compatible = "qcom,geni-uart"; 2619 reg = <0x0 0x00b80000 0x0 0x4000>; 2620 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2621 clock-names = "se"; 2622 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2623 interconnect-names = "qup-core", "qup-config"; 2624 pinctrl-0 = <&qup_uart21_default>; 2625 pinctrl-names = "default"; 2626 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2627 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2628 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2629 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2630 power-domains = <&rpmhpd SA8775P_CX>; 2631 operating-points-v2 = <&qup_opp_table_100mhz>; 2632 status = "disabled"; 2633 }; 2634 }; 2635 2636 rng: rng@10d2000 { 2637 compatible = "qcom,sa8775p-trng", "qcom,trng"; 2638 reg = <0 0x010d2000 0 0x1000>; 2639 }; 2640 2641 config_noc: interconnect@14c0000 { 2642 compatible = "qcom,sa8775p-config-noc"; 2643 reg = <0x0 0x014c0000 0x0 0x13080>; 2644 #interconnect-cells = <2>; 2645 qcom,bcm-voters = <&apps_bcm_voter>; 2646 }; 2647 2648 system_noc: interconnect@1680000 { 2649 compatible = "qcom,sa8775p-system-noc"; 2650 reg = <0x0 0x01680000 0x0 0x15080>; 2651 #interconnect-cells = <2>; 2652 qcom,bcm-voters = <&apps_bcm_voter>; 2653 }; 2654 2655 aggre1_noc: interconnect@16c0000 { 2656 compatible = "qcom,sa8775p-aggre1-noc"; 2657 reg = <0x0 0x016c0000 0x0 0x18080>; 2658 #interconnect-cells = <2>; 2659 qcom,bcm-voters = <&apps_bcm_voter>; 2660 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2661 <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, 2662 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 2663 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2664 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; 2665 }; 2666 2667 aggre2_noc: interconnect@1700000 { 2668 compatible = "qcom,sa8775p-aggre2-noc"; 2669 reg = <0x0 0x01700000 0x0 0x1b080>; 2670 #interconnect-cells = <2>; 2671 qcom,bcm-voters = <&apps_bcm_voter>; 2672 clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2673 <&rpmhcc RPMH_IPA_CLK>; 2674 }; 2675 2676 pcie_anoc: interconnect@1760000 { 2677 compatible = "qcom,sa8775p-pcie-anoc"; 2678 reg = <0x0 0x01760000 0x0 0xc080>; 2679 #interconnect-cells = <2>; 2680 qcom,bcm-voters = <&apps_bcm_voter>; 2681 }; 2682 2683 gpdsp_anoc: interconnect@1780000 { 2684 compatible = "qcom,sa8775p-gpdsp-anoc"; 2685 reg = <0x0 0x01780000 0x0 0xe080>; 2686 #interconnect-cells = <2>; 2687 qcom,bcm-voters = <&apps_bcm_voter>; 2688 }; 2689 2690 mmss_noc: interconnect@17a0000 { 2691 compatible = "qcom,sa8775p-mmss-noc"; 2692 reg = <0x0 0x017a0000 0x0 0x40000>; 2693 #interconnect-cells = <2>; 2694 qcom,bcm-voters = <&apps_bcm_voter>; 2695 }; 2696 2697 pcie0: pcie@1c00000 { 2698 compatible = "qcom,pcie-sa8775p"; 2699 reg = <0x0 0x01c00000 0x0 0x3000>, 2700 <0x0 0x40000000 0x0 0xf20>, 2701 <0x0 0x40000f20 0x0 0xa8>, 2702 <0x0 0x40001000 0x0 0x4000>, 2703 <0x0 0x40100000 0x0 0x100000>, 2704 <0x0 0x01c03000 0x0 0x1000>; 2705 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2706 device_type = "pci"; 2707 2708 #address-cells = <3>; 2709 #size-cells = <2>; 2710 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2711 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2712 bus-range = <0x00 0xff>; 2713 2714 dma-coherent; 2715 2716 linux,pci-domain = <0>; 2717 num-lanes = <2>; 2718 2719 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2721 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2723 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2724 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2725 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2726 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2727 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2728 interrupt-names = "msi0", 2729 "msi1", 2730 "msi2", 2731 "msi3", 2732 "msi4", 2733 "msi5", 2734 "msi6", 2735 "msi7", 2736 "global"; 2737 #interrupt-cells = <1>; 2738 interrupt-map-mask = <0 0 0 0x7>; 2739 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2740 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2741 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 2742 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 2743 2744 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2745 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2746 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2747 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2748 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 2749 2750 clock-names = "aux", 2751 "cfg", 2752 "bus_master", 2753 "bus_slave", 2754 "slave_q2a"; 2755 2756 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 2757 assigned-clock-rates = <19200000>; 2758 2759 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 2760 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 2761 interconnect-names = "pcie-mem", "cpu-pcie"; 2762 2763 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 2764 <0x100 &pcie_smmu 0x0001 0x1>; 2765 2766 resets = <&gcc GCC_PCIE_0_BCR>, 2767 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; 2768 reset-names = "pci", 2769 "link_down"; 2770 2771 power-domains = <&gcc PCIE_0_GDSC>; 2772 2773 phys = <&pcie0_phy>; 2774 phy-names = "pciephy"; 2775 2776 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2777 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2778 2779 status = "disabled"; 2780 2781 pcieport0: pcie@0 { 2782 device_type = "pci"; 2783 reg = <0x0 0x0 0x0 0x0 0x0>; 2784 bus-range = <0x01 0xff>; 2785 2786 #address-cells = <3>; 2787 #size-cells = <2>; 2788 ranges; 2789 }; 2790 }; 2791 2792 pcie0_ep: pcie-ep@1c00000 { 2793 compatible = "qcom,sa8775p-pcie-ep"; 2794 reg = <0x0 0x01c00000 0x0 0x3000>, 2795 <0x0 0x40000000 0x0 0xf20>, 2796 <0x0 0x40000f20 0x0 0xa8>, 2797 <0x0 0x40001000 0x0 0x4000>, 2798 <0x0 0x40200000 0x0 0x1fe00000>, 2799 <0x0 0x01c03000 0x0 0x1000>, 2800 <0x0 0x40005000 0x0 0x2000>; 2801 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 2802 "mmio", "dma"; 2803 2804 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2805 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2806 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2807 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2808 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 2809 2810 clock-names = "aux", 2811 "cfg", 2812 "bus_master", 2813 "bus_slave", 2814 "slave_q2a"; 2815 2816 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2817 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2818 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; 2819 2820 interrupt-names = "global", "doorbell", "dma"; 2821 2822 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 2823 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 2824 interconnect-names = "pcie-mem", "cpu-pcie"; 2825 2826 dma-coherent; 2827 iommus = <&pcie_smmu 0x0000 0x7f>; 2828 resets = <&gcc GCC_PCIE_0_BCR>; 2829 reset-names = "core"; 2830 power-domains = <&gcc PCIE_0_GDSC>; 2831 phys = <&pcie0_phy>; 2832 phy-names = "pciephy"; 2833 num-lanes = <2>; 2834 linux,pci-domain = <0>; 2835 2836 status = "disabled"; 2837 }; 2838 2839 pcie0_phy: phy@1c04000 { 2840 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 2841 reg = <0x0 0x1c04000 0x0 0x2000>; 2842 2843 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, 2844 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2845 <&gcc GCC_PCIE_CLKREF_EN>, 2846 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2847 <&gcc GCC_PCIE_0_PIPE_CLK>, 2848 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; 2849 clock-names = "aux", 2850 "cfg_ahb", 2851 "ref", 2852 "rchng", 2853 "pipe", 2854 "pipediv2"; 2855 2856 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2857 assigned-clock-rates = <100000000>; 2858 2859 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2860 reset-names = "phy"; 2861 2862 #clock-cells = <0>; 2863 clock-output-names = "pcie_0_pipe_clk"; 2864 2865 #phy-cells = <0>; 2866 2867 status = "disabled"; 2868 }; 2869 2870 pcie1: pcie@1c10000 { 2871 compatible = "qcom,pcie-sa8775p"; 2872 reg = <0x0 0x01c10000 0x0 0x3000>, 2873 <0x0 0x60000000 0x0 0xf20>, 2874 <0x0 0x60000f20 0x0 0xa8>, 2875 <0x0 0x60001000 0x0 0x4000>, 2876 <0x0 0x60100000 0x0 0x100000>, 2877 <0x0 0x01c13000 0x0 0x1000>; 2878 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2879 device_type = "pci"; 2880 2881 #address-cells = <3>; 2882 #size-cells = <2>; 2883 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2884 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 2885 bus-range = <0x00 0xff>; 2886 2887 dma-coherent; 2888 2889 linux,pci-domain = <1>; 2890 num-lanes = <4>; 2891 2892 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 2893 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2894 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2895 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2896 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2897 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2898 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2899 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2900 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; 2901 interrupt-names = "msi0", 2902 "msi1", 2903 "msi2", 2904 "msi3", 2905 "msi4", 2906 "msi5", 2907 "msi6", 2908 "msi7", 2909 "global"; 2910 #interrupt-cells = <1>; 2911 interrupt-map-mask = <0 0 0 0x7>; 2912 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2913 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2914 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2915 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2916 2917 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2918 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2919 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2920 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2921 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 2922 2923 clock-names = "aux", 2924 "cfg", 2925 "bus_master", 2926 "bus_slave", 2927 "slave_q2a"; 2928 2929 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2930 assigned-clock-rates = <19200000>; 2931 2932 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 2933 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 2934 interconnect-names = "pcie-mem", "cpu-pcie"; 2935 2936 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 2937 <0x100 &pcie_smmu 0x0081 0x1>; 2938 2939 resets = <&gcc GCC_PCIE_1_BCR>, 2940 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2941 reset-names = "pci", 2942 "link_down"; 2943 2944 power-domains = <&gcc PCIE_1_GDSC>; 2945 2946 phys = <&pcie1_phy>; 2947 phy-names = "pciephy"; 2948 2949 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 2950 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 2951 2952 status = "disabled"; 2953 2954 pcie@0 { 2955 device_type = "pci"; 2956 reg = <0x0 0x0 0x0 0x0 0x0>; 2957 bus-range = <0x01 0xff>; 2958 2959 #address-cells = <3>; 2960 #size-cells = <2>; 2961 ranges; 2962 }; 2963 }; 2964 2965 pcie1_ep: pcie-ep@1c10000 { 2966 compatible = "qcom,sa8775p-pcie-ep"; 2967 reg = <0x0 0x01c10000 0x0 0x3000>, 2968 <0x0 0x60000000 0x0 0xf20>, 2969 <0x0 0x60000f20 0x0 0xa8>, 2970 <0x0 0x60001000 0x0 0x4000>, 2971 <0x0 0x60200000 0x0 0x1fe00000>, 2972 <0x0 0x01c13000 0x0 0x1000>, 2973 <0x0 0x60005000 0x0 0x2000>; 2974 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 2975 "mmio", "dma"; 2976 2977 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2978 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2979 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2980 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2981 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 2982 2983 clock-names = "aux", 2984 "cfg", 2985 "bus_master", 2986 "bus_slave", 2987 "slave_q2a"; 2988 2989 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 2990 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 2991 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 2992 2993 interrupt-names = "global", "doorbell", "dma"; 2994 2995 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 2996 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 2997 interconnect-names = "pcie-mem", "cpu-pcie"; 2998 2999 dma-coherent; 3000 iommus = <&pcie_smmu 0x80 0x7f>; 3001 resets = <&gcc GCC_PCIE_1_BCR>; 3002 reset-names = "core"; 3003 power-domains = <&gcc PCIE_1_GDSC>; 3004 phys = <&pcie1_phy>; 3005 phy-names = "pciephy"; 3006 num-lanes = <4>; 3007 linux,pci-domain = <1>; 3008 3009 status = "disabled"; 3010 }; 3011 3012 pcie1_phy: phy@1c14000 { 3013 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 3014 reg = <0x0 0x1c14000 0x0 0x4000>; 3015 3016 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 3017 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3018 <&gcc GCC_PCIE_CLKREF_EN>, 3019 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 3020 <&gcc GCC_PCIE_1_PIPE_CLK>, 3021 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; 3022 clock-names = "aux", 3023 "cfg_ahb", 3024 "ref", 3025 "rchng", 3026 "pipe", 3027 "pipediv2"; 3028 3029 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 3030 assigned-clock-rates = <100000000>; 3031 3032 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 3033 reset-names = "phy"; 3034 3035 #clock-cells = <0>; 3036 clock-output-names = "pcie_1_pipe_clk"; 3037 3038 #phy-cells = <0>; 3039 3040 status = "disabled"; 3041 }; 3042 3043 ufs_mem_hc: ufshc@1d84000 { 3044 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 3045 reg = <0x0 0x01d84000 0x0 0x3000>; 3046 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 3047 phys = <&ufs_mem_phy>; 3048 phy-names = "ufsphy"; 3049 lanes-per-direction = <2>; 3050 #reset-cells = <1>; 3051 resets = <&gcc GCC_UFS_PHY_BCR>; 3052 reset-names = "rst"; 3053 power-domains = <&gcc UFS_PHY_GDSC>; 3054 required-opps = <&rpmhpd_opp_nom>; 3055 iommus = <&apps_smmu 0x100 0x0>; 3056 dma-coherent; 3057 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 3058 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3059 <&gcc GCC_UFS_PHY_AHB_CLK>, 3060 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 3061 <&rpmhcc RPMH_CXO_CLK>, 3062 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 3063 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 3064 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 3065 clock-names = "core_clk", 3066 "bus_aggr_clk", 3067 "iface_clk", 3068 "core_clk_unipro", 3069 "ref_clk", 3070 "tx_lane0_sync_clk", 3071 "rx_lane0_sync_clk", 3072 "rx_lane1_sync_clk"; 3073 freq-table-hz = <75000000 300000000>, 3074 <0 0>, 3075 <0 0>, 3076 <75000000 300000000>, 3077 <0 0>, 3078 <0 0>, 3079 <0 0>, 3080 <0 0>; 3081 qcom,ice = <&ice>; 3082 status = "disabled"; 3083 }; 3084 3085 ufs_mem_phy: phy@1d87000 { 3086 compatible = "qcom,sa8775p-qmp-ufs-phy"; 3087 reg = <0x0 0x01d87000 0x0 0xe10>; 3088 /* 3089 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 3090 * enables the CXO clock to eDP *and* UFS PHY. 3091 */ 3092 clocks = <&rpmhcc RPMH_CXO_CLK>, 3093 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 3094 <&gcc GCC_EDP_REF_CLKREF_EN>; 3095 clock-names = "ref", "ref_aux", "qref"; 3096 power-domains = <&gcc UFS_PHY_GDSC>; 3097 resets = <&ufs_mem_hc 0>; 3098 reset-names = "ufsphy"; 3099 #phy-cells = <0>; 3100 status = "disabled"; 3101 }; 3102 3103 ice: crypto@1d88000 { 3104 compatible = "qcom,sa8775p-inline-crypto-engine", 3105 "qcom,inline-crypto-engine"; 3106 reg = <0x0 0x01d88000 0x0 0x18000>; 3107 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, 3108 <&gcc GCC_UFS_PHY_AHB_CLK>; 3109 clock-names = "core", 3110 "iface"; 3111 power-domains = <&gcc UFS_PHY_GDSC>; 3112 }; 3113 3114 cryptobam: dma-controller@1dc4000 { 3115 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 3116 reg = <0x0 0x01dc4000 0x0 0x28000>; 3117 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3118 #dma-cells = <1>; 3119 qcom,ee = <0>; 3120 qcom,num-ees = <4>; 3121 num-channels = <20>; 3122 qcom,controlled-remotely; 3123 iommus = <&apps_smmu 0x480 0x00>, 3124 <&apps_smmu 0x481 0x00>; 3125 }; 3126 3127 crypto: crypto@1dfa000 { 3128 compatible = "qcom,sa8775p-qce", "qcom,sm8150-qce", "qcom,qce"; 3129 reg = <0x0 0x01dfa000 0x0 0x6000>; 3130 dmas = <&cryptobam 4>, <&cryptobam 5>; 3131 dma-names = "rx", "tx"; 3132 iommus = <&apps_smmu 0x480 0x0>, 3133 <&apps_smmu 0x481 0x0>; 3134 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS 3135 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3136 interconnect-names = "memory"; 3137 }; 3138 3139 lpass_ag_noc: interconnect@3c40000 { 3140 compatible = "qcom,sa8775p-lpass-ag-noc"; 3141 reg = <0x0 0x03c40000 0x0 0x17200>; 3142 #interconnect-cells = <2>; 3143 qcom,bcm-voters = <&apps_bcm_voter>; 3144 }; 3145 3146 ctcu@4001000 { 3147 compatible = "qcom,sa8775p-ctcu"; 3148 reg = <0x0 0x04001000 0x0 0x1000>; 3149 3150 clocks = <&aoss_qmp>; 3151 clock-names = "apb"; 3152 3153 in-ports { 3154 #address-cells = <1>; 3155 #size-cells = <0>; 3156 3157 port@0 { 3158 reg = <0>; 3159 3160 ctcu_in0: endpoint { 3161 remote-endpoint = <&etr0_out>; 3162 }; 3163 }; 3164 3165 port@1 { 3166 reg = <1>; 3167 3168 ctcu_in1: endpoint { 3169 remote-endpoint = <&etr1_out>; 3170 }; 3171 }; 3172 }; 3173 }; 3174 3175 stm: stm@4002000 { 3176 compatible = "arm,coresight-stm", "arm,primecell"; 3177 reg = <0x0 0x4002000 0x0 0x1000>, 3178 <0x0 0x16280000 0x0 0x180000>; 3179 reg-names = "stm-base", "stm-stimulus-base"; 3180 3181 clocks = <&aoss_qmp>; 3182 clock-names = "apb_pclk"; 3183 3184 out-ports { 3185 port { 3186 stm_out: endpoint { 3187 remote-endpoint = 3188 <&funnel0_in7>; 3189 }; 3190 }; 3191 }; 3192 }; 3193 3194 tpdm@4003000 { 3195 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3196 reg = <0x0 0x4003000 0x0 0x1000>; 3197 3198 clocks = <&aoss_qmp>; 3199 clock-names = "apb_pclk"; 3200 3201 qcom,cmb-element-bits = <32>; 3202 qcom,cmb-msrs-num = <32>; 3203 status = "disabled"; 3204 3205 out-ports { 3206 port { 3207 qdss_tpdm0_out: endpoint { 3208 remote-endpoint = 3209 <&qdss_tpda_in0>; 3210 }; 3211 }; 3212 }; 3213 }; 3214 3215 tpda@4004000 { 3216 compatible = "qcom,coresight-tpda", "arm,primecell"; 3217 reg = <0x0 0x4004000 0x0 0x1000>; 3218 3219 clocks = <&aoss_qmp>; 3220 clock-names = "apb_pclk"; 3221 3222 out-ports { 3223 port { 3224 qdss_tpda_out: endpoint { 3225 remote-endpoint = 3226 <&funnel0_in6>; 3227 }; 3228 }; 3229 }; 3230 3231 in-ports { 3232 #address-cells = <1>; 3233 #size-cells = <0>; 3234 3235 port@0 { 3236 reg = <0>; 3237 qdss_tpda_in0: endpoint { 3238 remote-endpoint = 3239 <&qdss_tpdm0_out>; 3240 }; 3241 }; 3242 3243 port@1 { 3244 reg = <1>; 3245 qdss_tpda_in1: endpoint { 3246 remote-endpoint = 3247 <&qdss_tpdm1_out>; 3248 }; 3249 }; 3250 }; 3251 }; 3252 3253 tpdm@400f000 { 3254 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3255 reg = <0x0 0x400f000 0x0 0x1000>; 3256 3257 clocks = <&aoss_qmp>; 3258 clock-names = "apb_pclk"; 3259 3260 qcom,cmb-element-bits = <32>; 3261 qcom,cmb-msrs-num = <32>; 3262 3263 out-ports { 3264 port { 3265 qdss_tpdm1_out: endpoint { 3266 remote-endpoint = 3267 <&qdss_tpda_in1>; 3268 }; 3269 }; 3270 }; 3271 }; 3272 3273 funnel@4041000 { 3274 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3275 reg = <0x0 0x4041000 0x0 0x1000>; 3276 3277 clocks = <&aoss_qmp>; 3278 clock-names = "apb_pclk"; 3279 3280 out-ports { 3281 port { 3282 funnel0_out: endpoint { 3283 remote-endpoint = 3284 <&qdss_funnel_in0>; 3285 }; 3286 }; 3287 }; 3288 3289 in-ports { 3290 #address-cells = <1>; 3291 #size-cells = <0>; 3292 3293 port@6 { 3294 reg = <6>; 3295 funnel0_in6: endpoint { 3296 remote-endpoint = 3297 <&qdss_tpda_out>; 3298 }; 3299 }; 3300 3301 port@7 { 3302 reg = <7>; 3303 funnel0_in7: endpoint { 3304 remote-endpoint = 3305 <&stm_out>; 3306 }; 3307 }; 3308 }; 3309 }; 3310 3311 funnel@4042000 { 3312 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3313 reg = <0x0 0x4042000 0x0 0x1000>; 3314 3315 clocks = <&aoss_qmp>; 3316 clock-names = "apb_pclk"; 3317 3318 out-ports { 3319 port { 3320 funnel1_out: endpoint { 3321 remote-endpoint = 3322 <&qdss_funnel_in1>; 3323 }; 3324 }; 3325 }; 3326 3327 in-ports { 3328 #address-cells = <1>; 3329 #size-cells = <0>; 3330 3331 port@4 { 3332 reg = <4>; 3333 funnel1_in4: endpoint { 3334 remote-endpoint = 3335 <&apss_funnel1_out>; 3336 }; 3337 }; 3338 3339 port@5 { 3340 reg = <5>; 3341 3342 funnel1_in5: endpoint { 3343 remote-endpoint = <&dlct0_funnel_out>; 3344 }; 3345 }; 3346 }; 3347 }; 3348 3349 funnel@4045000 { 3350 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3351 reg = <0x0 0x4045000 0x0 0x1000>; 3352 3353 clocks = <&aoss_qmp>; 3354 clock-names = "apb_pclk"; 3355 3356 out-ports { 3357 port { 3358 qdss_funnel_out: endpoint { 3359 remote-endpoint = 3360 <&aoss_funnel_in7>; 3361 }; 3362 }; 3363 }; 3364 3365 in-ports { 3366 #address-cells = <1>; 3367 #size-cells = <0>; 3368 3369 port@0 { 3370 reg = <0>; 3371 qdss_funnel_in0: endpoint { 3372 remote-endpoint = 3373 <&funnel0_out>; 3374 }; 3375 }; 3376 3377 port@1 { 3378 reg = <1>; 3379 qdss_funnel_in1: endpoint { 3380 remote-endpoint = 3381 <&funnel1_out>; 3382 }; 3383 }; 3384 }; 3385 }; 3386 3387 replicator@4046000 { 3388 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3389 reg = <0x0 0x04046000 0x0 0x1000>; 3390 3391 clocks = <&aoss_qmp>; 3392 clock-names = "apb_pclk"; 3393 3394 in-ports { 3395 port { 3396 qdss_rep_in: endpoint { 3397 remote-endpoint = <&swao_rep_out0>; 3398 }; 3399 }; 3400 }; 3401 3402 out-ports { 3403 port { 3404 qdss_rep_out0: endpoint { 3405 remote-endpoint = <&etr_rep_in>; 3406 }; 3407 }; 3408 }; 3409 }; 3410 3411 tmc_etr: tmc@4048000 { 3412 compatible = "arm,coresight-tmc", "arm,primecell"; 3413 reg = <0x0 0x04048000 0x0 0x1000>; 3414 3415 clocks = <&aoss_qmp>; 3416 clock-names = "apb_pclk"; 3417 iommus = <&apps_smmu 0x04c0 0x00>; 3418 3419 arm,scatter-gather; 3420 3421 in-ports { 3422 port { 3423 etr0_in: endpoint { 3424 remote-endpoint = <&etr_rep_out0>; 3425 }; 3426 }; 3427 }; 3428 3429 out-ports { 3430 port { 3431 etr0_out: endpoint { 3432 remote-endpoint = <&ctcu_in0>; 3433 }; 3434 }; 3435 }; 3436 }; 3437 3438 replicator@404e000 { 3439 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3440 reg = <0x0 0x0404e000 0x0 0x1000>; 3441 3442 clocks = <&aoss_qmp>; 3443 clock-names = "apb_pclk"; 3444 3445 in-ports { 3446 port { 3447 etr_rep_in: endpoint { 3448 remote-endpoint = <&qdss_rep_out0>; 3449 }; 3450 }; 3451 }; 3452 3453 out-ports { 3454 #address-cells = <1>; 3455 #size-cells = <0>; 3456 3457 port@0 { 3458 reg = <0>; 3459 3460 etr_rep_out0: endpoint { 3461 remote-endpoint = <&etr0_in>; 3462 }; 3463 }; 3464 3465 port@1 { 3466 reg = <1>; 3467 3468 etr_rep_out1: endpoint { 3469 remote-endpoint = <&etr1_in>; 3470 }; 3471 }; 3472 }; 3473 }; 3474 3475 tmc_etr1: tmc@404f000 { 3476 compatible = "arm,coresight-tmc", "arm,primecell"; 3477 reg = <0x0 0x0404f000 0x0 0x1000>; 3478 3479 clocks = <&aoss_qmp>; 3480 clock-names = "apb_pclk"; 3481 iommus = <&apps_smmu 0x04a0 0x40>; 3482 3483 arm,scatter-gather; 3484 arm,buffer-size = <0x400000>; 3485 3486 in-ports { 3487 port { 3488 etr1_in: endpoint { 3489 remote-endpoint = <&etr_rep_out1>; 3490 }; 3491 }; 3492 }; 3493 3494 out-ports { 3495 port { 3496 etr1_out: endpoint { 3497 remote-endpoint = <&ctcu_in1>; 3498 }; 3499 }; 3500 }; 3501 }; 3502 3503 tpda@4ad3000 { 3504 compatible = "qcom,coresight-tpda", "arm,primecell"; 3505 reg = <0x0 0x4ad3000 0x0 0x1000>; 3506 3507 clocks = <&aoss_qmp>; 3508 clock-names = "apb_pclk"; 3509 3510 in-ports { 3511 #address-cells = <1>; 3512 #size-cells = <0>; 3513 3514 port@10 { 3515 reg = <16>; 3516 dlct0_tpda_in16: endpoint { 3517 remote-endpoint = <&turing0_funnel_out>; 3518 }; 3519 }; 3520 }; 3521 3522 out-ports { 3523 port { 3524 dlct0_tpda_out: endpoint { 3525 remote-endpoint = 3526 <&dlct0_funnel_in0>; 3527 }; 3528 }; 3529 }; 3530 3531 }; 3532 3533 funnel@4ad4000 { 3534 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3535 reg = <0x0 0x4ad4000 0x0 0x1000>; 3536 3537 clocks = <&aoss_qmp>; 3538 clock-names = "apb_pclk"; 3539 3540 in-ports { 3541 port { 3542 dlct0_funnel_in0: endpoint { 3543 remote-endpoint = <&dlct0_tpda_out>; 3544 }; 3545 }; 3546 }; 3547 3548 out-ports { 3549 port { 3550 dlct0_funnel_out: endpoint { 3551 remote-endpoint = <&funnel1_in5>; 3552 }; 3553 }; 3554 }; 3555 }; 3556 3557 funnel@4b04000 { 3558 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3559 reg = <0x0 0x4b04000 0x0 0x1000>; 3560 3561 clocks = <&aoss_qmp>; 3562 clock-names = "apb_pclk"; 3563 3564 out-ports { 3565 port { 3566 aoss_funnel_out: endpoint { 3567 remote-endpoint = 3568 <&etf0_in>; 3569 }; 3570 }; 3571 }; 3572 3573 in-ports { 3574 #address-cells = <1>; 3575 #size-cells = <0>; 3576 3577 port@6 { 3578 reg = <6>; 3579 aoss_funnel_in6: endpoint { 3580 remote-endpoint = 3581 <&aoss_tpda_out>; 3582 }; 3583 }; 3584 3585 port@7 { 3586 reg = <7>; 3587 aoss_funnel_in7: endpoint { 3588 remote-endpoint = 3589 <&qdss_funnel_out>; 3590 }; 3591 }; 3592 }; 3593 }; 3594 3595 tmc_etf: tmc@4b05000 { 3596 compatible = "arm,coresight-tmc", "arm,primecell"; 3597 reg = <0x0 0x4b05000 0x0 0x1000>; 3598 3599 clocks = <&aoss_qmp>; 3600 clock-names = "apb_pclk"; 3601 3602 out-ports { 3603 port { 3604 etf0_out: endpoint { 3605 remote-endpoint = 3606 <&swao_rep_in>; 3607 }; 3608 }; 3609 }; 3610 3611 in-ports { 3612 port { 3613 etf0_in: endpoint { 3614 remote-endpoint = 3615 <&aoss_funnel_out>; 3616 }; 3617 }; 3618 }; 3619 }; 3620 3621 replicator@4b06000 { 3622 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3623 reg = <0x0 0x4b06000 0x0 0x1000>; 3624 3625 clocks = <&aoss_qmp>; 3626 clock-names = "apb_pclk"; 3627 3628 out-ports { 3629 #address-cells = <1>; 3630 #size-cells = <0>; 3631 3632 port@0 { 3633 reg = <0>; 3634 3635 swao_rep_out0: endpoint { 3636 remote-endpoint = <&qdss_rep_in>; 3637 }; 3638 }; 3639 3640 port@1 { 3641 reg = <1>; 3642 swao_rep_out1: endpoint { 3643 remote-endpoint = 3644 <&eud_in>; 3645 }; 3646 }; 3647 }; 3648 3649 in-ports { 3650 port { 3651 swao_rep_in: endpoint { 3652 remote-endpoint = 3653 <&etf0_out>; 3654 }; 3655 }; 3656 }; 3657 }; 3658 3659 tpda@4b08000 { 3660 compatible = "qcom,coresight-tpda", "arm,primecell"; 3661 reg = <0x0 0x4b08000 0x0 0x1000>; 3662 3663 clocks = <&aoss_qmp>; 3664 clock-names = "apb_pclk"; 3665 3666 out-ports { 3667 port { 3668 aoss_tpda_out: endpoint { 3669 remote-endpoint = 3670 <&aoss_funnel_in6>; 3671 }; 3672 }; 3673 }; 3674 3675 in-ports { 3676 #address-cells = <1>; 3677 #size-cells = <0>; 3678 3679 port@0 { 3680 reg = <0>; 3681 aoss_tpda_in0: endpoint { 3682 remote-endpoint = 3683 <&aoss_tpdm0_out>; 3684 }; 3685 }; 3686 3687 port@1 { 3688 reg = <1>; 3689 aoss_tpda_in1: endpoint { 3690 remote-endpoint = 3691 <&aoss_tpdm1_out>; 3692 }; 3693 }; 3694 3695 port@2 { 3696 reg = <2>; 3697 aoss_tpda_in2: endpoint { 3698 remote-endpoint = 3699 <&aoss_tpdm2_out>; 3700 }; 3701 }; 3702 3703 port@3 { 3704 reg = <3>; 3705 aoss_tpda_in3: endpoint { 3706 remote-endpoint = 3707 <&aoss_tpdm3_out>; 3708 }; 3709 }; 3710 3711 port@4 { 3712 reg = <4>; 3713 aoss_tpda_in4: endpoint { 3714 remote-endpoint = 3715 <&aoss_tpdm4_out>; 3716 }; 3717 }; 3718 }; 3719 }; 3720 3721 tpdm@4b09000 { 3722 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3723 reg = <0x0 0x4b09000 0x0 0x1000>; 3724 3725 clocks = <&aoss_qmp>; 3726 clock-names = "apb_pclk"; 3727 3728 qcom,cmb-element-bits = <64>; 3729 qcom,cmb-msrs-num = <32>; 3730 3731 out-ports { 3732 port { 3733 aoss_tpdm0_out: endpoint { 3734 remote-endpoint = 3735 <&aoss_tpda_in0>; 3736 }; 3737 }; 3738 }; 3739 }; 3740 3741 tpdm@4b0a000 { 3742 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3743 reg = <0x0 0x4b0a000 0x0 0x1000>; 3744 3745 clocks = <&aoss_qmp>; 3746 clock-names = "apb_pclk"; 3747 3748 qcom,cmb-element-bits = <64>; 3749 qcom,cmb-msrs-num = <32>; 3750 3751 out-ports { 3752 port { 3753 aoss_tpdm1_out: endpoint { 3754 remote-endpoint = 3755 <&aoss_tpda_in1>; 3756 }; 3757 }; 3758 }; 3759 }; 3760 3761 tpdm@4b0b000 { 3762 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3763 reg = <0x0 0x4b0b000 0x0 0x1000>; 3764 3765 clocks = <&aoss_qmp>; 3766 clock-names = "apb_pclk"; 3767 3768 qcom,cmb-element-bits = <64>; 3769 qcom,cmb-msrs-num = <32>; 3770 3771 out-ports { 3772 port { 3773 aoss_tpdm2_out: endpoint { 3774 remote-endpoint = 3775 <&aoss_tpda_in2>; 3776 }; 3777 }; 3778 }; 3779 }; 3780 3781 tpdm@4b0c000 { 3782 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3783 reg = <0x0 0x4b0c000 0x0 0x1000>; 3784 3785 clocks = <&aoss_qmp>; 3786 clock-names = "apb_pclk"; 3787 3788 qcom,cmb-element-bits = <64>; 3789 qcom,cmb-msrs-num = <32>; 3790 3791 out-ports { 3792 port { 3793 aoss_tpdm3_out: endpoint { 3794 remote-endpoint = 3795 <&aoss_tpda_in3>; 3796 }; 3797 }; 3798 }; 3799 }; 3800 3801 tpdm@4b0d000 { 3802 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3803 reg = <0x0 0x4b0d000 0x0 0x1000>; 3804 3805 clocks = <&aoss_qmp>; 3806 clock-names = "apb_pclk"; 3807 3808 qcom,dsb-element-bits = <32>; 3809 qcom,dsb-msrs-num = <32>; 3810 3811 out-ports { 3812 port { 3813 aoss_tpdm4_out: endpoint { 3814 remote-endpoint = 3815 <&aoss_tpda_in4>; 3816 }; 3817 }; 3818 }; 3819 }; 3820 3821 aoss_cti: cti@4b13000 { 3822 compatible = "arm,coresight-cti", "arm,primecell"; 3823 reg = <0x0 0x4b13000 0x0 0x1000>; 3824 3825 clocks = <&aoss_qmp>; 3826 clock-names = "apb_pclk"; 3827 }; 3828 3829 funnel@4b83000 { 3830 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3831 reg = <0x0 0x4b83000 0x0 0x1000>; 3832 3833 clocks = <&aoss_qmp>; 3834 clock-names = "apb_pclk"; 3835 3836 in-ports { 3837 #address-cells = <1>; 3838 #size-cells = <0>; 3839 3840 port@1 { 3841 reg = <1>; 3842 3843 turing0_funnel_in1: endpoint { 3844 remote-endpoint = <&turing_llm_tpdm_out>; 3845 }; 3846 }; 3847 }; 3848 3849 out-ports { 3850 port { 3851 turing0_funnel_out: endpoint { 3852 remote-endpoint = <&dlct0_tpda_in16>; 3853 }; 3854 }; 3855 }; 3856 }; 3857 3858 etm@6040000 { 3859 compatible = "arm,primecell"; 3860 reg = <0x0 0x6040000 0x0 0x1000>; 3861 cpu = <&cpu0>; 3862 3863 clocks = <&aoss_qmp>; 3864 clock-names = "apb_pclk"; 3865 arm,coresight-loses-context-with-cpu; 3866 qcom,skip-power-up; 3867 3868 out-ports { 3869 port { 3870 etm0_out: endpoint { 3871 remote-endpoint = 3872 <&apss_funnel0_in0>; 3873 }; 3874 }; 3875 }; 3876 }; 3877 3878 etm@6140000 { 3879 compatible = "arm,primecell"; 3880 reg = <0x0 0x6140000 0x0 0x1000>; 3881 cpu = <&cpu1>; 3882 3883 clocks = <&aoss_qmp>; 3884 clock-names = "apb_pclk"; 3885 arm,coresight-loses-context-with-cpu; 3886 qcom,skip-power-up; 3887 3888 out-ports { 3889 port { 3890 etm1_out: endpoint { 3891 remote-endpoint = 3892 <&apss_funnel0_in1>; 3893 }; 3894 }; 3895 }; 3896 }; 3897 3898 etm@6240000 { 3899 compatible = "arm,primecell"; 3900 reg = <0x0 0x6240000 0x0 0x1000>; 3901 cpu = <&cpu2>; 3902 3903 clocks = <&aoss_qmp>; 3904 clock-names = "apb_pclk"; 3905 arm,coresight-loses-context-with-cpu; 3906 qcom,skip-power-up; 3907 3908 out-ports { 3909 port { 3910 etm2_out: endpoint { 3911 remote-endpoint = 3912 <&apss_funnel0_in2>; 3913 }; 3914 }; 3915 }; 3916 }; 3917 3918 etm@6340000 { 3919 compatible = "arm,primecell"; 3920 reg = <0x0 0x6340000 0x0 0x1000>; 3921 cpu = <&cpu3>; 3922 3923 clocks = <&aoss_qmp>; 3924 clock-names = "apb_pclk"; 3925 arm,coresight-loses-context-with-cpu; 3926 qcom,skip-power-up; 3927 3928 out-ports { 3929 port { 3930 etm3_out: endpoint { 3931 remote-endpoint = 3932 <&apss_funnel0_in3>; 3933 }; 3934 }; 3935 }; 3936 }; 3937 3938 etm@6440000 { 3939 compatible = "arm,primecell"; 3940 reg = <0x0 0x6440000 0x0 0x1000>; 3941 cpu = <&cpu4>; 3942 3943 clocks = <&aoss_qmp>; 3944 clock-names = "apb_pclk"; 3945 arm,coresight-loses-context-with-cpu; 3946 qcom,skip-power-up; 3947 3948 out-ports { 3949 port { 3950 etm4_out: endpoint { 3951 remote-endpoint = 3952 <&apss_funnel0_in4>; 3953 }; 3954 }; 3955 }; 3956 }; 3957 3958 etm@6540000 { 3959 compatible = "arm,primecell"; 3960 reg = <0x0 0x6540000 0x0 0x1000>; 3961 cpu = <&cpu5>; 3962 3963 clocks = <&aoss_qmp>; 3964 clock-names = "apb_pclk"; 3965 arm,coresight-loses-context-with-cpu; 3966 qcom,skip-power-up; 3967 3968 out-ports { 3969 port { 3970 etm5_out: endpoint { 3971 remote-endpoint = 3972 <&apss_funnel0_in5>; 3973 }; 3974 }; 3975 }; 3976 }; 3977 3978 etm@6640000 { 3979 compatible = "arm,primecell"; 3980 reg = <0x0 0x6640000 0x0 0x1000>; 3981 cpu = <&cpu6>; 3982 3983 clocks = <&aoss_qmp>; 3984 clock-names = "apb_pclk"; 3985 arm,coresight-loses-context-with-cpu; 3986 qcom,skip-power-up; 3987 3988 out-ports { 3989 port { 3990 etm6_out: endpoint { 3991 remote-endpoint = 3992 <&apss_funnel0_in6>; 3993 }; 3994 }; 3995 }; 3996 }; 3997 3998 etm@6740000 { 3999 compatible = "arm,primecell"; 4000 reg = <0x0 0x6740000 0x0 0x1000>; 4001 cpu = <&cpu7>; 4002 4003 clocks = <&aoss_qmp>; 4004 clock-names = "apb_pclk"; 4005 arm,coresight-loses-context-with-cpu; 4006 qcom,skip-power-up; 4007 4008 out-ports { 4009 port { 4010 etm7_out: endpoint { 4011 remote-endpoint = 4012 <&apss_funnel0_in7>; 4013 }; 4014 }; 4015 }; 4016 }; 4017 4018 funnel@6800000 { 4019 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4020 reg = <0x0 0x6800000 0x0 0x1000>; 4021 4022 clocks = <&aoss_qmp>; 4023 clock-names = "apb_pclk"; 4024 4025 out-ports { 4026 port { 4027 apss_funnel0_out: endpoint { 4028 remote-endpoint = 4029 <&apss_funnel1_in0>; 4030 }; 4031 }; 4032 }; 4033 4034 in-ports { 4035 #address-cells = <1>; 4036 #size-cells = <0>; 4037 4038 port@0 { 4039 reg = <0>; 4040 apss_funnel0_in0: endpoint { 4041 remote-endpoint = 4042 <&etm0_out>; 4043 }; 4044 }; 4045 4046 port@1 { 4047 reg = <1>; 4048 apss_funnel0_in1: endpoint { 4049 remote-endpoint = 4050 <&etm1_out>; 4051 }; 4052 }; 4053 4054 port@2 { 4055 reg = <2>; 4056 apss_funnel0_in2: endpoint { 4057 remote-endpoint = 4058 <&etm2_out>; 4059 }; 4060 }; 4061 4062 port@3 { 4063 reg = <3>; 4064 apss_funnel0_in3: endpoint { 4065 remote-endpoint = 4066 <&etm3_out>; 4067 }; 4068 }; 4069 4070 port@4 { 4071 reg = <4>; 4072 apss_funnel0_in4: endpoint { 4073 remote-endpoint = 4074 <&etm4_out>; 4075 }; 4076 }; 4077 4078 port@5 { 4079 reg = <5>; 4080 apss_funnel0_in5: endpoint { 4081 remote-endpoint = 4082 <&etm5_out>; 4083 }; 4084 }; 4085 4086 port@6 { 4087 reg = <6>; 4088 apss_funnel0_in6: endpoint { 4089 remote-endpoint = 4090 <&etm6_out>; 4091 }; 4092 }; 4093 4094 port@7 { 4095 reg = <7>; 4096 apss_funnel0_in7: endpoint { 4097 remote-endpoint = 4098 <&etm7_out>; 4099 }; 4100 }; 4101 }; 4102 }; 4103 4104 funnel@6810000 { 4105 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4106 reg = <0x0 0x6810000 0x0 0x1000>; 4107 4108 clocks = <&aoss_qmp>; 4109 clock-names = "apb_pclk"; 4110 4111 out-ports { 4112 port { 4113 apss_funnel1_out: endpoint { 4114 remote-endpoint = 4115 <&funnel1_in4>; 4116 }; 4117 }; 4118 }; 4119 4120 in-ports { 4121 #address-cells = <1>; 4122 #size-cells = <0>; 4123 4124 port@0 { 4125 reg = <0>; 4126 apss_funnel1_in0: endpoint { 4127 remote-endpoint = 4128 <&apss_funnel0_out>; 4129 }; 4130 }; 4131 4132 port@3 { 4133 reg = <3>; 4134 apss_funnel1_in3: endpoint { 4135 remote-endpoint = 4136 <&apss_tpda_out>; 4137 }; 4138 }; 4139 }; 4140 }; 4141 4142 tpdm@6860000 { 4143 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4144 reg = <0x0 0x6860000 0x0 0x1000>; 4145 4146 clocks = <&aoss_qmp>; 4147 clock-names = "apb_pclk"; 4148 4149 qcom,cmb-element-bits = <64>; 4150 qcom,cmb-msrs-num = <32>; 4151 4152 out-ports { 4153 port { 4154 apss_tpdm3_out: endpoint { 4155 remote-endpoint = 4156 <&apss_tpda_in3>; 4157 }; 4158 }; 4159 }; 4160 }; 4161 4162 tpdm@6861000 { 4163 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4164 reg = <0x0 0x6861000 0x0 0x1000>; 4165 4166 clocks = <&aoss_qmp>; 4167 clock-names = "apb_pclk"; 4168 4169 qcom,dsb-element-bits = <32>; 4170 qcom,dsb-msrs-num = <32>; 4171 4172 out-ports { 4173 port { 4174 apss_tpdm4_out: endpoint { 4175 remote-endpoint = 4176 <&apss_tpda_in4>; 4177 }; 4178 }; 4179 }; 4180 }; 4181 4182 tpda@6863000 { 4183 compatible = "qcom,coresight-tpda", "arm,primecell"; 4184 reg = <0x0 0x6863000 0x0 0x1000>; 4185 4186 clocks = <&aoss_qmp>; 4187 clock-names = "apb_pclk"; 4188 4189 out-ports { 4190 port { 4191 apss_tpda_out: endpoint { 4192 remote-endpoint = 4193 <&apss_funnel1_in3>; 4194 }; 4195 }; 4196 }; 4197 4198 in-ports { 4199 #address-cells = <1>; 4200 #size-cells = <0>; 4201 4202 port@0 { 4203 reg = <0>; 4204 apss_tpda_in0: endpoint { 4205 remote-endpoint = 4206 <&apss_tpdm0_out>; 4207 }; 4208 }; 4209 4210 port@1 { 4211 reg = <1>; 4212 apss_tpda_in1: endpoint { 4213 remote-endpoint = 4214 <&apss_tpdm1_out>; 4215 }; 4216 }; 4217 4218 port@2 { 4219 reg = <2>; 4220 apss_tpda_in2: endpoint { 4221 remote-endpoint = 4222 <&apss_tpdm2_out>; 4223 }; 4224 }; 4225 4226 port@3 { 4227 reg = <3>; 4228 apss_tpda_in3: endpoint { 4229 remote-endpoint = 4230 <&apss_tpdm3_out>; 4231 }; 4232 }; 4233 4234 port@4 { 4235 reg = <4>; 4236 apss_tpda_in4: endpoint { 4237 remote-endpoint = 4238 <&apss_tpdm4_out>; 4239 }; 4240 }; 4241 }; 4242 }; 4243 4244 tpdm@68a0000 { 4245 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4246 reg = <0x0 0x68a0000 0x0 0x1000>; 4247 4248 clocks = <&aoss_qmp>; 4249 clock-names = "apb_pclk"; 4250 4251 qcom,cmb-element-bits = <32>; 4252 qcom,cmb-msrs-num = <32>; 4253 4254 out-ports { 4255 port { 4256 apss_tpdm0_out: endpoint { 4257 remote-endpoint = 4258 <&apss_tpda_in0>; 4259 }; 4260 }; 4261 }; 4262 }; 4263 4264 tpdm@68b0000 { 4265 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4266 reg = <0x0 0x68b0000 0x0 0x1000>; 4267 4268 clocks = <&aoss_qmp>; 4269 clock-names = "apb_pclk"; 4270 4271 qcom,cmb-element-bits = <32>; 4272 qcom,cmb-msrs-num = <32>; 4273 4274 out-ports { 4275 port { 4276 apss_tpdm1_out: endpoint { 4277 remote-endpoint = 4278 <&apss_tpda_in1>; 4279 }; 4280 }; 4281 }; 4282 }; 4283 4284 tpdm@68c0000 { 4285 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4286 reg = <0x0 0x68c0000 0x0 0x1000>; 4287 4288 clocks = <&aoss_qmp>; 4289 clock-names = "apb_pclk"; 4290 4291 qcom,dsb-element-bits = <32>; 4292 qcom,dsb-msrs-num = <32>; 4293 4294 out-ports { 4295 port { 4296 apss_tpdm2_out: endpoint { 4297 remote-endpoint = 4298 <&apss_tpda_in2>; 4299 }; 4300 }; 4301 }; 4302 }; 4303 4304 sdhc: mmc@87c4000 { 4305 compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; 4306 reg = <0x0 0x087c4000 0x0 0x1000>; 4307 4308 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 4309 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; 4310 interrupt-names = "hc_irq", 4311 "pwr_irq"; 4312 4313 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 4314 <&gcc GCC_SDCC1_APPS_CLK>; 4315 clock-names = "iface", 4316 "core"; 4317 4318 interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS 4319 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4320 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4321 &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4322 interconnect-names = "sdhc-ddr", 4323 "cpu-sdhc"; 4324 4325 iommus = <&apps_smmu 0x0 0x0>; 4326 dma-coherent; 4327 4328 operating-points-v2 = <&sdhc_opp_table>; 4329 power-domains = <&rpmhpd SA8775P_CX>; 4330 resets = <&gcc GCC_SDCC1_BCR>; 4331 4332 qcom,dll-config = <0x0007642c>; 4333 qcom,ddr-config = <0x80040868>; 4334 4335 status = "disabled"; 4336 4337 sdhc_opp_table: opp-table { 4338 compatible = "operating-points-v2"; 4339 4340 opp-100000000 { 4341 opp-hz = /bits/ 64 <100000000>; 4342 required-opps = <&rpmhpd_opp_low_svs>; 4343 opp-peak-kBps = <1800000 400000>; 4344 opp-avg-kBps = <100000 0>; 4345 }; 4346 4347 opp-384000000 { 4348 opp-hz = /bits/ 64 <384000000>; 4349 required-opps = <&rpmhpd_opp_nom>; 4350 opp-peak-kBps = <5400000 1600000>; 4351 opp-avg-kBps = <390000 0>; 4352 }; 4353 }; 4354 }; 4355 4356 usb_0_hsphy: phy@88e4000 { 4357 compatible = "qcom,sa8775p-usb-hs-phy", 4358 "qcom,usb-snps-hs-5nm-phy"; 4359 reg = <0 0x088e4000 0 0x120>; 4360 clocks = <&rpmhcc RPMH_CXO_CLK>; 4361 clock-names = "ref"; 4362 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 4363 4364 #phy-cells = <0>; 4365 4366 status = "disabled"; 4367 }; 4368 4369 usb_1_hsphy: phy@88e6000 { 4370 compatible = "qcom,sa8775p-usb-hs-phy", 4371 "qcom,usb-snps-hs-5nm-phy"; 4372 reg = <0 0x088e6000 0 0x120>; 4373 clocks = <&gcc GCC_USB_CLKREF_EN>; 4374 clock-names = "ref"; 4375 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 4376 4377 #phy-cells = <0>; 4378 4379 status = "disabled"; 4380 }; 4381 4382 usb_2_hsphy: phy@88e7000 { 4383 compatible = "qcom,sa8775p-usb-hs-phy", 4384 "qcom,usb-snps-hs-5nm-phy"; 4385 reg = <0 0x088e7000 0 0x120>; 4386 clocks = <&gcc GCC_USB_CLKREF_EN>; 4387 clock-names = "ref"; 4388 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 4389 4390 #phy-cells = <0>; 4391 4392 status = "disabled"; 4393 }; 4394 4395 usb_0_qmpphy: phy@88e8000 { 4396 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 4397 reg = <0 0x088e8000 0 0x2000>; 4398 4399 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4400 <&gcc GCC_USB_CLKREF_EN>, 4401 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4402 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4403 clock-names = "aux", "ref", "com_aux", "pipe"; 4404 4405 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4406 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 4407 reset-names = "phy", "phy_phy"; 4408 4409 power-domains = <&gcc USB30_PRIM_GDSC>; 4410 4411 #clock-cells = <0>; 4412 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 4413 4414 #phy-cells = <0>; 4415 4416 status = "disabled"; 4417 }; 4418 4419 usb_1_qmpphy: phy@88ea000 { 4420 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 4421 reg = <0 0x088ea000 0 0x2000>; 4422 4423 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4424 <&gcc GCC_USB_CLKREF_EN>, 4425 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 4426 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4427 clock-names = "aux", "ref", "com_aux", "pipe"; 4428 4429 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 4430 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 4431 reset-names = "phy", "phy_phy"; 4432 4433 power-domains = <&gcc USB30_SEC_GDSC>; 4434 4435 #clock-cells = <0>; 4436 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 4437 4438 #phy-cells = <0>; 4439 4440 status = "disabled"; 4441 }; 4442 4443 refgen: regulator@891c000 { 4444 compatible = "qcom,sa8775p-refgen-regulator", 4445 "qcom,sm8250-refgen-regulator"; 4446 reg = <0x0 0x0891c000 0x0 0x84>; 4447 }; 4448 4449 dc_noc: interconnect@90e0000 { 4450 compatible = "qcom,sa8775p-dc-noc"; 4451 reg = <0x0 0x090e0000 0x0 0x5080>; 4452 #interconnect-cells = <2>; 4453 qcom,bcm-voters = <&apps_bcm_voter>; 4454 }; 4455 4456 gem_noc: interconnect@9100000 { 4457 compatible = "qcom,sa8775p-gem-noc"; 4458 reg = <0x0 0x09100000 0x0 0xf6080>; 4459 #interconnect-cells = <2>; 4460 qcom,bcm-voters = <&apps_bcm_voter>; 4461 }; 4462 4463 usb_0: usb@a600000 { 4464 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4465 reg = <0 0x0a600000 0 0xfc100>; 4466 4467 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4468 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4469 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4470 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4471 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4472 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4473 4474 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4475 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4476 assigned-clock-rates = <19200000>, <200000000>; 4477 4478 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 4479 <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 4480 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4481 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4482 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4483 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 4484 interrupt-names = "dwc_usb3", 4485 "pwr_event", 4486 "hs_phy_irq", 4487 "dp_hs_phy_irq", 4488 "dm_hs_phy_irq", 4489 "ss_phy_irq"; 4490 4491 power-domains = <&gcc USB30_PRIM_GDSC>; 4492 required-opps = <&rpmhpd_opp_nom>; 4493 4494 resets = <&gcc GCC_USB30_PRIM_BCR>; 4495 4496 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4497 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4498 interconnect-names = "usb-ddr", "apps-usb"; 4499 4500 wakeup-source; 4501 4502 iommus = <&apps_smmu 0x080 0x0>; 4503 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 4504 phy-names = "usb2-phy", "usb3-phy"; 4505 snps,dis-u1-entry-quirk; 4506 snps,dis-u2-entry-quirk; 4507 4508 usb-role-switch; 4509 status = "disabled"; 4510 4511 ports { 4512 #address-cells = <1>; 4513 #size-cells = <0>; 4514 4515 port@0 { 4516 reg = <0>; 4517 4518 usb_0_dwc3_hs: endpoint { 4519 }; 4520 }; 4521 4522 port@1 { 4523 reg = <1>; 4524 4525 usb_0_dwc3_ss: endpoint { 4526 }; 4527 }; 4528 }; 4529 }; 4530 4531 usb_1: usb@a800000 { 4532 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4533 reg = <0 0x0a800000 0 0xfc100>; 4534 4535 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4536 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4537 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4538 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4539 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4540 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4541 4542 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4543 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4544 assigned-clock-rates = <19200000>, <200000000>; 4545 4546 interrupts-extended = <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 4547 <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 4548 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 4549 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 4550 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 4551 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 4552 interrupt-names = "dwc_usb3", 4553 "pwr_event", 4554 "hs_phy_irq", 4555 "dp_hs_phy_irq", 4556 "dm_hs_phy_irq", 4557 "ss_phy_irq"; 4558 4559 power-domains = <&gcc USB30_SEC_GDSC>; 4560 required-opps = <&rpmhpd_opp_nom>; 4561 4562 resets = <&gcc GCC_USB30_SEC_BCR>; 4563 4564 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 4565 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4566 interconnect-names = "usb-ddr", "apps-usb"; 4567 4568 wakeup-source; 4569 4570 iommus = <&apps_smmu 0x0a0 0x0>; 4571 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 4572 phy-names = "usb2-phy", "usb3-phy"; 4573 snps,dis-u1-entry-quirk; 4574 snps,dis-u2-entry-quirk; 4575 4576 status = "disabled"; 4577 }; 4578 4579 usb_2: usb@a400000 { 4580 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4581 reg = <0 0x0a400000 0 0xfc100>; 4582 4583 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4584 <&gcc GCC_USB20_MASTER_CLK>, 4585 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4586 <&gcc GCC_USB20_SLEEP_CLK>, 4587 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 4588 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4589 4590 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4591 <&gcc GCC_USB20_MASTER_CLK>; 4592 assigned-clock-rates = <19200000>, <200000000>; 4593 4594 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 4595 <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 4596 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 4597 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 4598 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 4599 interrupt-names = "dwc_usb3", 4600 "pwr_event", 4601 "hs_phy_irq", 4602 "dp_hs_phy_irq", 4603 "dm_hs_phy_irq"; 4604 4605 power-domains = <&gcc USB20_PRIM_GDSC>; 4606 required-opps = <&rpmhpd_opp_nom>; 4607 4608 resets = <&gcc GCC_USB20_PRIM_BCR>; 4609 4610 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 4611 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 4612 interconnect-names = "usb-ddr", "apps-usb"; 4613 4614 qcom,select-utmi-as-pipe-clk; 4615 wakeup-source; 4616 4617 iommus = <&apps_smmu 0x020 0x0>; 4618 phys = <&usb_2_hsphy>; 4619 phy-names = "usb2-phy"; 4620 snps,dis-u1-entry-quirk; 4621 snps,dis-u2-entry-quirk; 4622 4623 usb-role-switch; 4624 4625 status = "disabled"; 4626 4627 port { 4628 usb_2_dwc3_hs: endpoint { 4629 }; 4630 }; 4631 }; 4632 4633 tcsr_mutex: hwlock@1f40000 { 4634 compatible = "qcom,tcsr-mutex"; 4635 reg = <0x0 0x01f40000 0x0 0x20000>; 4636 #hwlock-cells = <1>; 4637 }; 4638 4639 tcsr: syscon@1fc0000 { 4640 compatible = "qcom,sa8775p-tcsr", "syscon"; 4641 reg = <0x0 0x1fc0000 0x0 0x30000>; 4642 }; 4643 4644 gpu: gpu@3d00000 { 4645 compatible = "qcom,adreno-663.0", "qcom,adreno"; 4646 reg = <0x0 0x03d00000 0x0 0x40000>, 4647 <0x0 0x03d9e000 0x0 0x1000>, 4648 <0x0 0x03d61000 0x0 0x800>; 4649 reg-names = "kgsl_3d0_reg_memory", 4650 "cx_mem", 4651 "cx_dbgc"; 4652 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4653 iommus = <&adreno_smmu 0 0xc00>, 4654 <&adreno_smmu 1 0xc00>; 4655 operating-points-v2 = <&gpu_opp_table>; 4656 qcom,gmu = <&gmu>; 4657 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4658 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4659 interconnect-names = "gfx-mem"; 4660 #cooling-cells = <2>; 4661 4662 nvmem-cells = <&gpu_speed_bin>; 4663 nvmem-cell-names = "speed_bin"; 4664 4665 status = "disabled"; 4666 4667 gpu_zap_shader: zap-shader { 4668 memory-region = <&pil_gpu_mem>; 4669 }; 4670 4671 gpu_opp_table: opp-table { 4672 compatible = "operating-points-v2"; 4673 4674 opp-405000000 { 4675 opp-hz = /bits/ 64 <405000000>; 4676 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4677 opp-peak-kBps = <5285156>; 4678 opp-supported-hw = <0x3>; 4679 }; 4680 4681 opp-530000000 { 4682 opp-hz = /bits/ 64 <530000000>; 4683 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4684 opp-peak-kBps = <12484375>; 4685 opp-supported-hw = <0x2>; 4686 }; 4687 4688 opp-676000000 { 4689 opp-hz = /bits/ 64 <676000000>; 4690 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4691 opp-peak-kBps = <8171875>; 4692 opp-supported-hw = <0x1>; 4693 }; 4694 4695 opp-778000000 { 4696 opp-hz = /bits/ 64 <778000000>; 4697 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4698 opp-peak-kBps = <10687500>; 4699 opp-supported-hw = <0x1>; 4700 }; 4701 4702 opp-800000000 { 4703 opp-hz = /bits/ 64 <800000000>; 4704 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4705 opp-peak-kBps = <12484375>; 4706 opp-supported-hw = <0x1>; 4707 }; 4708 }; 4709 }; 4710 4711 gmu: gmu@3d6a000 { 4712 compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; 4713 reg = <0x0 0x03d6a000 0x0 0x34000>, 4714 <0x0 0x03de0000 0x0 0x10000>, 4715 <0x0 0x0b290000 0x0 0x10000>; 4716 reg-names = "gmu", "rscc", "gmu_pdc"; 4717 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4718 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4719 interrupt-names = "hfi", "gmu"; 4720 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4721 <&gpucc GPU_CC_CXO_CLK>, 4722 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4723 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4724 <&gpucc GPU_CC_AHB_CLK>, 4725 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4726 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 4727 clock-names = "gmu", 4728 "cxo", 4729 "axi", 4730 "memnoc", 4731 "ahb", 4732 "hub", 4733 "smmu_vote"; 4734 power-domains = <&gpucc GPU_CC_CX_GDSC>, 4735 <&gpucc GPU_CC_GX_GDSC>; 4736 power-domain-names = "cx", 4737 "gx"; 4738 iommus = <&adreno_smmu 5 0xc00>; 4739 operating-points-v2 = <&gmu_opp_table>; 4740 4741 gmu_opp_table: opp-table { 4742 compatible = "operating-points-v2"; 4743 4744 opp-500000000 { 4745 opp-hz = /bits/ 64 <500000000>; 4746 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4747 }; 4748 }; 4749 }; 4750 4751 gpucc: clock-controller@3d90000 { 4752 compatible = "qcom,sa8775p-gpucc"; 4753 reg = <0x0 0x03d90000 0x0 0xa000>; 4754 clocks = <&rpmhcc RPMH_CXO_CLK>, 4755 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4756 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4757 clock-names = "bi_tcxo", 4758 "gcc_gpu_gpll0_clk_src", 4759 "gcc_gpu_gpll0_div_clk_src"; 4760 #clock-cells = <1>; 4761 #reset-cells = <1>; 4762 #power-domain-cells = <1>; 4763 }; 4764 4765 adreno_smmu: iommu@3da0000 { 4766 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 4767 "qcom,smmu-500", "arm,mmu-500"; 4768 reg = <0x0 0x03da0000 0x0 0x20000>; 4769 #iommu-cells = <2>; 4770 #global-interrupts = <2>; 4771 dma-coherent; 4772 power-domains = <&gpucc GPU_CC_CX_GDSC>; 4773 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4774 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4775 <&gpucc GPU_CC_AHB_CLK>, 4776 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4777 <&gpucc GPU_CC_CX_GMU_CLK>, 4778 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4779 <&gpucc GPU_CC_HUB_AON_CLK>; 4780 clock-names = "gcc_gpu_memnoc_gfx_clk", 4781 "gcc_gpu_snoc_dvm_gfx_clk", 4782 "gpu_cc_ahb_clk", 4783 "gpu_cc_hlos1_vote_gpu_smmu_clk", 4784 "gpu_cc_cx_gmu_clk", 4785 "gpu_cc_hub_cx_int_clk", 4786 "gpu_cc_hub_aon_clk"; 4787 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 4788 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4789 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4790 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4791 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4792 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4793 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4794 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4795 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4796 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4797 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4798 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 4799 }; 4800 4801 serdes0: phy@8901000 { 4802 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4803 reg = <0x0 0x08901000 0x0 0xe10>; 4804 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4805 clock-names = "sgmi_ref"; 4806 #phy-cells = <0>; 4807 status = "disabled"; 4808 }; 4809 4810 serdes1: phy@8902000 { 4811 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4812 reg = <0x0 0x08902000 0x0 0xe10>; 4813 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4814 clock-names = "sgmi_ref"; 4815 #phy-cells = <0>; 4816 status = "disabled"; 4817 }; 4818 4819 pmu@9091000 { 4820 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4821 reg = <0x0 0x9091000 0x0 0x1000>; 4822 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 4823 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 4824 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4825 4826 operating-points-v2 = <&llcc_bwmon_opp_table>; 4827 4828 llcc_bwmon_opp_table: opp-table { 4829 compatible = "operating-points-v2"; 4830 4831 opp-0 { 4832 opp-peak-kBps = <762000>; 4833 }; 4834 4835 opp-1 { 4836 opp-peak-kBps = <1720000>; 4837 }; 4838 4839 opp-2 { 4840 opp-peak-kBps = <2086000>; 4841 }; 4842 4843 opp-3 { 4844 opp-peak-kBps = <2601000>; 4845 }; 4846 4847 opp-4 { 4848 opp-peak-kBps = <2929000>; 4849 }; 4850 4851 opp-5 { 4852 opp-peak-kBps = <5931000>; 4853 }; 4854 4855 opp-6 { 4856 opp-peak-kBps = <6515000>; 4857 }; 4858 4859 opp-7 { 4860 opp-peak-kBps = <7984000>; 4861 }; 4862 4863 opp-8 { 4864 opp-peak-kBps = <10437000>; 4865 }; 4866 4867 opp-9 { 4868 opp-peak-kBps = <12195000>; 4869 }; 4870 }; 4871 }; 4872 4873 pmu@90b5400 { 4874 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4875 reg = <0x0 0x90b5400 0x0 0x600>; 4876 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4877 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4878 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4879 4880 operating-points-v2 = <&cpu_bwmon_opp_table>; 4881 4882 cpu_bwmon_opp_table: opp-table { 4883 compatible = "operating-points-v2"; 4884 4885 opp-0 { 4886 opp-peak-kBps = <9155000>; 4887 }; 4888 4889 opp-1 { 4890 opp-peak-kBps = <12298000>; 4891 }; 4892 4893 opp-2 { 4894 opp-peak-kBps = <14236000>; 4895 }; 4896 4897 opp-3 { 4898 opp-peak-kBps = <16265000>; 4899 }; 4900 }; 4901 4902 }; 4903 4904 pmu@90b6400 { 4905 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4906 reg = <0x0 0x90b6400 0x0 0x600>; 4907 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4908 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4909 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4910 4911 operating-points-v2 = <&cpu_bwmon_opp_table>; 4912 }; 4913 4914 llcc: system-cache-controller@9200000 { 4915 compatible = "qcom,sa8775p-llcc"; 4916 reg = <0x0 0x09200000 0x0 0x80000>, 4917 <0x0 0x09300000 0x0 0x80000>, 4918 <0x0 0x09400000 0x0 0x80000>, 4919 <0x0 0x09500000 0x0 0x80000>, 4920 <0x0 0x09600000 0x0 0x80000>, 4921 <0x0 0x09700000 0x0 0x80000>, 4922 <0x0 0x09a00000 0x0 0x80000>; 4923 reg-names = "llcc0_base", 4924 "llcc1_base", 4925 "llcc2_base", 4926 "llcc3_base", 4927 "llcc4_base", 4928 "llcc5_base", 4929 "llcc_broadcast_base"; 4930 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 4931 }; 4932 4933 iris: video-codec@aa00000 { 4934 compatible = "qcom,sa8775p-iris", "qcom,sm8550-iris"; 4935 4936 reg = <0x0 0x0aa00000 0x0 0xf0000>; 4937 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4938 4939 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 4940 <&videocc VIDEO_CC_MVS0_GDSC>, 4941 <&rpmhpd SA8775P_MX>, 4942 <&rpmhpd SA8775P_MMCX>; 4943 power-domain-names = "venus", 4944 "vcodec0", 4945 "mxc", 4946 "mmcx"; 4947 operating-points-v2 = <&iris_opp_table>; 4948 4949 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4950 <&videocc VIDEO_CC_MVS0C_CLK>, 4951 <&videocc VIDEO_CC_MVS0_CLK>; 4952 clock-names = "iface", 4953 "core", 4954 "vcodec0_core"; 4955 4956 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4957 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4958 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4959 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4960 interconnect-names = "cpu-cfg", 4961 "video-mem"; 4962 4963 memory-region = <&pil_video_mem>; 4964 4965 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 4966 reset-names = "bus"; 4967 4968 iommus = <&apps_smmu 0x0880 0x0400>, 4969 <&apps_smmu 0x0887 0x0400>; 4970 dma-coherent; 4971 4972 status = "disabled"; 4973 4974 iris_opp_table: opp-table { 4975 compatible = "operating-points-v2"; 4976 4977 opp-366000000 { 4978 opp-hz = /bits/ 64 <366000000>; 4979 required-opps = <&rpmhpd_opp_svs_l1>, 4980 <&rpmhpd_opp_svs_l1>; 4981 }; 4982 4983 opp-444000000 { 4984 opp-hz = /bits/ 64 <444000000>; 4985 required-opps = <&rpmhpd_opp_svs_l1>, 4986 <&rpmhpd_opp_nom>; 4987 }; 4988 4989 opp-533000000 { 4990 opp-hz = /bits/ 64 <533000000>; 4991 required-opps = <&rpmhpd_opp_nom>, 4992 <&rpmhpd_opp_turbo>; 4993 }; 4994 4995 opp-560000000 { 4996 opp-hz = /bits/ 64 <560000000>; 4997 required-opps = <&rpmhpd_opp_nom>, 4998 <&rpmhpd_opp_turbo_l1>; 4999 }; 5000 }; 5001 }; 5002 5003 videocc: clock-controller@abf0000 { 5004 compatible = "qcom,sa8775p-videocc"; 5005 reg = <0x0 0x0abf0000 0x0 0x10000>; 5006 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 5007 <&rpmhcc RPMH_CXO_CLK>, 5008 <&rpmhcc RPMH_CXO_CLK_A>, 5009 <&sleep_clk>; 5010 power-domains = <&rpmhpd SA8775P_MMCX>; 5011 #clock-cells = <1>; 5012 #reset-cells = <1>; 5013 #power-domain-cells = <1>; 5014 }; 5015 5016 cci0: cci@ac13000 { 5017 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 5018 reg = <0x0 0x0ac13000 0x0 0x1000>; 5019 5020 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 5021 5022 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5023 5024 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5025 <&camcc CAM_CC_CPAS_AHB_CLK>, 5026 <&camcc CAM_CC_CCI_0_CLK>; 5027 clock-names = "camnoc_axi", 5028 "cpas_ahb", 5029 "cci"; 5030 5031 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 5032 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 5033 pinctrl-names = "default", "sleep"; 5034 5035 #address-cells = <1>; 5036 #size-cells = <0>; 5037 5038 status = "disabled"; 5039 5040 cci0_i2c0: i2c-bus@0 { 5041 reg = <0>; 5042 clock-frequency = <1000000>; 5043 #address-cells = <1>; 5044 #size-cells = <0>; 5045 }; 5046 5047 cci0_i2c1: i2c-bus@1 { 5048 reg = <1>; 5049 clock-frequency = <1000000>; 5050 #address-cells = <1>; 5051 #size-cells = <0>; 5052 }; 5053 }; 5054 5055 cci1: cci@ac14000 { 5056 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 5057 reg = <0x0 0x0ac14000 0x0 0x1000>; 5058 5059 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 5060 5061 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5062 5063 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5064 <&camcc CAM_CC_CPAS_AHB_CLK>, 5065 <&camcc CAM_CC_CCI_1_CLK>; 5066 clock-names = "camnoc_axi", 5067 "cpas_ahb", 5068 "cci"; 5069 5070 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 5071 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 5072 pinctrl-names = "default", "sleep"; 5073 5074 #address-cells = <1>; 5075 #size-cells = <0>; 5076 5077 status = "disabled"; 5078 5079 cci1_i2c0: i2c-bus@0 { 5080 reg = <0>; 5081 clock-frequency = <1000000>; 5082 #address-cells = <1>; 5083 #size-cells = <0>; 5084 }; 5085 5086 cci1_i2c1: i2c-bus@1 { 5087 reg = <1>; 5088 clock-frequency = <1000000>; 5089 #address-cells = <1>; 5090 #size-cells = <0>; 5091 }; 5092 }; 5093 5094 cci2: cci@ac15000 { 5095 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 5096 reg = <0x0 0x0ac15000 0x0 0x1000>; 5097 5098 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 5099 5100 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5101 5102 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5103 <&camcc CAM_CC_CPAS_AHB_CLK>, 5104 <&camcc CAM_CC_CCI_2_CLK>; 5105 clock-names = "camnoc_axi", 5106 "cpas_ahb", 5107 "cci"; 5108 5109 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 5110 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 5111 pinctrl-names = "default", "sleep"; 5112 5113 #address-cells = <1>; 5114 #size-cells = <0>; 5115 5116 status = "disabled"; 5117 5118 cci2_i2c0: i2c-bus@0 { 5119 reg = <0>; 5120 clock-frequency = <1000000>; 5121 #address-cells = <1>; 5122 #size-cells = <0>; 5123 }; 5124 5125 cci2_i2c1: i2c-bus@1 { 5126 reg = <1>; 5127 clock-frequency = <1000000>; 5128 #address-cells = <1>; 5129 #size-cells = <0>; 5130 }; 5131 }; 5132 5133 cci3: cci@ac16000 { 5134 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 5135 reg = <0x0 0x0ac16000 0x0 0x1000>; 5136 5137 interrupts = <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>; 5138 5139 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5140 5141 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5142 <&camcc CAM_CC_CPAS_AHB_CLK>, 5143 <&camcc CAM_CC_CCI_3_CLK>; 5144 clock-names = "camnoc_axi", 5145 "cpas_ahb", 5146 "cci"; 5147 5148 pinctrl-0 = <&cci3_0_default &cci3_1_default>; 5149 pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>; 5150 pinctrl-names = "default", "sleep"; 5151 5152 #address-cells = <1>; 5153 #size-cells = <0>; 5154 5155 status = "disabled"; 5156 5157 cci3_i2c0: i2c-bus@0 { 5158 reg = <0>; 5159 clock-frequency = <1000000>; 5160 #address-cells = <1>; 5161 #size-cells = <0>; 5162 }; 5163 5164 cci3_i2c1: i2c-bus@1 { 5165 reg = <1>; 5166 clock-frequency = <1000000>; 5167 #address-cells = <1>; 5168 #size-cells = <0>; 5169 }; 5170 }; 5171 5172 camss: isp@ac78000 { 5173 compatible = "qcom,sa8775p-camss"; 5174 5175 reg = <0x0 0xac78000 0x0 0x1000>, 5176 <0x0 0xac7a000 0x0 0x0f00>, 5177 <0x0 0xac7c000 0x0 0x0f00>, 5178 <0x0 0xac84000 0x0 0x0f00>, 5179 <0x0 0xac88000 0x0 0x0f00>, 5180 <0x0 0xac8c000 0x0 0x0f00>, 5181 <0x0 0xac90000 0x0 0x0f00>, 5182 <0x0 0xac94000 0x0 0x0f00>, 5183 <0x0 0xac9c000 0x0 0x2000>, 5184 <0x0 0xac9e000 0x0 0x2000>, 5185 <0x0 0xaca0000 0x0 0x2000>, 5186 <0x0 0xaca2000 0x0 0x2000>, 5187 <0x0 0xacac000 0x0 0x0400>, 5188 <0x0 0xacad000 0x0 0x0400>, 5189 <0x0 0xacae000 0x0 0x0400>, 5190 <0x0 0xac4d000 0x0 0xd000>, 5191 <0x0 0xac5a000 0x0 0xd000>, 5192 <0x0 0xac85000 0x0 0x0d00>, 5193 <0x0 0xac89000 0x0 0x0d00>, 5194 <0x0 0xac8d000 0x0 0x0d00>, 5195 <0x0 0xac91000 0x0 0x0d00>, 5196 <0x0 0xac95000 0x0 0x0d00>; 5197 reg-names = "csid_wrapper", 5198 "csid0", 5199 "csid1", 5200 "csid_lite0", 5201 "csid_lite1", 5202 "csid_lite2", 5203 "csid_lite3", 5204 "csid_lite4", 5205 "csiphy0", 5206 "csiphy1", 5207 "csiphy2", 5208 "csiphy3", 5209 "tpg0", 5210 "tpg1", 5211 "tpg2", 5212 "vfe0", 5213 "vfe1", 5214 "vfe_lite0", 5215 "vfe_lite1", 5216 "vfe_lite2", 5217 "vfe_lite3", 5218 "vfe_lite4"; 5219 5220 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5221 <&camcc CAM_CC_CORE_AHB_CLK>, 5222 <&camcc CAM_CC_CPAS_AHB_CLK>, 5223 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 5224 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 5225 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 5226 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 5227 <&camcc CAM_CC_CSID_CLK>, 5228 <&camcc CAM_CC_CSIPHY0_CLK>, 5229 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 5230 <&camcc CAM_CC_CSIPHY1_CLK>, 5231 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 5232 <&camcc CAM_CC_CSIPHY2_CLK>, 5233 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 5234 <&camcc CAM_CC_CSIPHY3_CLK>, 5235 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 5236 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 5237 <&gcc GCC_CAMERA_HF_AXI_CLK>, 5238 <&gcc GCC_CAMERA_SF_AXI_CLK>, 5239 <&camcc CAM_CC_ICP_AHB_CLK>, 5240 <&camcc CAM_CC_IFE_0_CLK>, 5241 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 5242 <&camcc CAM_CC_IFE_1_CLK>, 5243 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 5244 <&camcc CAM_CC_IFE_LITE_CLK>, 5245 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 5246 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 5247 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 5248 clock-names = "camnoc_axi", 5249 "core_ahb", 5250 "cpas_ahb", 5251 "cpas_fast_ahb_clk", 5252 "cpas_vfe_lite", 5253 "cpas_vfe0", 5254 "cpas_vfe1", 5255 "csid", 5256 "csiphy0", 5257 "csiphy0_timer", 5258 "csiphy1", 5259 "csiphy1_timer", 5260 "csiphy2", 5261 "csiphy2_timer", 5262 "csiphy3", 5263 "csiphy3_timer", 5264 "csiphy_rx", 5265 "gcc_axi_hf", 5266 "gcc_axi_sf", 5267 "icp_ahb", 5268 "vfe0", 5269 "vfe0_fast_ahb", 5270 "vfe1", 5271 "vfe1_fast_ahb", 5272 "vfe_lite", 5273 "vfe_lite_ahb", 5274 "vfe_lite_cphy_rx", 5275 "vfe_lite_csid"; 5276 5277 interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, 5278 <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, 5279 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 5280 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 5281 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 5282 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 5283 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 5284 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 5285 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 5286 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 5287 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 5288 <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, 5289 <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, 5290 <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, 5291 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 5292 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 5293 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 5294 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 5295 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 5296 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 5297 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; 5298 interrupt-names = "csid0", 5299 "csid1", 5300 "csid_lite0", 5301 "csid_lite1", 5302 "csid_lite2", 5303 "csid_lite3", 5304 "csid_lite4", 5305 "csiphy0", 5306 "csiphy1", 5307 "csiphy2", 5308 "csiphy3", 5309 "tpg0", 5310 "tpg1", 5311 "tpg2", 5312 "vfe0", 5313 "vfe1", 5314 "vfe_lite0", 5315 "vfe_lite1", 5316 "vfe_lite2", 5317 "vfe_lite3", 5318 "vfe_lite4"; 5319 5320 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5321 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5322 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 5323 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5324 interconnect-names = "ahb", 5325 "hf_0"; 5326 5327 iommus = <&apps_smmu 0x3400 0x20>; 5328 5329 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5330 power-domain-names = "top"; 5331 5332 status = "disabled"; 5333 5334 ports { 5335 #address-cells = <1>; 5336 #size-cells = <0>; 5337 5338 port@0 { 5339 reg = <0>; 5340 }; 5341 5342 port@1 { 5343 reg = <1>; 5344 }; 5345 5346 port@2 { 5347 reg = <2>; 5348 }; 5349 5350 port@3 { 5351 reg = <3>; 5352 }; 5353 }; 5354 }; 5355 5356 camcc: clock-controller@ade0000 { 5357 compatible = "qcom,sa8775p-camcc"; 5358 reg = <0x0 0x0ade0000 0x0 0x20000>; 5359 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5360 <&rpmhcc RPMH_CXO_CLK>, 5361 <&rpmhcc RPMH_CXO_CLK_A>, 5362 <&sleep_clk>; 5363 power-domains = <&rpmhpd SA8775P_MMCX>; 5364 #clock-cells = <1>; 5365 #reset-cells = <1>; 5366 #power-domain-cells = <1>; 5367 }; 5368 5369 mdss0: display-subsystem@ae00000 { 5370 compatible = "qcom,sa8775p-mdss"; 5371 reg = <0x0 0x0ae00000 0x0 0x1000>; 5372 reg-names = "mdss"; 5373 5374 /* same path used twice */ 5375 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 5376 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5377 <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS 5378 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5379 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5380 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5381 interconnect-names = "mdp0-mem", 5382 "mdp1-mem", 5383 "cpu-cfg"; 5384 5385 resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; 5386 5387 power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; 5388 5389 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5390 <&gcc GCC_DISP_HF_AXI_CLK>, 5391 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; 5392 5393 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 5394 interrupt-controller; 5395 #interrupt-cells = <1>; 5396 5397 iommus = <&apps_smmu 0x1000 0x402>; 5398 5399 #address-cells = <2>; 5400 #size-cells = <2>; 5401 ranges; 5402 5403 status = "disabled"; 5404 5405 mdss0_mdp: display-controller@ae01000 { 5406 compatible = "qcom,sa8775p-dpu"; 5407 reg = <0x0 0x0ae01000 0x0 0x8f000>, 5408 <0x0 0x0aeb0000 0x0 0x3000>; 5409 reg-names = "mdp", "vbif"; 5410 5411 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5412 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5413 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 5414 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, 5415 <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5416 clock-names = "nrt_bus", 5417 "iface", 5418 "lut", 5419 "core", 5420 "vsync"; 5421 5422 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5423 assigned-clock-rates = <19200000>; 5424 5425 operating-points-v2 = <&mdss0_mdp_opp_table>; 5426 power-domains = <&rpmhpd SA8775P_MMCX>; 5427 5428 interrupt-parent = <&mdss0>; 5429 interrupts = <0>; 5430 5431 ports { 5432 #address-cells = <1>; 5433 #size-cells = <0>; 5434 5435 port@0 { 5436 reg = <0>; 5437 5438 dpu_intf0_out: endpoint { 5439 remote-endpoint = <&mdss0_dp0_in>; 5440 }; 5441 }; 5442 5443 port@1 { 5444 reg = <1>; 5445 5446 dpu_intf4_out: endpoint { 5447 remote-endpoint = <&mdss0_dp1_in>; 5448 }; 5449 }; 5450 5451 port@2 { 5452 reg = <2>; 5453 5454 dpu_intf1_out: endpoint { 5455 remote-endpoint = <&mdss0_dsi0_in>; 5456 }; 5457 }; 5458 5459 port@3 { 5460 reg = <3>; 5461 5462 dpu_intf2_out: endpoint { 5463 remote-endpoint = <&mdss0_dsi1_in>; 5464 }; 5465 }; 5466 }; 5467 5468 mdss0_mdp_opp_table: opp-table { 5469 compatible = "operating-points-v2"; 5470 5471 opp-375000000 { 5472 opp-hz = /bits/ 64 <375000000>; 5473 required-opps = <&rpmhpd_opp_svs_l1>; 5474 }; 5475 5476 opp-500000000 { 5477 opp-hz = /bits/ 64 <500000000>; 5478 required-opps = <&rpmhpd_opp_nom>; 5479 }; 5480 5481 opp-575000000 { 5482 opp-hz = /bits/ 64 <575000000>; 5483 required-opps = <&rpmhpd_opp_turbo>; 5484 }; 5485 5486 opp-650000000 { 5487 opp-hz = /bits/ 64 <650000000>; 5488 required-opps = <&rpmhpd_opp_turbo_l1>; 5489 }; 5490 }; 5491 }; 5492 5493 mdss0_dsi0: dsi@ae94000 { 5494 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5495 reg = <0x0 0x0ae94000 0x0 0x400>; 5496 reg-names = "dsi_ctrl"; 5497 5498 interrupt-parent = <&mdss0>; 5499 interrupts = <4>; 5500 5501 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK>, 5502 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, 5503 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK>, 5504 <&dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK>, 5505 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5506 <&gcc GCC_DISP_HF_AXI_CLK>; 5507 clock-names = "byte", 5508 "byte_intf", 5509 "pixel", 5510 "core", 5511 "iface", 5512 "bus"; 5513 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, 5514 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; 5515 assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 5516 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; 5517 phys = <&mdss0_dsi0_phy>; 5518 5519 operating-points-v2 = <&mdss_dsi_opp_table>; 5520 power-domains = <&rpmhpd SA8775P_MMCX>; 5521 5522 refgen-supply = <&refgen>; 5523 5524 #address-cells = <1>; 5525 #size-cells = <0>; 5526 5527 status = "disabled"; 5528 5529 ports { 5530 #address-cells = <1>; 5531 #size-cells = <0>; 5532 5533 port@0 { 5534 reg = <0>; 5535 5536 mdss0_dsi0_in: endpoint { 5537 remote-endpoint = <&dpu_intf1_out>; 5538 }; 5539 }; 5540 5541 port@1 { 5542 reg = <1>; 5543 5544 mdss0_dsi0_out: endpoint { }; 5545 }; 5546 }; 5547 5548 mdss_dsi_opp_table: opp-table { 5549 compatible = "operating-points-v2"; 5550 5551 opp-358000000 { 5552 opp-hz = /bits/ 64 <358000000>; 5553 required-opps = <&rpmhpd_opp_svs_l1>; 5554 }; 5555 }; 5556 }; 5557 5558 mdss0_dsi0_phy: phy@ae94400 { 5559 compatible = "qcom,sa8775p-dsi-phy-5nm"; 5560 reg = <0x0 0x0ae94400 0x0 0x200>, 5561 <0x0 0x0ae94600 0x0 0x280>, 5562 <0x0 0x0ae94900 0x0 0x27c>; 5563 reg-names = "dsi_phy", 5564 "dsi_phy_lane", 5565 "dsi_pll"; 5566 5567 #clock-cells = <1>; 5568 #phy-cells = <0>; 5569 5570 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5571 <&rpmhcc RPMH_CXO_CLK>; 5572 clock-names = "iface", "ref"; 5573 5574 status = "disabled"; 5575 }; 5576 5577 mdss0_dsi1: dsi@ae96000 { 5578 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5579 reg = <0x0 0x0ae96000 0x0 0x400>; 5580 reg-names = "dsi_ctrl"; 5581 5582 interrupt-parent = <&mdss0>; 5583 interrupts = <5>; 5584 5585 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK>, 5586 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK>, 5587 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK>, 5588 <&dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK>, 5589 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5590 <&gcc GCC_DISP_HF_AXI_CLK>; 5591 clock-names = "byte", 5592 "byte_intf", 5593 "pixel", 5594 "core", 5595 "iface", 5596 "bus"; 5597 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>, 5598 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC>; 5599 assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5600 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5601 phys = <&mdss0_dsi1_phy>; 5602 5603 operating-points-v2 = <&mdss_dsi_opp_table>; 5604 power-domains = <&rpmhpd SA8775P_MMCX>; 5605 5606 refgen-supply = <&refgen>; 5607 5608 #address-cells = <1>; 5609 #size-cells = <0>; 5610 5611 status = "disabled"; 5612 5613 ports { 5614 #address-cells = <1>; 5615 #size-cells = <0>; 5616 5617 port@0 { 5618 reg = <0>; 5619 5620 mdss0_dsi1_in: endpoint { 5621 remote-endpoint = <&dpu_intf2_out>; 5622 }; 5623 }; 5624 5625 port@1 { 5626 reg = <1>; 5627 5628 mdss0_dsi1_out: endpoint { }; 5629 }; 5630 }; 5631 }; 5632 5633 mdss0_dsi1_phy: phy@ae96400 { 5634 compatible = "qcom,sa8775p-dsi-phy-5nm"; 5635 reg = <0x0 0x0ae96400 0x0 0x200>, 5636 <0x0 0x0ae96600 0x0 0x280>, 5637 <0x0 0x0ae96900 0x0 0x27c>; 5638 reg-names = "dsi_phy", 5639 "dsi_phy_lane", 5640 "dsi_pll"; 5641 5642 #clock-cells = <1>; 5643 #phy-cells = <0>; 5644 5645 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5646 <&rpmhcc RPMH_CXO_CLK>; 5647 clock-names = "iface", "ref"; 5648 5649 status = "disabled"; 5650 }; 5651 5652 mdss0_dp0_phy: phy@aec2a00 { 5653 compatible = "qcom,sa8775p-edp-phy"; 5654 5655 reg = <0x0 0x0aec2a00 0x0 0x200>, 5656 <0x0 0x0aec2200 0x0 0xd0>, 5657 <0x0 0x0aec2600 0x0 0xd0>, 5658 <0x0 0x0aec2000 0x0 0x1c8>; 5659 5660 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5661 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5662 <&gcc GCC_EDP_REF_CLKREF_EN>; 5663 clock-names = "aux", 5664 "cfg_ahb", 5665 "ref"; 5666 5667 #clock-cells = <1>; 5668 #phy-cells = <0>; 5669 5670 status = "disabled"; 5671 }; 5672 5673 mdss0_dp1_phy: phy@aec5a00 { 5674 compatible = "qcom,sa8775p-edp-phy"; 5675 5676 reg = <0x0 0x0aec5a00 0x0 0x200>, 5677 <0x0 0x0aec5200 0x0 0xd0>, 5678 <0x0 0x0aec5600 0x0 0xd0>, 5679 <0x0 0x0aec5000 0x0 0x1c8>; 5680 5681 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 5682 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5683 <&gcc GCC_EDP_REF_CLKREF_EN>; 5684 clock-names = "aux", 5685 "cfg_ahb", 5686 "ref"; 5687 5688 #clock-cells = <1>; 5689 #phy-cells = <0>; 5690 5691 status = "disabled"; 5692 }; 5693 5694 mdss0_dp0: displayport-controller@af54000 { 5695 compatible = "qcom,sa8775p-dp"; 5696 5697 reg = <0x0 0x0af54000 0x0 0x104>, 5698 <0x0 0x0af54200 0x0 0x0c0>, 5699 <0x0 0x0af55000 0x0 0x770>, 5700 <0x0 0x0af56000 0x0 0x09c>, 5701 <0x0 0x0af57000 0x0 0x09c>, 5702 <0x0 0x0af58000 0x0 0x09c>, 5703 <0x0 0x0af59000 0x0 0x09c>, 5704 <0x0 0x0af5a000 0x0 0x23c>, 5705 <0x0 0x0af5b000 0x0 0x23c>; 5706 5707 interrupt-parent = <&mdss0>; 5708 interrupts = <12>; 5709 5710 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5711 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5712 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 5713 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5714 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5715 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, 5716 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, 5717 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; 5718 clock-names = "core_iface", 5719 "core_aux", 5720 "ctrl_link", 5721 "ctrl_link_iface", 5722 "stream_pixel", 5723 "stream_1_pixel", 5724 "stream_2_pixel", 5725 "stream_3_pixel"; 5726 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5727 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5728 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, 5729 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, 5730 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; 5731 assigned-clock-parents = <&mdss0_dp0_phy 0>, 5732 <&mdss0_dp0_phy 1>, 5733 <&mdss0_dp0_phy 1>, 5734 <&mdss0_dp0_phy 1>, 5735 <&mdss0_dp0_phy 1>; 5736 phys = <&mdss0_dp0_phy>; 5737 phy-names = "dp"; 5738 5739 operating-points-v2 = <&dp_opp_table>; 5740 power-domains = <&rpmhpd SA8775P_MMCX>; 5741 5742 #sound-dai-cells = <0>; 5743 5744 status = "disabled"; 5745 5746 ports { 5747 #address-cells = <1>; 5748 #size-cells = <0>; 5749 5750 port@0 { 5751 reg = <0>; 5752 5753 mdss0_dp0_in: endpoint { 5754 remote-endpoint = <&dpu_intf0_out>; 5755 }; 5756 }; 5757 5758 port@1 { 5759 reg = <1>; 5760 5761 mdss0_dp0_out: endpoint { }; 5762 }; 5763 }; 5764 5765 dp_opp_table: opp-table { 5766 compatible = "operating-points-v2"; 5767 5768 opp-162000000 { 5769 opp-hz = /bits/ 64 <162000000>; 5770 required-opps = <&rpmhpd_opp_low_svs>; 5771 }; 5772 5773 opp-270000000 { 5774 opp-hz = /bits/ 64 <270000000>; 5775 required-opps = <&rpmhpd_opp_svs>; 5776 }; 5777 5778 opp-540000000 { 5779 opp-hz = /bits/ 64 <540000000>; 5780 required-opps = <&rpmhpd_opp_svs_l1>; 5781 }; 5782 5783 opp-810000000 { 5784 opp-hz = /bits/ 64 <810000000>; 5785 required-opps = <&rpmhpd_opp_nom>; 5786 }; 5787 }; 5788 }; 5789 5790 mdss0_dp1: displayport-controller@af5c000 { 5791 compatible = "qcom,sa8775p-dp"; 5792 5793 reg = <0x0 0x0af5c000 0x0 0x104>, 5794 <0x0 0x0af5c200 0x0 0x0c0>, 5795 <0x0 0x0af5d000 0x0 0x770>, 5796 <0x0 0x0af5e000 0x0 0x09c>, 5797 <0x0 0x0af5f000 0x0 0x09c>, 5798 <0x0 0x0af60000 0x0 0x09c>, 5799 <0x0 0x0af61000 0x0 0x09c>, 5800 <0x0 0x0af62000 0x0 0x23c>, 5801 <0x0 0x0af63000 0x0 0x23c>; 5802 5803 interrupt-parent = <&mdss0>; 5804 interrupts = <13>; 5805 5806 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5807 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 5808 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, 5809 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5810 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5811 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5812 clock-names = "core_iface", 5813 "core_aux", 5814 "ctrl_link", 5815 "ctrl_link_iface", 5816 "stream_pixel", 5817 "stream_1_pixel"; 5818 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5819 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5820 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5821 assigned-clock-parents = <&mdss0_dp1_phy 0>, 5822 <&mdss0_dp1_phy 1>, 5823 <&mdss0_dp1_phy 1>; 5824 phys = <&mdss0_dp1_phy>; 5825 phy-names = "dp"; 5826 5827 operating-points-v2 = <&dp_opp_table>; 5828 power-domains = <&rpmhpd SA8775P_MMCX>; 5829 5830 #sound-dai-cells = <0>; 5831 5832 status = "disabled"; 5833 5834 ports { 5835 #address-cells = <1>; 5836 #size-cells = <0>; 5837 5838 port@0 { 5839 reg = <0>; 5840 5841 mdss0_dp1_in: endpoint { 5842 remote-endpoint = <&dpu_intf4_out>; 5843 }; 5844 }; 5845 5846 port@1 { 5847 reg = <1>; 5848 5849 mdss0_dp1_out: endpoint { }; 5850 }; 5851 }; 5852 }; 5853 }; 5854 5855 dispcc0: clock-controller@af00000 { 5856 compatible = "qcom,sa8775p-dispcc0"; 5857 reg = <0x0 0x0af00000 0x0 0x20000>; 5858 clocks = <&gcc GCC_DISP_AHB_CLK>, 5859 <&rpmhcc RPMH_CXO_CLK>, 5860 <&rpmhcc RPMH_CXO_CLK_A>, 5861 <&sleep_clk>, 5862 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, 5863 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>, 5864 <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 5865 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, 5866 <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5867 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5868 power-domains = <&rpmhpd SA8775P_MMCX>; 5869 #clock-cells = <1>; 5870 #reset-cells = <1>; 5871 #power-domain-cells = <1>; 5872 }; 5873 5874 pdc: interrupt-controller@b220000 { 5875 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 5876 reg = <0x0 0x0b220000 0x0 0x30000>, 5877 <0x0 0x17c000f0 0x0 0x64>; 5878 qcom,pdc-ranges = <0 480 40>, 5879 <40 140 14>, 5880 <54 263 1>, 5881 <55 306 4>, 5882 <59 312 3>, 5883 <62 374 2>, 5884 <64 434 2>, 5885 <66 438 2>, 5886 <70 520 1>, 5887 <73 523 1>, 5888 <118 568 6>, 5889 <124 609 3>, 5890 <159 638 1>, 5891 <160 720 3>, 5892 <169 728 30>, 5893 <199 416 2>, 5894 <201 449 1>, 5895 <202 89 1>, 5896 <203 451 1>, 5897 <204 462 1>, 5898 <205 264 1>, 5899 <206 579 1>, 5900 <207 653 1>, 5901 <208 656 1>, 5902 <209 659 1>, 5903 <210 122 1>, 5904 <211 699 1>, 5905 <212 705 1>, 5906 <213 450 1>, 5907 <214 643 2>, 5908 <216 646 5>, 5909 <221 390 5>, 5910 <226 700 2>, 5911 <228 440 1>, 5912 <229 663 1>, 5913 <230 524 2>, 5914 <232 612 3>, 5915 <235 723 5>; 5916 #interrupt-cells = <2>; 5917 interrupt-parent = <&intc>; 5918 interrupt-controller; 5919 }; 5920 5921 tsens2: thermal-sensor@c251000 { 5922 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5923 reg = <0x0 0x0c251000 0x0 0x1ff>, 5924 <0x0 0x0c224000 0x0 0x8>; 5925 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 5926 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 5927 #qcom,sensors = <13>; 5928 interrupt-names = "uplow", "critical"; 5929 #thermal-sensor-cells = <1>; 5930 }; 5931 5932 tsens3: thermal-sensor@c252000 { 5933 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5934 reg = <0x0 0x0c252000 0x0 0x1ff>, 5935 <0x0 0x0c225000 0x0 0x8>; 5936 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 5937 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 5938 #qcom,sensors = <13>; 5939 interrupt-names = "uplow", "critical"; 5940 #thermal-sensor-cells = <1>; 5941 }; 5942 5943 tsens0: thermal-sensor@c263000 { 5944 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5945 reg = <0x0 0x0c263000 0x0 0x1ff>, 5946 <0x0 0x0c222000 0x0 0x8>; 5947 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5948 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5949 #qcom,sensors = <12>; 5950 interrupt-names = "uplow", "critical"; 5951 #thermal-sensor-cells = <1>; 5952 }; 5953 5954 tsens1: thermal-sensor@c265000 { 5955 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5956 reg = <0x0 0x0c265000 0x0 0x1ff>, 5957 <0x0 0x0c223000 0x0 0x8>; 5958 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5959 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5960 #qcom,sensors = <12>; 5961 interrupt-names = "uplow", "critical"; 5962 #thermal-sensor-cells = <1>; 5963 }; 5964 5965 aoss_qmp: power-management@c300000 { 5966 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 5967 reg = <0x0 0x0c300000 0x0 0x400>; 5968 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5969 IPCC_MPROC_SIGNAL_GLINK_QMP 5970 IRQ_TYPE_EDGE_RISING>; 5971 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5972 #clock-cells = <0>; 5973 }; 5974 5975 sram@c3f0000 { 5976 compatible = "qcom,rpmh-stats"; 5977 reg = <0x0 0x0c3f0000 0x0 0x400>; 5978 }; 5979 5980 spmi_bus: spmi@c440000 { 5981 compatible = "qcom,spmi-pmic-arb"; 5982 reg = <0x0 0x0c440000 0x0 0x1100>, 5983 <0x0 0x0c600000 0x0 0x2000000>, 5984 <0x0 0x0e600000 0x0 0x100000>, 5985 <0x0 0x0e700000 0x0 0xa0000>, 5986 <0x0 0x0c40a000 0x0 0x26000>; 5987 reg-names = "core", 5988 "chnls", 5989 "obsrvr", 5990 "intr", 5991 "cnfg"; 5992 qcom,channel = <0>; 5993 qcom,ee = <0>; 5994 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5995 interrupt-names = "periph_irq"; 5996 interrupt-controller; 5997 #interrupt-cells = <4>; 5998 #address-cells = <2>; 5999 #size-cells = <0>; 6000 }; 6001 6002 tlmm: pinctrl@f000000 { 6003 compatible = "qcom,sa8775p-tlmm"; 6004 reg = <0x0 0x0f000000 0x0 0x1000000>; 6005 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 6006 gpio-controller; 6007 #gpio-cells = <2>; 6008 interrupt-controller; 6009 #interrupt-cells = <2>; 6010 gpio-ranges = <&tlmm 0 0 149>; 6011 wakeup-parent = <&pdc>; 6012 6013 dp0_hot_plug_det: dp0-hot-plug-det-state { 6014 pins = "gpio101"; 6015 function = "edp0_hot"; 6016 bias-disable; 6017 }; 6018 6019 dp1_hot_plug_det: dp1-hot-plug-det-state { 6020 pins = "gpio102"; 6021 function = "edp1_hot"; 6022 bias-disable; 6023 }; 6024 6025 hs0_mi2s_active: hs0-mi2s-active-state { 6026 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 6027 function = "hs0_mi2s"; 6028 drive-strength = <8>; 6029 bias-disable; 6030 }; 6031 6032 hs2_mi2s_active: hs2-mi2s-active-state { 6033 pins = "gpio122", "gpio123", "gpio124", "gpio125"; 6034 function = "hs2_mi2s"; 6035 drive-strength = <8>; 6036 bias-disable; 6037 }; 6038 6039 cci0_0_default: cci0-0-default-state { 6040 pins = "gpio60", "gpio61"; 6041 function = "cci_i2c"; 6042 drive-strength = <2>; 6043 bias-pull-up = <2200>; 6044 }; 6045 6046 cci0_0_sleep: cci0-0-sleep-state { 6047 pins = "gpio60", "gpio61"; 6048 function = "cci_i2c"; 6049 drive-strength = <2>; 6050 bias-pull-down; 6051 }; 6052 6053 cci0_1_default: cci0-1-default-state { 6054 pins = "gpio52", "gpio53"; 6055 function = "cci_i2c"; 6056 drive-strength = <2>; 6057 bias-pull-up = <2200>; 6058 }; 6059 6060 cci0_1_sleep: cci0-1-sleep-state { 6061 pins = "gpio52", "gpio53"; 6062 function = "cci_i2c"; 6063 drive-strength = <2>; 6064 bias-pull-down; 6065 }; 6066 6067 cci1_0_default: cci1-0-default-state { 6068 pins = "gpio62", "gpio63"; 6069 function = "cci_i2c"; 6070 drive-strength = <2>; 6071 bias-pull-up = <2200>; 6072 }; 6073 6074 cci1_0_sleep: cci1-0-sleep-state { 6075 pins = "gpio62", "gpio63"; 6076 function = "cci_i2c"; 6077 drive-strength = <2>; 6078 bias-pull-down; 6079 }; 6080 6081 cci1_1_default: cci1-1-default-state { 6082 pins = "gpio54", "gpio55"; 6083 function = "cci_i2c"; 6084 drive-strength = <2>; 6085 bias-pull-up = <2200>; 6086 }; 6087 6088 cci1_1_sleep: cci1-1-sleep-state { 6089 pins = "gpio54", "gpio55"; 6090 function = "cci_i2c"; 6091 drive-strength = <2>; 6092 bias-pull-down; 6093 }; 6094 6095 cci2_0_default: cci2-0-default-state { 6096 pins = "gpio64", "gpio65"; 6097 function = "cci_i2c"; 6098 drive-strength = <2>; 6099 bias-pull-up = <2200>; 6100 }; 6101 6102 cci2_0_sleep: cci2-0-sleep-state { 6103 pins = "gpio64", "gpio65"; 6104 function = "cci_i2c"; 6105 drive-strength = <2>; 6106 bias-pull-down; 6107 }; 6108 6109 cci2_1_default: cci2-1-default-state { 6110 pins = "gpio56", "gpio57"; 6111 function = "cci_i2c"; 6112 drive-strength = <2>; 6113 bias-pull-up = <2200>; 6114 }; 6115 6116 cci2_1_sleep: cci2-1-sleep-state { 6117 pins = "gpio56", "gpio57"; 6118 function = "cci_i2c"; 6119 drive-strength = <2>; 6120 bias-pull-down; 6121 }; 6122 6123 cci3_0_default: cci3-0-default-state { 6124 pins = "gpio66", "gpio67"; 6125 function = "cci_i2c"; 6126 drive-strength = <2>; 6127 bias-pull-up = <2200>; 6128 }; 6129 6130 cci3_0_sleep: cci3-0-sleep-state { 6131 pins = "gpio66", "gpio67"; 6132 function = "cci_i2c"; 6133 drive-strength = <2>; 6134 bias-pull-down; 6135 }; 6136 6137 cci3_1_default: cci3-1-default-state { 6138 pins = "gpio58", "gpio59"; 6139 function = "cci_i2c"; 6140 drive-strength = <2>; 6141 bias-pull-up = <2200>; 6142 }; 6143 6144 cci3_1_sleep: cci3-1-sleep-state { 6145 pins = "gpio58", "gpio59"; 6146 function = "cci_i2c"; 6147 drive-strength = <2>; 6148 bias-pull-down; 6149 }; 6150 6151 qup_i2c0_default: qup-i2c0-state { 6152 pins = "gpio20", "gpio21"; 6153 function = "qup0_se0"; 6154 }; 6155 6156 qup_i2c1_default: qup-i2c1-state { 6157 pins = "gpio24", "gpio25"; 6158 function = "qup0_se1"; 6159 }; 6160 6161 qup_i2c2_default: qup-i2c2-state { 6162 pins = "gpio36", "gpio37"; 6163 function = "qup0_se2"; 6164 }; 6165 6166 qup_i2c3_default: qup-i2c3-state { 6167 pins = "gpio28", "gpio29"; 6168 function = "qup0_se3"; 6169 }; 6170 6171 qup_i2c4_default: qup-i2c4-state { 6172 pins = "gpio32", "gpio33"; 6173 function = "qup0_se4"; 6174 }; 6175 6176 qup_i2c5_default: qup-i2c5-state { 6177 pins = "gpio36", "gpio37"; 6178 function = "qup0_se5"; 6179 }; 6180 6181 qup_i2c7_default: qup-i2c7-state { 6182 pins = "gpio40", "gpio41"; 6183 function = "qup1_se0"; 6184 }; 6185 6186 qup_i2c8_default: qup-i2c8-state { 6187 pins = "gpio42", "gpio43"; 6188 function = "qup1_se1"; 6189 }; 6190 6191 qup_i2c9_default: qup-i2c9-state { 6192 pins = "gpio46", "gpio47"; 6193 function = "qup1_se2"; 6194 }; 6195 6196 qup_i2c10_default: qup-i2c10-state { 6197 pins = "gpio44", "gpio45"; 6198 function = "qup1_se3"; 6199 }; 6200 6201 qup_i2c11_default: qup-i2c11-state { 6202 pins = "gpio48", "gpio49"; 6203 function = "qup1_se4"; 6204 }; 6205 6206 qup_i2c12_default: qup-i2c12-state { 6207 pins = "gpio52", "gpio53"; 6208 function = "qup1_se5"; 6209 }; 6210 6211 qup_i2c13_default: qup-i2c13-state { 6212 pins = "gpio56", "gpio57"; 6213 function = "qup1_se6"; 6214 }; 6215 6216 qup_i2c14_default: qup-i2c14-state { 6217 pins = "gpio80", "gpio81"; 6218 function = "qup2_se0"; 6219 }; 6220 6221 qup_i2c15_default: qup-i2c15-state { 6222 pins = "gpio84", "gpio85"; 6223 function = "qup2_se1"; 6224 }; 6225 6226 qup_i2c16_default: qup-i2c16-state { 6227 pins = "gpio86", "gpio87"; 6228 function = "qup2_se2"; 6229 }; 6230 6231 qup_i2c17_default: qup-i2c17-state { 6232 pins = "gpio91", "gpio92"; 6233 function = "qup2_se3"; 6234 }; 6235 6236 qup_i2c18_default: qup-i2c18-state { 6237 pins = "gpio95", "gpio96"; 6238 function = "qup2_se4"; 6239 }; 6240 6241 qup_i2c19_default: qup-i2c19-state { 6242 pins = "gpio99", "gpio100"; 6243 function = "qup2_se5"; 6244 }; 6245 6246 qup_i2c20_default: qup-i2c20-state { 6247 pins = "gpio97", "gpio98"; 6248 function = "qup2_se6"; 6249 }; 6250 6251 qup_i2c21_default: qup-i2c21-state { 6252 pins = "gpio13", "gpio14"; 6253 function = "qup3_se0"; 6254 }; 6255 6256 qup_spi0_default: qup-spi0-state { 6257 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 6258 function = "qup0_se0"; 6259 }; 6260 6261 qup_spi1_default: qup-spi1-state { 6262 pins = "gpio24", "gpio25", "gpio26", "gpio27"; 6263 function = "qup0_se1"; 6264 }; 6265 6266 qup_spi2_default: qup-spi2-state { 6267 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 6268 function = "qup0_se2"; 6269 }; 6270 6271 qup_spi3_default: qup-spi3-state { 6272 pins = "gpio28", "gpio29", "gpio30", "gpio31"; 6273 function = "qup0_se3"; 6274 }; 6275 6276 qup_spi4_default: qup-spi4-state { 6277 pins = "gpio32", "gpio33", "gpio34", "gpio35"; 6278 function = "qup0_se4"; 6279 }; 6280 6281 qup_spi5_default: qup-spi5-state { 6282 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 6283 function = "qup0_se5"; 6284 }; 6285 6286 qup_spi7_default: qup-spi7-state { 6287 pins = "gpio40", "gpio41", "gpio42", "gpio43"; 6288 function = "qup1_se0"; 6289 }; 6290 6291 qup_spi8_default: qup-spi8-state { 6292 pins = "gpio42", "gpio43", "gpio40", "gpio41"; 6293 function = "qup1_se1"; 6294 }; 6295 6296 qup_spi9_default: qup-spi9-state { 6297 pins = "gpio46", "gpio47", "gpio44", "gpio45"; 6298 function = "qup1_se2"; 6299 }; 6300 6301 qup_spi10_default: qup-spi10-state { 6302 pins = "gpio44", "gpio45", "gpio46", "gpio47"; 6303 function = "qup1_se3"; 6304 }; 6305 6306 qup_spi11_default: qup-spi11-state { 6307 pins = "gpio48", "gpio49", "gpio50", "gpio51"; 6308 function = "qup1_se4"; 6309 }; 6310 6311 qup_spi12_default: qup-spi12-state { 6312 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 6313 function = "qup1_se5"; 6314 }; 6315 6316 qup_spi14_default: qup-spi14-state { 6317 pins = "gpio80", "gpio81", "gpio82", "gpio83"; 6318 function = "qup2_se0"; 6319 }; 6320 6321 qup_spi15_default: qup-spi15-state { 6322 pins = "gpio84", "gpio85", "gpio99", "gpio100"; 6323 function = "qup2_se1"; 6324 }; 6325 6326 qup_spi16_default: qup-spi16-state { 6327 pins = "gpio86", "gpio87", "gpio88", "gpio89"; 6328 function = "qup2_se2"; 6329 }; 6330 6331 qup_spi17_default: qup-spi17-state { 6332 pins = "gpio91", "gpio92", "gpio93", "gpio94"; 6333 function = "qup2_se3"; 6334 }; 6335 6336 qup_spi18_default: qup-spi18-state { 6337 pins = "gpio95", "gpio96", "gpio97", "gpio98"; 6338 function = "qup2_se4"; 6339 }; 6340 6341 qup_spi19_default: qup-spi19-state { 6342 pins = "gpio99", "gpio100", "gpio84", "gpio85"; 6343 function = "qup2_se5"; 6344 }; 6345 6346 qup_spi20_default: qup-spi20-state { 6347 pins = "gpio97", "gpio98", "gpio95", "gpio96"; 6348 function = "qup2_se6"; 6349 }; 6350 6351 qup_spi21_default: qup-spi21-state { 6352 pins = "gpio13", "gpio14", "gpio15", "gpio16"; 6353 function = "qup3_se0"; 6354 }; 6355 6356 qup_uart0_default: qup-uart0-state { 6357 qup_uart0_cts: qup-uart0-cts-pins { 6358 pins = "gpio20"; 6359 function = "qup0_se0"; 6360 }; 6361 6362 qup_uart0_rts: qup-uart0-rts-pins { 6363 pins = "gpio21"; 6364 function = "qup0_se0"; 6365 }; 6366 6367 qup_uart0_tx: qup-uart0-tx-pins { 6368 pins = "gpio22"; 6369 function = "qup0_se0"; 6370 }; 6371 6372 qup_uart0_rx: qup-uart0-rx-pins { 6373 pins = "gpio23"; 6374 function = "qup0_se0"; 6375 }; 6376 }; 6377 6378 qup_uart1_default: qup-uart1-state { 6379 qup_uart1_cts: qup-uart1-cts-pins { 6380 pins = "gpio24"; 6381 function = "qup0_se1"; 6382 }; 6383 6384 qup_uart1_rts: qup-uart1-rts-pins { 6385 pins = "gpio25"; 6386 function = "qup0_se1"; 6387 }; 6388 6389 qup_uart1_tx: qup-uart1-tx-pins { 6390 pins = "gpio26"; 6391 function = "qup0_se1"; 6392 }; 6393 6394 qup_uart1_rx: qup-uart1-rx-pins { 6395 pins = "gpio27"; 6396 function = "qup0_se1"; 6397 }; 6398 }; 6399 6400 qup_uart2_default: qup-uart2-state { 6401 qup_uart2_cts: qup-uart2-cts-pins { 6402 pins = "gpio36"; 6403 function = "qup0_se2"; 6404 }; 6405 6406 qup_uart2_rts: qup-uart2-rts-pins { 6407 pins = "gpio37"; 6408 function = "qup0_se2"; 6409 }; 6410 6411 qup_uart2_tx: qup-uart2-tx-pins { 6412 pins = "gpio38"; 6413 function = "qup0_se2"; 6414 }; 6415 6416 qup_uart2_rx: qup-uart2-rx-pins { 6417 pins = "gpio39"; 6418 function = "qup0_se2"; 6419 }; 6420 }; 6421 6422 qup_uart3_default: qup-uart3-state { 6423 qup_uart3_cts: qup-uart3-cts-pins { 6424 pins = "gpio28"; 6425 function = "qup0_se3"; 6426 }; 6427 6428 qup_uart3_rts: qup-uart3-rts-pins { 6429 pins = "gpio29"; 6430 function = "qup0_se3"; 6431 }; 6432 6433 qup_uart3_tx: qup-uart3-tx-pins { 6434 pins = "gpio30"; 6435 function = "qup0_se3"; 6436 }; 6437 6438 qup_uart3_rx: qup-uart3-rx-pins { 6439 pins = "gpio31"; 6440 function = "qup0_se3"; 6441 }; 6442 }; 6443 6444 qup_uart4_default: qup-uart4-state { 6445 qup_uart4_cts: qup-uart4-cts-pins { 6446 pins = "gpio32"; 6447 function = "qup0_se4"; 6448 }; 6449 6450 qup_uart4_rts: qup-uart4-rts-pins { 6451 pins = "gpio33"; 6452 function = "qup0_se4"; 6453 }; 6454 6455 qup_uart4_tx: qup-uart4-tx-pins { 6456 pins = "gpio34"; 6457 function = "qup0_se4"; 6458 }; 6459 6460 qup_uart4_rx: qup-uart4-rx-pins { 6461 pins = "gpio35"; 6462 function = "qup0_se4"; 6463 }; 6464 }; 6465 6466 qup_uart5_default: qup-uart5-state { 6467 qup_uart5_cts: qup-uart5-cts-pins { 6468 pins = "gpio36"; 6469 function = "qup0_se5"; 6470 }; 6471 6472 qup_uart5_rts: qup-uart5-rts-pins { 6473 pins = "gpio37"; 6474 function = "qup0_se5"; 6475 }; 6476 6477 qup_uart5_tx: qup-uart5-tx-pins { 6478 pins = "gpio38"; 6479 function = "qup0_se5"; 6480 }; 6481 6482 qup_uart5_rx: qup-uart5-rx-pins { 6483 pins = "gpio39"; 6484 function = "qup0_se5"; 6485 }; 6486 }; 6487 6488 qup_uart7_default: qup-uart7-state { 6489 qup_uart7_cts: qup-uart7-cts-pins { 6490 pins = "gpio40"; 6491 function = "qup1_se0"; 6492 }; 6493 6494 qup_uart7_rts: qup-uart7-rts-pins { 6495 pins = "gpio41"; 6496 function = "qup1_se0"; 6497 }; 6498 6499 qup_uart7_tx: qup-uart7-tx-pins { 6500 pins = "gpio42"; 6501 function = "qup1_se0"; 6502 }; 6503 6504 qup_uart7_rx: qup-uart7-rx-pins { 6505 pins = "gpio43"; 6506 function = "qup1_se0"; 6507 }; 6508 }; 6509 6510 qup_uart8_default: qup-uart8-state { 6511 qup_uart8_cts: qup-uart8-cts-pins { 6512 pins = "gpio42"; 6513 function = "qup1_se1"; 6514 }; 6515 6516 qup_uart8_rts: qup-uart8-rts-pins { 6517 pins = "gpio43"; 6518 function = "qup1_se1"; 6519 }; 6520 6521 qup_uart8_tx: qup-uart8-tx-pins { 6522 pins = "gpio40"; 6523 function = "qup1_se1"; 6524 }; 6525 6526 qup_uart8_rx: qup-uart8-rx-pins { 6527 pins = "gpio41"; 6528 function = "qup1_se1"; 6529 }; 6530 }; 6531 6532 qup_uart9_default: qup-uart9-state { 6533 qup_uart9_cts: qup-uart9-cts-pins { 6534 pins = "gpio46"; 6535 function = "qup1_se2"; 6536 }; 6537 6538 qup_uart9_rts: qup-uart9-rts-pins { 6539 pins = "gpio47"; 6540 function = "qup1_se2"; 6541 }; 6542 6543 qup_uart9_tx: qup-uart9-tx-pins { 6544 pins = "gpio44"; 6545 function = "qup1_se2"; 6546 }; 6547 6548 qup_uart9_rx: qup-uart9-rx-pins { 6549 pins = "gpio45"; 6550 function = "qup1_se2"; 6551 }; 6552 }; 6553 6554 qup_uart10_default: qup-uart10-state { 6555 pins = "gpio46", "gpio47"; 6556 function = "qup1_se3"; 6557 }; 6558 6559 qup_uart11_default: qup-uart11-state { 6560 qup_uart11_cts: qup-uart11-cts-pins { 6561 pins = "gpio48"; 6562 function = "qup1_se4"; 6563 }; 6564 6565 qup_uart11_rts: qup-uart11-rts-pins { 6566 pins = "gpio49"; 6567 function = "qup1_se4"; 6568 }; 6569 6570 qup_uart11_tx: qup-uart11-tx-pins { 6571 pins = "gpio50"; 6572 function = "qup1_se4"; 6573 }; 6574 6575 qup_uart11_rx: qup-uart11-rx-pins { 6576 pins = "gpio51"; 6577 function = "qup1_se4"; 6578 }; 6579 }; 6580 6581 qup_uart12_default: qup-uart12-state { 6582 qup_uart12_cts: qup-uart12-cts-pins { 6583 pins = "gpio52"; 6584 function = "qup1_se5"; 6585 }; 6586 6587 qup_uart12_rts: qup-uart12-rts-pins { 6588 pins = "gpio53"; 6589 function = "qup1_se5"; 6590 }; 6591 6592 qup_uart12_tx: qup-uart12-tx-pins { 6593 pins = "gpio54"; 6594 function = "qup1_se5"; 6595 }; 6596 6597 qup_uart12_rx: qup-uart12-rx-pins { 6598 pins = "gpio55"; 6599 function = "qup1_se5"; 6600 }; 6601 }; 6602 6603 qup_uart14_default: qup-uart14-state { 6604 qup_uart14_cts: qup-uart14-cts-pins { 6605 pins = "gpio80"; 6606 function = "qup2_se0"; 6607 }; 6608 6609 qup_uart14_rts: qup-uart14-rts-pins { 6610 pins = "gpio81"; 6611 function = "qup2_se0"; 6612 }; 6613 6614 qup_uart14_tx: qup-uart14-tx-pins { 6615 pins = "gpio82"; 6616 function = "qup2_se0"; 6617 }; 6618 6619 qup_uart14_rx: qup-uart14-rx-pins { 6620 pins = "gpio83"; 6621 function = "qup2_se0"; 6622 }; 6623 }; 6624 6625 qup_uart15_default: qup-uart15-state { 6626 qup_uart15_cts: qup-uart15-cts-pins { 6627 pins = "gpio84"; 6628 function = "qup2_se1"; 6629 }; 6630 6631 qup_uart15_rts: qup-uart15-rts-pins { 6632 pins = "gpio85"; 6633 function = "qup2_se1"; 6634 }; 6635 6636 qup_uart15_tx: qup-uart15-tx-pins { 6637 pins = "gpio99"; 6638 function = "qup2_se1"; 6639 }; 6640 6641 qup_uart15_rx: qup-uart15-rx-pins { 6642 pins = "gpio100"; 6643 function = "qup2_se1"; 6644 }; 6645 }; 6646 6647 qup_uart16_default: qup-uart16-state { 6648 qup_uart16_cts: qup-uart16-cts-pins { 6649 pins = "gpio86"; 6650 function = "qup2_se2"; 6651 }; 6652 6653 qup_uart16_rts: qup-uart16-rts-pins { 6654 pins = "gpio87"; 6655 function = "qup2_se2"; 6656 }; 6657 6658 qup_uart16_tx: qup-uart16-tx-pins { 6659 pins = "gpio88"; 6660 function = "qup2_se2"; 6661 }; 6662 6663 qup_uart16_rx: qup-uart16-rx-pins { 6664 pins = "gpio89"; 6665 function = "qup2_se2"; 6666 }; 6667 }; 6668 6669 qup_uart17_default: qup-uart17-state { 6670 qup_uart17_cts: qup-uart17-cts-pins { 6671 pins = "gpio91"; 6672 function = "qup2_se3"; 6673 }; 6674 6675 qup_uart17_rts: qup0-uart17-rts-pins { 6676 pins = "gpio92"; 6677 function = "qup2_se3"; 6678 }; 6679 6680 qup_uart17_tx: qup0-uart17-tx-pins { 6681 pins = "gpio93"; 6682 function = "qup2_se3"; 6683 }; 6684 6685 qup_uart17_rx: qup0-uart17-rx-pins { 6686 pins = "gpio94"; 6687 function = "qup2_se3"; 6688 }; 6689 }; 6690 6691 qup_uart18_default: qup-uart18-state { 6692 qup_uart18_cts: qup-uart18-cts-pins { 6693 pins = "gpio95"; 6694 function = "qup2_se4"; 6695 }; 6696 6697 qup_uart18_rts: qup-uart18-rts-pins { 6698 pins = "gpio96"; 6699 function = "qup2_se4"; 6700 }; 6701 6702 qup_uart18_tx: qup-uart18-tx-pins { 6703 pins = "gpio97"; 6704 function = "qup2_se4"; 6705 }; 6706 6707 qup_uart18_rx: qup-uart18-rx-pins { 6708 pins = "gpio98"; 6709 function = "qup2_se4"; 6710 }; 6711 }; 6712 6713 qup_uart19_default: qup-uart19-state { 6714 qup_uart19_cts: qup-uart19-cts-pins { 6715 pins = "gpio99"; 6716 function = "qup2_se5"; 6717 }; 6718 6719 qup_uart19_rts: qup-uart19-rts-pins { 6720 pins = "gpio100"; 6721 function = "qup2_se5"; 6722 }; 6723 6724 qup_uart19_tx: qup-uart19-tx-pins { 6725 pins = "gpio84"; 6726 function = "qup2_se5"; 6727 }; 6728 6729 qup_uart19_rx: qup-uart19-rx-pins { 6730 pins = "gpio85"; 6731 function = "qup2_se5"; 6732 }; 6733 }; 6734 6735 qup_uart20_default: qup-uart20-state { 6736 qup_uart20_cts: qup-uart20-cts-pins { 6737 pins = "gpio97"; 6738 function = "qup2_se6"; 6739 }; 6740 6741 qup_uart20_rts: qup-uart20-rts-pins { 6742 pins = "gpio98"; 6743 function = "qup2_se6"; 6744 }; 6745 6746 qup_uart20_tx: qup-uart20-tx-pins { 6747 pins = "gpio95"; 6748 function = "qup2_se6"; 6749 }; 6750 6751 qup_uart20_rx: qup-uart20-rx-pins { 6752 pins = "gpio96"; 6753 function = "qup2_se6"; 6754 }; 6755 }; 6756 6757 qup_uart21_default: qup-uart21-state { 6758 qup_uart21_cts: qup-uart21-cts-pins { 6759 pins = "gpio13"; 6760 function = "qup3_se0"; 6761 }; 6762 6763 qup_uart21_rts: qup-uart21-rts-pins { 6764 pins = "gpio14"; 6765 function = "qup3_se0"; 6766 }; 6767 6768 qup_uart21_tx: qup-uart21-tx-pins { 6769 pins = "gpio15"; 6770 function = "qup3_se0"; 6771 }; 6772 6773 qup_uart21_rx: qup-uart21-rx-pins { 6774 pins = "gpio16"; 6775 function = "qup3_se0"; 6776 }; 6777 }; 6778 6779 sdc_default: sdc-default-state { 6780 clk-pins { 6781 pins = "sdc1_clk"; 6782 drive-strength = <16>; 6783 bias-disable; 6784 }; 6785 6786 cmd-pins { 6787 pins = "sdc1_cmd"; 6788 drive-strength = <10>; 6789 bias-pull-up; 6790 }; 6791 6792 data-pins { 6793 pins = "sdc1_data"; 6794 drive-strength = <10>; 6795 bias-pull-up; 6796 }; 6797 }; 6798 6799 sdc_sleep: sdc-sleep-state { 6800 clk-pins { 6801 pins = "sdc1_clk"; 6802 drive-strength = <2>; 6803 bias-bus-hold; 6804 }; 6805 6806 cmd-pins { 6807 pins = "sdc1_cmd"; 6808 drive-strength = <2>; 6809 bias-bus-hold; 6810 }; 6811 6812 data-pins { 6813 pins = "sdc1_data"; 6814 drive-strength = <2>; 6815 bias-bus-hold; 6816 }; 6817 }; 6818 }; 6819 6820 sram: sram@146d8000 { 6821 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; 6822 reg = <0x0 0x146d8000 0x0 0x1000>; 6823 ranges = <0x0 0x0 0x146d8000 0x1000>; 6824 6825 #address-cells = <1>; 6826 #size-cells = <1>; 6827 6828 pil-reloc@94c { 6829 compatible = "qcom,pil-reloc-info"; 6830 reg = <0x94c 0xc8>; 6831 }; 6832 }; 6833 6834 apps_smmu: iommu@15000000 { 6835 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6836 reg = <0x0 0x15000000 0x0 0x100000>; 6837 #iommu-cells = <2>; 6838 #global-interrupts = <2>; 6839 dma-coherent; 6840 6841 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 6842 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 6843 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6844 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6845 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6846 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6847 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6848 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6849 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6850 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6851 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6852 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6853 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6854 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6855 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6856 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6857 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6858 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6859 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6860 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6861 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6862 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6863 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6864 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6865 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6866 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6867 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6868 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6869 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6870 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6871 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6872 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6873 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6874 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6875 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6876 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6877 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6878 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6879 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6880 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6881 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6882 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6883 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6884 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6885 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6886 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6887 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6888 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6889 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6890 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6891 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6892 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6893 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6894 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6895 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6896 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6897 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6898 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6899 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6900 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6901 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6902 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6903 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6904 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6905 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6906 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6907 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6908 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6909 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6910 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6911 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6912 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6913 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6914 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6915 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6916 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 6917 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 6918 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 6919 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 6920 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 6921 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 6922 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 6923 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 6924 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 6925 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 6926 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 6927 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 6928 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 6929 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 6930 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 6931 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 6932 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 6933 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 6934 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 6935 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 6936 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 6937 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 6938 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 6939 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 6940 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 6941 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 6942 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 6943 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 6944 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 6945 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 6946 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 6947 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 6948 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 6949 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 6950 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 6951 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 6952 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 6953 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 6954 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 6955 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 6956 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 6957 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 6958 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 6959 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 6960 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 6961 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 6962 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 6963 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 6964 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 6965 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 6966 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 6967 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 6968 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 6969 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 6970 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 6971 }; 6972 6973 pcie_smmu: iommu@15200000 { 6974 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6975 reg = <0x0 0x15200000 0x0 0x80000>; 6976 #iommu-cells = <2>; 6977 #global-interrupts = <2>; 6978 dma-coherent; 6979 6980 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 6981 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 6982 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 6983 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 6984 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 6985 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 6986 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 6987 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 6988 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 6989 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 6990 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 6991 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 6992 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 6993 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 6994 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 6995 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 6996 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 6997 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 6998 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 6999 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 7000 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 7001 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 7002 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 7003 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 7004 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 7005 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 7006 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 7007 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 7008 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 7009 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 7010 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 7011 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 7012 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 7013 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 7014 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 7015 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 7016 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 7017 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 7018 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 7019 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 7020 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 7021 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 7022 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 7023 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 7024 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 7025 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 7026 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 7027 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 7028 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 7029 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 7030 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 7031 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 7032 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 7033 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 7034 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 7035 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 7036 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 7037 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 7038 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 7039 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 7040 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 7041 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 7042 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 7043 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 7044 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 7045 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 7046 }; 7047 7048 intc: interrupt-controller@17a00000 { 7049 compatible = "arm,gic-v3"; 7050 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 7051 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 7052 interrupt-controller; 7053 #address-cells = <0>; 7054 #interrupt-cells = <3>; 7055 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 7056 #redistributor-regions = <1>; 7057 redistributor-stride = <0x0 0x20000>; 7058 }; 7059 7060 watchdog@17c10000 { 7061 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 7062 reg = <0x0 0x17c10000 0x0 0x1000>; 7063 clocks = <&sleep_clk>; 7064 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 7065 }; 7066 7067 memtimer: timer@17c20000 { 7068 compatible = "arm,armv7-timer-mem"; 7069 reg = <0x0 0x17c20000 0x0 0x1000>; 7070 ranges = <0x0 0x0 0x0 0x20000000>; 7071 #address-cells = <1>; 7072 #size-cells = <1>; 7073 7074 frame@17c21000 { 7075 reg = <0x17c21000 0x1000>, 7076 <0x17c22000 0x1000>; 7077 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7078 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 7079 frame-number = <0>; 7080 }; 7081 7082 frame@17c23000 { 7083 reg = <0x17c23000 0x1000>; 7084 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 7085 frame-number = <1>; 7086 status = "disabled"; 7087 }; 7088 7089 frame@17c25000 { 7090 reg = <0x17c25000 0x1000>; 7091 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 7092 frame-number = <2>; 7093 status = "disabled"; 7094 }; 7095 7096 frame@17c27000 { 7097 reg = <0x17c27000 0x1000>; 7098 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 7099 frame-number = <3>; 7100 status = "disabled"; 7101 }; 7102 7103 frame@17c29000 { 7104 reg = <0x17c29000 0x1000>; 7105 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 7106 frame-number = <4>; 7107 status = "disabled"; 7108 }; 7109 7110 frame@17c2b000 { 7111 reg = <0x17c2b000 0x1000>; 7112 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 7113 frame-number = <5>; 7114 status = "disabled"; 7115 }; 7116 7117 frame@17c2d000 { 7118 reg = <0x17c2d000 0x1000>; 7119 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 7120 frame-number = <6>; 7121 status = "disabled"; 7122 }; 7123 }; 7124 7125 apps_rsc: rsc@18200000 { 7126 compatible = "qcom,rpmh-rsc"; 7127 reg = <0x0 0x18200000 0x0 0x10000>, 7128 <0x0 0x18210000 0x0 0x10000>, 7129 <0x0 0x18220000 0x0 0x10000>; 7130 reg-names = "drv-0", "drv-1", "drv-2"; 7131 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7132 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7133 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 7134 qcom,tcs-offset = <0xd00>; 7135 qcom,drv-id = <2>; 7136 qcom,tcs-config = <ACTIVE_TCS 2>, 7137 <SLEEP_TCS 3>, 7138 <WAKE_TCS 3>, 7139 <CONTROL_TCS 0>; 7140 label = "apps_rsc"; 7141 power-domains = <&system_pd>; 7142 7143 apps_bcm_voter: bcm-voter { 7144 compatible = "qcom,bcm-voter"; 7145 }; 7146 7147 rpmhcc: clock-controller { 7148 compatible = "qcom,sa8775p-rpmh-clk"; 7149 #clock-cells = <1>; 7150 clock-names = "xo"; 7151 clocks = <&xo_board_clk>; 7152 }; 7153 7154 rpmhpd: power-controller { 7155 compatible = "qcom,sa8775p-rpmhpd"; 7156 #power-domain-cells = <1>; 7157 operating-points-v2 = <&rpmhpd_opp_table>; 7158 7159 rpmhpd_opp_table: opp-table { 7160 compatible = "operating-points-v2"; 7161 7162 rpmhpd_opp_ret: opp-0 { 7163 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 7164 }; 7165 7166 rpmhpd_opp_min_svs: opp-1 { 7167 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 7168 }; 7169 7170 rpmhpd_opp_low_svs: opp2 { 7171 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 7172 }; 7173 7174 rpmhpd_opp_svs: opp3 { 7175 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 7176 }; 7177 7178 rpmhpd_opp_svs_l1: opp-4 { 7179 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 7180 }; 7181 7182 rpmhpd_opp_nom: opp-5 { 7183 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 7184 }; 7185 7186 rpmhpd_opp_nom_l1: opp-6 { 7187 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 7188 }; 7189 7190 rpmhpd_opp_nom_l2: opp-7 { 7191 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 7192 }; 7193 7194 rpmhpd_opp_turbo: opp-8 { 7195 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 7196 }; 7197 7198 rpmhpd_opp_turbo_l1: opp-9 { 7199 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 7200 }; 7201 }; 7202 }; 7203 }; 7204 7205 epss_l3_cl0: interconnect@18590000 { 7206 compatible = "qcom,sa8775p-epss-l3", 7207 "qcom,epss-l3"; 7208 reg = <0x0 0x18590000 0x0 0x1000>; 7209 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7210 clock-names = "xo", "alternate"; 7211 #interconnect-cells = <1>; 7212 }; 7213 7214 cpufreq_hw: cpufreq@18591000 { 7215 compatible = "qcom,sa8775p-cpufreq-epss", 7216 "qcom,cpufreq-epss"; 7217 reg = <0x0 0x18591000 0x0 0x1000>, 7218 <0x0 0x18593000 0x0 0x1000>; 7219 reg-names = "freq-domain0", "freq-domain1"; 7220 7221 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 7222 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 7223 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 7224 7225 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7226 clock-names = "xo", "alternate"; 7227 7228 #freq-domain-cells = <1>; 7229 }; 7230 7231 epss_l3_cl1: interconnect@18592000 { 7232 compatible = "qcom,sa8775p-epss-l3", 7233 "qcom,epss-l3"; 7234 reg = <0x0 0x18592000 0x0 0x1000>; 7235 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7236 clock-names = "xo", "alternate"; 7237 #interconnect-cells = <1>; 7238 }; 7239 7240 remoteproc_gpdsp0: remoteproc@20c00000 { 7241 compatible = "qcom,sa8775p-gpdsp0-pas"; 7242 reg = <0x0 0x20c00000 0x0 0x10000>; 7243 7244 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 7245 <&smp2p_gpdsp0_in 0 0>, 7246 <&smp2p_gpdsp0_in 1 0>, 7247 <&smp2p_gpdsp0_in 2 0>, 7248 <&smp2p_gpdsp0_in 3 0>; 7249 interrupt-names = "wdog", "fatal", "ready", 7250 "handover", "stop-ack"; 7251 7252 clocks = <&rpmhcc RPMH_CXO_CLK>; 7253 clock-names = "xo"; 7254 7255 power-domains = <&rpmhpd SA8775P_CX>, 7256 <&rpmhpd SA8775P_MXC>; 7257 power-domain-names = "cx", "mxc"; 7258 7259 interconnects = <&gpdsp_anoc MASTER_DSP0 0 7260 &config_noc SLAVE_CLK_CTL 0>; 7261 7262 memory-region = <&pil_gdsp0_mem>; 7263 7264 qcom,qmp = <&aoss_qmp>; 7265 7266 qcom,smem-states = <&smp2p_gpdsp0_out 0>; 7267 qcom,smem-state-names = "stop"; 7268 7269 status = "disabled"; 7270 7271 glink-edge { 7272 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 7273 IPCC_MPROC_SIGNAL_GLINK_QMP 7274 IRQ_TYPE_EDGE_RISING>; 7275 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 7276 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7277 7278 label = "gpdsp0"; 7279 qcom,remote-pid = <17>; 7280 7281 fastrpc { 7282 compatible = "qcom,fastrpc"; 7283 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7284 label = "gdsp0"; 7285 #address-cells = <1>; 7286 #size-cells = <0>; 7287 7288 compute-cb@1 { 7289 compatible = "qcom,fastrpc-compute-cb"; 7290 reg = <1>; 7291 iommus = <&apps_smmu 0x38a1 0x0>; 7292 dma-coherent; 7293 }; 7294 7295 compute-cb@2 { 7296 compatible = "qcom,fastrpc-compute-cb"; 7297 reg = <2>; 7298 iommus = <&apps_smmu 0x38a2 0x0>; 7299 dma-coherent; 7300 }; 7301 7302 compute-cb@3 { 7303 compatible = "qcom,fastrpc-compute-cb"; 7304 reg = <3>; 7305 iommus = <&apps_smmu 0x38a3 0x0>; 7306 dma-coherent; 7307 }; 7308 }; 7309 }; 7310 }; 7311 7312 remoteproc_gpdsp1: remoteproc@21c00000 { 7313 compatible = "qcom,sa8775p-gpdsp1-pas"; 7314 reg = <0x0 0x21c00000 0x0 0x10000>; 7315 7316 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 7317 <&smp2p_gpdsp1_in 0 0>, 7318 <&smp2p_gpdsp1_in 1 0>, 7319 <&smp2p_gpdsp1_in 2 0>, 7320 <&smp2p_gpdsp1_in 3 0>; 7321 interrupt-names = "wdog", "fatal", "ready", 7322 "handover", "stop-ack"; 7323 7324 clocks = <&rpmhcc RPMH_CXO_CLK>; 7325 clock-names = "xo"; 7326 7327 power-domains = <&rpmhpd SA8775P_CX>, 7328 <&rpmhpd SA8775P_MXC>; 7329 power-domain-names = "cx", "mxc"; 7330 7331 interconnects = <&gpdsp_anoc MASTER_DSP1 0 7332 &config_noc SLAVE_CLK_CTL 0>; 7333 7334 memory-region = <&pil_gdsp1_mem>; 7335 7336 qcom,qmp = <&aoss_qmp>; 7337 7338 qcom,smem-states = <&smp2p_gpdsp1_out 0>; 7339 qcom,smem-state-names = "stop"; 7340 7341 status = "disabled"; 7342 7343 glink-edge { 7344 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 7345 IPCC_MPROC_SIGNAL_GLINK_QMP 7346 IRQ_TYPE_EDGE_RISING>; 7347 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 7348 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7349 7350 label = "gpdsp1"; 7351 qcom,remote-pid = <18>; 7352 7353 fastrpc { 7354 compatible = "qcom,fastrpc"; 7355 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7356 label = "gdsp1"; 7357 #address-cells = <1>; 7358 #size-cells = <0>; 7359 7360 compute-cb@1 { 7361 compatible = "qcom,fastrpc-compute-cb"; 7362 reg = <1>; 7363 iommus = <&apps_smmu 0x38c1 0x0>; 7364 dma-coherent; 7365 }; 7366 7367 compute-cb@2 { 7368 compatible = "qcom,fastrpc-compute-cb"; 7369 reg = <2>; 7370 iommus = <&apps_smmu 0x38c2 0x0>; 7371 dma-coherent; 7372 }; 7373 7374 compute-cb@3 { 7375 compatible = "qcom,fastrpc-compute-cb"; 7376 reg = <3>; 7377 iommus = <&apps_smmu 0x38c3 0x0>; 7378 dma-coherent; 7379 }; 7380 }; 7381 }; 7382 }; 7383 7384 mdss1: display-subsystem@22000000 { 7385 compatible = "qcom,sa8775p-mdss"; 7386 reg = <0x0 0x22000000 0x0 0x1000>; 7387 reg-names = "mdss"; 7388 7389 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS 7390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 7391 <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS 7392 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 7393 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 7394 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 7395 interconnect-names = "mdp0-mem", 7396 "mdp1-mem", 7397 "cpu-cfg"; 7398 7399 resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>; 7400 7401 power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>; 7402 7403 clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, 7404 <&gcc GCC_DISP1_HF_AXI_CLK>, 7405 <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>; 7406 7407 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 7408 interrupt-controller; 7409 #interrupt-cells = <1>; 7410 7411 iommus = <&apps_smmu 0x1800 0x402>; 7412 7413 #address-cells = <2>; 7414 #size-cells = <2>; 7415 ranges; 7416 7417 status = "disabled"; 7418 7419 display-controller@22001000 { 7420 compatible = "qcom,sa8775p-dpu"; 7421 reg = <0x0 0x22001000 0x0 0x8f000>, 7422 <0x0 0x220b0000 0x0 0x3000>; 7423 reg-names = "mdp", "vbif"; 7424 7425 clocks = <&gcc GCC_DISP1_HF_AXI_CLK>, 7426 <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, 7427 <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 7428 <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>, 7429 <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 7430 clock-names = "nrt_bus", 7431 "iface", 7432 "lut", 7433 "core", 7434 "vsync"; 7435 7436 assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 7437 assigned-clock-rates = <19200000>; 7438 7439 operating-points-v2 = <&mdss0_mdp_opp_table>; 7440 power-domains = <&rpmhpd SA8775P_MMCX>; 7441 7442 interrupt-parent = <&mdss1>; 7443 interrupts = <0>; 7444 7445 ports { 7446 #address-cells = <1>; 7447 #size-cells = <0>; 7448 7449 port@0 { 7450 reg = <0>; 7451 7452 dpu1_intf0_out: endpoint { 7453 remote-endpoint = <&mdss1_dp0_in>; 7454 }; 7455 }; 7456 7457 port@1 { 7458 reg = <1>; 7459 7460 dpu1_intf4_out: endpoint { 7461 remote-endpoint = <&mdss1_dp1_in>; 7462 }; 7463 }; 7464 }; 7465 }; 7466 7467 mdss1_dp0_phy: phy@220c2a00 { 7468 compatible = "qcom,sa8775p-edp-phy"; 7469 reg = <0x0 0x220c2a00 0x0 0x200>, 7470 <0x0 0x220c2200 0x0 0xd0>, 7471 <0x0 0x220c2600 0x0 0xd0>, 7472 <0x0 0x220c2000 0x0 0x1c8>; 7473 7474 clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 7475 <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, 7476 <&gcc GCC_EDP_REF_CLKREF_EN>; 7477 clock-names = "aux", 7478 "cfg_ahb", 7479 "ref"; 7480 7481 #clock-cells = <1>; 7482 #phy-cells = <0>; 7483 7484 status = "disabled"; 7485 }; 7486 7487 mdss1_dp1_phy: phy@220c5a00 { 7488 compatible = "qcom,sa8775p-edp-phy"; 7489 reg = <0x0 0x220c5a00 0x0 0x200>, 7490 <0x0 0x220c5200 0x0 0xd0>, 7491 <0x0 0x220c5600 0x0 0xd0>, 7492 <0x0 0x220c5000 0x0 0x1c8>; 7493 7494 clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 7495 <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, 7496 <&gcc GCC_EDP_REF_CLKREF_EN>; 7497 clock-names = "aux", 7498 "cfg_ahb", 7499 "ref"; 7500 7501 #clock-cells = <1>; 7502 #phy-cells = <0>; 7503 7504 status = "disabled"; 7505 }; 7506 7507 mdss1_dp0: displayport-controller@22154000 { 7508 compatible = "qcom,sa8775p-dp"; 7509 reg = <0x0 0x22154000 0x0 0x104>, 7510 <0x0 0x22154200 0x0 0x0c0>, 7511 <0x0 0x22155000 0x0 0x770>, 7512 <0x0 0x22156000 0x0 0x09c>, 7513 <0x0 0x22157000 0x0 0x09c>, 7514 <0x0 0x22158000 0x0 0x09c>, 7515 <0x0 0x22159000 0x0 0x09c>, 7516 <0x0 0x2215a000 0x0 0x23c>, 7517 <0x0 0x2215b000 0x0 0x23c>; 7518 7519 interrupt-parent = <&mdss1>; 7520 interrupts = <12>; 7521 7522 clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, 7523 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 7524 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 7525 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 7526 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 7527 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, 7528 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, 7529 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; 7530 clock-names = "core_iface", 7531 "core_aux", 7532 "ctrl_link", 7533 "ctrl_link_iface", 7534 "stream_pixel", 7535 "stream_1_pixel", 7536 "stream_2_pixel", 7537 "stream_3_pixel"; 7538 assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 7539 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 7540 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, 7541 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, 7542 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; 7543 assigned-clock-parents = <&mdss1_dp0_phy 0>, 7544 <&mdss1_dp0_phy 1>, 7545 <&mdss1_dp0_phy 1>, 7546 <&mdss1_dp0_phy 1>, 7547 <&mdss1_dp0_phy 1>; 7548 phys = <&mdss1_dp0_phy>; 7549 phy-names = "dp"; 7550 7551 operating-points-v2 = <&dp_opp_table>; 7552 power-domains = <&rpmhpd SA8775P_MMCX>; 7553 7554 #sound-dai-cells = <0>; 7555 7556 status = "disabled"; 7557 7558 ports { 7559 #address-cells = <1>; 7560 #size-cells = <0>; 7561 7562 port@0 { 7563 reg = <0>; 7564 7565 mdss1_dp0_in: endpoint { 7566 remote-endpoint = <&dpu1_intf0_out>; 7567 }; 7568 }; 7569 7570 port@1 { 7571 reg = <1>; 7572 7573 mdss1_dp0_out: endpoint { }; 7574 }; 7575 }; 7576 }; 7577 7578 mdss1_dp1: displayport-controller@2215c000 { 7579 compatible = "qcom,sa8775p-dp"; 7580 reg = <0x0 0x2215c000 0x0 0x104>, 7581 <0x0 0x2215c200 0x0 0x0c0>, 7582 <0x0 0x2215d000 0x0 0x770>, 7583 <0x0 0x2215e000 0x0 0x09c>, 7584 <0x0 0x2215f000 0x0 0x09c>, 7585 <0x0 0x22160000 0x0 0x09c>, 7586 <0x0 0x22161000 0x0 0x09c>, 7587 <0x0 0x22162000 0x0 0x23c>, 7588 <0x0 0x22163000 0x0 0x23c>; 7589 7590 interrupt-parent = <&mdss1>; 7591 interrupts = <13>; 7592 7593 clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, 7594 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 7595 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, 7596 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 7597 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 7598 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 7599 clock-names = "core_iface", 7600 "core_aux", 7601 "ctrl_link", 7602 "ctrl_link_iface", 7603 "stream_pixel", 7604 "stream_1_pixel"; 7605 assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 7606 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 7607 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 7608 assigned-clock-parents = <&mdss1_dp1_phy 0>, 7609 <&mdss1_dp1_phy 1>, 7610 <&mdss1_dp1_phy 1>; 7611 phys = <&mdss1_dp1_phy>; 7612 phy-names = "dp"; 7613 7614 operating-points-v2 = <&dp_opp_table>; 7615 power-domains = <&rpmhpd SA8775P_MMCX>; 7616 7617 #sound-dai-cells = <0>; 7618 7619 status = "disabled"; 7620 7621 ports { 7622 #address-cells = <1>; 7623 #size-cells = <0>; 7624 7625 port@0 { 7626 reg = <0>; 7627 7628 mdss1_dp1_in: endpoint { 7629 remote-endpoint = <&dpu1_intf4_out>; 7630 }; 7631 }; 7632 7633 port@1 { 7634 reg = <1>; 7635 7636 mdss1_dp1_out: endpoint { }; 7637 }; 7638 }; 7639 7640 }; 7641 }; 7642 7643 dispcc1: clock-controller@22100000 { 7644 compatible = "qcom,sa8775p-dispcc1"; 7645 reg = <0x0 0x22100000 0x0 0x20000>; 7646 clocks = <&gcc GCC_DISP_AHB_CLK>, 7647 <&rpmhcc RPMH_CXO_CLK>, 7648 <&rpmhcc RPMH_CXO_CLK_A>, 7649 <&sleep_clk>, 7650 <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>, 7651 <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>, 7652 <0>, <0>, <0>, <0>; 7653 power-domains = <&rpmhpd SA8775P_MMCX>; 7654 #clock-cells = <1>; 7655 #reset-cells = <1>; 7656 #power-domain-cells = <1>; 7657 }; 7658 7659 ethernet1: ethernet@23000000 { 7660 compatible = "qcom,sa8775p-ethqos"; 7661 reg = <0x0 0x23000000 0x0 0x10000>, 7662 <0x0 0x23016000 0x0 0x100>; 7663 reg-names = "stmmaceth", "rgmii"; 7664 7665 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 7666 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 7667 interrupt-names = "macirq", "sfty"; 7668 7669 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 7670 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 7671 <&gcc GCC_EMAC1_PTP_CLK>, 7672 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 7673 clock-names = "stmmaceth", 7674 "pclk", 7675 "ptp_ref", 7676 "phyaux"; 7677 7678 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 7679 &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>, 7680 <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS 7681 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7682 interconnect-names = "cpu-mac", 7683 "mac-mem"; 7684 7685 power-domains = <&gcc EMAC1_GDSC>; 7686 7687 phys = <&serdes1>; 7688 phy-names = "serdes"; 7689 7690 iommus = <&apps_smmu 0x140 0xf>; 7691 dma-coherent; 7692 7693 snps,tso; 7694 snps,pbl = <32>; 7695 rx-fifo-depth = <16384>; 7696 tx-fifo-depth = <16384>; 7697 7698 status = "disabled"; 7699 }; 7700 7701 ethernet0: ethernet@23040000 { 7702 compatible = "qcom,sa8775p-ethqos"; 7703 reg = <0x0 0x23040000 0x0 0x10000>, 7704 <0x0 0x23056000 0x0 0x100>; 7705 reg-names = "stmmaceth", "rgmii"; 7706 7707 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 7708 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; 7709 interrupt-names = "macirq", "sfty"; 7710 7711 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 7712 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 7713 <&gcc GCC_EMAC0_PTP_CLK>, 7714 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 7715 clock-names = "stmmaceth", 7716 "pclk", 7717 "ptp_ref", 7718 "phyaux"; 7719 7720 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 7721 &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>, 7722 <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS 7723 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7724 interconnect-names = "cpu-mac", 7725 "mac-mem"; 7726 7727 power-domains = <&gcc EMAC0_GDSC>; 7728 7729 phys = <&serdes0>; 7730 phy-names = "serdes"; 7731 7732 iommus = <&apps_smmu 0x120 0xf>; 7733 dma-coherent; 7734 7735 snps,tso; 7736 snps,pbl = <32>; 7737 rx-fifo-depth = <16384>; 7738 tx-fifo-depth = <16384>; 7739 7740 status = "disabled"; 7741 }; 7742 7743 nspa_noc: interconnect@260c0000 { 7744 compatible = "qcom,sa8775p-nspa-noc"; 7745 reg = <0x0 0x260c0000 0x0 0x16080>; 7746 #interconnect-cells = <2>; 7747 qcom,bcm-voters = <&apps_bcm_voter>; 7748 }; 7749 7750 remoteproc_cdsp0: remoteproc@26300000 { 7751 compatible = "qcom,sa8775p-cdsp0-pas"; 7752 reg = <0x0 0x26300000 0x0 0x10000>; 7753 7754 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 7755 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>, 7756 <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>, 7757 <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>, 7758 <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>; 7759 interrupt-names = "wdog", "fatal", "ready", 7760 "handover", "stop-ack"; 7761 7762 clocks = <&rpmhcc RPMH_CXO_CLK>; 7763 clock-names = "xo"; 7764 7765 power-domains = <&rpmhpd SA8775P_CX>, 7766 <&rpmhpd SA8775P_MXC>, 7767 <&rpmhpd SA8775P_NSP0>; 7768 power-domain-names = "cx", "mxc", "nsp"; 7769 7770 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 7771 &mc_virt SLAVE_EBI1 0>; 7772 7773 memory-region = <&pil_cdsp0_mem>; 7774 7775 qcom,qmp = <&aoss_qmp>; 7776 7777 qcom,smem-states = <&smp2p_cdsp0_out 0>; 7778 qcom,smem-state-names = "stop"; 7779 7780 status = "disabled"; 7781 7782 glink-edge { 7783 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7784 IPCC_MPROC_SIGNAL_GLINK_QMP 7785 IRQ_TYPE_EDGE_RISING>; 7786 mboxes = <&ipcc IPCC_CLIENT_CDSP 7787 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7788 7789 label = "cdsp"; 7790 qcom,remote-pid = <5>; 7791 7792 fastrpc { 7793 compatible = "qcom,fastrpc"; 7794 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7795 label = "cdsp"; 7796 #address-cells = <1>; 7797 #size-cells = <0>; 7798 7799 compute-cb@1 { 7800 compatible = "qcom,fastrpc-compute-cb"; 7801 reg = <1>; 7802 iommus = <&apps_smmu 0x2141 0x04a0>, 7803 <&apps_smmu 0x2181 0x0400>; 7804 dma-coherent; 7805 }; 7806 7807 compute-cb@2 { 7808 compatible = "qcom,fastrpc-compute-cb"; 7809 reg = <2>; 7810 iommus = <&apps_smmu 0x2142 0x04a0>, 7811 <&apps_smmu 0x2182 0x0400>; 7812 dma-coherent; 7813 }; 7814 7815 compute-cb@3 { 7816 compatible = "qcom,fastrpc-compute-cb"; 7817 reg = <3>; 7818 iommus = <&apps_smmu 0x2143 0x04a0>, 7819 <&apps_smmu 0x2183 0x0400>; 7820 dma-coherent; 7821 }; 7822 7823 compute-cb@4 { 7824 compatible = "qcom,fastrpc-compute-cb"; 7825 reg = <4>; 7826 iommus = <&apps_smmu 0x2144 0x04a0>, 7827 <&apps_smmu 0x2184 0x0400>; 7828 dma-coherent; 7829 }; 7830 7831 compute-cb@5 { 7832 compatible = "qcom,fastrpc-compute-cb"; 7833 reg = <5>; 7834 iommus = <&apps_smmu 0x2145 0x04a0>, 7835 <&apps_smmu 0x2185 0x0400>; 7836 dma-coherent; 7837 }; 7838 7839 compute-cb@6 { 7840 compatible = "qcom,fastrpc-compute-cb"; 7841 reg = <6>; 7842 iommus = <&apps_smmu 0x2146 0x04a0>, 7843 <&apps_smmu 0x2186 0x0400>; 7844 dma-coherent; 7845 }; 7846 7847 compute-cb@7 { 7848 compatible = "qcom,fastrpc-compute-cb"; 7849 reg = <7>; 7850 iommus = <&apps_smmu 0x2147 0x04a0>, 7851 <&apps_smmu 0x2187 0x0400>; 7852 dma-coherent; 7853 }; 7854 7855 compute-cb@8 { 7856 compatible = "qcom,fastrpc-compute-cb"; 7857 reg = <8>; 7858 iommus = <&apps_smmu 0x2148 0x04a0>, 7859 <&apps_smmu 0x2188 0x0400>; 7860 dma-coherent; 7861 }; 7862 7863 compute-cb@9 { 7864 compatible = "qcom,fastrpc-compute-cb"; 7865 reg = <9>; 7866 iommus = <&apps_smmu 0x2149 0x04a0>, 7867 <&apps_smmu 0x2189 0x0400>; 7868 dma-coherent; 7869 }; 7870 7871 compute-cb@11 { 7872 compatible = "qcom,fastrpc-compute-cb"; 7873 reg = <11>; 7874 iommus = <&apps_smmu 0x214b 0x04a0>, 7875 <&apps_smmu 0x218b 0x0400>; 7876 dma-coherent; 7877 }; 7878 }; 7879 }; 7880 }; 7881 7882 nspb_noc: interconnect@2a0c0000 { 7883 compatible = "qcom,sa8775p-nspb-noc"; 7884 reg = <0x0 0x2a0c0000 0x0 0x16080>; 7885 #interconnect-cells = <2>; 7886 qcom,bcm-voters = <&apps_bcm_voter>; 7887 }; 7888 7889 remoteproc_cdsp1: remoteproc@2a300000 { 7890 compatible = "qcom,sa8775p-cdsp1-pas"; 7891 reg = <0x0 0x2a300000 0x0 0x10000>; 7892 7893 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 7894 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, 7895 <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>, 7896 <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>, 7897 <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>; 7898 interrupt-names = "wdog", "fatal", "ready", 7899 "handover", "stop-ack"; 7900 7901 clocks = <&rpmhcc RPMH_CXO_CLK>; 7902 clock-names = "xo"; 7903 7904 power-domains = <&rpmhpd SA8775P_CX>, 7905 <&rpmhpd SA8775P_MXC>, 7906 <&rpmhpd SA8775P_NSP1>; 7907 power-domain-names = "cx", "mxc", "nsp"; 7908 7909 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 7910 &mc_virt SLAVE_EBI1 0>; 7911 7912 memory-region = <&pil_cdsp1_mem>; 7913 7914 qcom,qmp = <&aoss_qmp>; 7915 7916 qcom,smem-states = <&smp2p_cdsp1_out 0>; 7917 qcom,smem-state-names = "stop"; 7918 7919 status = "disabled"; 7920 7921 glink-edge { 7922 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 7923 IPCC_MPROC_SIGNAL_GLINK_QMP 7924 IRQ_TYPE_EDGE_RISING>; 7925 mboxes = <&ipcc IPCC_CLIENT_NSP1 7926 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7927 7928 label = "cdsp"; 7929 qcom,remote-pid = <12>; 7930 7931 fastrpc { 7932 compatible = "qcom,fastrpc"; 7933 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7934 label = "cdsp1"; 7935 #address-cells = <1>; 7936 #size-cells = <0>; 7937 7938 compute-cb@1 { 7939 compatible = "qcom,fastrpc-compute-cb"; 7940 reg = <1>; 7941 iommus = <&apps_smmu 0x2941 0x04a0>, 7942 <&apps_smmu 0x2981 0x0400>; 7943 dma-coherent; 7944 }; 7945 7946 compute-cb@2 { 7947 compatible = "qcom,fastrpc-compute-cb"; 7948 reg = <2>; 7949 iommus = <&apps_smmu 0x2942 0x04a0>, 7950 <&apps_smmu 0x2982 0x0400>; 7951 dma-coherent; 7952 }; 7953 7954 compute-cb@3 { 7955 compatible = "qcom,fastrpc-compute-cb"; 7956 reg = <3>; 7957 iommus = <&apps_smmu 0x2943 0x04a0>, 7958 <&apps_smmu 0x2983 0x0400>; 7959 dma-coherent; 7960 }; 7961 7962 compute-cb@4 { 7963 compatible = "qcom,fastrpc-compute-cb"; 7964 reg = <4>; 7965 iommus = <&apps_smmu 0x2944 0x04a0>, 7966 <&apps_smmu 0x2984 0x0400>; 7967 dma-coherent; 7968 }; 7969 7970 compute-cb@5 { 7971 compatible = "qcom,fastrpc-compute-cb"; 7972 reg = <5>; 7973 iommus = <&apps_smmu 0x2945 0x04a0>, 7974 <&apps_smmu 0x2985 0x0400>; 7975 dma-coherent; 7976 }; 7977 7978 compute-cb@6 { 7979 compatible = "qcom,fastrpc-compute-cb"; 7980 reg = <6>; 7981 iommus = <&apps_smmu 0x2946 0x04a0>, 7982 <&apps_smmu 0x2986 0x0400>; 7983 dma-coherent; 7984 }; 7985 7986 compute-cb@7 { 7987 compatible = "qcom,fastrpc-compute-cb"; 7988 reg = <7>; 7989 iommus = <&apps_smmu 0x2947 0x04a0>, 7990 <&apps_smmu 0x2987 0x0400>; 7991 dma-coherent; 7992 }; 7993 7994 compute-cb@8 { 7995 compatible = "qcom,fastrpc-compute-cb"; 7996 reg = <8>; 7997 iommus = <&apps_smmu 0x2948 0x04a0>, 7998 <&apps_smmu 0x2988 0x0400>; 7999 dma-coherent; 8000 }; 8001 8002 compute-cb@9 { 8003 compatible = "qcom,fastrpc-compute-cb"; 8004 reg = <9>; 8005 iommus = <&apps_smmu 0x2949 0x04a0>, 8006 <&apps_smmu 0x2989 0x0400>; 8007 dma-coherent; 8008 }; 8009 8010 compute-cb@10 { 8011 compatible = "qcom,fastrpc-compute-cb"; 8012 reg = <10>; 8013 iommus = <&apps_smmu 0x294a 0x04a0>, 8014 <&apps_smmu 0x298a 0x0400>; 8015 dma-coherent; 8016 }; 8017 8018 compute-cb@11 { 8019 compatible = "qcom,fastrpc-compute-cb"; 8020 reg = <11>; 8021 iommus = <&apps_smmu 0x294b 0x04a0>, 8022 <&apps_smmu 0x298b 0x0400>; 8023 dma-coherent; 8024 }; 8025 8026 compute-cb@12 { 8027 compatible = "qcom,fastrpc-compute-cb"; 8028 reg = <12>; 8029 iommus = <&apps_smmu 0x294c 0x04a0>, 8030 <&apps_smmu 0x298c 0x0400>; 8031 dma-coherent; 8032 }; 8033 8034 compute-cb@13 { 8035 compatible = "qcom,fastrpc-compute-cb"; 8036 reg = <13>; 8037 iommus = <&apps_smmu 0x294d 0x04a0>, 8038 <&apps_smmu 0x298d 0x0400>; 8039 dma-coherent; 8040 }; 8041 }; 8042 }; 8043 }; 8044 8045 remoteproc_adsp: remoteproc@30000000 { 8046 compatible = "qcom,sa8775p-adsp-pas"; 8047 reg = <0x0 0x30000000 0x0 0x100>; 8048 8049 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 8050 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 8051 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 8052 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 8053 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 8054 interrupt-names = "wdog", "fatal", "ready", "handover", 8055 "stop-ack"; 8056 8057 clocks = <&rpmhcc RPMH_CXO_CLK>; 8058 clock-names = "xo"; 8059 8060 power-domains = <&rpmhpd SA8775P_LCX>, 8061 <&rpmhpd SA8775P_LMX>; 8062 power-domain-names = "lcx", "lmx"; 8063 8064 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 8065 8066 memory-region = <&pil_adsp_mem>; 8067 8068 qcom,qmp = <&aoss_qmp>; 8069 8070 qcom,smem-states = <&smp2p_adsp_out 0>; 8071 qcom,smem-state-names = "stop"; 8072 8073 status = "disabled"; 8074 8075 glink-edge { 8076 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 8077 IPCC_MPROC_SIGNAL_GLINK_QMP 8078 IRQ_TYPE_EDGE_RISING>; 8079 mboxes = <&ipcc IPCC_CLIENT_LPASS 8080 IPCC_MPROC_SIGNAL_GLINK_QMP>; 8081 8082 label = "lpass"; 8083 qcom,remote-pid = <2>; 8084 8085 fastrpc { 8086 compatible = "qcom,fastrpc"; 8087 qcom,glink-channels = "fastrpcglink-apps-dsp"; 8088 label = "adsp"; 8089 memory-region = <&adsp_rpc_remote_heap_mem>; 8090 qcom,vmids = <QCOM_SCM_VMID_LPASS 8091 QCOM_SCM_VMID_ADSP_HEAP>; 8092 #address-cells = <1>; 8093 #size-cells = <0>; 8094 8095 compute-cb@3 { 8096 compatible = "qcom,fastrpc-compute-cb"; 8097 reg = <3>; 8098 iommus = <&apps_smmu 0x3003 0x0>; 8099 dma-coherent; 8100 }; 8101 8102 compute-cb@4 { 8103 compatible = "qcom,fastrpc-compute-cb"; 8104 reg = <4>; 8105 iommus = <&apps_smmu 0x3004 0x0>; 8106 dma-coherent; 8107 }; 8108 8109 compute-cb@5 { 8110 compatible = "qcom,fastrpc-compute-cb"; 8111 reg = <5>; 8112 iommus = <&apps_smmu 0x3005 0x0>; 8113 qcom,nsessions = <5>; 8114 dma-coherent; 8115 }; 8116 }; 8117 8118 gpr { 8119 compatible = "qcom,gpr"; 8120 qcom,glink-channels = "adsp_apps"; 8121 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 8122 qcom,intents = <512 20>; 8123 #address-cells = <1>; 8124 #size-cells = <0>; 8125 8126 q6apm: service@1 { 8127 compatible = "qcom,q6apm"; 8128 reg = <GPR_APM_MODULE_IID>; 8129 #sound-dai-cells = <0>; 8130 qcom,protection-domain = "avs/audio", 8131 "msm/adsp/audio_pd"; 8132 8133 q6apmbedai: bedais { 8134 compatible = "qcom,q6apm-lpass-dais"; 8135 #sound-dai-cells = <1>; 8136 }; 8137 8138 q6apmdai: dais { 8139 compatible = "qcom,q6apm-dais"; 8140 iommus = <&apps_smmu 0x3001 0x0>; 8141 }; 8142 }; 8143 8144 q6prm: service@2 { 8145 compatible = "qcom,q6prm"; 8146 reg = <GPR_PRM_MODULE_IID>; 8147 qcom,protection-domain = "avs/audio", 8148 "msm/adsp/audio_pd"; 8149 8150 q6prmcc: clock-controller { 8151 compatible = "qcom,q6prm-lpass-clocks"; 8152 #clock-cells = <2>; 8153 }; 8154 }; 8155 }; 8156 }; 8157 }; 8158 }; 8159 8160 thermal-zones { 8161 aoss-0-thermal { 8162 thermal-sensors = <&tsens0 0>; 8163 8164 trips { 8165 trip-point0 { 8166 temperature = <105000>; 8167 hysteresis = <5000>; 8168 type = "passive"; 8169 }; 8170 8171 trip-point1 { 8172 temperature = <115000>; 8173 hysteresis = <5000>; 8174 type = "passive"; 8175 }; 8176 }; 8177 }; 8178 8179 cpu-0-0-0-thermal { 8180 polling-delay-passive = <10>; 8181 8182 thermal-sensors = <&tsens0 1>; 8183 8184 trips { 8185 trip-point0 { 8186 temperature = <105000>; 8187 hysteresis = <5000>; 8188 type = "passive"; 8189 }; 8190 8191 trip-point1 { 8192 temperature = <115000>; 8193 hysteresis = <5000>; 8194 type = "passive"; 8195 }; 8196 }; 8197 }; 8198 8199 cpu-0-1-0-thermal { 8200 polling-delay-passive = <10>; 8201 8202 thermal-sensors = <&tsens0 2>; 8203 8204 trips { 8205 trip-point0 { 8206 temperature = <105000>; 8207 hysteresis = <5000>; 8208 type = "passive"; 8209 }; 8210 8211 trip-point1 { 8212 temperature = <115000>; 8213 hysteresis = <5000>; 8214 type = "passive"; 8215 }; 8216 }; 8217 }; 8218 8219 cpu-0-2-0-thermal { 8220 polling-delay-passive = <10>; 8221 8222 thermal-sensors = <&tsens0 3>; 8223 8224 trips { 8225 trip-point0 { 8226 temperature = <105000>; 8227 hysteresis = <5000>; 8228 type = "passive"; 8229 }; 8230 8231 trip-point1 { 8232 temperature = <115000>; 8233 hysteresis = <5000>; 8234 type = "passive"; 8235 }; 8236 }; 8237 }; 8238 8239 cpu-0-3-0-thermal { 8240 polling-delay-passive = <10>; 8241 8242 thermal-sensors = <&tsens0 4>; 8243 8244 trips { 8245 trip-point0 { 8246 temperature = <105000>; 8247 hysteresis = <5000>; 8248 type = "passive"; 8249 }; 8250 8251 trip-point1 { 8252 temperature = <115000>; 8253 hysteresis = <5000>; 8254 type = "passive"; 8255 }; 8256 }; 8257 }; 8258 8259 gpuss-0-thermal { 8260 polling-delay-passive = <10>; 8261 8262 thermal-sensors = <&tsens0 5>; 8263 8264 cooling-maps { 8265 map0 { 8266 trip = <&gpuss0_alert0>; 8267 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8268 }; 8269 }; 8270 8271 trips { 8272 gpuss0_alert0: trip-point0 { 8273 temperature = <105000>; 8274 hysteresis = <5000>; 8275 type = "passive"; 8276 }; 8277 8278 trip-point1 { 8279 temperature = <115000>; 8280 hysteresis = <5000>; 8281 type = "passive"; 8282 }; 8283 }; 8284 }; 8285 8286 gpuss-1-thermal { 8287 polling-delay-passive = <10>; 8288 8289 thermal-sensors = <&tsens0 6>; 8290 8291 cooling-maps { 8292 map0 { 8293 trip = <&gpuss1_alert0>; 8294 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8295 }; 8296 }; 8297 8298 trips { 8299 gpuss1_alert0: trip-point0 { 8300 temperature = <105000>; 8301 hysteresis = <5000>; 8302 type = "passive"; 8303 }; 8304 8305 trip-point1 { 8306 temperature = <115000>; 8307 hysteresis = <5000>; 8308 type = "passive"; 8309 }; 8310 }; 8311 }; 8312 8313 gpuss-2-thermal { 8314 polling-delay-passive = <10>; 8315 8316 thermal-sensors = <&tsens0 7>; 8317 8318 cooling-maps { 8319 map0 { 8320 trip = <&gpuss2_alert0>; 8321 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8322 }; 8323 }; 8324 8325 trips { 8326 gpuss2_alert0: trip-point0 { 8327 temperature = <105000>; 8328 hysteresis = <5000>; 8329 type = "passive"; 8330 }; 8331 8332 trip-point1 { 8333 temperature = <115000>; 8334 hysteresis = <5000>; 8335 type = "passive"; 8336 }; 8337 }; 8338 }; 8339 8340 audio-thermal { 8341 thermal-sensors = <&tsens0 8>; 8342 8343 trips { 8344 trip-point0 { 8345 temperature = <105000>; 8346 hysteresis = <5000>; 8347 type = "passive"; 8348 }; 8349 8350 trip-point1 { 8351 temperature = <115000>; 8352 hysteresis = <5000>; 8353 type = "passive"; 8354 }; 8355 }; 8356 }; 8357 8358 camss-0-thermal { 8359 thermal-sensors = <&tsens0 9>; 8360 8361 trips { 8362 trip-point0 { 8363 temperature = <105000>; 8364 hysteresis = <5000>; 8365 type = "passive"; 8366 }; 8367 8368 trip-point1 { 8369 temperature = <115000>; 8370 hysteresis = <5000>; 8371 type = "passive"; 8372 }; 8373 }; 8374 }; 8375 8376 pcie-0-thermal { 8377 thermal-sensors = <&tsens0 10>; 8378 8379 trips { 8380 trip-point0 { 8381 temperature = <105000>; 8382 hysteresis = <5000>; 8383 type = "passive"; 8384 }; 8385 8386 trip-point1 { 8387 temperature = <115000>; 8388 hysteresis = <5000>; 8389 type = "passive"; 8390 }; 8391 }; 8392 }; 8393 8394 cpuss-0-0-thermal { 8395 thermal-sensors = <&tsens0 11>; 8396 8397 trips { 8398 trip-point0 { 8399 temperature = <105000>; 8400 hysteresis = <5000>; 8401 type = "passive"; 8402 }; 8403 8404 trip-point1 { 8405 temperature = <115000>; 8406 hysteresis = <5000>; 8407 type = "passive"; 8408 }; 8409 }; 8410 }; 8411 8412 aoss-1-thermal { 8413 thermal-sensors = <&tsens1 0>; 8414 8415 trips { 8416 trip-point0 { 8417 temperature = <105000>; 8418 hysteresis = <5000>; 8419 type = "passive"; 8420 }; 8421 8422 trip-point1 { 8423 temperature = <115000>; 8424 hysteresis = <5000>; 8425 type = "passive"; 8426 }; 8427 }; 8428 }; 8429 8430 cpu-0-0-1-thermal { 8431 polling-delay-passive = <10>; 8432 8433 thermal-sensors = <&tsens1 1>; 8434 8435 trips { 8436 trip-point0 { 8437 temperature = <105000>; 8438 hysteresis = <5000>; 8439 type = "passive"; 8440 }; 8441 8442 trip-point1 { 8443 temperature = <115000>; 8444 hysteresis = <5000>; 8445 type = "passive"; 8446 }; 8447 }; 8448 }; 8449 8450 cpu-0-1-1-thermal { 8451 polling-delay-passive = <10>; 8452 8453 thermal-sensors = <&tsens1 2>; 8454 8455 trips { 8456 trip-point0 { 8457 temperature = <105000>; 8458 hysteresis = <5000>; 8459 type = "passive"; 8460 }; 8461 8462 trip-point1 { 8463 temperature = <115000>; 8464 hysteresis = <5000>; 8465 type = "passive"; 8466 }; 8467 }; 8468 }; 8469 8470 cpu-0-2-1-thermal { 8471 polling-delay-passive = <10>; 8472 8473 thermal-sensors = <&tsens1 3>; 8474 8475 trips { 8476 trip-point0 { 8477 temperature = <105000>; 8478 hysteresis = <5000>; 8479 type = "passive"; 8480 }; 8481 8482 trip-point1 { 8483 temperature = <115000>; 8484 hysteresis = <5000>; 8485 type = "passive"; 8486 }; 8487 }; 8488 }; 8489 8490 cpu-0-3-1-thermal { 8491 polling-delay-passive = <10>; 8492 8493 thermal-sensors = <&tsens1 4>; 8494 8495 trips { 8496 trip-point0 { 8497 temperature = <105000>; 8498 hysteresis = <5000>; 8499 type = "passive"; 8500 }; 8501 8502 trip-point1 { 8503 temperature = <115000>; 8504 hysteresis = <5000>; 8505 type = "passive"; 8506 }; 8507 }; 8508 }; 8509 8510 gpuss-3-thermal { 8511 polling-delay-passive = <10>; 8512 8513 thermal-sensors = <&tsens1 5>; 8514 8515 cooling-maps { 8516 map0 { 8517 trip = <&gpuss3_alert0>; 8518 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8519 }; 8520 }; 8521 8522 trips { 8523 gpuss3_alert0: trip-point0 { 8524 temperature = <105000>; 8525 hysteresis = <5000>; 8526 type = "passive"; 8527 }; 8528 8529 trip-point1 { 8530 temperature = <115000>; 8531 hysteresis = <5000>; 8532 type = "passive"; 8533 }; 8534 }; 8535 }; 8536 8537 gpuss-4-thermal { 8538 polling-delay-passive = <10>; 8539 8540 thermal-sensors = <&tsens1 6>; 8541 8542 cooling-maps { 8543 map0 { 8544 trip = <&gpuss4_alert0>; 8545 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8546 }; 8547 }; 8548 8549 trips { 8550 gpuss4_alert0: trip-point0 { 8551 temperature = <105000>; 8552 hysteresis = <5000>; 8553 type = "passive"; 8554 }; 8555 8556 trip-point1 { 8557 temperature = <115000>; 8558 hysteresis = <5000>; 8559 type = "passive"; 8560 }; 8561 }; 8562 }; 8563 8564 gpuss-5-thermal { 8565 polling-delay-passive = <10>; 8566 8567 thermal-sensors = <&tsens1 7>; 8568 8569 cooling-maps { 8570 map0 { 8571 trip = <&gpuss5_alert0>; 8572 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8573 }; 8574 }; 8575 8576 trips { 8577 gpuss5_alert0: trip-point0 { 8578 temperature = <105000>; 8579 hysteresis = <5000>; 8580 type = "passive"; 8581 }; 8582 8583 trip-point1 { 8584 temperature = <115000>; 8585 hysteresis = <5000>; 8586 type = "passive"; 8587 }; 8588 }; 8589 }; 8590 8591 video-thermal { 8592 thermal-sensors = <&tsens1 8>; 8593 8594 trips { 8595 trip-point0 { 8596 temperature = <105000>; 8597 hysteresis = <5000>; 8598 type = "passive"; 8599 }; 8600 8601 trip-point1 { 8602 temperature = <115000>; 8603 hysteresis = <5000>; 8604 type = "passive"; 8605 }; 8606 }; 8607 }; 8608 8609 camss-1-thermal { 8610 thermal-sensors = <&tsens1 9>; 8611 8612 trips { 8613 trip-point0 { 8614 temperature = <105000>; 8615 hysteresis = <5000>; 8616 type = "passive"; 8617 }; 8618 8619 trip-point1 { 8620 temperature = <115000>; 8621 hysteresis = <5000>; 8622 type = "passive"; 8623 }; 8624 }; 8625 }; 8626 8627 pcie-1-thermal { 8628 thermal-sensors = <&tsens1 10>; 8629 8630 trips { 8631 trip-point0 { 8632 temperature = <105000>; 8633 hysteresis = <5000>; 8634 type = "passive"; 8635 }; 8636 8637 trip-point1 { 8638 temperature = <115000>; 8639 hysteresis = <5000>; 8640 type = "passive"; 8641 }; 8642 }; 8643 }; 8644 8645 cpuss-0-1-thermal { 8646 thermal-sensors = <&tsens1 11>; 8647 8648 trips { 8649 trip-point0 { 8650 temperature = <105000>; 8651 hysteresis = <5000>; 8652 type = "passive"; 8653 }; 8654 8655 trip-point1 { 8656 temperature = <115000>; 8657 hysteresis = <5000>; 8658 type = "passive"; 8659 }; 8660 }; 8661 }; 8662 8663 aoss-2-thermal { 8664 thermal-sensors = <&tsens2 0>; 8665 8666 trips { 8667 trip-point0 { 8668 temperature = <105000>; 8669 hysteresis = <5000>; 8670 type = "passive"; 8671 }; 8672 8673 trip-point1 { 8674 temperature = <115000>; 8675 hysteresis = <5000>; 8676 type = "passive"; 8677 }; 8678 }; 8679 }; 8680 8681 cpu-1-0-0-thermal { 8682 polling-delay-passive = <10>; 8683 8684 thermal-sensors = <&tsens2 1>; 8685 8686 trips { 8687 trip-point0 { 8688 temperature = <105000>; 8689 hysteresis = <5000>; 8690 type = "passive"; 8691 }; 8692 8693 trip-point1 { 8694 temperature = <115000>; 8695 hysteresis = <5000>; 8696 type = "passive"; 8697 }; 8698 }; 8699 }; 8700 8701 cpu-1-1-0-thermal { 8702 polling-delay-passive = <10>; 8703 8704 thermal-sensors = <&tsens2 2>; 8705 8706 trips { 8707 trip-point0 { 8708 temperature = <105000>; 8709 hysteresis = <5000>; 8710 type = "passive"; 8711 }; 8712 8713 trip-point1 { 8714 temperature = <115000>; 8715 hysteresis = <5000>; 8716 type = "passive"; 8717 }; 8718 }; 8719 }; 8720 8721 cpu-1-2-0-thermal { 8722 polling-delay-passive = <10>; 8723 8724 thermal-sensors = <&tsens2 3>; 8725 8726 trips { 8727 trip-point0 { 8728 temperature = <105000>; 8729 hysteresis = <5000>; 8730 type = "passive"; 8731 }; 8732 8733 trip-point1 { 8734 temperature = <115000>; 8735 hysteresis = <5000>; 8736 type = "passive"; 8737 }; 8738 }; 8739 }; 8740 8741 cpu-1-3-0-thermal { 8742 polling-delay-passive = <10>; 8743 8744 thermal-sensors = <&tsens2 4>; 8745 8746 trips { 8747 trip-point0 { 8748 temperature = <105000>; 8749 hysteresis = <5000>; 8750 type = "passive"; 8751 }; 8752 8753 trip-point1 { 8754 temperature = <115000>; 8755 hysteresis = <5000>; 8756 type = "passive"; 8757 }; 8758 }; 8759 }; 8760 8761 nsp-0-0-0-thermal { 8762 polling-delay-passive = <10>; 8763 8764 thermal-sensors = <&tsens2 5>; 8765 8766 trips { 8767 trip-point0 { 8768 temperature = <105000>; 8769 hysteresis = <5000>; 8770 type = "passive"; 8771 }; 8772 8773 trip-point1 { 8774 temperature = <115000>; 8775 hysteresis = <5000>; 8776 type = "passive"; 8777 }; 8778 }; 8779 }; 8780 8781 nsp-0-1-0-thermal { 8782 polling-delay-passive = <10>; 8783 8784 thermal-sensors = <&tsens2 6>; 8785 8786 trips { 8787 trip-point0 { 8788 temperature = <105000>; 8789 hysteresis = <5000>; 8790 type = "passive"; 8791 }; 8792 8793 trip-point1 { 8794 temperature = <115000>; 8795 hysteresis = <5000>; 8796 type = "passive"; 8797 }; 8798 }; 8799 }; 8800 8801 nsp-0-2-0-thermal { 8802 polling-delay-passive = <10>; 8803 8804 thermal-sensors = <&tsens2 7>; 8805 8806 trips { 8807 trip-point0 { 8808 temperature = <105000>; 8809 hysteresis = <5000>; 8810 type = "passive"; 8811 }; 8812 8813 trip-point1 { 8814 temperature = <115000>; 8815 hysteresis = <5000>; 8816 type = "passive"; 8817 }; 8818 }; 8819 }; 8820 8821 nsp-1-0-0-thermal { 8822 polling-delay-passive = <10>; 8823 8824 thermal-sensors = <&tsens2 8>; 8825 8826 trips { 8827 trip-point0 { 8828 temperature = <105000>; 8829 hysteresis = <5000>; 8830 type = "passive"; 8831 }; 8832 8833 trip-point1 { 8834 temperature = <115000>; 8835 hysteresis = <5000>; 8836 type = "passive"; 8837 }; 8838 }; 8839 }; 8840 8841 nsp-1-1-0-thermal { 8842 polling-delay-passive = <10>; 8843 8844 thermal-sensors = <&tsens2 9>; 8845 8846 trips { 8847 trip-point0 { 8848 temperature = <105000>; 8849 hysteresis = <5000>; 8850 type = "passive"; 8851 }; 8852 8853 trip-point1 { 8854 temperature = <115000>; 8855 hysteresis = <5000>; 8856 type = "passive"; 8857 }; 8858 }; 8859 }; 8860 8861 nsp-1-2-0-thermal { 8862 polling-delay-passive = <10>; 8863 8864 thermal-sensors = <&tsens2 10>; 8865 8866 trips { 8867 trip-point0 { 8868 temperature = <105000>; 8869 hysteresis = <5000>; 8870 type = "passive"; 8871 }; 8872 8873 trip-point1 { 8874 temperature = <115000>; 8875 hysteresis = <5000>; 8876 type = "passive"; 8877 }; 8878 }; 8879 }; 8880 8881 ddrss-0-thermal { 8882 thermal-sensors = <&tsens2 11>; 8883 8884 trips { 8885 trip-point0 { 8886 temperature = <105000>; 8887 hysteresis = <5000>; 8888 type = "passive"; 8889 }; 8890 8891 trip-point1 { 8892 temperature = <115000>; 8893 hysteresis = <5000>; 8894 type = "passive"; 8895 }; 8896 }; 8897 }; 8898 8899 cpuss-1-0-thermal { 8900 thermal-sensors = <&tsens2 12>; 8901 8902 trips { 8903 trip-point0 { 8904 temperature = <105000>; 8905 hysteresis = <5000>; 8906 type = "passive"; 8907 }; 8908 8909 trip-point1 { 8910 temperature = <115000>; 8911 hysteresis = <5000>; 8912 type = "passive"; 8913 }; 8914 }; 8915 }; 8916 8917 aoss-3-thermal { 8918 thermal-sensors = <&tsens3 0>; 8919 8920 trips { 8921 trip-point0 { 8922 temperature = <105000>; 8923 hysteresis = <5000>; 8924 type = "passive"; 8925 }; 8926 8927 trip-point1 { 8928 temperature = <115000>; 8929 hysteresis = <5000>; 8930 type = "passive"; 8931 }; 8932 }; 8933 }; 8934 8935 cpu-1-0-1-thermal { 8936 polling-delay-passive = <10>; 8937 8938 thermal-sensors = <&tsens3 1>; 8939 8940 trips { 8941 trip-point0 { 8942 temperature = <105000>; 8943 hysteresis = <5000>; 8944 type = "passive"; 8945 }; 8946 8947 trip-point1 { 8948 temperature = <115000>; 8949 hysteresis = <5000>; 8950 type = "passive"; 8951 }; 8952 }; 8953 }; 8954 8955 cpu-1-1-1-thermal { 8956 polling-delay-passive = <10>; 8957 8958 thermal-sensors = <&tsens3 2>; 8959 8960 trips { 8961 trip-point0 { 8962 temperature = <105000>; 8963 hysteresis = <5000>; 8964 type = "passive"; 8965 }; 8966 8967 trip-point1 { 8968 temperature = <115000>; 8969 hysteresis = <5000>; 8970 type = "passive"; 8971 }; 8972 }; 8973 }; 8974 8975 cpu-1-2-1-thermal { 8976 polling-delay-passive = <10>; 8977 8978 thermal-sensors = <&tsens3 3>; 8979 8980 trips { 8981 trip-point0 { 8982 temperature = <105000>; 8983 hysteresis = <5000>; 8984 type = "passive"; 8985 }; 8986 8987 trip-point1 { 8988 temperature = <115000>; 8989 hysteresis = <5000>; 8990 type = "passive"; 8991 }; 8992 }; 8993 }; 8994 8995 cpu-1-3-1-thermal { 8996 polling-delay-passive = <10>; 8997 8998 thermal-sensors = <&tsens3 4>; 8999 9000 trips { 9001 trip-point0 { 9002 temperature = <105000>; 9003 hysteresis = <5000>; 9004 type = "passive"; 9005 }; 9006 9007 trip-point1 { 9008 temperature = <115000>; 9009 hysteresis = <5000>; 9010 type = "passive"; 9011 }; 9012 }; 9013 }; 9014 9015 nsp-0-0-1-thermal { 9016 polling-delay-passive = <10>; 9017 9018 thermal-sensors = <&tsens3 5>; 9019 9020 trips { 9021 trip-point0 { 9022 temperature = <105000>; 9023 hysteresis = <5000>; 9024 type = "passive"; 9025 }; 9026 9027 trip-point1 { 9028 temperature = <115000>; 9029 hysteresis = <5000>; 9030 type = "passive"; 9031 }; 9032 }; 9033 }; 9034 9035 nsp-0-1-1-thermal { 9036 polling-delay-passive = <10>; 9037 9038 thermal-sensors = <&tsens3 6>; 9039 9040 trips { 9041 trip-point0 { 9042 temperature = <105000>; 9043 hysteresis = <5000>; 9044 type = "passive"; 9045 }; 9046 9047 trip-point1 { 9048 temperature = <115000>; 9049 hysteresis = <5000>; 9050 type = "passive"; 9051 }; 9052 }; 9053 }; 9054 9055 nsp-0-2-1-thermal { 9056 polling-delay-passive = <10>; 9057 9058 thermal-sensors = <&tsens3 7>; 9059 9060 trips { 9061 trip-point0 { 9062 temperature = <105000>; 9063 hysteresis = <5000>; 9064 type = "passive"; 9065 }; 9066 9067 trip-point1 { 9068 temperature = <115000>; 9069 hysteresis = <5000>; 9070 type = "passive"; 9071 }; 9072 }; 9073 }; 9074 9075 nsp-1-0-1-thermal { 9076 polling-delay-passive = <10>; 9077 9078 thermal-sensors = <&tsens3 8>; 9079 9080 trips { 9081 trip-point0 { 9082 temperature = <105000>; 9083 hysteresis = <5000>; 9084 type = "passive"; 9085 }; 9086 9087 trip-point1 { 9088 temperature = <115000>; 9089 hysteresis = <5000>; 9090 type = "passive"; 9091 }; 9092 }; 9093 }; 9094 9095 nsp-1-1-1-thermal { 9096 polling-delay-passive = <10>; 9097 9098 thermal-sensors = <&tsens3 9>; 9099 9100 trips { 9101 trip-point0 { 9102 temperature = <105000>; 9103 hysteresis = <5000>; 9104 type = "passive"; 9105 }; 9106 9107 trip-point1 { 9108 temperature = <115000>; 9109 hysteresis = <5000>; 9110 type = "passive"; 9111 }; 9112 }; 9113 }; 9114 9115 nsp-1-2-1-thermal { 9116 polling-delay-passive = <10>; 9117 9118 thermal-sensors = <&tsens3 10>; 9119 9120 trips { 9121 trip-point0 { 9122 temperature = <105000>; 9123 hysteresis = <5000>; 9124 type = "passive"; 9125 }; 9126 9127 trip-point1 { 9128 temperature = <115000>; 9129 hysteresis = <5000>; 9130 type = "passive"; 9131 }; 9132 }; 9133 }; 9134 9135 ddrss-1-thermal { 9136 thermal-sensors = <&tsens3 11>; 9137 9138 trips { 9139 trip-point0 { 9140 temperature = <105000>; 9141 hysteresis = <5000>; 9142 type = "passive"; 9143 }; 9144 9145 trip-point1 { 9146 temperature = <115000>; 9147 hysteresis = <5000>; 9148 type = "passive"; 9149 }; 9150 }; 9151 }; 9152 9153 cpuss-1-1-thermal { 9154 thermal-sensors = <&tsens3 12>; 9155 9156 trips { 9157 trip-point0 { 9158 temperature = <105000>; 9159 hysteresis = <5000>; 9160 type = "passive"; 9161 }; 9162 9163 trip-point1 { 9164 temperature = <115000>; 9165 hysteresis = <5000>; 9166 type = "passive"; 9167 }; 9168 }; 9169 }; 9170 }; 9171 9172 arch_timer: timer { 9173 compatible = "arm,armv8-timer"; 9174 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 9175 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 9176 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 9177 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 9178 }; 9179 9180 turing-llm-tpdm { 9181 compatible = "qcom,coresight-static-tpdm"; 9182 9183 qcom,cmb-element-bits = <32>; 9184 9185 out-ports { 9186 port { 9187 turing_llm_tpdm_out: endpoint { 9188 remote-endpoint = <&turing0_funnel_in1>; 9189 }; 9190 }; 9191 }; 9192 }; 9193}; 9194