1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#include <dt-bindings/interconnect/qcom,icc.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 12#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 13#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 14#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 15#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/firmware/qcom,scm.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 clocks { 32 xo_board_clk: xo-board-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo"; 50 reg = <0x0 0x0>; 51 enable-method = "psci"; 52 power-domains = <&cpu_pd0>; 53 power-domain-names = "psci"; 54 qcom,freq-domain = <&cpufreq_hw 0>; 55 next-level-cache = <&l2_0>; 56 capacity-dmips-mhz = <1024>; 57 dynamic-power-coefficient = <100>; 58 operating-points-v2 = <&cpu0_opp_table>; 59 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 60 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 61 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 62 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 63 l2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&l3_0>; 68 l3_0: l3-cache { 69 compatible = "cache"; 70 cache-level = <3>; 71 cache-unified; 72 }; 73 }; 74 }; 75 76 cpu1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "qcom,kryo"; 79 reg = <0x0 0x100>; 80 enable-method = "psci"; 81 power-domains = <&cpu_pd1>; 82 power-domain-names = "psci"; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 next-level-cache = <&l2_1>; 85 capacity-dmips-mhz = <1024>; 86 dynamic-power-coefficient = <100>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 89 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 90 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 91 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 92 l2_1: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 next-level-cache = <&l3_0>; 97 }; 98 }; 99 100 cpu2: cpu@200 { 101 device_type = "cpu"; 102 compatible = "qcom,kryo"; 103 reg = <0x0 0x200>; 104 enable-method = "psci"; 105 power-domains = <&cpu_pd2>; 106 power-domain-names = "psci"; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 next-level-cache = <&l2_2>; 109 capacity-dmips-mhz = <1024>; 110 dynamic-power-coefficient = <100>; 111 operating-points-v2 = <&cpu0_opp_table>; 112 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 113 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 114 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 115 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 116 l2_2: l2-cache { 117 compatible = "cache"; 118 cache-level = <2>; 119 cache-unified; 120 next-level-cache = <&l3_0>; 121 }; 122 }; 123 124 cpu3: cpu@300 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo"; 127 reg = <0x0 0x300>; 128 enable-method = "psci"; 129 power-domains = <&cpu_pd3>; 130 power-domain-names = "psci"; 131 qcom,freq-domain = <&cpufreq_hw 0>; 132 next-level-cache = <&l2_3>; 133 capacity-dmips-mhz = <1024>; 134 dynamic-power-coefficient = <100>; 135 operating-points-v2 = <&cpu0_opp_table>; 136 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 137 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 138 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 139 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 140 l2_3: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 cache-unified; 144 next-level-cache = <&l3_0>; 145 }; 146 }; 147 148 cpu4: cpu@10000 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo"; 151 reg = <0x0 0x10000>; 152 enable-method = "psci"; 153 power-domains = <&cpu_pd4>; 154 power-domain-names = "psci"; 155 qcom,freq-domain = <&cpufreq_hw 1>; 156 next-level-cache = <&l2_4>; 157 capacity-dmips-mhz = <1024>; 158 dynamic-power-coefficient = <100>; 159 operating-points-v2 = <&cpu4_opp_table>; 160 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 161 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 162 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 163 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 164 l2_4: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&l3_1>; 169 l3_1: l3-cache { 170 compatible = "cache"; 171 cache-level = <3>; 172 cache-unified; 173 }; 174 175 }; 176 }; 177 178 cpu5: cpu@10100 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo"; 181 reg = <0x0 0x10100>; 182 enable-method = "psci"; 183 power-domains = <&cpu_pd5>; 184 power-domain-names = "psci"; 185 qcom,freq-domain = <&cpufreq_hw 1>; 186 next-level-cache = <&l2_5>; 187 capacity-dmips-mhz = <1024>; 188 dynamic-power-coefficient = <100>; 189 operating-points-v2 = <&cpu4_opp_table>; 190 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 191 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 192 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 193 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 194 l2_5: l2-cache { 195 compatible = "cache"; 196 cache-level = <2>; 197 cache-unified; 198 next-level-cache = <&l3_1>; 199 }; 200 }; 201 202 cpu6: cpu@10200 { 203 device_type = "cpu"; 204 compatible = "qcom,kryo"; 205 reg = <0x0 0x10200>; 206 enable-method = "psci"; 207 power-domains = <&cpu_pd6>; 208 power-domain-names = "psci"; 209 qcom,freq-domain = <&cpufreq_hw 1>; 210 next-level-cache = <&l2_6>; 211 capacity-dmips-mhz = <1024>; 212 dynamic-power-coefficient = <100>; 213 operating-points-v2 = <&cpu4_opp_table>; 214 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 215 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 216 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 217 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 218 l2_6: l2-cache { 219 compatible = "cache"; 220 cache-level = <2>; 221 cache-unified; 222 next-level-cache = <&l3_1>; 223 }; 224 }; 225 226 cpu7: cpu@10300 { 227 device_type = "cpu"; 228 compatible = "qcom,kryo"; 229 reg = <0x0 0x10300>; 230 enable-method = "psci"; 231 power-domains = <&cpu_pd7>; 232 power-domain-names = "psci"; 233 qcom,freq-domain = <&cpufreq_hw 1>; 234 next-level-cache = <&l2_7>; 235 capacity-dmips-mhz = <1024>; 236 dynamic-power-coefficient = <100>; 237 operating-points-v2 = <&cpu4_opp_table>; 238 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 239 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 240 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 241 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 242 l2_7: l2-cache { 243 compatible = "cache"; 244 cache-level = <2>; 245 cache-unified; 246 next-level-cache = <&l3_1>; 247 }; 248 }; 249 250 cpu-map { 251 cluster0 { 252 core0 { 253 cpu = <&cpu0>; 254 }; 255 256 core1 { 257 cpu = <&cpu1>; 258 }; 259 260 core2 { 261 cpu = <&cpu2>; 262 }; 263 264 core3 { 265 cpu = <&cpu3>; 266 }; 267 }; 268 269 cluster1 { 270 core0 { 271 cpu = <&cpu4>; 272 }; 273 274 core1 { 275 cpu = <&cpu5>; 276 }; 277 278 core2 { 279 cpu = <&cpu6>; 280 }; 281 282 core3 { 283 cpu = <&cpu7>; 284 }; 285 }; 286 }; 287 288 idle-states { 289 entry-method = "psci"; 290 291 gold_cpu_sleep_0: cpu-sleep-0 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "gold-power-collapse"; 294 arm,psci-suspend-param = <0x40000003>; 295 entry-latency-us = <549>; 296 exit-latency-us = <901>; 297 min-residency-us = <1774>; 298 local-timer-stop; 299 }; 300 301 gold_rail_cpu_sleep_0: cpu-sleep-1 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "gold-rail-power-collapse"; 304 arm,psci-suspend-param = <0x40000004>; 305 entry-latency-us = <702>; 306 exit-latency-us = <1061>; 307 min-residency-us = <4488>; 308 local-timer-stop; 309 }; 310 }; 311 312 domain-idle-states { 313 cluster_sleep_gold: cluster-sleep-0 { 314 compatible = "domain-idle-state"; 315 arm,psci-suspend-param = <0x41000044>; 316 entry-latency-us = <2752>; 317 exit-latency-us = <3048>; 318 min-residency-us = <6118>; 319 }; 320 321 cluster_sleep_apss_rsc_pc: cluster-sleep-1 { 322 compatible = "domain-idle-state"; 323 arm,psci-suspend-param = <0x42000144>; 324 entry-latency-us = <3263>; 325 exit-latency-us = <6562>; 326 min-residency-us = <9987>; 327 }; 328 }; 329 }; 330 331 cpu0_opp_table: opp-table-cpu0 { 332 compatible = "operating-points-v2"; 333 opp-shared; 334 335 opp-1267200000 { 336 opp-hz = /bits/ 64 <1267200000>; 337 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 338 }; 339 340 opp-1363200000 { 341 opp-hz = /bits/ 64 <1363200000>; 342 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 343 }; 344 345 opp-1459200000 { 346 opp-hz = /bits/ 64 <1459200000>; 347 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 348 }; 349 350 opp-1536000000 { 351 opp-hz = /bits/ 64 <1536000000>; 352 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 353 }; 354 355 opp-1632000000 { 356 opp-hz = /bits/ 64 <1632000000>; 357 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 358 }; 359 360 opp-1708800000 { 361 opp-hz = /bits/ 64 <1708800000>; 362 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 363 }; 364 365 opp-1785600000 { 366 opp-hz = /bits/ 64 <1785600000>; 367 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 368 }; 369 370 opp-1862400000 { 371 opp-hz = /bits/ 64 <1862400000>; 372 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 373 }; 374 375 opp-1939200000 { 376 opp-hz = /bits/ 64 <1939200000>; 377 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 378 }; 379 380 opp-2016000000 { 381 opp-hz = /bits/ 64 <2016000000>; 382 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 383 }; 384 385 opp-2112000000 { 386 opp-hz = /bits/ 64 <2112000000>; 387 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 388 }; 389 390 opp-2188800000 { 391 opp-hz = /bits/ 64 <2188800000>; 392 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 393 }; 394 395 opp-2265600000 { 396 opp-hz = /bits/ 64 <2265600000>; 397 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 398 }; 399 400 opp-2361600000 { 401 opp-hz = /bits/ 64 <2361600000>; 402 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 403 }; 404 405 opp-2457600000 { 406 opp-hz = /bits/ 64 <2457600000>; 407 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 408 }; 409 410 opp-2553600000 { 411 opp-hz = /bits/ 64 <2553600000>; 412 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 413 }; 414 }; 415 416 cpu4_opp_table: opp-table-cpu4 { 417 compatible = "operating-points-v2"; 418 opp-shared; 419 420 opp-1267200000 { 421 opp-hz = /bits/ 64 <1267200000>; 422 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 423 }; 424 425 opp-1363200000 { 426 opp-hz = /bits/ 64 <1363200000>; 427 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 428 }; 429 430 opp-1459200000 { 431 opp-hz = /bits/ 64 <1459200000>; 432 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 433 }; 434 435 opp-1536000000 { 436 opp-hz = /bits/ 64 <1536000000>; 437 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 438 }; 439 440 opp-1632000000 { 441 opp-hz = /bits/ 64 <1632000000>; 442 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 443 }; 444 445 opp-1708800000 { 446 opp-hz = /bits/ 64 <1708800000>; 447 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 448 }; 449 450 opp-1785600000 { 451 opp-hz = /bits/ 64 <1785600000>; 452 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 453 }; 454 455 opp-1862400000 { 456 opp-hz = /bits/ 64 <1862400000>; 457 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 458 }; 459 460 opp-1939200000 { 461 opp-hz = /bits/ 64 <1939200000>; 462 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 463 }; 464 465 opp-2016000000 { 466 opp-hz = /bits/ 64 <2016000000>; 467 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 468 }; 469 470 opp-2112000000 { 471 opp-hz = /bits/ 64 <2112000000>; 472 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 473 }; 474 475 opp-2188800000 { 476 opp-hz = /bits/ 64 <2188800000>; 477 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 478 }; 479 480 opp-2265600000 { 481 opp-hz = /bits/ 64 <2265600000>; 482 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 483 }; 484 485 opp-2361600000 { 486 opp-hz = /bits/ 64 <2361600000>; 487 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 488 }; 489 490 opp-2457600000 { 491 opp-hz = /bits/ 64 <2457600000>; 492 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 493 }; 494 495 opp-2553600000 { 496 opp-hz = /bits/ 64 <2553600000>; 497 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 498 }; 499 }; 500 501 dummy-sink { 502 compatible = "arm,coresight-dummy-sink"; 503 504 in-ports { 505 port { 506 eud_in: endpoint { 507 remote-endpoint = 508 <&swao_rep_out1>; 509 }; 510 }; 511 }; 512 }; 513 514 firmware { 515 scm { 516 compatible = "qcom,scm-sa8775p", "qcom,scm"; 517 qcom,dload-mode = <&tcsr 0x13000>; 518 }; 519 }; 520 521 aggre1_noc: interconnect-aggre1-noc { 522 compatible = "qcom,sa8775p-aggre1-noc"; 523 #interconnect-cells = <2>; 524 qcom,bcm-voters = <&apps_bcm_voter>; 525 }; 526 527 aggre2_noc: interconnect-aggre2-noc { 528 compatible = "qcom,sa8775p-aggre2-noc"; 529 #interconnect-cells = <2>; 530 qcom,bcm-voters = <&apps_bcm_voter>; 531 }; 532 533 clk_virt: interconnect-clk-virt { 534 compatible = "qcom,sa8775p-clk-virt"; 535 #interconnect-cells = <2>; 536 qcom,bcm-voters = <&apps_bcm_voter>; 537 }; 538 539 config_noc: interconnect-config-noc { 540 compatible = "qcom,sa8775p-config-noc"; 541 #interconnect-cells = <2>; 542 qcom,bcm-voters = <&apps_bcm_voter>; 543 }; 544 545 dc_noc: interconnect-dc-noc { 546 compatible = "qcom,sa8775p-dc-noc"; 547 #interconnect-cells = <2>; 548 qcom,bcm-voters = <&apps_bcm_voter>; 549 }; 550 551 gem_noc: interconnect-gem-noc { 552 compatible = "qcom,sa8775p-gem-noc"; 553 #interconnect-cells = <2>; 554 qcom,bcm-voters = <&apps_bcm_voter>; 555 }; 556 557 gpdsp_anoc: interconnect-gpdsp-anoc { 558 compatible = "qcom,sa8775p-gpdsp-anoc"; 559 #interconnect-cells = <2>; 560 qcom,bcm-voters = <&apps_bcm_voter>; 561 }; 562 563 lpass_ag_noc: interconnect-lpass-ag-noc { 564 compatible = "qcom,sa8775p-lpass-ag-noc"; 565 #interconnect-cells = <2>; 566 qcom,bcm-voters = <&apps_bcm_voter>; 567 }; 568 569 mc_virt: interconnect-mc-virt { 570 compatible = "qcom,sa8775p-mc-virt"; 571 #interconnect-cells = <2>; 572 qcom,bcm-voters = <&apps_bcm_voter>; 573 }; 574 575 mmss_noc: interconnect-mmss-noc { 576 compatible = "qcom,sa8775p-mmss-noc"; 577 #interconnect-cells = <2>; 578 qcom,bcm-voters = <&apps_bcm_voter>; 579 }; 580 581 nspa_noc: interconnect-nspa-noc { 582 compatible = "qcom,sa8775p-nspa-noc"; 583 #interconnect-cells = <2>; 584 qcom,bcm-voters = <&apps_bcm_voter>; 585 }; 586 587 nspb_noc: interconnect-nspb-noc { 588 compatible = "qcom,sa8775p-nspb-noc"; 589 #interconnect-cells = <2>; 590 qcom,bcm-voters = <&apps_bcm_voter>; 591 }; 592 593 pcie_anoc: interconnect-pcie-anoc { 594 compatible = "qcom,sa8775p-pcie-anoc"; 595 #interconnect-cells = <2>; 596 qcom,bcm-voters = <&apps_bcm_voter>; 597 }; 598 599 system_noc: interconnect-system-noc { 600 compatible = "qcom,sa8775p-system-noc"; 601 #interconnect-cells = <2>; 602 qcom,bcm-voters = <&apps_bcm_voter>; 603 }; 604 605 /* Will be updated by the bootloader. */ 606 memory@80000000 { 607 device_type = "memory"; 608 reg = <0x0 0x80000000 0x0 0x0>; 609 }; 610 611 qup_opp_table_100mhz: opp-table-qup100mhz { 612 compatible = "operating-points-v2"; 613 614 opp-100000000 { 615 opp-hz = /bits/ 64 <100000000>; 616 required-opps = <&rpmhpd_opp_svs_l1>; 617 }; 618 }; 619 620 pmu { 621 compatible = "arm,armv8-pmuv3"; 622 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 623 }; 624 625 psci { 626 compatible = "arm,psci-1.0"; 627 method = "smc"; 628 629 cpu_pd0: power-domain-cpu0 { 630 #power-domain-cells = <0>; 631 power-domains = <&cluster_0_pd>; 632 domain-idle-states = <&gold_cpu_sleep_0>, 633 <&gold_rail_cpu_sleep_0>; 634 }; 635 636 cpu_pd1: power-domain-cpu1 { 637 #power-domain-cells = <0>; 638 power-domains = <&cluster_0_pd>; 639 domain-idle-states = <&gold_cpu_sleep_0>, 640 <&gold_rail_cpu_sleep_0>; 641 }; 642 643 cpu_pd2: power-domain-cpu2 { 644 #power-domain-cells = <0>; 645 power-domains = <&cluster_0_pd>; 646 domain-idle-states = <&gold_cpu_sleep_0>, 647 <&gold_rail_cpu_sleep_0>; 648 }; 649 650 cpu_pd3: power-domain-cpu3 { 651 #power-domain-cells = <0>; 652 power-domains = <&cluster_0_pd>; 653 domain-idle-states = <&gold_cpu_sleep_0>, 654 <&gold_rail_cpu_sleep_0>; 655 }; 656 657 cpu_pd4: power-domain-cpu4 { 658 #power-domain-cells = <0>; 659 power-domains = <&cluster_1_pd>; 660 domain-idle-states = <&gold_cpu_sleep_0>, 661 <&gold_rail_cpu_sleep_0>; 662 }; 663 664 cpu_pd5: power-domain-cpu5 { 665 #power-domain-cells = <0>; 666 power-domains = <&cluster_1_pd>; 667 domain-idle-states = <&gold_cpu_sleep_0>, 668 <&gold_rail_cpu_sleep_0>; 669 }; 670 671 cpu_pd6: power-domain-cpu6 { 672 #power-domain-cells = <0>; 673 power-domains = <&cluster_1_pd>; 674 domain-idle-states = <&gold_cpu_sleep_0>, 675 <&gold_rail_cpu_sleep_0>; 676 }; 677 678 cpu_pd7: power-domain-cpu7 { 679 #power-domain-cells = <0>; 680 power-domains = <&cluster_1_pd>; 681 domain-idle-states = <&gold_cpu_sleep_0>, 682 <&gold_rail_cpu_sleep_0>; 683 }; 684 685 cluster_0_pd: power-domain-cluster0 { 686 #power-domain-cells = <0>; 687 domain-idle-states = <&cluster_sleep_gold>; 688 power-domains = <&system_pd>; 689 }; 690 691 cluster_1_pd: power-domain-cluster1 { 692 #power-domain-cells = <0>; 693 domain-idle-states = <&cluster_sleep_gold>; 694 power-domains = <&system_pd>; 695 }; 696 697 system_pd: power-domain-system { 698 #power-domain-cells = <0>; 699 domain-idle-states = <&cluster_sleep_apss_rsc_pc>; 700 }; 701 }; 702 703 reserved-memory { 704 #address-cells = <2>; 705 #size-cells = <2>; 706 ranges; 707 708 sail_ss_mem: sail-ss@80000000 { 709 reg = <0x0 0x80000000 0x0 0x10000000>; 710 no-map; 711 }; 712 713 hyp_mem: hyp@90000000 { 714 reg = <0x0 0x90000000 0x0 0x600000>; 715 no-map; 716 }; 717 718 xbl_boot_mem: xbl-boot@90600000 { 719 reg = <0x0 0x90600000 0x0 0x200000>; 720 no-map; 721 }; 722 723 aop_image_mem: aop-image@90800000 { 724 reg = <0x0 0x90800000 0x0 0x60000>; 725 no-map; 726 }; 727 728 aop_cmd_db_mem: aop-cmd-db@90860000 { 729 compatible = "qcom,cmd-db"; 730 reg = <0x0 0x90860000 0x0 0x20000>; 731 no-map; 732 }; 733 734 uefi_log: uefi-log@908b0000 { 735 reg = <0x0 0x908b0000 0x0 0x10000>; 736 no-map; 737 }; 738 739 ddr_training_checksum: ddr-training-checksum@908c0000 { 740 reg = <0x0 0x908c0000 0x0 0x1000>; 741 no-map; 742 }; 743 744 reserved_mem: reserved@908f0000 { 745 reg = <0x0 0x908f0000 0x0 0xe000>; 746 no-map; 747 }; 748 749 secdata_apss_mem: secdata-apss@908fe000 { 750 reg = <0x0 0x908fe000 0x0 0x2000>; 751 no-map; 752 }; 753 754 smem_mem: smem@90900000 { 755 compatible = "qcom,smem"; 756 reg = <0x0 0x90900000 0x0 0x200000>; 757 no-map; 758 hwlocks = <&tcsr_mutex 3>; 759 }; 760 761 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { 762 reg = <0x0 0x90c00000 0x0 0x100000>; 763 no-map; 764 }; 765 766 sail_mailbox_mem: sail-ss@90d00000 { 767 reg = <0x0 0x90d00000 0x0 0x100000>; 768 no-map; 769 }; 770 771 sail_ota_mem: sail-ss@90e00000 { 772 reg = <0x0 0x90e00000 0x0 0x300000>; 773 no-map; 774 }; 775 776 gunyah_md_mem: gunyah-md@91a80000 { 777 reg = <0x0 0x91a80000 0x0 0x80000>; 778 no-map; 779 }; 780 781 aoss_backup_mem: aoss-backup@91b00000 { 782 reg = <0x0 0x91b00000 0x0 0x40000>; 783 no-map; 784 }; 785 786 cpucp_backup_mem: cpucp-backup@91b40000 { 787 reg = <0x0 0x91b40000 0x0 0x40000>; 788 no-map; 789 }; 790 791 tz_config_backup_mem: tz-config-backup@91b80000 { 792 reg = <0x0 0x91b80000 0x0 0x10000>; 793 no-map; 794 }; 795 796 ddr_training_data_mem: ddr-training-data@91b90000 { 797 reg = <0x0 0x91b90000 0x0 0x10000>; 798 no-map; 799 }; 800 801 cdt_data_backup_mem: cdt-data-backup@91ba0000 { 802 reg = <0x0 0x91ba0000 0x0 0x1000>; 803 no-map; 804 }; 805 806 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 807 reg = <0x0 0x93b00000 0x0 0xf00000>; 808 no-map; 809 }; 810 811 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 812 reg = <0x0 0x94a00000 0x0 0x800000>; 813 no-map; 814 }; 815 816 pil_camera_mem: pil-camera@95200000 { 817 reg = <0x0 0x95200000 0x0 0x700000>; 818 no-map; 819 }; 820 821 pil_adsp_mem: pil-adsp@95900000 { 822 reg = <0x0 0x95900000 0x0 0x1e00000>; 823 no-map; 824 }; 825 826 q6_adsp_dtb_mem: q6-adsp-dtb@97700000 { 827 reg = <0x0 0x97700000 0x0 0x80000>; 828 no-map; 829 }; 830 831 q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 { 832 reg = <0x0 0x97780000 0x0 0x80000>; 833 no-map; 834 }; 835 836 pil_gdsp0_mem: pil-gdsp0@97800000 { 837 reg = <0x0 0x97800000 0x0 0x1e00000>; 838 no-map; 839 }; 840 841 pil_gdsp1_mem: pil-gdsp1@99600000 { 842 reg = <0x0 0x99600000 0x0 0x1e00000>; 843 no-map; 844 }; 845 846 q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 { 847 reg = <0x0 0x9b400000 0x0 0x80000>; 848 no-map; 849 }; 850 851 q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 { 852 reg = <0x0 0x9b480000 0x0 0x80000>; 853 no-map; 854 }; 855 856 pil_cdsp0_mem: pil-cdsp0@9b500000 { 857 reg = <0x0 0x9b500000 0x0 0x1e00000>; 858 no-map; 859 }; 860 861 pil_gpu_mem: pil-gpu@9d300000 { 862 reg = <0x0 0x9d300000 0x0 0x2000>; 863 no-map; 864 }; 865 866 q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 { 867 reg = <0x0 0x9d380000 0x0 0x80000>; 868 no-map; 869 }; 870 871 pil_cdsp1_mem: pil-cdsp1@9d400000 { 872 reg = <0x0 0x9d400000 0x0 0x1e00000>; 873 no-map; 874 }; 875 876 pil_cvp_mem: pil-cvp@9f200000 { 877 reg = <0x0 0x9f200000 0x0 0x700000>; 878 no-map; 879 }; 880 881 pil_video_mem: pil-video@9f900000 { 882 reg = <0x0 0x9f900000 0x0 0x1000000>; 883 no-map; 884 }; 885 886 firmware_mem: firmware-region@b0000000 { 887 reg = <0x0 0xb0000000 0x0 0x800000>; 888 no-map; 889 }; 890 891 scmi_mem: scmi-region@d0000000 { 892 reg = <0x0 0xd0000000 0x0 0x40000>; 893 no-map; 894 }; 895 896 firmware_logs_mem: firmware-logs@d0040000 { 897 reg = <0x0 0xd0040000 0x0 0x10000>; 898 no-map; 899 }; 900 901 firmware_audio_mem: firmware-audio@d0050000 { 902 reg = <0x0 0xd0050000 0x0 0x4000>; 903 no-map; 904 }; 905 906 firmware_reserved_mem: firmware-reserved@d0054000 { 907 reg = <0x0 0xd0054000 0x0 0x9c000>; 908 no-map; 909 }; 910 911 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { 912 reg = <0x0 0xd00f0000 0x0 0x10000>; 913 no-map; 914 }; 915 916 tags_mem: tags@d0100000 { 917 reg = <0x0 0xd0100000 0x0 0x1200000>; 918 no-map; 919 }; 920 921 qtee_mem: qtee@d1300000 { 922 reg = <0x0 0xd1300000 0x0 0x500000>; 923 no-map; 924 }; 925 926 deepsleep_backup_mem: deepsleep-backup@d1800000 { 927 reg = <0x0 0xd1800000 0x0 0x100000>; 928 no-map; 929 }; 930 931 trusted_apps_mem: trusted-apps@d1900000 { 932 reg = <0x0 0xd1900000 0x0 0x1c00000>; 933 no-map; 934 }; 935 936 tz_stat_mem: tz-stat@db100000 { 937 reg = <0x0 0xdb100000 0x0 0x100000>; 938 no-map; 939 }; 940 941 cpucp_fw_mem: cpucp-fw@db200000 { 942 reg = <0x0 0xdb200000 0x0 0x100000>; 943 no-map; 944 }; 945 }; 946 947 smp2p-adsp { 948 compatible = "qcom,smp2p"; 949 qcom,smem = <443>, <429>; 950 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 951 IPCC_MPROC_SIGNAL_SMP2P 952 IRQ_TYPE_EDGE_RISING>; 953 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 954 955 qcom,local-pid = <0>; 956 qcom,remote-pid = <2>; 957 958 smp2p_adsp_out: master-kernel { 959 qcom,entry-name = "master-kernel"; 960 #qcom,smem-state-cells = <1>; 961 }; 962 963 smp2p_adsp_in: slave-kernel { 964 qcom,entry-name = "slave-kernel"; 965 interrupt-controller; 966 #interrupt-cells = <2>; 967 }; 968 }; 969 970 smp2p-cdsp0 { 971 compatible = "qcom,smp2p"; 972 qcom,smem = <94>, <432>; 973 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 974 IPCC_MPROC_SIGNAL_SMP2P 975 IRQ_TYPE_EDGE_RISING>; 976 mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 977 978 qcom,local-pid = <0>; 979 qcom,remote-pid = <5>; 980 981 smp2p_cdsp0_out: master-kernel { 982 qcom,entry-name = "master-kernel"; 983 #qcom,smem-state-cells = <1>; 984 }; 985 986 smp2p_cdsp0_in: slave-kernel { 987 qcom,entry-name = "slave-kernel"; 988 interrupt-controller; 989 #interrupt-cells = <2>; 990 }; 991 }; 992 993 smp2p-cdsp1 { 994 compatible = "qcom,smp2p"; 995 qcom,smem = <617>, <616>; 996 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 997 IPCC_MPROC_SIGNAL_SMP2P 998 IRQ_TYPE_EDGE_RISING>; 999 mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; 1000 1001 qcom,local-pid = <0>; 1002 qcom,remote-pid = <12>; 1003 1004 smp2p_cdsp1_out: master-kernel { 1005 qcom,entry-name = "master-kernel"; 1006 #qcom,smem-state-cells = <1>; 1007 }; 1008 1009 smp2p_cdsp1_in: slave-kernel { 1010 qcom,entry-name = "slave-kernel"; 1011 interrupt-controller; 1012 #interrupt-cells = <2>; 1013 }; 1014 }; 1015 1016 smp2p-gpdsp0 { 1017 compatible = "qcom,smp2p"; 1018 qcom,smem = <617>, <616>; 1019 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 1020 IPCC_MPROC_SIGNAL_SMP2P 1021 IRQ_TYPE_EDGE_RISING>; 1022 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; 1023 1024 qcom,local-pid = <0>; 1025 qcom,remote-pid = <17>; 1026 1027 smp2p_gpdsp0_out: master-kernel { 1028 qcom,entry-name = "master-kernel"; 1029 #qcom,smem-state-cells = <1>; 1030 }; 1031 1032 smp2p_gpdsp0_in: slave-kernel { 1033 qcom,entry-name = "slave-kernel"; 1034 interrupt-controller; 1035 #interrupt-cells = <2>; 1036 }; 1037 }; 1038 1039 smp2p-gpdsp1 { 1040 compatible = "qcom,smp2p"; 1041 qcom,smem = <617>, <616>; 1042 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 1043 IPCC_MPROC_SIGNAL_SMP2P 1044 IRQ_TYPE_EDGE_RISING>; 1045 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>; 1046 1047 qcom,local-pid = <0>; 1048 qcom,remote-pid = <18>; 1049 1050 smp2p_gpdsp1_out: master-kernel { 1051 qcom,entry-name = "master-kernel"; 1052 #qcom,smem-state-cells = <1>; 1053 }; 1054 1055 smp2p_gpdsp1_in: slave-kernel { 1056 qcom,entry-name = "slave-kernel"; 1057 interrupt-controller; 1058 #interrupt-cells = <2>; 1059 }; 1060 }; 1061 1062 soc: soc@0 { 1063 compatible = "simple-bus"; 1064 #address-cells = <2>; 1065 #size-cells = <2>; 1066 ranges = <0 0 0 0 0x10 0>; 1067 1068 gcc: clock-controller@100000 { 1069 compatible = "qcom,sa8775p-gcc"; 1070 reg = <0x0 0x00100000 0x0 0xc7018>; 1071 #clock-cells = <1>; 1072 #reset-cells = <1>; 1073 #power-domain-cells = <1>; 1074 clocks = <&rpmhcc RPMH_CXO_CLK>, 1075 <&sleep_clk>, 1076 <0>, 1077 <0>, 1078 <0>, 1079 <&usb_0_qmpphy>, 1080 <&usb_1_qmpphy>, 1081 <0>, 1082 <0>, 1083 <0>, 1084 <&pcie0_phy>, 1085 <&pcie1_phy>, 1086 <0>, 1087 <0>, 1088 <0>; 1089 power-domains = <&rpmhpd SA8775P_CX>; 1090 }; 1091 1092 ipcc: mailbox@408000 { 1093 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 1094 reg = <0x0 0x00408000 0x0 0x1000>; 1095 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1096 interrupt-controller; 1097 #interrupt-cells = <3>; 1098 #mbox-cells = <2>; 1099 }; 1100 1101 gpi_dma2: dma-controller@800000 { 1102 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1103 reg = <0x0 0x00800000 0x0 0x60000>; 1104 #dma-cells = <3>; 1105 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1117 dma-channels = <12>; 1118 dma-channel-mask = <0xfff>; 1119 iommus = <&apps_smmu 0x5b6 0x0>; 1120 status = "disabled"; 1121 }; 1122 1123 qupv3_id_2: geniqup@8c0000 { 1124 compatible = "qcom,geni-se-qup"; 1125 reg = <0x0 0x008c0000 0x0 0x6000>; 1126 ranges; 1127 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1128 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1129 clock-names = "m-ahb", "s-ahb"; 1130 iommus = <&apps_smmu 0x5a3 0x0>; 1131 #address-cells = <2>; 1132 #size-cells = <2>; 1133 status = "disabled"; 1134 1135 i2c14: i2c@880000 { 1136 compatible = "qcom,geni-i2c"; 1137 reg = <0x0 0x880000 0x0 0x4000>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1141 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1142 clock-names = "se"; 1143 pinctrl-0 = <&qup_i2c14_default>; 1144 pinctrl-names = "default"; 1145 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1146 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1147 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1148 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1149 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1150 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1151 interconnect-names = "qup-core", 1152 "qup-config", 1153 "qup-memory"; 1154 power-domains = <&rpmhpd SA8775P_CX>; 1155 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1156 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1157 dma-names = "tx", 1158 "rx"; 1159 status = "disabled"; 1160 }; 1161 1162 spi14: spi@880000 { 1163 compatible = "qcom,geni-spi"; 1164 reg = <0x0 0x880000 0x0 0x4000>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1168 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1169 clock-names = "se"; 1170 pinctrl-0 = <&qup_spi14_default>; 1171 pinctrl-names = "default"; 1172 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1173 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1174 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1175 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1176 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1177 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1178 interconnect-names = "qup-core", 1179 "qup-config", 1180 "qup-memory"; 1181 power-domains = <&rpmhpd SA8775P_CX>; 1182 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1183 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1184 dma-names = "tx", 1185 "rx"; 1186 status = "disabled"; 1187 }; 1188 1189 uart14: serial@880000 { 1190 compatible = "qcom,geni-uart"; 1191 reg = <0x0 0x00880000 0x0 0x4000>; 1192 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1193 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1194 clock-names = "se"; 1195 pinctrl-0 = <&qup_uart14_default>; 1196 pinctrl-names = "default"; 1197 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1198 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1199 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1200 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1201 interconnect-names = "qup-core", "qup-config"; 1202 power-domains = <&rpmhpd SA8775P_CX>; 1203 status = "disabled"; 1204 }; 1205 1206 i2c15: i2c@884000 { 1207 compatible = "qcom,geni-i2c"; 1208 reg = <0x0 0x884000 0x0 0x4000>; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1213 clock-names = "se"; 1214 pinctrl-0 = <&qup_i2c15_default>; 1215 pinctrl-names = "default"; 1216 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1217 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1218 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1219 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1220 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1221 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1222 interconnect-names = "qup-core", 1223 "qup-config", 1224 "qup-memory"; 1225 power-domains = <&rpmhpd SA8775P_CX>; 1226 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1227 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1228 dma-names = "tx", 1229 "rx"; 1230 status = "disabled"; 1231 }; 1232 1233 spi15: spi@884000 { 1234 compatible = "qcom,geni-spi"; 1235 reg = <0x0 0x884000 0x0 0x4000>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1240 clock-names = "se"; 1241 pinctrl-0 = <&qup_spi15_default>; 1242 pinctrl-names = "default"; 1243 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1244 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1245 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1246 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1247 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1248 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1249 interconnect-names = "qup-core", 1250 "qup-config", 1251 "qup-memory"; 1252 power-domains = <&rpmhpd SA8775P_CX>; 1253 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1254 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1255 dma-names = "tx", 1256 "rx"; 1257 status = "disabled"; 1258 }; 1259 1260 uart15: serial@884000 { 1261 compatible = "qcom,geni-uart"; 1262 reg = <0x0 0x00884000 0x0 0x4000>; 1263 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1265 clock-names = "se"; 1266 pinctrl-0 = <&qup_uart15_default>; 1267 pinctrl-names = "default"; 1268 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1269 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1270 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1271 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1272 interconnect-names = "qup-core", "qup-config"; 1273 power-domains = <&rpmhpd SA8775P_CX>; 1274 status = "disabled"; 1275 }; 1276 1277 i2c16: i2c@888000 { 1278 compatible = "qcom,geni-i2c"; 1279 reg = <0x0 0x888000 0x0 0x4000>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1283 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1284 clock-names = "se"; 1285 pinctrl-0 = <&qup_i2c16_default>; 1286 pinctrl-names = "default"; 1287 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1288 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1289 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1290 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1291 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1292 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1293 interconnect-names = "qup-core", 1294 "qup-config", 1295 "qup-memory"; 1296 power-domains = <&rpmhpd SA8775P_CX>; 1297 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1298 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1299 dma-names = "tx", 1300 "rx"; 1301 status = "disabled"; 1302 }; 1303 1304 spi16: spi@888000 { 1305 compatible = "qcom,geni-spi"; 1306 reg = <0x0 0x00888000 0x0 0x4000>; 1307 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1308 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1309 clock-names = "se"; 1310 pinctrl-0 = <&qup_spi16_default>; 1311 pinctrl-names = "default"; 1312 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1313 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1314 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1315 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1316 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1317 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1318 interconnect-names = "qup-core", 1319 "qup-config", 1320 "qup-memory"; 1321 power-domains = <&rpmhpd SA8775P_CX>; 1322 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1323 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1324 dma-names = "tx", 1325 "rx"; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 status = "disabled"; 1329 }; 1330 1331 uart16: serial@888000 { 1332 compatible = "qcom,geni-uart"; 1333 reg = <0x0 0x00888000 0x0 0x4000>; 1334 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1335 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1336 clock-names = "se"; 1337 pinctrl-0 = <&qup_uart16_default>; 1338 pinctrl-names = "default"; 1339 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1340 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1341 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1342 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1343 interconnect-names = "qup-core", "qup-config"; 1344 power-domains = <&rpmhpd SA8775P_CX>; 1345 status = "disabled"; 1346 }; 1347 1348 i2c17: i2c@88c000 { 1349 compatible = "qcom,geni-i2c"; 1350 reg = <0x0 0x88c000 0x0 0x4000>; 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1354 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1355 clock-names = "se"; 1356 pinctrl-0 = <&qup_i2c17_default>; 1357 pinctrl-names = "default"; 1358 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1359 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1360 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1361 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1362 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1363 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1364 interconnect-names = "qup-core", 1365 "qup-config", 1366 "qup-memory"; 1367 power-domains = <&rpmhpd SA8775P_CX>; 1368 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1369 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1370 dma-names = "tx", 1371 "rx"; 1372 status = "disabled"; 1373 }; 1374 1375 spi17: spi@88c000 { 1376 compatible = "qcom,geni-spi"; 1377 reg = <0x0 0x88c000 0x0 0x4000>; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1381 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1382 clock-names = "se"; 1383 pinctrl-0 = <&qup_spi17_default>; 1384 pinctrl-names = "default"; 1385 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1386 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1388 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1389 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1391 interconnect-names = "qup-core", 1392 "qup-config", 1393 "qup-memory"; 1394 power-domains = <&rpmhpd SA8775P_CX>; 1395 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1396 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1397 dma-names = "tx", 1398 "rx"; 1399 status = "disabled"; 1400 }; 1401 1402 uart17: serial@88c000 { 1403 compatible = "qcom,geni-uart"; 1404 reg = <0x0 0x0088c000 0x0 0x4000>; 1405 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1406 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1407 clock-names = "se"; 1408 pinctrl-0 = <&qup_uart17_default>; 1409 pinctrl-names = "default"; 1410 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1411 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1412 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1413 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1414 interconnect-names = "qup-core", "qup-config"; 1415 power-domains = <&rpmhpd SA8775P_CX>; 1416 status = "disabled"; 1417 }; 1418 1419 i2c18: i2c@890000 { 1420 compatible = "qcom,geni-i2c"; 1421 reg = <0x0 0x00890000 0x0 0x4000>; 1422 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1423 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1424 clock-names = "se"; 1425 pinctrl-0 = <&qup_i2c18_default>; 1426 pinctrl-names = "default"; 1427 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1428 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1429 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1430 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1431 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1432 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1433 interconnect-names = "qup-core", 1434 "qup-config", 1435 "qup-memory"; 1436 power-domains = <&rpmhpd SA8775P_CX>; 1437 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1438 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1439 dma-names = "tx", 1440 "rx"; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 status = "disabled"; 1444 }; 1445 1446 spi18: spi@890000 { 1447 compatible = "qcom,geni-spi"; 1448 reg = <0x0 0x890000 0x0 0x4000>; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1452 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1453 clock-names = "se"; 1454 pinctrl-0 = <&qup_spi18_default>; 1455 pinctrl-names = "default"; 1456 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1457 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1458 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1459 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1460 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1461 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1462 interconnect-names = "qup-core", 1463 "qup-config", 1464 "qup-memory"; 1465 power-domains = <&rpmhpd SA8775P_CX>; 1466 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1467 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1468 dma-names = "tx", 1469 "rx"; 1470 status = "disabled"; 1471 }; 1472 1473 uart18: serial@890000 { 1474 compatible = "qcom,geni-uart"; 1475 reg = <0x0 0x00890000 0x0 0x4000>; 1476 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1477 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1478 clock-names = "se"; 1479 pinctrl-0 = <&qup_uart18_default>; 1480 pinctrl-names = "default"; 1481 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1482 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1483 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1484 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1485 interconnect-names = "qup-core", "qup-config"; 1486 power-domains = <&rpmhpd SA8775P_CX>; 1487 status = "disabled"; 1488 }; 1489 1490 i2c19: i2c@894000 { 1491 compatible = "qcom,geni-i2c"; 1492 reg = <0x0 0x894000 0x0 0x4000>; 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1496 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1497 clock-names = "se"; 1498 pinctrl-0 = <&qup_i2c19_default>; 1499 pinctrl-names = "default"; 1500 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1501 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1502 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1503 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1504 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1505 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1506 interconnect-names = "qup-core", 1507 "qup-config", 1508 "qup-memory"; 1509 power-domains = <&rpmhpd SA8775P_CX>; 1510 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1511 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1512 dma-names = "tx", 1513 "rx"; 1514 status = "disabled"; 1515 }; 1516 1517 spi19: spi@894000 { 1518 compatible = "qcom,geni-spi"; 1519 reg = <0x0 0x894000 0x0 0x4000>; 1520 #address-cells = <1>; 1521 #size-cells = <0>; 1522 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1523 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1524 clock-names = "se"; 1525 pinctrl-0 = <&qup_spi19_default>; 1526 pinctrl-names = "default"; 1527 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1528 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1529 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1530 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1531 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1532 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1533 interconnect-names = "qup-core", 1534 "qup-config", 1535 "qup-memory"; 1536 power-domains = <&rpmhpd SA8775P_CX>; 1537 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1538 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1539 dma-names = "tx", 1540 "rx"; 1541 status = "disabled"; 1542 }; 1543 1544 uart19: serial@894000 { 1545 compatible = "qcom,geni-uart"; 1546 reg = <0x0 0x00894000 0x0 0x4000>; 1547 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1548 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1549 clock-names = "se"; 1550 pinctrl-0 = <&qup_uart19_default>; 1551 pinctrl-names = "default"; 1552 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1553 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1554 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1555 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1556 interconnect-names = "qup-core", "qup-config"; 1557 power-domains = <&rpmhpd SA8775P_CX>; 1558 status = "disabled"; 1559 }; 1560 1561 i2c20: i2c@898000 { 1562 compatible = "qcom,geni-i2c"; 1563 reg = <0x0 0x898000 0x0 0x4000>; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1567 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1568 clock-names = "se"; 1569 pinctrl-0 = <&qup_i2c20_default>; 1570 pinctrl-names = "default"; 1571 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1572 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1573 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1574 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1575 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1576 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1577 interconnect-names = "qup-core", 1578 "qup-config", 1579 "qup-memory"; 1580 power-domains = <&rpmhpd SA8775P_CX>; 1581 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1582 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1583 dma-names = "tx", 1584 "rx"; 1585 status = "disabled"; 1586 }; 1587 1588 spi20: spi@898000 { 1589 compatible = "qcom,geni-spi"; 1590 reg = <0x0 0x898000 0x0 0x4000>; 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1594 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1595 clock-names = "se"; 1596 pinctrl-0 = <&qup_spi20_default>; 1597 pinctrl-names = "default"; 1598 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1599 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1600 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1601 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1602 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1603 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1604 interconnect-names = "qup-core", 1605 "qup-config", 1606 "qup-memory"; 1607 power-domains = <&rpmhpd SA8775P_CX>; 1608 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1609 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1610 dma-names = "tx", 1611 "rx"; 1612 status = "disabled"; 1613 }; 1614 1615 uart20: serial@898000 { 1616 compatible = "qcom,geni-uart"; 1617 reg = <0x0 0x00898000 0x0 0x4000>; 1618 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1619 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1620 clock-names = "se"; 1621 pinctrl-0 = <&qup_uart20_default>; 1622 pinctrl-names = "default"; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1624 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1625 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1626 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1627 interconnect-names = "qup-core", "qup-config"; 1628 power-domains = <&rpmhpd SA8775P_CX>; 1629 status = "disabled"; 1630 }; 1631 1632 }; 1633 1634 gpi_dma0: dma-controller@900000 { 1635 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1636 reg = <0x0 0x00900000 0x0 0x60000>; 1637 #dma-cells = <3>; 1638 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1650 dma-channels = <12>; 1651 dma-channel-mask = <0xfff>; 1652 iommus = <&apps_smmu 0x416 0x0>; 1653 status = "disabled"; 1654 }; 1655 1656 qupv3_id_0: geniqup@9c0000 { 1657 compatible = "qcom,geni-se-qup"; 1658 reg = <0x0 0x9c0000 0x0 0x6000>; 1659 #address-cells = <2>; 1660 #size-cells = <2>; 1661 ranges; 1662 clock-names = "m-ahb", "s-ahb"; 1663 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1664 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1665 iommus = <&apps_smmu 0x403 0x0>; 1666 status = "disabled"; 1667 1668 i2c0: i2c@980000 { 1669 compatible = "qcom,geni-i2c"; 1670 reg = <0x0 0x980000 0x0 0x4000>; 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1674 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1675 clock-names = "se"; 1676 pinctrl-0 = <&qup_i2c0_default>; 1677 pinctrl-names = "default"; 1678 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1679 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1680 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1681 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1682 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1683 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1684 interconnect-names = "qup-core", 1685 "qup-config", 1686 "qup-memory"; 1687 power-domains = <&rpmhpd SA8775P_CX>; 1688 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1689 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1690 dma-names = "tx", 1691 "rx"; 1692 status = "disabled"; 1693 }; 1694 1695 spi0: spi@980000 { 1696 compatible = "qcom,geni-spi"; 1697 reg = <0x0 0x980000 0x0 0x4000>; 1698 #address-cells = <1>; 1699 #size-cells = <0>; 1700 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1701 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1702 clock-names = "se"; 1703 pinctrl-0 = <&qup_spi0_default>; 1704 pinctrl-names = "default"; 1705 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1706 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1707 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1708 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1709 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1710 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1711 interconnect-names = "qup-core", 1712 "qup-config", 1713 "qup-memory"; 1714 power-domains = <&rpmhpd SA8775P_CX>; 1715 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1716 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1717 dma-names = "tx", 1718 "rx"; 1719 status = "disabled"; 1720 }; 1721 1722 uart0: serial@980000 { 1723 compatible = "qcom,geni-uart"; 1724 reg = <0x0 0x980000 0x0 0x4000>; 1725 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1726 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1727 clock-names = "se"; 1728 pinctrl-0 = <&qup_uart0_default>; 1729 pinctrl-names = "default"; 1730 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1731 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1732 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1733 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1734 interconnect-names = "qup-core", "qup-config"; 1735 power-domains = <&rpmhpd SA8775P_CX>; 1736 status = "disabled"; 1737 }; 1738 1739 i2c1: i2c@984000 { 1740 compatible = "qcom,geni-i2c"; 1741 reg = <0x0 0x984000 0x0 0x4000>; 1742 #address-cells = <1>; 1743 #size-cells = <0>; 1744 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1745 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1746 clock-names = "se"; 1747 pinctrl-0 = <&qup_i2c1_default>; 1748 pinctrl-names = "default"; 1749 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1750 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1751 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1752 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1753 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1754 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1755 interconnect-names = "qup-core", 1756 "qup-config", 1757 "qup-memory"; 1758 power-domains = <&rpmhpd SA8775P_CX>; 1759 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1760 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1761 dma-names = "tx", 1762 "rx"; 1763 status = "disabled"; 1764 }; 1765 1766 spi1: spi@984000 { 1767 compatible = "qcom,geni-spi"; 1768 reg = <0x0 0x984000 0x0 0x4000>; 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1772 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1773 clock-names = "se"; 1774 pinctrl-0 = <&qup_spi1_default>; 1775 pinctrl-names = "default"; 1776 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1777 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1778 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1779 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1780 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1781 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1782 interconnect-names = "qup-core", 1783 "qup-config", 1784 "qup-memory"; 1785 power-domains = <&rpmhpd SA8775P_CX>; 1786 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1787 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1788 dma-names = "tx", 1789 "rx"; 1790 status = "disabled"; 1791 }; 1792 1793 uart1: serial@984000 { 1794 compatible = "qcom,geni-uart"; 1795 reg = <0x0 0x984000 0x0 0x4000>; 1796 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1797 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1798 clock-names = "se"; 1799 pinctrl-0 = <&qup_uart1_default>; 1800 pinctrl-names = "default"; 1801 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1802 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1803 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1804 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1805 interconnect-names = "qup-core", "qup-config"; 1806 power-domains = <&rpmhpd SA8775P_CX>; 1807 status = "disabled"; 1808 }; 1809 1810 i2c2: i2c@988000 { 1811 compatible = "qcom,geni-i2c"; 1812 reg = <0x0 0x988000 0x0 0x4000>; 1813 #address-cells = <1>; 1814 #size-cells = <0>; 1815 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1816 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1817 clock-names = "se"; 1818 pinctrl-0 = <&qup_i2c2_default>; 1819 pinctrl-names = "default"; 1820 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1821 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1822 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1823 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1824 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1825 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1826 interconnect-names = "qup-core", 1827 "qup-config", 1828 "qup-memory"; 1829 power-domains = <&rpmhpd SA8775P_CX>; 1830 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1831 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1832 dma-names = "tx", 1833 "rx"; 1834 status = "disabled"; 1835 }; 1836 1837 spi2: spi@988000 { 1838 compatible = "qcom,geni-spi"; 1839 reg = <0x0 0x988000 0x0 0x4000>; 1840 #address-cells = <1>; 1841 #size-cells = <0>; 1842 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1843 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1844 clock-names = "se"; 1845 pinctrl-0 = <&qup_spi2_default>; 1846 pinctrl-names = "default"; 1847 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1848 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1849 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1850 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1851 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1852 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1853 interconnect-names = "qup-core", 1854 "qup-config", 1855 "qup-memory"; 1856 power-domains = <&rpmhpd SA8775P_CX>; 1857 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1858 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1859 dma-names = "tx", 1860 "rx"; 1861 status = "disabled"; 1862 }; 1863 1864 uart2: serial@988000 { 1865 compatible = "qcom,geni-uart"; 1866 reg = <0x0 0x988000 0x0 0x4000>; 1867 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1868 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1869 clock-names = "se"; 1870 pinctrl-0 = <&qup_uart2_default>; 1871 pinctrl-names = "default"; 1872 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1873 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1874 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1875 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1876 interconnect-names = "qup-core", "qup-config"; 1877 power-domains = <&rpmhpd SA8775P_CX>; 1878 status = "disabled"; 1879 }; 1880 1881 i2c3: i2c@98c000 { 1882 compatible = "qcom,geni-i2c"; 1883 reg = <0x0 0x98c000 0x0 0x4000>; 1884 #address-cells = <1>; 1885 #size-cells = <0>; 1886 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1887 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1888 clock-names = "se"; 1889 pinctrl-0 = <&qup_i2c3_default>; 1890 pinctrl-names = "default"; 1891 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1892 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1893 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1894 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1895 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1896 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1897 interconnect-names = "qup-core", 1898 "qup-config", 1899 "qup-memory"; 1900 power-domains = <&rpmhpd SA8775P_CX>; 1901 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1902 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1903 dma-names = "tx", 1904 "rx"; 1905 status = "disabled"; 1906 }; 1907 1908 spi3: spi@98c000 { 1909 compatible = "qcom,geni-spi"; 1910 reg = <0x0 0x98c000 0x0 0x4000>; 1911 #address-cells = <1>; 1912 #size-cells = <0>; 1913 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1914 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1915 clock-names = "se"; 1916 pinctrl-0 = <&qup_spi3_default>; 1917 pinctrl-names = "default"; 1918 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1919 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1920 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1921 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1922 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1923 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1924 interconnect-names = "qup-core", 1925 "qup-config", 1926 "qup-memory"; 1927 power-domains = <&rpmhpd SA8775P_CX>; 1928 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1929 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1930 dma-names = "tx", 1931 "rx"; 1932 status = "disabled"; 1933 }; 1934 1935 uart3: serial@98c000 { 1936 compatible = "qcom,geni-uart"; 1937 reg = <0x0 0x98c000 0x0 0x4000>; 1938 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1939 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1940 clock-names = "se"; 1941 pinctrl-0 = <&qup_uart3_default>; 1942 pinctrl-names = "default"; 1943 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1944 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1945 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1946 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1947 interconnect-names = "qup-core", "qup-config"; 1948 power-domains = <&rpmhpd SA8775P_CX>; 1949 status = "disabled"; 1950 }; 1951 1952 i2c4: i2c@990000 { 1953 compatible = "qcom,geni-i2c"; 1954 reg = <0x0 0x990000 0x0 0x4000>; 1955 #address-cells = <1>; 1956 #size-cells = <0>; 1957 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1958 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1959 clock-names = "se"; 1960 pinctrl-0 = <&qup_i2c4_default>; 1961 pinctrl-names = "default"; 1962 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1963 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1964 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1965 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1966 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1967 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1968 interconnect-names = "qup-core", 1969 "qup-config", 1970 "qup-memory"; 1971 power-domains = <&rpmhpd SA8775P_CX>; 1972 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1973 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1974 dma-names = "tx", 1975 "rx"; 1976 status = "disabled"; 1977 }; 1978 1979 spi4: spi@990000 { 1980 compatible = "qcom,geni-spi"; 1981 reg = <0x0 0x990000 0x0 0x4000>; 1982 #address-cells = <1>; 1983 #size-cells = <0>; 1984 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1985 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1986 clock-names = "se"; 1987 pinctrl-0 = <&qup_spi4_default>; 1988 pinctrl-names = "default"; 1989 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1990 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1992 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1993 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1995 interconnect-names = "qup-core", 1996 "qup-config", 1997 "qup-memory"; 1998 power-domains = <&rpmhpd SA8775P_CX>; 1999 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2000 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2001 dma-names = "tx", 2002 "rx"; 2003 status = "disabled"; 2004 }; 2005 2006 uart4: serial@990000 { 2007 compatible = "qcom,geni-uart"; 2008 reg = <0x0 0x990000 0x0 0x4000>; 2009 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 2010 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2011 clock-names = "se"; 2012 pinctrl-0 = <&qup_uart4_default>; 2013 pinctrl-names = "default"; 2014 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2015 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2016 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2017 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2018 interconnect-names = "qup-core", "qup-config"; 2019 power-domains = <&rpmhpd SA8775P_CX>; 2020 status = "disabled"; 2021 }; 2022 2023 i2c5: i2c@994000 { 2024 compatible = "qcom,geni-i2c"; 2025 reg = <0x0 0x994000 0x0 0x4000>; 2026 #address-cells = <1>; 2027 #size-cells = <0>; 2028 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2029 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2030 clock-names = "se"; 2031 pinctrl-0 = <&qup_i2c5_default>; 2032 pinctrl-names = "default"; 2033 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2034 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2035 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2036 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2037 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2038 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2039 interconnect-names = "qup-core", 2040 "qup-config", 2041 "qup-memory"; 2042 power-domains = <&rpmhpd SA8775P_CX>; 2043 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2044 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2045 dma-names = "tx", 2046 "rx"; 2047 status = "disabled"; 2048 }; 2049 2050 spi5: spi@994000 { 2051 compatible = "qcom,geni-spi"; 2052 reg = <0x0 0x994000 0x0 0x4000>; 2053 #address-cells = <1>; 2054 #size-cells = <0>; 2055 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2056 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2057 clock-names = "se"; 2058 pinctrl-0 = <&qup_spi5_default>; 2059 pinctrl-names = "default"; 2060 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2061 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2062 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2063 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2064 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2065 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2066 interconnect-names = "qup-core", 2067 "qup-config", 2068 "qup-memory"; 2069 power-domains = <&rpmhpd SA8775P_CX>; 2070 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2071 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2072 dma-names = "tx", 2073 "rx"; 2074 status = "disabled"; 2075 }; 2076 2077 uart5: serial@994000 { 2078 compatible = "qcom,geni-uart"; 2079 reg = <0x0 0x994000 0x0 0x4000>; 2080 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2081 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2082 clock-names = "se"; 2083 pinctrl-0 = <&qup_uart5_default>; 2084 pinctrl-names = "default"; 2085 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2086 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2087 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2088 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2089 interconnect-names = "qup-core", "qup-config"; 2090 power-domains = <&rpmhpd SA8775P_CX>; 2091 status = "disabled"; 2092 }; 2093 }; 2094 2095 gpi_dma1: dma-controller@a00000 { 2096 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2097 reg = <0x0 0x00a00000 0x0 0x60000>; 2098 #dma-cells = <3>; 2099 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2111 iommus = <&apps_smmu 0x456 0x0>; 2112 dma-channels = <12>; 2113 dma-channel-mask = <0xfff>; 2114 status = "disabled"; 2115 }; 2116 2117 qupv3_id_1: geniqup@ac0000 { 2118 compatible = "qcom,geni-se-qup"; 2119 reg = <0x0 0x00ac0000 0x0 0x6000>; 2120 #address-cells = <2>; 2121 #size-cells = <2>; 2122 ranges; 2123 clock-names = "m-ahb", "s-ahb"; 2124 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 2125 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 2126 iommus = <&apps_smmu 0x443 0x0>; 2127 status = "disabled"; 2128 2129 i2c7: i2c@a80000 { 2130 compatible = "qcom,geni-i2c"; 2131 reg = <0x0 0xa80000 0x0 0x4000>; 2132 #address-cells = <1>; 2133 #size-cells = <0>; 2134 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2135 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2136 clock-names = "se"; 2137 pinctrl-0 = <&qup_i2c7_default>; 2138 pinctrl-names = "default"; 2139 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2140 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2141 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2142 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2143 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2144 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2145 interconnect-names = "qup-core", 2146 "qup-config", 2147 "qup-memory"; 2148 power-domains = <&rpmhpd SA8775P_CX>; 2149 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 2150 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 2151 dma-names = "tx", 2152 "rx"; 2153 status = "disabled"; 2154 }; 2155 2156 spi7: spi@a80000 { 2157 compatible = "qcom,geni-spi"; 2158 reg = <0x0 0xa80000 0x0 0x4000>; 2159 #address-cells = <1>; 2160 #size-cells = <0>; 2161 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2162 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2163 clock-names = "se"; 2164 pinctrl-0 = <&qup_spi7_default>; 2165 pinctrl-names = "default"; 2166 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2167 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2168 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2169 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2170 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2171 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2172 interconnect-names = "qup-core", 2173 "qup-config", 2174 "qup-memory"; 2175 power-domains = <&rpmhpd SA8775P_CX>; 2176 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 2177 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 2178 dma-names = "tx", 2179 "rx"; 2180 status = "disabled"; 2181 }; 2182 2183 uart7: serial@a80000 { 2184 compatible = "qcom,geni-uart"; 2185 reg = <0x0 0x00a80000 0x0 0x4000>; 2186 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2187 clock-names = "se"; 2188 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2189 pinctrl-0 = <&qup_uart7_default>; 2190 pinctrl-names = "default"; 2191 interconnect-names = "qup-core", "qup-config"; 2192 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2193 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2194 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2195 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2196 power-domains = <&rpmhpd SA8775P_CX>; 2197 operating-points-v2 = <&qup_opp_table_100mhz>; 2198 status = "disabled"; 2199 }; 2200 2201 i2c8: i2c@a84000 { 2202 compatible = "qcom,geni-i2c"; 2203 reg = <0x0 0xa84000 0x0 0x4000>; 2204 #address-cells = <1>; 2205 #size-cells = <0>; 2206 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2207 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2208 clock-names = "se"; 2209 pinctrl-0 = <&qup_i2c8_default>; 2210 pinctrl-names = "default"; 2211 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2212 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2213 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2214 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2215 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2216 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2217 interconnect-names = "qup-core", 2218 "qup-config", 2219 "qup-memory"; 2220 power-domains = <&rpmhpd SA8775P_CX>; 2221 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 2222 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 2223 dma-names = "tx", 2224 "rx"; 2225 status = "disabled"; 2226 }; 2227 2228 spi8: spi@a84000 { 2229 compatible = "qcom,geni-spi"; 2230 reg = <0x0 0xa84000 0x0 0x4000>; 2231 #address-cells = <1>; 2232 #size-cells = <0>; 2233 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2234 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2235 clock-names = "se"; 2236 pinctrl-0 = <&qup_spi8_default>; 2237 pinctrl-names = "default"; 2238 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2239 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2240 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2241 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2242 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2243 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2244 interconnect-names = "qup-core", 2245 "qup-config", 2246 "qup-memory"; 2247 power-domains = <&rpmhpd SA8775P_CX>; 2248 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 2249 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 2250 dma-names = "tx", 2251 "rx"; 2252 status = "disabled"; 2253 }; 2254 2255 uart8: serial@a84000 { 2256 compatible = "qcom,geni-uart"; 2257 reg = <0x0 0x00a84000 0x0 0x4000>; 2258 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2259 clock-names = "se"; 2260 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2261 pinctrl-0 = <&qup_uart8_default>; 2262 pinctrl-names = "default"; 2263 interconnect-names = "qup-core", "qup-config"; 2264 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2265 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2266 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2267 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2268 power-domains = <&rpmhpd SA8775P_CX>; 2269 operating-points-v2 = <&qup_opp_table_100mhz>; 2270 status = "disabled"; 2271 }; 2272 2273 i2c9: i2c@a88000 { 2274 compatible = "qcom,geni-i2c"; 2275 reg = <0x0 0xa88000 0x0 0x4000>; 2276 #address-cells = <1>; 2277 #size-cells = <0>; 2278 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2279 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2280 clock-names = "se"; 2281 pinctrl-0 = <&qup_i2c9_default>; 2282 pinctrl-names = "default"; 2283 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2284 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2285 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2286 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2287 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2288 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2289 interconnect-names = "qup-core", 2290 "qup-config", 2291 "qup-memory"; 2292 power-domains = <&rpmhpd SA8775P_CX>; 2293 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 2294 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 2295 dma-names = "tx", 2296 "rx"; 2297 status = "disabled"; 2298 }; 2299 2300 spi9: spi@a88000 { 2301 compatible = "qcom,geni-spi"; 2302 reg = <0x0 0xa88000 0x0 0x4000>; 2303 #address-cells = <1>; 2304 #size-cells = <0>; 2305 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2306 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2307 clock-names = "se"; 2308 pinctrl-0 = <&qup_spi9_default>; 2309 pinctrl-names = "default"; 2310 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2311 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2312 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2313 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2314 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2315 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2316 interconnect-names = "qup-core", 2317 "qup-config", 2318 "qup-memory"; 2319 power-domains = <&rpmhpd SA8775P_CX>; 2320 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 2321 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 2322 dma-names = "tx", 2323 "rx"; 2324 status = "disabled"; 2325 }; 2326 2327 uart9: serial@a88000 { 2328 compatible = "qcom,geni-uart"; 2329 reg = <0x0 0xa88000 0x0 0x4000>; 2330 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2331 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2332 clock-names = "se"; 2333 pinctrl-0 = <&qup_uart9_default>; 2334 pinctrl-names = "default"; 2335 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2336 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2337 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2338 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2339 interconnect-names = "qup-core", "qup-config"; 2340 power-domains = <&rpmhpd SA8775P_CX>; 2341 status = "disabled"; 2342 }; 2343 2344 i2c10: i2c@a8c000 { 2345 compatible = "qcom,geni-i2c"; 2346 reg = <0x0 0xa8c000 0x0 0x4000>; 2347 #address-cells = <1>; 2348 #size-cells = <0>; 2349 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2350 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2351 clock-names = "se"; 2352 pinctrl-0 = <&qup_i2c10_default>; 2353 pinctrl-names = "default"; 2354 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2355 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2356 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2357 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2358 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2359 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2360 interconnect-names = "qup-core", 2361 "qup-config", 2362 "qup-memory"; 2363 power-domains = <&rpmhpd SA8775P_CX>; 2364 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 2365 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 2366 dma-names = "tx", 2367 "rx"; 2368 status = "disabled"; 2369 }; 2370 2371 spi10: spi@a8c000 { 2372 compatible = "qcom,geni-spi"; 2373 reg = <0x0 0xa8c000 0x0 0x4000>; 2374 #address-cells = <1>; 2375 #size-cells = <0>; 2376 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2377 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2378 clock-names = "se"; 2379 pinctrl-0 = <&qup_spi10_default>; 2380 pinctrl-names = "default"; 2381 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2382 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2383 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2384 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2385 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2386 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2387 interconnect-names = "qup-core", 2388 "qup-config", 2389 "qup-memory"; 2390 power-domains = <&rpmhpd SA8775P_CX>; 2391 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 2392 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 2393 dma-names = "tx", 2394 "rx"; 2395 status = "disabled"; 2396 }; 2397 2398 uart10: serial@a8c000 { 2399 compatible = "qcom,geni-uart"; 2400 reg = <0x0 0x00a8c000 0x0 0x4000>; 2401 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2402 clock-names = "se"; 2403 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2404 pinctrl-0 = <&qup_uart10_default>; 2405 pinctrl-names = "default"; 2406 interconnect-names = "qup-core", "qup-config"; 2407 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 2408 &clk_virt SLAVE_QUP_CORE_1 0>, 2409 <&gem_noc MASTER_APPSS_PROC 0 2410 &config_noc SLAVE_QUP_1 0>; 2411 power-domains = <&rpmhpd SA8775P_CX>; 2412 operating-points-v2 = <&qup_opp_table_100mhz>; 2413 status = "disabled"; 2414 }; 2415 2416 i2c11: i2c@a90000 { 2417 compatible = "qcom,geni-i2c"; 2418 reg = <0x0 0xa90000 0x0 0x4000>; 2419 #address-cells = <1>; 2420 #size-cells = <0>; 2421 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2422 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2423 clock-names = "se"; 2424 pinctrl-0 = <&qup_i2c11_default>; 2425 pinctrl-names = "default"; 2426 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2427 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2428 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2429 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2430 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2431 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2432 interconnect-names = "qup-core", 2433 "qup-config", 2434 "qup-memory"; 2435 power-domains = <&rpmhpd SA8775P_CX>; 2436 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2437 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2438 dma-names = "tx", 2439 "rx"; 2440 status = "disabled"; 2441 }; 2442 2443 spi11: spi@a90000 { 2444 compatible = "qcom,geni-spi"; 2445 reg = <0x0 0xa90000 0x0 0x4000>; 2446 #address-cells = <1>; 2447 #size-cells = <0>; 2448 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2449 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2450 clock-names = "se"; 2451 pinctrl-0 = <&qup_spi11_default>; 2452 pinctrl-names = "default"; 2453 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2454 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2455 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2456 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2457 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2458 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2459 interconnect-names = "qup-core", 2460 "qup-config", 2461 "qup-memory"; 2462 power-domains = <&rpmhpd SA8775P_CX>; 2463 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2464 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2465 dma-names = "tx", 2466 "rx"; 2467 status = "disabled"; 2468 }; 2469 2470 uart11: serial@a90000 { 2471 compatible = "qcom,geni-uart"; 2472 reg = <0x0 0x00a90000 0x0 0x4000>; 2473 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2474 clock-names = "se"; 2475 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2476 pinctrl-0 = <&qup_uart11_default>; 2477 pinctrl-names = "default"; 2478 interconnect-names = "qup-core", "qup-config"; 2479 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2480 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2481 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2482 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2483 power-domains = <&rpmhpd SA8775P_CX>; 2484 operating-points-v2 = <&qup_opp_table_100mhz>; 2485 status = "disabled"; 2486 }; 2487 2488 i2c12: i2c@a94000 { 2489 compatible = "qcom,geni-i2c"; 2490 reg = <0x0 0xa94000 0x0 0x4000>; 2491 #address-cells = <1>; 2492 #size-cells = <0>; 2493 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2494 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2495 clock-names = "se"; 2496 pinctrl-0 = <&qup_i2c12_default>; 2497 pinctrl-names = "default"; 2498 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2499 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2500 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2501 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2502 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2503 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2504 interconnect-names = "qup-core", 2505 "qup-config", 2506 "qup-memory"; 2507 power-domains = <&rpmhpd SA8775P_CX>; 2508 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2509 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2510 dma-names = "tx", 2511 "rx"; 2512 status = "disabled"; 2513 }; 2514 2515 spi12: spi@a94000 { 2516 compatible = "qcom,geni-spi"; 2517 reg = <0x0 0xa94000 0x0 0x4000>; 2518 #address-cells = <1>; 2519 #size-cells = <0>; 2520 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2521 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2522 clock-names = "se"; 2523 pinctrl-0 = <&qup_spi12_default>; 2524 pinctrl-names = "default"; 2525 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2526 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2527 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2528 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2529 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2530 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2531 interconnect-names = "qup-core", 2532 "qup-config", 2533 "qup-memory"; 2534 power-domains = <&rpmhpd SA8775P_CX>; 2535 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2536 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2537 dma-names = "tx", 2538 "rx"; 2539 status = "disabled"; 2540 }; 2541 2542 uart12: serial@a94000 { 2543 compatible = "qcom,geni-uart"; 2544 reg = <0x0 0x00a94000 0x0 0x4000>; 2545 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2546 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2547 clock-names = "se"; 2548 pinctrl-0 = <&qup_uart12_default>; 2549 pinctrl-names = "default"; 2550 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2551 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2552 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2553 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2554 interconnect-names = "qup-core", "qup-config"; 2555 power-domains = <&rpmhpd SA8775P_CX>; 2556 status = "disabled"; 2557 }; 2558 2559 i2c13: i2c@a98000 { 2560 compatible = "qcom,geni-i2c"; 2561 reg = <0x0 0xa98000 0x0 0x4000>; 2562 #address-cells = <1>; 2563 #size-cells = <0>; 2564 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2565 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2566 clock-names = "se"; 2567 pinctrl-0 = <&qup_i2c13_default>; 2568 pinctrl-names = "default"; 2569 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2570 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2571 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2572 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2573 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2574 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2575 interconnect-names = "qup-core", 2576 "qup-config", 2577 "qup-memory"; 2578 power-domains = <&rpmhpd SA8775P_CX>; 2579 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2580 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2581 dma-names = "tx", 2582 "rx"; 2583 status = "disabled"; 2584 2585 }; 2586 }; 2587 2588 gpi_dma3: dma-controller@b00000 { 2589 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2590 reg = <0x0 0x00b00000 0x0 0x58000>; 2591 #dma-cells = <3>; 2592 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2593 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2594 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2595 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2596 iommus = <&apps_smmu 0x056 0x0>; 2597 dma-channels = <4>; 2598 dma-channel-mask = <0xf>; 2599 status = "disabled"; 2600 }; 2601 2602 qupv3_id_3: geniqup@bc0000 { 2603 compatible = "qcom,geni-se-qup"; 2604 reg = <0x0 0xbc0000 0x0 0x6000>; 2605 #address-cells = <2>; 2606 #size-cells = <2>; 2607 ranges; 2608 clock-names = "m-ahb", "s-ahb"; 2609 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2610 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2611 iommus = <&apps_smmu 0x43 0x0>; 2612 status = "disabled"; 2613 2614 i2c21: i2c@b80000 { 2615 compatible = "qcom,geni-i2c"; 2616 reg = <0x0 0xb80000 0x0 0x4000>; 2617 #address-cells = <1>; 2618 #size-cells = <0>; 2619 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2620 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2621 clock-names = "se"; 2622 pinctrl-0 = <&qup_i2c21_default>; 2623 pinctrl-names = "default"; 2624 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2625 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2626 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2627 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2628 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2629 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2630 interconnect-names = "qup-core", 2631 "qup-config", 2632 "qup-memory"; 2633 power-domains = <&rpmhpd SA8775P_CX>; 2634 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2635 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2636 dma-names = "tx", 2637 "rx"; 2638 status = "disabled"; 2639 }; 2640 2641 spi21: spi@b80000 { 2642 compatible = "qcom,geni-spi"; 2643 reg = <0x0 0xb80000 0x0 0x4000>; 2644 #address-cells = <1>; 2645 #size-cells = <0>; 2646 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2647 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2648 clock-names = "se"; 2649 pinctrl-0 = <&qup_spi21_default>; 2650 pinctrl-names = "default"; 2651 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2652 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2653 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2654 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2655 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2656 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2657 interconnect-names = "qup-core", 2658 "qup-config", 2659 "qup-memory"; 2660 power-domains = <&rpmhpd SA8775P_CX>; 2661 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2662 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2663 dma-names = "tx", 2664 "rx"; 2665 status = "disabled"; 2666 }; 2667 2668 uart21: serial@b80000 { 2669 compatible = "qcom,geni-uart"; 2670 reg = <0x0 0x00b80000 0x0 0x4000>; 2671 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2672 clock-names = "se"; 2673 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2674 interconnect-names = "qup-core", "qup-config"; 2675 pinctrl-0 = <&qup_uart21_default>; 2676 pinctrl-names = "default"; 2677 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2678 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2679 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2680 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2681 power-domains = <&rpmhpd SA8775P_CX>; 2682 operating-points-v2 = <&qup_opp_table_100mhz>; 2683 status = "disabled"; 2684 }; 2685 }; 2686 2687 rng: rng@10d2000 { 2688 compatible = "qcom,sa8775p-trng", "qcom,trng"; 2689 reg = <0 0x010d2000 0 0x1000>; 2690 }; 2691 2692 ufs_mem_hc: ufshc@1d84000 { 2693 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2694 reg = <0x0 0x01d84000 0x0 0x3000>; 2695 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2696 phys = <&ufs_mem_phy>; 2697 phy-names = "ufsphy"; 2698 lanes-per-direction = <2>; 2699 #reset-cells = <1>; 2700 resets = <&gcc GCC_UFS_PHY_BCR>; 2701 reset-names = "rst"; 2702 power-domains = <&gcc UFS_PHY_GDSC>; 2703 required-opps = <&rpmhpd_opp_nom>; 2704 iommus = <&apps_smmu 0x100 0x0>; 2705 dma-coherent; 2706 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2707 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2708 <&gcc GCC_UFS_PHY_AHB_CLK>, 2709 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2710 <&rpmhcc RPMH_CXO_CLK>, 2711 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2712 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2713 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2714 clock-names = "core_clk", 2715 "bus_aggr_clk", 2716 "iface_clk", 2717 "core_clk_unipro", 2718 "ref_clk", 2719 "tx_lane0_sync_clk", 2720 "rx_lane0_sync_clk", 2721 "rx_lane1_sync_clk"; 2722 freq-table-hz = <75000000 300000000>, 2723 <0 0>, 2724 <0 0>, 2725 <75000000 300000000>, 2726 <0 0>, 2727 <0 0>, 2728 <0 0>, 2729 <0 0>; 2730 qcom,ice = <&ice>; 2731 status = "disabled"; 2732 }; 2733 2734 ufs_mem_phy: phy@1d87000 { 2735 compatible = "qcom,sa8775p-qmp-ufs-phy"; 2736 reg = <0x0 0x01d87000 0x0 0xe10>; 2737 /* 2738 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2739 * enables the CXO clock to eDP *and* UFS PHY. 2740 */ 2741 clocks = <&rpmhcc RPMH_CXO_CLK>, 2742 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2743 <&gcc GCC_EDP_REF_CLKREF_EN>; 2744 clock-names = "ref", "ref_aux", "qref"; 2745 power-domains = <&gcc UFS_PHY_GDSC>; 2746 resets = <&ufs_mem_hc 0>; 2747 reset-names = "ufsphy"; 2748 #phy-cells = <0>; 2749 status = "disabled"; 2750 }; 2751 2752 ice: crypto@1d88000 { 2753 compatible = "qcom,sa8775p-inline-crypto-engine", 2754 "qcom,inline-crypto-engine"; 2755 reg = <0x0 0x01d88000 0x0 0x18000>; 2756 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2757 }; 2758 2759 cryptobam: dma-controller@1dc4000 { 2760 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2761 reg = <0x0 0x01dc4000 0x0 0x28000>; 2762 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2763 #dma-cells = <1>; 2764 qcom,ee = <0>; 2765 qcom,num-ees = <4>; 2766 num-channels = <20>; 2767 qcom,controlled-remotely; 2768 iommus = <&apps_smmu 0x480 0x00>, 2769 <&apps_smmu 0x481 0x00>; 2770 }; 2771 2772 ctcu@4001000 { 2773 compatible = "qcom,sa8775p-ctcu"; 2774 reg = <0x0 0x04001000 0x0 0x1000>; 2775 2776 clocks = <&aoss_qmp>; 2777 clock-names = "apb"; 2778 2779 in-ports { 2780 #address-cells = <1>; 2781 #size-cells = <0>; 2782 2783 port@0 { 2784 reg = <0>; 2785 2786 ctcu_in0: endpoint { 2787 remote-endpoint = <&etr0_out>; 2788 }; 2789 }; 2790 2791 port@1 { 2792 reg = <1>; 2793 2794 ctcu_in1: endpoint { 2795 remote-endpoint = <&etr1_out>; 2796 }; 2797 }; 2798 }; 2799 }; 2800 2801 stm: stm@4002000 { 2802 compatible = "arm,coresight-stm", "arm,primecell"; 2803 reg = <0x0 0x4002000 0x0 0x1000>, 2804 <0x0 0x16280000 0x0 0x180000>; 2805 reg-names = "stm-base", "stm-stimulus-base"; 2806 2807 clocks = <&aoss_qmp>; 2808 clock-names = "apb_pclk"; 2809 2810 out-ports { 2811 port { 2812 stm_out: endpoint { 2813 remote-endpoint = 2814 <&funnel0_in7>; 2815 }; 2816 }; 2817 }; 2818 }; 2819 2820 tpdm@4003000 { 2821 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2822 reg = <0x0 0x4003000 0x0 0x1000>; 2823 2824 clocks = <&aoss_qmp>; 2825 clock-names = "apb_pclk"; 2826 2827 qcom,cmb-element-bits = <32>; 2828 qcom,cmb-msrs-num = <32>; 2829 status = "disabled"; 2830 2831 out-ports { 2832 port { 2833 qdss_tpdm0_out: endpoint { 2834 remote-endpoint = 2835 <&qdss_tpda_in0>; 2836 }; 2837 }; 2838 }; 2839 }; 2840 2841 tpda@4004000 { 2842 compatible = "qcom,coresight-tpda", "arm,primecell"; 2843 reg = <0x0 0x4004000 0x0 0x1000>; 2844 2845 clocks = <&aoss_qmp>; 2846 clock-names = "apb_pclk"; 2847 2848 out-ports { 2849 port { 2850 qdss_tpda_out: endpoint { 2851 remote-endpoint = 2852 <&funnel0_in6>; 2853 }; 2854 }; 2855 }; 2856 2857 in-ports { 2858 #address-cells = <1>; 2859 #size-cells = <0>; 2860 2861 port@0 { 2862 reg = <0>; 2863 qdss_tpda_in0: endpoint { 2864 remote-endpoint = 2865 <&qdss_tpdm0_out>; 2866 }; 2867 }; 2868 2869 port@1 { 2870 reg = <1>; 2871 qdss_tpda_in1: endpoint { 2872 remote-endpoint = 2873 <&qdss_tpdm1_out>; 2874 }; 2875 }; 2876 }; 2877 }; 2878 2879 tpdm@400f000 { 2880 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2881 reg = <0x0 0x400f000 0x0 0x1000>; 2882 2883 clocks = <&aoss_qmp>; 2884 clock-names = "apb_pclk"; 2885 2886 qcom,cmb-element-bits = <32>; 2887 qcom,cmb-msrs-num = <32>; 2888 2889 out-ports { 2890 port { 2891 qdss_tpdm1_out: endpoint { 2892 remote-endpoint = 2893 <&qdss_tpda_in1>; 2894 }; 2895 }; 2896 }; 2897 }; 2898 2899 funnel@4041000 { 2900 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2901 reg = <0x0 0x4041000 0x0 0x1000>; 2902 2903 clocks = <&aoss_qmp>; 2904 clock-names = "apb_pclk"; 2905 2906 out-ports { 2907 port { 2908 funnel0_out: endpoint { 2909 remote-endpoint = 2910 <&qdss_funnel_in0>; 2911 }; 2912 }; 2913 }; 2914 2915 in-ports { 2916 #address-cells = <1>; 2917 #size-cells = <0>; 2918 2919 port@6 { 2920 reg = <6>; 2921 funnel0_in6: endpoint { 2922 remote-endpoint = 2923 <&qdss_tpda_out>; 2924 }; 2925 }; 2926 2927 port@7 { 2928 reg = <7>; 2929 funnel0_in7: endpoint { 2930 remote-endpoint = 2931 <&stm_out>; 2932 }; 2933 }; 2934 }; 2935 }; 2936 2937 funnel@4042000 { 2938 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2939 reg = <0x0 0x4042000 0x0 0x1000>; 2940 2941 clocks = <&aoss_qmp>; 2942 clock-names = "apb_pclk"; 2943 2944 out-ports { 2945 port { 2946 funnel1_out: endpoint { 2947 remote-endpoint = 2948 <&qdss_funnel_in1>; 2949 }; 2950 }; 2951 }; 2952 2953 in-ports { 2954 #address-cells = <1>; 2955 #size-cells = <0>; 2956 2957 port@4 { 2958 reg = <4>; 2959 funnel1_in4: endpoint { 2960 remote-endpoint = 2961 <&apss_funnel1_out>; 2962 }; 2963 }; 2964 }; 2965 }; 2966 2967 funnel@4045000 { 2968 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2969 reg = <0x0 0x4045000 0x0 0x1000>; 2970 2971 clocks = <&aoss_qmp>; 2972 clock-names = "apb_pclk"; 2973 2974 out-ports { 2975 port { 2976 qdss_funnel_out: endpoint { 2977 remote-endpoint = 2978 <&aoss_funnel_in7>; 2979 }; 2980 }; 2981 }; 2982 2983 in-ports { 2984 #address-cells = <1>; 2985 #size-cells = <0>; 2986 2987 port@0 { 2988 reg = <0>; 2989 qdss_funnel_in0: endpoint { 2990 remote-endpoint = 2991 <&funnel0_out>; 2992 }; 2993 }; 2994 2995 port@1 { 2996 reg = <1>; 2997 qdss_funnel_in1: endpoint { 2998 remote-endpoint = 2999 <&funnel1_out>; 3000 }; 3001 }; 3002 }; 3003 }; 3004 3005 replicator@4046000 { 3006 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3007 reg = <0x0 0x04046000 0x0 0x1000>; 3008 3009 clocks = <&aoss_qmp>; 3010 clock-names = "apb_pclk"; 3011 3012 in-ports { 3013 port { 3014 qdss_rep_in: endpoint { 3015 remote-endpoint = <&swao_rep_out0>; 3016 }; 3017 }; 3018 }; 3019 3020 out-ports { 3021 port { 3022 qdss_rep_out0: endpoint { 3023 remote-endpoint = <&etr_rep_in>; 3024 }; 3025 }; 3026 }; 3027 }; 3028 3029 tmc_etr: tmc@4048000 { 3030 compatible = "arm,coresight-tmc", "arm,primecell"; 3031 reg = <0x0 0x04048000 0x0 0x1000>; 3032 3033 clocks = <&aoss_qmp>; 3034 clock-names = "apb_pclk"; 3035 iommus = <&apps_smmu 0x04c0 0x00>; 3036 3037 arm,scatter-gather; 3038 3039 in-ports { 3040 port { 3041 etr0_in: endpoint { 3042 remote-endpoint = <&etr_rep_out0>; 3043 }; 3044 }; 3045 }; 3046 3047 out-ports { 3048 port { 3049 etr0_out: endpoint { 3050 remote-endpoint = <&ctcu_in0>; 3051 }; 3052 }; 3053 }; 3054 }; 3055 3056 replicator@404e000 { 3057 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3058 reg = <0x0 0x0404e000 0x0 0x1000>; 3059 3060 clocks = <&aoss_qmp>; 3061 clock-names = "apb_pclk"; 3062 3063 in-ports { 3064 port { 3065 etr_rep_in: endpoint { 3066 remote-endpoint = <&qdss_rep_out0>; 3067 }; 3068 }; 3069 }; 3070 3071 out-ports { 3072 #address-cells = <1>; 3073 #size-cells = <0>; 3074 3075 port@0 { 3076 reg = <0>; 3077 3078 etr_rep_out0: endpoint { 3079 remote-endpoint = <&etr0_in>; 3080 }; 3081 }; 3082 3083 port@1 { 3084 reg = <1>; 3085 3086 etr_rep_out1: endpoint { 3087 remote-endpoint = <&etr1_in>; 3088 }; 3089 }; 3090 }; 3091 }; 3092 3093 tmc_etr1: tmc@404f000 { 3094 compatible = "arm,coresight-tmc", "arm,primecell"; 3095 reg = <0x0 0x0404f000 0x0 0x1000>; 3096 3097 clocks = <&aoss_qmp>; 3098 clock-names = "apb_pclk"; 3099 iommus = <&apps_smmu 0x04a0 0x40>; 3100 3101 arm,scatter-gather; 3102 arm,buffer-size = <0x400000>; 3103 3104 in-ports { 3105 port { 3106 etr1_in: endpoint { 3107 remote-endpoint = <&etr_rep_out1>; 3108 }; 3109 }; 3110 }; 3111 3112 out-ports { 3113 port { 3114 etr1_out: endpoint { 3115 remote-endpoint = <&ctcu_in1>; 3116 }; 3117 }; 3118 }; 3119 }; 3120 3121 funnel@4b04000 { 3122 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3123 reg = <0x0 0x4b04000 0x0 0x1000>; 3124 3125 clocks = <&aoss_qmp>; 3126 clock-names = "apb_pclk"; 3127 3128 out-ports { 3129 port { 3130 aoss_funnel_out: endpoint { 3131 remote-endpoint = 3132 <&etf0_in>; 3133 }; 3134 }; 3135 }; 3136 3137 in-ports { 3138 #address-cells = <1>; 3139 #size-cells = <0>; 3140 3141 port@6 { 3142 reg = <6>; 3143 aoss_funnel_in6: endpoint { 3144 remote-endpoint = 3145 <&aoss_tpda_out>; 3146 }; 3147 }; 3148 3149 port@7 { 3150 reg = <7>; 3151 aoss_funnel_in7: endpoint { 3152 remote-endpoint = 3153 <&qdss_funnel_out>; 3154 }; 3155 }; 3156 }; 3157 }; 3158 3159 tmc_etf: tmc@4b05000 { 3160 compatible = "arm,coresight-tmc", "arm,primecell"; 3161 reg = <0x0 0x4b05000 0x0 0x1000>; 3162 3163 clocks = <&aoss_qmp>; 3164 clock-names = "apb_pclk"; 3165 3166 out-ports { 3167 port { 3168 etf0_out: endpoint { 3169 remote-endpoint = 3170 <&swao_rep_in>; 3171 }; 3172 }; 3173 }; 3174 3175 in-ports { 3176 port { 3177 etf0_in: endpoint { 3178 remote-endpoint = 3179 <&aoss_funnel_out>; 3180 }; 3181 }; 3182 }; 3183 }; 3184 3185 replicator@4b06000 { 3186 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3187 reg = <0x0 0x4b06000 0x0 0x1000>; 3188 3189 clocks = <&aoss_qmp>; 3190 clock-names = "apb_pclk"; 3191 3192 out-ports { 3193 #address-cells = <1>; 3194 #size-cells = <0>; 3195 3196 port@0 { 3197 reg = <0>; 3198 3199 swao_rep_out0: endpoint { 3200 remote-endpoint = <&qdss_rep_in>; 3201 }; 3202 }; 3203 3204 port@1 { 3205 reg = <1>; 3206 swao_rep_out1: endpoint { 3207 remote-endpoint = 3208 <&eud_in>; 3209 }; 3210 }; 3211 }; 3212 3213 in-ports { 3214 port { 3215 swao_rep_in: endpoint { 3216 remote-endpoint = 3217 <&etf0_out>; 3218 }; 3219 }; 3220 }; 3221 }; 3222 3223 tpda@4b08000 { 3224 compatible = "qcom,coresight-tpda", "arm,primecell"; 3225 reg = <0x0 0x4b08000 0x0 0x1000>; 3226 3227 clocks = <&aoss_qmp>; 3228 clock-names = "apb_pclk"; 3229 3230 out-ports { 3231 port { 3232 aoss_tpda_out: endpoint { 3233 remote-endpoint = 3234 <&aoss_funnel_in6>; 3235 }; 3236 }; 3237 }; 3238 3239 in-ports { 3240 #address-cells = <1>; 3241 #size-cells = <0>; 3242 3243 port@0 { 3244 reg = <0>; 3245 aoss_tpda_in0: endpoint { 3246 remote-endpoint = 3247 <&aoss_tpdm0_out>; 3248 }; 3249 }; 3250 3251 port@1 { 3252 reg = <1>; 3253 aoss_tpda_in1: endpoint { 3254 remote-endpoint = 3255 <&aoss_tpdm1_out>; 3256 }; 3257 }; 3258 3259 port@2 { 3260 reg = <2>; 3261 aoss_tpda_in2: endpoint { 3262 remote-endpoint = 3263 <&aoss_tpdm2_out>; 3264 }; 3265 }; 3266 3267 port@3 { 3268 reg = <3>; 3269 aoss_tpda_in3: endpoint { 3270 remote-endpoint = 3271 <&aoss_tpdm3_out>; 3272 }; 3273 }; 3274 3275 port@4 { 3276 reg = <4>; 3277 aoss_tpda_in4: endpoint { 3278 remote-endpoint = 3279 <&aoss_tpdm4_out>; 3280 }; 3281 }; 3282 }; 3283 }; 3284 3285 tpdm@4b09000 { 3286 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3287 reg = <0x0 0x4b09000 0x0 0x1000>; 3288 3289 clocks = <&aoss_qmp>; 3290 clock-names = "apb_pclk"; 3291 3292 qcom,cmb-element-bits = <64>; 3293 qcom,cmb-msrs-num = <32>; 3294 3295 out-ports { 3296 port { 3297 aoss_tpdm0_out: endpoint { 3298 remote-endpoint = 3299 <&aoss_tpda_in0>; 3300 }; 3301 }; 3302 }; 3303 }; 3304 3305 tpdm@4b0a000 { 3306 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3307 reg = <0x0 0x4b0a000 0x0 0x1000>; 3308 3309 clocks = <&aoss_qmp>; 3310 clock-names = "apb_pclk"; 3311 3312 qcom,cmb-element-bits = <64>; 3313 qcom,cmb-msrs-num = <32>; 3314 3315 out-ports { 3316 port { 3317 aoss_tpdm1_out: endpoint { 3318 remote-endpoint = 3319 <&aoss_tpda_in1>; 3320 }; 3321 }; 3322 }; 3323 }; 3324 3325 tpdm@4b0b000 { 3326 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3327 reg = <0x0 0x4b0b000 0x0 0x1000>; 3328 3329 clocks = <&aoss_qmp>; 3330 clock-names = "apb_pclk"; 3331 3332 qcom,cmb-element-bits = <64>; 3333 qcom,cmb-msrs-num = <32>; 3334 3335 out-ports { 3336 port { 3337 aoss_tpdm2_out: endpoint { 3338 remote-endpoint = 3339 <&aoss_tpda_in2>; 3340 }; 3341 }; 3342 }; 3343 }; 3344 3345 tpdm@4b0c000 { 3346 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3347 reg = <0x0 0x4b0c000 0x0 0x1000>; 3348 3349 clocks = <&aoss_qmp>; 3350 clock-names = "apb_pclk"; 3351 3352 qcom,cmb-element-bits = <64>; 3353 qcom,cmb-msrs-num = <32>; 3354 3355 out-ports { 3356 port { 3357 aoss_tpdm3_out: endpoint { 3358 remote-endpoint = 3359 <&aoss_tpda_in3>; 3360 }; 3361 }; 3362 }; 3363 }; 3364 3365 tpdm@4b0d000 { 3366 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3367 reg = <0x0 0x4b0d000 0x0 0x1000>; 3368 3369 clocks = <&aoss_qmp>; 3370 clock-names = "apb_pclk"; 3371 3372 qcom,dsb-element-bits = <32>; 3373 qcom,dsb-msrs-num = <32>; 3374 3375 out-ports { 3376 port { 3377 aoss_tpdm4_out: endpoint { 3378 remote-endpoint = 3379 <&aoss_tpda_in4>; 3380 }; 3381 }; 3382 }; 3383 }; 3384 3385 aoss_cti: cti@4b13000 { 3386 compatible = "arm,coresight-cti", "arm,primecell"; 3387 reg = <0x0 0x4b13000 0x0 0x1000>; 3388 3389 clocks = <&aoss_qmp>; 3390 clock-names = "apb_pclk"; 3391 }; 3392 3393 etm@6040000 { 3394 compatible = "arm,primecell"; 3395 reg = <0x0 0x6040000 0x0 0x1000>; 3396 cpu = <&cpu0>; 3397 3398 clocks = <&aoss_qmp>; 3399 clock-names = "apb_pclk"; 3400 arm,coresight-loses-context-with-cpu; 3401 qcom,skip-power-up; 3402 3403 out-ports { 3404 port { 3405 etm0_out: endpoint { 3406 remote-endpoint = 3407 <&apss_funnel0_in0>; 3408 }; 3409 }; 3410 }; 3411 }; 3412 3413 etm@6140000 { 3414 compatible = "arm,primecell"; 3415 reg = <0x0 0x6140000 0x0 0x1000>; 3416 cpu = <&cpu1>; 3417 3418 clocks = <&aoss_qmp>; 3419 clock-names = "apb_pclk"; 3420 arm,coresight-loses-context-with-cpu; 3421 qcom,skip-power-up; 3422 3423 out-ports { 3424 port { 3425 etm1_out: endpoint { 3426 remote-endpoint = 3427 <&apss_funnel0_in1>; 3428 }; 3429 }; 3430 }; 3431 }; 3432 3433 etm@6240000 { 3434 compatible = "arm,primecell"; 3435 reg = <0x0 0x6240000 0x0 0x1000>; 3436 cpu = <&cpu2>; 3437 3438 clocks = <&aoss_qmp>; 3439 clock-names = "apb_pclk"; 3440 arm,coresight-loses-context-with-cpu; 3441 qcom,skip-power-up; 3442 3443 out-ports { 3444 port { 3445 etm2_out: endpoint { 3446 remote-endpoint = 3447 <&apss_funnel0_in2>; 3448 }; 3449 }; 3450 }; 3451 }; 3452 3453 etm@6340000 { 3454 compatible = "arm,primecell"; 3455 reg = <0x0 0x6340000 0x0 0x1000>; 3456 cpu = <&cpu3>; 3457 3458 clocks = <&aoss_qmp>; 3459 clock-names = "apb_pclk"; 3460 arm,coresight-loses-context-with-cpu; 3461 qcom,skip-power-up; 3462 3463 out-ports { 3464 port { 3465 etm3_out: endpoint { 3466 remote-endpoint = 3467 <&apss_funnel0_in3>; 3468 }; 3469 }; 3470 }; 3471 }; 3472 3473 etm@6440000 { 3474 compatible = "arm,primecell"; 3475 reg = <0x0 0x6440000 0x0 0x1000>; 3476 cpu = <&cpu4>; 3477 3478 clocks = <&aoss_qmp>; 3479 clock-names = "apb_pclk"; 3480 arm,coresight-loses-context-with-cpu; 3481 qcom,skip-power-up; 3482 3483 out-ports { 3484 port { 3485 etm4_out: endpoint { 3486 remote-endpoint = 3487 <&apss_funnel0_in4>; 3488 }; 3489 }; 3490 }; 3491 }; 3492 3493 etm@6540000 { 3494 compatible = "arm,primecell"; 3495 reg = <0x0 0x6540000 0x0 0x1000>; 3496 cpu = <&cpu5>; 3497 3498 clocks = <&aoss_qmp>; 3499 clock-names = "apb_pclk"; 3500 arm,coresight-loses-context-with-cpu; 3501 qcom,skip-power-up; 3502 3503 out-ports { 3504 port { 3505 etm5_out: endpoint { 3506 remote-endpoint = 3507 <&apss_funnel0_in5>; 3508 }; 3509 }; 3510 }; 3511 }; 3512 3513 etm@6640000 { 3514 compatible = "arm,primecell"; 3515 reg = <0x0 0x6640000 0x0 0x1000>; 3516 cpu = <&cpu6>; 3517 3518 clocks = <&aoss_qmp>; 3519 clock-names = "apb_pclk"; 3520 arm,coresight-loses-context-with-cpu; 3521 qcom,skip-power-up; 3522 3523 out-ports { 3524 port { 3525 etm6_out: endpoint { 3526 remote-endpoint = 3527 <&apss_funnel0_in6>; 3528 }; 3529 }; 3530 }; 3531 }; 3532 3533 etm@6740000 { 3534 compatible = "arm,primecell"; 3535 reg = <0x0 0x6740000 0x0 0x1000>; 3536 cpu = <&cpu7>; 3537 3538 clocks = <&aoss_qmp>; 3539 clock-names = "apb_pclk"; 3540 arm,coresight-loses-context-with-cpu; 3541 qcom,skip-power-up; 3542 3543 out-ports { 3544 port { 3545 etm7_out: endpoint { 3546 remote-endpoint = 3547 <&apss_funnel0_in7>; 3548 }; 3549 }; 3550 }; 3551 }; 3552 3553 funnel@6800000 { 3554 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3555 reg = <0x0 0x6800000 0x0 0x1000>; 3556 3557 clocks = <&aoss_qmp>; 3558 clock-names = "apb_pclk"; 3559 3560 out-ports { 3561 port { 3562 apss_funnel0_out: endpoint { 3563 remote-endpoint = 3564 <&apss_funnel1_in0>; 3565 }; 3566 }; 3567 }; 3568 3569 in-ports { 3570 #address-cells = <1>; 3571 #size-cells = <0>; 3572 3573 port@0 { 3574 reg = <0>; 3575 apss_funnel0_in0: endpoint { 3576 remote-endpoint = 3577 <&etm0_out>; 3578 }; 3579 }; 3580 3581 port@1 { 3582 reg = <1>; 3583 apss_funnel0_in1: endpoint { 3584 remote-endpoint = 3585 <&etm1_out>; 3586 }; 3587 }; 3588 3589 port@2 { 3590 reg = <2>; 3591 apss_funnel0_in2: endpoint { 3592 remote-endpoint = 3593 <&etm2_out>; 3594 }; 3595 }; 3596 3597 port@3 { 3598 reg = <3>; 3599 apss_funnel0_in3: endpoint { 3600 remote-endpoint = 3601 <&etm3_out>; 3602 }; 3603 }; 3604 3605 port@4 { 3606 reg = <4>; 3607 apss_funnel0_in4: endpoint { 3608 remote-endpoint = 3609 <&etm4_out>; 3610 }; 3611 }; 3612 3613 port@5 { 3614 reg = <5>; 3615 apss_funnel0_in5: endpoint { 3616 remote-endpoint = 3617 <&etm5_out>; 3618 }; 3619 }; 3620 3621 port@6 { 3622 reg = <6>; 3623 apss_funnel0_in6: endpoint { 3624 remote-endpoint = 3625 <&etm6_out>; 3626 }; 3627 }; 3628 3629 port@7 { 3630 reg = <7>; 3631 apss_funnel0_in7: endpoint { 3632 remote-endpoint = 3633 <&etm7_out>; 3634 }; 3635 }; 3636 }; 3637 }; 3638 3639 funnel@6810000 { 3640 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3641 reg = <0x0 0x6810000 0x0 0x1000>; 3642 3643 clocks = <&aoss_qmp>; 3644 clock-names = "apb_pclk"; 3645 3646 out-ports { 3647 port { 3648 apss_funnel1_out: endpoint { 3649 remote-endpoint = 3650 <&funnel1_in4>; 3651 }; 3652 }; 3653 }; 3654 3655 in-ports { 3656 #address-cells = <1>; 3657 #size-cells = <0>; 3658 3659 port@0 { 3660 reg = <0>; 3661 apss_funnel1_in0: endpoint { 3662 remote-endpoint = 3663 <&apss_funnel0_out>; 3664 }; 3665 }; 3666 3667 port@3 { 3668 reg = <3>; 3669 apss_funnel1_in3: endpoint { 3670 remote-endpoint = 3671 <&apss_tpda_out>; 3672 }; 3673 }; 3674 }; 3675 }; 3676 3677 tpdm@6860000 { 3678 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3679 reg = <0x0 0x6860000 0x0 0x1000>; 3680 3681 clocks = <&aoss_qmp>; 3682 clock-names = "apb_pclk"; 3683 3684 qcom,cmb-element-bits = <64>; 3685 qcom,cmb-msrs-num = <32>; 3686 3687 out-ports { 3688 port { 3689 apss_tpdm3_out: endpoint { 3690 remote-endpoint = 3691 <&apss_tpda_in3>; 3692 }; 3693 }; 3694 }; 3695 }; 3696 3697 tpdm@6861000 { 3698 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3699 reg = <0x0 0x6861000 0x0 0x1000>; 3700 3701 clocks = <&aoss_qmp>; 3702 clock-names = "apb_pclk"; 3703 3704 qcom,dsb-element-bits = <32>; 3705 qcom,dsb-msrs-num = <32>; 3706 3707 out-ports { 3708 port { 3709 apss_tpdm4_out: endpoint { 3710 remote-endpoint = 3711 <&apss_tpda_in4>; 3712 }; 3713 }; 3714 }; 3715 }; 3716 3717 tpda@6863000 { 3718 compatible = "qcom,coresight-tpda", "arm,primecell"; 3719 reg = <0x0 0x6863000 0x0 0x1000>; 3720 3721 clocks = <&aoss_qmp>; 3722 clock-names = "apb_pclk"; 3723 3724 out-ports { 3725 port { 3726 apss_tpda_out: endpoint { 3727 remote-endpoint = 3728 <&apss_funnel1_in3>; 3729 }; 3730 }; 3731 }; 3732 3733 in-ports { 3734 #address-cells = <1>; 3735 #size-cells = <0>; 3736 3737 port@0 { 3738 reg = <0>; 3739 apss_tpda_in0: endpoint { 3740 remote-endpoint = 3741 <&apss_tpdm0_out>; 3742 }; 3743 }; 3744 3745 port@1 { 3746 reg = <1>; 3747 apss_tpda_in1: endpoint { 3748 remote-endpoint = 3749 <&apss_tpdm1_out>; 3750 }; 3751 }; 3752 3753 port@2 { 3754 reg = <2>; 3755 apss_tpda_in2: endpoint { 3756 remote-endpoint = 3757 <&apss_tpdm2_out>; 3758 }; 3759 }; 3760 3761 port@3 { 3762 reg = <3>; 3763 apss_tpda_in3: endpoint { 3764 remote-endpoint = 3765 <&apss_tpdm3_out>; 3766 }; 3767 }; 3768 3769 port@4 { 3770 reg = <4>; 3771 apss_tpda_in4: endpoint { 3772 remote-endpoint = 3773 <&apss_tpdm4_out>; 3774 }; 3775 }; 3776 }; 3777 }; 3778 3779 tpdm@68a0000 { 3780 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3781 reg = <0x0 0x68a0000 0x0 0x1000>; 3782 3783 clocks = <&aoss_qmp>; 3784 clock-names = "apb_pclk"; 3785 3786 qcom,cmb-element-bits = <32>; 3787 qcom,cmb-msrs-num = <32>; 3788 3789 out-ports { 3790 port { 3791 apss_tpdm0_out: endpoint { 3792 remote-endpoint = 3793 <&apss_tpda_in0>; 3794 }; 3795 }; 3796 }; 3797 }; 3798 3799 tpdm@68b0000 { 3800 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3801 reg = <0x0 0x68b0000 0x0 0x1000>; 3802 3803 clocks = <&aoss_qmp>; 3804 clock-names = "apb_pclk"; 3805 3806 qcom,cmb-element-bits = <32>; 3807 qcom,cmb-msrs-num = <32>; 3808 3809 out-ports { 3810 port { 3811 apss_tpdm1_out: endpoint { 3812 remote-endpoint = 3813 <&apss_tpda_in1>; 3814 }; 3815 }; 3816 }; 3817 }; 3818 3819 tpdm@68c0000 { 3820 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3821 reg = <0x0 0x68c0000 0x0 0x1000>; 3822 3823 clocks = <&aoss_qmp>; 3824 clock-names = "apb_pclk"; 3825 3826 qcom,dsb-element-bits = <32>; 3827 qcom,dsb-msrs-num = <32>; 3828 3829 out-ports { 3830 port { 3831 apss_tpdm2_out: endpoint { 3832 remote-endpoint = 3833 <&apss_tpda_in2>; 3834 }; 3835 }; 3836 }; 3837 }; 3838 3839 sdhc: mmc@87c4000 { 3840 compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; 3841 reg = <0x0 0x087c4000 0x0 0x1000>; 3842 3843 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; 3845 interrupt-names = "hc_irq", 3846 "pwr_irq"; 3847 3848 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3849 <&gcc GCC_SDCC1_APPS_CLK>; 3850 clock-names = "iface", 3851 "core"; 3852 3853 interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS 3854 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3855 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3856 &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3857 interconnect-names = "sdhc-ddr", 3858 "cpu-sdhc"; 3859 3860 iommus = <&apps_smmu 0x0 0x0>; 3861 dma-coherent; 3862 3863 operating-points-v2 = <&sdhc_opp_table>; 3864 power-domains = <&rpmhpd SA8775P_CX>; 3865 resets = <&gcc GCC_SDCC1_BCR>; 3866 3867 qcom,dll-config = <0x0007642c>; 3868 qcom,ddr-config = <0x80040868>; 3869 3870 status = "disabled"; 3871 3872 sdhc_opp_table: opp-table { 3873 compatible = "operating-points-v2"; 3874 3875 opp-100000000 { 3876 opp-hz = /bits/ 64 <100000000>; 3877 required-opps = <&rpmhpd_opp_low_svs>; 3878 opp-peak-kBps = <1800000 400000>; 3879 opp-avg-kBps = <100000 0>; 3880 }; 3881 3882 opp-384000000 { 3883 opp-hz = /bits/ 64 <384000000>; 3884 required-opps = <&rpmhpd_opp_nom>; 3885 opp-peak-kBps = <5400000 1600000>; 3886 opp-avg-kBps = <390000 0>; 3887 }; 3888 }; 3889 }; 3890 3891 usb_0_hsphy: phy@88e4000 { 3892 compatible = "qcom,sa8775p-usb-hs-phy", 3893 "qcom,usb-snps-hs-5nm-phy"; 3894 reg = <0 0x088e4000 0 0x120>; 3895 clocks = <&rpmhcc RPMH_CXO_CLK>; 3896 clock-names = "ref"; 3897 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 3898 3899 #phy-cells = <0>; 3900 3901 status = "disabled"; 3902 }; 3903 3904 usb_0_qmpphy: phy@88e8000 { 3905 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 3906 reg = <0 0x088e8000 0 0x2000>; 3907 3908 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3909 <&gcc GCC_USB_CLKREF_EN>, 3910 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3911 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3912 clock-names = "aux", "ref", "com_aux", "pipe"; 3913 3914 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3915 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 3916 reset-names = "phy", "phy_phy"; 3917 3918 power-domains = <&gcc USB30_PRIM_GDSC>; 3919 3920 #clock-cells = <0>; 3921 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 3922 3923 #phy-cells = <0>; 3924 3925 status = "disabled"; 3926 }; 3927 3928 usb_0: usb@a600000 { 3929 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 3930 reg = <0 0x0a600000 0 0xfc100>; 3931 3932 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3933 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3934 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3935 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3936 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3937 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3938 3939 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3940 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3941 assigned-clock-rates = <19200000>, <200000000>; 3942 3943 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 3944 <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 3945 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3946 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3947 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3948 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 3949 interrupt-names = "dwc_usb3", 3950 "pwr_event", 3951 "hs_phy_irq", 3952 "dp_hs_phy_irq", 3953 "dm_hs_phy_irq", 3954 "ss_phy_irq"; 3955 3956 power-domains = <&gcc USB30_PRIM_GDSC>; 3957 required-opps = <&rpmhpd_opp_nom>; 3958 3959 resets = <&gcc GCC_USB30_PRIM_BCR>; 3960 3961 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3962 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3963 interconnect-names = "usb-ddr", "apps-usb"; 3964 3965 wakeup-source; 3966 3967 iommus = <&apps_smmu 0x080 0x0>; 3968 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 3969 phy-names = "usb2-phy", "usb3-phy"; 3970 snps,dis-u1-entry-quirk; 3971 snps,dis-u2-entry-quirk; 3972 3973 status = "disabled"; 3974 }; 3975 3976 usb_1_hsphy: phy@88e6000 { 3977 compatible = "qcom,sa8775p-usb-hs-phy", 3978 "qcom,usb-snps-hs-5nm-phy"; 3979 reg = <0 0x088e6000 0 0x120>; 3980 clocks = <&gcc GCC_USB_CLKREF_EN>; 3981 clock-names = "ref"; 3982 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 3983 3984 #phy-cells = <0>; 3985 3986 status = "disabled"; 3987 }; 3988 3989 usb_1_qmpphy: phy@88ea000 { 3990 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 3991 reg = <0 0x088ea000 0 0x2000>; 3992 3993 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3994 <&gcc GCC_USB_CLKREF_EN>, 3995 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3996 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3997 clock-names = "aux", "ref", "com_aux", "pipe"; 3998 3999 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 4000 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 4001 reset-names = "phy", "phy_phy"; 4002 4003 power-domains = <&gcc USB30_SEC_GDSC>; 4004 4005 #clock-cells = <0>; 4006 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 4007 4008 #phy-cells = <0>; 4009 4010 status = "disabled"; 4011 }; 4012 4013 usb_1: usb@a800000 { 4014 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4015 reg = <0 0x0a800000 0 0xfc100>; 4016 4017 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4018 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4019 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4020 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4021 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4022 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4023 4024 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4025 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4026 assigned-clock-rates = <19200000>, <200000000>; 4027 4028 interrupts-extended = <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 4029 <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 4030 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 4031 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 4032 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 4033 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 4034 interrupt-names = "dwc_usb3", 4035 "pwr_event", 4036 "hs_phy_irq", 4037 "dp_hs_phy_irq", 4038 "dm_hs_phy_irq", 4039 "ss_phy_irq"; 4040 4041 power-domains = <&gcc USB30_SEC_GDSC>; 4042 required-opps = <&rpmhpd_opp_nom>; 4043 4044 resets = <&gcc GCC_USB30_SEC_BCR>; 4045 4046 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 4047 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4048 interconnect-names = "usb-ddr", "apps-usb"; 4049 4050 wakeup-source; 4051 4052 iommus = <&apps_smmu 0x0a0 0x0>; 4053 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 4054 phy-names = "usb2-phy", "usb3-phy"; 4055 snps,dis-u1-entry-quirk; 4056 snps,dis-u2-entry-quirk; 4057 4058 status = "disabled"; 4059 }; 4060 4061 usb_2_hsphy: phy@88e7000 { 4062 compatible = "qcom,sa8775p-usb-hs-phy", 4063 "qcom,usb-snps-hs-5nm-phy"; 4064 reg = <0 0x088e7000 0 0x120>; 4065 clocks = <&gcc GCC_USB_CLKREF_EN>; 4066 clock-names = "ref"; 4067 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 4068 4069 #phy-cells = <0>; 4070 4071 status = "disabled"; 4072 }; 4073 4074 usb_2: usb@a400000 { 4075 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4076 reg = <0 0x0a400000 0 0xfc100>; 4077 4078 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4079 <&gcc GCC_USB20_MASTER_CLK>, 4080 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4081 <&gcc GCC_USB20_SLEEP_CLK>, 4082 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 4083 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4084 4085 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4086 <&gcc GCC_USB20_MASTER_CLK>; 4087 assigned-clock-rates = <19200000>, <200000000>; 4088 4089 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 4090 <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 4091 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 4092 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 4093 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 4094 interrupt-names = "dwc_usb3", 4095 "pwr_event", 4096 "hs_phy_irq", 4097 "dp_hs_phy_irq", 4098 "dm_hs_phy_irq"; 4099 4100 power-domains = <&gcc USB20_PRIM_GDSC>; 4101 required-opps = <&rpmhpd_opp_nom>; 4102 4103 resets = <&gcc GCC_USB20_PRIM_BCR>; 4104 4105 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 4106 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 4107 interconnect-names = "usb-ddr", "apps-usb"; 4108 4109 wakeup-source; 4110 4111 iommus = <&apps_smmu 0x020 0x0>; 4112 phys = <&usb_2_hsphy>; 4113 phy-names = "usb2-phy"; 4114 snps,dis-u1-entry-quirk; 4115 snps,dis-u2-entry-quirk; 4116 4117 status = "disabled"; 4118 }; 4119 4120 tcsr_mutex: hwlock@1f40000 { 4121 compatible = "qcom,tcsr-mutex"; 4122 reg = <0x0 0x01f40000 0x0 0x20000>; 4123 #hwlock-cells = <1>; 4124 }; 4125 4126 tcsr: syscon@1fc0000 { 4127 compatible = "qcom,sa8775p-tcsr", "syscon"; 4128 reg = <0x0 0x1fc0000 0x0 0x30000>; 4129 }; 4130 4131 gpucc: clock-controller@3d90000 { 4132 compatible = "qcom,sa8775p-gpucc"; 4133 reg = <0x0 0x03d90000 0x0 0xa000>; 4134 clocks = <&rpmhcc RPMH_CXO_CLK>, 4135 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4136 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4137 clock-names = "bi_tcxo", 4138 "gcc_gpu_gpll0_clk_src", 4139 "gcc_gpu_gpll0_div_clk_src"; 4140 #clock-cells = <1>; 4141 #reset-cells = <1>; 4142 #power-domain-cells = <1>; 4143 }; 4144 4145 adreno_smmu: iommu@3da0000 { 4146 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 4147 "qcom,smmu-500", "arm,mmu-500"; 4148 reg = <0x0 0x03da0000 0x0 0x20000>; 4149 #iommu-cells = <2>; 4150 #global-interrupts = <2>; 4151 dma-coherent; 4152 power-domains = <&gpucc GPU_CC_CX_GDSC>; 4153 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4154 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4155 <&gpucc GPU_CC_AHB_CLK>, 4156 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4157 <&gpucc GPU_CC_CX_GMU_CLK>, 4158 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4159 <&gpucc GPU_CC_HUB_AON_CLK>; 4160 clock-names = "gcc_gpu_memnoc_gfx_clk", 4161 "gcc_gpu_snoc_dvm_gfx_clk", 4162 "gpu_cc_ahb_clk", 4163 "gpu_cc_hlos1_vote_gpu_smmu_clk", 4164 "gpu_cc_cx_gmu_clk", 4165 "gpu_cc_hub_cx_int_clk", 4166 "gpu_cc_hub_aon_clk"; 4167 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 4168 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4169 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4170 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4172 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4173 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4174 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4175 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4176 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4178 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 4179 }; 4180 4181 serdes0: phy@8901000 { 4182 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4183 reg = <0x0 0x08901000 0x0 0xe10>; 4184 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4185 clock-names = "sgmi_ref"; 4186 #phy-cells = <0>; 4187 status = "disabled"; 4188 }; 4189 4190 serdes1: phy@8902000 { 4191 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4192 reg = <0x0 0x08902000 0x0 0xe10>; 4193 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4194 clock-names = "sgmi_ref"; 4195 #phy-cells = <0>; 4196 status = "disabled"; 4197 }; 4198 4199 pmu@9091000 { 4200 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4201 reg = <0x0 0x9091000 0x0 0x1000>; 4202 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 4203 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 4204 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4205 4206 operating-points-v2 = <&llcc_bwmon_opp_table>; 4207 4208 llcc_bwmon_opp_table: opp-table { 4209 compatible = "operating-points-v2"; 4210 4211 opp-0 { 4212 opp-peak-kBps = <762000>; 4213 }; 4214 4215 opp-1 { 4216 opp-peak-kBps = <1720000>; 4217 }; 4218 4219 opp-2 { 4220 opp-peak-kBps = <2086000>; 4221 }; 4222 4223 opp-3 { 4224 opp-peak-kBps = <2601000>; 4225 }; 4226 4227 opp-4 { 4228 opp-peak-kBps = <2929000>; 4229 }; 4230 4231 opp-5 { 4232 opp-peak-kBps = <5931000>; 4233 }; 4234 4235 opp-6 { 4236 opp-peak-kBps = <6515000>; 4237 }; 4238 4239 opp-7 { 4240 opp-peak-kBps = <7984000>; 4241 }; 4242 4243 opp-8 { 4244 opp-peak-kBps = <10437000>; 4245 }; 4246 4247 opp-9 { 4248 opp-peak-kBps = <12195000>; 4249 }; 4250 }; 4251 }; 4252 4253 pmu@90b5400 { 4254 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4255 reg = <0x0 0x90b5400 0x0 0x600>; 4256 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4257 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4258 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4259 4260 operating-points-v2 = <&cpu_bwmon_opp_table>; 4261 4262 cpu_bwmon_opp_table: opp-table { 4263 compatible = "operating-points-v2"; 4264 4265 opp-0 { 4266 opp-peak-kBps = <9155000>; 4267 }; 4268 4269 opp-1 { 4270 opp-peak-kBps = <12298000>; 4271 }; 4272 4273 opp-2 { 4274 opp-peak-kBps = <14236000>; 4275 }; 4276 4277 opp-3 { 4278 opp-peak-kBps = <16265000>; 4279 }; 4280 }; 4281 4282 }; 4283 4284 pmu@90b6400 { 4285 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4286 reg = <0x0 0x90b6400 0x0 0x600>; 4287 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4288 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4289 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4290 4291 operating-points-v2 = <&cpu_bwmon_opp_table>; 4292 }; 4293 4294 llcc: system-cache-controller@9200000 { 4295 compatible = "qcom,sa8775p-llcc"; 4296 reg = <0x0 0x09200000 0x0 0x80000>, 4297 <0x0 0x09300000 0x0 0x80000>, 4298 <0x0 0x09400000 0x0 0x80000>, 4299 <0x0 0x09500000 0x0 0x80000>, 4300 <0x0 0x09600000 0x0 0x80000>, 4301 <0x0 0x09700000 0x0 0x80000>, 4302 <0x0 0x09a00000 0x0 0x80000>; 4303 reg-names = "llcc0_base", 4304 "llcc1_base", 4305 "llcc2_base", 4306 "llcc3_base", 4307 "llcc4_base", 4308 "llcc5_base", 4309 "llcc_broadcast_base"; 4310 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 4311 }; 4312 4313 iris: video-codec@aa00000 { 4314 compatible = "qcom,sa8775p-iris", "qcom,sm8550-iris"; 4315 4316 reg = <0x0 0x0aa00000 0x0 0xf0000>; 4317 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4318 4319 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 4320 <&videocc VIDEO_CC_MVS0_GDSC>, 4321 <&rpmhpd SA8775P_MX>, 4322 <&rpmhpd SA8775P_MMCX>; 4323 power-domain-names = "venus", 4324 "vcodec0", 4325 "mxc", 4326 "mmcx"; 4327 operating-points-v2 = <&iris_opp_table>; 4328 4329 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4330 <&videocc VIDEO_CC_MVS0C_CLK>, 4331 <&videocc VIDEO_CC_MVS0_CLK>; 4332 clock-names = "iface", 4333 "core", 4334 "vcodec0_core"; 4335 4336 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4337 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4338 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4339 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4340 interconnect-names = "cpu-cfg", 4341 "video-mem"; 4342 4343 memory-region = <&pil_video_mem>; 4344 4345 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 4346 reset-names = "bus"; 4347 4348 iommus = <&apps_smmu 0x0880 0x0400>, 4349 <&apps_smmu 0x0887 0x0400>; 4350 dma-coherent; 4351 4352 status = "disabled"; 4353 4354 iris_opp_table: opp-table { 4355 compatible = "operating-points-v2"; 4356 4357 opp-366000000 { 4358 opp-hz = /bits/ 64 <366000000>; 4359 required-opps = <&rpmhpd_opp_svs_l1>, 4360 <&rpmhpd_opp_svs_l1>; 4361 }; 4362 4363 opp-444000000 { 4364 opp-hz = /bits/ 64 <444000000>; 4365 required-opps = <&rpmhpd_opp_nom>, 4366 <&rpmhpd_opp_nom>; 4367 }; 4368 4369 opp-533000000 { 4370 opp-hz = /bits/ 64 <533000000>; 4371 required-opps = <&rpmhpd_opp_turbo>, 4372 <&rpmhpd_opp_turbo>; 4373 }; 4374 4375 opp-560000000 { 4376 opp-hz = /bits/ 64 <560000000>; 4377 required-opps = <&rpmhpd_opp_turbo_l1>, 4378 <&rpmhpd_opp_turbo_l1>; 4379 }; 4380 }; 4381 }; 4382 4383 videocc: clock-controller@abf0000 { 4384 compatible = "qcom,sa8775p-videocc"; 4385 reg = <0x0 0x0abf0000 0x0 0x10000>; 4386 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4387 <&rpmhcc RPMH_CXO_CLK>, 4388 <&rpmhcc RPMH_CXO_CLK_A>, 4389 <&sleep_clk>; 4390 power-domains = <&rpmhpd SA8775P_MMCX>; 4391 #clock-cells = <1>; 4392 #reset-cells = <1>; 4393 #power-domain-cells = <1>; 4394 }; 4395 4396 cci0: cci@ac13000 { 4397 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4398 reg = <0x0 0x0ac13000 0x0 0x1000>; 4399 4400 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4401 4402 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4403 4404 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4405 <&camcc CAM_CC_CPAS_AHB_CLK>, 4406 <&camcc CAM_CC_CCI_0_CLK>; 4407 clock-names = "camnoc_axi", 4408 "cpas_ahb", 4409 "cci"; 4410 4411 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 4412 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 4413 pinctrl-names = "default", "sleep"; 4414 4415 #address-cells = <1>; 4416 #size-cells = <0>; 4417 4418 status = "disabled"; 4419 4420 cci0_i2c0: i2c-bus@0 { 4421 reg = <0>; 4422 clock-frequency = <1000000>; 4423 #address-cells = <1>; 4424 #size-cells = <0>; 4425 }; 4426 4427 cci0_i2c1: i2c-bus@1 { 4428 reg = <1>; 4429 clock-frequency = <1000000>; 4430 #address-cells = <1>; 4431 #size-cells = <0>; 4432 }; 4433 }; 4434 4435 cci1: cci@ac14000 { 4436 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4437 reg = <0x0 0x0ac14000 0x0 0x1000>; 4438 4439 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4440 4441 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4442 4443 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4444 <&camcc CAM_CC_CPAS_AHB_CLK>, 4445 <&camcc CAM_CC_CCI_1_CLK>; 4446 clock-names = "camnoc_axi", 4447 "cpas_ahb", 4448 "cci"; 4449 4450 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 4451 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 4452 pinctrl-names = "default", "sleep"; 4453 4454 #address-cells = <1>; 4455 #size-cells = <0>; 4456 4457 status = "disabled"; 4458 4459 cci1_i2c0: i2c-bus@0 { 4460 reg = <0>; 4461 clock-frequency = <1000000>; 4462 #address-cells = <1>; 4463 #size-cells = <0>; 4464 }; 4465 4466 cci1_i2c1: i2c-bus@1 { 4467 reg = <1>; 4468 clock-frequency = <1000000>; 4469 #address-cells = <1>; 4470 #size-cells = <0>; 4471 }; 4472 }; 4473 4474 cci2: cci@ac15000 { 4475 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4476 reg = <0x0 0x0ac15000 0x0 0x1000>; 4477 4478 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 4479 4480 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4481 4482 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4483 <&camcc CAM_CC_CPAS_AHB_CLK>, 4484 <&camcc CAM_CC_CCI_2_CLK>; 4485 clock-names = "camnoc_axi", 4486 "cpas_ahb", 4487 "cci"; 4488 4489 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 4490 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 4491 pinctrl-names = "default", "sleep"; 4492 4493 #address-cells = <1>; 4494 #size-cells = <0>; 4495 4496 status = "disabled"; 4497 4498 cci2_i2c0: i2c-bus@0 { 4499 reg = <0>; 4500 clock-frequency = <1000000>; 4501 #address-cells = <1>; 4502 #size-cells = <0>; 4503 }; 4504 4505 cci2_i2c1: i2c-bus@1 { 4506 reg = <1>; 4507 clock-frequency = <1000000>; 4508 #address-cells = <1>; 4509 #size-cells = <0>; 4510 }; 4511 }; 4512 4513 cci3: cci@ac16000 { 4514 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4515 reg = <0x0 0x0ac16000 0x0 0x1000>; 4516 4517 interrupts = <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>; 4518 4519 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4520 4521 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4522 <&camcc CAM_CC_CPAS_AHB_CLK>, 4523 <&camcc CAM_CC_CCI_3_CLK>; 4524 clock-names = "camnoc_axi", 4525 "cpas_ahb", 4526 "cci"; 4527 4528 pinctrl-0 = <&cci3_0_default &cci3_1_default>; 4529 pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>; 4530 pinctrl-names = "default", "sleep"; 4531 4532 #address-cells = <1>; 4533 #size-cells = <0>; 4534 4535 status = "disabled"; 4536 4537 cci3_i2c0: i2c-bus@0 { 4538 reg = <0>; 4539 clock-frequency = <1000000>; 4540 #address-cells = <1>; 4541 #size-cells = <0>; 4542 }; 4543 4544 cci3_i2c1: i2c-bus@1 { 4545 reg = <1>; 4546 clock-frequency = <1000000>; 4547 #address-cells = <1>; 4548 #size-cells = <0>; 4549 }; 4550 }; 4551 4552 camss: isp@ac78000 { 4553 compatible = "qcom,sa8775p-camss"; 4554 4555 reg = <0x0 0xac78000 0x0 0x1000>, 4556 <0x0 0xac7a000 0x0 0x0f00>, 4557 <0x0 0xac7c000 0x0 0x0f00>, 4558 <0x0 0xac84000 0x0 0x0f00>, 4559 <0x0 0xac88000 0x0 0x0f00>, 4560 <0x0 0xac8c000 0x0 0x0f00>, 4561 <0x0 0xac90000 0x0 0x0f00>, 4562 <0x0 0xac94000 0x0 0x0f00>, 4563 <0x0 0xac9c000 0x0 0x2000>, 4564 <0x0 0xac9e000 0x0 0x2000>, 4565 <0x0 0xaca0000 0x0 0x2000>, 4566 <0x0 0xaca2000 0x0 0x2000>, 4567 <0x0 0xacac000 0x0 0x0400>, 4568 <0x0 0xacad000 0x0 0x0400>, 4569 <0x0 0xacae000 0x0 0x0400>, 4570 <0x0 0xac4d000 0x0 0xd000>, 4571 <0x0 0xac5a000 0x0 0xd000>, 4572 <0x0 0xac85000 0x0 0x0d00>, 4573 <0x0 0xac89000 0x0 0x0d00>, 4574 <0x0 0xac8d000 0x0 0x0d00>, 4575 <0x0 0xac91000 0x0 0x0d00>, 4576 <0x0 0xac95000 0x0 0x0d00>; 4577 reg-names = "csid_wrapper", 4578 "csid0", 4579 "csid1", 4580 "csid_lite0", 4581 "csid_lite1", 4582 "csid_lite2", 4583 "csid_lite3", 4584 "csid_lite4", 4585 "csiphy0", 4586 "csiphy1", 4587 "csiphy2", 4588 "csiphy3", 4589 "tpg0", 4590 "tpg1", 4591 "tpg2", 4592 "vfe0", 4593 "vfe1", 4594 "vfe_lite0", 4595 "vfe_lite1", 4596 "vfe_lite2", 4597 "vfe_lite3", 4598 "vfe_lite4"; 4599 4600 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4601 <&camcc CAM_CC_CORE_AHB_CLK>, 4602 <&camcc CAM_CC_CPAS_AHB_CLK>, 4603 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 4604 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 4605 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 4606 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 4607 <&camcc CAM_CC_CSID_CLK>, 4608 <&camcc CAM_CC_CSIPHY0_CLK>, 4609 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4610 <&camcc CAM_CC_CSIPHY1_CLK>, 4611 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4612 <&camcc CAM_CC_CSIPHY2_CLK>, 4613 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4614 <&camcc CAM_CC_CSIPHY3_CLK>, 4615 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4616 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 4617 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4618 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4619 <&camcc CAM_CC_ICP_AHB_CLK>, 4620 <&camcc CAM_CC_IFE_0_CLK>, 4621 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 4622 <&camcc CAM_CC_IFE_1_CLK>, 4623 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 4624 <&camcc CAM_CC_IFE_LITE_CLK>, 4625 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4626 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4627 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4628 clock-names = "camnoc_axi", 4629 "core_ahb", 4630 "cpas_ahb", 4631 "cpas_fast_ahb_clk", 4632 "cpas_vfe_lite", 4633 "cpas_vfe0", 4634 "cpas_vfe1", 4635 "csid", 4636 "csiphy0", 4637 "csiphy0_timer", 4638 "csiphy1", 4639 "csiphy1_timer", 4640 "csiphy2", 4641 "csiphy2_timer", 4642 "csiphy3", 4643 "csiphy3_timer", 4644 "csiphy_rx", 4645 "gcc_axi_hf", 4646 "gcc_axi_sf", 4647 "icp_ahb", 4648 "vfe0", 4649 "vfe0_fast_ahb", 4650 "vfe1", 4651 "vfe1_fast_ahb", 4652 "vfe_lite", 4653 "vfe_lite_ahb", 4654 "vfe_lite_cphy_rx", 4655 "vfe_lite_csid"; 4656 4657 interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, 4658 <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, 4659 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4660 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4661 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 4662 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 4663 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 4664 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4665 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4666 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4667 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4668 <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, 4669 <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, 4670 <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, 4671 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4672 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4673 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4674 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 4675 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 4676 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 4677 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; 4678 interrupt-names = "csid0", 4679 "csid1", 4680 "csid_lite0", 4681 "csid_lite1", 4682 "csid_lite2", 4683 "csid_lite3", 4684 "csid_lite4", 4685 "csiphy0", 4686 "csiphy1", 4687 "csiphy2", 4688 "csiphy3", 4689 "tpg0", 4690 "tpg1", 4691 "tpg2", 4692 "vfe0", 4693 "vfe1", 4694 "vfe_lite0", 4695 "vfe_lite1", 4696 "vfe_lite2", 4697 "vfe_lite3", 4698 "vfe_lite4"; 4699 4700 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4701 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4702 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 4703 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4704 interconnect-names = "ahb", 4705 "hf_0"; 4706 4707 iommus = <&apps_smmu 0x3400 0x20>; 4708 4709 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4710 power-domain-names = "top"; 4711 4712 status = "disabled"; 4713 4714 ports { 4715 #address-cells = <1>; 4716 #size-cells = <0>; 4717 4718 port@0 { 4719 reg = <0>; 4720 }; 4721 4722 port@1 { 4723 reg = <1>; 4724 }; 4725 4726 port@2 { 4727 reg = <2>; 4728 }; 4729 4730 port@3 { 4731 reg = <3>; 4732 }; 4733 }; 4734 }; 4735 4736 camcc: clock-controller@ade0000 { 4737 compatible = "qcom,sa8775p-camcc"; 4738 reg = <0x0 0x0ade0000 0x0 0x20000>; 4739 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4740 <&rpmhcc RPMH_CXO_CLK>, 4741 <&rpmhcc RPMH_CXO_CLK_A>, 4742 <&sleep_clk>; 4743 power-domains = <&rpmhpd SA8775P_MMCX>; 4744 #clock-cells = <1>; 4745 #reset-cells = <1>; 4746 #power-domain-cells = <1>; 4747 }; 4748 4749 mdss0: display-subsystem@ae00000 { 4750 compatible = "qcom,sa8775p-mdss"; 4751 reg = <0x0 0x0ae00000 0x0 0x1000>; 4752 reg-names = "mdss"; 4753 4754 /* same path used twice */ 4755 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 4756 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4757 <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS 4758 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4759 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4760 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4761 interconnect-names = "mdp0-mem", 4762 "mdp1-mem", 4763 "cpu-cfg"; 4764 4765 resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; 4766 4767 power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; 4768 4769 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4770 <&gcc GCC_DISP_HF_AXI_CLK>, 4771 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; 4772 4773 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 4774 interrupt-controller; 4775 #interrupt-cells = <1>; 4776 4777 iommus = <&apps_smmu 0x1000 0x402>; 4778 4779 #address-cells = <2>; 4780 #size-cells = <2>; 4781 ranges; 4782 4783 status = "disabled"; 4784 4785 mdss0_mdp: display-controller@ae01000 { 4786 compatible = "qcom,sa8775p-dpu"; 4787 reg = <0x0 0x0ae01000 0x0 0x8f000>, 4788 <0x0 0x0aeb0000 0x0 0x3000>; 4789 reg-names = "mdp", "vbif"; 4790 4791 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4792 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4793 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 4794 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, 4795 <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 4796 clock-names = "nrt_bus", 4797 "iface", 4798 "lut", 4799 "core", 4800 "vsync"; 4801 4802 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 4803 assigned-clock-rates = <19200000>; 4804 4805 operating-points-v2 = <&mdss0_mdp_opp_table>; 4806 power-domains = <&rpmhpd SA8775P_MMCX>; 4807 4808 interrupt-parent = <&mdss0>; 4809 interrupts = <0>; 4810 4811 ports { 4812 #address-cells = <1>; 4813 #size-cells = <0>; 4814 4815 port@0 { 4816 reg = <0>; 4817 4818 dpu_intf0_out: endpoint { 4819 remote-endpoint = <&mdss0_dp0_in>; 4820 }; 4821 }; 4822 4823 port@1 { 4824 reg = <1>; 4825 4826 dpu_intf4_out: endpoint { 4827 remote-endpoint = <&mdss0_dp1_in>; 4828 }; 4829 }; 4830 4831 port@2 { 4832 reg = <2>; 4833 4834 dpu_intf1_out: endpoint { 4835 remote-endpoint = <&mdss0_dsi0_in>; 4836 }; 4837 }; 4838 4839 port@3 { 4840 reg = <3>; 4841 4842 dpu_intf2_out: endpoint { 4843 remote-endpoint = <&mdss0_dsi1_in>; 4844 }; 4845 }; 4846 }; 4847 4848 mdss0_mdp_opp_table: opp-table { 4849 compatible = "operating-points-v2"; 4850 4851 opp-375000000 { 4852 opp-hz = /bits/ 64 <375000000>; 4853 required-opps = <&rpmhpd_opp_svs_l1>; 4854 }; 4855 4856 opp-500000000 { 4857 opp-hz = /bits/ 64 <500000000>; 4858 required-opps = <&rpmhpd_opp_nom>; 4859 }; 4860 4861 opp-575000000 { 4862 opp-hz = /bits/ 64 <575000000>; 4863 required-opps = <&rpmhpd_opp_turbo>; 4864 }; 4865 4866 opp-650000000 { 4867 opp-hz = /bits/ 64 <650000000>; 4868 required-opps = <&rpmhpd_opp_turbo_l1>; 4869 }; 4870 }; 4871 }; 4872 4873 mdss0_dsi0: dsi@ae94000 { 4874 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4875 reg = <0x0 0x0ae94000 0x0 0x400>; 4876 reg-names = "dsi_ctrl"; 4877 4878 interrupt-parent = <&mdss0>; 4879 interrupts = <4>; 4880 4881 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK>, 4882 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, 4883 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK>, 4884 <&dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK>, 4885 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4886 <&gcc GCC_DISP_HF_AXI_CLK>; 4887 clock-names = "byte", 4888 "byte_intf", 4889 "pixel", 4890 "core", 4891 "iface", 4892 "bus"; 4893 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, 4894 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; 4895 assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 4896 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; 4897 phys = <&mdss0_dsi0_phy>; 4898 4899 operating-points-v2 = <&mdss_dsi_opp_table>; 4900 power-domains = <&rpmhpd SA8775P_MMCX>; 4901 4902 #address-cells = <1>; 4903 #size-cells = <0>; 4904 4905 status = "disabled"; 4906 4907 ports { 4908 #address-cells = <1>; 4909 #size-cells = <0>; 4910 4911 port@0 { 4912 reg = <0>; 4913 4914 mdss0_dsi0_in: endpoint { 4915 remote-endpoint = <&dpu_intf1_out>; 4916 }; 4917 }; 4918 4919 port@1 { 4920 reg = <1>; 4921 4922 mdss0_dsi0_out: endpoint{ }; 4923 }; 4924 }; 4925 4926 mdss_dsi_opp_table: opp-table { 4927 compatible = "operating-points-v2"; 4928 4929 opp-358000000 { 4930 opp-hz = /bits/ 64 <358000000>; 4931 required-opps = <&rpmhpd_opp_svs_l1>; 4932 }; 4933 }; 4934 }; 4935 4936 mdss0_dsi0_phy: phy@ae94400 { 4937 compatible = "qcom,sa8775p-dsi-phy-5nm"; 4938 reg = <0x0 0x0ae94400 0x0 0x200>, 4939 <0x0 0x0ae94600 0x0 0x280>, 4940 <0x0 0x0ae94900 0x0 0x27c>; 4941 reg-names = "dsi_phy", 4942 "dsi_phy_lane", 4943 "dsi_pll"; 4944 4945 #clock-cells = <1>; 4946 #phy-cells = <0>; 4947 4948 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4949 <&rpmhcc RPMH_CXO_CLK>; 4950 clock-names = "iface", "ref"; 4951 4952 status = "disabled"; 4953 }; 4954 4955 mdss0_dsi1: dsi@ae96000 { 4956 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4957 reg = <0x0 0x0ae96000 0x0 0x400>; 4958 reg-names = "dsi_ctrl"; 4959 4960 interrupt-parent = <&mdss0>; 4961 interrupts = <5>; 4962 4963 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK>, 4964 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK>, 4965 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK>, 4966 <&dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK>, 4967 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4968 <&gcc GCC_DISP_HF_AXI_CLK>; 4969 clock-names = "byte", 4970 "byte_intf", 4971 "pixel", 4972 "core", 4973 "iface", 4974 "bus"; 4975 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>, 4976 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC>; 4977 assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 4978 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 4979 phys = <&mdss0_dsi1_phy>; 4980 4981 operating-points-v2 = <&mdss_dsi_opp_table>; 4982 power-domains = <&rpmhpd SA8775P_MMCX>; 4983 4984 #address-cells = <1>; 4985 #size-cells = <0>; 4986 4987 status = "disabled"; 4988 4989 ports { 4990 #address-cells = <1>; 4991 #size-cells = <0>; 4992 4993 port@0 { 4994 reg = <0>; 4995 4996 mdss0_dsi1_in: endpoint { 4997 remote-endpoint = <&dpu_intf2_out>; 4998 }; 4999 }; 5000 5001 port@1 { 5002 reg = <1>; 5003 5004 mdss0_dsi1_out: endpoint { }; 5005 }; 5006 }; 5007 }; 5008 5009 mdss0_dsi1_phy: phy@ae96400 { 5010 compatible = "qcom,sa8775p-dsi-phy-5nm"; 5011 reg = <0x0 0x0ae96400 0x0 0x200>, 5012 <0x0 0x0ae96600 0x0 0x280>, 5013 <0x0 0x0ae96900 0x0 0x27c>; 5014 reg-names = "dsi_phy", 5015 "dsi_phy_lane", 5016 "dsi_pll"; 5017 5018 #clock-cells = <1>; 5019 #phy-cells = <0>; 5020 5021 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5022 <&rpmhcc RPMH_CXO_CLK>; 5023 clock-names = "iface", "ref"; 5024 5025 status = "disabled"; 5026 }; 5027 5028 mdss0_dp0_phy: phy@aec2a00 { 5029 compatible = "qcom,sa8775p-edp-phy"; 5030 5031 reg = <0x0 0x0aec2a00 0x0 0x200>, 5032 <0x0 0x0aec2200 0x0 0xd0>, 5033 <0x0 0x0aec2600 0x0 0xd0>, 5034 <0x0 0x0aec2000 0x0 0x1c8>; 5035 5036 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5037 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; 5038 clock-names = "aux", 5039 "cfg_ahb"; 5040 5041 #clock-cells = <1>; 5042 #phy-cells = <0>; 5043 5044 status = "disabled"; 5045 }; 5046 5047 mdss0_dp1_phy: phy@aec5a00 { 5048 compatible = "qcom,sa8775p-edp-phy"; 5049 5050 reg = <0x0 0x0aec5a00 0x0 0x200>, 5051 <0x0 0x0aec5200 0x0 0xd0>, 5052 <0x0 0x0aec5600 0x0 0xd0>, 5053 <0x0 0x0aec5000 0x0 0x1c8>; 5054 5055 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 5056 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; 5057 clock-names = "aux", 5058 "cfg_ahb"; 5059 5060 #clock-cells = <1>; 5061 #phy-cells = <0>; 5062 5063 status = "disabled"; 5064 }; 5065 5066 mdss0_dp0: displayport-controller@af54000 { 5067 compatible = "qcom,sa8775p-dp"; 5068 5069 reg = <0x0 0x0af54000 0x0 0x104>, 5070 <0x0 0x0af54200 0x0 0x0c0>, 5071 <0x0 0x0af55000 0x0 0x770>, 5072 <0x0 0x0af56000 0x0 0x09c>, 5073 <0x0 0x0af57000 0x0 0x09c>, 5074 <0x0 0x0af58000 0x0 0x09c>, 5075 <0x0 0x0af59000 0x0 0x09c>, 5076 <0x0 0x0af5a000 0x0 0x23c>, 5077 <0x0 0x0af5b000 0x0 0x23c>; 5078 5079 interrupt-parent = <&mdss0>; 5080 interrupts = <12>; 5081 5082 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5083 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5084 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 5085 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5086 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5087 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, 5088 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, 5089 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; 5090 clock-names = "core_iface", 5091 "core_aux", 5092 "ctrl_link", 5093 "ctrl_link_iface", 5094 "stream_pixel", 5095 "stream_1_pixel", 5096 "stream_2_pixel", 5097 "stream_3_pixel"; 5098 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5099 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5100 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, 5101 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, 5102 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; 5103 assigned-clock-parents = <&mdss0_dp0_phy 0>, 5104 <&mdss0_dp0_phy 1>, 5105 <&mdss0_dp0_phy 1>, 5106 <&mdss0_dp0_phy 1>, 5107 <&mdss0_dp0_phy 1>; 5108 phys = <&mdss0_dp0_phy>; 5109 phy-names = "dp"; 5110 5111 operating-points-v2 = <&dp_opp_table>; 5112 power-domains = <&rpmhpd SA8775P_MMCX>; 5113 5114 #sound-dai-cells = <0>; 5115 5116 status = "disabled"; 5117 5118 ports { 5119 #address-cells = <1>; 5120 #size-cells = <0>; 5121 5122 port@0 { 5123 reg = <0>; 5124 5125 mdss0_dp0_in: endpoint { 5126 remote-endpoint = <&dpu_intf0_out>; 5127 }; 5128 }; 5129 5130 port@1 { 5131 reg = <1>; 5132 5133 mdss0_dp0_out: endpoint { }; 5134 }; 5135 }; 5136 5137 dp_opp_table: opp-table { 5138 compatible = "operating-points-v2"; 5139 5140 opp-160000000 { 5141 opp-hz = /bits/ 64 <160000000>; 5142 required-opps = <&rpmhpd_opp_low_svs>; 5143 }; 5144 5145 opp-270000000 { 5146 opp-hz = /bits/ 64 <270000000>; 5147 required-opps = <&rpmhpd_opp_svs>; 5148 }; 5149 5150 opp-540000000 { 5151 opp-hz = /bits/ 64 <540000000>; 5152 required-opps = <&rpmhpd_opp_svs_l1>; 5153 }; 5154 5155 opp-810000000 { 5156 opp-hz = /bits/ 64 <810000000>; 5157 required-opps = <&rpmhpd_opp_nom>; 5158 }; 5159 }; 5160 }; 5161 5162 mdss0_dp1: displayport-controller@af5c000 { 5163 compatible = "qcom,sa8775p-dp"; 5164 5165 reg = <0x0 0x0af5c000 0x0 0x104>, 5166 <0x0 0x0af5c200 0x0 0x0c0>, 5167 <0x0 0x0af5d000 0x0 0x770>, 5168 <0x0 0x0af5e000 0x0 0x09c>, 5169 <0x0 0x0af5f000 0x0 0x09c>, 5170 <0x0 0x0af60000 0x0 0x09c>, 5171 <0x0 0x0af61000 0x0 0x09c>, 5172 <0x0 0x0af62000 0x0 0x23c>, 5173 <0x0 0x0af63000 0x0 0x23c>; 5174 5175 interrupt-parent = <&mdss0>; 5176 interrupts = <13>; 5177 5178 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5179 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 5180 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, 5181 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5182 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5183 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5184 clock-names = "core_iface", 5185 "core_aux", 5186 "ctrl_link", 5187 "ctrl_link_iface", 5188 "stream_pixel", 5189 "stream_1_pixel"; 5190 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5191 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5192 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5193 assigned-clock-parents = <&mdss0_dp1_phy 0>, 5194 <&mdss0_dp1_phy 1>, 5195 <&mdss0_dp1_phy 1>; 5196 phys = <&mdss0_dp1_phy>; 5197 phy-names = "dp"; 5198 5199 operating-points-v2 = <&dp1_opp_table>; 5200 power-domains = <&rpmhpd SA8775P_MMCX>; 5201 5202 #sound-dai-cells = <0>; 5203 5204 status = "disabled"; 5205 5206 ports { 5207 #address-cells = <1>; 5208 #size-cells = <0>; 5209 5210 port@0 { 5211 reg = <0>; 5212 5213 mdss0_dp1_in: endpoint { 5214 remote-endpoint = <&dpu_intf4_out>; 5215 }; 5216 }; 5217 5218 port@1 { 5219 reg = <1>; 5220 5221 mdss0_dp1_out: endpoint { }; 5222 }; 5223 }; 5224 5225 dp1_opp_table: opp-table { 5226 compatible = "operating-points-v2"; 5227 5228 opp-160000000 { 5229 opp-hz = /bits/ 64 <160000000>; 5230 required-opps = <&rpmhpd_opp_low_svs>; 5231 }; 5232 5233 opp-270000000 { 5234 opp-hz = /bits/ 64 <270000000>; 5235 required-opps = <&rpmhpd_opp_svs>; 5236 }; 5237 5238 opp-540000000 { 5239 opp-hz = /bits/ 64 <540000000>; 5240 required-opps = <&rpmhpd_opp_svs_l1>; 5241 }; 5242 5243 opp-810000000 { 5244 opp-hz = /bits/ 64 <810000000>; 5245 required-opps = <&rpmhpd_opp_nom>; 5246 }; 5247 }; 5248 }; 5249 }; 5250 5251 dispcc0: clock-controller@af00000 { 5252 compatible = "qcom,sa8775p-dispcc0"; 5253 reg = <0x0 0x0af00000 0x0 0x20000>; 5254 clocks = <&gcc GCC_DISP_AHB_CLK>, 5255 <&rpmhcc RPMH_CXO_CLK>, 5256 <&rpmhcc RPMH_CXO_CLK_A>, 5257 <&sleep_clk>, 5258 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, 5259 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>, 5260 <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 5261 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, 5262 <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5263 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5264 power-domains = <&rpmhpd SA8775P_MMCX>; 5265 #clock-cells = <1>; 5266 #reset-cells = <1>; 5267 #power-domain-cells = <1>; 5268 }; 5269 5270 pdc: interrupt-controller@b220000 { 5271 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 5272 reg = <0x0 0x0b220000 0x0 0x30000>, 5273 <0x0 0x17c000f0 0x0 0x64>; 5274 qcom,pdc-ranges = <0 480 40>, 5275 <40 140 14>, 5276 <54 263 1>, 5277 <55 306 4>, 5278 <59 312 3>, 5279 <62 374 2>, 5280 <64 434 2>, 5281 <66 438 2>, 5282 <70 520 1>, 5283 <73 523 1>, 5284 <118 568 6>, 5285 <124 609 3>, 5286 <159 638 1>, 5287 <160 720 3>, 5288 <169 728 30>, 5289 <199 416 2>, 5290 <201 449 1>, 5291 <202 89 1>, 5292 <203 451 1>, 5293 <204 462 1>, 5294 <205 264 1>, 5295 <206 579 1>, 5296 <207 653 1>, 5297 <208 656 1>, 5298 <209 659 1>, 5299 <210 122 1>, 5300 <211 699 1>, 5301 <212 705 1>, 5302 <213 450 1>, 5303 <214 643 2>, 5304 <216 646 5>, 5305 <221 390 5>, 5306 <226 700 2>, 5307 <228 440 1>, 5308 <229 663 1>, 5309 <230 524 2>, 5310 <232 612 3>, 5311 <235 723 5>; 5312 #interrupt-cells = <2>; 5313 interrupt-parent = <&intc>; 5314 interrupt-controller; 5315 }; 5316 5317 tsens2: thermal-sensor@c251000 { 5318 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5319 reg = <0x0 0x0c251000 0x0 0x1ff>, 5320 <0x0 0x0c224000 0x0 0x8>; 5321 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 5322 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 5323 #qcom,sensors = <13>; 5324 interrupt-names = "uplow", "critical"; 5325 #thermal-sensor-cells = <1>; 5326 }; 5327 5328 tsens3: thermal-sensor@c252000 { 5329 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5330 reg = <0x0 0x0c252000 0x0 0x1ff>, 5331 <0x0 0x0c225000 0x0 0x8>; 5332 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 5333 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 5334 #qcom,sensors = <13>; 5335 interrupt-names = "uplow", "critical"; 5336 #thermal-sensor-cells = <1>; 5337 }; 5338 5339 tsens0: thermal-sensor@c263000 { 5340 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5341 reg = <0x0 0x0c263000 0x0 0x1ff>, 5342 <0x0 0x0c222000 0x0 0x8>; 5343 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5344 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5345 #qcom,sensors = <12>; 5346 interrupt-names = "uplow", "critical"; 5347 #thermal-sensor-cells = <1>; 5348 }; 5349 5350 tsens1: thermal-sensor@c265000 { 5351 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5352 reg = <0x0 0x0c265000 0x0 0x1ff>, 5353 <0x0 0x0c223000 0x0 0x8>; 5354 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5355 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5356 #qcom,sensors = <12>; 5357 interrupt-names = "uplow", "critical"; 5358 #thermal-sensor-cells = <1>; 5359 }; 5360 5361 aoss_qmp: power-management@c300000 { 5362 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 5363 reg = <0x0 0x0c300000 0x0 0x400>; 5364 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5365 IPCC_MPROC_SIGNAL_GLINK_QMP 5366 IRQ_TYPE_EDGE_RISING>; 5367 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5368 #clock-cells = <0>; 5369 }; 5370 5371 sram@c3f0000 { 5372 compatible = "qcom,rpmh-stats"; 5373 reg = <0x0 0x0c3f0000 0x0 0x400>; 5374 }; 5375 5376 spmi_bus: spmi@c440000 { 5377 compatible = "qcom,spmi-pmic-arb"; 5378 reg = <0x0 0x0c440000 0x0 0x1100>, 5379 <0x0 0x0c600000 0x0 0x2000000>, 5380 <0x0 0x0e600000 0x0 0x100000>, 5381 <0x0 0x0e700000 0x0 0xa0000>, 5382 <0x0 0x0c40a000 0x0 0x26000>; 5383 reg-names = "core", 5384 "chnls", 5385 "obsrvr", 5386 "intr", 5387 "cnfg"; 5388 qcom,channel = <0>; 5389 qcom,ee = <0>; 5390 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5391 interrupt-names = "periph_irq"; 5392 interrupt-controller; 5393 #interrupt-cells = <4>; 5394 #address-cells = <2>; 5395 #size-cells = <0>; 5396 }; 5397 5398 tlmm: pinctrl@f000000 { 5399 compatible = "qcom,sa8775p-tlmm"; 5400 reg = <0x0 0x0f000000 0x0 0x1000000>; 5401 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5402 gpio-controller; 5403 #gpio-cells = <2>; 5404 interrupt-controller; 5405 #interrupt-cells = <2>; 5406 gpio-ranges = <&tlmm 0 0 149>; 5407 wakeup-parent = <&pdc>; 5408 5409 dp0_hot_plug_det: dp0-hot-plug-det-state { 5410 pins = "gpio101"; 5411 function = "edp0_hot"; 5412 bias-disable; 5413 }; 5414 5415 dp1_hot_plug_det: dp1-hot-plug-det-state { 5416 pins = "gpio102"; 5417 function = "edp1_hot"; 5418 bias-disable; 5419 }; 5420 5421 hs0_mi2s_active: hs0-mi2s-active-state { 5422 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 5423 function = "hs0_mi2s"; 5424 drive-strength = <8>; 5425 bias-disable; 5426 }; 5427 5428 hs2_mi2s_active: hs2-mi2s-active-state { 5429 pins = "gpio122", "gpio123", "gpio124", "gpio125"; 5430 function = "hs2_mi2s"; 5431 drive-strength = <8>; 5432 bias-disable; 5433 }; 5434 5435 cci0_0_default: cci0-0-default-state { 5436 pins = "gpio60", "gpio61"; 5437 function = "cci_i2c"; 5438 drive-strength = <2>; 5439 bias-pull-up = <2200>; 5440 }; 5441 5442 cci0_0_sleep: cci0-0-sleep-state { 5443 pins = "gpio60", "gpio61"; 5444 function = "cci_i2c"; 5445 drive-strength = <2>; 5446 bias-pull-down; 5447 }; 5448 5449 cci0_1_default: cci0-1-default-state { 5450 pins = "gpio52", "gpio53"; 5451 function = "cci_i2c"; 5452 drive-strength = <2>; 5453 bias-pull-up = <2200>; 5454 }; 5455 5456 cci0_1_sleep: cci0-1-sleep-state { 5457 pins = "gpio52", "gpio53"; 5458 function = "cci_i2c"; 5459 drive-strength = <2>; 5460 bias-pull-down; 5461 }; 5462 5463 cci1_0_default: cci1-0-default-state { 5464 pins = "gpio62", "gpio63"; 5465 function = "cci_i2c"; 5466 drive-strength = <2>; 5467 bias-pull-up = <2200>; 5468 }; 5469 5470 cci1_0_sleep: cci1-0-sleep-state { 5471 pins = "gpio62", "gpio63"; 5472 function = "cci_i2c"; 5473 drive-strength = <2>; 5474 bias-pull-down; 5475 }; 5476 5477 cci1_1_default: cci1-1-default-state { 5478 pins = "gpio54", "gpio55"; 5479 function = "cci_i2c"; 5480 drive-strength = <2>; 5481 bias-pull-up = <2200>; 5482 }; 5483 5484 cci1_1_sleep: cci1-1-sleep-state { 5485 pins = "gpio54", "gpio55"; 5486 function = "cci_i2c"; 5487 drive-strength = <2>; 5488 bias-pull-down; 5489 }; 5490 5491 cci2_0_default: cci2-0-default-state { 5492 pins = "gpio64", "gpio65"; 5493 function = "cci_i2c"; 5494 drive-strength = <2>; 5495 bias-pull-up = <2200>; 5496 }; 5497 5498 cci2_0_sleep: cci2-0-sleep-state { 5499 pins = "gpio64", "gpio65"; 5500 function = "cci_i2c"; 5501 drive-strength = <2>; 5502 bias-pull-down; 5503 }; 5504 5505 cci2_1_default: cci2-1-default-state { 5506 pins = "gpio56", "gpio57"; 5507 function = "cci_i2c"; 5508 drive-strength = <2>; 5509 bias-pull-up = <2200>; 5510 }; 5511 5512 cci2_1_sleep: cci2-1-sleep-state { 5513 pins = "gpio56", "gpio57"; 5514 function = "cci_i2c"; 5515 drive-strength = <2>; 5516 bias-pull-down; 5517 }; 5518 5519 cci3_0_default: cci3-0-default-state { 5520 pins = "gpio66", "gpio67"; 5521 function = "cci_i2c"; 5522 drive-strength = <2>; 5523 bias-pull-up = <2200>; 5524 }; 5525 5526 cci3_0_sleep: cci3-0-sleep-state { 5527 pins = "gpio66", "gpio67"; 5528 function = "cci_i2c"; 5529 drive-strength = <2>; 5530 bias-pull-down; 5531 }; 5532 5533 cci3_1_default: cci3-1-default-state { 5534 pins = "gpio58", "gpio59"; 5535 function = "cci_i2c"; 5536 drive-strength = <2>; 5537 bias-pull-up = <2200>; 5538 }; 5539 5540 cci3_1_sleep: cci3-1-sleep-state { 5541 pins = "gpio58", "gpio59"; 5542 function = "cci_i2c"; 5543 drive-strength = <2>; 5544 bias-pull-down; 5545 }; 5546 5547 qup_i2c0_default: qup-i2c0-state { 5548 pins = "gpio20", "gpio21"; 5549 function = "qup0_se0"; 5550 }; 5551 5552 qup_i2c1_default: qup-i2c1-state { 5553 pins = "gpio24", "gpio25"; 5554 function = "qup0_se1"; 5555 }; 5556 5557 qup_i2c2_default: qup-i2c2-state { 5558 pins = "gpio36", "gpio37"; 5559 function = "qup0_se2"; 5560 }; 5561 5562 qup_i2c3_default: qup-i2c3-state { 5563 pins = "gpio28", "gpio29"; 5564 function = "qup0_se3"; 5565 }; 5566 5567 qup_i2c4_default: qup-i2c4-state { 5568 pins = "gpio32", "gpio33"; 5569 function = "qup0_se4"; 5570 }; 5571 5572 qup_i2c5_default: qup-i2c5-state { 5573 pins = "gpio36", "gpio37"; 5574 function = "qup0_se5"; 5575 }; 5576 5577 qup_i2c7_default: qup-i2c7-state { 5578 pins = "gpio40", "gpio41"; 5579 function = "qup1_se0"; 5580 }; 5581 5582 qup_i2c8_default: qup-i2c8-state { 5583 pins = "gpio42", "gpio43"; 5584 function = "qup1_se1"; 5585 }; 5586 5587 qup_i2c9_default: qup-i2c9-state { 5588 pins = "gpio46", "gpio47"; 5589 function = "qup1_se2"; 5590 }; 5591 5592 qup_i2c10_default: qup-i2c10-state { 5593 pins = "gpio44", "gpio45"; 5594 function = "qup1_se3"; 5595 }; 5596 5597 qup_i2c11_default: qup-i2c11-state { 5598 pins = "gpio48", "gpio49"; 5599 function = "qup1_se4"; 5600 }; 5601 5602 qup_i2c12_default: qup-i2c12-state { 5603 pins = "gpio52", "gpio53"; 5604 function = "qup1_se5"; 5605 }; 5606 5607 qup_i2c13_default: qup-i2c13-state { 5608 pins = "gpio56", "gpio57"; 5609 function = "qup1_se6"; 5610 }; 5611 5612 qup_i2c14_default: qup-i2c14-state { 5613 pins = "gpio80", "gpio81"; 5614 function = "qup2_se0"; 5615 }; 5616 5617 qup_i2c15_default: qup-i2c15-state { 5618 pins = "gpio84", "gpio85"; 5619 function = "qup2_se1"; 5620 }; 5621 5622 qup_i2c16_default: qup-i2c16-state { 5623 pins = "gpio86", "gpio87"; 5624 function = "qup2_se2"; 5625 }; 5626 5627 qup_i2c17_default: qup-i2c17-state { 5628 pins = "gpio91", "gpio92"; 5629 function = "qup2_se3"; 5630 }; 5631 5632 qup_i2c18_default: qup-i2c18-state { 5633 pins = "gpio95", "gpio96"; 5634 function = "qup2_se4"; 5635 }; 5636 5637 qup_i2c19_default: qup-i2c19-state { 5638 pins = "gpio99", "gpio100"; 5639 function = "qup2_se5"; 5640 }; 5641 5642 qup_i2c20_default: qup-i2c20-state { 5643 pins = "gpio97", "gpio98"; 5644 function = "qup2_se6"; 5645 }; 5646 5647 qup_i2c21_default: qup-i2c21-state { 5648 pins = "gpio13", "gpio14"; 5649 function = "qup3_se0"; 5650 }; 5651 5652 qup_spi0_default: qup-spi0-state { 5653 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 5654 function = "qup0_se0"; 5655 }; 5656 5657 qup_spi1_default: qup-spi1-state { 5658 pins = "gpio24", "gpio25", "gpio26", "gpio27"; 5659 function = "qup0_se1"; 5660 }; 5661 5662 qup_spi2_default: qup-spi2-state { 5663 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 5664 function = "qup0_se2"; 5665 }; 5666 5667 qup_spi3_default: qup-spi3-state { 5668 pins = "gpio28", "gpio29", "gpio30", "gpio31"; 5669 function = "qup0_se3"; 5670 }; 5671 5672 qup_spi4_default: qup-spi4-state { 5673 pins = "gpio32", "gpio33", "gpio34", "gpio35"; 5674 function = "qup0_se4"; 5675 }; 5676 5677 qup_spi5_default: qup-spi5-state { 5678 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 5679 function = "qup0_se5"; 5680 }; 5681 5682 qup_spi7_default: qup-spi7-state { 5683 pins = "gpio40", "gpio41", "gpio42", "gpio43"; 5684 function = "qup1_se0"; 5685 }; 5686 5687 qup_spi8_default: qup-spi8-state { 5688 pins = "gpio42", "gpio43", "gpio40", "gpio41"; 5689 function = "qup1_se1"; 5690 }; 5691 5692 qup_spi9_default: qup-spi9-state { 5693 pins = "gpio46", "gpio47", "gpio44", "gpio45"; 5694 function = "qup1_se2"; 5695 }; 5696 5697 qup_spi10_default: qup-spi10-state { 5698 pins = "gpio44", "gpio45", "gpio46", "gpio47"; 5699 function = "qup1_se3"; 5700 }; 5701 5702 qup_spi11_default: qup-spi11-state { 5703 pins = "gpio48", "gpio49", "gpio50", "gpio51"; 5704 function = "qup1_se4"; 5705 }; 5706 5707 qup_spi12_default: qup-spi12-state { 5708 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5709 function = "qup1_se5"; 5710 }; 5711 5712 qup_spi14_default: qup-spi14-state { 5713 pins = "gpio80", "gpio81", "gpio82", "gpio83"; 5714 function = "qup2_se0"; 5715 }; 5716 5717 qup_spi15_default: qup-spi15-state { 5718 pins = "gpio84", "gpio85", "gpio99", "gpio100"; 5719 function = "qup2_se1"; 5720 }; 5721 5722 qup_spi16_default: qup-spi16-state { 5723 pins = "gpio86", "gpio87", "gpio88", "gpio89"; 5724 function = "qup2_se2"; 5725 }; 5726 5727 qup_spi17_default: qup-spi17-state { 5728 pins = "gpio91", "gpio92", "gpio93", "gpio94"; 5729 function = "qup2_se3"; 5730 }; 5731 5732 qup_spi18_default: qup-spi18-state { 5733 pins = "gpio95", "gpio96", "gpio97", "gpio98"; 5734 function = "qup2_se4"; 5735 }; 5736 5737 qup_spi19_default: qup-spi19-state { 5738 pins = "gpio99", "gpio100", "gpio84", "gpio85"; 5739 function = "qup2_se5"; 5740 }; 5741 5742 qup_spi20_default: qup-spi20-state { 5743 pins = "gpio97", "gpio98", "gpio95", "gpio96"; 5744 function = "qup2_se6"; 5745 }; 5746 5747 qup_spi21_default: qup-spi21-state { 5748 pins = "gpio13", "gpio14", "gpio15", "gpio16"; 5749 function = "qup3_se0"; 5750 }; 5751 5752 qup_uart0_default: qup-uart0-state { 5753 qup_uart0_cts: qup-uart0-cts-pins { 5754 pins = "gpio20"; 5755 function = "qup0_se0"; 5756 }; 5757 5758 qup_uart0_rts: qup-uart0-rts-pins { 5759 pins = "gpio21"; 5760 function = "qup0_se0"; 5761 }; 5762 5763 qup_uart0_tx: qup-uart0-tx-pins { 5764 pins = "gpio22"; 5765 function = "qup0_se0"; 5766 }; 5767 5768 qup_uart0_rx: qup-uart0-rx-pins { 5769 pins = "gpio23"; 5770 function = "qup0_se0"; 5771 }; 5772 }; 5773 5774 qup_uart1_default: qup-uart1-state { 5775 qup_uart1_cts: qup-uart1-cts-pins { 5776 pins = "gpio24"; 5777 function = "qup0_se1"; 5778 }; 5779 5780 qup_uart1_rts: qup-uart1-rts-pins { 5781 pins = "gpio25"; 5782 function = "qup0_se1"; 5783 }; 5784 5785 qup_uart1_tx: qup-uart1-tx-pins { 5786 pins = "gpio26"; 5787 function = "qup0_se1"; 5788 }; 5789 5790 qup_uart1_rx: qup-uart1-rx-pins { 5791 pins = "gpio27"; 5792 function = "qup0_se1"; 5793 }; 5794 }; 5795 5796 qup_uart2_default: qup-uart2-state { 5797 qup_uart2_cts: qup-uart2-cts-pins { 5798 pins = "gpio36"; 5799 function = "qup0_se2"; 5800 }; 5801 5802 qup_uart2_rts: qup-uart2-rts-pins { 5803 pins = "gpio37"; 5804 function = "qup0_se2"; 5805 }; 5806 5807 qup_uart2_tx: qup-uart2-tx-pins { 5808 pins = "gpio38"; 5809 function = "qup0_se2"; 5810 }; 5811 5812 qup_uart2_rx: qup-uart2-rx-pins { 5813 pins = "gpio39"; 5814 function = "qup0_se2"; 5815 }; 5816 }; 5817 5818 qup_uart3_default: qup-uart3-state { 5819 qup_uart3_cts: qup-uart3-cts-pins { 5820 pins = "gpio28"; 5821 function = "qup0_se3"; 5822 }; 5823 5824 qup_uart3_rts: qup-uart3-rts-pins { 5825 pins = "gpio29"; 5826 function = "qup0_se3"; 5827 }; 5828 5829 qup_uart3_tx: qup-uart3-tx-pins { 5830 pins = "gpio30"; 5831 function = "qup0_se3"; 5832 }; 5833 5834 qup_uart3_rx: qup-uart3-rx-pins { 5835 pins = "gpio31"; 5836 function = "qup0_se3"; 5837 }; 5838 }; 5839 5840 qup_uart4_default: qup-uart4-state { 5841 qup_uart4_cts: qup-uart4-cts-pins { 5842 pins = "gpio32"; 5843 function = "qup0_se4"; 5844 }; 5845 5846 qup_uart4_rts: qup-uart4-rts-pins { 5847 pins = "gpio33"; 5848 function = "qup0_se4"; 5849 }; 5850 5851 qup_uart4_tx: qup-uart4-tx-pins { 5852 pins = "gpio34"; 5853 function = "qup0_se4"; 5854 }; 5855 5856 qup_uart4_rx: qup-uart4-rx-pins { 5857 pins = "gpio35"; 5858 function = "qup0_se4"; 5859 }; 5860 }; 5861 5862 qup_uart5_default: qup-uart5-state { 5863 qup_uart5_cts: qup-uart5-cts-pins { 5864 pins = "gpio36"; 5865 function = "qup0_se5"; 5866 }; 5867 5868 qup_uart5_rts: qup-uart5-rts-pins { 5869 pins = "gpio37"; 5870 function = "qup0_se5"; 5871 }; 5872 5873 qup_uart5_tx: qup-uart5-tx-pins { 5874 pins = "gpio38"; 5875 function = "qup0_se5"; 5876 }; 5877 5878 qup_uart5_rx: qup-uart5-rx-pins { 5879 pins = "gpio39"; 5880 function = "qup0_se5"; 5881 }; 5882 }; 5883 5884 qup_uart7_default: qup-uart7-state { 5885 qup_uart7_cts: qup-uart7-cts-pins { 5886 pins = "gpio40"; 5887 function = "qup1_se0"; 5888 }; 5889 5890 qup_uart7_rts: qup-uart7-rts-pins { 5891 pins = "gpio41"; 5892 function = "qup1_se0"; 5893 }; 5894 5895 qup_uart7_tx: qup-uart7-tx-pins { 5896 pins = "gpio42"; 5897 function = "qup1_se0"; 5898 }; 5899 5900 qup_uart7_rx: qup-uart7-rx-pins { 5901 pins = "gpio43"; 5902 function = "qup1_se0"; 5903 }; 5904 }; 5905 5906 qup_uart8_default: qup-uart8-state { 5907 qup_uart8_cts: qup-uart8-cts-pins { 5908 pins = "gpio42"; 5909 function = "qup1_se1"; 5910 }; 5911 5912 qup_uart8_rts: qup-uart8-rts-pins { 5913 pins = "gpio43"; 5914 function = "qup1_se1"; 5915 }; 5916 5917 qup_uart8_tx: qup-uart8-tx-pins { 5918 pins = "gpio40"; 5919 function = "qup1_se1"; 5920 }; 5921 5922 qup_uart8_rx: qup-uart8-rx-pins { 5923 pins = "gpio41"; 5924 function = "qup1_se1"; 5925 }; 5926 }; 5927 5928 qup_uart9_default: qup-uart9-state { 5929 qup_uart9_cts: qup-uart9-cts-pins { 5930 pins = "gpio46"; 5931 function = "qup1_se2"; 5932 }; 5933 5934 qup_uart9_rts: qup-uart9-rts-pins { 5935 pins = "gpio47"; 5936 function = "qup1_se2"; 5937 }; 5938 5939 qup_uart9_tx: qup-uart9-tx-pins { 5940 pins = "gpio44"; 5941 function = "qup1_se2"; 5942 }; 5943 5944 qup_uart9_rx: qup-uart9-rx-pins { 5945 pins = "gpio45"; 5946 function = "qup1_se2"; 5947 }; 5948 }; 5949 5950 qup_uart10_default: qup-uart10-state { 5951 pins = "gpio46", "gpio47"; 5952 function = "qup1_se3"; 5953 }; 5954 5955 qup_uart11_default: qup-uart11-state { 5956 qup_uart11_cts: qup-uart11-cts-pins { 5957 pins = "gpio48"; 5958 function = "qup1_se4"; 5959 }; 5960 5961 qup_uart11_rts: qup-uart11-rts-pins { 5962 pins = "gpio49"; 5963 function = "qup1_se4"; 5964 }; 5965 5966 qup_uart11_tx: qup-uart11-tx-pins { 5967 pins = "gpio50"; 5968 function = "qup1_se4"; 5969 }; 5970 5971 qup_uart11_rx: qup-uart11-rx-pins { 5972 pins = "gpio51"; 5973 function = "qup1_se4"; 5974 }; 5975 }; 5976 5977 qup_uart12_default: qup-uart12-state { 5978 qup_uart12_cts: qup-uart12-cts-pins { 5979 pins = "gpio52"; 5980 function = "qup1_se5"; 5981 }; 5982 5983 qup_uart12_rts: qup-uart12-rts-pins { 5984 pins = "gpio53"; 5985 function = "qup1_se5"; 5986 }; 5987 5988 qup_uart12_tx: qup-uart12-tx-pins { 5989 pins = "gpio54"; 5990 function = "qup1_se5"; 5991 }; 5992 5993 qup_uart12_rx: qup-uart12-rx-pins { 5994 pins = "gpio55"; 5995 function = "qup1_se5"; 5996 }; 5997 }; 5998 5999 qup_uart14_default: qup-uart14-state { 6000 qup_uart14_cts: qup-uart14-cts-pins { 6001 pins = "gpio80"; 6002 function = "qup2_se0"; 6003 }; 6004 6005 qup_uart14_rts: qup-uart14-rts-pins { 6006 pins = "gpio81"; 6007 function = "qup2_se0"; 6008 }; 6009 6010 qup_uart14_tx: qup-uart14-tx-pins { 6011 pins = "gpio82"; 6012 function = "qup2_se0"; 6013 }; 6014 6015 qup_uart14_rx: qup-uart14-rx-pins { 6016 pins = "gpio83"; 6017 function = "qup2_se0"; 6018 }; 6019 }; 6020 6021 qup_uart15_default: qup-uart15-state { 6022 qup_uart15_cts: qup-uart15-cts-pins { 6023 pins = "gpio84"; 6024 function = "qup2_se1"; 6025 }; 6026 6027 qup_uart15_rts: qup-uart15-rts-pins { 6028 pins = "gpio85"; 6029 function = "qup2_se1"; 6030 }; 6031 6032 qup_uart15_tx: qup-uart15-tx-pins { 6033 pins = "gpio99"; 6034 function = "qup2_se1"; 6035 }; 6036 6037 qup_uart15_rx: qup-uart15-rx-pins { 6038 pins = "gpio100"; 6039 function = "qup2_se1"; 6040 }; 6041 }; 6042 6043 qup_uart16_default: qup-uart16-state { 6044 qup_uart16_cts: qup-uart16-cts-pins { 6045 pins = "gpio86"; 6046 function = "qup2_se2"; 6047 }; 6048 6049 qup_uart16_rts: qup-uart16-rts-pins { 6050 pins = "gpio87"; 6051 function = "qup2_se2"; 6052 }; 6053 6054 qup_uart16_tx: qup-uart16-tx-pins { 6055 pins = "gpio88"; 6056 function = "qup2_se2"; 6057 }; 6058 6059 qup_uart16_rx: qup-uart16-rx-pins { 6060 pins = "gpio89"; 6061 function = "qup2_se2"; 6062 }; 6063 }; 6064 6065 qup_uart17_default: qup-uart17-state { 6066 qup_uart17_cts: qup-uart17-cts-pins { 6067 pins = "gpio91"; 6068 function = "qup2_se3"; 6069 }; 6070 6071 qup_uart17_rts: qup0-uart17-rts-pins { 6072 pins = "gpio92"; 6073 function = "qup2_se3"; 6074 }; 6075 6076 qup_uart17_tx: qup0-uart17-tx-pins { 6077 pins = "gpio93"; 6078 function = "qup2_se3"; 6079 }; 6080 6081 qup_uart17_rx: qup0-uart17-rx-pins { 6082 pins = "gpio94"; 6083 function = "qup2_se3"; 6084 }; 6085 }; 6086 6087 qup_uart18_default: qup-uart18-state { 6088 qup_uart18_cts: qup-uart18-cts-pins { 6089 pins = "gpio95"; 6090 function = "qup2_se4"; 6091 }; 6092 6093 qup_uart18_rts: qup-uart18-rts-pins { 6094 pins = "gpio96"; 6095 function = "qup2_se4"; 6096 }; 6097 6098 qup_uart18_tx: qup-uart18-tx-pins { 6099 pins = "gpio97"; 6100 function = "qup2_se4"; 6101 }; 6102 6103 qup_uart18_rx: qup-uart18-rx-pins { 6104 pins = "gpio98"; 6105 function = "qup2_se4"; 6106 }; 6107 }; 6108 6109 qup_uart19_default: qup-uart19-state { 6110 qup_uart19_cts: qup-uart19-cts-pins { 6111 pins = "gpio99"; 6112 function = "qup2_se5"; 6113 }; 6114 6115 qup_uart19_rts: qup-uart19-rts-pins { 6116 pins = "gpio100"; 6117 function = "qup2_se5"; 6118 }; 6119 6120 qup_uart19_tx: qup-uart19-tx-pins { 6121 pins = "gpio84"; 6122 function = "qup2_se5"; 6123 }; 6124 6125 qup_uart19_rx: qup-uart19-rx-pins { 6126 pins = "gpio85"; 6127 function = "qup2_se5"; 6128 }; 6129 }; 6130 6131 qup_uart20_default: qup-uart20-state { 6132 qup_uart20_cts: qup-uart20-cts-pins { 6133 pins = "gpio97"; 6134 function = "qup2_se6"; 6135 }; 6136 6137 qup_uart20_rts: qup-uart20-rts-pins { 6138 pins = "gpio98"; 6139 function = "qup2_se6"; 6140 }; 6141 6142 qup_uart20_tx: qup-uart20-tx-pins { 6143 pins = "gpio95"; 6144 function = "qup2_se6"; 6145 }; 6146 6147 qup_uart20_rx: qup-uart20-rx-pins { 6148 pins = "gpio96"; 6149 function = "qup2_se6"; 6150 }; 6151 }; 6152 6153 qup_uart21_default: qup-uart21-state { 6154 qup_uart21_cts: qup-uart21-cts-pins { 6155 pins = "gpio13"; 6156 function = "qup3_se0"; 6157 }; 6158 6159 qup_uart21_rts: qup-uart21-rts-pins { 6160 pins = "gpio14"; 6161 function = "qup3_se0"; 6162 }; 6163 6164 qup_uart21_tx: qup-uart21-tx-pins { 6165 pins = "gpio15"; 6166 function = "qup3_se0"; 6167 }; 6168 6169 qup_uart21_rx: qup-uart21-rx-pins { 6170 pins = "gpio16"; 6171 function = "qup3_se0"; 6172 }; 6173 }; 6174 6175 sdc_default: sdc-default-state { 6176 clk-pins { 6177 pins = "sdc1_clk"; 6178 drive-strength = <16>; 6179 bias-disable; 6180 }; 6181 6182 cmd-pins { 6183 pins = "sdc1_cmd"; 6184 drive-strength = <10>; 6185 bias-pull-up; 6186 }; 6187 6188 data-pins { 6189 pins = "sdc1_data"; 6190 drive-strength = <10>; 6191 bias-pull-up; 6192 }; 6193 }; 6194 6195 sdc_sleep: sdc-sleep-state { 6196 clk-pins { 6197 pins = "sdc1_clk"; 6198 drive-strength = <2>; 6199 bias-bus-hold; 6200 }; 6201 6202 cmd-pins { 6203 pins = "sdc1_cmd"; 6204 drive-strength = <2>; 6205 bias-bus-hold; 6206 }; 6207 6208 data-pins { 6209 pins = "sdc1_data"; 6210 drive-strength = <2>; 6211 bias-bus-hold; 6212 }; 6213 }; 6214 }; 6215 6216 sram: sram@146d8000 { 6217 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; 6218 reg = <0x0 0x146d8000 0x0 0x1000>; 6219 ranges = <0x0 0x0 0x146d8000 0x1000>; 6220 6221 #address-cells = <1>; 6222 #size-cells = <1>; 6223 6224 pil-reloc@94c { 6225 compatible = "qcom,pil-reloc-info"; 6226 reg = <0x94c 0xc8>; 6227 }; 6228 }; 6229 6230 apps_smmu: iommu@15000000 { 6231 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6232 reg = <0x0 0x15000000 0x0 0x100000>; 6233 #iommu-cells = <2>; 6234 #global-interrupts = <2>; 6235 dma-coherent; 6236 6237 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 6238 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 6239 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6240 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6241 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6242 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6243 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6244 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6245 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6246 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6247 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6248 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6249 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6250 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6251 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6252 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6253 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6254 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6255 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6256 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6257 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6258 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6259 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6260 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6261 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6262 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6263 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6264 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6265 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6266 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6267 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6268 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6269 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6270 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6271 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6272 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6273 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6274 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6275 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6276 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6277 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6278 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6279 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6280 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6281 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6282 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6283 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6284 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6285 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6286 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6287 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6288 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6289 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6290 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6291 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6292 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6293 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6294 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6295 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6296 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6297 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6298 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6299 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6300 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6301 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6302 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6303 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6304 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6305 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6306 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6307 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6308 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6309 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6310 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6311 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6312 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 6313 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 6314 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 6315 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 6316 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 6317 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 6318 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 6319 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 6320 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 6321 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 6322 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 6323 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 6324 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 6325 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 6326 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 6327 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 6328 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 6329 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 6330 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 6331 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 6332 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 6333 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 6334 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 6335 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 6336 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 6337 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 6338 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 6339 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 6340 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 6341 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 6342 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 6343 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 6344 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 6345 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 6346 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 6347 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 6348 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 6349 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 6350 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 6351 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 6352 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 6353 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 6354 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 6355 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 6356 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 6357 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 6358 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 6359 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 6360 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 6361 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 6362 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 6363 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 6364 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 6365 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 6366 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 6367 }; 6368 6369 pcie_smmu: iommu@15200000 { 6370 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6371 reg = <0x0 0x15200000 0x0 0x80000>; 6372 #iommu-cells = <2>; 6373 #global-interrupts = <2>; 6374 dma-coherent; 6375 6376 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 6377 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 6378 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 6379 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 6380 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 6381 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 6382 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 6383 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 6384 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 6385 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 6386 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 6387 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 6388 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 6389 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 6390 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 6391 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 6392 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 6393 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 6394 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 6395 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 6396 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 6397 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 6398 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 6399 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 6400 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 6401 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 6402 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 6403 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 6404 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 6405 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 6406 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 6407 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 6408 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 6409 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 6410 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 6411 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 6412 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 6413 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 6414 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 6415 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 6416 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 6417 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 6418 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 6419 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 6420 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 6421 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 6422 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 6423 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 6424 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 6425 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 6426 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 6427 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 6428 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 6429 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 6430 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 6431 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 6432 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 6433 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 6434 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 6435 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 6436 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 6437 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 6438 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 6439 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 6440 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 6441 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 6442 }; 6443 6444 intc: interrupt-controller@17a00000 { 6445 compatible = "arm,gic-v3"; 6446 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 6447 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 6448 interrupt-controller; 6449 #address-cells = <0>; 6450 #interrupt-cells = <3>; 6451 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 6452 #redistributor-regions = <1>; 6453 redistributor-stride = <0x0 0x20000>; 6454 }; 6455 6456 watchdog@17c10000 { 6457 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 6458 reg = <0x0 0x17c10000 0x0 0x1000>; 6459 clocks = <&sleep_clk>; 6460 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6461 }; 6462 6463 memtimer: timer@17c20000 { 6464 compatible = "arm,armv7-timer-mem"; 6465 reg = <0x0 0x17c20000 0x0 0x1000>; 6466 ranges = <0x0 0x0 0x0 0x20000000>; 6467 #address-cells = <1>; 6468 #size-cells = <1>; 6469 6470 frame@17c21000 { 6471 reg = <0x17c21000 0x1000>, 6472 <0x17c22000 0x1000>; 6473 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6474 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6475 frame-number = <0>; 6476 }; 6477 6478 frame@17c23000 { 6479 reg = <0x17c23000 0x1000>; 6480 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6481 frame-number = <1>; 6482 status = "disabled"; 6483 }; 6484 6485 frame@17c25000 { 6486 reg = <0x17c25000 0x1000>; 6487 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6488 frame-number = <2>; 6489 status = "disabled"; 6490 }; 6491 6492 frame@17c27000 { 6493 reg = <0x17c27000 0x1000>; 6494 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6495 frame-number = <3>; 6496 status = "disabled"; 6497 }; 6498 6499 frame@17c29000 { 6500 reg = <0x17c29000 0x1000>; 6501 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6502 frame-number = <4>; 6503 status = "disabled"; 6504 }; 6505 6506 frame@17c2b000 { 6507 reg = <0x17c2b000 0x1000>; 6508 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6509 frame-number = <5>; 6510 status = "disabled"; 6511 }; 6512 6513 frame@17c2d000 { 6514 reg = <0x17c2d000 0x1000>; 6515 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6516 frame-number = <6>; 6517 status = "disabled"; 6518 }; 6519 }; 6520 6521 apps_rsc: rsc@18200000 { 6522 compatible = "qcom,rpmh-rsc"; 6523 reg = <0x0 0x18200000 0x0 0x10000>, 6524 <0x0 0x18210000 0x0 0x10000>, 6525 <0x0 0x18220000 0x0 0x10000>; 6526 reg-names = "drv-0", "drv-1", "drv-2"; 6527 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6528 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6529 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6530 qcom,tcs-offset = <0xd00>; 6531 qcom,drv-id = <2>; 6532 qcom,tcs-config = <ACTIVE_TCS 2>, 6533 <SLEEP_TCS 3>, 6534 <WAKE_TCS 3>, 6535 <CONTROL_TCS 0>; 6536 label = "apps_rsc"; 6537 power-domains = <&system_pd>; 6538 6539 apps_bcm_voter: bcm-voter { 6540 compatible = "qcom,bcm-voter"; 6541 }; 6542 6543 rpmhcc: clock-controller { 6544 compatible = "qcom,sa8775p-rpmh-clk"; 6545 #clock-cells = <1>; 6546 clock-names = "xo"; 6547 clocks = <&xo_board_clk>; 6548 }; 6549 6550 rpmhpd: power-controller { 6551 compatible = "qcom,sa8775p-rpmhpd"; 6552 #power-domain-cells = <1>; 6553 operating-points-v2 = <&rpmhpd_opp_table>; 6554 6555 rpmhpd_opp_table: opp-table { 6556 compatible = "operating-points-v2"; 6557 6558 rpmhpd_opp_ret: opp-0 { 6559 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6560 }; 6561 6562 rpmhpd_opp_min_svs: opp-1 { 6563 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6564 }; 6565 6566 rpmhpd_opp_low_svs: opp2 { 6567 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6568 }; 6569 6570 rpmhpd_opp_svs: opp3 { 6571 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6572 }; 6573 6574 rpmhpd_opp_svs_l1: opp-4 { 6575 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6576 }; 6577 6578 rpmhpd_opp_nom: opp-5 { 6579 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6580 }; 6581 6582 rpmhpd_opp_nom_l1: opp-6 { 6583 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6584 }; 6585 6586 rpmhpd_opp_nom_l2: opp-7 { 6587 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6588 }; 6589 6590 rpmhpd_opp_turbo: opp-8 { 6591 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6592 }; 6593 6594 rpmhpd_opp_turbo_l1: opp-9 { 6595 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6596 }; 6597 }; 6598 }; 6599 }; 6600 6601 epss_l3_cl0: interconnect@18590000 { 6602 compatible = "qcom,sa8775p-epss-l3", 6603 "qcom,epss-l3"; 6604 reg = <0x0 0x18590000 0x0 0x1000>; 6605 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6606 clock-names = "xo", "alternate"; 6607 #interconnect-cells = <1>; 6608 }; 6609 6610 cpufreq_hw: cpufreq@18591000 { 6611 compatible = "qcom,sa8775p-cpufreq-epss", 6612 "qcom,cpufreq-epss"; 6613 reg = <0x0 0x18591000 0x0 0x1000>, 6614 <0x0 0x18593000 0x0 0x1000>; 6615 reg-names = "freq-domain0", "freq-domain1"; 6616 6617 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6618 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 6619 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 6620 6621 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6622 clock-names = "xo", "alternate"; 6623 6624 #freq-domain-cells = <1>; 6625 }; 6626 6627 epss_l3_cl1: interconnect@18592000 { 6628 compatible = "qcom,sa8775p-epss-l3", 6629 "qcom,epss-l3"; 6630 reg = <0x0 0x18592000 0x0 0x1000>; 6631 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6632 clock-names = "xo", "alternate"; 6633 #interconnect-cells = <1>; 6634 }; 6635 6636 remoteproc_gpdsp0: remoteproc@20c00000 { 6637 compatible = "qcom,sa8775p-gpdsp0-pas"; 6638 reg = <0x0 0x20c00000 0x0 0x10000>; 6639 6640 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 6641 <&smp2p_gpdsp0_in 0 0>, 6642 <&smp2p_gpdsp0_in 1 0>, 6643 <&smp2p_gpdsp0_in 2 0>, 6644 <&smp2p_gpdsp0_in 3 0>; 6645 interrupt-names = "wdog", "fatal", "ready", 6646 "handover", "stop-ack"; 6647 6648 clocks = <&rpmhcc RPMH_CXO_CLK>; 6649 clock-names = "xo"; 6650 6651 power-domains = <&rpmhpd SA8775P_CX>, 6652 <&rpmhpd SA8775P_MXC>; 6653 power-domain-names = "cx", "mxc"; 6654 6655 interconnects = <&gpdsp_anoc MASTER_DSP0 0 6656 &config_noc SLAVE_CLK_CTL 0>; 6657 6658 memory-region = <&pil_gdsp0_mem>; 6659 6660 qcom,qmp = <&aoss_qmp>; 6661 6662 qcom,smem-states = <&smp2p_gpdsp0_out 0>; 6663 qcom,smem-state-names = "stop"; 6664 6665 status = "disabled"; 6666 6667 glink-edge { 6668 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 6669 IPCC_MPROC_SIGNAL_GLINK_QMP 6670 IRQ_TYPE_EDGE_RISING>; 6671 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 6672 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6673 6674 label = "gpdsp0"; 6675 qcom,remote-pid = <17>; 6676 6677 fastrpc { 6678 compatible = "qcom,fastrpc"; 6679 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6680 label = "gdsp0"; 6681 #address-cells = <1>; 6682 #size-cells = <0>; 6683 6684 compute-cb@1 { 6685 compatible = "qcom,fastrpc-compute-cb"; 6686 reg = <1>; 6687 iommus = <&apps_smmu 0x38a1 0x0>; 6688 dma-coherent; 6689 }; 6690 6691 compute-cb@2 { 6692 compatible = "qcom,fastrpc-compute-cb"; 6693 reg = <2>; 6694 iommus = <&apps_smmu 0x38a2 0x0>; 6695 dma-coherent; 6696 }; 6697 6698 compute-cb@3 { 6699 compatible = "qcom,fastrpc-compute-cb"; 6700 reg = <3>; 6701 iommus = <&apps_smmu 0x38a3 0x0>; 6702 dma-coherent; 6703 }; 6704 }; 6705 }; 6706 }; 6707 6708 remoteproc_gpdsp1: remoteproc@21c00000 { 6709 compatible = "qcom,sa8775p-gpdsp1-pas"; 6710 reg = <0x0 0x21c00000 0x0 0x10000>; 6711 6712 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 6713 <&smp2p_gpdsp1_in 0 0>, 6714 <&smp2p_gpdsp1_in 1 0>, 6715 <&smp2p_gpdsp1_in 2 0>, 6716 <&smp2p_gpdsp1_in 3 0>; 6717 interrupt-names = "wdog", "fatal", "ready", 6718 "handover", "stop-ack"; 6719 6720 clocks = <&rpmhcc RPMH_CXO_CLK>; 6721 clock-names = "xo"; 6722 6723 power-domains = <&rpmhpd SA8775P_CX>, 6724 <&rpmhpd SA8775P_MXC>; 6725 power-domain-names = "cx", "mxc"; 6726 6727 interconnects = <&gpdsp_anoc MASTER_DSP1 0 6728 &config_noc SLAVE_CLK_CTL 0>; 6729 6730 memory-region = <&pil_gdsp1_mem>; 6731 6732 qcom,qmp = <&aoss_qmp>; 6733 6734 qcom,smem-states = <&smp2p_gpdsp1_out 0>; 6735 qcom,smem-state-names = "stop"; 6736 6737 status = "disabled"; 6738 6739 glink-edge { 6740 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 6741 IPCC_MPROC_SIGNAL_GLINK_QMP 6742 IRQ_TYPE_EDGE_RISING>; 6743 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 6744 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6745 6746 label = "gpdsp1"; 6747 qcom,remote-pid = <18>; 6748 6749 fastrpc { 6750 compatible = "qcom,fastrpc"; 6751 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6752 label = "gdsp1"; 6753 #address-cells = <1>; 6754 #size-cells = <0>; 6755 6756 compute-cb@1 { 6757 compatible = "qcom,fastrpc-compute-cb"; 6758 reg = <1>; 6759 iommus = <&apps_smmu 0x38c1 0x0>; 6760 dma-coherent; 6761 }; 6762 6763 compute-cb@2 { 6764 compatible = "qcom,fastrpc-compute-cb"; 6765 reg = <2>; 6766 iommus = <&apps_smmu 0x38c2 0x0>; 6767 dma-coherent; 6768 }; 6769 6770 compute-cb@3 { 6771 compatible = "qcom,fastrpc-compute-cb"; 6772 reg = <3>; 6773 iommus = <&apps_smmu 0x38c3 0x0>; 6774 dma-coherent; 6775 }; 6776 }; 6777 }; 6778 }; 6779 6780 dispcc1: clock-controller@22100000 { 6781 compatible = "qcom,sa8775p-dispcc1"; 6782 reg = <0x0 0x22100000 0x0 0x20000>; 6783 clocks = <&gcc GCC_DISP_AHB_CLK>, 6784 <&rpmhcc RPMH_CXO_CLK>, 6785 <&rpmhcc RPMH_CXO_CLK_A>, 6786 <&sleep_clk>, 6787 <0>, <0>, <0>, <0>, 6788 <0>, <0>, <0>, <0>; 6789 power-domains = <&rpmhpd SA8775P_MMCX>; 6790 #clock-cells = <1>; 6791 #reset-cells = <1>; 6792 #power-domain-cells = <1>; 6793 status = "disabled"; 6794 }; 6795 6796 ethernet1: ethernet@23000000 { 6797 compatible = "qcom,sa8775p-ethqos"; 6798 reg = <0x0 0x23000000 0x0 0x10000>, 6799 <0x0 0x23016000 0x0 0x100>; 6800 reg-names = "stmmaceth", "rgmii"; 6801 6802 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 6803 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 6804 interrupt-names = "macirq", "sfty"; 6805 6806 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 6807 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 6808 <&gcc GCC_EMAC1_PTP_CLK>, 6809 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 6810 clock-names = "stmmaceth", 6811 "pclk", 6812 "ptp_ref", 6813 "phyaux"; 6814 6815 interconnects = <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS 6816 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 6817 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 6818 &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>; 6819 interconnect-names = "mac-mem", "cpu-mac"; 6820 6821 power-domains = <&gcc EMAC1_GDSC>; 6822 6823 phys = <&serdes1>; 6824 phy-names = "serdes"; 6825 6826 iommus = <&apps_smmu 0x140 0xf>; 6827 dma-coherent; 6828 6829 snps,tso; 6830 snps,pbl = <32>; 6831 rx-fifo-depth = <16384>; 6832 tx-fifo-depth = <16384>; 6833 6834 status = "disabled"; 6835 }; 6836 6837 ethernet0: ethernet@23040000 { 6838 compatible = "qcom,sa8775p-ethqos"; 6839 reg = <0x0 0x23040000 0x0 0x10000>, 6840 <0x0 0x23056000 0x0 0x100>; 6841 reg-names = "stmmaceth", "rgmii"; 6842 6843 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 6844 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; 6845 interrupt-names = "macirq", "sfty"; 6846 6847 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 6848 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 6849 <&gcc GCC_EMAC0_PTP_CLK>, 6850 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 6851 clock-names = "stmmaceth", 6852 "pclk", 6853 "ptp_ref", 6854 "phyaux"; 6855 6856 interconnects = <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS 6857 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 6858 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 6859 &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>; 6860 interconnect-names = "mac-mem", "cpu-mac"; 6861 6862 power-domains = <&gcc EMAC0_GDSC>; 6863 6864 phys = <&serdes0>; 6865 phy-names = "serdes"; 6866 6867 iommus = <&apps_smmu 0x120 0xf>; 6868 dma-coherent; 6869 6870 snps,tso; 6871 snps,pbl = <32>; 6872 rx-fifo-depth = <16384>; 6873 tx-fifo-depth = <16384>; 6874 6875 status = "disabled"; 6876 }; 6877 6878 remoteproc_cdsp0: remoteproc@26300000 { 6879 compatible = "qcom,sa8775p-cdsp0-pas"; 6880 reg = <0x0 0x26300000 0x0 0x10000>; 6881 6882 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 6883 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>, 6884 <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>, 6885 <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>, 6886 <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>; 6887 interrupt-names = "wdog", "fatal", "ready", 6888 "handover", "stop-ack"; 6889 6890 clocks = <&rpmhcc RPMH_CXO_CLK>; 6891 clock-names = "xo"; 6892 6893 power-domains = <&rpmhpd SA8775P_CX>, 6894 <&rpmhpd SA8775P_MXC>, 6895 <&rpmhpd SA8775P_NSP0>; 6896 power-domain-names = "cx", "mxc", "nsp"; 6897 6898 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 6899 &mc_virt SLAVE_EBI1 0>; 6900 6901 memory-region = <&pil_cdsp0_mem>; 6902 6903 qcom,qmp = <&aoss_qmp>; 6904 6905 qcom,smem-states = <&smp2p_cdsp0_out 0>; 6906 qcom,smem-state-names = "stop"; 6907 6908 status = "disabled"; 6909 6910 glink-edge { 6911 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 6912 IPCC_MPROC_SIGNAL_GLINK_QMP 6913 IRQ_TYPE_EDGE_RISING>; 6914 mboxes = <&ipcc IPCC_CLIENT_CDSP 6915 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6916 6917 label = "cdsp"; 6918 qcom,remote-pid = <5>; 6919 6920 fastrpc { 6921 compatible = "qcom,fastrpc"; 6922 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6923 label = "cdsp"; 6924 #address-cells = <1>; 6925 #size-cells = <0>; 6926 6927 compute-cb@1 { 6928 compatible = "qcom,fastrpc-compute-cb"; 6929 reg = <1>; 6930 iommus = <&apps_smmu 0x2141 0x04a0>, 6931 <&apps_smmu 0x2181 0x0400>; 6932 dma-coherent; 6933 }; 6934 6935 compute-cb@2 { 6936 compatible = "qcom,fastrpc-compute-cb"; 6937 reg = <2>; 6938 iommus = <&apps_smmu 0x2142 0x04a0>, 6939 <&apps_smmu 0x2182 0x0400>; 6940 dma-coherent; 6941 }; 6942 6943 compute-cb@3 { 6944 compatible = "qcom,fastrpc-compute-cb"; 6945 reg = <3>; 6946 iommus = <&apps_smmu 0x2143 0x04a0>, 6947 <&apps_smmu 0x2183 0x0400>; 6948 dma-coherent; 6949 }; 6950 6951 compute-cb@4 { 6952 compatible = "qcom,fastrpc-compute-cb"; 6953 reg = <4>; 6954 iommus = <&apps_smmu 0x2144 0x04a0>, 6955 <&apps_smmu 0x2184 0x0400>; 6956 dma-coherent; 6957 }; 6958 6959 compute-cb@5 { 6960 compatible = "qcom,fastrpc-compute-cb"; 6961 reg = <5>; 6962 iommus = <&apps_smmu 0x2145 0x04a0>, 6963 <&apps_smmu 0x2185 0x0400>; 6964 dma-coherent; 6965 }; 6966 6967 compute-cb@6 { 6968 compatible = "qcom,fastrpc-compute-cb"; 6969 reg = <6>; 6970 iommus = <&apps_smmu 0x2146 0x04a0>, 6971 <&apps_smmu 0x2186 0x0400>; 6972 dma-coherent; 6973 }; 6974 6975 compute-cb@7 { 6976 compatible = "qcom,fastrpc-compute-cb"; 6977 reg = <7>; 6978 iommus = <&apps_smmu 0x2147 0x04a0>, 6979 <&apps_smmu 0x2187 0x0400>; 6980 dma-coherent; 6981 }; 6982 6983 compute-cb@8 { 6984 compatible = "qcom,fastrpc-compute-cb"; 6985 reg = <8>; 6986 iommus = <&apps_smmu 0x2148 0x04a0>, 6987 <&apps_smmu 0x2188 0x0400>; 6988 dma-coherent; 6989 }; 6990 6991 compute-cb@9 { 6992 compatible = "qcom,fastrpc-compute-cb"; 6993 reg = <9>; 6994 iommus = <&apps_smmu 0x2149 0x04a0>, 6995 <&apps_smmu 0x2189 0x0400>; 6996 dma-coherent; 6997 }; 6998 6999 compute-cb@11 { 7000 compatible = "qcom,fastrpc-compute-cb"; 7001 reg = <11>; 7002 iommus = <&apps_smmu 0x214b 0x04a0>, 7003 <&apps_smmu 0x218b 0x0400>; 7004 dma-coherent; 7005 }; 7006 }; 7007 }; 7008 }; 7009 7010 remoteproc_cdsp1: remoteproc@2a300000 { 7011 compatible = "qcom,sa8775p-cdsp1-pas"; 7012 reg = <0x0 0x2A300000 0x0 0x10000>; 7013 7014 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 7015 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, 7016 <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>, 7017 <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>, 7018 <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>; 7019 interrupt-names = "wdog", "fatal", "ready", 7020 "handover", "stop-ack"; 7021 7022 clocks = <&rpmhcc RPMH_CXO_CLK>; 7023 clock-names = "xo"; 7024 7025 power-domains = <&rpmhpd SA8775P_CX>, 7026 <&rpmhpd SA8775P_MXC>, 7027 <&rpmhpd SA8775P_NSP1>; 7028 power-domain-names = "cx", "mxc", "nsp"; 7029 7030 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 7031 &mc_virt SLAVE_EBI1 0>; 7032 7033 memory-region = <&pil_cdsp1_mem>; 7034 7035 qcom,qmp = <&aoss_qmp>; 7036 7037 qcom,smem-states = <&smp2p_cdsp1_out 0>; 7038 qcom,smem-state-names = "stop"; 7039 7040 status = "disabled"; 7041 7042 glink-edge { 7043 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 7044 IPCC_MPROC_SIGNAL_GLINK_QMP 7045 IRQ_TYPE_EDGE_RISING>; 7046 mboxes = <&ipcc IPCC_CLIENT_NSP1 7047 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7048 7049 label = "cdsp"; 7050 qcom,remote-pid = <12>; 7051 7052 fastrpc { 7053 compatible = "qcom,fastrpc"; 7054 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7055 label = "cdsp1"; 7056 #address-cells = <1>; 7057 #size-cells = <0>; 7058 7059 compute-cb@1 { 7060 compatible = "qcom,fastrpc-compute-cb"; 7061 reg = <1>; 7062 iommus = <&apps_smmu 0x2941 0x04a0>, 7063 <&apps_smmu 0x2981 0x0400>; 7064 dma-coherent; 7065 }; 7066 7067 compute-cb@2 { 7068 compatible = "qcom,fastrpc-compute-cb"; 7069 reg = <2>; 7070 iommus = <&apps_smmu 0x2942 0x04a0>, 7071 <&apps_smmu 0x2982 0x0400>; 7072 dma-coherent; 7073 }; 7074 7075 compute-cb@3 { 7076 compatible = "qcom,fastrpc-compute-cb"; 7077 reg = <3>; 7078 iommus = <&apps_smmu 0x2943 0x04a0>, 7079 <&apps_smmu 0x2983 0x0400>; 7080 dma-coherent; 7081 }; 7082 7083 compute-cb@4 { 7084 compatible = "qcom,fastrpc-compute-cb"; 7085 reg = <4>; 7086 iommus = <&apps_smmu 0x2944 0x04a0>, 7087 <&apps_smmu 0x2984 0x0400>; 7088 dma-coherent; 7089 }; 7090 7091 compute-cb@5 { 7092 compatible = "qcom,fastrpc-compute-cb"; 7093 reg = <5>; 7094 iommus = <&apps_smmu 0x2945 0x04a0>, 7095 <&apps_smmu 0x2985 0x0400>; 7096 dma-coherent; 7097 }; 7098 7099 compute-cb@6 { 7100 compatible = "qcom,fastrpc-compute-cb"; 7101 reg = <6>; 7102 iommus = <&apps_smmu 0x2946 0x04a0>, 7103 <&apps_smmu 0x2986 0x0400>; 7104 dma-coherent; 7105 }; 7106 7107 compute-cb@7 { 7108 compatible = "qcom,fastrpc-compute-cb"; 7109 reg = <7>; 7110 iommus = <&apps_smmu 0x2947 0x04a0>, 7111 <&apps_smmu 0x2987 0x0400>; 7112 dma-coherent; 7113 }; 7114 7115 compute-cb@8 { 7116 compatible = "qcom,fastrpc-compute-cb"; 7117 reg = <8>; 7118 iommus = <&apps_smmu 0x2948 0x04a0>, 7119 <&apps_smmu 0x2988 0x0400>; 7120 dma-coherent; 7121 }; 7122 7123 compute-cb@9 { 7124 compatible = "qcom,fastrpc-compute-cb"; 7125 reg = <9>; 7126 iommus = <&apps_smmu 0x2949 0x04a0>, 7127 <&apps_smmu 0x2989 0x0400>; 7128 dma-coherent; 7129 }; 7130 7131 compute-cb@10 { 7132 compatible = "qcom,fastrpc-compute-cb"; 7133 reg = <10>; 7134 iommus = <&apps_smmu 0x294a 0x04a0>, 7135 <&apps_smmu 0x298a 0x0400>; 7136 dma-coherent; 7137 }; 7138 7139 compute-cb@11 { 7140 compatible = "qcom,fastrpc-compute-cb"; 7141 reg = <11>; 7142 iommus = <&apps_smmu 0x294b 0x04a0>, 7143 <&apps_smmu 0x298b 0x0400>; 7144 dma-coherent; 7145 }; 7146 7147 compute-cb@12 { 7148 compatible = "qcom,fastrpc-compute-cb"; 7149 reg = <12>; 7150 iommus = <&apps_smmu 0x294c 0x04a0>, 7151 <&apps_smmu 0x298c 0x0400>; 7152 dma-coherent; 7153 }; 7154 7155 compute-cb@13 { 7156 compatible = "qcom,fastrpc-compute-cb"; 7157 reg = <13>; 7158 iommus = <&apps_smmu 0x294d 0x04a0>, 7159 <&apps_smmu 0x298d 0x0400>; 7160 dma-coherent; 7161 }; 7162 }; 7163 }; 7164 }; 7165 7166 remoteproc_adsp: remoteproc@30000000 { 7167 compatible = "qcom,sa8775p-adsp-pas"; 7168 reg = <0x0 0x30000000 0x0 0x100>; 7169 7170 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 7171 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 7172 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 7173 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 7174 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 7175 interrupt-names = "wdog", "fatal", "ready", "handover", 7176 "stop-ack"; 7177 7178 clocks = <&rpmhcc RPMH_CXO_CLK>; 7179 clock-names = "xo"; 7180 7181 power-domains = <&rpmhpd SA8775P_LCX>, 7182 <&rpmhpd SA8775P_LMX>; 7183 power-domain-names = "lcx", "lmx"; 7184 7185 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 7186 7187 memory-region = <&pil_adsp_mem>; 7188 7189 qcom,qmp = <&aoss_qmp>; 7190 7191 qcom,smem-states = <&smp2p_adsp_out 0>; 7192 qcom,smem-state-names = "stop"; 7193 7194 status = "disabled"; 7195 7196 remoteproc_adsp_glink: glink-edge { 7197 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 7198 IPCC_MPROC_SIGNAL_GLINK_QMP 7199 IRQ_TYPE_EDGE_RISING>; 7200 mboxes = <&ipcc IPCC_CLIENT_LPASS 7201 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7202 7203 label = "lpass"; 7204 qcom,remote-pid = <2>; 7205 7206 fastrpc { 7207 compatible = "qcom,fastrpc"; 7208 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7209 label = "adsp"; 7210 memory-region = <&adsp_rpc_remote_heap_mem>; 7211 qcom,vmids = <QCOM_SCM_VMID_LPASS 7212 QCOM_SCM_VMID_ADSP_HEAP>; 7213 #address-cells = <1>; 7214 #size-cells = <0>; 7215 7216 compute-cb@3 { 7217 compatible = "qcom,fastrpc-compute-cb"; 7218 reg = <3>; 7219 iommus = <&apps_smmu 0x3003 0x0>; 7220 dma-coherent; 7221 }; 7222 7223 compute-cb@4 { 7224 compatible = "qcom,fastrpc-compute-cb"; 7225 reg = <4>; 7226 iommus = <&apps_smmu 0x3004 0x0>; 7227 dma-coherent; 7228 }; 7229 7230 compute-cb@5 { 7231 compatible = "qcom,fastrpc-compute-cb"; 7232 reg = <5>; 7233 iommus = <&apps_smmu 0x3005 0x0>; 7234 qcom,nsessions = <5>; 7235 dma-coherent; 7236 }; 7237 }; 7238 7239 gpr { 7240 compatible = "qcom,gpr"; 7241 qcom,glink-channels = "adsp_apps"; 7242 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 7243 qcom,intents = <512 20>; 7244 #address-cells = <1>; 7245 #size-cells = <0>; 7246 7247 q6apm: service@1 { 7248 compatible = "qcom,q6apm"; 7249 reg = <GPR_APM_MODULE_IID>; 7250 #sound-dai-cells = <0>; 7251 qcom,protection-domain = "avs/audio", 7252 "msm/adsp/audio_pd"; 7253 7254 q6apmbedai: bedais { 7255 compatible = "qcom,q6apm-lpass-dais"; 7256 #sound-dai-cells = <1>; 7257 }; 7258 7259 q6apmdai: dais { 7260 compatible = "qcom,q6apm-dais"; 7261 iommus = <&apps_smmu 0x3001 0x0>; 7262 }; 7263 }; 7264 7265 q6prm: service@2 { 7266 compatible = "qcom,q6prm"; 7267 reg = <GPR_PRM_MODULE_IID>; 7268 qcom,protection-domain = "avs/audio", 7269 "msm/adsp/audio_pd"; 7270 7271 q6prmcc: clock-controller { 7272 compatible = "qcom,q6prm-lpass-clocks"; 7273 #clock-cells = <2>; 7274 }; 7275 }; 7276 }; 7277 }; 7278 }; 7279 }; 7280 7281 thermal-zones { 7282 aoss-0-thermal { 7283 thermal-sensors = <&tsens0 0>; 7284 7285 trips { 7286 trip-point0 { 7287 temperature = <105000>; 7288 hysteresis = <5000>; 7289 type = "passive"; 7290 }; 7291 7292 trip-point1 { 7293 temperature = <115000>; 7294 hysteresis = <5000>; 7295 type = "passive"; 7296 }; 7297 }; 7298 }; 7299 7300 cpu-0-0-0-thermal { 7301 polling-delay-passive = <10>; 7302 7303 thermal-sensors = <&tsens0 1>; 7304 7305 trips { 7306 trip-point0 { 7307 temperature = <105000>; 7308 hysteresis = <5000>; 7309 type = "passive"; 7310 }; 7311 7312 trip-point1 { 7313 temperature = <115000>; 7314 hysteresis = <5000>; 7315 type = "passive"; 7316 }; 7317 }; 7318 }; 7319 7320 cpu-0-1-0-thermal { 7321 polling-delay-passive = <10>; 7322 7323 thermal-sensors = <&tsens0 2>; 7324 7325 trips { 7326 trip-point0 { 7327 temperature = <105000>; 7328 hysteresis = <5000>; 7329 type = "passive"; 7330 }; 7331 7332 trip-point1 { 7333 temperature = <115000>; 7334 hysteresis = <5000>; 7335 type = "passive"; 7336 }; 7337 }; 7338 }; 7339 7340 cpu-0-2-0-thermal { 7341 polling-delay-passive = <10>; 7342 7343 thermal-sensors = <&tsens0 3>; 7344 7345 trips { 7346 trip-point0 { 7347 temperature = <105000>; 7348 hysteresis = <5000>; 7349 type = "passive"; 7350 }; 7351 7352 trip-point1 { 7353 temperature = <115000>; 7354 hysteresis = <5000>; 7355 type = "passive"; 7356 }; 7357 }; 7358 }; 7359 7360 cpu-0-3-0-thermal { 7361 polling-delay-passive = <10>; 7362 7363 thermal-sensors = <&tsens0 4>; 7364 7365 trips { 7366 trip-point0 { 7367 temperature = <105000>; 7368 hysteresis = <5000>; 7369 type = "passive"; 7370 }; 7371 7372 trip-point1 { 7373 temperature = <115000>; 7374 hysteresis = <5000>; 7375 type = "passive"; 7376 }; 7377 }; 7378 }; 7379 7380 gpuss-0-thermal { 7381 polling-delay-passive = <10>; 7382 7383 thermal-sensors = <&tsens0 5>; 7384 7385 trips { 7386 trip-point0 { 7387 temperature = <105000>; 7388 hysteresis = <5000>; 7389 type = "passive"; 7390 }; 7391 7392 trip-point1 { 7393 temperature = <115000>; 7394 hysteresis = <5000>; 7395 type = "passive"; 7396 }; 7397 }; 7398 }; 7399 7400 gpuss-1-thermal { 7401 polling-delay-passive = <10>; 7402 7403 thermal-sensors = <&tsens0 6>; 7404 7405 trips { 7406 trip-point0 { 7407 temperature = <105000>; 7408 hysteresis = <5000>; 7409 type = "passive"; 7410 }; 7411 7412 trip-point1 { 7413 temperature = <115000>; 7414 hysteresis = <5000>; 7415 type = "passive"; 7416 }; 7417 }; 7418 }; 7419 7420 gpuss-2-thermal { 7421 polling-delay-passive = <10>; 7422 7423 thermal-sensors = <&tsens0 7>; 7424 7425 trips { 7426 trip-point0 { 7427 temperature = <105000>; 7428 hysteresis = <5000>; 7429 type = "passive"; 7430 }; 7431 7432 trip-point1 { 7433 temperature = <115000>; 7434 hysteresis = <5000>; 7435 type = "passive"; 7436 }; 7437 }; 7438 }; 7439 7440 audio-thermal { 7441 thermal-sensors = <&tsens0 8>; 7442 7443 trips { 7444 trip-point0 { 7445 temperature = <105000>; 7446 hysteresis = <5000>; 7447 type = "passive"; 7448 }; 7449 7450 trip-point1 { 7451 temperature = <115000>; 7452 hysteresis = <5000>; 7453 type = "passive"; 7454 }; 7455 }; 7456 }; 7457 7458 camss-0-thermal { 7459 thermal-sensors = <&tsens0 9>; 7460 7461 trips { 7462 trip-point0 { 7463 temperature = <105000>; 7464 hysteresis = <5000>; 7465 type = "passive"; 7466 }; 7467 7468 trip-point1 { 7469 temperature = <115000>; 7470 hysteresis = <5000>; 7471 type = "passive"; 7472 }; 7473 }; 7474 }; 7475 7476 pcie-0-thermal { 7477 thermal-sensors = <&tsens0 10>; 7478 7479 trips { 7480 trip-point0 { 7481 temperature = <105000>; 7482 hysteresis = <5000>; 7483 type = "passive"; 7484 }; 7485 7486 trip-point1 { 7487 temperature = <115000>; 7488 hysteresis = <5000>; 7489 type = "passive"; 7490 }; 7491 }; 7492 }; 7493 7494 cpuss-0-0-thermal { 7495 thermal-sensors = <&tsens0 11>; 7496 7497 trips { 7498 trip-point0 { 7499 temperature = <105000>; 7500 hysteresis = <5000>; 7501 type = "passive"; 7502 }; 7503 7504 trip-point1 { 7505 temperature = <115000>; 7506 hysteresis = <5000>; 7507 type = "passive"; 7508 }; 7509 }; 7510 }; 7511 7512 aoss-1-thermal { 7513 thermal-sensors = <&tsens1 0>; 7514 7515 trips { 7516 trip-point0 { 7517 temperature = <105000>; 7518 hysteresis = <5000>; 7519 type = "passive"; 7520 }; 7521 7522 trip-point1 { 7523 temperature = <115000>; 7524 hysteresis = <5000>; 7525 type = "passive"; 7526 }; 7527 }; 7528 }; 7529 7530 cpu-0-0-1-thermal { 7531 polling-delay-passive = <10>; 7532 7533 thermal-sensors = <&tsens1 1>; 7534 7535 trips { 7536 trip-point0 { 7537 temperature = <105000>; 7538 hysteresis = <5000>; 7539 type = "passive"; 7540 }; 7541 7542 trip-point1 { 7543 temperature = <115000>; 7544 hysteresis = <5000>; 7545 type = "passive"; 7546 }; 7547 }; 7548 }; 7549 7550 cpu-0-1-1-thermal { 7551 polling-delay-passive = <10>; 7552 7553 thermal-sensors = <&tsens1 2>; 7554 7555 trips { 7556 trip-point0 { 7557 temperature = <105000>; 7558 hysteresis = <5000>; 7559 type = "passive"; 7560 }; 7561 7562 trip-point1 { 7563 temperature = <115000>; 7564 hysteresis = <5000>; 7565 type = "passive"; 7566 }; 7567 }; 7568 }; 7569 7570 cpu-0-2-1-thermal { 7571 polling-delay-passive = <10>; 7572 7573 thermal-sensors = <&tsens1 3>; 7574 7575 trips { 7576 trip-point0 { 7577 temperature = <105000>; 7578 hysteresis = <5000>; 7579 type = "passive"; 7580 }; 7581 7582 trip-point1 { 7583 temperature = <115000>; 7584 hysteresis = <5000>; 7585 type = "passive"; 7586 }; 7587 }; 7588 }; 7589 7590 cpu-0-3-1-thermal { 7591 polling-delay-passive = <10>; 7592 7593 thermal-sensors = <&tsens1 4>; 7594 7595 trips { 7596 trip-point0 { 7597 temperature = <105000>; 7598 hysteresis = <5000>; 7599 type = "passive"; 7600 }; 7601 7602 trip-point1 { 7603 temperature = <115000>; 7604 hysteresis = <5000>; 7605 type = "passive"; 7606 }; 7607 }; 7608 }; 7609 7610 gpuss-3-thermal { 7611 polling-delay-passive = <10>; 7612 7613 thermal-sensors = <&tsens1 5>; 7614 7615 trips { 7616 trip-point0 { 7617 temperature = <105000>; 7618 hysteresis = <5000>; 7619 type = "passive"; 7620 }; 7621 7622 trip-point1 { 7623 temperature = <115000>; 7624 hysteresis = <5000>; 7625 type = "passive"; 7626 }; 7627 }; 7628 }; 7629 7630 gpuss-4-thermal { 7631 polling-delay-passive = <10>; 7632 7633 thermal-sensors = <&tsens1 6>; 7634 7635 trips { 7636 trip-point0 { 7637 temperature = <105000>; 7638 hysteresis = <5000>; 7639 type = "passive"; 7640 }; 7641 7642 trip-point1 { 7643 temperature = <115000>; 7644 hysteresis = <5000>; 7645 type = "passive"; 7646 }; 7647 }; 7648 }; 7649 7650 gpuss-5-thermal { 7651 polling-delay-passive = <10>; 7652 7653 thermal-sensors = <&tsens1 7>; 7654 7655 trips { 7656 trip-point0 { 7657 temperature = <105000>; 7658 hysteresis = <5000>; 7659 type = "passive"; 7660 }; 7661 7662 trip-point1 { 7663 temperature = <115000>; 7664 hysteresis = <5000>; 7665 type = "passive"; 7666 }; 7667 }; 7668 }; 7669 7670 video-thermal { 7671 thermal-sensors = <&tsens1 8>; 7672 7673 trips { 7674 trip-point0 { 7675 temperature = <105000>; 7676 hysteresis = <5000>; 7677 type = "passive"; 7678 }; 7679 7680 trip-point1 { 7681 temperature = <115000>; 7682 hysteresis = <5000>; 7683 type = "passive"; 7684 }; 7685 }; 7686 }; 7687 7688 camss-1-thermal { 7689 thermal-sensors = <&tsens1 9>; 7690 7691 trips { 7692 trip-point0 { 7693 temperature = <105000>; 7694 hysteresis = <5000>; 7695 type = "passive"; 7696 }; 7697 7698 trip-point1 { 7699 temperature = <115000>; 7700 hysteresis = <5000>; 7701 type = "passive"; 7702 }; 7703 }; 7704 }; 7705 7706 pcie-1-thermal { 7707 thermal-sensors = <&tsens1 10>; 7708 7709 trips { 7710 trip-point0 { 7711 temperature = <105000>; 7712 hysteresis = <5000>; 7713 type = "passive"; 7714 }; 7715 7716 trip-point1 { 7717 temperature = <115000>; 7718 hysteresis = <5000>; 7719 type = "passive"; 7720 }; 7721 }; 7722 }; 7723 7724 cpuss-0-1-thermal { 7725 thermal-sensors = <&tsens1 11>; 7726 7727 trips { 7728 trip-point0 { 7729 temperature = <105000>; 7730 hysteresis = <5000>; 7731 type = "passive"; 7732 }; 7733 7734 trip-point1 { 7735 temperature = <115000>; 7736 hysteresis = <5000>; 7737 type = "passive"; 7738 }; 7739 }; 7740 }; 7741 7742 aoss-2-thermal { 7743 thermal-sensors = <&tsens2 0>; 7744 7745 trips { 7746 trip-point0 { 7747 temperature = <105000>; 7748 hysteresis = <5000>; 7749 type = "passive"; 7750 }; 7751 7752 trip-point1 { 7753 temperature = <115000>; 7754 hysteresis = <5000>; 7755 type = "passive"; 7756 }; 7757 }; 7758 }; 7759 7760 cpu-1-0-0-thermal { 7761 polling-delay-passive = <10>; 7762 7763 thermal-sensors = <&tsens2 1>; 7764 7765 trips { 7766 trip-point0 { 7767 temperature = <105000>; 7768 hysteresis = <5000>; 7769 type = "passive"; 7770 }; 7771 7772 trip-point1 { 7773 temperature = <115000>; 7774 hysteresis = <5000>; 7775 type = "passive"; 7776 }; 7777 }; 7778 }; 7779 7780 cpu-1-1-0-thermal { 7781 polling-delay-passive = <10>; 7782 7783 thermal-sensors = <&tsens2 2>; 7784 7785 trips { 7786 trip-point0 { 7787 temperature = <105000>; 7788 hysteresis = <5000>; 7789 type = "passive"; 7790 }; 7791 7792 trip-point1 { 7793 temperature = <115000>; 7794 hysteresis = <5000>; 7795 type = "passive"; 7796 }; 7797 }; 7798 }; 7799 7800 cpu-1-2-0-thermal { 7801 polling-delay-passive = <10>; 7802 7803 thermal-sensors = <&tsens2 3>; 7804 7805 trips { 7806 trip-point0 { 7807 temperature = <105000>; 7808 hysteresis = <5000>; 7809 type = "passive"; 7810 }; 7811 7812 trip-point1 { 7813 temperature = <115000>; 7814 hysteresis = <5000>; 7815 type = "passive"; 7816 }; 7817 }; 7818 }; 7819 7820 cpu-1-3-0-thermal { 7821 polling-delay-passive = <10>; 7822 7823 thermal-sensors = <&tsens2 4>; 7824 7825 trips { 7826 trip-point0 { 7827 temperature = <105000>; 7828 hysteresis = <5000>; 7829 type = "passive"; 7830 }; 7831 7832 trip-point1 { 7833 temperature = <115000>; 7834 hysteresis = <5000>; 7835 type = "passive"; 7836 }; 7837 }; 7838 }; 7839 7840 nsp-0-0-0-thermal { 7841 polling-delay-passive = <10>; 7842 7843 thermal-sensors = <&tsens2 5>; 7844 7845 trips { 7846 trip-point0 { 7847 temperature = <105000>; 7848 hysteresis = <5000>; 7849 type = "passive"; 7850 }; 7851 7852 trip-point1 { 7853 temperature = <115000>; 7854 hysteresis = <5000>; 7855 type = "passive"; 7856 }; 7857 }; 7858 }; 7859 7860 nsp-0-1-0-thermal { 7861 polling-delay-passive = <10>; 7862 7863 thermal-sensors = <&tsens2 6>; 7864 7865 trips { 7866 trip-point0 { 7867 temperature = <105000>; 7868 hysteresis = <5000>; 7869 type = "passive"; 7870 }; 7871 7872 trip-point1 { 7873 temperature = <115000>; 7874 hysteresis = <5000>; 7875 type = "passive"; 7876 }; 7877 }; 7878 }; 7879 7880 nsp-0-2-0-thermal { 7881 polling-delay-passive = <10>; 7882 7883 thermal-sensors = <&tsens2 7>; 7884 7885 trips { 7886 trip-point0 { 7887 temperature = <105000>; 7888 hysteresis = <5000>; 7889 type = "passive"; 7890 }; 7891 7892 trip-point1 { 7893 temperature = <115000>; 7894 hysteresis = <5000>; 7895 type = "passive"; 7896 }; 7897 }; 7898 }; 7899 7900 nsp-1-0-0-thermal { 7901 polling-delay-passive = <10>; 7902 7903 thermal-sensors = <&tsens2 8>; 7904 7905 trips { 7906 trip-point0 { 7907 temperature = <105000>; 7908 hysteresis = <5000>; 7909 type = "passive"; 7910 }; 7911 7912 trip-point1 { 7913 temperature = <115000>; 7914 hysteresis = <5000>; 7915 type = "passive"; 7916 }; 7917 }; 7918 }; 7919 7920 nsp-1-1-0-thermal { 7921 polling-delay-passive = <10>; 7922 7923 thermal-sensors = <&tsens2 9>; 7924 7925 trips { 7926 trip-point0 { 7927 temperature = <105000>; 7928 hysteresis = <5000>; 7929 type = "passive"; 7930 }; 7931 7932 trip-point1 { 7933 temperature = <115000>; 7934 hysteresis = <5000>; 7935 type = "passive"; 7936 }; 7937 }; 7938 }; 7939 7940 nsp-1-2-0-thermal { 7941 polling-delay-passive = <10>; 7942 7943 thermal-sensors = <&tsens2 10>; 7944 7945 trips { 7946 trip-point0 { 7947 temperature = <105000>; 7948 hysteresis = <5000>; 7949 type = "passive"; 7950 }; 7951 7952 trip-point1 { 7953 temperature = <115000>; 7954 hysteresis = <5000>; 7955 type = "passive"; 7956 }; 7957 }; 7958 }; 7959 7960 ddrss-0-thermal { 7961 thermal-sensors = <&tsens2 11>; 7962 7963 trips { 7964 trip-point0 { 7965 temperature = <105000>; 7966 hysteresis = <5000>; 7967 type = "passive"; 7968 }; 7969 7970 trip-point1 { 7971 temperature = <115000>; 7972 hysteresis = <5000>; 7973 type = "passive"; 7974 }; 7975 }; 7976 }; 7977 7978 cpuss-1-0-thermal { 7979 thermal-sensors = <&tsens2 12>; 7980 7981 trips { 7982 trip-point0 { 7983 temperature = <105000>; 7984 hysteresis = <5000>; 7985 type = "passive"; 7986 }; 7987 7988 trip-point1 { 7989 temperature = <115000>; 7990 hysteresis = <5000>; 7991 type = "passive"; 7992 }; 7993 }; 7994 }; 7995 7996 aoss-3-thermal { 7997 thermal-sensors = <&tsens3 0>; 7998 7999 trips { 8000 trip-point0 { 8001 temperature = <105000>; 8002 hysteresis = <5000>; 8003 type = "passive"; 8004 }; 8005 8006 trip-point1 { 8007 temperature = <115000>; 8008 hysteresis = <5000>; 8009 type = "passive"; 8010 }; 8011 }; 8012 }; 8013 8014 cpu-1-0-1-thermal { 8015 polling-delay-passive = <10>; 8016 8017 thermal-sensors = <&tsens3 1>; 8018 8019 trips { 8020 trip-point0 { 8021 temperature = <105000>; 8022 hysteresis = <5000>; 8023 type = "passive"; 8024 }; 8025 8026 trip-point1 { 8027 temperature = <115000>; 8028 hysteresis = <5000>; 8029 type = "passive"; 8030 }; 8031 }; 8032 }; 8033 8034 cpu-1-1-1-thermal { 8035 polling-delay-passive = <10>; 8036 8037 thermal-sensors = <&tsens3 2>; 8038 8039 trips { 8040 trip-point0 { 8041 temperature = <105000>; 8042 hysteresis = <5000>; 8043 type = "passive"; 8044 }; 8045 8046 trip-point1 { 8047 temperature = <115000>; 8048 hysteresis = <5000>; 8049 type = "passive"; 8050 }; 8051 }; 8052 }; 8053 8054 cpu-1-2-1-thermal { 8055 polling-delay-passive = <10>; 8056 8057 thermal-sensors = <&tsens3 3>; 8058 8059 trips { 8060 trip-point0 { 8061 temperature = <105000>; 8062 hysteresis = <5000>; 8063 type = "passive"; 8064 }; 8065 8066 trip-point1 { 8067 temperature = <115000>; 8068 hysteresis = <5000>; 8069 type = "passive"; 8070 }; 8071 }; 8072 }; 8073 8074 cpu-1-3-1-thermal { 8075 polling-delay-passive = <10>; 8076 8077 thermal-sensors = <&tsens3 4>; 8078 8079 trips { 8080 trip-point0 { 8081 temperature = <105000>; 8082 hysteresis = <5000>; 8083 type = "passive"; 8084 }; 8085 8086 trip-point1 { 8087 temperature = <115000>; 8088 hysteresis = <5000>; 8089 type = "passive"; 8090 }; 8091 }; 8092 }; 8093 8094 nsp-0-0-1-thermal { 8095 polling-delay-passive = <10>; 8096 8097 thermal-sensors = <&tsens3 5>; 8098 8099 trips { 8100 trip-point0 { 8101 temperature = <105000>; 8102 hysteresis = <5000>; 8103 type = "passive"; 8104 }; 8105 8106 trip-point1 { 8107 temperature = <115000>; 8108 hysteresis = <5000>; 8109 type = "passive"; 8110 }; 8111 }; 8112 }; 8113 8114 nsp-0-1-1-thermal { 8115 polling-delay-passive = <10>; 8116 8117 thermal-sensors = <&tsens3 6>; 8118 8119 trips { 8120 trip-point0 { 8121 temperature = <105000>; 8122 hysteresis = <5000>; 8123 type = "passive"; 8124 }; 8125 8126 trip-point1 { 8127 temperature = <115000>; 8128 hysteresis = <5000>; 8129 type = "passive"; 8130 }; 8131 }; 8132 }; 8133 8134 nsp-0-2-1-thermal { 8135 polling-delay-passive = <10>; 8136 8137 thermal-sensors = <&tsens3 7>; 8138 8139 trips { 8140 trip-point0 { 8141 temperature = <105000>; 8142 hysteresis = <5000>; 8143 type = "passive"; 8144 }; 8145 8146 trip-point1 { 8147 temperature = <115000>; 8148 hysteresis = <5000>; 8149 type = "passive"; 8150 }; 8151 }; 8152 }; 8153 8154 nsp-1-0-1-thermal { 8155 polling-delay-passive = <10>; 8156 8157 thermal-sensors = <&tsens3 8>; 8158 8159 trips { 8160 trip-point0 { 8161 temperature = <105000>; 8162 hysteresis = <5000>; 8163 type = "passive"; 8164 }; 8165 8166 trip-point1 { 8167 temperature = <115000>; 8168 hysteresis = <5000>; 8169 type = "passive"; 8170 }; 8171 }; 8172 }; 8173 8174 nsp-1-1-1-thermal { 8175 polling-delay-passive = <10>; 8176 8177 thermal-sensors = <&tsens3 9>; 8178 8179 trips { 8180 trip-point0 { 8181 temperature = <105000>; 8182 hysteresis = <5000>; 8183 type = "passive"; 8184 }; 8185 8186 trip-point1 { 8187 temperature = <115000>; 8188 hysteresis = <5000>; 8189 type = "passive"; 8190 }; 8191 }; 8192 }; 8193 8194 nsp-1-2-1-thermal { 8195 polling-delay-passive = <10>; 8196 8197 thermal-sensors = <&tsens3 10>; 8198 8199 trips { 8200 trip-point0 { 8201 temperature = <105000>; 8202 hysteresis = <5000>; 8203 type = "passive"; 8204 }; 8205 8206 trip-point1 { 8207 temperature = <115000>; 8208 hysteresis = <5000>; 8209 type = "passive"; 8210 }; 8211 }; 8212 }; 8213 8214 ddrss-1-thermal { 8215 thermal-sensors = <&tsens3 11>; 8216 8217 trips { 8218 trip-point0 { 8219 temperature = <105000>; 8220 hysteresis = <5000>; 8221 type = "passive"; 8222 }; 8223 8224 trip-point1 { 8225 temperature = <115000>; 8226 hysteresis = <5000>; 8227 type = "passive"; 8228 }; 8229 }; 8230 }; 8231 8232 cpuss-1-1-thermal { 8233 thermal-sensors = <&tsens3 12>; 8234 8235 trips { 8236 trip-point0 { 8237 temperature = <105000>; 8238 hysteresis = <5000>; 8239 type = "passive"; 8240 }; 8241 8242 trip-point1 { 8243 temperature = <115000>; 8244 hysteresis = <5000>; 8245 type = "passive"; 8246 }; 8247 }; 8248 }; 8249 }; 8250 8251 arch_timer: timer { 8252 compatible = "arm,armv8-timer"; 8253 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 8254 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 8255 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 8256 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 8257 }; 8258 8259 pcie0: pcie@1c00000 { 8260 compatible = "qcom,pcie-sa8775p"; 8261 reg = <0x0 0x01c00000 0x0 0x3000>, 8262 <0x0 0x40000000 0x0 0xf20>, 8263 <0x0 0x40000f20 0x0 0xa8>, 8264 <0x0 0x40001000 0x0 0x4000>, 8265 <0x0 0x40100000 0x0 0x100000>, 8266 <0x0 0x01c03000 0x0 0x1000>; 8267 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 8268 device_type = "pci"; 8269 8270 #address-cells = <3>; 8271 #size-cells = <2>; 8272 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 8273 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 8274 bus-range = <0x00 0xff>; 8275 8276 dma-coherent; 8277 8278 linux,pci-domain = <0>; 8279 num-lanes = <2>; 8280 8281 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 8282 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 8283 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 8284 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 8285 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 8286 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 8287 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 8288 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 8289 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 8290 interrupt-names = "msi0", 8291 "msi1", 8292 "msi2", 8293 "msi3", 8294 "msi4", 8295 "msi5", 8296 "msi6", 8297 "msi7", 8298 "global"; 8299 #interrupt-cells = <1>; 8300 interrupt-map-mask = <0 0 0 0x7>; 8301 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 8302 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 8303 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 8304 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 8305 8306 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 8307 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 8308 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 8309 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 8310 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 8311 8312 clock-names = "aux", 8313 "cfg", 8314 "bus_master", 8315 "bus_slave", 8316 "slave_q2a"; 8317 8318 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 8319 assigned-clock-rates = <19200000>; 8320 8321 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 8322 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 8323 interconnect-names = "pcie-mem", "cpu-pcie"; 8324 8325 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 8326 <0x100 &pcie_smmu 0x0001 0x1>; 8327 8328 resets = <&gcc GCC_PCIE_0_BCR>, 8329 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; 8330 reset-names = "pci", 8331 "link_down"; 8332 8333 power-domains = <&gcc PCIE_0_GDSC>; 8334 8335 phys = <&pcie0_phy>; 8336 phy-names = "pciephy"; 8337 8338 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 8339 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 8340 8341 status = "disabled"; 8342 8343 pcieport0: pcie@0 { 8344 device_type = "pci"; 8345 reg = <0x0 0x0 0x0 0x0 0x0>; 8346 bus-range = <0x01 0xff>; 8347 8348 #address-cells = <3>; 8349 #size-cells = <2>; 8350 ranges; 8351 }; 8352 }; 8353 8354 pcie0_ep: pcie-ep@1c00000 { 8355 compatible = "qcom,sa8775p-pcie-ep"; 8356 reg = <0x0 0x01c00000 0x0 0x3000>, 8357 <0x0 0x40000000 0x0 0xf20>, 8358 <0x0 0x40000f20 0x0 0xa8>, 8359 <0x0 0x40001000 0x0 0x4000>, 8360 <0x0 0x40200000 0x0 0x1fe00000>, 8361 <0x0 0x01c03000 0x0 0x1000>, 8362 <0x0 0x40005000 0x0 0x2000>; 8363 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 8364 "mmio", "dma"; 8365 8366 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 8367 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 8368 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 8369 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 8370 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 8371 8372 clock-names = "aux", 8373 "cfg", 8374 "bus_master", 8375 "bus_slave", 8376 "slave_q2a"; 8377 8378 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 8379 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 8380 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; 8381 8382 interrupt-names = "global", "doorbell", "dma"; 8383 8384 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 8385 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 8386 interconnect-names = "pcie-mem", "cpu-pcie"; 8387 8388 dma-coherent; 8389 iommus = <&pcie_smmu 0x0000 0x7f>; 8390 resets = <&gcc GCC_PCIE_0_BCR>; 8391 reset-names = "core"; 8392 power-domains = <&gcc PCIE_0_GDSC>; 8393 phys = <&pcie0_phy>; 8394 phy-names = "pciephy"; 8395 num-lanes = <2>; 8396 linux,pci-domain = <0>; 8397 8398 status = "disabled"; 8399 }; 8400 8401 pcie0_phy: phy@1c04000 { 8402 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 8403 reg = <0x0 0x1c04000 0x0 0x2000>; 8404 8405 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, 8406 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 8407 <&gcc GCC_PCIE_CLKREF_EN>, 8408 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 8409 <&gcc GCC_PCIE_0_PIPE_CLK>, 8410 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; 8411 clock-names = "aux", 8412 "cfg_ahb", 8413 "ref", 8414 "rchng", 8415 "pipe", 8416 "pipediv2"; 8417 8418 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 8419 assigned-clock-rates = <100000000>; 8420 8421 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 8422 reset-names = "phy"; 8423 8424 #clock-cells = <0>; 8425 clock-output-names = "pcie_0_pipe_clk"; 8426 8427 #phy-cells = <0>; 8428 8429 status = "disabled"; 8430 }; 8431 8432 pcie1: pcie@1c10000 { 8433 compatible = "qcom,pcie-sa8775p"; 8434 reg = <0x0 0x01c10000 0x0 0x3000>, 8435 <0x0 0x60000000 0x0 0xf20>, 8436 <0x0 0x60000f20 0x0 0xa8>, 8437 <0x0 0x60001000 0x0 0x4000>, 8438 <0x0 0x60100000 0x0 0x100000>, 8439 <0x0 0x01c13000 0x0 0x1000>; 8440 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 8441 device_type = "pci"; 8442 8443 #address-cells = <3>; 8444 #size-cells = <2>; 8445 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 8446 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 8447 bus-range = <0x00 0xff>; 8448 8449 dma-coherent; 8450 8451 linux,pci-domain = <1>; 8452 num-lanes = <4>; 8453 8454 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 8455 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 8456 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 8457 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 8458 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 8459 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 8460 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 8461 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 8462 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; 8463 interrupt-names = "msi0", 8464 "msi1", 8465 "msi2", 8466 "msi3", 8467 "msi4", 8468 "msi5", 8469 "msi6", 8470 "msi7", 8471 "global"; 8472 #interrupt-cells = <1>; 8473 interrupt-map-mask = <0 0 0 0x7>; 8474 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 8475 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 8476 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 8477 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 8478 8479 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 8480 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 8481 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 8482 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 8483 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 8484 8485 clock-names = "aux", 8486 "cfg", 8487 "bus_master", 8488 "bus_slave", 8489 "slave_q2a"; 8490 8491 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 8492 assigned-clock-rates = <19200000>; 8493 8494 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 8495 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 8496 interconnect-names = "pcie-mem", "cpu-pcie"; 8497 8498 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 8499 <0x100 &pcie_smmu 0x0081 0x1>; 8500 8501 resets = <&gcc GCC_PCIE_1_BCR>, 8502 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 8503 reset-names = "pci", 8504 "link_down"; 8505 8506 power-domains = <&gcc PCIE_1_GDSC>; 8507 8508 phys = <&pcie1_phy>; 8509 phy-names = "pciephy"; 8510 8511 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 8512 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 8513 8514 status = "disabled"; 8515 8516 pcie@0 { 8517 device_type = "pci"; 8518 reg = <0x0 0x0 0x0 0x0 0x0>; 8519 bus-range = <0x01 0xff>; 8520 8521 #address-cells = <3>; 8522 #size-cells = <2>; 8523 ranges; 8524 }; 8525 }; 8526 8527 pcie1_ep: pcie-ep@1c10000 { 8528 compatible = "qcom,sa8775p-pcie-ep"; 8529 reg = <0x0 0x01c10000 0x0 0x3000>, 8530 <0x0 0x60000000 0x0 0xf20>, 8531 <0x0 0x60000f20 0x0 0xa8>, 8532 <0x0 0x60001000 0x0 0x4000>, 8533 <0x0 0x60200000 0x0 0x1fe00000>, 8534 <0x0 0x01c13000 0x0 0x1000>, 8535 <0x0 0x60005000 0x0 0x2000>; 8536 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 8537 "mmio", "dma"; 8538 8539 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 8540 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 8541 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 8542 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 8543 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 8544 8545 clock-names = "aux", 8546 "cfg", 8547 "bus_master", 8548 "bus_slave", 8549 "slave_q2a"; 8550 8551 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 8552 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 8553 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 8554 8555 interrupt-names = "global", "doorbell", "dma"; 8556 8557 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 8558 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 8559 interconnect-names = "pcie-mem", "cpu-pcie"; 8560 8561 dma-coherent; 8562 iommus = <&pcie_smmu 0x80 0x7f>; 8563 resets = <&gcc GCC_PCIE_1_BCR>; 8564 reset-names = "core"; 8565 power-domains = <&gcc PCIE_1_GDSC>; 8566 phys = <&pcie1_phy>; 8567 phy-names = "pciephy"; 8568 num-lanes = <4>; 8569 linux,pci-domain = <1>; 8570 8571 status = "disabled"; 8572 }; 8573 8574 pcie1_phy: phy@1c14000 { 8575 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 8576 reg = <0x0 0x1c14000 0x0 0x4000>; 8577 8578 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 8579 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 8580 <&gcc GCC_PCIE_CLKREF_EN>, 8581 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 8582 <&gcc GCC_PCIE_1_PIPE_CLK>, 8583 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; 8584 clock-names = "aux", 8585 "cfg_ahb", 8586 "ref", 8587 "rchng", 8588 "pipe", 8589 "pipediv2"; 8590 8591 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 8592 assigned-clock-rates = <100000000>; 8593 8594 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 8595 reset-names = "phy"; 8596 8597 #clock-cells = <0>; 8598 clock-output-names = "pcie_1_pipe_clk"; 8599 8600 #phy-cells = <0>; 8601 8602 status = "disabled"; 8603 }; 8604}; 8605