1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#include <dt-bindings/interconnect/qcom,icc.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 12#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 13#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 14#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 15#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/firmware/qcom,scm.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 clocks { 33 xo_board_clk: xo-board-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "qcom,kryo"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 power-domains = <&cpu_pd0>; 54 power-domain-names = "psci"; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 next-level-cache = <&l2_0>; 57 capacity-dmips-mhz = <1024>; 58 #cooling-cells = <2>; 59 dynamic-power-coefficient = <100>; 60 operating-points-v2 = <&cpu0_opp_table>; 61 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 62 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 63 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 64 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 65 l2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&l3_0>; 70 l3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 cpu1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo"; 81 reg = <0x0 0x100>; 82 enable-method = "psci"; 83 power-domains = <&cpu_pd1>; 84 power-domain-names = "psci"; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 next-level-cache = <&l2_1>; 87 capacity-dmips-mhz = <1024>; 88 #cooling-cells = <2>; 89 dynamic-power-coefficient = <100>; 90 operating-points-v2 = <&cpu0_opp_table>; 91 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 92 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 93 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 94 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 95 l2_1: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 next-level-cache = <&l3_0>; 100 }; 101 }; 102 103 cpu2: cpu@200 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo"; 106 reg = <0x0 0x200>; 107 enable-method = "psci"; 108 power-domains = <&cpu_pd2>; 109 power-domain-names = "psci"; 110 qcom,freq-domain = <&cpufreq_hw 0>; 111 next-level-cache = <&l2_2>; 112 capacity-dmips-mhz = <1024>; 113 #cooling-cells = <2>; 114 dynamic-power-coefficient = <100>; 115 operating-points-v2 = <&cpu0_opp_table>; 116 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 117 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 118 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 119 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 120 l2_2: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 cache-unified; 124 next-level-cache = <&l3_0>; 125 }; 126 }; 127 128 cpu3: cpu@300 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo"; 131 reg = <0x0 0x300>; 132 enable-method = "psci"; 133 power-domains = <&cpu_pd3>; 134 power-domain-names = "psci"; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 next-level-cache = <&l2_3>; 137 capacity-dmips-mhz = <1024>; 138 #cooling-cells = <2>; 139 dynamic-power-coefficient = <100>; 140 operating-points-v2 = <&cpu0_opp_table>; 141 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 143 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 144 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 145 l2_3: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&l3_0>; 150 }; 151 }; 152 153 cpu4: cpu@10000 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo"; 156 reg = <0x0 0x10000>; 157 enable-method = "psci"; 158 power-domains = <&cpu_pd4>; 159 power-domain-names = "psci"; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 next-level-cache = <&l2_4>; 162 capacity-dmips-mhz = <1024>; 163 #cooling-cells = <2>; 164 dynamic-power-coefficient = <100>; 165 operating-points-v2 = <&cpu4_opp_table>; 166 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 167 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 168 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 169 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 170 l2_4: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_1>; 175 l3_1: l3-cache { 176 compatible = "cache"; 177 cache-level = <3>; 178 cache-unified; 179 }; 180 181 }; 182 }; 183 184 cpu5: cpu@10100 { 185 device_type = "cpu"; 186 compatible = "qcom,kryo"; 187 reg = <0x0 0x10100>; 188 enable-method = "psci"; 189 power-domains = <&cpu_pd5>; 190 power-domain-names = "psci"; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 next-level-cache = <&l2_5>; 193 capacity-dmips-mhz = <1024>; 194 #cooling-cells = <2>; 195 dynamic-power-coefficient = <100>; 196 operating-points-v2 = <&cpu4_opp_table>; 197 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 198 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 199 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 200 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 201 l2_5: l2-cache { 202 compatible = "cache"; 203 cache-level = <2>; 204 cache-unified; 205 next-level-cache = <&l3_1>; 206 }; 207 }; 208 209 cpu6: cpu@10200 { 210 device_type = "cpu"; 211 compatible = "qcom,kryo"; 212 reg = <0x0 0x10200>; 213 enable-method = "psci"; 214 power-domains = <&cpu_pd6>; 215 power-domain-names = "psci"; 216 qcom,freq-domain = <&cpufreq_hw 1>; 217 next-level-cache = <&l2_6>; 218 capacity-dmips-mhz = <1024>; 219 #cooling-cells = <2>; 220 dynamic-power-coefficient = <100>; 221 operating-points-v2 = <&cpu4_opp_table>; 222 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 223 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 224 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 225 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 226 l2_6: l2-cache { 227 compatible = "cache"; 228 cache-level = <2>; 229 cache-unified; 230 next-level-cache = <&l3_1>; 231 }; 232 }; 233 234 cpu7: cpu@10300 { 235 device_type = "cpu"; 236 compatible = "qcom,kryo"; 237 reg = <0x0 0x10300>; 238 enable-method = "psci"; 239 power-domains = <&cpu_pd7>; 240 power-domain-names = "psci"; 241 qcom,freq-domain = <&cpufreq_hw 1>; 242 next-level-cache = <&l2_7>; 243 capacity-dmips-mhz = <1024>; 244 #cooling-cells = <2>; 245 dynamic-power-coefficient = <100>; 246 operating-points-v2 = <&cpu4_opp_table>; 247 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 248 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 249 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 250 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 251 l2_7: l2-cache { 252 compatible = "cache"; 253 cache-level = <2>; 254 cache-unified; 255 next-level-cache = <&l3_1>; 256 }; 257 }; 258 259 cpu-map { 260 cluster0 { 261 core0 { 262 cpu = <&cpu0>; 263 }; 264 265 core1 { 266 cpu = <&cpu1>; 267 }; 268 269 core2 { 270 cpu = <&cpu2>; 271 }; 272 273 core3 { 274 cpu = <&cpu3>; 275 }; 276 }; 277 278 cluster1 { 279 core0 { 280 cpu = <&cpu4>; 281 }; 282 283 core1 { 284 cpu = <&cpu5>; 285 }; 286 287 core2 { 288 cpu = <&cpu6>; 289 }; 290 291 core3 { 292 cpu = <&cpu7>; 293 }; 294 }; 295 }; 296 297 idle-states { 298 entry-method = "psci"; 299 300 gold_cpu_sleep_0: cpu-sleep-0 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "gold-power-collapse"; 303 arm,psci-suspend-param = <0x40000003>; 304 entry-latency-us = <549>; 305 exit-latency-us = <901>; 306 min-residency-us = <1774>; 307 local-timer-stop; 308 }; 309 310 gold_rail_cpu_sleep_0: cpu-sleep-1 { 311 compatible = "arm,idle-state"; 312 idle-state-name = "gold-rail-power-collapse"; 313 arm,psci-suspend-param = <0x40000004>; 314 entry-latency-us = <702>; 315 exit-latency-us = <1061>; 316 min-residency-us = <4488>; 317 local-timer-stop; 318 }; 319 }; 320 321 domain-idle-states { 322 cluster_sleep_gold: cluster-sleep-0 { 323 compatible = "domain-idle-state"; 324 arm,psci-suspend-param = <0x41000044>; 325 entry-latency-us = <2752>; 326 exit-latency-us = <3048>; 327 min-residency-us = <6118>; 328 }; 329 330 cluster_sleep_apss_rsc_pc: cluster-sleep-1 { 331 compatible = "domain-idle-state"; 332 arm,psci-suspend-param = <0x42000144>; 333 entry-latency-us = <3263>; 334 exit-latency-us = <6562>; 335 min-residency-us = <9987>; 336 }; 337 }; 338 }; 339 340 cpu0_opp_table: opp-table-cpu0 { 341 compatible = "operating-points-v2"; 342 opp-shared; 343 344 opp-1267200000 { 345 opp-hz = /bits/ 64 <1267200000>; 346 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 347 }; 348 349 opp-1363200000 { 350 opp-hz = /bits/ 64 <1363200000>; 351 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 352 }; 353 354 opp-1459200000 { 355 opp-hz = /bits/ 64 <1459200000>; 356 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 357 }; 358 359 opp-1536000000 { 360 opp-hz = /bits/ 64 <1536000000>; 361 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 362 }; 363 364 opp-1632000000 { 365 opp-hz = /bits/ 64 <1632000000>; 366 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 367 }; 368 369 opp-1708800000 { 370 opp-hz = /bits/ 64 <1708800000>; 371 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 372 }; 373 374 opp-1785600000 { 375 opp-hz = /bits/ 64 <1785600000>; 376 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 377 }; 378 379 opp-1862400000 { 380 opp-hz = /bits/ 64 <1862400000>; 381 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 382 }; 383 384 opp-1939200000 { 385 opp-hz = /bits/ 64 <1939200000>; 386 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 387 }; 388 389 opp-2016000000 { 390 opp-hz = /bits/ 64 <2016000000>; 391 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 392 }; 393 394 opp-2112000000 { 395 opp-hz = /bits/ 64 <2112000000>; 396 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 397 }; 398 399 opp-2188800000 { 400 opp-hz = /bits/ 64 <2188800000>; 401 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 402 }; 403 404 opp-2265600000 { 405 opp-hz = /bits/ 64 <2265600000>; 406 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 407 }; 408 409 opp-2361600000 { 410 opp-hz = /bits/ 64 <2361600000>; 411 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 412 }; 413 414 opp-2457600000 { 415 opp-hz = /bits/ 64 <2457600000>; 416 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 417 }; 418 419 opp-2553600000 { 420 opp-hz = /bits/ 64 <2553600000>; 421 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 422 }; 423 }; 424 425 cpu4_opp_table: opp-table-cpu4 { 426 compatible = "operating-points-v2"; 427 opp-shared; 428 429 opp-1267200000 { 430 opp-hz = /bits/ 64 <1267200000>; 431 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 432 }; 433 434 opp-1363200000 { 435 opp-hz = /bits/ 64 <1363200000>; 436 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 437 }; 438 439 opp-1459200000 { 440 opp-hz = /bits/ 64 <1459200000>; 441 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 442 }; 443 444 opp-1536000000 { 445 opp-hz = /bits/ 64 <1536000000>; 446 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 447 }; 448 449 opp-1632000000 { 450 opp-hz = /bits/ 64 <1632000000>; 451 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 452 }; 453 454 opp-1708800000 { 455 opp-hz = /bits/ 64 <1708800000>; 456 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 457 }; 458 459 opp-1785600000 { 460 opp-hz = /bits/ 64 <1785600000>; 461 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 462 }; 463 464 opp-1862400000 { 465 opp-hz = /bits/ 64 <1862400000>; 466 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 467 }; 468 469 opp-1939200000 { 470 opp-hz = /bits/ 64 <1939200000>; 471 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 472 }; 473 474 opp-2016000000 { 475 opp-hz = /bits/ 64 <2016000000>; 476 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 477 }; 478 479 opp-2112000000 { 480 opp-hz = /bits/ 64 <2112000000>; 481 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 482 }; 483 484 opp-2188800000 { 485 opp-hz = /bits/ 64 <2188800000>; 486 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 487 }; 488 489 opp-2265600000 { 490 opp-hz = /bits/ 64 <2265600000>; 491 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 492 }; 493 494 opp-2361600000 { 495 opp-hz = /bits/ 64 <2361600000>; 496 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 497 }; 498 499 opp-2457600000 { 500 opp-hz = /bits/ 64 <2457600000>; 501 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 502 }; 503 504 opp-2553600000 { 505 opp-hz = /bits/ 64 <2553600000>; 506 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 507 }; 508 }; 509 510 dummy-sink { 511 compatible = "arm,coresight-dummy-sink"; 512 513 in-ports { 514 port { 515 eud_in: endpoint { 516 remote-endpoint = 517 <&swao_rep_out1>; 518 }; 519 }; 520 }; 521 }; 522 523 firmware { 524 scm { 525 compatible = "qcom,scm-sa8775p", "qcom,scm"; 526 qcom,dload-mode = <&tcsr 0x13000>; 527 }; 528 }; 529 530 clk_virt: interconnect-clk-virt { 531 compatible = "qcom,sa8775p-clk-virt"; 532 #interconnect-cells = <2>; 533 qcom,bcm-voters = <&apps_bcm_voter>; 534 }; 535 536 mc_virt: interconnect-mc-virt { 537 compatible = "qcom,sa8775p-mc-virt"; 538 #interconnect-cells = <2>; 539 qcom,bcm-voters = <&apps_bcm_voter>; 540 }; 541 542 /* Will be updated by the bootloader. */ 543 memory@80000000 { 544 device_type = "memory"; 545 reg = <0x0 0x80000000 0x0 0x0>; 546 }; 547 548 qup_opp_table_100mhz: opp-table-qup100mhz { 549 compatible = "operating-points-v2"; 550 551 opp-100000000 { 552 opp-hz = /bits/ 64 <100000000>; 553 required-opps = <&rpmhpd_opp_svs_l1>; 554 }; 555 }; 556 557 pmu { 558 compatible = "arm,armv8-pmuv3"; 559 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 560 }; 561 562 psci { 563 compatible = "arm,psci-1.0"; 564 method = "smc"; 565 566 cpu_pd0: power-domain-cpu0 { 567 #power-domain-cells = <0>; 568 power-domains = <&cluster_0_pd>; 569 domain-idle-states = <&gold_cpu_sleep_0>, 570 <&gold_rail_cpu_sleep_0>; 571 }; 572 573 cpu_pd1: power-domain-cpu1 { 574 #power-domain-cells = <0>; 575 power-domains = <&cluster_0_pd>; 576 domain-idle-states = <&gold_cpu_sleep_0>, 577 <&gold_rail_cpu_sleep_0>; 578 }; 579 580 cpu_pd2: power-domain-cpu2 { 581 #power-domain-cells = <0>; 582 power-domains = <&cluster_0_pd>; 583 domain-idle-states = <&gold_cpu_sleep_0>, 584 <&gold_rail_cpu_sleep_0>; 585 }; 586 587 cpu_pd3: power-domain-cpu3 { 588 #power-domain-cells = <0>; 589 power-domains = <&cluster_0_pd>; 590 domain-idle-states = <&gold_cpu_sleep_0>, 591 <&gold_rail_cpu_sleep_0>; 592 }; 593 594 cpu_pd4: power-domain-cpu4 { 595 #power-domain-cells = <0>; 596 power-domains = <&cluster_1_pd>; 597 domain-idle-states = <&gold_cpu_sleep_0>, 598 <&gold_rail_cpu_sleep_0>; 599 }; 600 601 cpu_pd5: power-domain-cpu5 { 602 #power-domain-cells = <0>; 603 power-domains = <&cluster_1_pd>; 604 domain-idle-states = <&gold_cpu_sleep_0>, 605 <&gold_rail_cpu_sleep_0>; 606 }; 607 608 cpu_pd6: power-domain-cpu6 { 609 #power-domain-cells = <0>; 610 power-domains = <&cluster_1_pd>; 611 domain-idle-states = <&gold_cpu_sleep_0>, 612 <&gold_rail_cpu_sleep_0>; 613 }; 614 615 cpu_pd7: power-domain-cpu7 { 616 #power-domain-cells = <0>; 617 power-domains = <&cluster_1_pd>; 618 domain-idle-states = <&gold_cpu_sleep_0>, 619 <&gold_rail_cpu_sleep_0>; 620 }; 621 622 cluster_0_pd: power-domain-cluster0 { 623 #power-domain-cells = <0>; 624 domain-idle-states = <&cluster_sleep_gold>; 625 power-domains = <&system_pd>; 626 }; 627 628 cluster_1_pd: power-domain-cluster1 { 629 #power-domain-cells = <0>; 630 domain-idle-states = <&cluster_sleep_gold>; 631 power-domains = <&system_pd>; 632 }; 633 634 system_pd: power-domain-system { 635 #power-domain-cells = <0>; 636 domain-idle-states = <&cluster_sleep_apss_rsc_pc>; 637 }; 638 }; 639 640 reserved-memory { 641 #address-cells = <2>; 642 #size-cells = <2>; 643 ranges; 644 645 sail_ss_mem: sail-ss@80000000 { 646 reg = <0x0 0x80000000 0x0 0x10000000>; 647 no-map; 648 }; 649 650 hyp_mem: hyp@90000000 { 651 reg = <0x0 0x90000000 0x0 0x600000>; 652 no-map; 653 }; 654 655 xbl_boot_mem: xbl-boot@90600000 { 656 reg = <0x0 0x90600000 0x0 0x200000>; 657 no-map; 658 }; 659 660 aop_image_mem: aop-image@90800000 { 661 reg = <0x0 0x90800000 0x0 0x60000>; 662 no-map; 663 }; 664 665 aop_cmd_db_mem: aop-cmd-db@90860000 { 666 compatible = "qcom,cmd-db"; 667 reg = <0x0 0x90860000 0x0 0x20000>; 668 no-map; 669 }; 670 671 uefi_log: uefi-log@908b0000 { 672 reg = <0x0 0x908b0000 0x0 0x10000>; 673 no-map; 674 }; 675 676 ddr_training_checksum: ddr-training-checksum@908c0000 { 677 reg = <0x0 0x908c0000 0x0 0x1000>; 678 no-map; 679 }; 680 681 reserved_mem: reserved@908f0000 { 682 reg = <0x0 0x908f0000 0x0 0xe000>; 683 no-map; 684 }; 685 686 secdata_apss_mem: secdata-apss@908fe000 { 687 reg = <0x0 0x908fe000 0x0 0x2000>; 688 no-map; 689 }; 690 691 smem_mem: smem@90900000 { 692 compatible = "qcom,smem"; 693 reg = <0x0 0x90900000 0x0 0x200000>; 694 no-map; 695 hwlocks = <&tcsr_mutex 3>; 696 }; 697 698 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { 699 reg = <0x0 0x90c00000 0x0 0x100000>; 700 no-map; 701 }; 702 703 sail_mailbox_mem: sail-ss@90d00000 { 704 reg = <0x0 0x90d00000 0x0 0x100000>; 705 no-map; 706 }; 707 708 sail_ota_mem: sail-ss@90e00000 { 709 reg = <0x0 0x90e00000 0x0 0x300000>; 710 no-map; 711 }; 712 713 gunyah_md_mem: gunyah-md@91a80000 { 714 reg = <0x0 0x91a80000 0x0 0x80000>; 715 no-map; 716 }; 717 718 aoss_backup_mem: aoss-backup@91b00000 { 719 reg = <0x0 0x91b00000 0x0 0x40000>; 720 no-map; 721 }; 722 723 cpucp_backup_mem: cpucp-backup@91b40000 { 724 reg = <0x0 0x91b40000 0x0 0x40000>; 725 no-map; 726 }; 727 728 tz_config_backup_mem: tz-config-backup@91b80000 { 729 reg = <0x0 0x91b80000 0x0 0x10000>; 730 no-map; 731 }; 732 733 ddr_training_data_mem: ddr-training-data@91b90000 { 734 reg = <0x0 0x91b90000 0x0 0x10000>; 735 no-map; 736 }; 737 738 cdt_data_backup_mem: cdt-data-backup@91ba0000 { 739 reg = <0x0 0x91ba0000 0x0 0x1000>; 740 no-map; 741 }; 742 743 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 744 reg = <0x0 0x93b00000 0x0 0xf00000>; 745 no-map; 746 }; 747 748 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 749 reg = <0x0 0x94a00000 0x0 0x800000>; 750 no-map; 751 }; 752 753 pil_camera_mem: pil-camera@95200000 { 754 reg = <0x0 0x95200000 0x0 0x700000>; 755 no-map; 756 }; 757 758 pil_adsp_mem: pil-adsp@95900000 { 759 reg = <0x0 0x95900000 0x0 0x1e00000>; 760 no-map; 761 }; 762 763 q6_adsp_dtb_mem: q6-adsp-dtb@97700000 { 764 reg = <0x0 0x97700000 0x0 0x80000>; 765 no-map; 766 }; 767 768 q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 { 769 reg = <0x0 0x97780000 0x0 0x80000>; 770 no-map; 771 }; 772 773 pil_gdsp0_mem: pil-gdsp0@97800000 { 774 reg = <0x0 0x97800000 0x0 0x1e00000>; 775 no-map; 776 }; 777 778 pil_gdsp1_mem: pil-gdsp1@99600000 { 779 reg = <0x0 0x99600000 0x0 0x1e00000>; 780 no-map; 781 }; 782 783 q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 { 784 reg = <0x0 0x9b400000 0x0 0x80000>; 785 no-map; 786 }; 787 788 q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 { 789 reg = <0x0 0x9b480000 0x0 0x80000>; 790 no-map; 791 }; 792 793 pil_cdsp0_mem: pil-cdsp0@9b500000 { 794 reg = <0x0 0x9b500000 0x0 0x1e00000>; 795 no-map; 796 }; 797 798 pil_gpu_mem: pil-gpu@9d300000 { 799 reg = <0x0 0x9d300000 0x0 0x2000>; 800 no-map; 801 }; 802 803 q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 { 804 reg = <0x0 0x9d380000 0x0 0x80000>; 805 no-map; 806 }; 807 808 pil_cdsp1_mem: pil-cdsp1@9d400000 { 809 reg = <0x0 0x9d400000 0x0 0x1e00000>; 810 no-map; 811 }; 812 813 pil_cvp_mem: pil-cvp@9f200000 { 814 reg = <0x0 0x9f200000 0x0 0x700000>; 815 no-map; 816 }; 817 818 pil_video_mem: pil-video@9f900000 { 819 reg = <0x0 0x9f900000 0x0 0x1000000>; 820 no-map; 821 }; 822 823 firmware_mem: firmware-region@b0000000 { 824 reg = <0x0 0xb0000000 0x0 0x800000>; 825 no-map; 826 }; 827 828 scmi_mem: scmi-region@d0000000 { 829 reg = <0x0 0xd0000000 0x0 0x40000>; 830 no-map; 831 }; 832 833 firmware_logs_mem: firmware-logs@d0040000 { 834 reg = <0x0 0xd0040000 0x0 0x10000>; 835 no-map; 836 }; 837 838 firmware_audio_mem: firmware-audio@d0050000 { 839 reg = <0x0 0xd0050000 0x0 0x4000>; 840 no-map; 841 }; 842 843 firmware_reserved_mem: firmware-reserved@d0054000 { 844 reg = <0x0 0xd0054000 0x0 0x9c000>; 845 no-map; 846 }; 847 848 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { 849 reg = <0x0 0xd00f0000 0x0 0x10000>; 850 no-map; 851 }; 852 853 tags_mem: tags@d0100000 { 854 reg = <0x0 0xd0100000 0x0 0x1200000>; 855 no-map; 856 }; 857 858 qtee_mem: qtee@d1300000 { 859 reg = <0x0 0xd1300000 0x0 0x500000>; 860 no-map; 861 }; 862 863 deepsleep_backup_mem: deepsleep-backup@d1800000 { 864 reg = <0x0 0xd1800000 0x0 0x100000>; 865 no-map; 866 }; 867 868 trusted_apps_mem: trusted-apps@d1900000 { 869 reg = <0x0 0xd1900000 0x0 0x1c00000>; 870 no-map; 871 }; 872 873 tz_stat_mem: tz-stat@db100000 { 874 reg = <0x0 0xdb100000 0x0 0x100000>; 875 no-map; 876 }; 877 878 cpucp_fw_mem: cpucp-fw@db200000 { 879 reg = <0x0 0xdb200000 0x0 0x100000>; 880 no-map; 881 }; 882 }; 883 884 smp2p-adsp { 885 compatible = "qcom,smp2p"; 886 qcom,smem = <443>, <429>; 887 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 888 IPCC_MPROC_SIGNAL_SMP2P 889 IRQ_TYPE_EDGE_RISING>; 890 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 891 892 qcom,local-pid = <0>; 893 qcom,remote-pid = <2>; 894 895 smp2p_adsp_out: master-kernel { 896 qcom,entry-name = "master-kernel"; 897 #qcom,smem-state-cells = <1>; 898 }; 899 900 smp2p_adsp_in: slave-kernel { 901 qcom,entry-name = "slave-kernel"; 902 interrupt-controller; 903 #interrupt-cells = <2>; 904 }; 905 }; 906 907 smp2p-cdsp0 { 908 compatible = "qcom,smp2p"; 909 qcom,smem = <94>, <432>; 910 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 911 IPCC_MPROC_SIGNAL_SMP2P 912 IRQ_TYPE_EDGE_RISING>; 913 mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 914 915 qcom,local-pid = <0>; 916 qcom,remote-pid = <5>; 917 918 smp2p_cdsp0_out: master-kernel { 919 qcom,entry-name = "master-kernel"; 920 #qcom,smem-state-cells = <1>; 921 }; 922 923 smp2p_cdsp0_in: slave-kernel { 924 qcom,entry-name = "slave-kernel"; 925 interrupt-controller; 926 #interrupt-cells = <2>; 927 }; 928 }; 929 930 smp2p-cdsp1 { 931 compatible = "qcom,smp2p"; 932 qcom,smem = <617>, <616>; 933 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 934 IPCC_MPROC_SIGNAL_SMP2P 935 IRQ_TYPE_EDGE_RISING>; 936 mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; 937 938 qcom,local-pid = <0>; 939 qcom,remote-pid = <12>; 940 941 smp2p_cdsp1_out: master-kernel { 942 qcom,entry-name = "master-kernel"; 943 #qcom,smem-state-cells = <1>; 944 }; 945 946 smp2p_cdsp1_in: slave-kernel { 947 qcom,entry-name = "slave-kernel"; 948 interrupt-controller; 949 #interrupt-cells = <2>; 950 }; 951 }; 952 953 smp2p-gpdsp0 { 954 compatible = "qcom,smp2p"; 955 qcom,smem = <617>, <616>; 956 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 957 IPCC_MPROC_SIGNAL_SMP2P 958 IRQ_TYPE_EDGE_RISING>; 959 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; 960 961 qcom,local-pid = <0>; 962 qcom,remote-pid = <17>; 963 964 smp2p_gpdsp0_out: master-kernel { 965 qcom,entry-name = "master-kernel"; 966 #qcom,smem-state-cells = <1>; 967 }; 968 969 smp2p_gpdsp0_in: slave-kernel { 970 qcom,entry-name = "slave-kernel"; 971 interrupt-controller; 972 #interrupt-cells = <2>; 973 }; 974 }; 975 976 smp2p-gpdsp1 { 977 compatible = "qcom,smp2p"; 978 qcom,smem = <617>, <616>; 979 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 980 IPCC_MPROC_SIGNAL_SMP2P 981 IRQ_TYPE_EDGE_RISING>; 982 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>; 983 984 qcom,local-pid = <0>; 985 qcom,remote-pid = <18>; 986 987 smp2p_gpdsp1_out: master-kernel { 988 qcom,entry-name = "master-kernel"; 989 #qcom,smem-state-cells = <1>; 990 }; 991 992 smp2p_gpdsp1_in: slave-kernel { 993 qcom,entry-name = "slave-kernel"; 994 interrupt-controller; 995 #interrupt-cells = <2>; 996 }; 997 }; 998 999 soc: soc@0 { 1000 compatible = "simple-bus"; 1001 #address-cells = <2>; 1002 #size-cells = <2>; 1003 ranges = <0 0 0 0 0x10 0>; 1004 1005 gcc: clock-controller@100000 { 1006 compatible = "qcom,sa8775p-gcc"; 1007 reg = <0x0 0x00100000 0x0 0xc7018>; 1008 #clock-cells = <1>; 1009 #reset-cells = <1>; 1010 #power-domain-cells = <1>; 1011 clocks = <&rpmhcc RPMH_CXO_CLK>, 1012 <&sleep_clk>, 1013 <0>, 1014 <0>, 1015 <0>, 1016 <&usb_0_qmpphy>, 1017 <&usb_1_qmpphy>, 1018 <0>, 1019 <0>, 1020 <0>, 1021 <&pcie0_phy>, 1022 <&pcie1_phy>, 1023 <0>, 1024 <0>, 1025 <0>; 1026 power-domains = <&rpmhpd SA8775P_CX>; 1027 }; 1028 1029 ipcc: mailbox@408000 { 1030 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 1031 reg = <0x0 0x00408000 0x0 0x1000>; 1032 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1033 interrupt-controller; 1034 #interrupt-cells = <3>; 1035 #mbox-cells = <2>; 1036 }; 1037 1038 qfprom: efuse@784000 { 1039 compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; 1040 reg = <0x0 0x00784000 0x0 0x3000>; 1041 #address-cells = <1>; 1042 #size-cells = <1>; 1043 1044 gpu_speed_bin: gpu_speed_bin@240c { 1045 reg = <0x240c 0x1>; 1046 bits = <0 8>; 1047 }; 1048 }; 1049 1050 gpi_dma2: dma-controller@800000 { 1051 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1052 reg = <0x0 0x00800000 0x0 0x60000>; 1053 #dma-cells = <3>; 1054 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1066 dma-channels = <12>; 1067 dma-channel-mask = <0xfff>; 1068 iommus = <&apps_smmu 0x5b6 0x0>; 1069 status = "disabled"; 1070 }; 1071 1072 qupv3_id_2: geniqup@8c0000 { 1073 compatible = "qcom,geni-se-qup"; 1074 reg = <0x0 0x008c0000 0x0 0x6000>; 1075 ranges; 1076 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1077 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1078 clock-names = "m-ahb", "s-ahb"; 1079 iommus = <&apps_smmu 0x5a3 0x0>; 1080 #address-cells = <2>; 1081 #size-cells = <2>; 1082 status = "disabled"; 1083 1084 i2c14: i2c@880000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0x0 0x880000 0x0 0x4000>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1091 clock-names = "se"; 1092 pinctrl-0 = <&qup_i2c14_default>; 1093 pinctrl-names = "default"; 1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1095 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1096 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1097 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1098 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1099 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1100 interconnect-names = "qup-core", 1101 "qup-config", 1102 "qup-memory"; 1103 power-domains = <&rpmhpd SA8775P_CX>; 1104 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1105 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1106 dma-names = "tx", 1107 "rx"; 1108 status = "disabled"; 1109 }; 1110 1111 spi14: spi@880000 { 1112 compatible = "qcom,geni-spi"; 1113 reg = <0x0 0x880000 0x0 0x4000>; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1118 clock-names = "se"; 1119 pinctrl-0 = <&qup_spi14_default>; 1120 pinctrl-names = "default"; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1122 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1123 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1124 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1125 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1126 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1127 interconnect-names = "qup-core", 1128 "qup-config", 1129 "qup-memory"; 1130 power-domains = <&rpmhpd SA8775P_CX>; 1131 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1132 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1133 dma-names = "tx", 1134 "rx"; 1135 status = "disabled"; 1136 }; 1137 1138 uart14: serial@880000 { 1139 compatible = "qcom,geni-uart"; 1140 reg = <0x0 0x00880000 0x0 0x4000>; 1141 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1143 clock-names = "se"; 1144 pinctrl-0 = <&qup_uart14_default>; 1145 pinctrl-names = "default"; 1146 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1147 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1148 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1149 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1150 interconnect-names = "qup-core", "qup-config"; 1151 power-domains = <&rpmhpd SA8775P_CX>; 1152 status = "disabled"; 1153 }; 1154 1155 i2c15: i2c@884000 { 1156 compatible = "qcom,geni-i2c"; 1157 reg = <0x0 0x884000 0x0 0x4000>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1162 clock-names = "se"; 1163 pinctrl-0 = <&qup_i2c15_default>; 1164 pinctrl-names = "default"; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1166 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1167 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1168 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1169 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1170 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1171 interconnect-names = "qup-core", 1172 "qup-config", 1173 "qup-memory"; 1174 power-domains = <&rpmhpd SA8775P_CX>; 1175 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1176 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1177 dma-names = "tx", 1178 "rx"; 1179 status = "disabled"; 1180 }; 1181 1182 spi15: spi@884000 { 1183 compatible = "qcom,geni-spi"; 1184 reg = <0x0 0x884000 0x0 0x4000>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1189 clock-names = "se"; 1190 pinctrl-0 = <&qup_spi15_default>; 1191 pinctrl-names = "default"; 1192 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1193 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1194 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1195 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1196 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1197 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1198 interconnect-names = "qup-core", 1199 "qup-config", 1200 "qup-memory"; 1201 power-domains = <&rpmhpd SA8775P_CX>; 1202 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1203 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1204 dma-names = "tx", 1205 "rx"; 1206 status = "disabled"; 1207 }; 1208 1209 uart15: serial@884000 { 1210 compatible = "qcom,geni-uart"; 1211 reg = <0x0 0x00884000 0x0 0x4000>; 1212 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1213 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1214 clock-names = "se"; 1215 pinctrl-0 = <&qup_uart15_default>; 1216 pinctrl-names = "default"; 1217 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1218 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1219 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1220 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1221 interconnect-names = "qup-core", "qup-config"; 1222 power-domains = <&rpmhpd SA8775P_CX>; 1223 status = "disabled"; 1224 }; 1225 1226 i2c16: i2c@888000 { 1227 compatible = "qcom,geni-i2c"; 1228 reg = <0x0 0x888000 0x0 0x4000>; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1233 clock-names = "se"; 1234 pinctrl-0 = <&qup_i2c16_default>; 1235 pinctrl-names = "default"; 1236 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1237 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1238 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1239 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1240 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1241 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1242 interconnect-names = "qup-core", 1243 "qup-config", 1244 "qup-memory"; 1245 power-domains = <&rpmhpd SA8775P_CX>; 1246 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1247 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1248 dma-names = "tx", 1249 "rx"; 1250 status = "disabled"; 1251 }; 1252 1253 spi16: spi@888000 { 1254 compatible = "qcom,geni-spi"; 1255 reg = <0x0 0x00888000 0x0 0x4000>; 1256 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1258 clock-names = "se"; 1259 pinctrl-0 = <&qup_spi16_default>; 1260 pinctrl-names = "default"; 1261 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1262 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1263 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1264 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1265 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1266 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1267 interconnect-names = "qup-core", 1268 "qup-config", 1269 "qup-memory"; 1270 power-domains = <&rpmhpd SA8775P_CX>; 1271 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1272 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1273 dma-names = "tx", 1274 "rx"; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 status = "disabled"; 1278 }; 1279 1280 uart16: serial@888000 { 1281 compatible = "qcom,geni-uart"; 1282 reg = <0x0 0x00888000 0x0 0x4000>; 1283 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1284 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1285 clock-names = "se"; 1286 pinctrl-0 = <&qup_uart16_default>; 1287 pinctrl-names = "default"; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1289 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1290 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1291 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1292 interconnect-names = "qup-core", "qup-config"; 1293 power-domains = <&rpmhpd SA8775P_CX>; 1294 status = "disabled"; 1295 }; 1296 1297 i2c17: i2c@88c000 { 1298 compatible = "qcom,geni-i2c"; 1299 reg = <0x0 0x88c000 0x0 0x4000>; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1304 clock-names = "se"; 1305 pinctrl-0 = <&qup_i2c17_default>; 1306 pinctrl-names = "default"; 1307 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1308 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1309 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1310 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1311 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1313 interconnect-names = "qup-core", 1314 "qup-config", 1315 "qup-memory"; 1316 power-domains = <&rpmhpd SA8775P_CX>; 1317 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1318 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1319 dma-names = "tx", 1320 "rx"; 1321 status = "disabled"; 1322 }; 1323 1324 spi17: spi@88c000 { 1325 compatible = "qcom,geni-spi"; 1326 reg = <0x0 0x88c000 0x0 0x4000>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1330 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1331 clock-names = "se"; 1332 pinctrl-0 = <&qup_spi17_default>; 1333 pinctrl-names = "default"; 1334 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1335 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1336 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1337 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1338 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1339 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1340 interconnect-names = "qup-core", 1341 "qup-config", 1342 "qup-memory"; 1343 power-domains = <&rpmhpd SA8775P_CX>; 1344 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1345 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1346 dma-names = "tx", 1347 "rx"; 1348 status = "disabled"; 1349 }; 1350 1351 uart17: serial@88c000 { 1352 compatible = "qcom,geni-uart"; 1353 reg = <0x0 0x0088c000 0x0 0x4000>; 1354 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1355 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1356 clock-names = "se"; 1357 pinctrl-0 = <&qup_uart17_default>; 1358 pinctrl-names = "default"; 1359 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1360 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1361 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1362 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1363 interconnect-names = "qup-core", "qup-config"; 1364 power-domains = <&rpmhpd SA8775P_CX>; 1365 status = "disabled"; 1366 }; 1367 1368 i2c18: i2c@890000 { 1369 compatible = "qcom,geni-i2c"; 1370 reg = <0x0 0x00890000 0x0 0x4000>; 1371 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1372 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1373 clock-names = "se"; 1374 pinctrl-0 = <&qup_i2c18_default>; 1375 pinctrl-names = "default"; 1376 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1377 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1378 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1379 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1380 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1381 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1382 interconnect-names = "qup-core", 1383 "qup-config", 1384 "qup-memory"; 1385 power-domains = <&rpmhpd SA8775P_CX>; 1386 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1387 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1388 dma-names = "tx", 1389 "rx"; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 status = "disabled"; 1393 }; 1394 1395 spi18: spi@890000 { 1396 compatible = "qcom,geni-spi"; 1397 reg = <0x0 0x890000 0x0 0x4000>; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1401 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1402 clock-names = "se"; 1403 pinctrl-0 = <&qup_spi18_default>; 1404 pinctrl-names = "default"; 1405 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1406 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1407 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1408 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1409 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1410 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1411 interconnect-names = "qup-core", 1412 "qup-config", 1413 "qup-memory"; 1414 power-domains = <&rpmhpd SA8775P_CX>; 1415 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1416 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1417 dma-names = "tx", 1418 "rx"; 1419 status = "disabled"; 1420 }; 1421 1422 uart18: serial@890000 { 1423 compatible = "qcom,geni-uart"; 1424 reg = <0x0 0x00890000 0x0 0x4000>; 1425 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1426 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1427 clock-names = "se"; 1428 pinctrl-0 = <&qup_uart18_default>; 1429 pinctrl-names = "default"; 1430 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1431 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1432 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1433 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1434 interconnect-names = "qup-core", "qup-config"; 1435 power-domains = <&rpmhpd SA8775P_CX>; 1436 status = "disabled"; 1437 }; 1438 1439 i2c19: i2c@894000 { 1440 compatible = "qcom,geni-i2c"; 1441 reg = <0x0 0x894000 0x0 0x4000>; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1445 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1446 clock-names = "se"; 1447 pinctrl-0 = <&qup_i2c19_default>; 1448 pinctrl-names = "default"; 1449 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1450 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1451 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1452 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1453 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1454 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1455 interconnect-names = "qup-core", 1456 "qup-config", 1457 "qup-memory"; 1458 power-domains = <&rpmhpd SA8775P_CX>; 1459 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1460 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1461 dma-names = "tx", 1462 "rx"; 1463 status = "disabled"; 1464 }; 1465 1466 spi19: spi@894000 { 1467 compatible = "qcom,geni-spi"; 1468 reg = <0x0 0x894000 0x0 0x4000>; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1472 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1473 clock-names = "se"; 1474 pinctrl-0 = <&qup_spi19_default>; 1475 pinctrl-names = "default"; 1476 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1477 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1478 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1479 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1480 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1481 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1482 interconnect-names = "qup-core", 1483 "qup-config", 1484 "qup-memory"; 1485 power-domains = <&rpmhpd SA8775P_CX>; 1486 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1487 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1488 dma-names = "tx", 1489 "rx"; 1490 status = "disabled"; 1491 }; 1492 1493 uart19: serial@894000 { 1494 compatible = "qcom,geni-uart"; 1495 reg = <0x0 0x00894000 0x0 0x4000>; 1496 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1497 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1498 clock-names = "se"; 1499 pinctrl-0 = <&qup_uart19_default>; 1500 pinctrl-names = "default"; 1501 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1502 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1503 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1504 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1505 interconnect-names = "qup-core", "qup-config"; 1506 power-domains = <&rpmhpd SA8775P_CX>; 1507 status = "disabled"; 1508 }; 1509 1510 i2c20: i2c@898000 { 1511 compatible = "qcom,geni-i2c"; 1512 reg = <0x0 0x898000 0x0 0x4000>; 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1516 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1517 clock-names = "se"; 1518 pinctrl-0 = <&qup_i2c20_default>; 1519 pinctrl-names = "default"; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1521 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1522 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1523 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1524 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1525 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1526 interconnect-names = "qup-core", 1527 "qup-config", 1528 "qup-memory"; 1529 power-domains = <&rpmhpd SA8775P_CX>; 1530 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1531 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1532 dma-names = "tx", 1533 "rx"; 1534 status = "disabled"; 1535 }; 1536 1537 spi20: spi@898000 { 1538 compatible = "qcom,geni-spi"; 1539 reg = <0x0 0x898000 0x0 0x4000>; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1543 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1544 clock-names = "se"; 1545 pinctrl-0 = <&qup_spi20_default>; 1546 pinctrl-names = "default"; 1547 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1548 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1549 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1550 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1551 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1552 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1553 interconnect-names = "qup-core", 1554 "qup-config", 1555 "qup-memory"; 1556 power-domains = <&rpmhpd SA8775P_CX>; 1557 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1558 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1559 dma-names = "tx", 1560 "rx"; 1561 status = "disabled"; 1562 }; 1563 1564 uart20: serial@898000 { 1565 compatible = "qcom,geni-uart"; 1566 reg = <0x0 0x00898000 0x0 0x4000>; 1567 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1568 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1569 clock-names = "se"; 1570 pinctrl-0 = <&qup_uart20_default>; 1571 pinctrl-names = "default"; 1572 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1573 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1574 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1575 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1576 interconnect-names = "qup-core", "qup-config"; 1577 power-domains = <&rpmhpd SA8775P_CX>; 1578 status = "disabled"; 1579 }; 1580 1581 }; 1582 1583 gpi_dma0: dma-controller@900000 { 1584 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1585 reg = <0x0 0x00900000 0x0 0x60000>; 1586 #dma-cells = <3>; 1587 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1599 dma-channels = <12>; 1600 dma-channel-mask = <0xfff>; 1601 iommus = <&apps_smmu 0x416 0x0>; 1602 status = "disabled"; 1603 }; 1604 1605 qupv3_id_0: geniqup@9c0000 { 1606 compatible = "qcom,geni-se-qup"; 1607 reg = <0x0 0x9c0000 0x0 0x6000>; 1608 #address-cells = <2>; 1609 #size-cells = <2>; 1610 ranges; 1611 clock-names = "m-ahb", "s-ahb"; 1612 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1613 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1614 iommus = <&apps_smmu 0x403 0x0>; 1615 status = "disabled"; 1616 1617 i2c0: i2c@980000 { 1618 compatible = "qcom,geni-i2c"; 1619 reg = <0x0 0x980000 0x0 0x4000>; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1624 clock-names = "se"; 1625 pinctrl-0 = <&qup_i2c0_default>; 1626 pinctrl-names = "default"; 1627 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1628 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1629 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1630 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1631 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1632 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1633 interconnect-names = "qup-core", 1634 "qup-config", 1635 "qup-memory"; 1636 power-domains = <&rpmhpd SA8775P_CX>; 1637 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1638 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1639 dma-names = "tx", 1640 "rx"; 1641 status = "disabled"; 1642 }; 1643 1644 spi0: spi@980000 { 1645 compatible = "qcom,geni-spi"; 1646 reg = <0x0 0x980000 0x0 0x4000>; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1650 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1651 clock-names = "se"; 1652 pinctrl-0 = <&qup_spi0_default>; 1653 pinctrl-names = "default"; 1654 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1655 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1656 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1657 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1658 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1659 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1660 interconnect-names = "qup-core", 1661 "qup-config", 1662 "qup-memory"; 1663 power-domains = <&rpmhpd SA8775P_CX>; 1664 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1665 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1666 dma-names = "tx", 1667 "rx"; 1668 status = "disabled"; 1669 }; 1670 1671 uart0: serial@980000 { 1672 compatible = "qcom,geni-uart"; 1673 reg = <0x0 0x980000 0x0 0x4000>; 1674 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1675 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1676 clock-names = "se"; 1677 pinctrl-0 = <&qup_uart0_default>; 1678 pinctrl-names = "default"; 1679 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1680 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1681 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1682 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1683 interconnect-names = "qup-core", "qup-config"; 1684 power-domains = <&rpmhpd SA8775P_CX>; 1685 status = "disabled"; 1686 }; 1687 1688 i2c1: i2c@984000 { 1689 compatible = "qcom,geni-i2c"; 1690 reg = <0x0 0x984000 0x0 0x4000>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1694 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1695 clock-names = "se"; 1696 pinctrl-0 = <&qup_i2c1_default>; 1697 pinctrl-names = "default"; 1698 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1699 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1700 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1701 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1702 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1703 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1704 interconnect-names = "qup-core", 1705 "qup-config", 1706 "qup-memory"; 1707 power-domains = <&rpmhpd SA8775P_CX>; 1708 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1709 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1710 dma-names = "tx", 1711 "rx"; 1712 status = "disabled"; 1713 }; 1714 1715 spi1: spi@984000 { 1716 compatible = "qcom,geni-spi"; 1717 reg = <0x0 0x984000 0x0 0x4000>; 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1721 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1722 clock-names = "se"; 1723 pinctrl-0 = <&qup_spi1_default>; 1724 pinctrl-names = "default"; 1725 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1726 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1727 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1728 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1729 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1730 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1731 interconnect-names = "qup-core", 1732 "qup-config", 1733 "qup-memory"; 1734 power-domains = <&rpmhpd SA8775P_CX>; 1735 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1736 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1737 dma-names = "tx", 1738 "rx"; 1739 status = "disabled"; 1740 }; 1741 1742 uart1: serial@984000 { 1743 compatible = "qcom,geni-uart"; 1744 reg = <0x0 0x984000 0x0 0x4000>; 1745 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1746 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1747 clock-names = "se"; 1748 pinctrl-0 = <&qup_uart1_default>; 1749 pinctrl-names = "default"; 1750 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1751 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1752 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1753 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1754 interconnect-names = "qup-core", "qup-config"; 1755 power-domains = <&rpmhpd SA8775P_CX>; 1756 status = "disabled"; 1757 }; 1758 1759 i2c2: i2c@988000 { 1760 compatible = "qcom,geni-i2c"; 1761 reg = <0x0 0x988000 0x0 0x4000>; 1762 #address-cells = <1>; 1763 #size-cells = <0>; 1764 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1765 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1766 clock-names = "se"; 1767 pinctrl-0 = <&qup_i2c2_default>; 1768 pinctrl-names = "default"; 1769 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1770 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1771 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1772 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1773 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1774 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1775 interconnect-names = "qup-core", 1776 "qup-config", 1777 "qup-memory"; 1778 power-domains = <&rpmhpd SA8775P_CX>; 1779 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1780 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1781 dma-names = "tx", 1782 "rx"; 1783 status = "disabled"; 1784 }; 1785 1786 spi2: spi@988000 { 1787 compatible = "qcom,geni-spi"; 1788 reg = <0x0 0x988000 0x0 0x4000>; 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1792 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1793 clock-names = "se"; 1794 pinctrl-0 = <&qup_spi2_default>; 1795 pinctrl-names = "default"; 1796 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1797 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1798 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1799 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1800 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1801 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1802 interconnect-names = "qup-core", 1803 "qup-config", 1804 "qup-memory"; 1805 power-domains = <&rpmhpd SA8775P_CX>; 1806 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1807 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1808 dma-names = "tx", 1809 "rx"; 1810 status = "disabled"; 1811 }; 1812 1813 uart2: serial@988000 { 1814 compatible = "qcom,geni-uart"; 1815 reg = <0x0 0x988000 0x0 0x4000>; 1816 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1817 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1818 clock-names = "se"; 1819 pinctrl-0 = <&qup_uart2_default>; 1820 pinctrl-names = "default"; 1821 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1822 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1823 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1824 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1825 interconnect-names = "qup-core", "qup-config"; 1826 power-domains = <&rpmhpd SA8775P_CX>; 1827 status = "disabled"; 1828 }; 1829 1830 i2c3: i2c@98c000 { 1831 compatible = "qcom,geni-i2c"; 1832 reg = <0x0 0x98c000 0x0 0x4000>; 1833 #address-cells = <1>; 1834 #size-cells = <0>; 1835 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1836 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1837 clock-names = "se"; 1838 pinctrl-0 = <&qup_i2c3_default>; 1839 pinctrl-names = "default"; 1840 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1841 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1842 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1843 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1844 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1845 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1846 interconnect-names = "qup-core", 1847 "qup-config", 1848 "qup-memory"; 1849 power-domains = <&rpmhpd SA8775P_CX>; 1850 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1851 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1852 dma-names = "tx", 1853 "rx"; 1854 status = "disabled"; 1855 }; 1856 1857 spi3: spi@98c000 { 1858 compatible = "qcom,geni-spi"; 1859 reg = <0x0 0x98c000 0x0 0x4000>; 1860 #address-cells = <1>; 1861 #size-cells = <0>; 1862 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1863 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1864 clock-names = "se"; 1865 pinctrl-0 = <&qup_spi3_default>; 1866 pinctrl-names = "default"; 1867 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1868 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1869 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1870 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1871 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1872 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1873 interconnect-names = "qup-core", 1874 "qup-config", 1875 "qup-memory"; 1876 power-domains = <&rpmhpd SA8775P_CX>; 1877 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1878 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1879 dma-names = "tx", 1880 "rx"; 1881 status = "disabled"; 1882 }; 1883 1884 uart3: serial@98c000 { 1885 compatible = "qcom,geni-uart"; 1886 reg = <0x0 0x98c000 0x0 0x4000>; 1887 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1888 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1889 clock-names = "se"; 1890 pinctrl-0 = <&qup_uart3_default>; 1891 pinctrl-names = "default"; 1892 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1893 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1894 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1895 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1896 interconnect-names = "qup-core", "qup-config"; 1897 power-domains = <&rpmhpd SA8775P_CX>; 1898 status = "disabled"; 1899 }; 1900 1901 i2c4: i2c@990000 { 1902 compatible = "qcom,geni-i2c"; 1903 reg = <0x0 0x990000 0x0 0x4000>; 1904 #address-cells = <1>; 1905 #size-cells = <0>; 1906 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1907 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1908 clock-names = "se"; 1909 pinctrl-0 = <&qup_i2c4_default>; 1910 pinctrl-names = "default"; 1911 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1912 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1913 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1914 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1915 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1916 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1917 interconnect-names = "qup-core", 1918 "qup-config", 1919 "qup-memory"; 1920 power-domains = <&rpmhpd SA8775P_CX>; 1921 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1922 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1923 dma-names = "tx", 1924 "rx"; 1925 status = "disabled"; 1926 }; 1927 1928 spi4: spi@990000 { 1929 compatible = "qcom,geni-spi"; 1930 reg = <0x0 0x990000 0x0 0x4000>; 1931 #address-cells = <1>; 1932 #size-cells = <0>; 1933 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1934 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1935 clock-names = "se"; 1936 pinctrl-0 = <&qup_spi4_default>; 1937 pinctrl-names = "default"; 1938 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1939 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1940 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1941 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1942 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1943 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1944 interconnect-names = "qup-core", 1945 "qup-config", 1946 "qup-memory"; 1947 power-domains = <&rpmhpd SA8775P_CX>; 1948 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1949 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1950 dma-names = "tx", 1951 "rx"; 1952 status = "disabled"; 1953 }; 1954 1955 uart4: serial@990000 { 1956 compatible = "qcom,geni-uart"; 1957 reg = <0x0 0x990000 0x0 0x4000>; 1958 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1959 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1960 clock-names = "se"; 1961 pinctrl-0 = <&qup_uart4_default>; 1962 pinctrl-names = "default"; 1963 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1964 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1965 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1966 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1967 interconnect-names = "qup-core", "qup-config"; 1968 power-domains = <&rpmhpd SA8775P_CX>; 1969 status = "disabled"; 1970 }; 1971 1972 i2c5: i2c@994000 { 1973 compatible = "qcom,geni-i2c"; 1974 reg = <0x0 0x994000 0x0 0x4000>; 1975 #address-cells = <1>; 1976 #size-cells = <0>; 1977 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1978 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1979 clock-names = "se"; 1980 pinctrl-0 = <&qup_i2c5_default>; 1981 pinctrl-names = "default"; 1982 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1983 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1984 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1985 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1986 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1987 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1988 interconnect-names = "qup-core", 1989 "qup-config", 1990 "qup-memory"; 1991 power-domains = <&rpmhpd SA8775P_CX>; 1992 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1993 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1994 dma-names = "tx", 1995 "rx"; 1996 status = "disabled"; 1997 }; 1998 1999 spi5: spi@994000 { 2000 compatible = "qcom,geni-spi"; 2001 reg = <0x0 0x994000 0x0 0x4000>; 2002 #address-cells = <1>; 2003 #size-cells = <0>; 2004 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2005 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2006 clock-names = "se"; 2007 pinctrl-0 = <&qup_spi5_default>; 2008 pinctrl-names = "default"; 2009 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2010 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2011 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2012 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2013 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2014 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2015 interconnect-names = "qup-core", 2016 "qup-config", 2017 "qup-memory"; 2018 power-domains = <&rpmhpd SA8775P_CX>; 2019 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2020 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2021 dma-names = "tx", 2022 "rx"; 2023 status = "disabled"; 2024 }; 2025 2026 uart5: serial@994000 { 2027 compatible = "qcom,geni-uart"; 2028 reg = <0x0 0x994000 0x0 0x4000>; 2029 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2030 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2031 clock-names = "se"; 2032 pinctrl-0 = <&qup_uart5_default>; 2033 pinctrl-names = "default"; 2034 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2035 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2036 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2037 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2038 interconnect-names = "qup-core", "qup-config"; 2039 power-domains = <&rpmhpd SA8775P_CX>; 2040 status = "disabled"; 2041 }; 2042 }; 2043 2044 gpi_dma1: dma-controller@a00000 { 2045 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2046 reg = <0x0 0x00a00000 0x0 0x60000>; 2047 #dma-cells = <3>; 2048 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2060 iommus = <&apps_smmu 0x456 0x0>; 2061 dma-channels = <12>; 2062 dma-channel-mask = <0xfff>; 2063 status = "disabled"; 2064 }; 2065 2066 qupv3_id_1: geniqup@ac0000 { 2067 compatible = "qcom,geni-se-qup"; 2068 reg = <0x0 0x00ac0000 0x0 0x6000>; 2069 #address-cells = <2>; 2070 #size-cells = <2>; 2071 ranges; 2072 clock-names = "m-ahb", "s-ahb"; 2073 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 2074 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 2075 iommus = <&apps_smmu 0x443 0x0>; 2076 status = "disabled"; 2077 2078 i2c7: i2c@a80000 { 2079 compatible = "qcom,geni-i2c"; 2080 reg = <0x0 0xa80000 0x0 0x4000>; 2081 #address-cells = <1>; 2082 #size-cells = <0>; 2083 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2084 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2085 clock-names = "se"; 2086 pinctrl-0 = <&qup_i2c7_default>; 2087 pinctrl-names = "default"; 2088 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2089 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2090 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2091 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2092 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2093 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2094 interconnect-names = "qup-core", 2095 "qup-config", 2096 "qup-memory"; 2097 power-domains = <&rpmhpd SA8775P_CX>; 2098 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 2099 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 2100 dma-names = "tx", 2101 "rx"; 2102 status = "disabled"; 2103 }; 2104 2105 spi7: spi@a80000 { 2106 compatible = "qcom,geni-spi"; 2107 reg = <0x0 0xa80000 0x0 0x4000>; 2108 #address-cells = <1>; 2109 #size-cells = <0>; 2110 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2111 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2112 clock-names = "se"; 2113 pinctrl-0 = <&qup_spi7_default>; 2114 pinctrl-names = "default"; 2115 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2116 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2117 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2118 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2119 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2120 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2121 interconnect-names = "qup-core", 2122 "qup-config", 2123 "qup-memory"; 2124 power-domains = <&rpmhpd SA8775P_CX>; 2125 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 2126 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 2127 dma-names = "tx", 2128 "rx"; 2129 status = "disabled"; 2130 }; 2131 2132 uart7: serial@a80000 { 2133 compatible = "qcom,geni-uart"; 2134 reg = <0x0 0x00a80000 0x0 0x4000>; 2135 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2136 clock-names = "se"; 2137 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2138 pinctrl-0 = <&qup_uart7_default>; 2139 pinctrl-names = "default"; 2140 interconnect-names = "qup-core", "qup-config"; 2141 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2142 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2143 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2144 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2145 power-domains = <&rpmhpd SA8775P_CX>; 2146 operating-points-v2 = <&qup_opp_table_100mhz>; 2147 status = "disabled"; 2148 }; 2149 2150 i2c8: i2c@a84000 { 2151 compatible = "qcom,geni-i2c"; 2152 reg = <0x0 0xa84000 0x0 0x4000>; 2153 #address-cells = <1>; 2154 #size-cells = <0>; 2155 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2156 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2157 clock-names = "se"; 2158 pinctrl-0 = <&qup_i2c8_default>; 2159 pinctrl-names = "default"; 2160 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2161 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2162 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2163 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2164 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2165 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2166 interconnect-names = "qup-core", 2167 "qup-config", 2168 "qup-memory"; 2169 power-domains = <&rpmhpd SA8775P_CX>; 2170 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 2171 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 2172 dma-names = "tx", 2173 "rx"; 2174 status = "disabled"; 2175 }; 2176 2177 spi8: spi@a84000 { 2178 compatible = "qcom,geni-spi"; 2179 reg = <0x0 0xa84000 0x0 0x4000>; 2180 #address-cells = <1>; 2181 #size-cells = <0>; 2182 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2183 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2184 clock-names = "se"; 2185 pinctrl-0 = <&qup_spi8_default>; 2186 pinctrl-names = "default"; 2187 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2188 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2189 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2190 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2191 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2193 interconnect-names = "qup-core", 2194 "qup-config", 2195 "qup-memory"; 2196 power-domains = <&rpmhpd SA8775P_CX>; 2197 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 2198 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 2199 dma-names = "tx", 2200 "rx"; 2201 status = "disabled"; 2202 }; 2203 2204 uart8: serial@a84000 { 2205 compatible = "qcom,geni-uart"; 2206 reg = <0x0 0x00a84000 0x0 0x4000>; 2207 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2208 clock-names = "se"; 2209 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2210 pinctrl-0 = <&qup_uart8_default>; 2211 pinctrl-names = "default"; 2212 interconnect-names = "qup-core", "qup-config"; 2213 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2214 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2215 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2216 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2217 power-domains = <&rpmhpd SA8775P_CX>; 2218 operating-points-v2 = <&qup_opp_table_100mhz>; 2219 status = "disabled"; 2220 }; 2221 2222 i2c9: i2c@a88000 { 2223 compatible = "qcom,geni-i2c"; 2224 reg = <0x0 0xa88000 0x0 0x4000>; 2225 #address-cells = <1>; 2226 #size-cells = <0>; 2227 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2228 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2229 clock-names = "se"; 2230 pinctrl-0 = <&qup_i2c9_default>; 2231 pinctrl-names = "default"; 2232 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2233 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2234 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2235 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2236 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2237 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2238 interconnect-names = "qup-core", 2239 "qup-config", 2240 "qup-memory"; 2241 power-domains = <&rpmhpd SA8775P_CX>; 2242 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 2243 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 2244 dma-names = "tx", 2245 "rx"; 2246 status = "disabled"; 2247 }; 2248 2249 spi9: spi@a88000 { 2250 compatible = "qcom,geni-spi"; 2251 reg = <0x0 0xa88000 0x0 0x4000>; 2252 #address-cells = <1>; 2253 #size-cells = <0>; 2254 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2255 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2256 clock-names = "se"; 2257 pinctrl-0 = <&qup_spi9_default>; 2258 pinctrl-names = "default"; 2259 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2260 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2261 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2262 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2263 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2264 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2265 interconnect-names = "qup-core", 2266 "qup-config", 2267 "qup-memory"; 2268 power-domains = <&rpmhpd SA8775P_CX>; 2269 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 2270 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 2271 dma-names = "tx", 2272 "rx"; 2273 status = "disabled"; 2274 }; 2275 2276 uart9: serial@a88000 { 2277 compatible = "qcom,geni-uart"; 2278 reg = <0x0 0xa88000 0x0 0x4000>; 2279 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2280 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2281 clock-names = "se"; 2282 pinctrl-0 = <&qup_uart9_default>; 2283 pinctrl-names = "default"; 2284 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2285 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2286 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2287 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2288 interconnect-names = "qup-core", "qup-config"; 2289 power-domains = <&rpmhpd SA8775P_CX>; 2290 status = "disabled"; 2291 }; 2292 2293 i2c10: i2c@a8c000 { 2294 compatible = "qcom,geni-i2c"; 2295 reg = <0x0 0xa8c000 0x0 0x4000>; 2296 #address-cells = <1>; 2297 #size-cells = <0>; 2298 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2299 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2300 clock-names = "se"; 2301 pinctrl-0 = <&qup_i2c10_default>; 2302 pinctrl-names = "default"; 2303 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2304 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2305 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2306 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2307 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2308 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2309 interconnect-names = "qup-core", 2310 "qup-config", 2311 "qup-memory"; 2312 power-domains = <&rpmhpd SA8775P_CX>; 2313 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 2314 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 2315 dma-names = "tx", 2316 "rx"; 2317 status = "disabled"; 2318 }; 2319 2320 spi10: spi@a8c000 { 2321 compatible = "qcom,geni-spi"; 2322 reg = <0x0 0xa8c000 0x0 0x4000>; 2323 #address-cells = <1>; 2324 #size-cells = <0>; 2325 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2326 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2327 clock-names = "se"; 2328 pinctrl-0 = <&qup_spi10_default>; 2329 pinctrl-names = "default"; 2330 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2331 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2332 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2333 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2334 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2335 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2336 interconnect-names = "qup-core", 2337 "qup-config", 2338 "qup-memory"; 2339 power-domains = <&rpmhpd SA8775P_CX>; 2340 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 2341 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 2342 dma-names = "tx", 2343 "rx"; 2344 status = "disabled"; 2345 }; 2346 2347 uart10: serial@a8c000 { 2348 compatible = "qcom,geni-uart"; 2349 reg = <0x0 0x00a8c000 0x0 0x4000>; 2350 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2351 clock-names = "se"; 2352 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2353 pinctrl-0 = <&qup_uart10_default>; 2354 pinctrl-names = "default"; 2355 interconnect-names = "qup-core", "qup-config"; 2356 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 2357 &clk_virt SLAVE_QUP_CORE_1 0>, 2358 <&gem_noc MASTER_APPSS_PROC 0 2359 &config_noc SLAVE_QUP_1 0>; 2360 power-domains = <&rpmhpd SA8775P_CX>; 2361 operating-points-v2 = <&qup_opp_table_100mhz>; 2362 status = "disabled"; 2363 }; 2364 2365 i2c11: i2c@a90000 { 2366 compatible = "qcom,geni-i2c"; 2367 reg = <0x0 0xa90000 0x0 0x4000>; 2368 #address-cells = <1>; 2369 #size-cells = <0>; 2370 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2371 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2372 clock-names = "se"; 2373 pinctrl-0 = <&qup_i2c11_default>; 2374 pinctrl-names = "default"; 2375 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2376 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2377 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2378 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2379 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2380 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2381 interconnect-names = "qup-core", 2382 "qup-config", 2383 "qup-memory"; 2384 power-domains = <&rpmhpd SA8775P_CX>; 2385 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2386 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2387 dma-names = "tx", 2388 "rx"; 2389 status = "disabled"; 2390 }; 2391 2392 spi11: spi@a90000 { 2393 compatible = "qcom,geni-spi"; 2394 reg = <0x0 0xa90000 0x0 0x4000>; 2395 #address-cells = <1>; 2396 #size-cells = <0>; 2397 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2398 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2399 clock-names = "se"; 2400 pinctrl-0 = <&qup_spi11_default>; 2401 pinctrl-names = "default"; 2402 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2403 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2404 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2405 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2406 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2407 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2408 interconnect-names = "qup-core", 2409 "qup-config", 2410 "qup-memory"; 2411 power-domains = <&rpmhpd SA8775P_CX>; 2412 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2413 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2414 dma-names = "tx", 2415 "rx"; 2416 status = "disabled"; 2417 }; 2418 2419 uart11: serial@a90000 { 2420 compatible = "qcom,geni-uart"; 2421 reg = <0x0 0x00a90000 0x0 0x4000>; 2422 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2423 clock-names = "se"; 2424 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2425 pinctrl-0 = <&qup_uart11_default>; 2426 pinctrl-names = "default"; 2427 interconnect-names = "qup-core", "qup-config"; 2428 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2429 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2430 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2431 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2432 power-domains = <&rpmhpd SA8775P_CX>; 2433 operating-points-v2 = <&qup_opp_table_100mhz>; 2434 status = "disabled"; 2435 }; 2436 2437 i2c12: i2c@a94000 { 2438 compatible = "qcom,geni-i2c"; 2439 reg = <0x0 0xa94000 0x0 0x4000>; 2440 #address-cells = <1>; 2441 #size-cells = <0>; 2442 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2443 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2444 clock-names = "se"; 2445 pinctrl-0 = <&qup_i2c12_default>; 2446 pinctrl-names = "default"; 2447 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2448 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2449 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2450 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2451 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2452 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2453 interconnect-names = "qup-core", 2454 "qup-config", 2455 "qup-memory"; 2456 power-domains = <&rpmhpd SA8775P_CX>; 2457 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2458 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2459 dma-names = "tx", 2460 "rx"; 2461 status = "disabled"; 2462 }; 2463 2464 spi12: spi@a94000 { 2465 compatible = "qcom,geni-spi"; 2466 reg = <0x0 0xa94000 0x0 0x4000>; 2467 #address-cells = <1>; 2468 #size-cells = <0>; 2469 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2470 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2471 clock-names = "se"; 2472 pinctrl-0 = <&qup_spi12_default>; 2473 pinctrl-names = "default"; 2474 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2475 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2476 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2477 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2478 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2479 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2480 interconnect-names = "qup-core", 2481 "qup-config", 2482 "qup-memory"; 2483 power-domains = <&rpmhpd SA8775P_CX>; 2484 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2485 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2486 dma-names = "tx", 2487 "rx"; 2488 status = "disabled"; 2489 }; 2490 2491 uart12: serial@a94000 { 2492 compatible = "qcom,geni-uart"; 2493 reg = <0x0 0x00a94000 0x0 0x4000>; 2494 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2495 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2496 clock-names = "se"; 2497 pinctrl-0 = <&qup_uart12_default>; 2498 pinctrl-names = "default"; 2499 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2500 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2501 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2502 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2503 interconnect-names = "qup-core", "qup-config"; 2504 power-domains = <&rpmhpd SA8775P_CX>; 2505 status = "disabled"; 2506 }; 2507 2508 i2c13: i2c@a98000 { 2509 compatible = "qcom,geni-i2c"; 2510 reg = <0x0 0xa98000 0x0 0x4000>; 2511 #address-cells = <1>; 2512 #size-cells = <0>; 2513 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2514 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2515 clock-names = "se"; 2516 pinctrl-0 = <&qup_i2c13_default>; 2517 pinctrl-names = "default"; 2518 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2519 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2520 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2521 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2522 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2523 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2524 interconnect-names = "qup-core", 2525 "qup-config", 2526 "qup-memory"; 2527 power-domains = <&rpmhpd SA8775P_CX>; 2528 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2529 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2530 dma-names = "tx", 2531 "rx"; 2532 status = "disabled"; 2533 2534 }; 2535 }; 2536 2537 gpi_dma3: dma-controller@b00000 { 2538 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2539 reg = <0x0 0x00b00000 0x0 0x58000>; 2540 #dma-cells = <3>; 2541 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2542 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2543 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2544 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2545 iommus = <&apps_smmu 0x056 0x0>; 2546 dma-channels = <4>; 2547 dma-channel-mask = <0xf>; 2548 status = "disabled"; 2549 }; 2550 2551 qupv3_id_3: geniqup@bc0000 { 2552 compatible = "qcom,geni-se-qup"; 2553 reg = <0x0 0xbc0000 0x0 0x6000>; 2554 #address-cells = <2>; 2555 #size-cells = <2>; 2556 ranges; 2557 clock-names = "m-ahb", "s-ahb"; 2558 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2559 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2560 iommus = <&apps_smmu 0x43 0x0>; 2561 status = "disabled"; 2562 2563 i2c21: i2c@b80000 { 2564 compatible = "qcom,geni-i2c"; 2565 reg = <0x0 0xb80000 0x0 0x4000>; 2566 #address-cells = <1>; 2567 #size-cells = <0>; 2568 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2569 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2570 clock-names = "se"; 2571 pinctrl-0 = <&qup_i2c21_default>; 2572 pinctrl-names = "default"; 2573 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2574 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2575 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2576 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2577 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2578 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2579 interconnect-names = "qup-core", 2580 "qup-config", 2581 "qup-memory"; 2582 power-domains = <&rpmhpd SA8775P_CX>; 2583 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2584 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2585 dma-names = "tx", 2586 "rx"; 2587 status = "disabled"; 2588 }; 2589 2590 spi21: spi@b80000 { 2591 compatible = "qcom,geni-spi"; 2592 reg = <0x0 0xb80000 0x0 0x4000>; 2593 #address-cells = <1>; 2594 #size-cells = <0>; 2595 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2596 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2597 clock-names = "se"; 2598 pinctrl-0 = <&qup_spi21_default>; 2599 pinctrl-names = "default"; 2600 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2601 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2602 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2603 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2604 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2605 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2606 interconnect-names = "qup-core", 2607 "qup-config", 2608 "qup-memory"; 2609 power-domains = <&rpmhpd SA8775P_CX>; 2610 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2611 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2612 dma-names = "tx", 2613 "rx"; 2614 status = "disabled"; 2615 }; 2616 2617 uart21: serial@b80000 { 2618 compatible = "qcom,geni-uart"; 2619 reg = <0x0 0x00b80000 0x0 0x4000>; 2620 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2621 clock-names = "se"; 2622 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2623 interconnect-names = "qup-core", "qup-config"; 2624 pinctrl-0 = <&qup_uart21_default>; 2625 pinctrl-names = "default"; 2626 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2627 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2628 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2629 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2630 power-domains = <&rpmhpd SA8775P_CX>; 2631 operating-points-v2 = <&qup_opp_table_100mhz>; 2632 status = "disabled"; 2633 }; 2634 }; 2635 2636 rng: rng@10d2000 { 2637 compatible = "qcom,sa8775p-trng", "qcom,trng"; 2638 reg = <0 0x010d2000 0 0x1000>; 2639 }; 2640 2641 config_noc: interconnect@14c0000 { 2642 compatible = "qcom,sa8775p-config-noc"; 2643 reg = <0x0 0x014c0000 0x0 0x13080>; 2644 #interconnect-cells = <2>; 2645 qcom,bcm-voters = <&apps_bcm_voter>; 2646 }; 2647 2648 system_noc: interconnect@1680000 { 2649 compatible = "qcom,sa8775p-system-noc"; 2650 reg = <0x0 0x01680000 0x0 0x15080>; 2651 #interconnect-cells = <2>; 2652 qcom,bcm-voters = <&apps_bcm_voter>; 2653 }; 2654 2655 aggre1_noc: interconnect@16c0000 { 2656 compatible = "qcom,sa8775p-aggre1-noc"; 2657 reg = <0x0 0x016c0000 0x0 0x18080>; 2658 #interconnect-cells = <2>; 2659 qcom,bcm-voters = <&apps_bcm_voter>; 2660 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2661 <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, 2662 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 2663 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2664 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; 2665 }; 2666 2667 aggre2_noc: interconnect@1700000 { 2668 compatible = "qcom,sa8775p-aggre2-noc"; 2669 reg = <0x0 0x01700000 0x0 0x1b080>; 2670 #interconnect-cells = <2>; 2671 qcom,bcm-voters = <&apps_bcm_voter>; 2672 clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2673 <&rpmhcc RPMH_IPA_CLK>; 2674 }; 2675 2676 pcie_anoc: interconnect@1760000 { 2677 compatible = "qcom,sa8775p-pcie-anoc"; 2678 reg = <0x0 0x01760000 0x0 0xc080>; 2679 #interconnect-cells = <2>; 2680 qcom,bcm-voters = <&apps_bcm_voter>; 2681 }; 2682 2683 gpdsp_anoc: interconnect@1780000 { 2684 compatible = "qcom,sa8775p-gpdsp-anoc"; 2685 reg = <0x0 0x01780000 0x0 0xe080>; 2686 #interconnect-cells = <2>; 2687 qcom,bcm-voters = <&apps_bcm_voter>; 2688 }; 2689 2690 mmss_noc: interconnect@17a0000 { 2691 compatible = "qcom,sa8775p-mmss-noc"; 2692 reg = <0x0 0x017a0000 0x0 0x40000>; 2693 #interconnect-cells = <2>; 2694 qcom,bcm-voters = <&apps_bcm_voter>; 2695 }; 2696 2697 ufs_mem_hc: ufshc@1d84000 { 2698 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2699 reg = <0x0 0x01d84000 0x0 0x3000>; 2700 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2701 phys = <&ufs_mem_phy>; 2702 phy-names = "ufsphy"; 2703 lanes-per-direction = <2>; 2704 #reset-cells = <1>; 2705 resets = <&gcc GCC_UFS_PHY_BCR>; 2706 reset-names = "rst"; 2707 power-domains = <&gcc UFS_PHY_GDSC>; 2708 required-opps = <&rpmhpd_opp_nom>; 2709 iommus = <&apps_smmu 0x100 0x0>; 2710 dma-coherent; 2711 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2712 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2713 <&gcc GCC_UFS_PHY_AHB_CLK>, 2714 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2715 <&rpmhcc RPMH_CXO_CLK>, 2716 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2717 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2718 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2719 clock-names = "core_clk", 2720 "bus_aggr_clk", 2721 "iface_clk", 2722 "core_clk_unipro", 2723 "ref_clk", 2724 "tx_lane0_sync_clk", 2725 "rx_lane0_sync_clk", 2726 "rx_lane1_sync_clk"; 2727 freq-table-hz = <75000000 300000000>, 2728 <0 0>, 2729 <0 0>, 2730 <75000000 300000000>, 2731 <0 0>, 2732 <0 0>, 2733 <0 0>, 2734 <0 0>; 2735 qcom,ice = <&ice>; 2736 status = "disabled"; 2737 }; 2738 2739 ufs_mem_phy: phy@1d87000 { 2740 compatible = "qcom,sa8775p-qmp-ufs-phy"; 2741 reg = <0x0 0x01d87000 0x0 0xe10>; 2742 /* 2743 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2744 * enables the CXO clock to eDP *and* UFS PHY. 2745 */ 2746 clocks = <&rpmhcc RPMH_CXO_CLK>, 2747 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2748 <&gcc GCC_EDP_REF_CLKREF_EN>; 2749 clock-names = "ref", "ref_aux", "qref"; 2750 power-domains = <&gcc UFS_PHY_GDSC>; 2751 resets = <&ufs_mem_hc 0>; 2752 reset-names = "ufsphy"; 2753 #phy-cells = <0>; 2754 status = "disabled"; 2755 }; 2756 2757 ice: crypto@1d88000 { 2758 compatible = "qcom,sa8775p-inline-crypto-engine", 2759 "qcom,inline-crypto-engine"; 2760 reg = <0x0 0x01d88000 0x0 0x18000>; 2761 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2762 }; 2763 2764 cryptobam: dma-controller@1dc4000 { 2765 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2766 reg = <0x0 0x01dc4000 0x0 0x28000>; 2767 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2768 #dma-cells = <1>; 2769 qcom,ee = <0>; 2770 qcom,num-ees = <4>; 2771 num-channels = <20>; 2772 qcom,controlled-remotely; 2773 iommus = <&apps_smmu 0x480 0x00>, 2774 <&apps_smmu 0x481 0x00>; 2775 }; 2776 2777 crypto: crypto@1dfa000 { 2778 compatible = "qcom,sa8775p-qce", "qcom,sm8150-qce", "qcom,qce"; 2779 reg = <0x0 0x01dfa000 0x0 0x6000>; 2780 dmas = <&cryptobam 4>, <&cryptobam 5>; 2781 dma-names = "rx", "tx"; 2782 iommus = <&apps_smmu 0x480 0x0>, 2783 <&apps_smmu 0x481 0x0>; 2784 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS 2785 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2786 interconnect-names = "memory"; 2787 }; 2788 2789 lpass_ag_noc: interconnect@3c40000 { 2790 compatible = "qcom,sa8775p-lpass-ag-noc"; 2791 reg = <0x0 0x03c40000 0x0 0x17200>; 2792 #interconnect-cells = <2>; 2793 qcom,bcm-voters = <&apps_bcm_voter>; 2794 }; 2795 2796 ctcu@4001000 { 2797 compatible = "qcom,sa8775p-ctcu"; 2798 reg = <0x0 0x04001000 0x0 0x1000>; 2799 2800 clocks = <&aoss_qmp>; 2801 clock-names = "apb"; 2802 2803 in-ports { 2804 #address-cells = <1>; 2805 #size-cells = <0>; 2806 2807 port@0 { 2808 reg = <0>; 2809 2810 ctcu_in0: endpoint { 2811 remote-endpoint = <&etr0_out>; 2812 }; 2813 }; 2814 2815 port@1 { 2816 reg = <1>; 2817 2818 ctcu_in1: endpoint { 2819 remote-endpoint = <&etr1_out>; 2820 }; 2821 }; 2822 }; 2823 }; 2824 2825 stm: stm@4002000 { 2826 compatible = "arm,coresight-stm", "arm,primecell"; 2827 reg = <0x0 0x4002000 0x0 0x1000>, 2828 <0x0 0x16280000 0x0 0x180000>; 2829 reg-names = "stm-base", "stm-stimulus-base"; 2830 2831 clocks = <&aoss_qmp>; 2832 clock-names = "apb_pclk"; 2833 2834 out-ports { 2835 port { 2836 stm_out: endpoint { 2837 remote-endpoint = 2838 <&funnel0_in7>; 2839 }; 2840 }; 2841 }; 2842 }; 2843 2844 tpdm@4003000 { 2845 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2846 reg = <0x0 0x4003000 0x0 0x1000>; 2847 2848 clocks = <&aoss_qmp>; 2849 clock-names = "apb_pclk"; 2850 2851 qcom,cmb-element-bits = <32>; 2852 qcom,cmb-msrs-num = <32>; 2853 status = "disabled"; 2854 2855 out-ports { 2856 port { 2857 qdss_tpdm0_out: endpoint { 2858 remote-endpoint = 2859 <&qdss_tpda_in0>; 2860 }; 2861 }; 2862 }; 2863 }; 2864 2865 tpda@4004000 { 2866 compatible = "qcom,coresight-tpda", "arm,primecell"; 2867 reg = <0x0 0x4004000 0x0 0x1000>; 2868 2869 clocks = <&aoss_qmp>; 2870 clock-names = "apb_pclk"; 2871 2872 out-ports { 2873 port { 2874 qdss_tpda_out: endpoint { 2875 remote-endpoint = 2876 <&funnel0_in6>; 2877 }; 2878 }; 2879 }; 2880 2881 in-ports { 2882 #address-cells = <1>; 2883 #size-cells = <0>; 2884 2885 port@0 { 2886 reg = <0>; 2887 qdss_tpda_in0: endpoint { 2888 remote-endpoint = 2889 <&qdss_tpdm0_out>; 2890 }; 2891 }; 2892 2893 port@1 { 2894 reg = <1>; 2895 qdss_tpda_in1: endpoint { 2896 remote-endpoint = 2897 <&qdss_tpdm1_out>; 2898 }; 2899 }; 2900 }; 2901 }; 2902 2903 tpdm@400f000 { 2904 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2905 reg = <0x0 0x400f000 0x0 0x1000>; 2906 2907 clocks = <&aoss_qmp>; 2908 clock-names = "apb_pclk"; 2909 2910 qcom,cmb-element-bits = <32>; 2911 qcom,cmb-msrs-num = <32>; 2912 2913 out-ports { 2914 port { 2915 qdss_tpdm1_out: endpoint { 2916 remote-endpoint = 2917 <&qdss_tpda_in1>; 2918 }; 2919 }; 2920 }; 2921 }; 2922 2923 funnel@4041000 { 2924 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2925 reg = <0x0 0x4041000 0x0 0x1000>; 2926 2927 clocks = <&aoss_qmp>; 2928 clock-names = "apb_pclk"; 2929 2930 out-ports { 2931 port { 2932 funnel0_out: endpoint { 2933 remote-endpoint = 2934 <&qdss_funnel_in0>; 2935 }; 2936 }; 2937 }; 2938 2939 in-ports { 2940 #address-cells = <1>; 2941 #size-cells = <0>; 2942 2943 port@6 { 2944 reg = <6>; 2945 funnel0_in6: endpoint { 2946 remote-endpoint = 2947 <&qdss_tpda_out>; 2948 }; 2949 }; 2950 2951 port@7 { 2952 reg = <7>; 2953 funnel0_in7: endpoint { 2954 remote-endpoint = 2955 <&stm_out>; 2956 }; 2957 }; 2958 }; 2959 }; 2960 2961 funnel@4042000 { 2962 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2963 reg = <0x0 0x4042000 0x0 0x1000>; 2964 2965 clocks = <&aoss_qmp>; 2966 clock-names = "apb_pclk"; 2967 2968 out-ports { 2969 port { 2970 funnel1_out: endpoint { 2971 remote-endpoint = 2972 <&qdss_funnel_in1>; 2973 }; 2974 }; 2975 }; 2976 2977 in-ports { 2978 #address-cells = <1>; 2979 #size-cells = <0>; 2980 2981 port@4 { 2982 reg = <4>; 2983 funnel1_in4: endpoint { 2984 remote-endpoint = 2985 <&apss_funnel1_out>; 2986 }; 2987 }; 2988 2989 port@5 { 2990 reg = <5>; 2991 2992 funnel1_in5: endpoint { 2993 remote-endpoint = <&dlct0_funnel_out>; 2994 }; 2995 }; 2996 }; 2997 }; 2998 2999 funnel@4045000 { 3000 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3001 reg = <0x0 0x4045000 0x0 0x1000>; 3002 3003 clocks = <&aoss_qmp>; 3004 clock-names = "apb_pclk"; 3005 3006 out-ports { 3007 port { 3008 qdss_funnel_out: endpoint { 3009 remote-endpoint = 3010 <&aoss_funnel_in7>; 3011 }; 3012 }; 3013 }; 3014 3015 in-ports { 3016 #address-cells = <1>; 3017 #size-cells = <0>; 3018 3019 port@0 { 3020 reg = <0>; 3021 qdss_funnel_in0: endpoint { 3022 remote-endpoint = 3023 <&funnel0_out>; 3024 }; 3025 }; 3026 3027 port@1 { 3028 reg = <1>; 3029 qdss_funnel_in1: endpoint { 3030 remote-endpoint = 3031 <&funnel1_out>; 3032 }; 3033 }; 3034 }; 3035 }; 3036 3037 replicator@4046000 { 3038 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3039 reg = <0x0 0x04046000 0x0 0x1000>; 3040 3041 clocks = <&aoss_qmp>; 3042 clock-names = "apb_pclk"; 3043 3044 in-ports { 3045 port { 3046 qdss_rep_in: endpoint { 3047 remote-endpoint = <&swao_rep_out0>; 3048 }; 3049 }; 3050 }; 3051 3052 out-ports { 3053 port { 3054 qdss_rep_out0: endpoint { 3055 remote-endpoint = <&etr_rep_in>; 3056 }; 3057 }; 3058 }; 3059 }; 3060 3061 tmc_etr: tmc@4048000 { 3062 compatible = "arm,coresight-tmc", "arm,primecell"; 3063 reg = <0x0 0x04048000 0x0 0x1000>; 3064 3065 clocks = <&aoss_qmp>; 3066 clock-names = "apb_pclk"; 3067 iommus = <&apps_smmu 0x04c0 0x00>; 3068 3069 arm,scatter-gather; 3070 3071 in-ports { 3072 port { 3073 etr0_in: endpoint { 3074 remote-endpoint = <&etr_rep_out0>; 3075 }; 3076 }; 3077 }; 3078 3079 out-ports { 3080 port { 3081 etr0_out: endpoint { 3082 remote-endpoint = <&ctcu_in0>; 3083 }; 3084 }; 3085 }; 3086 }; 3087 3088 replicator@404e000 { 3089 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3090 reg = <0x0 0x0404e000 0x0 0x1000>; 3091 3092 clocks = <&aoss_qmp>; 3093 clock-names = "apb_pclk"; 3094 3095 in-ports { 3096 port { 3097 etr_rep_in: endpoint { 3098 remote-endpoint = <&qdss_rep_out0>; 3099 }; 3100 }; 3101 }; 3102 3103 out-ports { 3104 #address-cells = <1>; 3105 #size-cells = <0>; 3106 3107 port@0 { 3108 reg = <0>; 3109 3110 etr_rep_out0: endpoint { 3111 remote-endpoint = <&etr0_in>; 3112 }; 3113 }; 3114 3115 port@1 { 3116 reg = <1>; 3117 3118 etr_rep_out1: endpoint { 3119 remote-endpoint = <&etr1_in>; 3120 }; 3121 }; 3122 }; 3123 }; 3124 3125 tmc_etr1: tmc@404f000 { 3126 compatible = "arm,coresight-tmc", "arm,primecell"; 3127 reg = <0x0 0x0404f000 0x0 0x1000>; 3128 3129 clocks = <&aoss_qmp>; 3130 clock-names = "apb_pclk"; 3131 iommus = <&apps_smmu 0x04a0 0x40>; 3132 3133 arm,scatter-gather; 3134 arm,buffer-size = <0x400000>; 3135 3136 in-ports { 3137 port { 3138 etr1_in: endpoint { 3139 remote-endpoint = <&etr_rep_out1>; 3140 }; 3141 }; 3142 }; 3143 3144 out-ports { 3145 port { 3146 etr1_out: endpoint { 3147 remote-endpoint = <&ctcu_in1>; 3148 }; 3149 }; 3150 }; 3151 }; 3152 3153 tpda@4ad3000 { 3154 compatible = "qcom,coresight-tpda", "arm,primecell"; 3155 reg = <0x0 0x4ad3000 0x0 0x1000>; 3156 3157 clocks = <&aoss_qmp>; 3158 clock-names = "apb_pclk"; 3159 3160 in-ports { 3161 #address-cells = <1>; 3162 #size-cells = <0>; 3163 3164 port@10 { 3165 reg = <16>; 3166 dlct0_tpda_in16: endpoint { 3167 remote-endpoint = <&turing0_funnel_out>; 3168 }; 3169 }; 3170 }; 3171 3172 out-ports { 3173 port { 3174 dlct0_tpda_out: endpoint { 3175 remote-endpoint = 3176 <&dlct0_funnel_in0>; 3177 }; 3178 }; 3179 }; 3180 3181 }; 3182 3183 funnel@4ad4000 { 3184 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3185 reg = <0x0 0x4ad4000 0x0 0x1000>; 3186 3187 clocks = <&aoss_qmp>; 3188 clock-names = "apb_pclk"; 3189 3190 in-ports { 3191 port { 3192 dlct0_funnel_in0: endpoint { 3193 remote-endpoint = <&dlct0_tpda_out>; 3194 }; 3195 }; 3196 }; 3197 3198 out-ports { 3199 port { 3200 dlct0_funnel_out: endpoint { 3201 remote-endpoint = <&funnel1_in5>; 3202 }; 3203 }; 3204 }; 3205 }; 3206 3207 funnel@4b04000 { 3208 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3209 reg = <0x0 0x4b04000 0x0 0x1000>; 3210 3211 clocks = <&aoss_qmp>; 3212 clock-names = "apb_pclk"; 3213 3214 out-ports { 3215 port { 3216 aoss_funnel_out: endpoint { 3217 remote-endpoint = 3218 <&etf0_in>; 3219 }; 3220 }; 3221 }; 3222 3223 in-ports { 3224 #address-cells = <1>; 3225 #size-cells = <0>; 3226 3227 port@6 { 3228 reg = <6>; 3229 aoss_funnel_in6: endpoint { 3230 remote-endpoint = 3231 <&aoss_tpda_out>; 3232 }; 3233 }; 3234 3235 port@7 { 3236 reg = <7>; 3237 aoss_funnel_in7: endpoint { 3238 remote-endpoint = 3239 <&qdss_funnel_out>; 3240 }; 3241 }; 3242 }; 3243 }; 3244 3245 tmc_etf: tmc@4b05000 { 3246 compatible = "arm,coresight-tmc", "arm,primecell"; 3247 reg = <0x0 0x4b05000 0x0 0x1000>; 3248 3249 clocks = <&aoss_qmp>; 3250 clock-names = "apb_pclk"; 3251 3252 out-ports { 3253 port { 3254 etf0_out: endpoint { 3255 remote-endpoint = 3256 <&swao_rep_in>; 3257 }; 3258 }; 3259 }; 3260 3261 in-ports { 3262 port { 3263 etf0_in: endpoint { 3264 remote-endpoint = 3265 <&aoss_funnel_out>; 3266 }; 3267 }; 3268 }; 3269 }; 3270 3271 replicator@4b06000 { 3272 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3273 reg = <0x0 0x4b06000 0x0 0x1000>; 3274 3275 clocks = <&aoss_qmp>; 3276 clock-names = "apb_pclk"; 3277 3278 out-ports { 3279 #address-cells = <1>; 3280 #size-cells = <0>; 3281 3282 port@0 { 3283 reg = <0>; 3284 3285 swao_rep_out0: endpoint { 3286 remote-endpoint = <&qdss_rep_in>; 3287 }; 3288 }; 3289 3290 port@1 { 3291 reg = <1>; 3292 swao_rep_out1: endpoint { 3293 remote-endpoint = 3294 <&eud_in>; 3295 }; 3296 }; 3297 }; 3298 3299 in-ports { 3300 port { 3301 swao_rep_in: endpoint { 3302 remote-endpoint = 3303 <&etf0_out>; 3304 }; 3305 }; 3306 }; 3307 }; 3308 3309 tpda@4b08000 { 3310 compatible = "qcom,coresight-tpda", "arm,primecell"; 3311 reg = <0x0 0x4b08000 0x0 0x1000>; 3312 3313 clocks = <&aoss_qmp>; 3314 clock-names = "apb_pclk"; 3315 3316 out-ports { 3317 port { 3318 aoss_tpda_out: endpoint { 3319 remote-endpoint = 3320 <&aoss_funnel_in6>; 3321 }; 3322 }; 3323 }; 3324 3325 in-ports { 3326 #address-cells = <1>; 3327 #size-cells = <0>; 3328 3329 port@0 { 3330 reg = <0>; 3331 aoss_tpda_in0: endpoint { 3332 remote-endpoint = 3333 <&aoss_tpdm0_out>; 3334 }; 3335 }; 3336 3337 port@1 { 3338 reg = <1>; 3339 aoss_tpda_in1: endpoint { 3340 remote-endpoint = 3341 <&aoss_tpdm1_out>; 3342 }; 3343 }; 3344 3345 port@2 { 3346 reg = <2>; 3347 aoss_tpda_in2: endpoint { 3348 remote-endpoint = 3349 <&aoss_tpdm2_out>; 3350 }; 3351 }; 3352 3353 port@3 { 3354 reg = <3>; 3355 aoss_tpda_in3: endpoint { 3356 remote-endpoint = 3357 <&aoss_tpdm3_out>; 3358 }; 3359 }; 3360 3361 port@4 { 3362 reg = <4>; 3363 aoss_tpda_in4: endpoint { 3364 remote-endpoint = 3365 <&aoss_tpdm4_out>; 3366 }; 3367 }; 3368 }; 3369 }; 3370 3371 tpdm@4b09000 { 3372 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3373 reg = <0x0 0x4b09000 0x0 0x1000>; 3374 3375 clocks = <&aoss_qmp>; 3376 clock-names = "apb_pclk"; 3377 3378 qcom,cmb-element-bits = <64>; 3379 qcom,cmb-msrs-num = <32>; 3380 3381 out-ports { 3382 port { 3383 aoss_tpdm0_out: endpoint { 3384 remote-endpoint = 3385 <&aoss_tpda_in0>; 3386 }; 3387 }; 3388 }; 3389 }; 3390 3391 tpdm@4b0a000 { 3392 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3393 reg = <0x0 0x4b0a000 0x0 0x1000>; 3394 3395 clocks = <&aoss_qmp>; 3396 clock-names = "apb_pclk"; 3397 3398 qcom,cmb-element-bits = <64>; 3399 qcom,cmb-msrs-num = <32>; 3400 3401 out-ports { 3402 port { 3403 aoss_tpdm1_out: endpoint { 3404 remote-endpoint = 3405 <&aoss_tpda_in1>; 3406 }; 3407 }; 3408 }; 3409 }; 3410 3411 tpdm@4b0b000 { 3412 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3413 reg = <0x0 0x4b0b000 0x0 0x1000>; 3414 3415 clocks = <&aoss_qmp>; 3416 clock-names = "apb_pclk"; 3417 3418 qcom,cmb-element-bits = <64>; 3419 qcom,cmb-msrs-num = <32>; 3420 3421 out-ports { 3422 port { 3423 aoss_tpdm2_out: endpoint { 3424 remote-endpoint = 3425 <&aoss_tpda_in2>; 3426 }; 3427 }; 3428 }; 3429 }; 3430 3431 tpdm@4b0c000 { 3432 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3433 reg = <0x0 0x4b0c000 0x0 0x1000>; 3434 3435 clocks = <&aoss_qmp>; 3436 clock-names = "apb_pclk"; 3437 3438 qcom,cmb-element-bits = <64>; 3439 qcom,cmb-msrs-num = <32>; 3440 3441 out-ports { 3442 port { 3443 aoss_tpdm3_out: endpoint { 3444 remote-endpoint = 3445 <&aoss_tpda_in3>; 3446 }; 3447 }; 3448 }; 3449 }; 3450 3451 tpdm@4b0d000 { 3452 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3453 reg = <0x0 0x4b0d000 0x0 0x1000>; 3454 3455 clocks = <&aoss_qmp>; 3456 clock-names = "apb_pclk"; 3457 3458 qcom,dsb-element-bits = <32>; 3459 qcom,dsb-msrs-num = <32>; 3460 3461 out-ports { 3462 port { 3463 aoss_tpdm4_out: endpoint { 3464 remote-endpoint = 3465 <&aoss_tpda_in4>; 3466 }; 3467 }; 3468 }; 3469 }; 3470 3471 aoss_cti: cti@4b13000 { 3472 compatible = "arm,coresight-cti", "arm,primecell"; 3473 reg = <0x0 0x4b13000 0x0 0x1000>; 3474 3475 clocks = <&aoss_qmp>; 3476 clock-names = "apb_pclk"; 3477 }; 3478 3479 funnel@4b83000 { 3480 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3481 reg = <0x0 0x4b83000 0x0 0x1000>; 3482 3483 clocks = <&aoss_qmp>; 3484 clock-names = "apb_pclk"; 3485 3486 in-ports { 3487 #address-cells = <1>; 3488 #size-cells = <0>; 3489 3490 port@1 { 3491 reg = <1>; 3492 3493 turing0_funnel_in1: endpoint { 3494 remote-endpoint = <&turing_llm_tpdm_out>; 3495 }; 3496 }; 3497 }; 3498 3499 out-ports { 3500 port { 3501 turing0_funnel_out: endpoint { 3502 remote-endpoint = <&dlct0_tpda_in16>; 3503 }; 3504 }; 3505 }; 3506 }; 3507 3508 etm@6040000 { 3509 compatible = "arm,primecell"; 3510 reg = <0x0 0x6040000 0x0 0x1000>; 3511 cpu = <&cpu0>; 3512 3513 clocks = <&aoss_qmp>; 3514 clock-names = "apb_pclk"; 3515 arm,coresight-loses-context-with-cpu; 3516 qcom,skip-power-up; 3517 3518 out-ports { 3519 port { 3520 etm0_out: endpoint { 3521 remote-endpoint = 3522 <&apss_funnel0_in0>; 3523 }; 3524 }; 3525 }; 3526 }; 3527 3528 etm@6140000 { 3529 compatible = "arm,primecell"; 3530 reg = <0x0 0x6140000 0x0 0x1000>; 3531 cpu = <&cpu1>; 3532 3533 clocks = <&aoss_qmp>; 3534 clock-names = "apb_pclk"; 3535 arm,coresight-loses-context-with-cpu; 3536 qcom,skip-power-up; 3537 3538 out-ports { 3539 port { 3540 etm1_out: endpoint { 3541 remote-endpoint = 3542 <&apss_funnel0_in1>; 3543 }; 3544 }; 3545 }; 3546 }; 3547 3548 etm@6240000 { 3549 compatible = "arm,primecell"; 3550 reg = <0x0 0x6240000 0x0 0x1000>; 3551 cpu = <&cpu2>; 3552 3553 clocks = <&aoss_qmp>; 3554 clock-names = "apb_pclk"; 3555 arm,coresight-loses-context-with-cpu; 3556 qcom,skip-power-up; 3557 3558 out-ports { 3559 port { 3560 etm2_out: endpoint { 3561 remote-endpoint = 3562 <&apss_funnel0_in2>; 3563 }; 3564 }; 3565 }; 3566 }; 3567 3568 etm@6340000 { 3569 compatible = "arm,primecell"; 3570 reg = <0x0 0x6340000 0x0 0x1000>; 3571 cpu = <&cpu3>; 3572 3573 clocks = <&aoss_qmp>; 3574 clock-names = "apb_pclk"; 3575 arm,coresight-loses-context-with-cpu; 3576 qcom,skip-power-up; 3577 3578 out-ports { 3579 port { 3580 etm3_out: endpoint { 3581 remote-endpoint = 3582 <&apss_funnel0_in3>; 3583 }; 3584 }; 3585 }; 3586 }; 3587 3588 etm@6440000 { 3589 compatible = "arm,primecell"; 3590 reg = <0x0 0x6440000 0x0 0x1000>; 3591 cpu = <&cpu4>; 3592 3593 clocks = <&aoss_qmp>; 3594 clock-names = "apb_pclk"; 3595 arm,coresight-loses-context-with-cpu; 3596 qcom,skip-power-up; 3597 3598 out-ports { 3599 port { 3600 etm4_out: endpoint { 3601 remote-endpoint = 3602 <&apss_funnel0_in4>; 3603 }; 3604 }; 3605 }; 3606 }; 3607 3608 etm@6540000 { 3609 compatible = "arm,primecell"; 3610 reg = <0x0 0x6540000 0x0 0x1000>; 3611 cpu = <&cpu5>; 3612 3613 clocks = <&aoss_qmp>; 3614 clock-names = "apb_pclk"; 3615 arm,coresight-loses-context-with-cpu; 3616 qcom,skip-power-up; 3617 3618 out-ports { 3619 port { 3620 etm5_out: endpoint { 3621 remote-endpoint = 3622 <&apss_funnel0_in5>; 3623 }; 3624 }; 3625 }; 3626 }; 3627 3628 etm@6640000 { 3629 compatible = "arm,primecell"; 3630 reg = <0x0 0x6640000 0x0 0x1000>; 3631 cpu = <&cpu6>; 3632 3633 clocks = <&aoss_qmp>; 3634 clock-names = "apb_pclk"; 3635 arm,coresight-loses-context-with-cpu; 3636 qcom,skip-power-up; 3637 3638 out-ports { 3639 port { 3640 etm6_out: endpoint { 3641 remote-endpoint = 3642 <&apss_funnel0_in6>; 3643 }; 3644 }; 3645 }; 3646 }; 3647 3648 etm@6740000 { 3649 compatible = "arm,primecell"; 3650 reg = <0x0 0x6740000 0x0 0x1000>; 3651 cpu = <&cpu7>; 3652 3653 clocks = <&aoss_qmp>; 3654 clock-names = "apb_pclk"; 3655 arm,coresight-loses-context-with-cpu; 3656 qcom,skip-power-up; 3657 3658 out-ports { 3659 port { 3660 etm7_out: endpoint { 3661 remote-endpoint = 3662 <&apss_funnel0_in7>; 3663 }; 3664 }; 3665 }; 3666 }; 3667 3668 funnel@6800000 { 3669 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3670 reg = <0x0 0x6800000 0x0 0x1000>; 3671 3672 clocks = <&aoss_qmp>; 3673 clock-names = "apb_pclk"; 3674 3675 out-ports { 3676 port { 3677 apss_funnel0_out: endpoint { 3678 remote-endpoint = 3679 <&apss_funnel1_in0>; 3680 }; 3681 }; 3682 }; 3683 3684 in-ports { 3685 #address-cells = <1>; 3686 #size-cells = <0>; 3687 3688 port@0 { 3689 reg = <0>; 3690 apss_funnel0_in0: endpoint { 3691 remote-endpoint = 3692 <&etm0_out>; 3693 }; 3694 }; 3695 3696 port@1 { 3697 reg = <1>; 3698 apss_funnel0_in1: endpoint { 3699 remote-endpoint = 3700 <&etm1_out>; 3701 }; 3702 }; 3703 3704 port@2 { 3705 reg = <2>; 3706 apss_funnel0_in2: endpoint { 3707 remote-endpoint = 3708 <&etm2_out>; 3709 }; 3710 }; 3711 3712 port@3 { 3713 reg = <3>; 3714 apss_funnel0_in3: endpoint { 3715 remote-endpoint = 3716 <&etm3_out>; 3717 }; 3718 }; 3719 3720 port@4 { 3721 reg = <4>; 3722 apss_funnel0_in4: endpoint { 3723 remote-endpoint = 3724 <&etm4_out>; 3725 }; 3726 }; 3727 3728 port@5 { 3729 reg = <5>; 3730 apss_funnel0_in5: endpoint { 3731 remote-endpoint = 3732 <&etm5_out>; 3733 }; 3734 }; 3735 3736 port@6 { 3737 reg = <6>; 3738 apss_funnel0_in6: endpoint { 3739 remote-endpoint = 3740 <&etm6_out>; 3741 }; 3742 }; 3743 3744 port@7 { 3745 reg = <7>; 3746 apss_funnel0_in7: endpoint { 3747 remote-endpoint = 3748 <&etm7_out>; 3749 }; 3750 }; 3751 }; 3752 }; 3753 3754 funnel@6810000 { 3755 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3756 reg = <0x0 0x6810000 0x0 0x1000>; 3757 3758 clocks = <&aoss_qmp>; 3759 clock-names = "apb_pclk"; 3760 3761 out-ports { 3762 port { 3763 apss_funnel1_out: endpoint { 3764 remote-endpoint = 3765 <&funnel1_in4>; 3766 }; 3767 }; 3768 }; 3769 3770 in-ports { 3771 #address-cells = <1>; 3772 #size-cells = <0>; 3773 3774 port@0 { 3775 reg = <0>; 3776 apss_funnel1_in0: endpoint { 3777 remote-endpoint = 3778 <&apss_funnel0_out>; 3779 }; 3780 }; 3781 3782 port@3 { 3783 reg = <3>; 3784 apss_funnel1_in3: endpoint { 3785 remote-endpoint = 3786 <&apss_tpda_out>; 3787 }; 3788 }; 3789 }; 3790 }; 3791 3792 tpdm@6860000 { 3793 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3794 reg = <0x0 0x6860000 0x0 0x1000>; 3795 3796 clocks = <&aoss_qmp>; 3797 clock-names = "apb_pclk"; 3798 3799 qcom,cmb-element-bits = <64>; 3800 qcom,cmb-msrs-num = <32>; 3801 3802 out-ports { 3803 port { 3804 apss_tpdm3_out: endpoint { 3805 remote-endpoint = 3806 <&apss_tpda_in3>; 3807 }; 3808 }; 3809 }; 3810 }; 3811 3812 tpdm@6861000 { 3813 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3814 reg = <0x0 0x6861000 0x0 0x1000>; 3815 3816 clocks = <&aoss_qmp>; 3817 clock-names = "apb_pclk"; 3818 3819 qcom,dsb-element-bits = <32>; 3820 qcom,dsb-msrs-num = <32>; 3821 3822 out-ports { 3823 port { 3824 apss_tpdm4_out: endpoint { 3825 remote-endpoint = 3826 <&apss_tpda_in4>; 3827 }; 3828 }; 3829 }; 3830 }; 3831 3832 tpda@6863000 { 3833 compatible = "qcom,coresight-tpda", "arm,primecell"; 3834 reg = <0x0 0x6863000 0x0 0x1000>; 3835 3836 clocks = <&aoss_qmp>; 3837 clock-names = "apb_pclk"; 3838 3839 out-ports { 3840 port { 3841 apss_tpda_out: endpoint { 3842 remote-endpoint = 3843 <&apss_funnel1_in3>; 3844 }; 3845 }; 3846 }; 3847 3848 in-ports { 3849 #address-cells = <1>; 3850 #size-cells = <0>; 3851 3852 port@0 { 3853 reg = <0>; 3854 apss_tpda_in0: endpoint { 3855 remote-endpoint = 3856 <&apss_tpdm0_out>; 3857 }; 3858 }; 3859 3860 port@1 { 3861 reg = <1>; 3862 apss_tpda_in1: endpoint { 3863 remote-endpoint = 3864 <&apss_tpdm1_out>; 3865 }; 3866 }; 3867 3868 port@2 { 3869 reg = <2>; 3870 apss_tpda_in2: endpoint { 3871 remote-endpoint = 3872 <&apss_tpdm2_out>; 3873 }; 3874 }; 3875 3876 port@3 { 3877 reg = <3>; 3878 apss_tpda_in3: endpoint { 3879 remote-endpoint = 3880 <&apss_tpdm3_out>; 3881 }; 3882 }; 3883 3884 port@4 { 3885 reg = <4>; 3886 apss_tpda_in4: endpoint { 3887 remote-endpoint = 3888 <&apss_tpdm4_out>; 3889 }; 3890 }; 3891 }; 3892 }; 3893 3894 tpdm@68a0000 { 3895 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3896 reg = <0x0 0x68a0000 0x0 0x1000>; 3897 3898 clocks = <&aoss_qmp>; 3899 clock-names = "apb_pclk"; 3900 3901 qcom,cmb-element-bits = <32>; 3902 qcom,cmb-msrs-num = <32>; 3903 3904 out-ports { 3905 port { 3906 apss_tpdm0_out: endpoint { 3907 remote-endpoint = 3908 <&apss_tpda_in0>; 3909 }; 3910 }; 3911 }; 3912 }; 3913 3914 tpdm@68b0000 { 3915 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3916 reg = <0x0 0x68b0000 0x0 0x1000>; 3917 3918 clocks = <&aoss_qmp>; 3919 clock-names = "apb_pclk"; 3920 3921 qcom,cmb-element-bits = <32>; 3922 qcom,cmb-msrs-num = <32>; 3923 3924 out-ports { 3925 port { 3926 apss_tpdm1_out: endpoint { 3927 remote-endpoint = 3928 <&apss_tpda_in1>; 3929 }; 3930 }; 3931 }; 3932 }; 3933 3934 tpdm@68c0000 { 3935 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3936 reg = <0x0 0x68c0000 0x0 0x1000>; 3937 3938 clocks = <&aoss_qmp>; 3939 clock-names = "apb_pclk"; 3940 3941 qcom,dsb-element-bits = <32>; 3942 qcom,dsb-msrs-num = <32>; 3943 3944 out-ports { 3945 port { 3946 apss_tpdm2_out: endpoint { 3947 remote-endpoint = 3948 <&apss_tpda_in2>; 3949 }; 3950 }; 3951 }; 3952 }; 3953 3954 sdhc: mmc@87c4000 { 3955 compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; 3956 reg = <0x0 0x087c4000 0x0 0x1000>; 3957 3958 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 3959 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; 3960 interrupt-names = "hc_irq", 3961 "pwr_irq"; 3962 3963 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3964 <&gcc GCC_SDCC1_APPS_CLK>; 3965 clock-names = "iface", 3966 "core"; 3967 3968 interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS 3969 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3970 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3971 &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3972 interconnect-names = "sdhc-ddr", 3973 "cpu-sdhc"; 3974 3975 iommus = <&apps_smmu 0x0 0x0>; 3976 dma-coherent; 3977 3978 operating-points-v2 = <&sdhc_opp_table>; 3979 power-domains = <&rpmhpd SA8775P_CX>; 3980 resets = <&gcc GCC_SDCC1_BCR>; 3981 3982 qcom,dll-config = <0x0007642c>; 3983 qcom,ddr-config = <0x80040868>; 3984 3985 status = "disabled"; 3986 3987 sdhc_opp_table: opp-table { 3988 compatible = "operating-points-v2"; 3989 3990 opp-100000000 { 3991 opp-hz = /bits/ 64 <100000000>; 3992 required-opps = <&rpmhpd_opp_low_svs>; 3993 opp-peak-kBps = <1800000 400000>; 3994 opp-avg-kBps = <100000 0>; 3995 }; 3996 3997 opp-384000000 { 3998 opp-hz = /bits/ 64 <384000000>; 3999 required-opps = <&rpmhpd_opp_nom>; 4000 opp-peak-kBps = <5400000 1600000>; 4001 opp-avg-kBps = <390000 0>; 4002 }; 4003 }; 4004 }; 4005 4006 usb_0_hsphy: phy@88e4000 { 4007 compatible = "qcom,sa8775p-usb-hs-phy", 4008 "qcom,usb-snps-hs-5nm-phy"; 4009 reg = <0 0x088e4000 0 0x120>; 4010 clocks = <&rpmhcc RPMH_CXO_CLK>; 4011 clock-names = "ref"; 4012 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 4013 4014 #phy-cells = <0>; 4015 4016 status = "disabled"; 4017 }; 4018 4019 usb_1_hsphy: phy@88e6000 { 4020 compatible = "qcom,sa8775p-usb-hs-phy", 4021 "qcom,usb-snps-hs-5nm-phy"; 4022 reg = <0 0x088e6000 0 0x120>; 4023 clocks = <&gcc GCC_USB_CLKREF_EN>; 4024 clock-names = "ref"; 4025 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 4026 4027 #phy-cells = <0>; 4028 4029 status = "disabled"; 4030 }; 4031 4032 usb_2_hsphy: phy@88e7000 { 4033 compatible = "qcom,sa8775p-usb-hs-phy", 4034 "qcom,usb-snps-hs-5nm-phy"; 4035 reg = <0 0x088e7000 0 0x120>; 4036 clocks = <&gcc GCC_USB_CLKREF_EN>; 4037 clock-names = "ref"; 4038 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 4039 4040 #phy-cells = <0>; 4041 4042 status = "disabled"; 4043 }; 4044 4045 usb_0_qmpphy: phy@88e8000 { 4046 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 4047 reg = <0 0x088e8000 0 0x2000>; 4048 4049 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4050 <&gcc GCC_USB_CLKREF_EN>, 4051 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4052 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4053 clock-names = "aux", "ref", "com_aux", "pipe"; 4054 4055 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4056 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 4057 reset-names = "phy", "phy_phy"; 4058 4059 power-domains = <&gcc USB30_PRIM_GDSC>; 4060 4061 #clock-cells = <0>; 4062 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 4063 4064 #phy-cells = <0>; 4065 4066 status = "disabled"; 4067 }; 4068 4069 usb_1_qmpphy: phy@88ea000 { 4070 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 4071 reg = <0 0x088ea000 0 0x2000>; 4072 4073 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4074 <&gcc GCC_USB_CLKREF_EN>, 4075 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 4076 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4077 clock-names = "aux", "ref", "com_aux", "pipe"; 4078 4079 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 4080 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 4081 reset-names = "phy", "phy_phy"; 4082 4083 power-domains = <&gcc USB30_SEC_GDSC>; 4084 4085 #clock-cells = <0>; 4086 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 4087 4088 #phy-cells = <0>; 4089 4090 status = "disabled"; 4091 }; 4092 4093 refgen: regulator@891c000 { 4094 compatible = "qcom,sa8775p-refgen-regulator", 4095 "qcom,sm8250-refgen-regulator"; 4096 reg = <0x0 0x0891c000 0x0 0x84>; 4097 }; 4098 4099 dc_noc: interconnect@90e0000 { 4100 compatible = "qcom,sa8775p-dc-noc"; 4101 reg = <0x0 0x090e0000 0x0 0x5080>; 4102 #interconnect-cells = <2>; 4103 qcom,bcm-voters = <&apps_bcm_voter>; 4104 }; 4105 4106 gem_noc: interconnect@9100000 { 4107 compatible = "qcom,sa8775p-gem-noc"; 4108 reg = <0x0 0x09100000 0x0 0xf6080>; 4109 #interconnect-cells = <2>; 4110 qcom,bcm-voters = <&apps_bcm_voter>; 4111 }; 4112 4113 usb_0: usb@a600000 { 4114 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4115 reg = <0 0x0a600000 0 0xfc100>; 4116 4117 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4118 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4119 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4120 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4121 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4122 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4123 4124 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4125 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4126 assigned-clock-rates = <19200000>, <200000000>; 4127 4128 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 4129 <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 4130 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4131 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4132 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4133 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 4134 interrupt-names = "dwc_usb3", 4135 "pwr_event", 4136 "hs_phy_irq", 4137 "dp_hs_phy_irq", 4138 "dm_hs_phy_irq", 4139 "ss_phy_irq"; 4140 4141 power-domains = <&gcc USB30_PRIM_GDSC>; 4142 required-opps = <&rpmhpd_opp_nom>; 4143 4144 resets = <&gcc GCC_USB30_PRIM_BCR>; 4145 4146 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4147 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4148 interconnect-names = "usb-ddr", "apps-usb"; 4149 4150 wakeup-source; 4151 4152 iommus = <&apps_smmu 0x080 0x0>; 4153 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 4154 phy-names = "usb2-phy", "usb3-phy"; 4155 snps,dis-u1-entry-quirk; 4156 snps,dis-u2-entry-quirk; 4157 4158 usb-role-switch; 4159 status = "disabled"; 4160 4161 ports { 4162 #address-cells = <1>; 4163 #size-cells = <0>; 4164 4165 port@0 { 4166 reg = <0>; 4167 4168 usb_0_dwc3_hs: endpoint { 4169 }; 4170 }; 4171 4172 port@1 { 4173 reg = <1>; 4174 4175 usb_0_dwc3_ss: endpoint { 4176 }; 4177 }; 4178 }; 4179 }; 4180 4181 usb_1: usb@a800000 { 4182 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4183 reg = <0 0x0a800000 0 0xfc100>; 4184 4185 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4186 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4187 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4188 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4189 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4190 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4191 4192 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4193 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4194 assigned-clock-rates = <19200000>, <200000000>; 4195 4196 interrupts-extended = <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 4197 <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 4198 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 4199 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 4200 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 4201 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 4202 interrupt-names = "dwc_usb3", 4203 "pwr_event", 4204 "hs_phy_irq", 4205 "dp_hs_phy_irq", 4206 "dm_hs_phy_irq", 4207 "ss_phy_irq"; 4208 4209 power-domains = <&gcc USB30_SEC_GDSC>; 4210 required-opps = <&rpmhpd_opp_nom>; 4211 4212 resets = <&gcc GCC_USB30_SEC_BCR>; 4213 4214 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 4215 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4216 interconnect-names = "usb-ddr", "apps-usb"; 4217 4218 wakeup-source; 4219 4220 iommus = <&apps_smmu 0x0a0 0x0>; 4221 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 4222 phy-names = "usb2-phy", "usb3-phy"; 4223 snps,dis-u1-entry-quirk; 4224 snps,dis-u2-entry-quirk; 4225 4226 status = "disabled"; 4227 }; 4228 4229 usb_2: usb@a400000 { 4230 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4231 reg = <0 0x0a400000 0 0xfc100>; 4232 4233 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4234 <&gcc GCC_USB20_MASTER_CLK>, 4235 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4236 <&gcc GCC_USB20_SLEEP_CLK>, 4237 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 4238 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4239 4240 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4241 <&gcc GCC_USB20_MASTER_CLK>; 4242 assigned-clock-rates = <19200000>, <200000000>; 4243 4244 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 4245 <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 4246 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 4247 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 4248 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 4249 interrupt-names = "dwc_usb3", 4250 "pwr_event", 4251 "hs_phy_irq", 4252 "dp_hs_phy_irq", 4253 "dm_hs_phy_irq"; 4254 4255 power-domains = <&gcc USB20_PRIM_GDSC>; 4256 required-opps = <&rpmhpd_opp_nom>; 4257 4258 resets = <&gcc GCC_USB20_PRIM_BCR>; 4259 4260 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 4261 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 4262 interconnect-names = "usb-ddr", "apps-usb"; 4263 4264 qcom,select-utmi-as-pipe-clk; 4265 wakeup-source; 4266 4267 iommus = <&apps_smmu 0x020 0x0>; 4268 phys = <&usb_2_hsphy>; 4269 phy-names = "usb2-phy"; 4270 snps,dis-u1-entry-quirk; 4271 snps,dis-u2-entry-quirk; 4272 4273 usb-role-switch; 4274 4275 status = "disabled"; 4276 4277 port { 4278 usb_2_dwc3_hs: endpoint { 4279 }; 4280 }; 4281 }; 4282 4283 tcsr_mutex: hwlock@1f40000 { 4284 compatible = "qcom,tcsr-mutex"; 4285 reg = <0x0 0x01f40000 0x0 0x20000>; 4286 #hwlock-cells = <1>; 4287 }; 4288 4289 tcsr: syscon@1fc0000 { 4290 compatible = "qcom,sa8775p-tcsr", "syscon"; 4291 reg = <0x0 0x1fc0000 0x0 0x30000>; 4292 }; 4293 4294 gpu: gpu@3d00000 { 4295 compatible = "qcom,adreno-663.0", "qcom,adreno"; 4296 reg = <0x0 0x03d00000 0x0 0x40000>, 4297 <0x0 0x03d9e000 0x0 0x1000>, 4298 <0x0 0x03d61000 0x0 0x800>; 4299 reg-names = "kgsl_3d0_reg_memory", 4300 "cx_mem", 4301 "cx_dbgc"; 4302 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4303 iommus = <&adreno_smmu 0 0xc00>, 4304 <&adreno_smmu 1 0xc00>; 4305 operating-points-v2 = <&gpu_opp_table>; 4306 qcom,gmu = <&gmu>; 4307 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4308 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4309 interconnect-names = "gfx-mem"; 4310 #cooling-cells = <2>; 4311 4312 nvmem-cells = <&gpu_speed_bin>; 4313 nvmem-cell-names = "speed_bin"; 4314 4315 status = "disabled"; 4316 4317 gpu_zap_shader: zap-shader { 4318 memory-region = <&pil_gpu_mem>; 4319 }; 4320 4321 gpu_opp_table: opp-table { 4322 compatible = "operating-points-v2"; 4323 4324 opp-405000000 { 4325 opp-hz = /bits/ 64 <405000000>; 4326 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4327 opp-peak-kBps = <5285156>; 4328 opp-supported-hw = <0x3>; 4329 }; 4330 4331 opp-530000000 { 4332 opp-hz = /bits/ 64 <530000000>; 4333 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4334 opp-peak-kBps = <12484375>; 4335 opp-supported-hw = <0x2>; 4336 }; 4337 4338 opp-676000000 { 4339 opp-hz = /bits/ 64 <676000000>; 4340 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4341 opp-peak-kBps = <8171875>; 4342 opp-supported-hw = <0x1>; 4343 }; 4344 4345 opp-778000000 { 4346 opp-hz = /bits/ 64 <778000000>; 4347 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4348 opp-peak-kBps = <10687500>; 4349 opp-supported-hw = <0x1>; 4350 }; 4351 4352 opp-800000000 { 4353 opp-hz = /bits/ 64 <800000000>; 4354 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4355 opp-peak-kBps = <12484375>; 4356 opp-supported-hw = <0x1>; 4357 }; 4358 }; 4359 }; 4360 4361 gmu: gmu@3d6a000 { 4362 compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; 4363 reg = <0x0 0x03d6a000 0x0 0x34000>, 4364 <0x0 0x03de0000 0x0 0x10000>, 4365 <0x0 0x0b290000 0x0 0x10000>; 4366 reg-names = "gmu", "rscc", "gmu_pdc"; 4367 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4368 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4369 interrupt-names = "hfi", "gmu"; 4370 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4371 <&gpucc GPU_CC_CXO_CLK>, 4372 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4373 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4374 <&gpucc GPU_CC_AHB_CLK>, 4375 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4376 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 4377 clock-names = "gmu", 4378 "cxo", 4379 "axi", 4380 "memnoc", 4381 "ahb", 4382 "hub", 4383 "smmu_vote"; 4384 power-domains = <&gpucc GPU_CC_CX_GDSC>, 4385 <&gpucc GPU_CC_GX_GDSC>; 4386 power-domain-names = "cx", 4387 "gx"; 4388 iommus = <&adreno_smmu 5 0xc00>; 4389 operating-points-v2 = <&gmu_opp_table>; 4390 4391 gmu_opp_table: opp-table { 4392 compatible = "operating-points-v2"; 4393 4394 opp-500000000 { 4395 opp-hz = /bits/ 64 <500000000>; 4396 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4397 }; 4398 }; 4399 }; 4400 4401 gpucc: clock-controller@3d90000 { 4402 compatible = "qcom,sa8775p-gpucc"; 4403 reg = <0x0 0x03d90000 0x0 0xa000>; 4404 clocks = <&rpmhcc RPMH_CXO_CLK>, 4405 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4406 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4407 clock-names = "bi_tcxo", 4408 "gcc_gpu_gpll0_clk_src", 4409 "gcc_gpu_gpll0_div_clk_src"; 4410 #clock-cells = <1>; 4411 #reset-cells = <1>; 4412 #power-domain-cells = <1>; 4413 }; 4414 4415 adreno_smmu: iommu@3da0000 { 4416 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 4417 "qcom,smmu-500", "arm,mmu-500"; 4418 reg = <0x0 0x03da0000 0x0 0x20000>; 4419 #iommu-cells = <2>; 4420 #global-interrupts = <2>; 4421 dma-coherent; 4422 power-domains = <&gpucc GPU_CC_CX_GDSC>; 4423 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4424 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4425 <&gpucc GPU_CC_AHB_CLK>, 4426 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4427 <&gpucc GPU_CC_CX_GMU_CLK>, 4428 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4429 <&gpucc GPU_CC_HUB_AON_CLK>; 4430 clock-names = "gcc_gpu_memnoc_gfx_clk", 4431 "gcc_gpu_snoc_dvm_gfx_clk", 4432 "gpu_cc_ahb_clk", 4433 "gpu_cc_hlos1_vote_gpu_smmu_clk", 4434 "gpu_cc_cx_gmu_clk", 4435 "gpu_cc_hub_cx_int_clk", 4436 "gpu_cc_hub_aon_clk"; 4437 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 4438 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4439 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4440 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4441 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4442 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4443 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4444 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4445 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4446 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4447 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4448 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 4449 }; 4450 4451 serdes0: phy@8901000 { 4452 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4453 reg = <0x0 0x08901000 0x0 0xe10>; 4454 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4455 clock-names = "sgmi_ref"; 4456 #phy-cells = <0>; 4457 status = "disabled"; 4458 }; 4459 4460 serdes1: phy@8902000 { 4461 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4462 reg = <0x0 0x08902000 0x0 0xe10>; 4463 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4464 clock-names = "sgmi_ref"; 4465 #phy-cells = <0>; 4466 status = "disabled"; 4467 }; 4468 4469 pmu@9091000 { 4470 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4471 reg = <0x0 0x9091000 0x0 0x1000>; 4472 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 4473 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 4474 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4475 4476 operating-points-v2 = <&llcc_bwmon_opp_table>; 4477 4478 llcc_bwmon_opp_table: opp-table { 4479 compatible = "operating-points-v2"; 4480 4481 opp-0 { 4482 opp-peak-kBps = <762000>; 4483 }; 4484 4485 opp-1 { 4486 opp-peak-kBps = <1720000>; 4487 }; 4488 4489 opp-2 { 4490 opp-peak-kBps = <2086000>; 4491 }; 4492 4493 opp-3 { 4494 opp-peak-kBps = <2601000>; 4495 }; 4496 4497 opp-4 { 4498 opp-peak-kBps = <2929000>; 4499 }; 4500 4501 opp-5 { 4502 opp-peak-kBps = <5931000>; 4503 }; 4504 4505 opp-6 { 4506 opp-peak-kBps = <6515000>; 4507 }; 4508 4509 opp-7 { 4510 opp-peak-kBps = <7984000>; 4511 }; 4512 4513 opp-8 { 4514 opp-peak-kBps = <10437000>; 4515 }; 4516 4517 opp-9 { 4518 opp-peak-kBps = <12195000>; 4519 }; 4520 }; 4521 }; 4522 4523 pmu@90b5400 { 4524 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4525 reg = <0x0 0x90b5400 0x0 0x600>; 4526 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4527 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4528 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4529 4530 operating-points-v2 = <&cpu_bwmon_opp_table>; 4531 4532 cpu_bwmon_opp_table: opp-table { 4533 compatible = "operating-points-v2"; 4534 4535 opp-0 { 4536 opp-peak-kBps = <9155000>; 4537 }; 4538 4539 opp-1 { 4540 opp-peak-kBps = <12298000>; 4541 }; 4542 4543 opp-2 { 4544 opp-peak-kBps = <14236000>; 4545 }; 4546 4547 opp-3 { 4548 opp-peak-kBps = <16265000>; 4549 }; 4550 }; 4551 4552 }; 4553 4554 pmu@90b6400 { 4555 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4556 reg = <0x0 0x90b6400 0x0 0x600>; 4557 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4558 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4559 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4560 4561 operating-points-v2 = <&cpu_bwmon_opp_table>; 4562 }; 4563 4564 llcc: system-cache-controller@9200000 { 4565 compatible = "qcom,sa8775p-llcc"; 4566 reg = <0x0 0x09200000 0x0 0x80000>, 4567 <0x0 0x09300000 0x0 0x80000>, 4568 <0x0 0x09400000 0x0 0x80000>, 4569 <0x0 0x09500000 0x0 0x80000>, 4570 <0x0 0x09600000 0x0 0x80000>, 4571 <0x0 0x09700000 0x0 0x80000>, 4572 <0x0 0x09a00000 0x0 0x80000>; 4573 reg-names = "llcc0_base", 4574 "llcc1_base", 4575 "llcc2_base", 4576 "llcc3_base", 4577 "llcc4_base", 4578 "llcc5_base", 4579 "llcc_broadcast_base"; 4580 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 4581 }; 4582 4583 iris: video-codec@aa00000 { 4584 compatible = "qcom,sa8775p-iris", "qcom,sm8550-iris"; 4585 4586 reg = <0x0 0x0aa00000 0x0 0xf0000>; 4587 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4588 4589 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 4590 <&videocc VIDEO_CC_MVS0_GDSC>, 4591 <&rpmhpd SA8775P_MX>, 4592 <&rpmhpd SA8775P_MMCX>; 4593 power-domain-names = "venus", 4594 "vcodec0", 4595 "mxc", 4596 "mmcx"; 4597 operating-points-v2 = <&iris_opp_table>; 4598 4599 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4600 <&videocc VIDEO_CC_MVS0C_CLK>, 4601 <&videocc VIDEO_CC_MVS0_CLK>; 4602 clock-names = "iface", 4603 "core", 4604 "vcodec0_core"; 4605 4606 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4607 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4608 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4609 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4610 interconnect-names = "cpu-cfg", 4611 "video-mem"; 4612 4613 memory-region = <&pil_video_mem>; 4614 4615 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 4616 reset-names = "bus"; 4617 4618 iommus = <&apps_smmu 0x0880 0x0400>, 4619 <&apps_smmu 0x0887 0x0400>; 4620 dma-coherent; 4621 4622 status = "disabled"; 4623 4624 iris_opp_table: opp-table { 4625 compatible = "operating-points-v2"; 4626 4627 opp-366000000 { 4628 opp-hz = /bits/ 64 <366000000>; 4629 required-opps = <&rpmhpd_opp_svs_l1>, 4630 <&rpmhpd_opp_svs_l1>; 4631 }; 4632 4633 opp-444000000 { 4634 opp-hz = /bits/ 64 <444000000>; 4635 required-opps = <&rpmhpd_opp_svs_l1>, 4636 <&rpmhpd_opp_nom>; 4637 }; 4638 4639 opp-533000000 { 4640 opp-hz = /bits/ 64 <533000000>; 4641 required-opps = <&rpmhpd_opp_nom>, 4642 <&rpmhpd_opp_turbo>; 4643 }; 4644 4645 opp-560000000 { 4646 opp-hz = /bits/ 64 <560000000>; 4647 required-opps = <&rpmhpd_opp_nom>, 4648 <&rpmhpd_opp_turbo_l1>; 4649 }; 4650 }; 4651 }; 4652 4653 videocc: clock-controller@abf0000 { 4654 compatible = "qcom,sa8775p-videocc"; 4655 reg = <0x0 0x0abf0000 0x0 0x10000>; 4656 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4657 <&rpmhcc RPMH_CXO_CLK>, 4658 <&rpmhcc RPMH_CXO_CLK_A>, 4659 <&sleep_clk>; 4660 power-domains = <&rpmhpd SA8775P_MMCX>; 4661 #clock-cells = <1>; 4662 #reset-cells = <1>; 4663 #power-domain-cells = <1>; 4664 }; 4665 4666 cci0: cci@ac13000 { 4667 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4668 reg = <0x0 0x0ac13000 0x0 0x1000>; 4669 4670 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4671 4672 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4673 4674 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4675 <&camcc CAM_CC_CPAS_AHB_CLK>, 4676 <&camcc CAM_CC_CCI_0_CLK>; 4677 clock-names = "camnoc_axi", 4678 "cpas_ahb", 4679 "cci"; 4680 4681 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 4682 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 4683 pinctrl-names = "default", "sleep"; 4684 4685 #address-cells = <1>; 4686 #size-cells = <0>; 4687 4688 status = "disabled"; 4689 4690 cci0_i2c0: i2c-bus@0 { 4691 reg = <0>; 4692 clock-frequency = <1000000>; 4693 #address-cells = <1>; 4694 #size-cells = <0>; 4695 }; 4696 4697 cci0_i2c1: i2c-bus@1 { 4698 reg = <1>; 4699 clock-frequency = <1000000>; 4700 #address-cells = <1>; 4701 #size-cells = <0>; 4702 }; 4703 }; 4704 4705 cci1: cci@ac14000 { 4706 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4707 reg = <0x0 0x0ac14000 0x0 0x1000>; 4708 4709 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4710 4711 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4712 4713 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4714 <&camcc CAM_CC_CPAS_AHB_CLK>, 4715 <&camcc CAM_CC_CCI_1_CLK>; 4716 clock-names = "camnoc_axi", 4717 "cpas_ahb", 4718 "cci"; 4719 4720 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 4721 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 4722 pinctrl-names = "default", "sleep"; 4723 4724 #address-cells = <1>; 4725 #size-cells = <0>; 4726 4727 status = "disabled"; 4728 4729 cci1_i2c0: i2c-bus@0 { 4730 reg = <0>; 4731 clock-frequency = <1000000>; 4732 #address-cells = <1>; 4733 #size-cells = <0>; 4734 }; 4735 4736 cci1_i2c1: i2c-bus@1 { 4737 reg = <1>; 4738 clock-frequency = <1000000>; 4739 #address-cells = <1>; 4740 #size-cells = <0>; 4741 }; 4742 }; 4743 4744 cci2: cci@ac15000 { 4745 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4746 reg = <0x0 0x0ac15000 0x0 0x1000>; 4747 4748 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 4749 4750 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4751 4752 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4753 <&camcc CAM_CC_CPAS_AHB_CLK>, 4754 <&camcc CAM_CC_CCI_2_CLK>; 4755 clock-names = "camnoc_axi", 4756 "cpas_ahb", 4757 "cci"; 4758 4759 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 4760 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 4761 pinctrl-names = "default", "sleep"; 4762 4763 #address-cells = <1>; 4764 #size-cells = <0>; 4765 4766 status = "disabled"; 4767 4768 cci2_i2c0: i2c-bus@0 { 4769 reg = <0>; 4770 clock-frequency = <1000000>; 4771 #address-cells = <1>; 4772 #size-cells = <0>; 4773 }; 4774 4775 cci2_i2c1: i2c-bus@1 { 4776 reg = <1>; 4777 clock-frequency = <1000000>; 4778 #address-cells = <1>; 4779 #size-cells = <0>; 4780 }; 4781 }; 4782 4783 cci3: cci@ac16000 { 4784 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4785 reg = <0x0 0x0ac16000 0x0 0x1000>; 4786 4787 interrupts = <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>; 4788 4789 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4790 4791 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4792 <&camcc CAM_CC_CPAS_AHB_CLK>, 4793 <&camcc CAM_CC_CCI_3_CLK>; 4794 clock-names = "camnoc_axi", 4795 "cpas_ahb", 4796 "cci"; 4797 4798 pinctrl-0 = <&cci3_0_default &cci3_1_default>; 4799 pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>; 4800 pinctrl-names = "default", "sleep"; 4801 4802 #address-cells = <1>; 4803 #size-cells = <0>; 4804 4805 status = "disabled"; 4806 4807 cci3_i2c0: i2c-bus@0 { 4808 reg = <0>; 4809 clock-frequency = <1000000>; 4810 #address-cells = <1>; 4811 #size-cells = <0>; 4812 }; 4813 4814 cci3_i2c1: i2c-bus@1 { 4815 reg = <1>; 4816 clock-frequency = <1000000>; 4817 #address-cells = <1>; 4818 #size-cells = <0>; 4819 }; 4820 }; 4821 4822 camss: isp@ac78000 { 4823 compatible = "qcom,sa8775p-camss"; 4824 4825 reg = <0x0 0xac78000 0x0 0x1000>, 4826 <0x0 0xac7a000 0x0 0x0f00>, 4827 <0x0 0xac7c000 0x0 0x0f00>, 4828 <0x0 0xac84000 0x0 0x0f00>, 4829 <0x0 0xac88000 0x0 0x0f00>, 4830 <0x0 0xac8c000 0x0 0x0f00>, 4831 <0x0 0xac90000 0x0 0x0f00>, 4832 <0x0 0xac94000 0x0 0x0f00>, 4833 <0x0 0xac9c000 0x0 0x2000>, 4834 <0x0 0xac9e000 0x0 0x2000>, 4835 <0x0 0xaca0000 0x0 0x2000>, 4836 <0x0 0xaca2000 0x0 0x2000>, 4837 <0x0 0xacac000 0x0 0x0400>, 4838 <0x0 0xacad000 0x0 0x0400>, 4839 <0x0 0xacae000 0x0 0x0400>, 4840 <0x0 0xac4d000 0x0 0xd000>, 4841 <0x0 0xac5a000 0x0 0xd000>, 4842 <0x0 0xac85000 0x0 0x0d00>, 4843 <0x0 0xac89000 0x0 0x0d00>, 4844 <0x0 0xac8d000 0x0 0x0d00>, 4845 <0x0 0xac91000 0x0 0x0d00>, 4846 <0x0 0xac95000 0x0 0x0d00>; 4847 reg-names = "csid_wrapper", 4848 "csid0", 4849 "csid1", 4850 "csid_lite0", 4851 "csid_lite1", 4852 "csid_lite2", 4853 "csid_lite3", 4854 "csid_lite4", 4855 "csiphy0", 4856 "csiphy1", 4857 "csiphy2", 4858 "csiphy3", 4859 "tpg0", 4860 "tpg1", 4861 "tpg2", 4862 "vfe0", 4863 "vfe1", 4864 "vfe_lite0", 4865 "vfe_lite1", 4866 "vfe_lite2", 4867 "vfe_lite3", 4868 "vfe_lite4"; 4869 4870 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4871 <&camcc CAM_CC_CORE_AHB_CLK>, 4872 <&camcc CAM_CC_CPAS_AHB_CLK>, 4873 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 4874 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 4875 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 4876 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 4877 <&camcc CAM_CC_CSID_CLK>, 4878 <&camcc CAM_CC_CSIPHY0_CLK>, 4879 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4880 <&camcc CAM_CC_CSIPHY1_CLK>, 4881 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4882 <&camcc CAM_CC_CSIPHY2_CLK>, 4883 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4884 <&camcc CAM_CC_CSIPHY3_CLK>, 4885 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4886 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 4887 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4888 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4889 <&camcc CAM_CC_ICP_AHB_CLK>, 4890 <&camcc CAM_CC_IFE_0_CLK>, 4891 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 4892 <&camcc CAM_CC_IFE_1_CLK>, 4893 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 4894 <&camcc CAM_CC_IFE_LITE_CLK>, 4895 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4896 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4897 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4898 clock-names = "camnoc_axi", 4899 "core_ahb", 4900 "cpas_ahb", 4901 "cpas_fast_ahb_clk", 4902 "cpas_vfe_lite", 4903 "cpas_vfe0", 4904 "cpas_vfe1", 4905 "csid", 4906 "csiphy0", 4907 "csiphy0_timer", 4908 "csiphy1", 4909 "csiphy1_timer", 4910 "csiphy2", 4911 "csiphy2_timer", 4912 "csiphy3", 4913 "csiphy3_timer", 4914 "csiphy_rx", 4915 "gcc_axi_hf", 4916 "gcc_axi_sf", 4917 "icp_ahb", 4918 "vfe0", 4919 "vfe0_fast_ahb", 4920 "vfe1", 4921 "vfe1_fast_ahb", 4922 "vfe_lite", 4923 "vfe_lite_ahb", 4924 "vfe_lite_cphy_rx", 4925 "vfe_lite_csid"; 4926 4927 interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, 4928 <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, 4929 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4930 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4931 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 4932 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 4933 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 4934 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4935 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4936 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4937 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4938 <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, 4939 <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, 4940 <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, 4941 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4942 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4943 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4944 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 4945 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 4946 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 4947 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; 4948 interrupt-names = "csid0", 4949 "csid1", 4950 "csid_lite0", 4951 "csid_lite1", 4952 "csid_lite2", 4953 "csid_lite3", 4954 "csid_lite4", 4955 "csiphy0", 4956 "csiphy1", 4957 "csiphy2", 4958 "csiphy3", 4959 "tpg0", 4960 "tpg1", 4961 "tpg2", 4962 "vfe0", 4963 "vfe1", 4964 "vfe_lite0", 4965 "vfe_lite1", 4966 "vfe_lite2", 4967 "vfe_lite3", 4968 "vfe_lite4"; 4969 4970 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4971 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4972 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 4973 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4974 interconnect-names = "ahb", 4975 "hf_0"; 4976 4977 iommus = <&apps_smmu 0x3400 0x20>; 4978 4979 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4980 power-domain-names = "top"; 4981 4982 status = "disabled"; 4983 4984 ports { 4985 #address-cells = <1>; 4986 #size-cells = <0>; 4987 4988 port@0 { 4989 reg = <0>; 4990 }; 4991 4992 port@1 { 4993 reg = <1>; 4994 }; 4995 4996 port@2 { 4997 reg = <2>; 4998 }; 4999 5000 port@3 { 5001 reg = <3>; 5002 }; 5003 }; 5004 }; 5005 5006 camcc: clock-controller@ade0000 { 5007 compatible = "qcom,sa8775p-camcc"; 5008 reg = <0x0 0x0ade0000 0x0 0x20000>; 5009 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5010 <&rpmhcc RPMH_CXO_CLK>, 5011 <&rpmhcc RPMH_CXO_CLK_A>, 5012 <&sleep_clk>; 5013 power-domains = <&rpmhpd SA8775P_MMCX>; 5014 #clock-cells = <1>; 5015 #reset-cells = <1>; 5016 #power-domain-cells = <1>; 5017 }; 5018 5019 mdss0: display-subsystem@ae00000 { 5020 compatible = "qcom,sa8775p-mdss"; 5021 reg = <0x0 0x0ae00000 0x0 0x1000>; 5022 reg-names = "mdss"; 5023 5024 /* same path used twice */ 5025 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 5026 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5027 <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS 5028 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5029 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5030 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5031 interconnect-names = "mdp0-mem", 5032 "mdp1-mem", 5033 "cpu-cfg"; 5034 5035 resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; 5036 5037 power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; 5038 5039 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5040 <&gcc GCC_DISP_HF_AXI_CLK>, 5041 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; 5042 5043 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 5044 interrupt-controller; 5045 #interrupt-cells = <1>; 5046 5047 iommus = <&apps_smmu 0x1000 0x402>; 5048 5049 #address-cells = <2>; 5050 #size-cells = <2>; 5051 ranges; 5052 5053 status = "disabled"; 5054 5055 mdss0_mdp: display-controller@ae01000 { 5056 compatible = "qcom,sa8775p-dpu"; 5057 reg = <0x0 0x0ae01000 0x0 0x8f000>, 5058 <0x0 0x0aeb0000 0x0 0x3000>; 5059 reg-names = "mdp", "vbif"; 5060 5061 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5062 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5063 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 5064 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, 5065 <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5066 clock-names = "nrt_bus", 5067 "iface", 5068 "lut", 5069 "core", 5070 "vsync"; 5071 5072 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5073 assigned-clock-rates = <19200000>; 5074 5075 operating-points-v2 = <&mdss0_mdp_opp_table>; 5076 power-domains = <&rpmhpd SA8775P_MMCX>; 5077 5078 interrupt-parent = <&mdss0>; 5079 interrupts = <0>; 5080 5081 ports { 5082 #address-cells = <1>; 5083 #size-cells = <0>; 5084 5085 port@0 { 5086 reg = <0>; 5087 5088 dpu_intf0_out: endpoint { 5089 remote-endpoint = <&mdss0_dp0_in>; 5090 }; 5091 }; 5092 5093 port@1 { 5094 reg = <1>; 5095 5096 dpu_intf4_out: endpoint { 5097 remote-endpoint = <&mdss0_dp1_in>; 5098 }; 5099 }; 5100 5101 port@2 { 5102 reg = <2>; 5103 5104 dpu_intf1_out: endpoint { 5105 remote-endpoint = <&mdss0_dsi0_in>; 5106 }; 5107 }; 5108 5109 port@3 { 5110 reg = <3>; 5111 5112 dpu_intf2_out: endpoint { 5113 remote-endpoint = <&mdss0_dsi1_in>; 5114 }; 5115 }; 5116 }; 5117 5118 mdss0_mdp_opp_table: opp-table { 5119 compatible = "operating-points-v2"; 5120 5121 opp-375000000 { 5122 opp-hz = /bits/ 64 <375000000>; 5123 required-opps = <&rpmhpd_opp_svs_l1>; 5124 }; 5125 5126 opp-500000000 { 5127 opp-hz = /bits/ 64 <500000000>; 5128 required-opps = <&rpmhpd_opp_nom>; 5129 }; 5130 5131 opp-575000000 { 5132 opp-hz = /bits/ 64 <575000000>; 5133 required-opps = <&rpmhpd_opp_turbo>; 5134 }; 5135 5136 opp-650000000 { 5137 opp-hz = /bits/ 64 <650000000>; 5138 required-opps = <&rpmhpd_opp_turbo_l1>; 5139 }; 5140 }; 5141 }; 5142 5143 mdss0_dsi0: dsi@ae94000 { 5144 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5145 reg = <0x0 0x0ae94000 0x0 0x400>; 5146 reg-names = "dsi_ctrl"; 5147 5148 interrupt-parent = <&mdss0>; 5149 interrupts = <4>; 5150 5151 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK>, 5152 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, 5153 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK>, 5154 <&dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK>, 5155 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5156 <&gcc GCC_DISP_HF_AXI_CLK>; 5157 clock-names = "byte", 5158 "byte_intf", 5159 "pixel", 5160 "core", 5161 "iface", 5162 "bus"; 5163 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, 5164 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; 5165 assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 5166 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; 5167 phys = <&mdss0_dsi0_phy>; 5168 5169 operating-points-v2 = <&mdss_dsi_opp_table>; 5170 power-domains = <&rpmhpd SA8775P_MMCX>; 5171 5172 refgen-supply = <&refgen>; 5173 5174 #address-cells = <1>; 5175 #size-cells = <0>; 5176 5177 status = "disabled"; 5178 5179 ports { 5180 #address-cells = <1>; 5181 #size-cells = <0>; 5182 5183 port@0 { 5184 reg = <0>; 5185 5186 mdss0_dsi0_in: endpoint { 5187 remote-endpoint = <&dpu_intf1_out>; 5188 }; 5189 }; 5190 5191 port@1 { 5192 reg = <1>; 5193 5194 mdss0_dsi0_out: endpoint { }; 5195 }; 5196 }; 5197 5198 mdss_dsi_opp_table: opp-table { 5199 compatible = "operating-points-v2"; 5200 5201 opp-358000000 { 5202 opp-hz = /bits/ 64 <358000000>; 5203 required-opps = <&rpmhpd_opp_svs_l1>; 5204 }; 5205 }; 5206 }; 5207 5208 mdss0_dsi0_phy: phy@ae94400 { 5209 compatible = "qcom,sa8775p-dsi-phy-5nm"; 5210 reg = <0x0 0x0ae94400 0x0 0x200>, 5211 <0x0 0x0ae94600 0x0 0x280>, 5212 <0x0 0x0ae94900 0x0 0x27c>; 5213 reg-names = "dsi_phy", 5214 "dsi_phy_lane", 5215 "dsi_pll"; 5216 5217 #clock-cells = <1>; 5218 #phy-cells = <0>; 5219 5220 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5221 <&rpmhcc RPMH_CXO_CLK>; 5222 clock-names = "iface", "ref"; 5223 5224 status = "disabled"; 5225 }; 5226 5227 mdss0_dsi1: dsi@ae96000 { 5228 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5229 reg = <0x0 0x0ae96000 0x0 0x400>; 5230 reg-names = "dsi_ctrl"; 5231 5232 interrupt-parent = <&mdss0>; 5233 interrupts = <5>; 5234 5235 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK>, 5236 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK>, 5237 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK>, 5238 <&dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK>, 5239 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5240 <&gcc GCC_DISP_HF_AXI_CLK>; 5241 clock-names = "byte", 5242 "byte_intf", 5243 "pixel", 5244 "core", 5245 "iface", 5246 "bus"; 5247 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>, 5248 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC>; 5249 assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5250 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5251 phys = <&mdss0_dsi1_phy>; 5252 5253 operating-points-v2 = <&mdss_dsi_opp_table>; 5254 power-domains = <&rpmhpd SA8775P_MMCX>; 5255 5256 refgen-supply = <&refgen>; 5257 5258 #address-cells = <1>; 5259 #size-cells = <0>; 5260 5261 status = "disabled"; 5262 5263 ports { 5264 #address-cells = <1>; 5265 #size-cells = <0>; 5266 5267 port@0 { 5268 reg = <0>; 5269 5270 mdss0_dsi1_in: endpoint { 5271 remote-endpoint = <&dpu_intf2_out>; 5272 }; 5273 }; 5274 5275 port@1 { 5276 reg = <1>; 5277 5278 mdss0_dsi1_out: endpoint { }; 5279 }; 5280 }; 5281 }; 5282 5283 mdss0_dsi1_phy: phy@ae96400 { 5284 compatible = "qcom,sa8775p-dsi-phy-5nm"; 5285 reg = <0x0 0x0ae96400 0x0 0x200>, 5286 <0x0 0x0ae96600 0x0 0x280>, 5287 <0x0 0x0ae96900 0x0 0x27c>; 5288 reg-names = "dsi_phy", 5289 "dsi_phy_lane", 5290 "dsi_pll"; 5291 5292 #clock-cells = <1>; 5293 #phy-cells = <0>; 5294 5295 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5296 <&rpmhcc RPMH_CXO_CLK>; 5297 clock-names = "iface", "ref"; 5298 5299 status = "disabled"; 5300 }; 5301 5302 mdss0_dp0_phy: phy@aec2a00 { 5303 compatible = "qcom,sa8775p-edp-phy"; 5304 5305 reg = <0x0 0x0aec2a00 0x0 0x200>, 5306 <0x0 0x0aec2200 0x0 0xd0>, 5307 <0x0 0x0aec2600 0x0 0xd0>, 5308 <0x0 0x0aec2000 0x0 0x1c8>; 5309 5310 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5311 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; 5312 clock-names = "aux", 5313 "cfg_ahb"; 5314 5315 #clock-cells = <1>; 5316 #phy-cells = <0>; 5317 5318 status = "disabled"; 5319 }; 5320 5321 mdss0_dp1_phy: phy@aec5a00 { 5322 compatible = "qcom,sa8775p-edp-phy"; 5323 5324 reg = <0x0 0x0aec5a00 0x0 0x200>, 5325 <0x0 0x0aec5200 0x0 0xd0>, 5326 <0x0 0x0aec5600 0x0 0xd0>, 5327 <0x0 0x0aec5000 0x0 0x1c8>; 5328 5329 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 5330 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; 5331 clock-names = "aux", 5332 "cfg_ahb"; 5333 5334 #clock-cells = <1>; 5335 #phy-cells = <0>; 5336 5337 status = "disabled"; 5338 }; 5339 5340 mdss0_dp0: displayport-controller@af54000 { 5341 compatible = "qcom,sa8775p-dp"; 5342 5343 reg = <0x0 0x0af54000 0x0 0x104>, 5344 <0x0 0x0af54200 0x0 0x0c0>, 5345 <0x0 0x0af55000 0x0 0x770>, 5346 <0x0 0x0af56000 0x0 0x09c>, 5347 <0x0 0x0af57000 0x0 0x09c>, 5348 <0x0 0x0af58000 0x0 0x09c>, 5349 <0x0 0x0af59000 0x0 0x09c>, 5350 <0x0 0x0af5a000 0x0 0x23c>, 5351 <0x0 0x0af5b000 0x0 0x23c>; 5352 5353 interrupt-parent = <&mdss0>; 5354 interrupts = <12>; 5355 5356 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5357 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5358 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 5359 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5360 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5361 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, 5362 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, 5363 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; 5364 clock-names = "core_iface", 5365 "core_aux", 5366 "ctrl_link", 5367 "ctrl_link_iface", 5368 "stream_pixel", 5369 "stream_1_pixel", 5370 "stream_2_pixel", 5371 "stream_3_pixel"; 5372 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5373 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5374 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, 5375 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, 5376 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; 5377 assigned-clock-parents = <&mdss0_dp0_phy 0>, 5378 <&mdss0_dp0_phy 1>, 5379 <&mdss0_dp0_phy 1>, 5380 <&mdss0_dp0_phy 1>, 5381 <&mdss0_dp0_phy 1>; 5382 phys = <&mdss0_dp0_phy>; 5383 phy-names = "dp"; 5384 5385 operating-points-v2 = <&dp_opp_table>; 5386 power-domains = <&rpmhpd SA8775P_MMCX>; 5387 5388 #sound-dai-cells = <0>; 5389 5390 status = "disabled"; 5391 5392 ports { 5393 #address-cells = <1>; 5394 #size-cells = <0>; 5395 5396 port@0 { 5397 reg = <0>; 5398 5399 mdss0_dp0_in: endpoint { 5400 remote-endpoint = <&dpu_intf0_out>; 5401 }; 5402 }; 5403 5404 port@1 { 5405 reg = <1>; 5406 5407 mdss0_dp0_out: endpoint { }; 5408 }; 5409 }; 5410 5411 dp_opp_table: opp-table { 5412 compatible = "operating-points-v2"; 5413 5414 opp-162000000 { 5415 opp-hz = /bits/ 64 <162000000>; 5416 required-opps = <&rpmhpd_opp_low_svs>; 5417 }; 5418 5419 opp-270000000 { 5420 opp-hz = /bits/ 64 <270000000>; 5421 required-opps = <&rpmhpd_opp_svs>; 5422 }; 5423 5424 opp-540000000 { 5425 opp-hz = /bits/ 64 <540000000>; 5426 required-opps = <&rpmhpd_opp_svs_l1>; 5427 }; 5428 5429 opp-810000000 { 5430 opp-hz = /bits/ 64 <810000000>; 5431 required-opps = <&rpmhpd_opp_nom>; 5432 }; 5433 }; 5434 }; 5435 5436 mdss0_dp1: displayport-controller@af5c000 { 5437 compatible = "qcom,sa8775p-dp"; 5438 5439 reg = <0x0 0x0af5c000 0x0 0x104>, 5440 <0x0 0x0af5c200 0x0 0x0c0>, 5441 <0x0 0x0af5d000 0x0 0x770>, 5442 <0x0 0x0af5e000 0x0 0x09c>, 5443 <0x0 0x0af5f000 0x0 0x09c>, 5444 <0x0 0x0af60000 0x0 0x09c>, 5445 <0x0 0x0af61000 0x0 0x09c>, 5446 <0x0 0x0af62000 0x0 0x23c>, 5447 <0x0 0x0af63000 0x0 0x23c>; 5448 5449 interrupt-parent = <&mdss0>; 5450 interrupts = <13>; 5451 5452 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5453 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 5454 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, 5455 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5456 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5457 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5458 clock-names = "core_iface", 5459 "core_aux", 5460 "ctrl_link", 5461 "ctrl_link_iface", 5462 "stream_pixel", 5463 "stream_1_pixel"; 5464 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5465 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5466 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5467 assigned-clock-parents = <&mdss0_dp1_phy 0>, 5468 <&mdss0_dp1_phy 1>, 5469 <&mdss0_dp1_phy 1>; 5470 phys = <&mdss0_dp1_phy>; 5471 phy-names = "dp"; 5472 5473 operating-points-v2 = <&dp1_opp_table>; 5474 power-domains = <&rpmhpd SA8775P_MMCX>; 5475 5476 #sound-dai-cells = <0>; 5477 5478 status = "disabled"; 5479 5480 ports { 5481 #address-cells = <1>; 5482 #size-cells = <0>; 5483 5484 port@0 { 5485 reg = <0>; 5486 5487 mdss0_dp1_in: endpoint { 5488 remote-endpoint = <&dpu_intf4_out>; 5489 }; 5490 }; 5491 5492 port@1 { 5493 reg = <1>; 5494 5495 mdss0_dp1_out: endpoint { }; 5496 }; 5497 }; 5498 5499 dp1_opp_table: opp-table { 5500 compatible = "operating-points-v2"; 5501 5502 opp-162000000 { 5503 opp-hz = /bits/ 64 <162000000>; 5504 required-opps = <&rpmhpd_opp_low_svs>; 5505 }; 5506 5507 opp-270000000 { 5508 opp-hz = /bits/ 64 <270000000>; 5509 required-opps = <&rpmhpd_opp_svs>; 5510 }; 5511 5512 opp-540000000 { 5513 opp-hz = /bits/ 64 <540000000>; 5514 required-opps = <&rpmhpd_opp_svs_l1>; 5515 }; 5516 5517 opp-810000000 { 5518 opp-hz = /bits/ 64 <810000000>; 5519 required-opps = <&rpmhpd_opp_nom>; 5520 }; 5521 }; 5522 }; 5523 }; 5524 5525 dispcc0: clock-controller@af00000 { 5526 compatible = "qcom,sa8775p-dispcc0"; 5527 reg = <0x0 0x0af00000 0x0 0x20000>; 5528 clocks = <&gcc GCC_DISP_AHB_CLK>, 5529 <&rpmhcc RPMH_CXO_CLK>, 5530 <&rpmhcc RPMH_CXO_CLK_A>, 5531 <&sleep_clk>, 5532 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, 5533 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>, 5534 <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 5535 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, 5536 <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5537 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5538 power-domains = <&rpmhpd SA8775P_MMCX>; 5539 #clock-cells = <1>; 5540 #reset-cells = <1>; 5541 #power-domain-cells = <1>; 5542 }; 5543 5544 pdc: interrupt-controller@b220000 { 5545 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 5546 reg = <0x0 0x0b220000 0x0 0x30000>, 5547 <0x0 0x17c000f0 0x0 0x64>; 5548 qcom,pdc-ranges = <0 480 40>, 5549 <40 140 14>, 5550 <54 263 1>, 5551 <55 306 4>, 5552 <59 312 3>, 5553 <62 374 2>, 5554 <64 434 2>, 5555 <66 438 2>, 5556 <70 520 1>, 5557 <73 523 1>, 5558 <118 568 6>, 5559 <124 609 3>, 5560 <159 638 1>, 5561 <160 720 3>, 5562 <169 728 30>, 5563 <199 416 2>, 5564 <201 449 1>, 5565 <202 89 1>, 5566 <203 451 1>, 5567 <204 462 1>, 5568 <205 264 1>, 5569 <206 579 1>, 5570 <207 653 1>, 5571 <208 656 1>, 5572 <209 659 1>, 5573 <210 122 1>, 5574 <211 699 1>, 5575 <212 705 1>, 5576 <213 450 1>, 5577 <214 643 2>, 5578 <216 646 5>, 5579 <221 390 5>, 5580 <226 700 2>, 5581 <228 440 1>, 5582 <229 663 1>, 5583 <230 524 2>, 5584 <232 612 3>, 5585 <235 723 5>; 5586 #interrupt-cells = <2>; 5587 interrupt-parent = <&intc>; 5588 interrupt-controller; 5589 }; 5590 5591 tsens2: thermal-sensor@c251000 { 5592 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5593 reg = <0x0 0x0c251000 0x0 0x1ff>, 5594 <0x0 0x0c224000 0x0 0x8>; 5595 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 5596 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 5597 #qcom,sensors = <13>; 5598 interrupt-names = "uplow", "critical"; 5599 #thermal-sensor-cells = <1>; 5600 }; 5601 5602 tsens3: thermal-sensor@c252000 { 5603 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5604 reg = <0x0 0x0c252000 0x0 0x1ff>, 5605 <0x0 0x0c225000 0x0 0x8>; 5606 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 5607 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 5608 #qcom,sensors = <13>; 5609 interrupt-names = "uplow", "critical"; 5610 #thermal-sensor-cells = <1>; 5611 }; 5612 5613 tsens0: thermal-sensor@c263000 { 5614 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5615 reg = <0x0 0x0c263000 0x0 0x1ff>, 5616 <0x0 0x0c222000 0x0 0x8>; 5617 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5618 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5619 #qcom,sensors = <12>; 5620 interrupt-names = "uplow", "critical"; 5621 #thermal-sensor-cells = <1>; 5622 }; 5623 5624 tsens1: thermal-sensor@c265000 { 5625 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5626 reg = <0x0 0x0c265000 0x0 0x1ff>, 5627 <0x0 0x0c223000 0x0 0x8>; 5628 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5629 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5630 #qcom,sensors = <12>; 5631 interrupt-names = "uplow", "critical"; 5632 #thermal-sensor-cells = <1>; 5633 }; 5634 5635 aoss_qmp: power-management@c300000 { 5636 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 5637 reg = <0x0 0x0c300000 0x0 0x400>; 5638 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5639 IPCC_MPROC_SIGNAL_GLINK_QMP 5640 IRQ_TYPE_EDGE_RISING>; 5641 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5642 #clock-cells = <0>; 5643 }; 5644 5645 sram@c3f0000 { 5646 compatible = "qcom,rpmh-stats"; 5647 reg = <0x0 0x0c3f0000 0x0 0x400>; 5648 }; 5649 5650 spmi_bus: spmi@c440000 { 5651 compatible = "qcom,spmi-pmic-arb"; 5652 reg = <0x0 0x0c440000 0x0 0x1100>, 5653 <0x0 0x0c600000 0x0 0x2000000>, 5654 <0x0 0x0e600000 0x0 0x100000>, 5655 <0x0 0x0e700000 0x0 0xa0000>, 5656 <0x0 0x0c40a000 0x0 0x26000>; 5657 reg-names = "core", 5658 "chnls", 5659 "obsrvr", 5660 "intr", 5661 "cnfg"; 5662 qcom,channel = <0>; 5663 qcom,ee = <0>; 5664 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5665 interrupt-names = "periph_irq"; 5666 interrupt-controller; 5667 #interrupt-cells = <4>; 5668 #address-cells = <2>; 5669 #size-cells = <0>; 5670 }; 5671 5672 tlmm: pinctrl@f000000 { 5673 compatible = "qcom,sa8775p-tlmm"; 5674 reg = <0x0 0x0f000000 0x0 0x1000000>; 5675 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5676 gpio-controller; 5677 #gpio-cells = <2>; 5678 interrupt-controller; 5679 #interrupt-cells = <2>; 5680 gpio-ranges = <&tlmm 0 0 149>; 5681 wakeup-parent = <&pdc>; 5682 5683 dp0_hot_plug_det: dp0-hot-plug-det-state { 5684 pins = "gpio101"; 5685 function = "edp0_hot"; 5686 bias-disable; 5687 }; 5688 5689 dp1_hot_plug_det: dp1-hot-plug-det-state { 5690 pins = "gpio102"; 5691 function = "edp1_hot"; 5692 bias-disable; 5693 }; 5694 5695 hs0_mi2s_active: hs0-mi2s-active-state { 5696 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 5697 function = "hs0_mi2s"; 5698 drive-strength = <8>; 5699 bias-disable; 5700 }; 5701 5702 hs2_mi2s_active: hs2-mi2s-active-state { 5703 pins = "gpio122", "gpio123", "gpio124", "gpio125"; 5704 function = "hs2_mi2s"; 5705 drive-strength = <8>; 5706 bias-disable; 5707 }; 5708 5709 cci0_0_default: cci0-0-default-state { 5710 pins = "gpio60", "gpio61"; 5711 function = "cci_i2c"; 5712 drive-strength = <2>; 5713 bias-pull-up = <2200>; 5714 }; 5715 5716 cci0_0_sleep: cci0-0-sleep-state { 5717 pins = "gpio60", "gpio61"; 5718 function = "cci_i2c"; 5719 drive-strength = <2>; 5720 bias-pull-down; 5721 }; 5722 5723 cci0_1_default: cci0-1-default-state { 5724 pins = "gpio52", "gpio53"; 5725 function = "cci_i2c"; 5726 drive-strength = <2>; 5727 bias-pull-up = <2200>; 5728 }; 5729 5730 cci0_1_sleep: cci0-1-sleep-state { 5731 pins = "gpio52", "gpio53"; 5732 function = "cci_i2c"; 5733 drive-strength = <2>; 5734 bias-pull-down; 5735 }; 5736 5737 cci1_0_default: cci1-0-default-state { 5738 pins = "gpio62", "gpio63"; 5739 function = "cci_i2c"; 5740 drive-strength = <2>; 5741 bias-pull-up = <2200>; 5742 }; 5743 5744 cci1_0_sleep: cci1-0-sleep-state { 5745 pins = "gpio62", "gpio63"; 5746 function = "cci_i2c"; 5747 drive-strength = <2>; 5748 bias-pull-down; 5749 }; 5750 5751 cci1_1_default: cci1-1-default-state { 5752 pins = "gpio54", "gpio55"; 5753 function = "cci_i2c"; 5754 drive-strength = <2>; 5755 bias-pull-up = <2200>; 5756 }; 5757 5758 cci1_1_sleep: cci1-1-sleep-state { 5759 pins = "gpio54", "gpio55"; 5760 function = "cci_i2c"; 5761 drive-strength = <2>; 5762 bias-pull-down; 5763 }; 5764 5765 cci2_0_default: cci2-0-default-state { 5766 pins = "gpio64", "gpio65"; 5767 function = "cci_i2c"; 5768 drive-strength = <2>; 5769 bias-pull-up = <2200>; 5770 }; 5771 5772 cci2_0_sleep: cci2-0-sleep-state { 5773 pins = "gpio64", "gpio65"; 5774 function = "cci_i2c"; 5775 drive-strength = <2>; 5776 bias-pull-down; 5777 }; 5778 5779 cci2_1_default: cci2-1-default-state { 5780 pins = "gpio56", "gpio57"; 5781 function = "cci_i2c"; 5782 drive-strength = <2>; 5783 bias-pull-up = <2200>; 5784 }; 5785 5786 cci2_1_sleep: cci2-1-sleep-state { 5787 pins = "gpio56", "gpio57"; 5788 function = "cci_i2c"; 5789 drive-strength = <2>; 5790 bias-pull-down; 5791 }; 5792 5793 cci3_0_default: cci3-0-default-state { 5794 pins = "gpio66", "gpio67"; 5795 function = "cci_i2c"; 5796 drive-strength = <2>; 5797 bias-pull-up = <2200>; 5798 }; 5799 5800 cci3_0_sleep: cci3-0-sleep-state { 5801 pins = "gpio66", "gpio67"; 5802 function = "cci_i2c"; 5803 drive-strength = <2>; 5804 bias-pull-down; 5805 }; 5806 5807 cci3_1_default: cci3-1-default-state { 5808 pins = "gpio58", "gpio59"; 5809 function = "cci_i2c"; 5810 drive-strength = <2>; 5811 bias-pull-up = <2200>; 5812 }; 5813 5814 cci3_1_sleep: cci3-1-sleep-state { 5815 pins = "gpio58", "gpio59"; 5816 function = "cci_i2c"; 5817 drive-strength = <2>; 5818 bias-pull-down; 5819 }; 5820 5821 qup_i2c0_default: qup-i2c0-state { 5822 pins = "gpio20", "gpio21"; 5823 function = "qup0_se0"; 5824 }; 5825 5826 qup_i2c1_default: qup-i2c1-state { 5827 pins = "gpio24", "gpio25"; 5828 function = "qup0_se1"; 5829 }; 5830 5831 qup_i2c2_default: qup-i2c2-state { 5832 pins = "gpio36", "gpio37"; 5833 function = "qup0_se2"; 5834 }; 5835 5836 qup_i2c3_default: qup-i2c3-state { 5837 pins = "gpio28", "gpio29"; 5838 function = "qup0_se3"; 5839 }; 5840 5841 qup_i2c4_default: qup-i2c4-state { 5842 pins = "gpio32", "gpio33"; 5843 function = "qup0_se4"; 5844 }; 5845 5846 qup_i2c5_default: qup-i2c5-state { 5847 pins = "gpio36", "gpio37"; 5848 function = "qup0_se5"; 5849 }; 5850 5851 qup_i2c7_default: qup-i2c7-state { 5852 pins = "gpio40", "gpio41"; 5853 function = "qup1_se0"; 5854 }; 5855 5856 qup_i2c8_default: qup-i2c8-state { 5857 pins = "gpio42", "gpio43"; 5858 function = "qup1_se1"; 5859 }; 5860 5861 qup_i2c9_default: qup-i2c9-state { 5862 pins = "gpio46", "gpio47"; 5863 function = "qup1_se2"; 5864 }; 5865 5866 qup_i2c10_default: qup-i2c10-state { 5867 pins = "gpio44", "gpio45"; 5868 function = "qup1_se3"; 5869 }; 5870 5871 qup_i2c11_default: qup-i2c11-state { 5872 pins = "gpio48", "gpio49"; 5873 function = "qup1_se4"; 5874 }; 5875 5876 qup_i2c12_default: qup-i2c12-state { 5877 pins = "gpio52", "gpio53"; 5878 function = "qup1_se5"; 5879 }; 5880 5881 qup_i2c13_default: qup-i2c13-state { 5882 pins = "gpio56", "gpio57"; 5883 function = "qup1_se6"; 5884 }; 5885 5886 qup_i2c14_default: qup-i2c14-state { 5887 pins = "gpio80", "gpio81"; 5888 function = "qup2_se0"; 5889 }; 5890 5891 qup_i2c15_default: qup-i2c15-state { 5892 pins = "gpio84", "gpio85"; 5893 function = "qup2_se1"; 5894 }; 5895 5896 qup_i2c16_default: qup-i2c16-state { 5897 pins = "gpio86", "gpio87"; 5898 function = "qup2_se2"; 5899 }; 5900 5901 qup_i2c17_default: qup-i2c17-state { 5902 pins = "gpio91", "gpio92"; 5903 function = "qup2_se3"; 5904 }; 5905 5906 qup_i2c18_default: qup-i2c18-state { 5907 pins = "gpio95", "gpio96"; 5908 function = "qup2_se4"; 5909 }; 5910 5911 qup_i2c19_default: qup-i2c19-state { 5912 pins = "gpio99", "gpio100"; 5913 function = "qup2_se5"; 5914 }; 5915 5916 qup_i2c20_default: qup-i2c20-state { 5917 pins = "gpio97", "gpio98"; 5918 function = "qup2_se6"; 5919 }; 5920 5921 qup_i2c21_default: qup-i2c21-state { 5922 pins = "gpio13", "gpio14"; 5923 function = "qup3_se0"; 5924 }; 5925 5926 qup_spi0_default: qup-spi0-state { 5927 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 5928 function = "qup0_se0"; 5929 }; 5930 5931 qup_spi1_default: qup-spi1-state { 5932 pins = "gpio24", "gpio25", "gpio26", "gpio27"; 5933 function = "qup0_se1"; 5934 }; 5935 5936 qup_spi2_default: qup-spi2-state { 5937 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 5938 function = "qup0_se2"; 5939 }; 5940 5941 qup_spi3_default: qup-spi3-state { 5942 pins = "gpio28", "gpio29", "gpio30", "gpio31"; 5943 function = "qup0_se3"; 5944 }; 5945 5946 qup_spi4_default: qup-spi4-state { 5947 pins = "gpio32", "gpio33", "gpio34", "gpio35"; 5948 function = "qup0_se4"; 5949 }; 5950 5951 qup_spi5_default: qup-spi5-state { 5952 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 5953 function = "qup0_se5"; 5954 }; 5955 5956 qup_spi7_default: qup-spi7-state { 5957 pins = "gpio40", "gpio41", "gpio42", "gpio43"; 5958 function = "qup1_se0"; 5959 }; 5960 5961 qup_spi8_default: qup-spi8-state { 5962 pins = "gpio42", "gpio43", "gpio40", "gpio41"; 5963 function = "qup1_se1"; 5964 }; 5965 5966 qup_spi9_default: qup-spi9-state { 5967 pins = "gpio46", "gpio47", "gpio44", "gpio45"; 5968 function = "qup1_se2"; 5969 }; 5970 5971 qup_spi10_default: qup-spi10-state { 5972 pins = "gpio44", "gpio45", "gpio46", "gpio47"; 5973 function = "qup1_se3"; 5974 }; 5975 5976 qup_spi11_default: qup-spi11-state { 5977 pins = "gpio48", "gpio49", "gpio50", "gpio51"; 5978 function = "qup1_se4"; 5979 }; 5980 5981 qup_spi12_default: qup-spi12-state { 5982 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5983 function = "qup1_se5"; 5984 }; 5985 5986 qup_spi14_default: qup-spi14-state { 5987 pins = "gpio80", "gpio81", "gpio82", "gpio83"; 5988 function = "qup2_se0"; 5989 }; 5990 5991 qup_spi15_default: qup-spi15-state { 5992 pins = "gpio84", "gpio85", "gpio99", "gpio100"; 5993 function = "qup2_se1"; 5994 }; 5995 5996 qup_spi16_default: qup-spi16-state { 5997 pins = "gpio86", "gpio87", "gpio88", "gpio89"; 5998 function = "qup2_se2"; 5999 }; 6000 6001 qup_spi17_default: qup-spi17-state { 6002 pins = "gpio91", "gpio92", "gpio93", "gpio94"; 6003 function = "qup2_se3"; 6004 }; 6005 6006 qup_spi18_default: qup-spi18-state { 6007 pins = "gpio95", "gpio96", "gpio97", "gpio98"; 6008 function = "qup2_se4"; 6009 }; 6010 6011 qup_spi19_default: qup-spi19-state { 6012 pins = "gpio99", "gpio100", "gpio84", "gpio85"; 6013 function = "qup2_se5"; 6014 }; 6015 6016 qup_spi20_default: qup-spi20-state { 6017 pins = "gpio97", "gpio98", "gpio95", "gpio96"; 6018 function = "qup2_se6"; 6019 }; 6020 6021 qup_spi21_default: qup-spi21-state { 6022 pins = "gpio13", "gpio14", "gpio15", "gpio16"; 6023 function = "qup3_se0"; 6024 }; 6025 6026 qup_uart0_default: qup-uart0-state { 6027 qup_uart0_cts: qup-uart0-cts-pins { 6028 pins = "gpio20"; 6029 function = "qup0_se0"; 6030 }; 6031 6032 qup_uart0_rts: qup-uart0-rts-pins { 6033 pins = "gpio21"; 6034 function = "qup0_se0"; 6035 }; 6036 6037 qup_uart0_tx: qup-uart0-tx-pins { 6038 pins = "gpio22"; 6039 function = "qup0_se0"; 6040 }; 6041 6042 qup_uart0_rx: qup-uart0-rx-pins { 6043 pins = "gpio23"; 6044 function = "qup0_se0"; 6045 }; 6046 }; 6047 6048 qup_uart1_default: qup-uart1-state { 6049 qup_uart1_cts: qup-uart1-cts-pins { 6050 pins = "gpio24"; 6051 function = "qup0_se1"; 6052 }; 6053 6054 qup_uart1_rts: qup-uart1-rts-pins { 6055 pins = "gpio25"; 6056 function = "qup0_se1"; 6057 }; 6058 6059 qup_uart1_tx: qup-uart1-tx-pins { 6060 pins = "gpio26"; 6061 function = "qup0_se1"; 6062 }; 6063 6064 qup_uart1_rx: qup-uart1-rx-pins { 6065 pins = "gpio27"; 6066 function = "qup0_se1"; 6067 }; 6068 }; 6069 6070 qup_uart2_default: qup-uart2-state { 6071 qup_uart2_cts: qup-uart2-cts-pins { 6072 pins = "gpio36"; 6073 function = "qup0_se2"; 6074 }; 6075 6076 qup_uart2_rts: qup-uart2-rts-pins { 6077 pins = "gpio37"; 6078 function = "qup0_se2"; 6079 }; 6080 6081 qup_uart2_tx: qup-uart2-tx-pins { 6082 pins = "gpio38"; 6083 function = "qup0_se2"; 6084 }; 6085 6086 qup_uart2_rx: qup-uart2-rx-pins { 6087 pins = "gpio39"; 6088 function = "qup0_se2"; 6089 }; 6090 }; 6091 6092 qup_uart3_default: qup-uart3-state { 6093 qup_uart3_cts: qup-uart3-cts-pins { 6094 pins = "gpio28"; 6095 function = "qup0_se3"; 6096 }; 6097 6098 qup_uart3_rts: qup-uart3-rts-pins { 6099 pins = "gpio29"; 6100 function = "qup0_se3"; 6101 }; 6102 6103 qup_uart3_tx: qup-uart3-tx-pins { 6104 pins = "gpio30"; 6105 function = "qup0_se3"; 6106 }; 6107 6108 qup_uart3_rx: qup-uart3-rx-pins { 6109 pins = "gpio31"; 6110 function = "qup0_se3"; 6111 }; 6112 }; 6113 6114 qup_uart4_default: qup-uart4-state { 6115 qup_uart4_cts: qup-uart4-cts-pins { 6116 pins = "gpio32"; 6117 function = "qup0_se4"; 6118 }; 6119 6120 qup_uart4_rts: qup-uart4-rts-pins { 6121 pins = "gpio33"; 6122 function = "qup0_se4"; 6123 }; 6124 6125 qup_uart4_tx: qup-uart4-tx-pins { 6126 pins = "gpio34"; 6127 function = "qup0_se4"; 6128 }; 6129 6130 qup_uart4_rx: qup-uart4-rx-pins { 6131 pins = "gpio35"; 6132 function = "qup0_se4"; 6133 }; 6134 }; 6135 6136 qup_uart5_default: qup-uart5-state { 6137 qup_uart5_cts: qup-uart5-cts-pins { 6138 pins = "gpio36"; 6139 function = "qup0_se5"; 6140 }; 6141 6142 qup_uart5_rts: qup-uart5-rts-pins { 6143 pins = "gpio37"; 6144 function = "qup0_se5"; 6145 }; 6146 6147 qup_uart5_tx: qup-uart5-tx-pins { 6148 pins = "gpio38"; 6149 function = "qup0_se5"; 6150 }; 6151 6152 qup_uart5_rx: qup-uart5-rx-pins { 6153 pins = "gpio39"; 6154 function = "qup0_se5"; 6155 }; 6156 }; 6157 6158 qup_uart7_default: qup-uart7-state { 6159 qup_uart7_cts: qup-uart7-cts-pins { 6160 pins = "gpio40"; 6161 function = "qup1_se0"; 6162 }; 6163 6164 qup_uart7_rts: qup-uart7-rts-pins { 6165 pins = "gpio41"; 6166 function = "qup1_se0"; 6167 }; 6168 6169 qup_uart7_tx: qup-uart7-tx-pins { 6170 pins = "gpio42"; 6171 function = "qup1_se0"; 6172 }; 6173 6174 qup_uart7_rx: qup-uart7-rx-pins { 6175 pins = "gpio43"; 6176 function = "qup1_se0"; 6177 }; 6178 }; 6179 6180 qup_uart8_default: qup-uart8-state { 6181 qup_uart8_cts: qup-uart8-cts-pins { 6182 pins = "gpio42"; 6183 function = "qup1_se1"; 6184 }; 6185 6186 qup_uart8_rts: qup-uart8-rts-pins { 6187 pins = "gpio43"; 6188 function = "qup1_se1"; 6189 }; 6190 6191 qup_uart8_tx: qup-uart8-tx-pins { 6192 pins = "gpio40"; 6193 function = "qup1_se1"; 6194 }; 6195 6196 qup_uart8_rx: qup-uart8-rx-pins { 6197 pins = "gpio41"; 6198 function = "qup1_se1"; 6199 }; 6200 }; 6201 6202 qup_uart9_default: qup-uart9-state { 6203 qup_uart9_cts: qup-uart9-cts-pins { 6204 pins = "gpio46"; 6205 function = "qup1_se2"; 6206 }; 6207 6208 qup_uart9_rts: qup-uart9-rts-pins { 6209 pins = "gpio47"; 6210 function = "qup1_se2"; 6211 }; 6212 6213 qup_uart9_tx: qup-uart9-tx-pins { 6214 pins = "gpio44"; 6215 function = "qup1_se2"; 6216 }; 6217 6218 qup_uart9_rx: qup-uart9-rx-pins { 6219 pins = "gpio45"; 6220 function = "qup1_se2"; 6221 }; 6222 }; 6223 6224 qup_uart10_default: qup-uart10-state { 6225 pins = "gpio46", "gpio47"; 6226 function = "qup1_se3"; 6227 }; 6228 6229 qup_uart11_default: qup-uart11-state { 6230 qup_uart11_cts: qup-uart11-cts-pins { 6231 pins = "gpio48"; 6232 function = "qup1_se4"; 6233 }; 6234 6235 qup_uart11_rts: qup-uart11-rts-pins { 6236 pins = "gpio49"; 6237 function = "qup1_se4"; 6238 }; 6239 6240 qup_uart11_tx: qup-uart11-tx-pins { 6241 pins = "gpio50"; 6242 function = "qup1_se4"; 6243 }; 6244 6245 qup_uart11_rx: qup-uart11-rx-pins { 6246 pins = "gpio51"; 6247 function = "qup1_se4"; 6248 }; 6249 }; 6250 6251 qup_uart12_default: qup-uart12-state { 6252 qup_uart12_cts: qup-uart12-cts-pins { 6253 pins = "gpio52"; 6254 function = "qup1_se5"; 6255 }; 6256 6257 qup_uart12_rts: qup-uart12-rts-pins { 6258 pins = "gpio53"; 6259 function = "qup1_se5"; 6260 }; 6261 6262 qup_uart12_tx: qup-uart12-tx-pins { 6263 pins = "gpio54"; 6264 function = "qup1_se5"; 6265 }; 6266 6267 qup_uart12_rx: qup-uart12-rx-pins { 6268 pins = "gpio55"; 6269 function = "qup1_se5"; 6270 }; 6271 }; 6272 6273 qup_uart14_default: qup-uart14-state { 6274 qup_uart14_cts: qup-uart14-cts-pins { 6275 pins = "gpio80"; 6276 function = "qup2_se0"; 6277 }; 6278 6279 qup_uart14_rts: qup-uart14-rts-pins { 6280 pins = "gpio81"; 6281 function = "qup2_se0"; 6282 }; 6283 6284 qup_uart14_tx: qup-uart14-tx-pins { 6285 pins = "gpio82"; 6286 function = "qup2_se0"; 6287 }; 6288 6289 qup_uart14_rx: qup-uart14-rx-pins { 6290 pins = "gpio83"; 6291 function = "qup2_se0"; 6292 }; 6293 }; 6294 6295 qup_uart15_default: qup-uart15-state { 6296 qup_uart15_cts: qup-uart15-cts-pins { 6297 pins = "gpio84"; 6298 function = "qup2_se1"; 6299 }; 6300 6301 qup_uart15_rts: qup-uart15-rts-pins { 6302 pins = "gpio85"; 6303 function = "qup2_se1"; 6304 }; 6305 6306 qup_uart15_tx: qup-uart15-tx-pins { 6307 pins = "gpio99"; 6308 function = "qup2_se1"; 6309 }; 6310 6311 qup_uart15_rx: qup-uart15-rx-pins { 6312 pins = "gpio100"; 6313 function = "qup2_se1"; 6314 }; 6315 }; 6316 6317 qup_uart16_default: qup-uart16-state { 6318 qup_uart16_cts: qup-uart16-cts-pins { 6319 pins = "gpio86"; 6320 function = "qup2_se2"; 6321 }; 6322 6323 qup_uart16_rts: qup-uart16-rts-pins { 6324 pins = "gpio87"; 6325 function = "qup2_se2"; 6326 }; 6327 6328 qup_uart16_tx: qup-uart16-tx-pins { 6329 pins = "gpio88"; 6330 function = "qup2_se2"; 6331 }; 6332 6333 qup_uart16_rx: qup-uart16-rx-pins { 6334 pins = "gpio89"; 6335 function = "qup2_se2"; 6336 }; 6337 }; 6338 6339 qup_uart17_default: qup-uart17-state { 6340 qup_uart17_cts: qup-uart17-cts-pins { 6341 pins = "gpio91"; 6342 function = "qup2_se3"; 6343 }; 6344 6345 qup_uart17_rts: qup0-uart17-rts-pins { 6346 pins = "gpio92"; 6347 function = "qup2_se3"; 6348 }; 6349 6350 qup_uart17_tx: qup0-uart17-tx-pins { 6351 pins = "gpio93"; 6352 function = "qup2_se3"; 6353 }; 6354 6355 qup_uart17_rx: qup0-uart17-rx-pins { 6356 pins = "gpio94"; 6357 function = "qup2_se3"; 6358 }; 6359 }; 6360 6361 qup_uart18_default: qup-uart18-state { 6362 qup_uart18_cts: qup-uart18-cts-pins { 6363 pins = "gpio95"; 6364 function = "qup2_se4"; 6365 }; 6366 6367 qup_uart18_rts: qup-uart18-rts-pins { 6368 pins = "gpio96"; 6369 function = "qup2_se4"; 6370 }; 6371 6372 qup_uart18_tx: qup-uart18-tx-pins { 6373 pins = "gpio97"; 6374 function = "qup2_se4"; 6375 }; 6376 6377 qup_uart18_rx: qup-uart18-rx-pins { 6378 pins = "gpio98"; 6379 function = "qup2_se4"; 6380 }; 6381 }; 6382 6383 qup_uart19_default: qup-uart19-state { 6384 qup_uart19_cts: qup-uart19-cts-pins { 6385 pins = "gpio99"; 6386 function = "qup2_se5"; 6387 }; 6388 6389 qup_uart19_rts: qup-uart19-rts-pins { 6390 pins = "gpio100"; 6391 function = "qup2_se5"; 6392 }; 6393 6394 qup_uart19_tx: qup-uart19-tx-pins { 6395 pins = "gpio84"; 6396 function = "qup2_se5"; 6397 }; 6398 6399 qup_uart19_rx: qup-uart19-rx-pins { 6400 pins = "gpio85"; 6401 function = "qup2_se5"; 6402 }; 6403 }; 6404 6405 qup_uart20_default: qup-uart20-state { 6406 qup_uart20_cts: qup-uart20-cts-pins { 6407 pins = "gpio97"; 6408 function = "qup2_se6"; 6409 }; 6410 6411 qup_uart20_rts: qup-uart20-rts-pins { 6412 pins = "gpio98"; 6413 function = "qup2_se6"; 6414 }; 6415 6416 qup_uart20_tx: qup-uart20-tx-pins { 6417 pins = "gpio95"; 6418 function = "qup2_se6"; 6419 }; 6420 6421 qup_uart20_rx: qup-uart20-rx-pins { 6422 pins = "gpio96"; 6423 function = "qup2_se6"; 6424 }; 6425 }; 6426 6427 qup_uart21_default: qup-uart21-state { 6428 qup_uart21_cts: qup-uart21-cts-pins { 6429 pins = "gpio13"; 6430 function = "qup3_se0"; 6431 }; 6432 6433 qup_uart21_rts: qup-uart21-rts-pins { 6434 pins = "gpio14"; 6435 function = "qup3_se0"; 6436 }; 6437 6438 qup_uart21_tx: qup-uart21-tx-pins { 6439 pins = "gpio15"; 6440 function = "qup3_se0"; 6441 }; 6442 6443 qup_uart21_rx: qup-uart21-rx-pins { 6444 pins = "gpio16"; 6445 function = "qup3_se0"; 6446 }; 6447 }; 6448 6449 sdc_default: sdc-default-state { 6450 clk-pins { 6451 pins = "sdc1_clk"; 6452 drive-strength = <16>; 6453 bias-disable; 6454 }; 6455 6456 cmd-pins { 6457 pins = "sdc1_cmd"; 6458 drive-strength = <10>; 6459 bias-pull-up; 6460 }; 6461 6462 data-pins { 6463 pins = "sdc1_data"; 6464 drive-strength = <10>; 6465 bias-pull-up; 6466 }; 6467 }; 6468 6469 sdc_sleep: sdc-sleep-state { 6470 clk-pins { 6471 pins = "sdc1_clk"; 6472 drive-strength = <2>; 6473 bias-bus-hold; 6474 }; 6475 6476 cmd-pins { 6477 pins = "sdc1_cmd"; 6478 drive-strength = <2>; 6479 bias-bus-hold; 6480 }; 6481 6482 data-pins { 6483 pins = "sdc1_data"; 6484 drive-strength = <2>; 6485 bias-bus-hold; 6486 }; 6487 }; 6488 }; 6489 6490 sram: sram@146d8000 { 6491 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; 6492 reg = <0x0 0x146d8000 0x0 0x1000>; 6493 ranges = <0x0 0x0 0x146d8000 0x1000>; 6494 6495 #address-cells = <1>; 6496 #size-cells = <1>; 6497 6498 pil-reloc@94c { 6499 compatible = "qcom,pil-reloc-info"; 6500 reg = <0x94c 0xc8>; 6501 }; 6502 }; 6503 6504 apps_smmu: iommu@15000000 { 6505 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6506 reg = <0x0 0x15000000 0x0 0x100000>; 6507 #iommu-cells = <2>; 6508 #global-interrupts = <2>; 6509 dma-coherent; 6510 6511 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 6512 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 6513 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6514 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6515 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6516 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6517 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6518 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6519 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6520 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6521 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6522 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6523 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6524 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6525 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6526 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6527 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6528 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6529 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6530 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6531 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6532 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6533 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6534 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6535 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6536 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6537 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6538 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6539 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6540 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6541 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6542 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6543 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6544 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6545 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6546 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6547 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6548 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6549 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6550 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6551 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6552 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6553 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6554 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6555 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6556 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6557 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6558 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6559 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6560 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6561 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6562 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6563 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6564 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6565 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6566 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6567 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6568 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6569 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6570 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6571 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6572 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6573 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6574 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6575 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6576 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6577 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6578 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6579 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6580 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6581 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6582 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6583 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6584 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6585 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6586 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 6587 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 6588 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 6589 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 6590 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 6591 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 6592 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 6593 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 6594 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 6595 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 6596 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 6597 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 6598 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 6599 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 6600 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 6601 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 6602 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 6603 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 6604 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 6605 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 6606 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 6607 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 6608 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 6609 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 6610 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 6611 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 6612 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 6613 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 6614 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 6615 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 6616 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 6617 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 6618 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 6619 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 6620 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 6621 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 6622 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 6623 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 6624 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 6625 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 6626 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 6627 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 6628 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 6629 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 6630 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 6631 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 6632 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 6633 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 6634 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 6635 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 6636 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 6637 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 6638 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 6639 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 6640 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 6641 }; 6642 6643 pcie_smmu: iommu@15200000 { 6644 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6645 reg = <0x0 0x15200000 0x0 0x80000>; 6646 #iommu-cells = <2>; 6647 #global-interrupts = <2>; 6648 dma-coherent; 6649 6650 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 6651 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 6652 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 6653 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 6654 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 6655 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 6656 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 6657 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 6658 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 6659 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 6660 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 6661 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 6662 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 6663 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 6664 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 6665 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 6666 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 6667 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 6668 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 6669 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 6670 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 6671 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 6672 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 6673 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 6674 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 6675 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 6676 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 6677 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 6678 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 6679 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 6680 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 6681 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 6682 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 6683 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 6684 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 6685 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 6686 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 6687 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 6688 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 6689 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 6690 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 6691 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 6692 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 6693 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 6694 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 6695 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 6696 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 6697 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 6698 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 6699 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 6700 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 6701 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 6702 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 6703 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 6704 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 6705 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 6706 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 6707 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 6708 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 6709 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 6710 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 6711 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 6712 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 6713 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 6714 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 6715 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 6716 }; 6717 6718 intc: interrupt-controller@17a00000 { 6719 compatible = "arm,gic-v3"; 6720 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 6721 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 6722 interrupt-controller; 6723 #address-cells = <0>; 6724 #interrupt-cells = <3>; 6725 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 6726 #redistributor-regions = <1>; 6727 redistributor-stride = <0x0 0x20000>; 6728 }; 6729 6730 watchdog@17c10000 { 6731 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 6732 reg = <0x0 0x17c10000 0x0 0x1000>; 6733 clocks = <&sleep_clk>; 6734 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6735 }; 6736 6737 memtimer: timer@17c20000 { 6738 compatible = "arm,armv7-timer-mem"; 6739 reg = <0x0 0x17c20000 0x0 0x1000>; 6740 ranges = <0x0 0x0 0x0 0x20000000>; 6741 #address-cells = <1>; 6742 #size-cells = <1>; 6743 6744 frame@17c21000 { 6745 reg = <0x17c21000 0x1000>, 6746 <0x17c22000 0x1000>; 6747 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6748 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6749 frame-number = <0>; 6750 }; 6751 6752 frame@17c23000 { 6753 reg = <0x17c23000 0x1000>; 6754 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6755 frame-number = <1>; 6756 status = "disabled"; 6757 }; 6758 6759 frame@17c25000 { 6760 reg = <0x17c25000 0x1000>; 6761 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6762 frame-number = <2>; 6763 status = "disabled"; 6764 }; 6765 6766 frame@17c27000 { 6767 reg = <0x17c27000 0x1000>; 6768 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6769 frame-number = <3>; 6770 status = "disabled"; 6771 }; 6772 6773 frame@17c29000 { 6774 reg = <0x17c29000 0x1000>; 6775 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6776 frame-number = <4>; 6777 status = "disabled"; 6778 }; 6779 6780 frame@17c2b000 { 6781 reg = <0x17c2b000 0x1000>; 6782 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6783 frame-number = <5>; 6784 status = "disabled"; 6785 }; 6786 6787 frame@17c2d000 { 6788 reg = <0x17c2d000 0x1000>; 6789 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6790 frame-number = <6>; 6791 status = "disabled"; 6792 }; 6793 }; 6794 6795 apps_rsc: rsc@18200000 { 6796 compatible = "qcom,rpmh-rsc"; 6797 reg = <0x0 0x18200000 0x0 0x10000>, 6798 <0x0 0x18210000 0x0 0x10000>, 6799 <0x0 0x18220000 0x0 0x10000>; 6800 reg-names = "drv-0", "drv-1", "drv-2"; 6801 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6802 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6803 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6804 qcom,tcs-offset = <0xd00>; 6805 qcom,drv-id = <2>; 6806 qcom,tcs-config = <ACTIVE_TCS 2>, 6807 <SLEEP_TCS 3>, 6808 <WAKE_TCS 3>, 6809 <CONTROL_TCS 0>; 6810 label = "apps_rsc"; 6811 power-domains = <&system_pd>; 6812 6813 apps_bcm_voter: bcm-voter { 6814 compatible = "qcom,bcm-voter"; 6815 }; 6816 6817 rpmhcc: clock-controller { 6818 compatible = "qcom,sa8775p-rpmh-clk"; 6819 #clock-cells = <1>; 6820 clock-names = "xo"; 6821 clocks = <&xo_board_clk>; 6822 }; 6823 6824 rpmhpd: power-controller { 6825 compatible = "qcom,sa8775p-rpmhpd"; 6826 #power-domain-cells = <1>; 6827 operating-points-v2 = <&rpmhpd_opp_table>; 6828 6829 rpmhpd_opp_table: opp-table { 6830 compatible = "operating-points-v2"; 6831 6832 rpmhpd_opp_ret: opp-0 { 6833 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6834 }; 6835 6836 rpmhpd_opp_min_svs: opp-1 { 6837 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6838 }; 6839 6840 rpmhpd_opp_low_svs: opp2 { 6841 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6842 }; 6843 6844 rpmhpd_opp_svs: opp3 { 6845 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6846 }; 6847 6848 rpmhpd_opp_svs_l1: opp-4 { 6849 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6850 }; 6851 6852 rpmhpd_opp_nom: opp-5 { 6853 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6854 }; 6855 6856 rpmhpd_opp_nom_l1: opp-6 { 6857 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6858 }; 6859 6860 rpmhpd_opp_nom_l2: opp-7 { 6861 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6862 }; 6863 6864 rpmhpd_opp_turbo: opp-8 { 6865 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6866 }; 6867 6868 rpmhpd_opp_turbo_l1: opp-9 { 6869 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6870 }; 6871 }; 6872 }; 6873 }; 6874 6875 epss_l3_cl0: interconnect@18590000 { 6876 compatible = "qcom,sa8775p-epss-l3", 6877 "qcom,epss-l3"; 6878 reg = <0x0 0x18590000 0x0 0x1000>; 6879 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6880 clock-names = "xo", "alternate"; 6881 #interconnect-cells = <1>; 6882 }; 6883 6884 cpufreq_hw: cpufreq@18591000 { 6885 compatible = "qcom,sa8775p-cpufreq-epss", 6886 "qcom,cpufreq-epss"; 6887 reg = <0x0 0x18591000 0x0 0x1000>, 6888 <0x0 0x18593000 0x0 0x1000>; 6889 reg-names = "freq-domain0", "freq-domain1"; 6890 6891 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6892 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 6893 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 6894 6895 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6896 clock-names = "xo", "alternate"; 6897 6898 #freq-domain-cells = <1>; 6899 }; 6900 6901 epss_l3_cl1: interconnect@18592000 { 6902 compatible = "qcom,sa8775p-epss-l3", 6903 "qcom,epss-l3"; 6904 reg = <0x0 0x18592000 0x0 0x1000>; 6905 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6906 clock-names = "xo", "alternate"; 6907 #interconnect-cells = <1>; 6908 }; 6909 6910 remoteproc_gpdsp0: remoteproc@20c00000 { 6911 compatible = "qcom,sa8775p-gpdsp0-pas"; 6912 reg = <0x0 0x20c00000 0x0 0x10000>; 6913 6914 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 6915 <&smp2p_gpdsp0_in 0 0>, 6916 <&smp2p_gpdsp0_in 1 0>, 6917 <&smp2p_gpdsp0_in 2 0>, 6918 <&smp2p_gpdsp0_in 3 0>; 6919 interrupt-names = "wdog", "fatal", "ready", 6920 "handover", "stop-ack"; 6921 6922 clocks = <&rpmhcc RPMH_CXO_CLK>; 6923 clock-names = "xo"; 6924 6925 power-domains = <&rpmhpd SA8775P_CX>, 6926 <&rpmhpd SA8775P_MXC>; 6927 power-domain-names = "cx", "mxc"; 6928 6929 interconnects = <&gpdsp_anoc MASTER_DSP0 0 6930 &config_noc SLAVE_CLK_CTL 0>; 6931 6932 memory-region = <&pil_gdsp0_mem>; 6933 6934 qcom,qmp = <&aoss_qmp>; 6935 6936 qcom,smem-states = <&smp2p_gpdsp0_out 0>; 6937 qcom,smem-state-names = "stop"; 6938 6939 status = "disabled"; 6940 6941 glink-edge { 6942 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 6943 IPCC_MPROC_SIGNAL_GLINK_QMP 6944 IRQ_TYPE_EDGE_RISING>; 6945 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 6946 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6947 6948 label = "gpdsp0"; 6949 qcom,remote-pid = <17>; 6950 6951 fastrpc { 6952 compatible = "qcom,fastrpc"; 6953 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6954 label = "gdsp0"; 6955 #address-cells = <1>; 6956 #size-cells = <0>; 6957 6958 compute-cb@1 { 6959 compatible = "qcom,fastrpc-compute-cb"; 6960 reg = <1>; 6961 iommus = <&apps_smmu 0x38a1 0x0>; 6962 dma-coherent; 6963 }; 6964 6965 compute-cb@2 { 6966 compatible = "qcom,fastrpc-compute-cb"; 6967 reg = <2>; 6968 iommus = <&apps_smmu 0x38a2 0x0>; 6969 dma-coherent; 6970 }; 6971 6972 compute-cb@3 { 6973 compatible = "qcom,fastrpc-compute-cb"; 6974 reg = <3>; 6975 iommus = <&apps_smmu 0x38a3 0x0>; 6976 dma-coherent; 6977 }; 6978 }; 6979 }; 6980 }; 6981 6982 remoteproc_gpdsp1: remoteproc@21c00000 { 6983 compatible = "qcom,sa8775p-gpdsp1-pas"; 6984 reg = <0x0 0x21c00000 0x0 0x10000>; 6985 6986 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 6987 <&smp2p_gpdsp1_in 0 0>, 6988 <&smp2p_gpdsp1_in 1 0>, 6989 <&smp2p_gpdsp1_in 2 0>, 6990 <&smp2p_gpdsp1_in 3 0>; 6991 interrupt-names = "wdog", "fatal", "ready", 6992 "handover", "stop-ack"; 6993 6994 clocks = <&rpmhcc RPMH_CXO_CLK>; 6995 clock-names = "xo"; 6996 6997 power-domains = <&rpmhpd SA8775P_CX>, 6998 <&rpmhpd SA8775P_MXC>; 6999 power-domain-names = "cx", "mxc"; 7000 7001 interconnects = <&gpdsp_anoc MASTER_DSP1 0 7002 &config_noc SLAVE_CLK_CTL 0>; 7003 7004 memory-region = <&pil_gdsp1_mem>; 7005 7006 qcom,qmp = <&aoss_qmp>; 7007 7008 qcom,smem-states = <&smp2p_gpdsp1_out 0>; 7009 qcom,smem-state-names = "stop"; 7010 7011 status = "disabled"; 7012 7013 glink-edge { 7014 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 7015 IPCC_MPROC_SIGNAL_GLINK_QMP 7016 IRQ_TYPE_EDGE_RISING>; 7017 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 7018 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7019 7020 label = "gpdsp1"; 7021 qcom,remote-pid = <18>; 7022 7023 fastrpc { 7024 compatible = "qcom,fastrpc"; 7025 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7026 label = "gdsp1"; 7027 #address-cells = <1>; 7028 #size-cells = <0>; 7029 7030 compute-cb@1 { 7031 compatible = "qcom,fastrpc-compute-cb"; 7032 reg = <1>; 7033 iommus = <&apps_smmu 0x38c1 0x0>; 7034 dma-coherent; 7035 }; 7036 7037 compute-cb@2 { 7038 compatible = "qcom,fastrpc-compute-cb"; 7039 reg = <2>; 7040 iommus = <&apps_smmu 0x38c2 0x0>; 7041 dma-coherent; 7042 }; 7043 7044 compute-cb@3 { 7045 compatible = "qcom,fastrpc-compute-cb"; 7046 reg = <3>; 7047 iommus = <&apps_smmu 0x38c3 0x0>; 7048 dma-coherent; 7049 }; 7050 }; 7051 }; 7052 }; 7053 7054 dispcc1: clock-controller@22100000 { 7055 compatible = "qcom,sa8775p-dispcc1"; 7056 reg = <0x0 0x22100000 0x0 0x20000>; 7057 clocks = <&gcc GCC_DISP_AHB_CLK>, 7058 <&rpmhcc RPMH_CXO_CLK>, 7059 <&rpmhcc RPMH_CXO_CLK_A>, 7060 <&sleep_clk>, 7061 <0>, <0>, <0>, <0>, 7062 <0>, <0>, <0>, <0>; 7063 power-domains = <&rpmhpd SA8775P_MMCX>; 7064 #clock-cells = <1>; 7065 #reset-cells = <1>; 7066 #power-domain-cells = <1>; 7067 status = "disabled"; 7068 }; 7069 7070 ethernet1: ethernet@23000000 { 7071 compatible = "qcom,sa8775p-ethqos"; 7072 reg = <0x0 0x23000000 0x0 0x10000>, 7073 <0x0 0x23016000 0x0 0x100>; 7074 reg-names = "stmmaceth", "rgmii"; 7075 7076 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 7077 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 7078 interrupt-names = "macirq", "sfty"; 7079 7080 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 7081 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 7082 <&gcc GCC_EMAC1_PTP_CLK>, 7083 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 7084 clock-names = "stmmaceth", 7085 "pclk", 7086 "ptp_ref", 7087 "phyaux"; 7088 7089 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 7090 &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>, 7091 <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS 7092 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7093 interconnect-names = "cpu-mac", 7094 "mac-mem"; 7095 7096 power-domains = <&gcc EMAC1_GDSC>; 7097 7098 phys = <&serdes1>; 7099 phy-names = "serdes"; 7100 7101 iommus = <&apps_smmu 0x140 0xf>; 7102 dma-coherent; 7103 7104 snps,tso; 7105 snps,pbl = <32>; 7106 rx-fifo-depth = <16384>; 7107 tx-fifo-depth = <16384>; 7108 7109 status = "disabled"; 7110 }; 7111 7112 ethernet0: ethernet@23040000 { 7113 compatible = "qcom,sa8775p-ethqos"; 7114 reg = <0x0 0x23040000 0x0 0x10000>, 7115 <0x0 0x23056000 0x0 0x100>; 7116 reg-names = "stmmaceth", "rgmii"; 7117 7118 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 7119 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; 7120 interrupt-names = "macirq", "sfty"; 7121 7122 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 7123 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 7124 <&gcc GCC_EMAC0_PTP_CLK>, 7125 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 7126 clock-names = "stmmaceth", 7127 "pclk", 7128 "ptp_ref", 7129 "phyaux"; 7130 7131 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 7132 &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>, 7133 <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS 7134 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7135 interconnect-names = "cpu-mac", 7136 "mac-mem"; 7137 7138 power-domains = <&gcc EMAC0_GDSC>; 7139 7140 phys = <&serdes0>; 7141 phy-names = "serdes"; 7142 7143 iommus = <&apps_smmu 0x120 0xf>; 7144 dma-coherent; 7145 7146 snps,tso; 7147 snps,pbl = <32>; 7148 rx-fifo-depth = <16384>; 7149 tx-fifo-depth = <16384>; 7150 7151 status = "disabled"; 7152 }; 7153 7154 nspa_noc: interconnect@260c0000 { 7155 compatible = "qcom,sa8775p-nspa-noc"; 7156 reg = <0x0 0x260c0000 0x0 0x16080>; 7157 #interconnect-cells = <2>; 7158 qcom,bcm-voters = <&apps_bcm_voter>; 7159 }; 7160 7161 remoteproc_cdsp0: remoteproc@26300000 { 7162 compatible = "qcom,sa8775p-cdsp0-pas"; 7163 reg = <0x0 0x26300000 0x0 0x10000>; 7164 7165 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 7166 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>, 7167 <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>, 7168 <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>, 7169 <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>; 7170 interrupt-names = "wdog", "fatal", "ready", 7171 "handover", "stop-ack"; 7172 7173 clocks = <&rpmhcc RPMH_CXO_CLK>; 7174 clock-names = "xo"; 7175 7176 power-domains = <&rpmhpd SA8775P_CX>, 7177 <&rpmhpd SA8775P_MXC>, 7178 <&rpmhpd SA8775P_NSP0>; 7179 power-domain-names = "cx", "mxc", "nsp"; 7180 7181 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 7182 &mc_virt SLAVE_EBI1 0>; 7183 7184 memory-region = <&pil_cdsp0_mem>; 7185 7186 qcom,qmp = <&aoss_qmp>; 7187 7188 qcom,smem-states = <&smp2p_cdsp0_out 0>; 7189 qcom,smem-state-names = "stop"; 7190 7191 status = "disabled"; 7192 7193 glink-edge { 7194 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7195 IPCC_MPROC_SIGNAL_GLINK_QMP 7196 IRQ_TYPE_EDGE_RISING>; 7197 mboxes = <&ipcc IPCC_CLIENT_CDSP 7198 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7199 7200 label = "cdsp"; 7201 qcom,remote-pid = <5>; 7202 7203 fastrpc { 7204 compatible = "qcom,fastrpc"; 7205 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7206 label = "cdsp"; 7207 #address-cells = <1>; 7208 #size-cells = <0>; 7209 7210 compute-cb@1 { 7211 compatible = "qcom,fastrpc-compute-cb"; 7212 reg = <1>; 7213 iommus = <&apps_smmu 0x2141 0x04a0>, 7214 <&apps_smmu 0x2181 0x0400>; 7215 dma-coherent; 7216 }; 7217 7218 compute-cb@2 { 7219 compatible = "qcom,fastrpc-compute-cb"; 7220 reg = <2>; 7221 iommus = <&apps_smmu 0x2142 0x04a0>, 7222 <&apps_smmu 0x2182 0x0400>; 7223 dma-coherent; 7224 }; 7225 7226 compute-cb@3 { 7227 compatible = "qcom,fastrpc-compute-cb"; 7228 reg = <3>; 7229 iommus = <&apps_smmu 0x2143 0x04a0>, 7230 <&apps_smmu 0x2183 0x0400>; 7231 dma-coherent; 7232 }; 7233 7234 compute-cb@4 { 7235 compatible = "qcom,fastrpc-compute-cb"; 7236 reg = <4>; 7237 iommus = <&apps_smmu 0x2144 0x04a0>, 7238 <&apps_smmu 0x2184 0x0400>; 7239 dma-coherent; 7240 }; 7241 7242 compute-cb@5 { 7243 compatible = "qcom,fastrpc-compute-cb"; 7244 reg = <5>; 7245 iommus = <&apps_smmu 0x2145 0x04a0>, 7246 <&apps_smmu 0x2185 0x0400>; 7247 dma-coherent; 7248 }; 7249 7250 compute-cb@6 { 7251 compatible = "qcom,fastrpc-compute-cb"; 7252 reg = <6>; 7253 iommus = <&apps_smmu 0x2146 0x04a0>, 7254 <&apps_smmu 0x2186 0x0400>; 7255 dma-coherent; 7256 }; 7257 7258 compute-cb@7 { 7259 compatible = "qcom,fastrpc-compute-cb"; 7260 reg = <7>; 7261 iommus = <&apps_smmu 0x2147 0x04a0>, 7262 <&apps_smmu 0x2187 0x0400>; 7263 dma-coherent; 7264 }; 7265 7266 compute-cb@8 { 7267 compatible = "qcom,fastrpc-compute-cb"; 7268 reg = <8>; 7269 iommus = <&apps_smmu 0x2148 0x04a0>, 7270 <&apps_smmu 0x2188 0x0400>; 7271 dma-coherent; 7272 }; 7273 7274 compute-cb@9 { 7275 compatible = "qcom,fastrpc-compute-cb"; 7276 reg = <9>; 7277 iommus = <&apps_smmu 0x2149 0x04a0>, 7278 <&apps_smmu 0x2189 0x0400>; 7279 dma-coherent; 7280 }; 7281 7282 compute-cb@11 { 7283 compatible = "qcom,fastrpc-compute-cb"; 7284 reg = <11>; 7285 iommus = <&apps_smmu 0x214b 0x04a0>, 7286 <&apps_smmu 0x218b 0x0400>; 7287 dma-coherent; 7288 }; 7289 }; 7290 }; 7291 }; 7292 7293 nspb_noc: interconnect@2a0c0000 { 7294 compatible = "qcom,sa8775p-nspb-noc"; 7295 reg = <0x0 0x2a0c0000 0x0 0x16080>; 7296 #interconnect-cells = <2>; 7297 qcom,bcm-voters = <&apps_bcm_voter>; 7298 }; 7299 7300 remoteproc_cdsp1: remoteproc@2a300000 { 7301 compatible = "qcom,sa8775p-cdsp1-pas"; 7302 reg = <0x0 0x2a300000 0x0 0x10000>; 7303 7304 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 7305 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, 7306 <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>, 7307 <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>, 7308 <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>; 7309 interrupt-names = "wdog", "fatal", "ready", 7310 "handover", "stop-ack"; 7311 7312 clocks = <&rpmhcc RPMH_CXO_CLK>; 7313 clock-names = "xo"; 7314 7315 power-domains = <&rpmhpd SA8775P_CX>, 7316 <&rpmhpd SA8775P_MXC>, 7317 <&rpmhpd SA8775P_NSP1>; 7318 power-domain-names = "cx", "mxc", "nsp"; 7319 7320 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 7321 &mc_virt SLAVE_EBI1 0>; 7322 7323 memory-region = <&pil_cdsp1_mem>; 7324 7325 qcom,qmp = <&aoss_qmp>; 7326 7327 qcom,smem-states = <&smp2p_cdsp1_out 0>; 7328 qcom,smem-state-names = "stop"; 7329 7330 status = "disabled"; 7331 7332 glink-edge { 7333 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 7334 IPCC_MPROC_SIGNAL_GLINK_QMP 7335 IRQ_TYPE_EDGE_RISING>; 7336 mboxes = <&ipcc IPCC_CLIENT_NSP1 7337 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7338 7339 label = "cdsp"; 7340 qcom,remote-pid = <12>; 7341 7342 fastrpc { 7343 compatible = "qcom,fastrpc"; 7344 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7345 label = "cdsp1"; 7346 #address-cells = <1>; 7347 #size-cells = <0>; 7348 7349 compute-cb@1 { 7350 compatible = "qcom,fastrpc-compute-cb"; 7351 reg = <1>; 7352 iommus = <&apps_smmu 0x2941 0x04a0>, 7353 <&apps_smmu 0x2981 0x0400>; 7354 dma-coherent; 7355 }; 7356 7357 compute-cb@2 { 7358 compatible = "qcom,fastrpc-compute-cb"; 7359 reg = <2>; 7360 iommus = <&apps_smmu 0x2942 0x04a0>, 7361 <&apps_smmu 0x2982 0x0400>; 7362 dma-coherent; 7363 }; 7364 7365 compute-cb@3 { 7366 compatible = "qcom,fastrpc-compute-cb"; 7367 reg = <3>; 7368 iommus = <&apps_smmu 0x2943 0x04a0>, 7369 <&apps_smmu 0x2983 0x0400>; 7370 dma-coherent; 7371 }; 7372 7373 compute-cb@4 { 7374 compatible = "qcom,fastrpc-compute-cb"; 7375 reg = <4>; 7376 iommus = <&apps_smmu 0x2944 0x04a0>, 7377 <&apps_smmu 0x2984 0x0400>; 7378 dma-coherent; 7379 }; 7380 7381 compute-cb@5 { 7382 compatible = "qcom,fastrpc-compute-cb"; 7383 reg = <5>; 7384 iommus = <&apps_smmu 0x2945 0x04a0>, 7385 <&apps_smmu 0x2985 0x0400>; 7386 dma-coherent; 7387 }; 7388 7389 compute-cb@6 { 7390 compatible = "qcom,fastrpc-compute-cb"; 7391 reg = <6>; 7392 iommus = <&apps_smmu 0x2946 0x04a0>, 7393 <&apps_smmu 0x2986 0x0400>; 7394 dma-coherent; 7395 }; 7396 7397 compute-cb@7 { 7398 compatible = "qcom,fastrpc-compute-cb"; 7399 reg = <7>; 7400 iommus = <&apps_smmu 0x2947 0x04a0>, 7401 <&apps_smmu 0x2987 0x0400>; 7402 dma-coherent; 7403 }; 7404 7405 compute-cb@8 { 7406 compatible = "qcom,fastrpc-compute-cb"; 7407 reg = <8>; 7408 iommus = <&apps_smmu 0x2948 0x04a0>, 7409 <&apps_smmu 0x2988 0x0400>; 7410 dma-coherent; 7411 }; 7412 7413 compute-cb@9 { 7414 compatible = "qcom,fastrpc-compute-cb"; 7415 reg = <9>; 7416 iommus = <&apps_smmu 0x2949 0x04a0>, 7417 <&apps_smmu 0x2989 0x0400>; 7418 dma-coherent; 7419 }; 7420 7421 compute-cb@10 { 7422 compatible = "qcom,fastrpc-compute-cb"; 7423 reg = <10>; 7424 iommus = <&apps_smmu 0x294a 0x04a0>, 7425 <&apps_smmu 0x298a 0x0400>; 7426 dma-coherent; 7427 }; 7428 7429 compute-cb@11 { 7430 compatible = "qcom,fastrpc-compute-cb"; 7431 reg = <11>; 7432 iommus = <&apps_smmu 0x294b 0x04a0>, 7433 <&apps_smmu 0x298b 0x0400>; 7434 dma-coherent; 7435 }; 7436 7437 compute-cb@12 { 7438 compatible = "qcom,fastrpc-compute-cb"; 7439 reg = <12>; 7440 iommus = <&apps_smmu 0x294c 0x04a0>, 7441 <&apps_smmu 0x298c 0x0400>; 7442 dma-coherent; 7443 }; 7444 7445 compute-cb@13 { 7446 compatible = "qcom,fastrpc-compute-cb"; 7447 reg = <13>; 7448 iommus = <&apps_smmu 0x294d 0x04a0>, 7449 <&apps_smmu 0x298d 0x0400>; 7450 dma-coherent; 7451 }; 7452 }; 7453 }; 7454 }; 7455 7456 remoteproc_adsp: remoteproc@30000000 { 7457 compatible = "qcom,sa8775p-adsp-pas"; 7458 reg = <0x0 0x30000000 0x0 0x100>; 7459 7460 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 7461 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 7462 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 7463 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 7464 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 7465 interrupt-names = "wdog", "fatal", "ready", "handover", 7466 "stop-ack"; 7467 7468 clocks = <&rpmhcc RPMH_CXO_CLK>; 7469 clock-names = "xo"; 7470 7471 power-domains = <&rpmhpd SA8775P_LCX>, 7472 <&rpmhpd SA8775P_LMX>; 7473 power-domain-names = "lcx", "lmx"; 7474 7475 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 7476 7477 memory-region = <&pil_adsp_mem>; 7478 7479 qcom,qmp = <&aoss_qmp>; 7480 7481 qcom,smem-states = <&smp2p_adsp_out 0>; 7482 qcom,smem-state-names = "stop"; 7483 7484 status = "disabled"; 7485 7486 remoteproc_adsp_glink: glink-edge { 7487 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 7488 IPCC_MPROC_SIGNAL_GLINK_QMP 7489 IRQ_TYPE_EDGE_RISING>; 7490 mboxes = <&ipcc IPCC_CLIENT_LPASS 7491 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7492 7493 label = "lpass"; 7494 qcom,remote-pid = <2>; 7495 7496 fastrpc { 7497 compatible = "qcom,fastrpc"; 7498 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7499 label = "adsp"; 7500 memory-region = <&adsp_rpc_remote_heap_mem>; 7501 qcom,vmids = <QCOM_SCM_VMID_LPASS 7502 QCOM_SCM_VMID_ADSP_HEAP>; 7503 #address-cells = <1>; 7504 #size-cells = <0>; 7505 7506 compute-cb@3 { 7507 compatible = "qcom,fastrpc-compute-cb"; 7508 reg = <3>; 7509 iommus = <&apps_smmu 0x3003 0x0>; 7510 dma-coherent; 7511 }; 7512 7513 compute-cb@4 { 7514 compatible = "qcom,fastrpc-compute-cb"; 7515 reg = <4>; 7516 iommus = <&apps_smmu 0x3004 0x0>; 7517 dma-coherent; 7518 }; 7519 7520 compute-cb@5 { 7521 compatible = "qcom,fastrpc-compute-cb"; 7522 reg = <5>; 7523 iommus = <&apps_smmu 0x3005 0x0>; 7524 qcom,nsessions = <5>; 7525 dma-coherent; 7526 }; 7527 }; 7528 7529 gpr { 7530 compatible = "qcom,gpr"; 7531 qcom,glink-channels = "adsp_apps"; 7532 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 7533 qcom,intents = <512 20>; 7534 #address-cells = <1>; 7535 #size-cells = <0>; 7536 7537 q6apm: service@1 { 7538 compatible = "qcom,q6apm"; 7539 reg = <GPR_APM_MODULE_IID>; 7540 #sound-dai-cells = <0>; 7541 qcom,protection-domain = "avs/audio", 7542 "msm/adsp/audio_pd"; 7543 7544 q6apmbedai: bedais { 7545 compatible = "qcom,q6apm-lpass-dais"; 7546 #sound-dai-cells = <1>; 7547 }; 7548 7549 q6apmdai: dais { 7550 compatible = "qcom,q6apm-dais"; 7551 iommus = <&apps_smmu 0x3001 0x0>; 7552 }; 7553 }; 7554 7555 q6prm: service@2 { 7556 compatible = "qcom,q6prm"; 7557 reg = <GPR_PRM_MODULE_IID>; 7558 qcom,protection-domain = "avs/audio", 7559 "msm/adsp/audio_pd"; 7560 7561 q6prmcc: clock-controller { 7562 compatible = "qcom,q6prm-lpass-clocks"; 7563 #clock-cells = <2>; 7564 }; 7565 }; 7566 }; 7567 }; 7568 }; 7569 }; 7570 7571 thermal-zones { 7572 aoss-0-thermal { 7573 thermal-sensors = <&tsens0 0>; 7574 7575 trips { 7576 trip-point0 { 7577 temperature = <105000>; 7578 hysteresis = <5000>; 7579 type = "passive"; 7580 }; 7581 7582 trip-point1 { 7583 temperature = <115000>; 7584 hysteresis = <5000>; 7585 type = "passive"; 7586 }; 7587 }; 7588 }; 7589 7590 cpu-0-0-0-thermal { 7591 polling-delay-passive = <10>; 7592 7593 thermal-sensors = <&tsens0 1>; 7594 7595 trips { 7596 trip-point0 { 7597 temperature = <105000>; 7598 hysteresis = <5000>; 7599 type = "passive"; 7600 }; 7601 7602 trip-point1 { 7603 temperature = <115000>; 7604 hysteresis = <5000>; 7605 type = "passive"; 7606 }; 7607 }; 7608 }; 7609 7610 cpu-0-1-0-thermal { 7611 polling-delay-passive = <10>; 7612 7613 thermal-sensors = <&tsens0 2>; 7614 7615 trips { 7616 trip-point0 { 7617 temperature = <105000>; 7618 hysteresis = <5000>; 7619 type = "passive"; 7620 }; 7621 7622 trip-point1 { 7623 temperature = <115000>; 7624 hysteresis = <5000>; 7625 type = "passive"; 7626 }; 7627 }; 7628 }; 7629 7630 cpu-0-2-0-thermal { 7631 polling-delay-passive = <10>; 7632 7633 thermal-sensors = <&tsens0 3>; 7634 7635 trips { 7636 trip-point0 { 7637 temperature = <105000>; 7638 hysteresis = <5000>; 7639 type = "passive"; 7640 }; 7641 7642 trip-point1 { 7643 temperature = <115000>; 7644 hysteresis = <5000>; 7645 type = "passive"; 7646 }; 7647 }; 7648 }; 7649 7650 cpu-0-3-0-thermal { 7651 polling-delay-passive = <10>; 7652 7653 thermal-sensors = <&tsens0 4>; 7654 7655 trips { 7656 trip-point0 { 7657 temperature = <105000>; 7658 hysteresis = <5000>; 7659 type = "passive"; 7660 }; 7661 7662 trip-point1 { 7663 temperature = <115000>; 7664 hysteresis = <5000>; 7665 type = "passive"; 7666 }; 7667 }; 7668 }; 7669 7670 gpuss-0-thermal { 7671 polling-delay-passive = <10>; 7672 7673 thermal-sensors = <&tsens0 5>; 7674 7675 cooling-maps { 7676 map0 { 7677 trip = <&gpuss0_alert0>; 7678 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7679 }; 7680 }; 7681 7682 trips { 7683 gpuss0_alert0: trip-point0 { 7684 temperature = <105000>; 7685 hysteresis = <5000>; 7686 type = "passive"; 7687 }; 7688 7689 trip-point1 { 7690 temperature = <115000>; 7691 hysteresis = <5000>; 7692 type = "passive"; 7693 }; 7694 }; 7695 }; 7696 7697 gpuss-1-thermal { 7698 polling-delay-passive = <10>; 7699 7700 thermal-sensors = <&tsens0 6>; 7701 7702 cooling-maps { 7703 map0 { 7704 trip = <&gpuss1_alert0>; 7705 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7706 }; 7707 }; 7708 7709 trips { 7710 gpuss1_alert0: trip-point0 { 7711 temperature = <105000>; 7712 hysteresis = <5000>; 7713 type = "passive"; 7714 }; 7715 7716 trip-point1 { 7717 temperature = <115000>; 7718 hysteresis = <5000>; 7719 type = "passive"; 7720 }; 7721 }; 7722 }; 7723 7724 gpuss-2-thermal { 7725 polling-delay-passive = <10>; 7726 7727 thermal-sensors = <&tsens0 7>; 7728 7729 cooling-maps { 7730 map0 { 7731 trip = <&gpuss2_alert0>; 7732 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7733 }; 7734 }; 7735 7736 trips { 7737 gpuss2_alert0: trip-point0 { 7738 temperature = <105000>; 7739 hysteresis = <5000>; 7740 type = "passive"; 7741 }; 7742 7743 trip-point1 { 7744 temperature = <115000>; 7745 hysteresis = <5000>; 7746 type = "passive"; 7747 }; 7748 }; 7749 }; 7750 7751 audio-thermal { 7752 thermal-sensors = <&tsens0 8>; 7753 7754 trips { 7755 trip-point0 { 7756 temperature = <105000>; 7757 hysteresis = <5000>; 7758 type = "passive"; 7759 }; 7760 7761 trip-point1 { 7762 temperature = <115000>; 7763 hysteresis = <5000>; 7764 type = "passive"; 7765 }; 7766 }; 7767 }; 7768 7769 camss-0-thermal { 7770 thermal-sensors = <&tsens0 9>; 7771 7772 trips { 7773 trip-point0 { 7774 temperature = <105000>; 7775 hysteresis = <5000>; 7776 type = "passive"; 7777 }; 7778 7779 trip-point1 { 7780 temperature = <115000>; 7781 hysteresis = <5000>; 7782 type = "passive"; 7783 }; 7784 }; 7785 }; 7786 7787 pcie-0-thermal { 7788 thermal-sensors = <&tsens0 10>; 7789 7790 trips { 7791 trip-point0 { 7792 temperature = <105000>; 7793 hysteresis = <5000>; 7794 type = "passive"; 7795 }; 7796 7797 trip-point1 { 7798 temperature = <115000>; 7799 hysteresis = <5000>; 7800 type = "passive"; 7801 }; 7802 }; 7803 }; 7804 7805 cpuss-0-0-thermal { 7806 thermal-sensors = <&tsens0 11>; 7807 7808 trips { 7809 trip-point0 { 7810 temperature = <105000>; 7811 hysteresis = <5000>; 7812 type = "passive"; 7813 }; 7814 7815 trip-point1 { 7816 temperature = <115000>; 7817 hysteresis = <5000>; 7818 type = "passive"; 7819 }; 7820 }; 7821 }; 7822 7823 aoss-1-thermal { 7824 thermal-sensors = <&tsens1 0>; 7825 7826 trips { 7827 trip-point0 { 7828 temperature = <105000>; 7829 hysteresis = <5000>; 7830 type = "passive"; 7831 }; 7832 7833 trip-point1 { 7834 temperature = <115000>; 7835 hysteresis = <5000>; 7836 type = "passive"; 7837 }; 7838 }; 7839 }; 7840 7841 cpu-0-0-1-thermal { 7842 polling-delay-passive = <10>; 7843 7844 thermal-sensors = <&tsens1 1>; 7845 7846 trips { 7847 trip-point0 { 7848 temperature = <105000>; 7849 hysteresis = <5000>; 7850 type = "passive"; 7851 }; 7852 7853 trip-point1 { 7854 temperature = <115000>; 7855 hysteresis = <5000>; 7856 type = "passive"; 7857 }; 7858 }; 7859 }; 7860 7861 cpu-0-1-1-thermal { 7862 polling-delay-passive = <10>; 7863 7864 thermal-sensors = <&tsens1 2>; 7865 7866 trips { 7867 trip-point0 { 7868 temperature = <105000>; 7869 hysteresis = <5000>; 7870 type = "passive"; 7871 }; 7872 7873 trip-point1 { 7874 temperature = <115000>; 7875 hysteresis = <5000>; 7876 type = "passive"; 7877 }; 7878 }; 7879 }; 7880 7881 cpu-0-2-1-thermal { 7882 polling-delay-passive = <10>; 7883 7884 thermal-sensors = <&tsens1 3>; 7885 7886 trips { 7887 trip-point0 { 7888 temperature = <105000>; 7889 hysteresis = <5000>; 7890 type = "passive"; 7891 }; 7892 7893 trip-point1 { 7894 temperature = <115000>; 7895 hysteresis = <5000>; 7896 type = "passive"; 7897 }; 7898 }; 7899 }; 7900 7901 cpu-0-3-1-thermal { 7902 polling-delay-passive = <10>; 7903 7904 thermal-sensors = <&tsens1 4>; 7905 7906 trips { 7907 trip-point0 { 7908 temperature = <105000>; 7909 hysteresis = <5000>; 7910 type = "passive"; 7911 }; 7912 7913 trip-point1 { 7914 temperature = <115000>; 7915 hysteresis = <5000>; 7916 type = "passive"; 7917 }; 7918 }; 7919 }; 7920 7921 gpuss-3-thermal { 7922 polling-delay-passive = <10>; 7923 7924 thermal-sensors = <&tsens1 5>; 7925 7926 cooling-maps { 7927 map0 { 7928 trip = <&gpuss3_alert0>; 7929 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7930 }; 7931 }; 7932 7933 trips { 7934 gpuss3_alert0: trip-point0 { 7935 temperature = <105000>; 7936 hysteresis = <5000>; 7937 type = "passive"; 7938 }; 7939 7940 trip-point1 { 7941 temperature = <115000>; 7942 hysteresis = <5000>; 7943 type = "passive"; 7944 }; 7945 }; 7946 }; 7947 7948 gpuss-4-thermal { 7949 polling-delay-passive = <10>; 7950 7951 thermal-sensors = <&tsens1 6>; 7952 7953 cooling-maps { 7954 map0 { 7955 trip = <&gpuss4_alert0>; 7956 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7957 }; 7958 }; 7959 7960 trips { 7961 gpuss4_alert0: trip-point0 { 7962 temperature = <105000>; 7963 hysteresis = <5000>; 7964 type = "passive"; 7965 }; 7966 7967 trip-point1 { 7968 temperature = <115000>; 7969 hysteresis = <5000>; 7970 type = "passive"; 7971 }; 7972 }; 7973 }; 7974 7975 gpuss-5-thermal { 7976 polling-delay-passive = <10>; 7977 7978 thermal-sensors = <&tsens1 7>; 7979 7980 cooling-maps { 7981 map0 { 7982 trip = <&gpuss5_alert0>; 7983 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7984 }; 7985 }; 7986 7987 trips { 7988 gpuss5_alert0: trip-point0 { 7989 temperature = <105000>; 7990 hysteresis = <5000>; 7991 type = "passive"; 7992 }; 7993 7994 trip-point1 { 7995 temperature = <115000>; 7996 hysteresis = <5000>; 7997 type = "passive"; 7998 }; 7999 }; 8000 }; 8001 8002 video-thermal { 8003 thermal-sensors = <&tsens1 8>; 8004 8005 trips { 8006 trip-point0 { 8007 temperature = <105000>; 8008 hysteresis = <5000>; 8009 type = "passive"; 8010 }; 8011 8012 trip-point1 { 8013 temperature = <115000>; 8014 hysteresis = <5000>; 8015 type = "passive"; 8016 }; 8017 }; 8018 }; 8019 8020 camss-1-thermal { 8021 thermal-sensors = <&tsens1 9>; 8022 8023 trips { 8024 trip-point0 { 8025 temperature = <105000>; 8026 hysteresis = <5000>; 8027 type = "passive"; 8028 }; 8029 8030 trip-point1 { 8031 temperature = <115000>; 8032 hysteresis = <5000>; 8033 type = "passive"; 8034 }; 8035 }; 8036 }; 8037 8038 pcie-1-thermal { 8039 thermal-sensors = <&tsens1 10>; 8040 8041 trips { 8042 trip-point0 { 8043 temperature = <105000>; 8044 hysteresis = <5000>; 8045 type = "passive"; 8046 }; 8047 8048 trip-point1 { 8049 temperature = <115000>; 8050 hysteresis = <5000>; 8051 type = "passive"; 8052 }; 8053 }; 8054 }; 8055 8056 cpuss-0-1-thermal { 8057 thermal-sensors = <&tsens1 11>; 8058 8059 trips { 8060 trip-point0 { 8061 temperature = <105000>; 8062 hysteresis = <5000>; 8063 type = "passive"; 8064 }; 8065 8066 trip-point1 { 8067 temperature = <115000>; 8068 hysteresis = <5000>; 8069 type = "passive"; 8070 }; 8071 }; 8072 }; 8073 8074 aoss-2-thermal { 8075 thermal-sensors = <&tsens2 0>; 8076 8077 trips { 8078 trip-point0 { 8079 temperature = <105000>; 8080 hysteresis = <5000>; 8081 type = "passive"; 8082 }; 8083 8084 trip-point1 { 8085 temperature = <115000>; 8086 hysteresis = <5000>; 8087 type = "passive"; 8088 }; 8089 }; 8090 }; 8091 8092 cpu-1-0-0-thermal { 8093 polling-delay-passive = <10>; 8094 8095 thermal-sensors = <&tsens2 1>; 8096 8097 trips { 8098 trip-point0 { 8099 temperature = <105000>; 8100 hysteresis = <5000>; 8101 type = "passive"; 8102 }; 8103 8104 trip-point1 { 8105 temperature = <115000>; 8106 hysteresis = <5000>; 8107 type = "passive"; 8108 }; 8109 }; 8110 }; 8111 8112 cpu-1-1-0-thermal { 8113 polling-delay-passive = <10>; 8114 8115 thermal-sensors = <&tsens2 2>; 8116 8117 trips { 8118 trip-point0 { 8119 temperature = <105000>; 8120 hysteresis = <5000>; 8121 type = "passive"; 8122 }; 8123 8124 trip-point1 { 8125 temperature = <115000>; 8126 hysteresis = <5000>; 8127 type = "passive"; 8128 }; 8129 }; 8130 }; 8131 8132 cpu-1-2-0-thermal { 8133 polling-delay-passive = <10>; 8134 8135 thermal-sensors = <&tsens2 3>; 8136 8137 trips { 8138 trip-point0 { 8139 temperature = <105000>; 8140 hysteresis = <5000>; 8141 type = "passive"; 8142 }; 8143 8144 trip-point1 { 8145 temperature = <115000>; 8146 hysteresis = <5000>; 8147 type = "passive"; 8148 }; 8149 }; 8150 }; 8151 8152 cpu-1-3-0-thermal { 8153 polling-delay-passive = <10>; 8154 8155 thermal-sensors = <&tsens2 4>; 8156 8157 trips { 8158 trip-point0 { 8159 temperature = <105000>; 8160 hysteresis = <5000>; 8161 type = "passive"; 8162 }; 8163 8164 trip-point1 { 8165 temperature = <115000>; 8166 hysteresis = <5000>; 8167 type = "passive"; 8168 }; 8169 }; 8170 }; 8171 8172 nsp-0-0-0-thermal { 8173 polling-delay-passive = <10>; 8174 8175 thermal-sensors = <&tsens2 5>; 8176 8177 trips { 8178 trip-point0 { 8179 temperature = <105000>; 8180 hysteresis = <5000>; 8181 type = "passive"; 8182 }; 8183 8184 trip-point1 { 8185 temperature = <115000>; 8186 hysteresis = <5000>; 8187 type = "passive"; 8188 }; 8189 }; 8190 }; 8191 8192 nsp-0-1-0-thermal { 8193 polling-delay-passive = <10>; 8194 8195 thermal-sensors = <&tsens2 6>; 8196 8197 trips { 8198 trip-point0 { 8199 temperature = <105000>; 8200 hysteresis = <5000>; 8201 type = "passive"; 8202 }; 8203 8204 trip-point1 { 8205 temperature = <115000>; 8206 hysteresis = <5000>; 8207 type = "passive"; 8208 }; 8209 }; 8210 }; 8211 8212 nsp-0-2-0-thermal { 8213 polling-delay-passive = <10>; 8214 8215 thermal-sensors = <&tsens2 7>; 8216 8217 trips { 8218 trip-point0 { 8219 temperature = <105000>; 8220 hysteresis = <5000>; 8221 type = "passive"; 8222 }; 8223 8224 trip-point1 { 8225 temperature = <115000>; 8226 hysteresis = <5000>; 8227 type = "passive"; 8228 }; 8229 }; 8230 }; 8231 8232 nsp-1-0-0-thermal { 8233 polling-delay-passive = <10>; 8234 8235 thermal-sensors = <&tsens2 8>; 8236 8237 trips { 8238 trip-point0 { 8239 temperature = <105000>; 8240 hysteresis = <5000>; 8241 type = "passive"; 8242 }; 8243 8244 trip-point1 { 8245 temperature = <115000>; 8246 hysteresis = <5000>; 8247 type = "passive"; 8248 }; 8249 }; 8250 }; 8251 8252 nsp-1-1-0-thermal { 8253 polling-delay-passive = <10>; 8254 8255 thermal-sensors = <&tsens2 9>; 8256 8257 trips { 8258 trip-point0 { 8259 temperature = <105000>; 8260 hysteresis = <5000>; 8261 type = "passive"; 8262 }; 8263 8264 trip-point1 { 8265 temperature = <115000>; 8266 hysteresis = <5000>; 8267 type = "passive"; 8268 }; 8269 }; 8270 }; 8271 8272 nsp-1-2-0-thermal { 8273 polling-delay-passive = <10>; 8274 8275 thermal-sensors = <&tsens2 10>; 8276 8277 trips { 8278 trip-point0 { 8279 temperature = <105000>; 8280 hysteresis = <5000>; 8281 type = "passive"; 8282 }; 8283 8284 trip-point1 { 8285 temperature = <115000>; 8286 hysteresis = <5000>; 8287 type = "passive"; 8288 }; 8289 }; 8290 }; 8291 8292 ddrss-0-thermal { 8293 thermal-sensors = <&tsens2 11>; 8294 8295 trips { 8296 trip-point0 { 8297 temperature = <105000>; 8298 hysteresis = <5000>; 8299 type = "passive"; 8300 }; 8301 8302 trip-point1 { 8303 temperature = <115000>; 8304 hysteresis = <5000>; 8305 type = "passive"; 8306 }; 8307 }; 8308 }; 8309 8310 cpuss-1-0-thermal { 8311 thermal-sensors = <&tsens2 12>; 8312 8313 trips { 8314 trip-point0 { 8315 temperature = <105000>; 8316 hysteresis = <5000>; 8317 type = "passive"; 8318 }; 8319 8320 trip-point1 { 8321 temperature = <115000>; 8322 hysteresis = <5000>; 8323 type = "passive"; 8324 }; 8325 }; 8326 }; 8327 8328 aoss-3-thermal { 8329 thermal-sensors = <&tsens3 0>; 8330 8331 trips { 8332 trip-point0 { 8333 temperature = <105000>; 8334 hysteresis = <5000>; 8335 type = "passive"; 8336 }; 8337 8338 trip-point1 { 8339 temperature = <115000>; 8340 hysteresis = <5000>; 8341 type = "passive"; 8342 }; 8343 }; 8344 }; 8345 8346 cpu-1-0-1-thermal { 8347 polling-delay-passive = <10>; 8348 8349 thermal-sensors = <&tsens3 1>; 8350 8351 trips { 8352 trip-point0 { 8353 temperature = <105000>; 8354 hysteresis = <5000>; 8355 type = "passive"; 8356 }; 8357 8358 trip-point1 { 8359 temperature = <115000>; 8360 hysteresis = <5000>; 8361 type = "passive"; 8362 }; 8363 }; 8364 }; 8365 8366 cpu-1-1-1-thermal { 8367 polling-delay-passive = <10>; 8368 8369 thermal-sensors = <&tsens3 2>; 8370 8371 trips { 8372 trip-point0 { 8373 temperature = <105000>; 8374 hysteresis = <5000>; 8375 type = "passive"; 8376 }; 8377 8378 trip-point1 { 8379 temperature = <115000>; 8380 hysteresis = <5000>; 8381 type = "passive"; 8382 }; 8383 }; 8384 }; 8385 8386 cpu-1-2-1-thermal { 8387 polling-delay-passive = <10>; 8388 8389 thermal-sensors = <&tsens3 3>; 8390 8391 trips { 8392 trip-point0 { 8393 temperature = <105000>; 8394 hysteresis = <5000>; 8395 type = "passive"; 8396 }; 8397 8398 trip-point1 { 8399 temperature = <115000>; 8400 hysteresis = <5000>; 8401 type = "passive"; 8402 }; 8403 }; 8404 }; 8405 8406 cpu-1-3-1-thermal { 8407 polling-delay-passive = <10>; 8408 8409 thermal-sensors = <&tsens3 4>; 8410 8411 trips { 8412 trip-point0 { 8413 temperature = <105000>; 8414 hysteresis = <5000>; 8415 type = "passive"; 8416 }; 8417 8418 trip-point1 { 8419 temperature = <115000>; 8420 hysteresis = <5000>; 8421 type = "passive"; 8422 }; 8423 }; 8424 }; 8425 8426 nsp-0-0-1-thermal { 8427 polling-delay-passive = <10>; 8428 8429 thermal-sensors = <&tsens3 5>; 8430 8431 trips { 8432 trip-point0 { 8433 temperature = <105000>; 8434 hysteresis = <5000>; 8435 type = "passive"; 8436 }; 8437 8438 trip-point1 { 8439 temperature = <115000>; 8440 hysteresis = <5000>; 8441 type = "passive"; 8442 }; 8443 }; 8444 }; 8445 8446 nsp-0-1-1-thermal { 8447 polling-delay-passive = <10>; 8448 8449 thermal-sensors = <&tsens3 6>; 8450 8451 trips { 8452 trip-point0 { 8453 temperature = <105000>; 8454 hysteresis = <5000>; 8455 type = "passive"; 8456 }; 8457 8458 trip-point1 { 8459 temperature = <115000>; 8460 hysteresis = <5000>; 8461 type = "passive"; 8462 }; 8463 }; 8464 }; 8465 8466 nsp-0-2-1-thermal { 8467 polling-delay-passive = <10>; 8468 8469 thermal-sensors = <&tsens3 7>; 8470 8471 trips { 8472 trip-point0 { 8473 temperature = <105000>; 8474 hysteresis = <5000>; 8475 type = "passive"; 8476 }; 8477 8478 trip-point1 { 8479 temperature = <115000>; 8480 hysteresis = <5000>; 8481 type = "passive"; 8482 }; 8483 }; 8484 }; 8485 8486 nsp-1-0-1-thermal { 8487 polling-delay-passive = <10>; 8488 8489 thermal-sensors = <&tsens3 8>; 8490 8491 trips { 8492 trip-point0 { 8493 temperature = <105000>; 8494 hysteresis = <5000>; 8495 type = "passive"; 8496 }; 8497 8498 trip-point1 { 8499 temperature = <115000>; 8500 hysteresis = <5000>; 8501 type = "passive"; 8502 }; 8503 }; 8504 }; 8505 8506 nsp-1-1-1-thermal { 8507 polling-delay-passive = <10>; 8508 8509 thermal-sensors = <&tsens3 9>; 8510 8511 trips { 8512 trip-point0 { 8513 temperature = <105000>; 8514 hysteresis = <5000>; 8515 type = "passive"; 8516 }; 8517 8518 trip-point1 { 8519 temperature = <115000>; 8520 hysteresis = <5000>; 8521 type = "passive"; 8522 }; 8523 }; 8524 }; 8525 8526 nsp-1-2-1-thermal { 8527 polling-delay-passive = <10>; 8528 8529 thermal-sensors = <&tsens3 10>; 8530 8531 trips { 8532 trip-point0 { 8533 temperature = <105000>; 8534 hysteresis = <5000>; 8535 type = "passive"; 8536 }; 8537 8538 trip-point1 { 8539 temperature = <115000>; 8540 hysteresis = <5000>; 8541 type = "passive"; 8542 }; 8543 }; 8544 }; 8545 8546 ddrss-1-thermal { 8547 thermal-sensors = <&tsens3 11>; 8548 8549 trips { 8550 trip-point0 { 8551 temperature = <105000>; 8552 hysteresis = <5000>; 8553 type = "passive"; 8554 }; 8555 8556 trip-point1 { 8557 temperature = <115000>; 8558 hysteresis = <5000>; 8559 type = "passive"; 8560 }; 8561 }; 8562 }; 8563 8564 cpuss-1-1-thermal { 8565 thermal-sensors = <&tsens3 12>; 8566 8567 trips { 8568 trip-point0 { 8569 temperature = <105000>; 8570 hysteresis = <5000>; 8571 type = "passive"; 8572 }; 8573 8574 trip-point1 { 8575 temperature = <115000>; 8576 hysteresis = <5000>; 8577 type = "passive"; 8578 }; 8579 }; 8580 }; 8581 }; 8582 8583 arch_timer: timer { 8584 compatible = "arm,armv8-timer"; 8585 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 8586 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 8587 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 8588 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 8589 }; 8590 8591 turing-llm-tpdm { 8592 compatible = "qcom,coresight-static-tpdm"; 8593 8594 qcom,cmb-element-bits = <32>; 8595 8596 out-ports { 8597 port { 8598 turing_llm_tpdm_out: endpoint { 8599 remote-endpoint = <&turing0_funnel_in1>; 8600 }; 8601 }; 8602 }; 8603 }; 8604 8605 pcie0: pcie@1c00000 { 8606 compatible = "qcom,pcie-sa8775p"; 8607 reg = <0x0 0x01c00000 0x0 0x3000>, 8608 <0x0 0x40000000 0x0 0xf20>, 8609 <0x0 0x40000f20 0x0 0xa8>, 8610 <0x0 0x40001000 0x0 0x4000>, 8611 <0x0 0x40100000 0x0 0x100000>, 8612 <0x0 0x01c03000 0x0 0x1000>; 8613 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 8614 device_type = "pci"; 8615 8616 #address-cells = <3>; 8617 #size-cells = <2>; 8618 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 8619 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 8620 bus-range = <0x00 0xff>; 8621 8622 dma-coherent; 8623 8624 linux,pci-domain = <0>; 8625 num-lanes = <2>; 8626 8627 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 8628 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 8629 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 8630 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 8631 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 8632 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 8633 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 8634 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 8635 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 8636 interrupt-names = "msi0", 8637 "msi1", 8638 "msi2", 8639 "msi3", 8640 "msi4", 8641 "msi5", 8642 "msi6", 8643 "msi7", 8644 "global"; 8645 #interrupt-cells = <1>; 8646 interrupt-map-mask = <0 0 0 0x7>; 8647 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 8648 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 8649 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 8650 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 8651 8652 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 8653 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 8654 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 8655 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 8656 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 8657 8658 clock-names = "aux", 8659 "cfg", 8660 "bus_master", 8661 "bus_slave", 8662 "slave_q2a"; 8663 8664 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 8665 assigned-clock-rates = <19200000>; 8666 8667 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 8668 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 8669 interconnect-names = "pcie-mem", "cpu-pcie"; 8670 8671 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 8672 <0x100 &pcie_smmu 0x0001 0x1>; 8673 8674 resets = <&gcc GCC_PCIE_0_BCR>, 8675 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; 8676 reset-names = "pci", 8677 "link_down"; 8678 8679 power-domains = <&gcc PCIE_0_GDSC>; 8680 8681 phys = <&pcie0_phy>; 8682 phy-names = "pciephy"; 8683 8684 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 8685 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 8686 8687 status = "disabled"; 8688 8689 pcieport0: pcie@0 { 8690 device_type = "pci"; 8691 reg = <0x0 0x0 0x0 0x0 0x0>; 8692 bus-range = <0x01 0xff>; 8693 8694 #address-cells = <3>; 8695 #size-cells = <2>; 8696 ranges; 8697 }; 8698 }; 8699 8700 pcie0_ep: pcie-ep@1c00000 { 8701 compatible = "qcom,sa8775p-pcie-ep"; 8702 reg = <0x0 0x01c00000 0x0 0x3000>, 8703 <0x0 0x40000000 0x0 0xf20>, 8704 <0x0 0x40000f20 0x0 0xa8>, 8705 <0x0 0x40001000 0x0 0x4000>, 8706 <0x0 0x40200000 0x0 0x1fe00000>, 8707 <0x0 0x01c03000 0x0 0x1000>, 8708 <0x0 0x40005000 0x0 0x2000>; 8709 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 8710 "mmio", "dma"; 8711 8712 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 8713 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 8714 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 8715 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 8716 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 8717 8718 clock-names = "aux", 8719 "cfg", 8720 "bus_master", 8721 "bus_slave", 8722 "slave_q2a"; 8723 8724 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 8725 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 8726 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; 8727 8728 interrupt-names = "global", "doorbell", "dma"; 8729 8730 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 8731 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 8732 interconnect-names = "pcie-mem", "cpu-pcie"; 8733 8734 dma-coherent; 8735 iommus = <&pcie_smmu 0x0000 0x7f>; 8736 resets = <&gcc GCC_PCIE_0_BCR>; 8737 reset-names = "core"; 8738 power-domains = <&gcc PCIE_0_GDSC>; 8739 phys = <&pcie0_phy>; 8740 phy-names = "pciephy"; 8741 num-lanes = <2>; 8742 linux,pci-domain = <0>; 8743 8744 status = "disabled"; 8745 }; 8746 8747 pcie0_phy: phy@1c04000 { 8748 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 8749 reg = <0x0 0x1c04000 0x0 0x2000>; 8750 8751 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, 8752 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 8753 <&gcc GCC_PCIE_CLKREF_EN>, 8754 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 8755 <&gcc GCC_PCIE_0_PIPE_CLK>, 8756 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; 8757 clock-names = "aux", 8758 "cfg_ahb", 8759 "ref", 8760 "rchng", 8761 "pipe", 8762 "pipediv2"; 8763 8764 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 8765 assigned-clock-rates = <100000000>; 8766 8767 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 8768 reset-names = "phy"; 8769 8770 #clock-cells = <0>; 8771 clock-output-names = "pcie_0_pipe_clk"; 8772 8773 #phy-cells = <0>; 8774 8775 status = "disabled"; 8776 }; 8777 8778 pcie1: pcie@1c10000 { 8779 compatible = "qcom,pcie-sa8775p"; 8780 reg = <0x0 0x01c10000 0x0 0x3000>, 8781 <0x0 0x60000000 0x0 0xf20>, 8782 <0x0 0x60000f20 0x0 0xa8>, 8783 <0x0 0x60001000 0x0 0x4000>, 8784 <0x0 0x60100000 0x0 0x100000>, 8785 <0x0 0x01c13000 0x0 0x1000>; 8786 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 8787 device_type = "pci"; 8788 8789 #address-cells = <3>; 8790 #size-cells = <2>; 8791 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 8792 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 8793 bus-range = <0x00 0xff>; 8794 8795 dma-coherent; 8796 8797 linux,pci-domain = <1>; 8798 num-lanes = <4>; 8799 8800 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 8801 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 8802 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 8803 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 8804 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 8805 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 8806 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 8807 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 8808 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; 8809 interrupt-names = "msi0", 8810 "msi1", 8811 "msi2", 8812 "msi3", 8813 "msi4", 8814 "msi5", 8815 "msi6", 8816 "msi7", 8817 "global"; 8818 #interrupt-cells = <1>; 8819 interrupt-map-mask = <0 0 0 0x7>; 8820 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 8821 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 8822 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 8823 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 8824 8825 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 8826 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 8827 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 8828 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 8829 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 8830 8831 clock-names = "aux", 8832 "cfg", 8833 "bus_master", 8834 "bus_slave", 8835 "slave_q2a"; 8836 8837 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 8838 assigned-clock-rates = <19200000>; 8839 8840 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 8841 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 8842 interconnect-names = "pcie-mem", "cpu-pcie"; 8843 8844 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 8845 <0x100 &pcie_smmu 0x0081 0x1>; 8846 8847 resets = <&gcc GCC_PCIE_1_BCR>, 8848 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 8849 reset-names = "pci", 8850 "link_down"; 8851 8852 power-domains = <&gcc PCIE_1_GDSC>; 8853 8854 phys = <&pcie1_phy>; 8855 phy-names = "pciephy"; 8856 8857 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 8858 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 8859 8860 status = "disabled"; 8861 8862 pcie@0 { 8863 device_type = "pci"; 8864 reg = <0x0 0x0 0x0 0x0 0x0>; 8865 bus-range = <0x01 0xff>; 8866 8867 #address-cells = <3>; 8868 #size-cells = <2>; 8869 ranges; 8870 }; 8871 }; 8872 8873 pcie1_ep: pcie-ep@1c10000 { 8874 compatible = "qcom,sa8775p-pcie-ep"; 8875 reg = <0x0 0x01c10000 0x0 0x3000>, 8876 <0x0 0x60000000 0x0 0xf20>, 8877 <0x0 0x60000f20 0x0 0xa8>, 8878 <0x0 0x60001000 0x0 0x4000>, 8879 <0x0 0x60200000 0x0 0x1fe00000>, 8880 <0x0 0x01c13000 0x0 0x1000>, 8881 <0x0 0x60005000 0x0 0x2000>; 8882 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 8883 "mmio", "dma"; 8884 8885 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 8886 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 8887 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 8888 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 8889 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 8890 8891 clock-names = "aux", 8892 "cfg", 8893 "bus_master", 8894 "bus_slave", 8895 "slave_q2a"; 8896 8897 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 8898 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 8899 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 8900 8901 interrupt-names = "global", "doorbell", "dma"; 8902 8903 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 8904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 8905 interconnect-names = "pcie-mem", "cpu-pcie"; 8906 8907 dma-coherent; 8908 iommus = <&pcie_smmu 0x80 0x7f>; 8909 resets = <&gcc GCC_PCIE_1_BCR>; 8910 reset-names = "core"; 8911 power-domains = <&gcc PCIE_1_GDSC>; 8912 phys = <&pcie1_phy>; 8913 phy-names = "pciephy"; 8914 num-lanes = <4>; 8915 linux,pci-domain = <1>; 8916 8917 status = "disabled"; 8918 }; 8919 8920 pcie1_phy: phy@1c14000 { 8921 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 8922 reg = <0x0 0x1c14000 0x0 0x4000>; 8923 8924 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 8925 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 8926 <&gcc GCC_PCIE_CLKREF_EN>, 8927 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 8928 <&gcc GCC_PCIE_1_PIPE_CLK>, 8929 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; 8930 clock-names = "aux", 8931 "cfg_ahb", 8932 "ref", 8933 "rchng", 8934 "pipe", 8935 "pipediv2"; 8936 8937 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 8938 assigned-clock-rates = <100000000>; 8939 8940 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 8941 reset-names = "phy"; 8942 8943 #clock-cells = <0>; 8944 clock-output-names = "pcie_1_pipe_clk"; 8945 8946 #phy-cells = <0>; 8947 8948 status = "disabled"; 8949 }; 8950}; 8951