1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#include <dt-bindings/interconnect/qcom,icc.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 12#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 13#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 14#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 15#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/firmware/qcom,scm.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 clocks { 33 xo_board_clk: xo-board-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "qcom,kryo"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 power-domains = <&cpu_pd0>; 54 power-domain-names = "psci"; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 next-level-cache = <&l2_0>; 57 capacity-dmips-mhz = <1024>; 58 #cooling-cells = <2>; 59 dynamic-power-coefficient = <100>; 60 operating-points-v2 = <&cpu0_opp_table>; 61 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 62 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 63 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 64 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 65 l2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&l3_0>; 70 l3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 cpu1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo"; 81 reg = <0x0 0x100>; 82 enable-method = "psci"; 83 power-domains = <&cpu_pd1>; 84 power-domain-names = "psci"; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 next-level-cache = <&l2_1>; 87 capacity-dmips-mhz = <1024>; 88 #cooling-cells = <2>; 89 dynamic-power-coefficient = <100>; 90 operating-points-v2 = <&cpu0_opp_table>; 91 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 92 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 93 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 94 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 95 l2_1: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 next-level-cache = <&l3_0>; 100 }; 101 }; 102 103 cpu2: cpu@200 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo"; 106 reg = <0x0 0x200>; 107 enable-method = "psci"; 108 power-domains = <&cpu_pd2>; 109 power-domain-names = "psci"; 110 qcom,freq-domain = <&cpufreq_hw 0>; 111 next-level-cache = <&l2_2>; 112 capacity-dmips-mhz = <1024>; 113 #cooling-cells = <2>; 114 dynamic-power-coefficient = <100>; 115 operating-points-v2 = <&cpu0_opp_table>; 116 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 117 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 118 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 119 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 120 l2_2: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 cache-unified; 124 next-level-cache = <&l3_0>; 125 }; 126 }; 127 128 cpu3: cpu@300 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo"; 131 reg = <0x0 0x300>; 132 enable-method = "psci"; 133 power-domains = <&cpu_pd3>; 134 power-domain-names = "psci"; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 next-level-cache = <&l2_3>; 137 capacity-dmips-mhz = <1024>; 138 #cooling-cells = <2>; 139 dynamic-power-coefficient = <100>; 140 operating-points-v2 = <&cpu0_opp_table>; 141 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 143 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 144 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 145 l2_3: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&l3_0>; 150 }; 151 }; 152 153 cpu4: cpu@10000 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo"; 156 reg = <0x0 0x10000>; 157 enable-method = "psci"; 158 power-domains = <&cpu_pd4>; 159 power-domain-names = "psci"; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 next-level-cache = <&l2_4>; 162 capacity-dmips-mhz = <1024>; 163 #cooling-cells = <2>; 164 dynamic-power-coefficient = <100>; 165 operating-points-v2 = <&cpu4_opp_table>; 166 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 167 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 168 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 169 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 170 l2_4: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_1>; 175 l3_1: l3-cache { 176 compatible = "cache"; 177 cache-level = <3>; 178 cache-unified; 179 }; 180 181 }; 182 }; 183 184 cpu5: cpu@10100 { 185 device_type = "cpu"; 186 compatible = "qcom,kryo"; 187 reg = <0x0 0x10100>; 188 enable-method = "psci"; 189 power-domains = <&cpu_pd5>; 190 power-domain-names = "psci"; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 next-level-cache = <&l2_5>; 193 capacity-dmips-mhz = <1024>; 194 #cooling-cells = <2>; 195 dynamic-power-coefficient = <100>; 196 operating-points-v2 = <&cpu4_opp_table>; 197 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 198 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 199 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 200 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 201 l2_5: l2-cache { 202 compatible = "cache"; 203 cache-level = <2>; 204 cache-unified; 205 next-level-cache = <&l3_1>; 206 }; 207 }; 208 209 cpu6: cpu@10200 { 210 device_type = "cpu"; 211 compatible = "qcom,kryo"; 212 reg = <0x0 0x10200>; 213 enable-method = "psci"; 214 power-domains = <&cpu_pd6>; 215 power-domain-names = "psci"; 216 qcom,freq-domain = <&cpufreq_hw 1>; 217 next-level-cache = <&l2_6>; 218 capacity-dmips-mhz = <1024>; 219 #cooling-cells = <2>; 220 dynamic-power-coefficient = <100>; 221 operating-points-v2 = <&cpu4_opp_table>; 222 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 223 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 224 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 225 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 226 l2_6: l2-cache { 227 compatible = "cache"; 228 cache-level = <2>; 229 cache-unified; 230 next-level-cache = <&l3_1>; 231 }; 232 }; 233 234 cpu7: cpu@10300 { 235 device_type = "cpu"; 236 compatible = "qcom,kryo"; 237 reg = <0x0 0x10300>; 238 enable-method = "psci"; 239 power-domains = <&cpu_pd7>; 240 power-domain-names = "psci"; 241 qcom,freq-domain = <&cpufreq_hw 1>; 242 next-level-cache = <&l2_7>; 243 capacity-dmips-mhz = <1024>; 244 #cooling-cells = <2>; 245 dynamic-power-coefficient = <100>; 246 operating-points-v2 = <&cpu4_opp_table>; 247 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 248 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 249 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 250 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 251 l2_7: l2-cache { 252 compatible = "cache"; 253 cache-level = <2>; 254 cache-unified; 255 next-level-cache = <&l3_1>; 256 }; 257 }; 258 259 cpu-map { 260 cluster0 { 261 core0 { 262 cpu = <&cpu0>; 263 }; 264 265 core1 { 266 cpu = <&cpu1>; 267 }; 268 269 core2 { 270 cpu = <&cpu2>; 271 }; 272 273 core3 { 274 cpu = <&cpu3>; 275 }; 276 }; 277 278 cluster1 { 279 core0 { 280 cpu = <&cpu4>; 281 }; 282 283 core1 { 284 cpu = <&cpu5>; 285 }; 286 287 core2 { 288 cpu = <&cpu6>; 289 }; 290 291 core3 { 292 cpu = <&cpu7>; 293 }; 294 }; 295 }; 296 297 idle-states { 298 entry-method = "psci"; 299 300 gold_rail_cpu_sleep_0: cpu-sleep-0 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "gold-rail-power-collapse"; 303 arm,psci-suspend-param = <0x40000004>; 304 entry-latency-us = <702>; 305 exit-latency-us = <1061>; 306 min-residency-us = <4488>; 307 local-timer-stop; 308 }; 309 }; 310 311 domain-idle-states { 312 cluster_sleep_gold: cluster-sleep-0 { 313 compatible = "domain-idle-state"; 314 arm,psci-suspend-param = <0x41000044>; 315 entry-latency-us = <2752>; 316 exit-latency-us = <3048>; 317 min-residency-us = <6118>; 318 }; 319 320 cluster_sleep_apss_rsc_pc: cluster-sleep-1 { 321 compatible = "domain-idle-state"; 322 arm,psci-suspend-param = <0x42000144>; 323 entry-latency-us = <3263>; 324 exit-latency-us = <6562>; 325 min-residency-us = <9987>; 326 }; 327 }; 328 }; 329 330 cpu0_opp_table: opp-table-cpu0 { 331 compatible = "operating-points-v2"; 332 opp-shared; 333 334 opp-1267200000 { 335 opp-hz = /bits/ 64 <1267200000>; 336 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 337 }; 338 339 opp-1363200000 { 340 opp-hz = /bits/ 64 <1363200000>; 341 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 342 }; 343 344 opp-1459200000 { 345 opp-hz = /bits/ 64 <1459200000>; 346 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 347 }; 348 349 opp-1536000000 { 350 opp-hz = /bits/ 64 <1536000000>; 351 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 352 }; 353 354 opp-1632000000 { 355 opp-hz = /bits/ 64 <1632000000>; 356 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 357 }; 358 359 opp-1708800000 { 360 opp-hz = /bits/ 64 <1708800000>; 361 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 362 }; 363 364 opp-1785600000 { 365 opp-hz = /bits/ 64 <1785600000>; 366 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 367 }; 368 369 opp-1862400000 { 370 opp-hz = /bits/ 64 <1862400000>; 371 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 372 }; 373 374 opp-1939200000 { 375 opp-hz = /bits/ 64 <1939200000>; 376 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 377 }; 378 379 opp-2016000000 { 380 opp-hz = /bits/ 64 <2016000000>; 381 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 382 }; 383 384 opp-2112000000 { 385 opp-hz = /bits/ 64 <2112000000>; 386 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 387 }; 388 389 opp-2188800000 { 390 opp-hz = /bits/ 64 <2188800000>; 391 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 392 }; 393 394 opp-2265600000 { 395 opp-hz = /bits/ 64 <2265600000>; 396 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 397 }; 398 399 opp-2361600000 { 400 opp-hz = /bits/ 64 <2361600000>; 401 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 402 }; 403 404 opp-2457600000 { 405 opp-hz = /bits/ 64 <2457600000>; 406 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 407 }; 408 409 opp-2553600000 { 410 opp-hz = /bits/ 64 <2553600000>; 411 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 412 }; 413 }; 414 415 cpu4_opp_table: opp-table-cpu4 { 416 compatible = "operating-points-v2"; 417 opp-shared; 418 419 opp-1267200000 { 420 opp-hz = /bits/ 64 <1267200000>; 421 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 422 }; 423 424 opp-1363200000 { 425 opp-hz = /bits/ 64 <1363200000>; 426 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 427 }; 428 429 opp-1459200000 { 430 opp-hz = /bits/ 64 <1459200000>; 431 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 432 }; 433 434 opp-1536000000 { 435 opp-hz = /bits/ 64 <1536000000>; 436 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 437 }; 438 439 opp-1632000000 { 440 opp-hz = /bits/ 64 <1632000000>; 441 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 442 }; 443 444 opp-1708800000 { 445 opp-hz = /bits/ 64 <1708800000>; 446 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 447 }; 448 449 opp-1785600000 { 450 opp-hz = /bits/ 64 <1785600000>; 451 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 452 }; 453 454 opp-1862400000 { 455 opp-hz = /bits/ 64 <1862400000>; 456 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 457 }; 458 459 opp-1939200000 { 460 opp-hz = /bits/ 64 <1939200000>; 461 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 462 }; 463 464 opp-2016000000 { 465 opp-hz = /bits/ 64 <2016000000>; 466 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 467 }; 468 469 opp-2112000000 { 470 opp-hz = /bits/ 64 <2112000000>; 471 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 472 }; 473 474 opp-2188800000 { 475 opp-hz = /bits/ 64 <2188800000>; 476 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 477 }; 478 479 opp-2265600000 { 480 opp-hz = /bits/ 64 <2265600000>; 481 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 482 }; 483 484 opp-2361600000 { 485 opp-hz = /bits/ 64 <2361600000>; 486 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 487 }; 488 489 opp-2457600000 { 490 opp-hz = /bits/ 64 <2457600000>; 491 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 492 }; 493 494 opp-2553600000 { 495 opp-hz = /bits/ 64 <2553600000>; 496 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 497 }; 498 }; 499 500 dummy-sink { 501 compatible = "arm,coresight-dummy-sink"; 502 503 in-ports { 504 port { 505 eud_in: endpoint { 506 remote-endpoint = 507 <&swao_rep_out1>; 508 }; 509 }; 510 }; 511 }; 512 513 firmware { 514 scm { 515 compatible = "qcom,scm-sa8775p", "qcom,scm"; 516 qcom,dload-mode = <&tcsr 0x13000>; 517 sram = <&minidump_config>; 518 }; 519 }; 520 521 clk_virt: interconnect-clk-virt { 522 compatible = "qcom,sa8775p-clk-virt"; 523 #interconnect-cells = <2>; 524 qcom,bcm-voters = <&apps_bcm_voter>; 525 }; 526 527 mc_virt: interconnect-mc-virt { 528 compatible = "qcom,sa8775p-mc-virt"; 529 #interconnect-cells = <2>; 530 qcom,bcm-voters = <&apps_bcm_voter>; 531 }; 532 533 /* Will be updated by the bootloader. */ 534 memory@80000000 { 535 device_type = "memory"; 536 reg = <0x0 0x80000000 0x0 0x0>; 537 }; 538 539 qup_opp_table_100mhz: opp-table-qup100mhz { 540 compatible = "operating-points-v2"; 541 542 opp-100000000 { 543 opp-hz = /bits/ 64 <100000000>; 544 required-opps = <&rpmhpd_opp_svs_l1>; 545 }; 546 }; 547 548 pmu { 549 compatible = "arm,armv8-pmuv3"; 550 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 551 }; 552 553 psci { 554 compatible = "arm,psci-1.0"; 555 method = "smc"; 556 557 cpu_pd0: power-domain-cpu0 { 558 #power-domain-cells = <0>; 559 power-domains = <&cluster_0_pd>; 560 domain-idle-states = <&gold_rail_cpu_sleep_0>; 561 }; 562 563 cpu_pd1: power-domain-cpu1 { 564 #power-domain-cells = <0>; 565 power-domains = <&cluster_0_pd>; 566 domain-idle-states = <&gold_rail_cpu_sleep_0>; 567 }; 568 569 cpu_pd2: power-domain-cpu2 { 570 #power-domain-cells = <0>; 571 power-domains = <&cluster_0_pd>; 572 domain-idle-states = <&gold_rail_cpu_sleep_0>; 573 }; 574 575 cpu_pd3: power-domain-cpu3 { 576 #power-domain-cells = <0>; 577 power-domains = <&cluster_0_pd>; 578 domain-idle-states = <&gold_rail_cpu_sleep_0>; 579 }; 580 581 cpu_pd4: power-domain-cpu4 { 582 #power-domain-cells = <0>; 583 power-domains = <&cluster_1_pd>; 584 domain-idle-states = <&gold_rail_cpu_sleep_0>; 585 }; 586 587 cpu_pd5: power-domain-cpu5 { 588 #power-domain-cells = <0>; 589 power-domains = <&cluster_1_pd>; 590 domain-idle-states = <&gold_rail_cpu_sleep_0>; 591 }; 592 593 cpu_pd6: power-domain-cpu6 { 594 #power-domain-cells = <0>; 595 power-domains = <&cluster_1_pd>; 596 domain-idle-states = <&gold_rail_cpu_sleep_0>; 597 }; 598 599 cpu_pd7: power-domain-cpu7 { 600 #power-domain-cells = <0>; 601 power-domains = <&cluster_1_pd>; 602 domain-idle-states = <&gold_rail_cpu_sleep_0>; 603 }; 604 605 cluster_0_pd: power-domain-cluster0 { 606 #power-domain-cells = <0>; 607 domain-idle-states = <&cluster_sleep_gold>; 608 power-domains = <&system_pd>; 609 }; 610 611 cluster_1_pd: power-domain-cluster1 { 612 #power-domain-cells = <0>; 613 domain-idle-states = <&cluster_sleep_gold>; 614 power-domains = <&system_pd>; 615 }; 616 617 system_pd: power-domain-system { 618 #power-domain-cells = <0>; 619 domain-idle-states = <&cluster_sleep_apss_rsc_pc>; 620 }; 621 }; 622 623 reserved-memory { 624 #address-cells = <2>; 625 #size-cells = <2>; 626 ranges; 627 628 sail_ss_mem: sail-ss@80000000 { 629 reg = <0x0 0x80000000 0x0 0x10000000>; 630 no-map; 631 }; 632 633 hyp_mem: hyp@90000000 { 634 reg = <0x0 0x90000000 0x0 0x600000>; 635 no-map; 636 }; 637 638 xbl_boot_mem: xbl-boot@90600000 { 639 reg = <0x0 0x90600000 0x0 0x200000>; 640 no-map; 641 }; 642 643 aop_image_mem: aop-image@90800000 { 644 reg = <0x0 0x90800000 0x0 0x60000>; 645 no-map; 646 }; 647 648 aop_cmd_db_mem: aop-cmd-db@90860000 { 649 compatible = "qcom,cmd-db"; 650 reg = <0x0 0x90860000 0x0 0x20000>; 651 no-map; 652 }; 653 654 uefi_log: uefi-log@908b0000 { 655 reg = <0x0 0x908b0000 0x0 0x10000>; 656 no-map; 657 }; 658 659 ddr_training_checksum: ddr-training-checksum@908c0000 { 660 reg = <0x0 0x908c0000 0x0 0x1000>; 661 no-map; 662 }; 663 664 reserved_mem: reserved@908f0000 { 665 reg = <0x0 0x908f0000 0x0 0xe000>; 666 no-map; 667 }; 668 669 secdata_apss_mem: secdata-apss@908fe000 { 670 reg = <0x0 0x908fe000 0x0 0x2000>; 671 no-map; 672 }; 673 674 smem_mem: smem@90900000 { 675 compatible = "qcom,smem"; 676 reg = <0x0 0x90900000 0x0 0x200000>; 677 no-map; 678 hwlocks = <&tcsr_mutex 3>; 679 }; 680 681 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { 682 reg = <0x0 0x90c00000 0x0 0x100000>; 683 no-map; 684 }; 685 686 sail_mailbox_mem: sail-ss@90d00000 { 687 reg = <0x0 0x90d00000 0x0 0x100000>; 688 no-map; 689 }; 690 691 sail_ota_mem: sail-ss@90e00000 { 692 reg = <0x0 0x90e00000 0x0 0x300000>; 693 no-map; 694 }; 695 696 gunyah_md_mem: gunyah-md@91a80000 { 697 reg = <0x0 0x91a80000 0x0 0x80000>; 698 no-map; 699 }; 700 701 aoss_backup_mem: aoss-backup@91b00000 { 702 reg = <0x0 0x91b00000 0x0 0x40000>; 703 no-map; 704 }; 705 706 cpucp_backup_mem: cpucp-backup@91b40000 { 707 reg = <0x0 0x91b40000 0x0 0x40000>; 708 no-map; 709 }; 710 711 tz_config_backup_mem: tz-config-backup@91b80000 { 712 reg = <0x0 0x91b80000 0x0 0x10000>; 713 no-map; 714 }; 715 716 ddr_training_data_mem: ddr-training-data@91b90000 { 717 reg = <0x0 0x91b90000 0x0 0x10000>; 718 no-map; 719 }; 720 721 cdt_data_backup_mem: cdt-data-backup@91ba0000 { 722 reg = <0x0 0x91ba0000 0x0 0x1000>; 723 no-map; 724 }; 725 726 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 727 reg = <0x0 0x93b00000 0x0 0xf00000>; 728 no-map; 729 }; 730 731 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 732 reg = <0x0 0x94a00000 0x0 0x800000>; 733 no-map; 734 }; 735 736 pil_camera_mem: pil-camera@95200000 { 737 reg = <0x0 0x95200000 0x0 0x700000>; 738 no-map; 739 }; 740 741 pil_adsp_mem: pil-adsp@95900000 { 742 reg = <0x0 0x95900000 0x0 0x1e00000>; 743 no-map; 744 }; 745 746 q6_adsp_dtb_mem: q6-adsp-dtb@97700000 { 747 reg = <0x0 0x97700000 0x0 0x80000>; 748 no-map; 749 }; 750 751 q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 { 752 reg = <0x0 0x97780000 0x0 0x80000>; 753 no-map; 754 }; 755 756 pil_gdsp0_mem: pil-gdsp0@97800000 { 757 reg = <0x0 0x97800000 0x0 0x1e00000>; 758 no-map; 759 }; 760 761 pil_gdsp1_mem: pil-gdsp1@99600000 { 762 reg = <0x0 0x99600000 0x0 0x1e00000>; 763 no-map; 764 }; 765 766 q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 { 767 reg = <0x0 0x9b400000 0x0 0x80000>; 768 no-map; 769 }; 770 771 q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 { 772 reg = <0x0 0x9b480000 0x0 0x80000>; 773 no-map; 774 }; 775 776 pil_cdsp0_mem: pil-cdsp0@9b500000 { 777 reg = <0x0 0x9b500000 0x0 0x1e00000>; 778 no-map; 779 }; 780 781 pil_gpu_mem: pil-gpu@9d300000 { 782 reg = <0x0 0x9d300000 0x0 0x2000>; 783 no-map; 784 }; 785 786 q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 { 787 reg = <0x0 0x9d380000 0x0 0x80000>; 788 no-map; 789 }; 790 791 pil_cdsp1_mem: pil-cdsp1@9d400000 { 792 reg = <0x0 0x9d400000 0x0 0x1e00000>; 793 no-map; 794 }; 795 796 pil_cvp_mem: pil-cvp@9f200000 { 797 reg = <0x0 0x9f200000 0x0 0x700000>; 798 no-map; 799 }; 800 801 pil_video_mem: pil-video@9f900000 { 802 reg = <0x0 0x9f900000 0x0 0x1000000>; 803 no-map; 804 }; 805 806 firmware_mem: firmware-region@b0000000 { 807 reg = <0x0 0xb0000000 0x0 0x800000>; 808 no-map; 809 }; 810 811 scmi_mem: scmi-region@d0000000 { 812 reg = <0x0 0xd0000000 0x0 0x40000>; 813 no-map; 814 }; 815 816 firmware_logs_mem: firmware-logs@d0040000 { 817 reg = <0x0 0xd0040000 0x0 0x10000>; 818 no-map; 819 }; 820 821 firmware_audio_mem: firmware-audio@d0050000 { 822 reg = <0x0 0xd0050000 0x0 0x4000>; 823 no-map; 824 }; 825 826 firmware_reserved_mem: firmware-reserved@d0054000 { 827 reg = <0x0 0xd0054000 0x0 0x9c000>; 828 no-map; 829 }; 830 831 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { 832 reg = <0x0 0xd00f0000 0x0 0x10000>; 833 no-map; 834 }; 835 836 tags_mem: tags@d0100000 { 837 reg = <0x0 0xd0100000 0x0 0x1200000>; 838 no-map; 839 }; 840 841 qtee_mem: qtee@d1300000 { 842 reg = <0x0 0xd1300000 0x0 0x500000>; 843 no-map; 844 }; 845 846 deepsleep_backup_mem: deepsleep-backup@d1800000 { 847 reg = <0x0 0xd1800000 0x0 0x100000>; 848 no-map; 849 }; 850 851 trusted_apps_mem: trusted-apps@d1900000 { 852 reg = <0x0 0xd1900000 0x0 0x1c00000>; 853 no-map; 854 }; 855 856 tz_stat_mem: tz-stat@db100000 { 857 reg = <0x0 0xdb100000 0x0 0x100000>; 858 no-map; 859 }; 860 861 cpucp_fw_mem: cpucp-fw@db200000 { 862 reg = <0x0 0xdb200000 0x0 0x100000>; 863 no-map; 864 }; 865 }; 866 867 smp2p-adsp { 868 compatible = "qcom,smp2p"; 869 qcom,smem = <443>, <429>; 870 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 871 IPCC_MPROC_SIGNAL_SMP2P 872 IRQ_TYPE_EDGE_RISING>; 873 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 874 875 qcom,local-pid = <0>; 876 qcom,remote-pid = <2>; 877 878 smp2p_adsp_out: master-kernel { 879 qcom,entry-name = "master-kernel"; 880 #qcom,smem-state-cells = <1>; 881 }; 882 883 smp2p_adsp_in: slave-kernel { 884 qcom,entry-name = "slave-kernel"; 885 interrupt-controller; 886 #interrupt-cells = <2>; 887 }; 888 }; 889 890 smp2p-cdsp0 { 891 compatible = "qcom,smp2p"; 892 qcom,smem = <94>, <432>; 893 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 894 IPCC_MPROC_SIGNAL_SMP2P 895 IRQ_TYPE_EDGE_RISING>; 896 mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 897 898 qcom,local-pid = <0>; 899 qcom,remote-pid = <5>; 900 901 smp2p_cdsp0_out: master-kernel { 902 qcom,entry-name = "master-kernel"; 903 #qcom,smem-state-cells = <1>; 904 }; 905 906 smp2p_cdsp0_in: slave-kernel { 907 qcom,entry-name = "slave-kernel"; 908 interrupt-controller; 909 #interrupt-cells = <2>; 910 }; 911 }; 912 913 smp2p-cdsp1 { 914 compatible = "qcom,smp2p"; 915 qcom,smem = <617>, <616>; 916 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 917 IPCC_MPROC_SIGNAL_SMP2P 918 IRQ_TYPE_EDGE_RISING>; 919 mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; 920 921 qcom,local-pid = <0>; 922 qcom,remote-pid = <12>; 923 924 smp2p_cdsp1_out: master-kernel { 925 qcom,entry-name = "master-kernel"; 926 #qcom,smem-state-cells = <1>; 927 }; 928 929 smp2p_cdsp1_in: slave-kernel { 930 qcom,entry-name = "slave-kernel"; 931 interrupt-controller; 932 #interrupt-cells = <2>; 933 }; 934 }; 935 936 smp2p-gpdsp0 { 937 compatible = "qcom,smp2p"; 938 qcom,smem = <617>, <616>; 939 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 940 IPCC_MPROC_SIGNAL_SMP2P 941 IRQ_TYPE_EDGE_RISING>; 942 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; 943 944 qcom,local-pid = <0>; 945 qcom,remote-pid = <17>; 946 947 smp2p_gpdsp0_out: master-kernel { 948 qcom,entry-name = "master-kernel"; 949 #qcom,smem-state-cells = <1>; 950 }; 951 952 smp2p_gpdsp0_in: slave-kernel { 953 qcom,entry-name = "slave-kernel"; 954 interrupt-controller; 955 #interrupt-cells = <2>; 956 }; 957 }; 958 959 smp2p-gpdsp1 { 960 compatible = "qcom,smp2p"; 961 qcom,smem = <617>, <616>; 962 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 963 IPCC_MPROC_SIGNAL_SMP2P 964 IRQ_TYPE_EDGE_RISING>; 965 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>; 966 967 qcom,local-pid = <0>; 968 qcom,remote-pid = <18>; 969 970 smp2p_gpdsp1_out: master-kernel { 971 qcom,entry-name = "master-kernel"; 972 #qcom,smem-state-cells = <1>; 973 }; 974 975 smp2p_gpdsp1_in: slave-kernel { 976 qcom,entry-name = "slave-kernel"; 977 interrupt-controller; 978 #interrupt-cells = <2>; 979 }; 980 }; 981 982 soc: soc@0 { 983 compatible = "simple-bus"; 984 #address-cells = <2>; 985 #size-cells = <2>; 986 ranges = <0 0 0 0 0x10 0>; 987 988 gcc: clock-controller@100000 { 989 compatible = "qcom,sa8775p-gcc"; 990 reg = <0x0 0x00100000 0x0 0xc7018>; 991 #clock-cells = <1>; 992 #reset-cells = <1>; 993 #power-domain-cells = <1>; 994 clocks = <&rpmhcc RPMH_CXO_CLK>, 995 <&sleep_clk>, 996 <0>, 997 <0>, 998 <0>, 999 <&usb_0_qmpphy>, 1000 <&usb_1_qmpphy>, 1001 <0>, 1002 <0>, 1003 <0>, 1004 <&pcie0_phy>, 1005 <&pcie1_phy>, 1006 <0>, 1007 <0>, 1008 <0>; 1009 power-domains = <&rpmhpd SA8775P_CX>; 1010 }; 1011 1012 ipcc: mailbox@408000 { 1013 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 1014 reg = <0x0 0x00408000 0x0 0x1000>; 1015 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1016 interrupt-controller; 1017 #interrupt-cells = <3>; 1018 #mbox-cells = <2>; 1019 }; 1020 1021 qfprom: efuse@784000 { 1022 compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; 1023 reg = <0x0 0x00784000 0x0 0x3000>; 1024 #address-cells = <1>; 1025 #size-cells = <1>; 1026 1027 gpu_speed_bin: gpu-speed-bin@240c { 1028 reg = <0x240c 0x1>; 1029 bits = <0 8>; 1030 }; 1031 }; 1032 1033 gpi_dma2: dma-controller@800000 { 1034 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1035 reg = <0x0 0x00800000 0x0 0x60000>; 1036 #dma-cells = <3>; 1037 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1049 dma-channels = <12>; 1050 dma-channel-mask = <0xfff>; 1051 iommus = <&apps_smmu 0x5b6 0x0>; 1052 status = "disabled"; 1053 }; 1054 1055 qupv3_id_2: geniqup@8c0000 { 1056 compatible = "qcom,geni-se-qup"; 1057 reg = <0x0 0x008c0000 0x0 0x6000>; 1058 ranges; 1059 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1060 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1061 clock-names = "m-ahb", "s-ahb"; 1062 iommus = <&apps_smmu 0x5a3 0x0>; 1063 #address-cells = <2>; 1064 #size-cells = <2>; 1065 status = "disabled"; 1066 1067 i2c14: i2c@880000 { 1068 compatible = "qcom,geni-i2c"; 1069 reg = <0x0 0x880000 0x0 0x4000>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1073 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1074 clock-names = "se"; 1075 pinctrl-0 = <&qup_i2c14_default>; 1076 pinctrl-names = "default"; 1077 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1078 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1079 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1080 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1081 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1082 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1083 interconnect-names = "qup-core", 1084 "qup-config", 1085 "qup-memory"; 1086 power-domains = <&rpmhpd SA8775P_CX>; 1087 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1088 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1089 dma-names = "tx", 1090 "rx"; 1091 status = "disabled"; 1092 }; 1093 1094 spi14: spi@880000 { 1095 compatible = "qcom,geni-spi"; 1096 reg = <0x0 0x880000 0x0 0x4000>; 1097 #address-cells = <1>; 1098 #size-cells = <0>; 1099 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1101 clock-names = "se"; 1102 pinctrl-0 = <&qup_spi14_default>; 1103 pinctrl-names = "default"; 1104 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1105 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1106 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1107 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1108 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1109 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1110 interconnect-names = "qup-core", 1111 "qup-config", 1112 "qup-memory"; 1113 power-domains = <&rpmhpd SA8775P_CX>; 1114 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1115 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1116 dma-names = "tx", 1117 "rx"; 1118 status = "disabled"; 1119 }; 1120 1121 uart14: serial@880000 { 1122 compatible = "qcom,geni-uart"; 1123 reg = <0x0 0x00880000 0x0 0x4000>; 1124 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1126 clock-names = "se"; 1127 pinctrl-0 = <&qup_uart14_default>; 1128 pinctrl-names = "default"; 1129 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1130 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1131 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1132 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1133 interconnect-names = "qup-core", "qup-config"; 1134 power-domains = <&rpmhpd SA8775P_CX>; 1135 status = "disabled"; 1136 }; 1137 1138 i2c15: i2c@884000 { 1139 compatible = "qcom,geni-i2c"; 1140 reg = <0x0 0x884000 0x0 0x4000>; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1145 clock-names = "se"; 1146 pinctrl-0 = <&qup_i2c15_default>; 1147 pinctrl-names = "default"; 1148 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1149 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1150 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1151 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1152 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1153 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1154 interconnect-names = "qup-core", 1155 "qup-config", 1156 "qup-memory"; 1157 power-domains = <&rpmhpd SA8775P_CX>; 1158 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1159 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1160 dma-names = "tx", 1161 "rx"; 1162 status = "disabled"; 1163 }; 1164 1165 spi15: spi@884000 { 1166 compatible = "qcom,geni-spi"; 1167 reg = <0x0 0x884000 0x0 0x4000>; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1172 clock-names = "se"; 1173 pinctrl-0 = <&qup_spi15_default>; 1174 pinctrl-names = "default"; 1175 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1176 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1177 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1178 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1179 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1180 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1181 interconnect-names = "qup-core", 1182 "qup-config", 1183 "qup-memory"; 1184 power-domains = <&rpmhpd SA8775P_CX>; 1185 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1186 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1187 dma-names = "tx", 1188 "rx"; 1189 status = "disabled"; 1190 }; 1191 1192 uart15: serial@884000 { 1193 compatible = "qcom,geni-uart"; 1194 reg = <0x0 0x00884000 0x0 0x4000>; 1195 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1196 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1197 clock-names = "se"; 1198 pinctrl-0 = <&qup_uart15_default>; 1199 pinctrl-names = "default"; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1201 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1202 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1203 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1204 interconnect-names = "qup-core", "qup-config"; 1205 power-domains = <&rpmhpd SA8775P_CX>; 1206 status = "disabled"; 1207 }; 1208 1209 i2c16: i2c@888000 { 1210 compatible = "qcom,geni-i2c"; 1211 reg = <0x0 0x888000 0x0 0x4000>; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1216 clock-names = "se"; 1217 pinctrl-0 = <&qup_i2c16_default>; 1218 pinctrl-names = "default"; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1220 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1221 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1222 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1223 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1224 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1225 interconnect-names = "qup-core", 1226 "qup-config", 1227 "qup-memory"; 1228 power-domains = <&rpmhpd SA8775P_CX>; 1229 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1230 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1231 dma-names = "tx", 1232 "rx"; 1233 status = "disabled"; 1234 }; 1235 1236 spi16: spi@888000 { 1237 compatible = "qcom,geni-spi"; 1238 reg = <0x0 0x00888000 0x0 0x4000>; 1239 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1241 clock-names = "se"; 1242 pinctrl-0 = <&qup_spi16_default>; 1243 pinctrl-names = "default"; 1244 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1245 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1246 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1247 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1248 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1249 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1250 interconnect-names = "qup-core", 1251 "qup-config", 1252 "qup-memory"; 1253 power-domains = <&rpmhpd SA8775P_CX>; 1254 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1255 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1256 dma-names = "tx", 1257 "rx"; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 1263 uart16: serial@888000 { 1264 compatible = "qcom,geni-uart"; 1265 reg = <0x0 0x00888000 0x0 0x4000>; 1266 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1267 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1268 clock-names = "se"; 1269 pinctrl-0 = <&qup_uart16_default>; 1270 pinctrl-names = "default"; 1271 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1272 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1273 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1274 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1275 interconnect-names = "qup-core", "qup-config"; 1276 power-domains = <&rpmhpd SA8775P_CX>; 1277 status = "disabled"; 1278 }; 1279 1280 i2c17: i2c@88c000 { 1281 compatible = "qcom,geni-i2c"; 1282 reg = <0x0 0x88c000 0x0 0x4000>; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1286 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1287 clock-names = "se"; 1288 pinctrl-0 = <&qup_i2c17_default>; 1289 pinctrl-names = "default"; 1290 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1291 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1292 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1293 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1294 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1295 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1296 interconnect-names = "qup-core", 1297 "qup-config", 1298 "qup-memory"; 1299 power-domains = <&rpmhpd SA8775P_CX>; 1300 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1301 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1302 dma-names = "tx", 1303 "rx"; 1304 status = "disabled"; 1305 }; 1306 1307 spi17: spi@88c000 { 1308 compatible = "qcom,geni-spi"; 1309 reg = <0x0 0x88c000 0x0 0x4000>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1313 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1314 clock-names = "se"; 1315 pinctrl-0 = <&qup_spi17_default>; 1316 pinctrl-names = "default"; 1317 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1318 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1319 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1320 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1321 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1322 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1323 interconnect-names = "qup-core", 1324 "qup-config", 1325 "qup-memory"; 1326 power-domains = <&rpmhpd SA8775P_CX>; 1327 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1328 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1329 dma-names = "tx", 1330 "rx"; 1331 status = "disabled"; 1332 }; 1333 1334 uart17: serial@88c000 { 1335 compatible = "qcom,geni-uart"; 1336 reg = <0x0 0x0088c000 0x0 0x4000>; 1337 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1338 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1339 clock-names = "se"; 1340 pinctrl-0 = <&qup_uart17_default>; 1341 pinctrl-names = "default"; 1342 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1343 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1344 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1345 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1346 interconnect-names = "qup-core", "qup-config"; 1347 power-domains = <&rpmhpd SA8775P_CX>; 1348 status = "disabled"; 1349 }; 1350 1351 i2c18: i2c@890000 { 1352 compatible = "qcom,geni-i2c"; 1353 reg = <0x0 0x00890000 0x0 0x4000>; 1354 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1355 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1356 clock-names = "se"; 1357 pinctrl-0 = <&qup_i2c18_default>; 1358 pinctrl-names = "default"; 1359 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1360 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1361 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1362 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1363 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1364 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1365 interconnect-names = "qup-core", 1366 "qup-config", 1367 "qup-memory"; 1368 power-domains = <&rpmhpd SA8775P_CX>; 1369 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1370 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1371 dma-names = "tx", 1372 "rx"; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 status = "disabled"; 1376 }; 1377 1378 spi18: spi@890000 { 1379 compatible = "qcom,geni-spi"; 1380 reg = <0x0 0x890000 0x0 0x4000>; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1385 clock-names = "se"; 1386 pinctrl-0 = <&qup_spi18_default>; 1387 pinctrl-names = "default"; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1389 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1390 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1391 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1392 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1393 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1394 interconnect-names = "qup-core", 1395 "qup-config", 1396 "qup-memory"; 1397 power-domains = <&rpmhpd SA8775P_CX>; 1398 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1399 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1400 dma-names = "tx", 1401 "rx"; 1402 status = "disabled"; 1403 }; 1404 1405 uart18: serial@890000 { 1406 compatible = "qcom,geni-uart"; 1407 reg = <0x0 0x00890000 0x0 0x4000>; 1408 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1409 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1410 clock-names = "se"; 1411 pinctrl-0 = <&qup_uart18_default>; 1412 pinctrl-names = "default"; 1413 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1414 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1415 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1416 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1417 interconnect-names = "qup-core", "qup-config"; 1418 power-domains = <&rpmhpd SA8775P_CX>; 1419 status = "disabled"; 1420 }; 1421 1422 i2c19: i2c@894000 { 1423 compatible = "qcom,geni-i2c"; 1424 reg = <0x0 0x894000 0x0 0x4000>; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1428 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1429 clock-names = "se"; 1430 pinctrl-0 = <&qup_i2c19_default>; 1431 pinctrl-names = "default"; 1432 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1433 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1434 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1435 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1436 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1437 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1438 interconnect-names = "qup-core", 1439 "qup-config", 1440 "qup-memory"; 1441 power-domains = <&rpmhpd SA8775P_CX>; 1442 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1443 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1444 dma-names = "tx", 1445 "rx"; 1446 status = "disabled"; 1447 }; 1448 1449 spi19: spi@894000 { 1450 compatible = "qcom,geni-spi"; 1451 reg = <0x0 0x894000 0x0 0x4000>; 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1455 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1456 clock-names = "se"; 1457 pinctrl-0 = <&qup_spi19_default>; 1458 pinctrl-names = "default"; 1459 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1460 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1461 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1462 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1463 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1464 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1465 interconnect-names = "qup-core", 1466 "qup-config", 1467 "qup-memory"; 1468 power-domains = <&rpmhpd SA8775P_CX>; 1469 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1470 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1471 dma-names = "tx", 1472 "rx"; 1473 status = "disabled"; 1474 }; 1475 1476 uart19: serial@894000 { 1477 compatible = "qcom,geni-uart"; 1478 reg = <0x0 0x00894000 0x0 0x4000>; 1479 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1480 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1481 clock-names = "se"; 1482 pinctrl-0 = <&qup_uart19_default>; 1483 pinctrl-names = "default"; 1484 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1485 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1486 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1487 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1488 interconnect-names = "qup-core", "qup-config"; 1489 power-domains = <&rpmhpd SA8775P_CX>; 1490 status = "disabled"; 1491 }; 1492 1493 i2c20: i2c@898000 { 1494 compatible = "qcom,geni-i2c"; 1495 reg = <0x0 0x898000 0x0 0x4000>; 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1499 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1500 clock-names = "se"; 1501 pinctrl-0 = <&qup_i2c20_default>; 1502 pinctrl-names = "default"; 1503 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1504 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1505 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1506 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1507 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1508 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1509 interconnect-names = "qup-core", 1510 "qup-config", 1511 "qup-memory"; 1512 power-domains = <&rpmhpd SA8775P_CX>; 1513 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1514 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1515 dma-names = "tx", 1516 "rx"; 1517 status = "disabled"; 1518 }; 1519 1520 spi20: spi@898000 { 1521 compatible = "qcom,geni-spi"; 1522 reg = <0x0 0x898000 0x0 0x4000>; 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1526 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1527 clock-names = "se"; 1528 pinctrl-0 = <&qup_spi20_default>; 1529 pinctrl-names = "default"; 1530 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1531 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1532 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1533 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1534 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1535 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1536 interconnect-names = "qup-core", 1537 "qup-config", 1538 "qup-memory"; 1539 power-domains = <&rpmhpd SA8775P_CX>; 1540 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1541 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1542 dma-names = "tx", 1543 "rx"; 1544 status = "disabled"; 1545 }; 1546 1547 uart20: serial@898000 { 1548 compatible = "qcom,geni-uart"; 1549 reg = <0x0 0x00898000 0x0 0x4000>; 1550 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1551 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1552 clock-names = "se"; 1553 pinctrl-0 = <&qup_uart20_default>; 1554 pinctrl-names = "default"; 1555 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1556 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1557 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1558 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1559 interconnect-names = "qup-core", "qup-config"; 1560 power-domains = <&rpmhpd SA8775P_CX>; 1561 status = "disabled"; 1562 }; 1563 1564 }; 1565 1566 gpi_dma0: dma-controller@900000 { 1567 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1568 reg = <0x0 0x00900000 0x0 0x60000>; 1569 #dma-cells = <3>; 1570 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1572 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1573 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1574 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1575 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1576 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1579 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1582 dma-channels = <12>; 1583 dma-channel-mask = <0xfff>; 1584 iommus = <&apps_smmu 0x416 0x0>; 1585 status = "disabled"; 1586 }; 1587 1588 qupv3_id_0: geniqup@9c0000 { 1589 compatible = "qcom,geni-se-qup"; 1590 reg = <0x0 0x9c0000 0x0 0x6000>; 1591 #address-cells = <2>; 1592 #size-cells = <2>; 1593 ranges; 1594 clock-names = "m-ahb", "s-ahb"; 1595 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1596 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1597 iommus = <&apps_smmu 0x403 0x0>; 1598 status = "disabled"; 1599 1600 i2c0: i2c@980000 { 1601 compatible = "qcom,geni-i2c"; 1602 reg = <0x0 0x980000 0x0 0x4000>; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1606 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1607 clock-names = "se"; 1608 pinctrl-0 = <&qup_i2c0_default>; 1609 pinctrl-names = "default"; 1610 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1611 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1612 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1613 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1614 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1615 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1616 interconnect-names = "qup-core", 1617 "qup-config", 1618 "qup-memory"; 1619 power-domains = <&rpmhpd SA8775P_CX>; 1620 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1621 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1622 dma-names = "tx", 1623 "rx"; 1624 status = "disabled"; 1625 }; 1626 1627 spi0: spi@980000 { 1628 compatible = "qcom,geni-spi"; 1629 reg = <0x0 0x980000 0x0 0x4000>; 1630 #address-cells = <1>; 1631 #size-cells = <0>; 1632 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1633 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1634 clock-names = "se"; 1635 pinctrl-0 = <&qup_spi0_default>; 1636 pinctrl-names = "default"; 1637 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1638 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1639 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1640 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1641 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1642 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1643 interconnect-names = "qup-core", 1644 "qup-config", 1645 "qup-memory"; 1646 power-domains = <&rpmhpd SA8775P_CX>; 1647 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1648 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1649 dma-names = "tx", 1650 "rx"; 1651 status = "disabled"; 1652 }; 1653 1654 uart0: serial@980000 { 1655 compatible = "qcom,geni-uart"; 1656 reg = <0x0 0x980000 0x0 0x4000>; 1657 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1658 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1659 clock-names = "se"; 1660 pinctrl-0 = <&qup_uart0_default>; 1661 pinctrl-names = "default"; 1662 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1663 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1664 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1665 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1666 interconnect-names = "qup-core", "qup-config"; 1667 power-domains = <&rpmhpd SA8775P_CX>; 1668 status = "disabled"; 1669 }; 1670 1671 i2c1: i2c@984000 { 1672 compatible = "qcom,geni-i2c"; 1673 reg = <0x0 0x984000 0x0 0x4000>; 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1677 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1678 clock-names = "se"; 1679 pinctrl-0 = <&qup_i2c1_default>; 1680 pinctrl-names = "default"; 1681 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1682 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1683 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1684 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1685 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1686 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1687 interconnect-names = "qup-core", 1688 "qup-config", 1689 "qup-memory"; 1690 power-domains = <&rpmhpd SA8775P_CX>; 1691 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1692 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1693 dma-names = "tx", 1694 "rx"; 1695 status = "disabled"; 1696 }; 1697 1698 spi1: spi@984000 { 1699 compatible = "qcom,geni-spi"; 1700 reg = <0x0 0x984000 0x0 0x4000>; 1701 #address-cells = <1>; 1702 #size-cells = <0>; 1703 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1704 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1705 clock-names = "se"; 1706 pinctrl-0 = <&qup_spi1_default>; 1707 pinctrl-names = "default"; 1708 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1709 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1710 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1711 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1712 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1713 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1714 interconnect-names = "qup-core", 1715 "qup-config", 1716 "qup-memory"; 1717 power-domains = <&rpmhpd SA8775P_CX>; 1718 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1719 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1720 dma-names = "tx", 1721 "rx"; 1722 status = "disabled"; 1723 }; 1724 1725 uart1: serial@984000 { 1726 compatible = "qcom,geni-uart"; 1727 reg = <0x0 0x984000 0x0 0x4000>; 1728 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1729 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1730 clock-names = "se"; 1731 pinctrl-0 = <&qup_uart1_default>; 1732 pinctrl-names = "default"; 1733 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1734 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1735 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1736 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1737 interconnect-names = "qup-core", "qup-config"; 1738 power-domains = <&rpmhpd SA8775P_CX>; 1739 status = "disabled"; 1740 }; 1741 1742 i2c2: i2c@988000 { 1743 compatible = "qcom,geni-i2c"; 1744 reg = <0x0 0x988000 0x0 0x4000>; 1745 #address-cells = <1>; 1746 #size-cells = <0>; 1747 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1748 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1749 clock-names = "se"; 1750 pinctrl-0 = <&qup_i2c2_default>; 1751 pinctrl-names = "default"; 1752 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1753 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1754 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1755 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1756 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1757 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1758 interconnect-names = "qup-core", 1759 "qup-config", 1760 "qup-memory"; 1761 power-domains = <&rpmhpd SA8775P_CX>; 1762 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1763 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1764 dma-names = "tx", 1765 "rx"; 1766 status = "disabled"; 1767 }; 1768 1769 spi2: spi@988000 { 1770 compatible = "qcom,geni-spi"; 1771 reg = <0x0 0x988000 0x0 0x4000>; 1772 #address-cells = <1>; 1773 #size-cells = <0>; 1774 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1775 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1776 clock-names = "se"; 1777 pinctrl-0 = <&qup_spi2_default>; 1778 pinctrl-names = "default"; 1779 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1780 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1781 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1782 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1783 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1784 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1785 interconnect-names = "qup-core", 1786 "qup-config", 1787 "qup-memory"; 1788 power-domains = <&rpmhpd SA8775P_CX>; 1789 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1790 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1791 dma-names = "tx", 1792 "rx"; 1793 status = "disabled"; 1794 }; 1795 1796 uart2: serial@988000 { 1797 compatible = "qcom,geni-uart"; 1798 reg = <0x0 0x988000 0x0 0x4000>; 1799 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1800 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1801 clock-names = "se"; 1802 pinctrl-0 = <&qup_uart2_default>; 1803 pinctrl-names = "default"; 1804 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1805 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1806 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1807 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1808 interconnect-names = "qup-core", "qup-config"; 1809 power-domains = <&rpmhpd SA8775P_CX>; 1810 status = "disabled"; 1811 }; 1812 1813 i2c3: i2c@98c000 { 1814 compatible = "qcom,geni-i2c"; 1815 reg = <0x0 0x98c000 0x0 0x4000>; 1816 #address-cells = <1>; 1817 #size-cells = <0>; 1818 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1819 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1820 clock-names = "se"; 1821 pinctrl-0 = <&qup_i2c3_default>; 1822 pinctrl-names = "default"; 1823 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1824 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1825 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1826 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1827 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1828 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1829 interconnect-names = "qup-core", 1830 "qup-config", 1831 "qup-memory"; 1832 power-domains = <&rpmhpd SA8775P_CX>; 1833 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1834 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1835 dma-names = "tx", 1836 "rx"; 1837 status = "disabled"; 1838 }; 1839 1840 spi3: spi@98c000 { 1841 compatible = "qcom,geni-spi"; 1842 reg = <0x0 0x98c000 0x0 0x4000>; 1843 #address-cells = <1>; 1844 #size-cells = <0>; 1845 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1846 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1847 clock-names = "se"; 1848 pinctrl-0 = <&qup_spi3_default>; 1849 pinctrl-names = "default"; 1850 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1851 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1852 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1853 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1854 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1855 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1856 interconnect-names = "qup-core", 1857 "qup-config", 1858 "qup-memory"; 1859 power-domains = <&rpmhpd SA8775P_CX>; 1860 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1861 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1862 dma-names = "tx", 1863 "rx"; 1864 status = "disabled"; 1865 }; 1866 1867 uart3: serial@98c000 { 1868 compatible = "qcom,geni-uart"; 1869 reg = <0x0 0x98c000 0x0 0x4000>; 1870 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1871 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1872 clock-names = "se"; 1873 pinctrl-0 = <&qup_uart3_default>; 1874 pinctrl-names = "default"; 1875 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1876 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1877 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1878 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1879 interconnect-names = "qup-core", "qup-config"; 1880 power-domains = <&rpmhpd SA8775P_CX>; 1881 status = "disabled"; 1882 }; 1883 1884 i2c4: i2c@990000 { 1885 compatible = "qcom,geni-i2c"; 1886 reg = <0x0 0x990000 0x0 0x4000>; 1887 #address-cells = <1>; 1888 #size-cells = <0>; 1889 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1890 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1891 clock-names = "se"; 1892 pinctrl-0 = <&qup_i2c4_default>; 1893 pinctrl-names = "default"; 1894 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1895 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1896 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1897 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1898 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1899 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1900 interconnect-names = "qup-core", 1901 "qup-config", 1902 "qup-memory"; 1903 power-domains = <&rpmhpd SA8775P_CX>; 1904 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1905 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1906 dma-names = "tx", 1907 "rx"; 1908 status = "disabled"; 1909 }; 1910 1911 spi4: spi@990000 { 1912 compatible = "qcom,geni-spi"; 1913 reg = <0x0 0x990000 0x0 0x4000>; 1914 #address-cells = <1>; 1915 #size-cells = <0>; 1916 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1917 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1918 clock-names = "se"; 1919 pinctrl-0 = <&qup_spi4_default>; 1920 pinctrl-names = "default"; 1921 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1922 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1923 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1924 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1925 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1926 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1927 interconnect-names = "qup-core", 1928 "qup-config", 1929 "qup-memory"; 1930 power-domains = <&rpmhpd SA8775P_CX>; 1931 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1932 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1933 dma-names = "tx", 1934 "rx"; 1935 status = "disabled"; 1936 }; 1937 1938 uart4: serial@990000 { 1939 compatible = "qcom,geni-uart"; 1940 reg = <0x0 0x990000 0x0 0x4000>; 1941 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1942 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1943 clock-names = "se"; 1944 pinctrl-0 = <&qup_uart4_default>; 1945 pinctrl-names = "default"; 1946 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1947 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1948 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1949 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1950 interconnect-names = "qup-core", "qup-config"; 1951 power-domains = <&rpmhpd SA8775P_CX>; 1952 status = "disabled"; 1953 }; 1954 1955 i2c5: i2c@994000 { 1956 compatible = "qcom,geni-i2c"; 1957 reg = <0x0 0x994000 0x0 0x4000>; 1958 #address-cells = <1>; 1959 #size-cells = <0>; 1960 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1961 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1962 clock-names = "se"; 1963 pinctrl-0 = <&qup_i2c5_default>; 1964 pinctrl-names = "default"; 1965 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1966 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1967 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1968 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1969 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1970 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1971 interconnect-names = "qup-core", 1972 "qup-config", 1973 "qup-memory"; 1974 power-domains = <&rpmhpd SA8775P_CX>; 1975 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1976 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1977 dma-names = "tx", 1978 "rx"; 1979 status = "disabled"; 1980 }; 1981 1982 spi5: spi@994000 { 1983 compatible = "qcom,geni-spi"; 1984 reg = <0x0 0x994000 0x0 0x4000>; 1985 #address-cells = <1>; 1986 #size-cells = <0>; 1987 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1988 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1989 clock-names = "se"; 1990 pinctrl-0 = <&qup_spi5_default>; 1991 pinctrl-names = "default"; 1992 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1993 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1994 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1995 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1996 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1997 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1998 interconnect-names = "qup-core", 1999 "qup-config", 2000 "qup-memory"; 2001 power-domains = <&rpmhpd SA8775P_CX>; 2002 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2003 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2004 dma-names = "tx", 2005 "rx"; 2006 status = "disabled"; 2007 }; 2008 2009 uart5: serial@994000 { 2010 compatible = "qcom,geni-uart"; 2011 reg = <0x0 0x994000 0x0 0x4000>; 2012 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2013 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2014 clock-names = "se"; 2015 pinctrl-0 = <&qup_uart5_default>; 2016 pinctrl-names = "default"; 2017 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2018 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2019 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2020 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2021 interconnect-names = "qup-core", "qup-config"; 2022 power-domains = <&rpmhpd SA8775P_CX>; 2023 status = "disabled"; 2024 }; 2025 }; 2026 2027 gpi_dma1: dma-controller@a00000 { 2028 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2029 reg = <0x0 0x00a00000 0x0 0x60000>; 2030 #dma-cells = <3>; 2031 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 2040 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2043 iommus = <&apps_smmu 0x456 0x0>; 2044 dma-channels = <12>; 2045 dma-channel-mask = <0xfff>; 2046 status = "disabled"; 2047 }; 2048 2049 qupv3_id_1: geniqup@ac0000 { 2050 compatible = "qcom,geni-se-qup"; 2051 reg = <0x0 0x00ac0000 0x0 0x6000>; 2052 #address-cells = <2>; 2053 #size-cells = <2>; 2054 ranges; 2055 clock-names = "m-ahb", "s-ahb"; 2056 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 2057 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 2058 iommus = <&apps_smmu 0x443 0x0>; 2059 status = "disabled"; 2060 2061 i2c7: i2c@a80000 { 2062 compatible = "qcom,geni-i2c"; 2063 reg = <0x0 0xa80000 0x0 0x4000>; 2064 #address-cells = <1>; 2065 #size-cells = <0>; 2066 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2067 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2068 clock-names = "se"; 2069 pinctrl-0 = <&qup_i2c7_default>; 2070 pinctrl-names = "default"; 2071 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2072 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2073 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2074 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2075 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2076 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2077 interconnect-names = "qup-core", 2078 "qup-config", 2079 "qup-memory"; 2080 power-domains = <&rpmhpd SA8775P_CX>; 2081 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 2082 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 2083 dma-names = "tx", 2084 "rx"; 2085 status = "disabled"; 2086 }; 2087 2088 spi7: spi@a80000 { 2089 compatible = "qcom,geni-spi"; 2090 reg = <0x0 0xa80000 0x0 0x4000>; 2091 #address-cells = <1>; 2092 #size-cells = <0>; 2093 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2094 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2095 clock-names = "se"; 2096 pinctrl-0 = <&qup_spi7_default>; 2097 pinctrl-names = "default"; 2098 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2099 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2100 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2101 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2102 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2103 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2104 interconnect-names = "qup-core", 2105 "qup-config", 2106 "qup-memory"; 2107 power-domains = <&rpmhpd SA8775P_CX>; 2108 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 2109 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 2110 dma-names = "tx", 2111 "rx"; 2112 status = "disabled"; 2113 }; 2114 2115 uart7: serial@a80000 { 2116 compatible = "qcom,geni-uart"; 2117 reg = <0x0 0x00a80000 0x0 0x4000>; 2118 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2119 clock-names = "se"; 2120 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2121 pinctrl-0 = <&qup_uart7_default>; 2122 pinctrl-names = "default"; 2123 interconnect-names = "qup-core", "qup-config"; 2124 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2125 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2126 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2127 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2128 power-domains = <&rpmhpd SA8775P_CX>; 2129 operating-points-v2 = <&qup_opp_table_100mhz>; 2130 status = "disabled"; 2131 }; 2132 2133 i2c8: i2c@a84000 { 2134 compatible = "qcom,geni-i2c"; 2135 reg = <0x0 0xa84000 0x0 0x4000>; 2136 #address-cells = <1>; 2137 #size-cells = <0>; 2138 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2139 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2140 clock-names = "se"; 2141 pinctrl-0 = <&qup_i2c8_default>; 2142 pinctrl-names = "default"; 2143 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2144 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2145 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2146 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2147 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2148 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2149 interconnect-names = "qup-core", 2150 "qup-config", 2151 "qup-memory"; 2152 power-domains = <&rpmhpd SA8775P_CX>; 2153 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 2154 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 2155 dma-names = "tx", 2156 "rx"; 2157 status = "disabled"; 2158 }; 2159 2160 spi8: spi@a84000 { 2161 compatible = "qcom,geni-spi"; 2162 reg = <0x0 0xa84000 0x0 0x4000>; 2163 #address-cells = <1>; 2164 #size-cells = <0>; 2165 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2166 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2167 clock-names = "se"; 2168 pinctrl-0 = <&qup_spi8_default>; 2169 pinctrl-names = "default"; 2170 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2171 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2173 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2174 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2176 interconnect-names = "qup-core", 2177 "qup-config", 2178 "qup-memory"; 2179 power-domains = <&rpmhpd SA8775P_CX>; 2180 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 2181 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 2182 dma-names = "tx", 2183 "rx"; 2184 status = "disabled"; 2185 }; 2186 2187 uart8: serial@a84000 { 2188 compatible = "qcom,geni-uart"; 2189 reg = <0x0 0x00a84000 0x0 0x4000>; 2190 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2191 clock-names = "se"; 2192 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2193 pinctrl-0 = <&qup_uart8_default>; 2194 pinctrl-names = "default"; 2195 interconnect-names = "qup-core", "qup-config"; 2196 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2197 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2198 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2199 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2200 power-domains = <&rpmhpd SA8775P_CX>; 2201 operating-points-v2 = <&qup_opp_table_100mhz>; 2202 status = "disabled"; 2203 }; 2204 2205 i2c9: i2c@a88000 { 2206 compatible = "qcom,geni-i2c"; 2207 reg = <0x0 0xa88000 0x0 0x4000>; 2208 #address-cells = <1>; 2209 #size-cells = <0>; 2210 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2211 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2212 clock-names = "se"; 2213 pinctrl-0 = <&qup_i2c9_default>; 2214 pinctrl-names = "default"; 2215 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2216 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2217 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2218 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2219 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2220 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2221 interconnect-names = "qup-core", 2222 "qup-config", 2223 "qup-memory"; 2224 power-domains = <&rpmhpd SA8775P_CX>; 2225 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 2226 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 2227 dma-names = "tx", 2228 "rx"; 2229 status = "disabled"; 2230 }; 2231 2232 spi9: spi@a88000 { 2233 compatible = "qcom,geni-spi"; 2234 reg = <0x0 0xa88000 0x0 0x4000>; 2235 #address-cells = <1>; 2236 #size-cells = <0>; 2237 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2238 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2239 clock-names = "se"; 2240 pinctrl-0 = <&qup_spi9_default>; 2241 pinctrl-names = "default"; 2242 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2243 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2244 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2245 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2246 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2247 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2248 interconnect-names = "qup-core", 2249 "qup-config", 2250 "qup-memory"; 2251 power-domains = <&rpmhpd SA8775P_CX>; 2252 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 2253 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 2254 dma-names = "tx", 2255 "rx"; 2256 status = "disabled"; 2257 }; 2258 2259 uart9: serial@a88000 { 2260 compatible = "qcom,geni-uart"; 2261 reg = <0x0 0xa88000 0x0 0x4000>; 2262 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2263 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2264 clock-names = "se"; 2265 pinctrl-0 = <&qup_uart9_default>; 2266 pinctrl-names = "default"; 2267 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2268 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2269 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2270 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2271 interconnect-names = "qup-core", "qup-config"; 2272 power-domains = <&rpmhpd SA8775P_CX>; 2273 status = "disabled"; 2274 }; 2275 2276 i2c10: i2c@a8c000 { 2277 compatible = "qcom,geni-i2c"; 2278 reg = <0x0 0xa8c000 0x0 0x4000>; 2279 #address-cells = <1>; 2280 #size-cells = <0>; 2281 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2282 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2283 clock-names = "se"; 2284 pinctrl-0 = <&qup_i2c10_default>; 2285 pinctrl-names = "default"; 2286 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2287 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2288 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2289 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2290 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2291 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2292 interconnect-names = "qup-core", 2293 "qup-config", 2294 "qup-memory"; 2295 power-domains = <&rpmhpd SA8775P_CX>; 2296 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 2297 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 2298 dma-names = "tx", 2299 "rx"; 2300 status = "disabled"; 2301 }; 2302 2303 spi10: spi@a8c000 { 2304 compatible = "qcom,geni-spi"; 2305 reg = <0x0 0xa8c000 0x0 0x4000>; 2306 #address-cells = <1>; 2307 #size-cells = <0>; 2308 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2309 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2310 clock-names = "se"; 2311 pinctrl-0 = <&qup_spi10_default>; 2312 pinctrl-names = "default"; 2313 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2314 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2315 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2316 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2317 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2318 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2319 interconnect-names = "qup-core", 2320 "qup-config", 2321 "qup-memory"; 2322 power-domains = <&rpmhpd SA8775P_CX>; 2323 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 2324 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 2325 dma-names = "tx", 2326 "rx"; 2327 status = "disabled"; 2328 }; 2329 2330 uart10: serial@a8c000 { 2331 compatible = "qcom,geni-uart"; 2332 reg = <0x0 0x00a8c000 0x0 0x4000>; 2333 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2334 clock-names = "se"; 2335 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2336 pinctrl-0 = <&qup_uart10_default>; 2337 pinctrl-names = "default"; 2338 interconnect-names = "qup-core", "qup-config"; 2339 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 2340 &clk_virt SLAVE_QUP_CORE_1 0>, 2341 <&gem_noc MASTER_APPSS_PROC 0 2342 &config_noc SLAVE_QUP_1 0>; 2343 power-domains = <&rpmhpd SA8775P_CX>; 2344 operating-points-v2 = <&qup_opp_table_100mhz>; 2345 status = "disabled"; 2346 }; 2347 2348 i2c11: i2c@a90000 { 2349 compatible = "qcom,geni-i2c"; 2350 reg = <0x0 0xa90000 0x0 0x4000>; 2351 #address-cells = <1>; 2352 #size-cells = <0>; 2353 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2354 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2355 clock-names = "se"; 2356 pinctrl-0 = <&qup_i2c11_default>; 2357 pinctrl-names = "default"; 2358 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2359 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2360 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2361 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2362 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2363 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2364 interconnect-names = "qup-core", 2365 "qup-config", 2366 "qup-memory"; 2367 power-domains = <&rpmhpd SA8775P_CX>; 2368 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2369 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2370 dma-names = "tx", 2371 "rx"; 2372 status = "disabled"; 2373 }; 2374 2375 spi11: spi@a90000 { 2376 compatible = "qcom,geni-spi"; 2377 reg = <0x0 0xa90000 0x0 0x4000>; 2378 #address-cells = <1>; 2379 #size-cells = <0>; 2380 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2381 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2382 clock-names = "se"; 2383 pinctrl-0 = <&qup_spi11_default>; 2384 pinctrl-names = "default"; 2385 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2386 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2387 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2388 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2389 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2391 interconnect-names = "qup-core", 2392 "qup-config", 2393 "qup-memory"; 2394 power-domains = <&rpmhpd SA8775P_CX>; 2395 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2396 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2397 dma-names = "tx", 2398 "rx"; 2399 status = "disabled"; 2400 }; 2401 2402 uart11: serial@a90000 { 2403 compatible = "qcom,geni-uart"; 2404 reg = <0x0 0x00a90000 0x0 0x4000>; 2405 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2406 clock-names = "se"; 2407 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2408 pinctrl-0 = <&qup_uart11_default>; 2409 pinctrl-names = "default"; 2410 interconnect-names = "qup-core", "qup-config"; 2411 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2412 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2413 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2414 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2415 power-domains = <&rpmhpd SA8775P_CX>; 2416 operating-points-v2 = <&qup_opp_table_100mhz>; 2417 status = "disabled"; 2418 }; 2419 2420 i2c12: i2c@a94000 { 2421 compatible = "qcom,geni-i2c"; 2422 reg = <0x0 0xa94000 0x0 0x4000>; 2423 #address-cells = <1>; 2424 #size-cells = <0>; 2425 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2426 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2427 clock-names = "se"; 2428 pinctrl-0 = <&qup_i2c12_default>; 2429 pinctrl-names = "default"; 2430 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2431 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2432 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2433 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2434 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2435 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2436 interconnect-names = "qup-core", 2437 "qup-config", 2438 "qup-memory"; 2439 power-domains = <&rpmhpd SA8775P_CX>; 2440 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2441 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2442 dma-names = "tx", 2443 "rx"; 2444 status = "disabled"; 2445 }; 2446 2447 spi12: spi@a94000 { 2448 compatible = "qcom,geni-spi"; 2449 reg = <0x0 0xa94000 0x0 0x4000>; 2450 #address-cells = <1>; 2451 #size-cells = <0>; 2452 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2453 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2454 clock-names = "se"; 2455 pinctrl-0 = <&qup_spi12_default>; 2456 pinctrl-names = "default"; 2457 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2458 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2459 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2460 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2461 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2462 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2463 interconnect-names = "qup-core", 2464 "qup-config", 2465 "qup-memory"; 2466 power-domains = <&rpmhpd SA8775P_CX>; 2467 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2468 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2469 dma-names = "tx", 2470 "rx"; 2471 status = "disabled"; 2472 }; 2473 2474 uart12: serial@a94000 { 2475 compatible = "qcom,geni-uart"; 2476 reg = <0x0 0x00a94000 0x0 0x4000>; 2477 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2478 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2479 clock-names = "se"; 2480 pinctrl-0 = <&qup_uart12_default>; 2481 pinctrl-names = "default"; 2482 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2483 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2484 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2485 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2486 interconnect-names = "qup-core", "qup-config"; 2487 power-domains = <&rpmhpd SA8775P_CX>; 2488 status = "disabled"; 2489 }; 2490 2491 i2c13: i2c@a98000 { 2492 compatible = "qcom,geni-i2c"; 2493 reg = <0x0 0xa98000 0x0 0x4000>; 2494 #address-cells = <1>; 2495 #size-cells = <0>; 2496 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2497 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2498 clock-names = "se"; 2499 pinctrl-0 = <&qup_i2c13_default>; 2500 pinctrl-names = "default"; 2501 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2502 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2503 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2504 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2505 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2506 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2507 interconnect-names = "qup-core", 2508 "qup-config", 2509 "qup-memory"; 2510 power-domains = <&rpmhpd SA8775P_CX>; 2511 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2512 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2513 dma-names = "tx", 2514 "rx"; 2515 status = "disabled"; 2516 2517 }; 2518 }; 2519 2520 gpi_dma3: dma-controller@b00000 { 2521 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2522 reg = <0x0 0x00b00000 0x0 0x58000>; 2523 #dma-cells = <3>; 2524 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2525 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2526 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2527 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2528 iommus = <&apps_smmu 0x056 0x0>; 2529 dma-channels = <4>; 2530 dma-channel-mask = <0xf>; 2531 status = "disabled"; 2532 }; 2533 2534 qupv3_id_3: geniqup@bc0000 { 2535 compatible = "qcom,geni-se-qup"; 2536 reg = <0x0 0xbc0000 0x0 0x6000>; 2537 #address-cells = <2>; 2538 #size-cells = <2>; 2539 ranges; 2540 clock-names = "m-ahb", "s-ahb"; 2541 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2542 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2543 iommus = <&apps_smmu 0x43 0x0>; 2544 status = "disabled"; 2545 2546 i2c21: i2c@b80000 { 2547 compatible = "qcom,geni-i2c"; 2548 reg = <0x0 0xb80000 0x0 0x4000>; 2549 #address-cells = <1>; 2550 #size-cells = <0>; 2551 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2552 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2553 clock-names = "se"; 2554 pinctrl-0 = <&qup_i2c21_default>; 2555 pinctrl-names = "default"; 2556 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2557 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2558 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2559 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2560 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2561 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2562 interconnect-names = "qup-core", 2563 "qup-config", 2564 "qup-memory"; 2565 power-domains = <&rpmhpd SA8775P_CX>; 2566 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2567 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2568 dma-names = "tx", 2569 "rx"; 2570 status = "disabled"; 2571 }; 2572 2573 spi21: spi@b80000 { 2574 compatible = "qcom,geni-spi"; 2575 reg = <0x0 0xb80000 0x0 0x4000>; 2576 #address-cells = <1>; 2577 #size-cells = <0>; 2578 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2579 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2580 clock-names = "se"; 2581 pinctrl-0 = <&qup_spi21_default>; 2582 pinctrl-names = "default"; 2583 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2584 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2585 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2586 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2587 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2588 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2589 interconnect-names = "qup-core", 2590 "qup-config", 2591 "qup-memory"; 2592 power-domains = <&rpmhpd SA8775P_CX>; 2593 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2594 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2595 dma-names = "tx", 2596 "rx"; 2597 status = "disabled"; 2598 }; 2599 2600 uart21: serial@b80000 { 2601 compatible = "qcom,geni-uart"; 2602 reg = <0x0 0x00b80000 0x0 0x4000>; 2603 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2604 clock-names = "se"; 2605 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2606 interconnect-names = "qup-core", "qup-config"; 2607 pinctrl-0 = <&qup_uart21_default>; 2608 pinctrl-names = "default"; 2609 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2610 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2611 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2612 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2613 power-domains = <&rpmhpd SA8775P_CX>; 2614 operating-points-v2 = <&qup_opp_table_100mhz>; 2615 status = "disabled"; 2616 }; 2617 }; 2618 2619 rng: rng@10d2000 { 2620 compatible = "qcom,sa8775p-trng", "qcom,trng"; 2621 reg = <0 0x010d2000 0 0x1000>; 2622 }; 2623 2624 config_noc: interconnect@14c0000 { 2625 compatible = "qcom,sa8775p-config-noc"; 2626 reg = <0x0 0x014c0000 0x0 0x13080>; 2627 #interconnect-cells = <2>; 2628 qcom,bcm-voters = <&apps_bcm_voter>; 2629 }; 2630 2631 system_noc: interconnect@1680000 { 2632 compatible = "qcom,sa8775p-system-noc"; 2633 reg = <0x0 0x01680000 0x0 0x15080>; 2634 #interconnect-cells = <2>; 2635 qcom,bcm-voters = <&apps_bcm_voter>; 2636 }; 2637 2638 aggre1_noc: interconnect@16c0000 { 2639 compatible = "qcom,sa8775p-aggre1-noc"; 2640 reg = <0x0 0x016c0000 0x0 0x18080>; 2641 #interconnect-cells = <2>; 2642 qcom,bcm-voters = <&apps_bcm_voter>; 2643 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2644 <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, 2645 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 2646 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2647 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; 2648 }; 2649 2650 aggre2_noc: interconnect@1700000 { 2651 compatible = "qcom,sa8775p-aggre2-noc"; 2652 reg = <0x0 0x01700000 0x0 0x1b080>; 2653 #interconnect-cells = <2>; 2654 qcom,bcm-voters = <&apps_bcm_voter>; 2655 clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2656 <&rpmhcc RPMH_IPA_CLK>; 2657 }; 2658 2659 pcie_anoc: interconnect@1760000 { 2660 compatible = "qcom,sa8775p-pcie-anoc"; 2661 reg = <0x0 0x01760000 0x0 0xc080>; 2662 #interconnect-cells = <2>; 2663 qcom,bcm-voters = <&apps_bcm_voter>; 2664 }; 2665 2666 gpdsp_anoc: interconnect@1780000 { 2667 compatible = "qcom,sa8775p-gpdsp-anoc"; 2668 reg = <0x0 0x01780000 0x0 0xe080>; 2669 #interconnect-cells = <2>; 2670 qcom,bcm-voters = <&apps_bcm_voter>; 2671 }; 2672 2673 mmss_noc: interconnect@17a0000 { 2674 compatible = "qcom,sa8775p-mmss-noc"; 2675 reg = <0x0 0x017a0000 0x0 0x40000>; 2676 #interconnect-cells = <2>; 2677 qcom,bcm-voters = <&apps_bcm_voter>; 2678 }; 2679 2680 pcie0: pcie@1c00000 { 2681 compatible = "qcom,pcie-sa8775p"; 2682 reg = <0x0 0x01c00000 0x0 0x3000>, 2683 <0x0 0x40000000 0x0 0xf20>, 2684 <0x0 0x40000f20 0x0 0xa8>, 2685 <0x0 0x40001000 0x0 0x4000>, 2686 <0x0 0x40100000 0x0 0x100000>, 2687 <0x0 0x01c03000 0x0 0x1000>; 2688 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2689 device_type = "pci"; 2690 2691 #address-cells = <3>; 2692 #size-cells = <2>; 2693 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2694 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2695 bus-range = <0x00 0xff>; 2696 2697 dma-coherent; 2698 2699 linux,pci-domain = <0>; 2700 num-lanes = <2>; 2701 2702 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2703 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2704 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2706 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2707 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2708 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2711 interrupt-names = "msi0", 2712 "msi1", 2713 "msi2", 2714 "msi3", 2715 "msi4", 2716 "msi5", 2717 "msi6", 2718 "msi7", 2719 "global"; 2720 #interrupt-cells = <1>; 2721 interrupt-map-mask = <0 0 0 0x7>; 2722 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2723 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2724 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 2725 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 2726 2727 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2728 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2729 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2730 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2731 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 2732 2733 clock-names = "aux", 2734 "cfg", 2735 "bus_master", 2736 "bus_slave", 2737 "slave_q2a"; 2738 2739 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 2740 assigned-clock-rates = <19200000>; 2741 2742 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 2743 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 2744 interconnect-names = "pcie-mem", "cpu-pcie"; 2745 2746 iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>, 2747 <0x100 &pcie_smmu 0x0001 0x0 0x1>; 2748 2749 resets = <&gcc GCC_PCIE_0_BCR>, 2750 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; 2751 reset-names = "pci", 2752 "link_down"; 2753 2754 power-domains = <&gcc PCIE_0_GDSC>; 2755 2756 phys = <&pcie0_phy>; 2757 phy-names = "pciephy"; 2758 2759 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2760 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2761 2762 status = "disabled"; 2763 2764 pcieport0: pcie@0 { 2765 compatible = "pciclass,0604"; 2766 device_type = "pci"; 2767 reg = <0x0 0x0 0x0 0x0 0x0>; 2768 bus-range = <0x01 0xff>; 2769 2770 #address-cells = <3>; 2771 #size-cells = <2>; 2772 ranges; 2773 }; 2774 }; 2775 2776 pcie0_ep: pcie-ep@1c00000 { 2777 compatible = "qcom,sa8775p-pcie-ep"; 2778 reg = <0x0 0x01c00000 0x0 0x3000>, 2779 <0x0 0x40000000 0x0 0xf20>, 2780 <0x0 0x40000f20 0x0 0xa8>, 2781 <0x0 0x40001000 0x0 0x4000>, 2782 <0x0 0x40200000 0x0 0x1fe00000>, 2783 <0x0 0x01c03000 0x0 0x1000>, 2784 <0x0 0x40005000 0x0 0x2000>; 2785 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 2786 "mmio", "dma"; 2787 2788 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2789 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2790 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2791 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2792 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 2793 2794 clock-names = "aux", 2795 "cfg", 2796 "bus_master", 2797 "bus_slave", 2798 "slave_q2a"; 2799 2800 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2801 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2802 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; 2803 2804 interrupt-names = "global", "doorbell", "dma"; 2805 2806 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 2807 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 2808 interconnect-names = "pcie-mem", "cpu-pcie"; 2809 2810 dma-coherent; 2811 iommus = <&pcie_smmu 0x0000 0x7f>; 2812 resets = <&gcc GCC_PCIE_0_BCR>; 2813 reset-names = "core"; 2814 power-domains = <&gcc PCIE_0_GDSC>; 2815 phys = <&pcie0_phy>; 2816 phy-names = "pciephy"; 2817 num-lanes = <2>; 2818 linux,pci-domain = <0>; 2819 2820 status = "disabled"; 2821 }; 2822 2823 pcie0_phy: phy@1c04000 { 2824 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 2825 reg = <0x0 0x1c04000 0x0 0x2000>; 2826 2827 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, 2828 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2829 <&gcc GCC_PCIE_CLKREF_EN>, 2830 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2831 <&gcc GCC_PCIE_0_PIPE_CLK>, 2832 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; 2833 clock-names = "aux", 2834 "cfg_ahb", 2835 "ref", 2836 "rchng", 2837 "pipe", 2838 "pipediv2"; 2839 2840 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2841 assigned-clock-rates = <100000000>; 2842 2843 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2844 reset-names = "phy"; 2845 2846 #clock-cells = <0>; 2847 clock-output-names = "pcie_0_pipe_clk"; 2848 2849 #phy-cells = <0>; 2850 2851 status = "disabled"; 2852 }; 2853 2854 pcie1: pcie@1c10000 { 2855 compatible = "qcom,pcie-sa8775p"; 2856 reg = <0x0 0x01c10000 0x0 0x3000>, 2857 <0x0 0x60000000 0x0 0xf20>, 2858 <0x0 0x60000f20 0x0 0xa8>, 2859 <0x0 0x60001000 0x0 0x4000>, 2860 <0x0 0x60100000 0x0 0x100000>, 2861 <0x0 0x01c13000 0x0 0x1000>; 2862 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2863 device_type = "pci"; 2864 2865 #address-cells = <3>; 2866 #size-cells = <2>; 2867 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2868 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 2869 bus-range = <0x00 0xff>; 2870 2871 dma-coherent; 2872 2873 linux,pci-domain = <1>; 2874 num-lanes = <4>; 2875 2876 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 2877 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2878 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2879 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2880 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2881 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2882 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2883 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2884 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; 2885 interrupt-names = "msi0", 2886 "msi1", 2887 "msi2", 2888 "msi3", 2889 "msi4", 2890 "msi5", 2891 "msi6", 2892 "msi7", 2893 "global"; 2894 #interrupt-cells = <1>; 2895 interrupt-map-mask = <0 0 0 0x7>; 2896 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2897 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2898 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2899 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2900 2901 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2902 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2903 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2904 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2905 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 2906 2907 clock-names = "aux", 2908 "cfg", 2909 "bus_master", 2910 "bus_slave", 2911 "slave_q2a"; 2912 2913 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2914 assigned-clock-rates = <19200000>; 2915 2916 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 2917 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 2918 interconnect-names = "pcie-mem", "cpu-pcie"; 2919 2920 iommu-map = <0x0 &pcie_smmu 0x0080 0x0 0x1>, 2921 <0x100 &pcie_smmu 0x0081 0x0 0x1>; 2922 2923 resets = <&gcc GCC_PCIE_1_BCR>, 2924 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2925 reset-names = "pci", 2926 "link_down"; 2927 2928 power-domains = <&gcc PCIE_1_GDSC>; 2929 2930 phys = <&pcie1_phy>; 2931 phy-names = "pciephy"; 2932 2933 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 2934 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 2935 2936 status = "disabled"; 2937 2938 pcie@0 { 2939 device_type = "pci"; 2940 reg = <0x0 0x0 0x0 0x0 0x0>; 2941 bus-range = <0x01 0xff>; 2942 2943 #address-cells = <3>; 2944 #size-cells = <2>; 2945 ranges; 2946 }; 2947 }; 2948 2949 pcie1_ep: pcie-ep@1c10000 { 2950 compatible = "qcom,sa8775p-pcie-ep"; 2951 reg = <0x0 0x01c10000 0x0 0x3000>, 2952 <0x0 0x60000000 0x0 0xf20>, 2953 <0x0 0x60000f20 0x0 0xa8>, 2954 <0x0 0x60001000 0x0 0x4000>, 2955 <0x0 0x60200000 0x0 0x1fe00000>, 2956 <0x0 0x01c13000 0x0 0x1000>, 2957 <0x0 0x60005000 0x0 0x2000>; 2958 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 2959 "mmio", "dma"; 2960 2961 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2962 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2963 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2964 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2965 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 2966 2967 clock-names = "aux", 2968 "cfg", 2969 "bus_master", 2970 "bus_slave", 2971 "slave_q2a"; 2972 2973 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 2974 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 2975 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 2976 2977 interrupt-names = "global", "doorbell", "dma"; 2978 2979 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 2980 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 2981 interconnect-names = "pcie-mem", "cpu-pcie"; 2982 2983 dma-coherent; 2984 iommus = <&pcie_smmu 0x80 0x7f>; 2985 resets = <&gcc GCC_PCIE_1_BCR>; 2986 reset-names = "core"; 2987 power-domains = <&gcc PCIE_1_GDSC>; 2988 phys = <&pcie1_phy>; 2989 phy-names = "pciephy"; 2990 num-lanes = <4>; 2991 linux,pci-domain = <1>; 2992 2993 status = "disabled"; 2994 }; 2995 2996 pcie1_phy: phy@1c14000 { 2997 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 2998 reg = <0x0 0x1c14000 0x0 0x4000>; 2999 3000 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 3001 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 3002 <&gcc GCC_PCIE_CLKREF_EN>, 3003 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 3004 <&gcc GCC_PCIE_1_PIPE_CLK>, 3005 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; 3006 clock-names = "aux", 3007 "cfg_ahb", 3008 "ref", 3009 "rchng", 3010 "pipe", 3011 "pipediv2"; 3012 3013 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 3014 assigned-clock-rates = <100000000>; 3015 3016 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 3017 reset-names = "phy"; 3018 3019 #clock-cells = <0>; 3020 clock-output-names = "pcie_1_pipe_clk"; 3021 3022 #phy-cells = <0>; 3023 3024 status = "disabled"; 3025 }; 3026 3027 ufs_mem_hc: ufshc@1d84000 { 3028 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 3029 reg = <0x0 0x01d84000 0x0 0x3000>; 3030 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 3031 phys = <&ufs_mem_phy>; 3032 phy-names = "ufsphy"; 3033 lanes-per-direction = <2>; 3034 #reset-cells = <1>; 3035 resets = <&gcc GCC_UFS_PHY_BCR>; 3036 reset-names = "rst"; 3037 power-domains = <&gcc UFS_PHY_GDSC>; 3038 required-opps = <&rpmhpd_opp_nom>; 3039 iommus = <&apps_smmu 0x100 0x0>; 3040 dma-coherent; 3041 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 3042 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3043 <&gcc GCC_UFS_PHY_AHB_CLK>, 3044 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 3045 <&rpmhcc RPMH_CXO_CLK>, 3046 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 3047 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 3048 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 3049 clock-names = "core_clk", 3050 "bus_aggr_clk", 3051 "iface_clk", 3052 "core_clk_unipro", 3053 "ref_clk", 3054 "tx_lane0_sync_clk", 3055 "rx_lane0_sync_clk", 3056 "rx_lane1_sync_clk"; 3057 freq-table-hz = <75000000 300000000>, 3058 <0 0>, 3059 <0 0>, 3060 <75000000 300000000>, 3061 <0 0>, 3062 <0 0>, 3063 <0 0>, 3064 <0 0>; 3065 qcom,ice = <&ice>; 3066 status = "disabled"; 3067 }; 3068 3069 ufs_mem_phy: phy@1d87000 { 3070 compatible = "qcom,sa8775p-qmp-ufs-phy"; 3071 reg = <0x0 0x01d87000 0x0 0xe10>; 3072 /* 3073 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 3074 * enables the CXO clock to eDP *and* UFS PHY. 3075 */ 3076 clocks = <&rpmhcc RPMH_CXO_CLK>, 3077 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 3078 <&gcc GCC_EDP_REF_CLKREF_EN>; 3079 clock-names = "ref", "ref_aux", "qref"; 3080 power-domains = <&gcc UFS_PHY_GDSC>; 3081 resets = <&ufs_mem_hc 0>; 3082 reset-names = "ufsphy"; 3083 #phy-cells = <0>; 3084 status = "disabled"; 3085 }; 3086 3087 ice: crypto@1d88000 { 3088 compatible = "qcom,sa8775p-inline-crypto-engine", 3089 "qcom,inline-crypto-engine"; 3090 reg = <0x0 0x01d88000 0x0 0x18000>; 3091 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, 3092 <&gcc GCC_UFS_PHY_AHB_CLK>; 3093 clock-names = "core", 3094 "iface"; 3095 power-domains = <&gcc UFS_PHY_GDSC>; 3096 }; 3097 3098 cryptobam: dma-controller@1dc4000 { 3099 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 3100 reg = <0x0 0x01dc4000 0x0 0x28000>; 3101 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3102 #dma-cells = <1>; 3103 qcom,ee = <0>; 3104 qcom,num-ees = <4>; 3105 num-channels = <20>; 3106 qcom,controlled-remotely; 3107 iommus = <&apps_smmu 0x480 0x00>, 3108 <&apps_smmu 0x481 0x00>; 3109 }; 3110 3111 crypto: crypto@1dfa000 { 3112 compatible = "qcom,sa8775p-qce", "qcom,sm8150-qce", "qcom,qce"; 3113 reg = <0x0 0x01dfa000 0x0 0x6000>; 3114 dmas = <&cryptobam 4>, <&cryptobam 5>; 3115 dma-names = "rx", "tx"; 3116 iommus = <&apps_smmu 0x480 0x0>, 3117 <&apps_smmu 0x481 0x0>; 3118 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS 3119 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3120 interconnect-names = "memory"; 3121 }; 3122 3123 lpass_ag_noc: interconnect@3c40000 { 3124 compatible = "qcom,sa8775p-lpass-ag-noc"; 3125 reg = <0x0 0x03c40000 0x0 0x17200>; 3126 #interconnect-cells = <2>; 3127 qcom,bcm-voters = <&apps_bcm_voter>; 3128 }; 3129 3130 ctcu@4001000 { 3131 compatible = "qcom,sa8775p-ctcu"; 3132 reg = <0x0 0x04001000 0x0 0x1000>; 3133 3134 clocks = <&aoss_qmp>; 3135 clock-names = "apb"; 3136 3137 in-ports { 3138 #address-cells = <1>; 3139 #size-cells = <0>; 3140 3141 port@0 { 3142 reg = <0>; 3143 3144 ctcu_in0: endpoint { 3145 remote-endpoint = <&etr0_out>; 3146 }; 3147 }; 3148 3149 port@1 { 3150 reg = <1>; 3151 3152 ctcu_in1: endpoint { 3153 remote-endpoint = <&etr1_out>; 3154 }; 3155 }; 3156 }; 3157 }; 3158 3159 stm: stm@4002000 { 3160 compatible = "arm,coresight-stm", "arm,primecell"; 3161 reg = <0x0 0x4002000 0x0 0x1000>, 3162 <0x0 0x16280000 0x0 0x180000>; 3163 reg-names = "stm-base", "stm-stimulus-base"; 3164 3165 clocks = <&aoss_qmp>; 3166 clock-names = "apb_pclk"; 3167 3168 out-ports { 3169 port { 3170 stm_out: endpoint { 3171 remote-endpoint = 3172 <&funnel0_in7>; 3173 }; 3174 }; 3175 }; 3176 }; 3177 3178 tpdm@4003000 { 3179 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3180 reg = <0x0 0x4003000 0x0 0x1000>; 3181 3182 clocks = <&aoss_qmp>; 3183 clock-names = "apb_pclk"; 3184 label = "tpdm_dcc"; 3185 3186 qcom,cmb-element-bits = <32>; 3187 qcom,cmb-msrs-num = <32>; 3188 status = "disabled"; 3189 3190 out-ports { 3191 port { 3192 qdss_tpdm0_out: endpoint { 3193 remote-endpoint = 3194 <&qdss_tpda_in0>; 3195 }; 3196 }; 3197 }; 3198 }; 3199 3200 tpda@4004000 { 3201 compatible = "qcom,coresight-tpda", "arm,primecell"; 3202 reg = <0x0 0x4004000 0x0 0x1000>; 3203 3204 clocks = <&aoss_qmp>; 3205 clock-names = "apb_pclk"; 3206 3207 out-ports { 3208 port { 3209 qdss_tpda_out: endpoint { 3210 remote-endpoint = 3211 <&funnel0_in6>; 3212 }; 3213 }; 3214 }; 3215 3216 in-ports { 3217 #address-cells = <1>; 3218 #size-cells = <0>; 3219 3220 port@0 { 3221 reg = <0>; 3222 qdss_tpda_in0: endpoint { 3223 remote-endpoint = 3224 <&qdss_tpdm0_out>; 3225 }; 3226 }; 3227 3228 port@1 { 3229 reg = <1>; 3230 qdss_tpda_in1: endpoint { 3231 remote-endpoint = 3232 <&qdss_tpdm1_out>; 3233 }; 3234 }; 3235 }; 3236 }; 3237 3238 tpdm@400f000 { 3239 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3240 reg = <0x0 0x400f000 0x0 0x1000>; 3241 3242 clocks = <&aoss_qmp>; 3243 clock-names = "apb_pclk"; 3244 label = "tpdm_spdm"; 3245 3246 qcom,cmb-element-bits = <32>; 3247 qcom,cmb-msrs-num = <32>; 3248 3249 out-ports { 3250 port { 3251 qdss_tpdm1_out: endpoint { 3252 remote-endpoint = 3253 <&qdss_tpda_in1>; 3254 }; 3255 }; 3256 }; 3257 }; 3258 3259 funnel@4041000 { 3260 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3261 reg = <0x0 0x4041000 0x0 0x1000>; 3262 3263 clocks = <&aoss_qmp>; 3264 clock-names = "apb_pclk"; 3265 3266 out-ports { 3267 port { 3268 funnel0_out: endpoint { 3269 remote-endpoint = 3270 <&qdss_funnel_in0>; 3271 }; 3272 }; 3273 }; 3274 3275 in-ports { 3276 #address-cells = <1>; 3277 #size-cells = <0>; 3278 3279 port@6 { 3280 reg = <6>; 3281 funnel0_in6: endpoint { 3282 remote-endpoint = 3283 <&qdss_tpda_out>; 3284 }; 3285 }; 3286 3287 port@7 { 3288 reg = <7>; 3289 funnel0_in7: endpoint { 3290 remote-endpoint = 3291 <&stm_out>; 3292 }; 3293 }; 3294 }; 3295 }; 3296 3297 funnel@4042000 { 3298 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3299 reg = <0x0 0x4042000 0x0 0x1000>; 3300 3301 clocks = <&aoss_qmp>; 3302 clock-names = "apb_pclk"; 3303 3304 out-ports { 3305 port { 3306 funnel1_out: endpoint { 3307 remote-endpoint = 3308 <&qdss_funnel_in1>; 3309 }; 3310 }; 3311 }; 3312 3313 in-ports { 3314 #address-cells = <1>; 3315 #size-cells = <0>; 3316 3317 port@4 { 3318 reg = <4>; 3319 funnel1_in4: endpoint { 3320 remote-endpoint = 3321 <&apss_funnel1_out>; 3322 }; 3323 }; 3324 3325 port@5 { 3326 reg = <5>; 3327 3328 funnel1_in5: endpoint { 3329 remote-endpoint = <&dlct0_funnel_out>; 3330 }; 3331 }; 3332 }; 3333 }; 3334 3335 funnel@4045000 { 3336 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3337 reg = <0x0 0x4045000 0x0 0x1000>; 3338 3339 clocks = <&aoss_qmp>; 3340 clock-names = "apb_pclk"; 3341 3342 out-ports { 3343 port { 3344 qdss_funnel_out: endpoint { 3345 remote-endpoint = 3346 <&aoss_funnel_in7>; 3347 }; 3348 }; 3349 }; 3350 3351 in-ports { 3352 #address-cells = <1>; 3353 #size-cells = <0>; 3354 3355 port@0 { 3356 reg = <0>; 3357 qdss_funnel_in0: endpoint { 3358 remote-endpoint = 3359 <&funnel0_out>; 3360 }; 3361 }; 3362 3363 port@1 { 3364 reg = <1>; 3365 qdss_funnel_in1: endpoint { 3366 remote-endpoint = 3367 <&funnel1_out>; 3368 }; 3369 }; 3370 }; 3371 }; 3372 3373 replicator@4046000 { 3374 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3375 reg = <0x0 0x04046000 0x0 0x1000>; 3376 3377 clocks = <&aoss_qmp>; 3378 clock-names = "apb_pclk"; 3379 3380 in-ports { 3381 port { 3382 qdss_rep_in: endpoint { 3383 remote-endpoint = <&swao_rep_out0>; 3384 }; 3385 }; 3386 }; 3387 3388 out-ports { 3389 port { 3390 qdss_rep_out0: endpoint { 3391 remote-endpoint = <&etr_rep_in>; 3392 }; 3393 }; 3394 }; 3395 }; 3396 3397 tmc_etr: tmc@4048000 { 3398 compatible = "arm,coresight-tmc", "arm,primecell"; 3399 reg = <0x0 0x04048000 0x0 0x1000>; 3400 3401 clocks = <&aoss_qmp>; 3402 clock-names = "apb_pclk"; 3403 iommus = <&apps_smmu 0x04c0 0x00>; 3404 3405 arm,scatter-gather; 3406 3407 in-ports { 3408 port { 3409 etr0_in: endpoint { 3410 remote-endpoint = <&etr_rep_out0>; 3411 }; 3412 }; 3413 }; 3414 3415 out-ports { 3416 port { 3417 etr0_out: endpoint { 3418 remote-endpoint = <&ctcu_in0>; 3419 }; 3420 }; 3421 }; 3422 }; 3423 3424 replicator@404e000 { 3425 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3426 reg = <0x0 0x0404e000 0x0 0x1000>; 3427 3428 clocks = <&aoss_qmp>; 3429 clock-names = "apb_pclk"; 3430 3431 in-ports { 3432 port { 3433 etr_rep_in: endpoint { 3434 remote-endpoint = <&qdss_rep_out0>; 3435 }; 3436 }; 3437 }; 3438 3439 out-ports { 3440 #address-cells = <1>; 3441 #size-cells = <0>; 3442 3443 port@0 { 3444 reg = <0>; 3445 3446 etr_rep_out0: endpoint { 3447 remote-endpoint = <&etr0_in>; 3448 }; 3449 }; 3450 3451 port@1 { 3452 reg = <1>; 3453 3454 etr_rep_out1: endpoint { 3455 remote-endpoint = <&etr1_in>; 3456 }; 3457 }; 3458 }; 3459 }; 3460 3461 tmc_etr1: tmc@404f000 { 3462 compatible = "arm,coresight-tmc", "arm,primecell"; 3463 reg = <0x0 0x0404f000 0x0 0x1000>; 3464 3465 clocks = <&aoss_qmp>; 3466 clock-names = "apb_pclk"; 3467 iommus = <&apps_smmu 0x04a0 0x40>; 3468 3469 arm,scatter-gather; 3470 arm,buffer-size = <0x400000>; 3471 3472 in-ports { 3473 port { 3474 etr1_in: endpoint { 3475 remote-endpoint = <&etr_rep_out1>; 3476 }; 3477 }; 3478 }; 3479 3480 out-ports { 3481 port { 3482 etr1_out: endpoint { 3483 remote-endpoint = <&ctcu_in1>; 3484 }; 3485 }; 3486 }; 3487 }; 3488 3489 tpda@4ad3000 { 3490 compatible = "qcom,coresight-tpda", "arm,primecell"; 3491 reg = <0x0 0x4ad3000 0x0 0x1000>; 3492 3493 clocks = <&aoss_qmp>; 3494 clock-names = "apb_pclk"; 3495 3496 in-ports { 3497 #address-cells = <1>; 3498 #size-cells = <0>; 3499 3500 port@10 { 3501 reg = <16>; 3502 dlct0_tpda_in16: endpoint { 3503 remote-endpoint = <&turing0_funnel_out>; 3504 }; 3505 }; 3506 }; 3507 3508 out-ports { 3509 port { 3510 dlct0_tpda_out: endpoint { 3511 remote-endpoint = 3512 <&dlct0_funnel_in0>; 3513 }; 3514 }; 3515 }; 3516 3517 }; 3518 3519 funnel@4ad4000 { 3520 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3521 reg = <0x0 0x4ad4000 0x0 0x1000>; 3522 3523 clocks = <&aoss_qmp>; 3524 clock-names = "apb_pclk"; 3525 3526 in-ports { 3527 port { 3528 dlct0_funnel_in0: endpoint { 3529 remote-endpoint = <&dlct0_tpda_out>; 3530 }; 3531 }; 3532 }; 3533 3534 out-ports { 3535 port { 3536 dlct0_funnel_out: endpoint { 3537 remote-endpoint = <&funnel1_in5>; 3538 }; 3539 }; 3540 }; 3541 }; 3542 3543 funnel@4b04000 { 3544 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3545 reg = <0x0 0x4b04000 0x0 0x1000>; 3546 3547 clocks = <&aoss_qmp>; 3548 clock-names = "apb_pclk"; 3549 3550 out-ports { 3551 port { 3552 aoss_funnel_out: endpoint { 3553 remote-endpoint = 3554 <&etf0_in>; 3555 }; 3556 }; 3557 }; 3558 3559 in-ports { 3560 #address-cells = <1>; 3561 #size-cells = <0>; 3562 3563 port@6 { 3564 reg = <6>; 3565 aoss_funnel_in6: endpoint { 3566 remote-endpoint = 3567 <&aoss_tpda_out>; 3568 }; 3569 }; 3570 3571 port@7 { 3572 reg = <7>; 3573 aoss_funnel_in7: endpoint { 3574 remote-endpoint = 3575 <&qdss_funnel_out>; 3576 }; 3577 }; 3578 }; 3579 }; 3580 3581 tmc_etf: tmc@4b05000 { 3582 compatible = "arm,coresight-tmc", "arm,primecell"; 3583 reg = <0x0 0x4b05000 0x0 0x1000>; 3584 3585 clocks = <&aoss_qmp>; 3586 clock-names = "apb_pclk"; 3587 3588 out-ports { 3589 port { 3590 etf0_out: endpoint { 3591 remote-endpoint = 3592 <&swao_rep_in>; 3593 }; 3594 }; 3595 }; 3596 3597 in-ports { 3598 port { 3599 etf0_in: endpoint { 3600 remote-endpoint = 3601 <&aoss_funnel_out>; 3602 }; 3603 }; 3604 }; 3605 }; 3606 3607 replicator@4b06000 { 3608 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3609 reg = <0x0 0x4b06000 0x0 0x1000>; 3610 3611 clocks = <&aoss_qmp>; 3612 clock-names = "apb_pclk"; 3613 3614 out-ports { 3615 #address-cells = <1>; 3616 #size-cells = <0>; 3617 3618 port@0 { 3619 reg = <0>; 3620 3621 swao_rep_out0: endpoint { 3622 remote-endpoint = <&qdss_rep_in>; 3623 }; 3624 }; 3625 3626 port@1 { 3627 reg = <1>; 3628 swao_rep_out1: endpoint { 3629 remote-endpoint = 3630 <&eud_in>; 3631 }; 3632 }; 3633 }; 3634 3635 in-ports { 3636 port { 3637 swao_rep_in: endpoint { 3638 remote-endpoint = 3639 <&etf0_out>; 3640 }; 3641 }; 3642 }; 3643 }; 3644 3645 tpda@4b08000 { 3646 compatible = "qcom,coresight-tpda", "arm,primecell"; 3647 reg = <0x0 0x4b08000 0x0 0x1000>; 3648 3649 clocks = <&aoss_qmp>; 3650 clock-names = "apb_pclk"; 3651 3652 out-ports { 3653 port { 3654 aoss_tpda_out: endpoint { 3655 remote-endpoint = 3656 <&aoss_funnel_in6>; 3657 }; 3658 }; 3659 }; 3660 3661 in-ports { 3662 #address-cells = <1>; 3663 #size-cells = <0>; 3664 3665 port@0 { 3666 reg = <0>; 3667 aoss_tpda_in0: endpoint { 3668 remote-endpoint = 3669 <&aoss_tpdm0_out>; 3670 }; 3671 }; 3672 3673 port@1 { 3674 reg = <1>; 3675 aoss_tpda_in1: endpoint { 3676 remote-endpoint = 3677 <&aoss_tpdm1_out>; 3678 }; 3679 }; 3680 3681 port@2 { 3682 reg = <2>; 3683 aoss_tpda_in2: endpoint { 3684 remote-endpoint = 3685 <&aoss_tpdm2_out>; 3686 }; 3687 }; 3688 3689 port@3 { 3690 reg = <3>; 3691 aoss_tpda_in3: endpoint { 3692 remote-endpoint = 3693 <&aoss_tpdm3_out>; 3694 }; 3695 }; 3696 3697 port@4 { 3698 reg = <4>; 3699 aoss_tpda_in4: endpoint { 3700 remote-endpoint = 3701 <&aoss_tpdm4_out>; 3702 }; 3703 }; 3704 }; 3705 }; 3706 3707 tpdm@4b09000 { 3708 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3709 reg = <0x0 0x4b09000 0x0 0x1000>; 3710 3711 clocks = <&aoss_qmp>; 3712 clock-names = "apb_pclk"; 3713 label = "tpdm_swao_prio_0"; 3714 3715 qcom,cmb-element-bits = <64>; 3716 qcom,cmb-msrs-num = <32>; 3717 3718 out-ports { 3719 port { 3720 aoss_tpdm0_out: endpoint { 3721 remote-endpoint = 3722 <&aoss_tpda_in0>; 3723 }; 3724 }; 3725 }; 3726 }; 3727 3728 tpdm@4b0a000 { 3729 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3730 reg = <0x0 0x4b0a000 0x0 0x1000>; 3731 3732 clocks = <&aoss_qmp>; 3733 clock-names = "apb_pclk"; 3734 label = "tpdm_swao_prio_1"; 3735 3736 qcom,cmb-element-bits = <64>; 3737 qcom,cmb-msrs-num = <32>; 3738 3739 out-ports { 3740 port { 3741 aoss_tpdm1_out: endpoint { 3742 remote-endpoint = 3743 <&aoss_tpda_in1>; 3744 }; 3745 }; 3746 }; 3747 }; 3748 3749 tpdm@4b0b000 { 3750 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3751 reg = <0x0 0x4b0b000 0x0 0x1000>; 3752 3753 clocks = <&aoss_qmp>; 3754 clock-names = "apb_pclk"; 3755 label = "tpdm_swao_prio_2"; 3756 3757 qcom,cmb-element-bits = <64>; 3758 qcom,cmb-msrs-num = <32>; 3759 3760 out-ports { 3761 port { 3762 aoss_tpdm2_out: endpoint { 3763 remote-endpoint = 3764 <&aoss_tpda_in2>; 3765 }; 3766 }; 3767 }; 3768 }; 3769 3770 tpdm@4b0c000 { 3771 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3772 reg = <0x0 0x4b0c000 0x0 0x1000>; 3773 3774 clocks = <&aoss_qmp>; 3775 clock-names = "apb_pclk"; 3776 label = "tpdm_swao_prio_3"; 3777 3778 qcom,cmb-element-bits = <64>; 3779 qcom,cmb-msrs-num = <32>; 3780 3781 out-ports { 3782 port { 3783 aoss_tpdm3_out: endpoint { 3784 remote-endpoint = 3785 <&aoss_tpda_in3>; 3786 }; 3787 }; 3788 }; 3789 }; 3790 3791 tpdm@4b0d000 { 3792 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3793 reg = <0x0 0x4b0d000 0x0 0x1000>; 3794 3795 clocks = <&aoss_qmp>; 3796 clock-names = "apb_pclk"; 3797 label = "tpdm_swao_1"; 3798 3799 qcom,dsb-element-bits = <32>; 3800 qcom,dsb-msrs-num = <32>; 3801 3802 out-ports { 3803 port { 3804 aoss_tpdm4_out: endpoint { 3805 remote-endpoint = 3806 <&aoss_tpda_in4>; 3807 }; 3808 }; 3809 }; 3810 }; 3811 3812 aoss_cti: cti@4b13000 { 3813 compatible = "arm,coresight-cti", "arm,primecell"; 3814 reg = <0x0 0x4b13000 0x0 0x1000>; 3815 3816 clocks = <&aoss_qmp>; 3817 clock-names = "apb_pclk"; 3818 label = "cti_aoss"; 3819 }; 3820 3821 funnel@4b83000 { 3822 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3823 reg = <0x0 0x4b83000 0x0 0x1000>; 3824 3825 clocks = <&aoss_qmp>; 3826 clock-names = "apb_pclk"; 3827 3828 in-ports { 3829 #address-cells = <1>; 3830 #size-cells = <0>; 3831 3832 port@1 { 3833 reg = <1>; 3834 3835 turing0_funnel_in1: endpoint { 3836 remote-endpoint = <&turing_llm_tpdm_out>; 3837 }; 3838 }; 3839 }; 3840 3841 out-ports { 3842 port { 3843 turing0_funnel_out: endpoint { 3844 remote-endpoint = <&dlct0_tpda_in16>; 3845 }; 3846 }; 3847 }; 3848 }; 3849 3850 etm@6040000 { 3851 compatible = "arm,primecell"; 3852 reg = <0x0 0x6040000 0x0 0x1000>; 3853 cpu = <&cpu0>; 3854 3855 clocks = <&aoss_qmp>; 3856 clock-names = "apb_pclk"; 3857 arm,coresight-loses-context-with-cpu; 3858 qcom,skip-power-up; 3859 3860 out-ports { 3861 port { 3862 etm0_out: endpoint { 3863 remote-endpoint = 3864 <&apss_funnel0_in0>; 3865 }; 3866 }; 3867 }; 3868 }; 3869 3870 etm@6140000 { 3871 compatible = "arm,primecell"; 3872 reg = <0x0 0x6140000 0x0 0x1000>; 3873 cpu = <&cpu1>; 3874 3875 clocks = <&aoss_qmp>; 3876 clock-names = "apb_pclk"; 3877 arm,coresight-loses-context-with-cpu; 3878 qcom,skip-power-up; 3879 3880 out-ports { 3881 port { 3882 etm1_out: endpoint { 3883 remote-endpoint = 3884 <&apss_funnel0_in1>; 3885 }; 3886 }; 3887 }; 3888 }; 3889 3890 etm@6240000 { 3891 compatible = "arm,primecell"; 3892 reg = <0x0 0x6240000 0x0 0x1000>; 3893 cpu = <&cpu2>; 3894 3895 clocks = <&aoss_qmp>; 3896 clock-names = "apb_pclk"; 3897 arm,coresight-loses-context-with-cpu; 3898 qcom,skip-power-up; 3899 3900 out-ports { 3901 port { 3902 etm2_out: endpoint { 3903 remote-endpoint = 3904 <&apss_funnel0_in2>; 3905 }; 3906 }; 3907 }; 3908 }; 3909 3910 etm@6340000 { 3911 compatible = "arm,primecell"; 3912 reg = <0x0 0x6340000 0x0 0x1000>; 3913 cpu = <&cpu3>; 3914 3915 clocks = <&aoss_qmp>; 3916 clock-names = "apb_pclk"; 3917 arm,coresight-loses-context-with-cpu; 3918 qcom,skip-power-up; 3919 3920 out-ports { 3921 port { 3922 etm3_out: endpoint { 3923 remote-endpoint = 3924 <&apss_funnel0_in3>; 3925 }; 3926 }; 3927 }; 3928 }; 3929 3930 etm@6440000 { 3931 compatible = "arm,primecell"; 3932 reg = <0x0 0x6440000 0x0 0x1000>; 3933 cpu = <&cpu4>; 3934 3935 clocks = <&aoss_qmp>; 3936 clock-names = "apb_pclk"; 3937 arm,coresight-loses-context-with-cpu; 3938 qcom,skip-power-up; 3939 3940 out-ports { 3941 port { 3942 etm4_out: endpoint { 3943 remote-endpoint = 3944 <&apss_funnel0_in4>; 3945 }; 3946 }; 3947 }; 3948 }; 3949 3950 etm@6540000 { 3951 compatible = "arm,primecell"; 3952 reg = <0x0 0x6540000 0x0 0x1000>; 3953 cpu = <&cpu5>; 3954 3955 clocks = <&aoss_qmp>; 3956 clock-names = "apb_pclk"; 3957 arm,coresight-loses-context-with-cpu; 3958 qcom,skip-power-up; 3959 3960 out-ports { 3961 port { 3962 etm5_out: endpoint { 3963 remote-endpoint = 3964 <&apss_funnel0_in5>; 3965 }; 3966 }; 3967 }; 3968 }; 3969 3970 etm@6640000 { 3971 compatible = "arm,primecell"; 3972 reg = <0x0 0x6640000 0x0 0x1000>; 3973 cpu = <&cpu6>; 3974 3975 clocks = <&aoss_qmp>; 3976 clock-names = "apb_pclk"; 3977 arm,coresight-loses-context-with-cpu; 3978 qcom,skip-power-up; 3979 3980 out-ports { 3981 port { 3982 etm6_out: endpoint { 3983 remote-endpoint = 3984 <&apss_funnel0_in6>; 3985 }; 3986 }; 3987 }; 3988 }; 3989 3990 etm@6740000 { 3991 compatible = "arm,primecell"; 3992 reg = <0x0 0x6740000 0x0 0x1000>; 3993 cpu = <&cpu7>; 3994 3995 clocks = <&aoss_qmp>; 3996 clock-names = "apb_pclk"; 3997 arm,coresight-loses-context-with-cpu; 3998 qcom,skip-power-up; 3999 4000 out-ports { 4001 port { 4002 etm7_out: endpoint { 4003 remote-endpoint = 4004 <&apss_funnel0_in7>; 4005 }; 4006 }; 4007 }; 4008 }; 4009 4010 funnel@6800000 { 4011 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4012 reg = <0x0 0x6800000 0x0 0x1000>; 4013 4014 clocks = <&aoss_qmp>; 4015 clock-names = "apb_pclk"; 4016 4017 out-ports { 4018 port { 4019 apss_funnel0_out: endpoint { 4020 remote-endpoint = 4021 <&apss_funnel1_in0>; 4022 }; 4023 }; 4024 }; 4025 4026 in-ports { 4027 #address-cells = <1>; 4028 #size-cells = <0>; 4029 4030 port@0 { 4031 reg = <0>; 4032 apss_funnel0_in0: endpoint { 4033 remote-endpoint = 4034 <&etm0_out>; 4035 }; 4036 }; 4037 4038 port@1 { 4039 reg = <1>; 4040 apss_funnel0_in1: endpoint { 4041 remote-endpoint = 4042 <&etm1_out>; 4043 }; 4044 }; 4045 4046 port@2 { 4047 reg = <2>; 4048 apss_funnel0_in2: endpoint { 4049 remote-endpoint = 4050 <&etm2_out>; 4051 }; 4052 }; 4053 4054 port@3 { 4055 reg = <3>; 4056 apss_funnel0_in3: endpoint { 4057 remote-endpoint = 4058 <&etm3_out>; 4059 }; 4060 }; 4061 4062 port@4 { 4063 reg = <4>; 4064 apss_funnel0_in4: endpoint { 4065 remote-endpoint = 4066 <&etm4_out>; 4067 }; 4068 }; 4069 4070 port@5 { 4071 reg = <5>; 4072 apss_funnel0_in5: endpoint { 4073 remote-endpoint = 4074 <&etm5_out>; 4075 }; 4076 }; 4077 4078 port@6 { 4079 reg = <6>; 4080 apss_funnel0_in6: endpoint { 4081 remote-endpoint = 4082 <&etm6_out>; 4083 }; 4084 }; 4085 4086 port@7 { 4087 reg = <7>; 4088 apss_funnel0_in7: endpoint { 4089 remote-endpoint = 4090 <&etm7_out>; 4091 }; 4092 }; 4093 }; 4094 }; 4095 4096 funnel@6810000 { 4097 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4098 reg = <0x0 0x6810000 0x0 0x1000>; 4099 4100 clocks = <&aoss_qmp>; 4101 clock-names = "apb_pclk"; 4102 4103 out-ports { 4104 port { 4105 apss_funnel1_out: endpoint { 4106 remote-endpoint = 4107 <&funnel1_in4>; 4108 }; 4109 }; 4110 }; 4111 4112 in-ports { 4113 #address-cells = <1>; 4114 #size-cells = <0>; 4115 4116 port@0 { 4117 reg = <0>; 4118 apss_funnel1_in0: endpoint { 4119 remote-endpoint = 4120 <&apss_funnel0_out>; 4121 }; 4122 }; 4123 4124 port@3 { 4125 reg = <3>; 4126 apss_funnel1_in3: endpoint { 4127 remote-endpoint = 4128 <&apss_tpda_out>; 4129 }; 4130 }; 4131 }; 4132 }; 4133 4134 tpdm@6860000 { 4135 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4136 reg = <0x0 0x6860000 0x0 0x1000>; 4137 4138 clocks = <&aoss_qmp>; 4139 clock-names = "apb_pclk"; 4140 label = "tpdm_actpm"; 4141 4142 qcom,cmb-element-bits = <64>; 4143 qcom,cmb-msrs-num = <32>; 4144 4145 out-ports { 4146 port { 4147 apss_tpdm3_out: endpoint { 4148 remote-endpoint = 4149 <&apss_tpda_in3>; 4150 }; 4151 }; 4152 }; 4153 }; 4154 4155 tpdm@6861000 { 4156 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4157 reg = <0x0 0x6861000 0x0 0x1000>; 4158 4159 clocks = <&aoss_qmp>; 4160 clock-names = "apb_pclk"; 4161 label = "tpdm_apss"; 4162 4163 qcom,dsb-element-bits = <32>; 4164 qcom,dsb-msrs-num = <32>; 4165 4166 out-ports { 4167 port { 4168 apss_tpdm4_out: endpoint { 4169 remote-endpoint = 4170 <&apss_tpda_in4>; 4171 }; 4172 }; 4173 }; 4174 }; 4175 4176 tpda@6863000 { 4177 compatible = "qcom,coresight-tpda", "arm,primecell"; 4178 reg = <0x0 0x6863000 0x0 0x1000>; 4179 4180 clocks = <&aoss_qmp>; 4181 clock-names = "apb_pclk"; 4182 4183 out-ports { 4184 port { 4185 apss_tpda_out: endpoint { 4186 remote-endpoint = 4187 <&apss_funnel1_in3>; 4188 }; 4189 }; 4190 }; 4191 4192 in-ports { 4193 #address-cells = <1>; 4194 #size-cells = <0>; 4195 4196 port@0 { 4197 reg = <0>; 4198 apss_tpda_in0: endpoint { 4199 remote-endpoint = 4200 <&apss_tpdm0_out>; 4201 }; 4202 }; 4203 4204 port@1 { 4205 reg = <1>; 4206 apss_tpda_in1: endpoint { 4207 remote-endpoint = 4208 <&apss_tpdm1_out>; 4209 }; 4210 }; 4211 4212 port@2 { 4213 reg = <2>; 4214 apss_tpda_in2: endpoint { 4215 remote-endpoint = 4216 <&apss_tpdm2_out>; 4217 }; 4218 }; 4219 4220 port@3 { 4221 reg = <3>; 4222 apss_tpda_in3: endpoint { 4223 remote-endpoint = 4224 <&apss_tpdm3_out>; 4225 }; 4226 }; 4227 4228 port@4 { 4229 reg = <4>; 4230 apss_tpda_in4: endpoint { 4231 remote-endpoint = 4232 <&apss_tpdm4_out>; 4233 }; 4234 }; 4235 }; 4236 }; 4237 4238 tpdm@68a0000 { 4239 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4240 reg = <0x0 0x68a0000 0x0 0x1000>; 4241 4242 clocks = <&aoss_qmp>; 4243 clock-names = "apb_pclk"; 4244 label = "tpdm_llm_silver"; 4245 4246 qcom,cmb-element-bits = <32>; 4247 qcom,cmb-msrs-num = <32>; 4248 4249 out-ports { 4250 port { 4251 apss_tpdm0_out: endpoint { 4252 remote-endpoint = 4253 <&apss_tpda_in0>; 4254 }; 4255 }; 4256 }; 4257 }; 4258 4259 tpdm@68b0000 { 4260 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4261 reg = <0x0 0x68b0000 0x0 0x1000>; 4262 4263 clocks = <&aoss_qmp>; 4264 clock-names = "apb_pclk"; 4265 label = "tpdm_llm_gold"; 4266 4267 qcom,cmb-element-bits = <32>; 4268 qcom,cmb-msrs-num = <32>; 4269 4270 out-ports { 4271 port { 4272 apss_tpdm1_out: endpoint { 4273 remote-endpoint = 4274 <&apss_tpda_in1>; 4275 }; 4276 }; 4277 }; 4278 }; 4279 4280 tpdm@68c0000 { 4281 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4282 reg = <0x0 0x68c0000 0x0 0x1000>; 4283 4284 clocks = <&aoss_qmp>; 4285 clock-names = "apb_pclk"; 4286 label = "tpdm_llm_ext"; 4287 4288 qcom,dsb-element-bits = <32>; 4289 qcom,dsb-msrs-num = <32>; 4290 4291 out-ports { 4292 port { 4293 apss_tpdm2_out: endpoint { 4294 remote-endpoint = 4295 <&apss_tpda_in2>; 4296 }; 4297 }; 4298 }; 4299 }; 4300 4301 sdhc: mmc@87c4000 { 4302 compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; 4303 reg = <0x0 0x087c4000 0x0 0x1000>; 4304 4305 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 4306 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; 4307 interrupt-names = "hc_irq", 4308 "pwr_irq"; 4309 4310 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 4311 <&gcc GCC_SDCC1_APPS_CLK>; 4312 clock-names = "iface", 4313 "core"; 4314 4315 interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS 4316 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4317 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4318 &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4319 interconnect-names = "sdhc-ddr", 4320 "cpu-sdhc"; 4321 4322 iommus = <&apps_smmu 0x0 0x0>; 4323 dma-coherent; 4324 4325 operating-points-v2 = <&sdhc_opp_table>; 4326 power-domains = <&rpmhpd SA8775P_CX>; 4327 resets = <&gcc GCC_SDCC1_BCR>; 4328 4329 qcom,dll-config = <0x0007642c>; 4330 qcom,ddr-config = <0x80040868>; 4331 4332 status = "disabled"; 4333 4334 sdhc_opp_table: opp-table { 4335 compatible = "operating-points-v2"; 4336 4337 opp-100000000 { 4338 opp-hz = /bits/ 64 <100000000>; 4339 required-opps = <&rpmhpd_opp_low_svs>; 4340 opp-peak-kBps = <1800000 400000>; 4341 opp-avg-kBps = <100000 0>; 4342 }; 4343 4344 opp-384000000 { 4345 opp-hz = /bits/ 64 <384000000>; 4346 required-opps = <&rpmhpd_opp_nom>; 4347 opp-peak-kBps = <5400000 1600000>; 4348 opp-avg-kBps = <390000 0>; 4349 }; 4350 }; 4351 }; 4352 4353 usb_0_hsphy: phy@88e4000 { 4354 compatible = "qcom,sa8775p-usb-hs-phy", 4355 "qcom,usb-snps-hs-5nm-phy"; 4356 reg = <0 0x088e4000 0 0x120>; 4357 clocks = <&rpmhcc RPMH_CXO_CLK>; 4358 clock-names = "ref"; 4359 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 4360 4361 #phy-cells = <0>; 4362 4363 status = "disabled"; 4364 }; 4365 4366 usb_1_hsphy: phy@88e6000 { 4367 compatible = "qcom,sa8775p-usb-hs-phy", 4368 "qcom,usb-snps-hs-5nm-phy"; 4369 reg = <0 0x088e6000 0 0x120>; 4370 clocks = <&gcc GCC_USB_CLKREF_EN>; 4371 clock-names = "ref"; 4372 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 4373 4374 #phy-cells = <0>; 4375 4376 status = "disabled"; 4377 }; 4378 4379 usb_2_hsphy: phy@88e7000 { 4380 compatible = "qcom,sa8775p-usb-hs-phy", 4381 "qcom,usb-snps-hs-5nm-phy"; 4382 reg = <0 0x088e7000 0 0x120>; 4383 clocks = <&gcc GCC_USB_CLKREF_EN>; 4384 clock-names = "ref"; 4385 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 4386 4387 #phy-cells = <0>; 4388 4389 status = "disabled"; 4390 }; 4391 4392 usb_0_qmpphy: phy@88e8000 { 4393 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 4394 reg = <0 0x088e8000 0 0x2000>; 4395 4396 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4397 <&gcc GCC_USB_CLKREF_EN>, 4398 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4399 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4400 clock-names = "aux", "ref", "com_aux", "pipe"; 4401 4402 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4403 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 4404 reset-names = "phy", "phy_phy"; 4405 4406 power-domains = <&gcc USB30_PRIM_GDSC>; 4407 4408 #clock-cells = <0>; 4409 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 4410 4411 #phy-cells = <0>; 4412 4413 status = "disabled"; 4414 }; 4415 4416 usb_1_qmpphy: phy@88ea000 { 4417 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 4418 reg = <0 0x088ea000 0 0x2000>; 4419 4420 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4421 <&gcc GCC_USB_CLKREF_EN>, 4422 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 4423 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4424 clock-names = "aux", "ref", "com_aux", "pipe"; 4425 4426 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 4427 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 4428 reset-names = "phy", "phy_phy"; 4429 4430 power-domains = <&gcc USB30_SEC_GDSC>; 4431 4432 #clock-cells = <0>; 4433 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 4434 4435 #phy-cells = <0>; 4436 4437 status = "disabled"; 4438 }; 4439 4440 refgen: regulator@891c000 { 4441 compatible = "qcom,sa8775p-refgen-regulator", 4442 "qcom,sm8250-refgen-regulator"; 4443 reg = <0x0 0x0891c000 0x0 0x84>; 4444 }; 4445 4446 dc_noc: interconnect@90e0000 { 4447 compatible = "qcom,sa8775p-dc-noc"; 4448 reg = <0x0 0x090e0000 0x0 0x5080>; 4449 #interconnect-cells = <2>; 4450 qcom,bcm-voters = <&apps_bcm_voter>; 4451 }; 4452 4453 gem_noc: interconnect@9100000 { 4454 compatible = "qcom,sa8775p-gem-noc"; 4455 reg = <0x0 0x09100000 0x0 0xf6080>; 4456 #interconnect-cells = <2>; 4457 qcom,bcm-voters = <&apps_bcm_voter>; 4458 }; 4459 4460 usb_0: usb@a600000 { 4461 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4462 reg = <0 0x0a600000 0 0xfc100>; 4463 4464 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4465 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4466 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4467 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4468 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4469 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4470 4471 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4472 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4473 assigned-clock-rates = <19200000>, <200000000>; 4474 4475 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 4476 <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 4477 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4478 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4479 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4480 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 4481 interrupt-names = "dwc_usb3", 4482 "pwr_event", 4483 "hs_phy_irq", 4484 "dp_hs_phy_irq", 4485 "dm_hs_phy_irq", 4486 "ss_phy_irq"; 4487 4488 power-domains = <&gcc USB30_PRIM_GDSC>; 4489 required-opps = <&rpmhpd_opp_nom>; 4490 4491 resets = <&gcc GCC_USB30_PRIM_BCR>; 4492 4493 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4494 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4495 interconnect-names = "usb-ddr", "apps-usb"; 4496 4497 wakeup-source; 4498 4499 iommus = <&apps_smmu 0x080 0x0>; 4500 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 4501 phy-names = "usb2-phy", "usb3-phy"; 4502 snps,dis-u1-entry-quirk; 4503 snps,dis-u2-entry-quirk; 4504 4505 usb-role-switch; 4506 status = "disabled"; 4507 4508 ports { 4509 #address-cells = <1>; 4510 #size-cells = <0>; 4511 4512 port@0 { 4513 reg = <0>; 4514 4515 usb_0_dwc3_hs: endpoint { 4516 }; 4517 }; 4518 4519 port@1 { 4520 reg = <1>; 4521 4522 usb_0_dwc3_ss: endpoint { 4523 }; 4524 }; 4525 }; 4526 }; 4527 4528 usb_1: usb@a800000 { 4529 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4530 reg = <0 0x0a800000 0 0xfc100>; 4531 4532 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4533 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4534 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4535 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4536 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4537 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4538 4539 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4540 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4541 assigned-clock-rates = <19200000>, <200000000>; 4542 4543 interrupts-extended = <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 4544 <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 4545 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 4546 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 4547 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 4548 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 4549 interrupt-names = "dwc_usb3", 4550 "pwr_event", 4551 "hs_phy_irq", 4552 "dp_hs_phy_irq", 4553 "dm_hs_phy_irq", 4554 "ss_phy_irq"; 4555 4556 power-domains = <&gcc USB30_SEC_GDSC>; 4557 required-opps = <&rpmhpd_opp_nom>; 4558 4559 resets = <&gcc GCC_USB30_SEC_BCR>; 4560 4561 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 4562 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4563 interconnect-names = "usb-ddr", "apps-usb"; 4564 4565 wakeup-source; 4566 4567 iommus = <&apps_smmu 0x0a0 0x0>; 4568 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 4569 phy-names = "usb2-phy", "usb3-phy"; 4570 snps,dis-u1-entry-quirk; 4571 snps,dis-u2-entry-quirk; 4572 4573 status = "disabled"; 4574 }; 4575 4576 usb_2: usb@a400000 { 4577 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4578 reg = <0 0x0a400000 0 0xfc100>; 4579 4580 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4581 <&gcc GCC_USB20_MASTER_CLK>, 4582 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4583 <&gcc GCC_USB20_SLEEP_CLK>, 4584 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 4585 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4586 4587 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4588 <&gcc GCC_USB20_MASTER_CLK>; 4589 assigned-clock-rates = <19200000>, <200000000>; 4590 4591 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 4592 <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 4593 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 4594 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 4595 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 4596 interrupt-names = "dwc_usb3", 4597 "pwr_event", 4598 "hs_phy_irq", 4599 "dp_hs_phy_irq", 4600 "dm_hs_phy_irq"; 4601 4602 power-domains = <&gcc USB20_PRIM_GDSC>; 4603 required-opps = <&rpmhpd_opp_nom>; 4604 4605 resets = <&gcc GCC_USB20_PRIM_BCR>; 4606 4607 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 4608 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 4609 interconnect-names = "usb-ddr", "apps-usb"; 4610 4611 qcom,select-utmi-as-pipe-clk; 4612 wakeup-source; 4613 4614 iommus = <&apps_smmu 0x020 0x0>; 4615 phys = <&usb_2_hsphy>; 4616 phy-names = "usb2-phy"; 4617 snps,dis-u1-entry-quirk; 4618 snps,dis-u2-entry-quirk; 4619 4620 usb-role-switch; 4621 4622 status = "disabled"; 4623 4624 port { 4625 usb_2_dwc3_hs: endpoint { 4626 }; 4627 }; 4628 }; 4629 4630 tcsr_mutex: hwlock@1f40000 { 4631 compatible = "qcom,tcsr-mutex"; 4632 reg = <0x0 0x01f40000 0x0 0x20000>; 4633 #hwlock-cells = <1>; 4634 }; 4635 4636 tcsr: syscon@1fc0000 { 4637 compatible = "qcom,sa8775p-tcsr", "syscon"; 4638 reg = <0x0 0x1fc0000 0x0 0x30000>; 4639 }; 4640 4641 gpu: gpu@3d00000 { 4642 compatible = "qcom,adreno-663.0", "qcom,adreno"; 4643 reg = <0x0 0x03d00000 0x0 0x40000>, 4644 <0x0 0x03d9e000 0x0 0x1000>, 4645 <0x0 0x03d61000 0x0 0x800>; 4646 reg-names = "kgsl_3d0_reg_memory", 4647 "cx_mem", 4648 "cx_dbgc"; 4649 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4650 iommus = <&adreno_smmu 0 0xc00>, 4651 <&adreno_smmu 1 0xc00>; 4652 operating-points-v2 = <&gpu_opp_table>; 4653 qcom,gmu = <&gmu>; 4654 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4655 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4656 interconnect-names = "gfx-mem"; 4657 #cooling-cells = <2>; 4658 4659 nvmem-cells = <&gpu_speed_bin>; 4660 nvmem-cell-names = "speed_bin"; 4661 4662 status = "disabled"; 4663 4664 gpu_zap_shader: zap-shader { 4665 memory-region = <&pil_gpu_mem>; 4666 }; 4667 4668 gpu_opp_table: opp-table { 4669 compatible = "operating-points-v2"; 4670 4671 opp-405000000 { 4672 opp-hz = /bits/ 64 <405000000>; 4673 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4674 opp-peak-kBps = <5285156>; 4675 opp-supported-hw = <0x3>; 4676 }; 4677 4678 opp-530000000 { 4679 opp-hz = /bits/ 64 <530000000>; 4680 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4681 opp-peak-kBps = <12484375>; 4682 opp-supported-hw = <0x2>; 4683 }; 4684 4685 opp-676000000 { 4686 opp-hz = /bits/ 64 <676000000>; 4687 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4688 opp-peak-kBps = <8171875>; 4689 opp-supported-hw = <0x1>; 4690 }; 4691 4692 opp-778000000 { 4693 opp-hz = /bits/ 64 <778000000>; 4694 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4695 opp-peak-kBps = <10687500>; 4696 opp-supported-hw = <0x1>; 4697 }; 4698 4699 opp-800000000 { 4700 opp-hz = /bits/ 64 <800000000>; 4701 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4702 opp-peak-kBps = <12484375>; 4703 opp-supported-hw = <0x1>; 4704 }; 4705 }; 4706 }; 4707 4708 gmu: gmu@3d6a000 { 4709 compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; 4710 reg = <0x0 0x03d6a000 0x0 0x34000>, 4711 <0x0 0x03de0000 0x0 0x10000>, 4712 <0x0 0x0b290000 0x0 0x10000>; 4713 reg-names = "gmu", "rscc", "gmu_pdc"; 4714 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4715 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4716 interrupt-names = "hfi", "gmu"; 4717 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4718 <&gpucc GPU_CC_CXO_CLK>, 4719 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4720 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4721 <&gpucc GPU_CC_AHB_CLK>, 4722 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4723 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 4724 clock-names = "gmu", 4725 "cxo", 4726 "axi", 4727 "memnoc", 4728 "ahb", 4729 "hub", 4730 "smmu_vote"; 4731 power-domains = <&gpucc GPU_CC_CX_GDSC>, 4732 <&gpucc GPU_CC_GX_GDSC>; 4733 power-domain-names = "cx", 4734 "gx"; 4735 iommus = <&adreno_smmu 5 0xc00>; 4736 operating-points-v2 = <&gmu_opp_table>; 4737 4738 gmu_opp_table: opp-table { 4739 compatible = "operating-points-v2"; 4740 4741 opp-500000000 { 4742 opp-hz = /bits/ 64 <500000000>; 4743 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4744 }; 4745 }; 4746 }; 4747 4748 gpucc: clock-controller@3d90000 { 4749 compatible = "qcom,sa8775p-gpucc"; 4750 reg = <0x0 0x03d90000 0x0 0xa000>; 4751 clocks = <&rpmhcc RPMH_CXO_CLK>, 4752 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4753 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4754 clock-names = "bi_tcxo", 4755 "gcc_gpu_gpll0_clk_src", 4756 "gcc_gpu_gpll0_div_clk_src"; 4757 #clock-cells = <1>; 4758 #reset-cells = <1>; 4759 #power-domain-cells = <1>; 4760 }; 4761 4762 adreno_smmu: iommu@3da0000 { 4763 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 4764 "qcom,smmu-500", "arm,mmu-500"; 4765 reg = <0x0 0x03da0000 0x0 0x20000>; 4766 #iommu-cells = <2>; 4767 #global-interrupts = <2>; 4768 dma-coherent; 4769 power-domains = <&gpucc GPU_CC_CX_GDSC>; 4770 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4771 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4772 <&gpucc GPU_CC_AHB_CLK>, 4773 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4774 <&gpucc GPU_CC_CX_GMU_CLK>, 4775 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4776 <&gpucc GPU_CC_HUB_AON_CLK>; 4777 clock-names = "gcc_gpu_memnoc_gfx_clk", 4778 "gcc_gpu_snoc_dvm_gfx_clk", 4779 "gpu_cc_ahb_clk", 4780 "gpu_cc_hlos1_vote_gpu_smmu_clk", 4781 "gpu_cc_cx_gmu_clk", 4782 "gpu_cc_hub_cx_int_clk", 4783 "gpu_cc_hub_aon_clk"; 4784 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 4785 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4786 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4787 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4788 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4789 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4790 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4791 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4792 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4793 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4794 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4795 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 4796 }; 4797 4798 serdes0: phy@8901000 { 4799 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4800 reg = <0x0 0x08901000 0x0 0xe10>; 4801 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4802 clock-names = "sgmi_ref"; 4803 #phy-cells = <0>; 4804 status = "disabled"; 4805 }; 4806 4807 serdes1: phy@8902000 { 4808 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4809 reg = <0x0 0x08902000 0x0 0xe10>; 4810 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4811 clock-names = "sgmi_ref"; 4812 #phy-cells = <0>; 4813 status = "disabled"; 4814 }; 4815 4816 pmu@9091000 { 4817 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4818 reg = <0x0 0x9091000 0x0 0x1000>; 4819 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 4820 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 4821 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4822 4823 operating-points-v2 = <&llcc_bwmon_opp_table>; 4824 4825 llcc_bwmon_opp_table: opp-table { 4826 compatible = "operating-points-v2"; 4827 4828 opp-0 { 4829 opp-peak-kBps = <762000>; 4830 }; 4831 4832 opp-1 { 4833 opp-peak-kBps = <1720000>; 4834 }; 4835 4836 opp-2 { 4837 opp-peak-kBps = <2086000>; 4838 }; 4839 4840 opp-3 { 4841 opp-peak-kBps = <2601000>; 4842 }; 4843 4844 opp-4 { 4845 opp-peak-kBps = <2929000>; 4846 }; 4847 4848 opp-5 { 4849 opp-peak-kBps = <5931000>; 4850 }; 4851 4852 opp-6 { 4853 opp-peak-kBps = <6515000>; 4854 }; 4855 4856 opp-7 { 4857 opp-peak-kBps = <7984000>; 4858 }; 4859 4860 opp-8 { 4861 opp-peak-kBps = <10437000>; 4862 }; 4863 4864 opp-9 { 4865 opp-peak-kBps = <12195000>; 4866 }; 4867 }; 4868 }; 4869 4870 pmu@90b5400 { 4871 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4872 reg = <0x0 0x90b5400 0x0 0x600>; 4873 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4874 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4875 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4876 4877 operating-points-v2 = <&cpu_bwmon_opp_table>; 4878 4879 cpu_bwmon_opp_table: opp-table { 4880 compatible = "operating-points-v2"; 4881 4882 opp-0 { 4883 opp-peak-kBps = <9155000>; 4884 }; 4885 4886 opp-1 { 4887 opp-peak-kBps = <12298000>; 4888 }; 4889 4890 opp-2 { 4891 opp-peak-kBps = <14236000>; 4892 }; 4893 4894 opp-3 { 4895 opp-peak-kBps = <16265000>; 4896 }; 4897 }; 4898 4899 }; 4900 4901 pmu@90b6400 { 4902 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4903 reg = <0x0 0x90b6400 0x0 0x600>; 4904 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4905 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4906 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4907 4908 operating-points-v2 = <&cpu_bwmon_opp_table>; 4909 }; 4910 4911 llcc: system-cache-controller@9200000 { 4912 compatible = "qcom,sa8775p-llcc"; 4913 reg = <0x0 0x09200000 0x0 0x80000>, 4914 <0x0 0x09300000 0x0 0x80000>, 4915 <0x0 0x09400000 0x0 0x80000>, 4916 <0x0 0x09500000 0x0 0x80000>, 4917 <0x0 0x09600000 0x0 0x80000>, 4918 <0x0 0x09700000 0x0 0x80000>, 4919 <0x0 0x09a00000 0x0 0x80000>; 4920 reg-names = "llcc0_base", 4921 "llcc1_base", 4922 "llcc2_base", 4923 "llcc3_base", 4924 "llcc4_base", 4925 "llcc5_base", 4926 "llcc_broadcast_base"; 4927 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 4928 }; 4929 4930 iris: video-codec@aa00000 { 4931 compatible = "qcom,sa8775p-iris", "qcom,sm8550-iris"; 4932 4933 reg = <0x0 0x0aa00000 0x0 0xf0000>; 4934 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4935 4936 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 4937 <&videocc VIDEO_CC_MVS0_GDSC>, 4938 <&rpmhpd SA8775P_MX>, 4939 <&rpmhpd SA8775P_MMCX>; 4940 power-domain-names = "venus", 4941 "vcodec0", 4942 "mxc", 4943 "mmcx"; 4944 operating-points-v2 = <&iris_opp_table>; 4945 4946 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4947 <&videocc VIDEO_CC_MVS0C_CLK>, 4948 <&videocc VIDEO_CC_MVS0_CLK>; 4949 clock-names = "iface", 4950 "core", 4951 "vcodec0_core"; 4952 4953 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4954 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4955 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4956 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4957 interconnect-names = "cpu-cfg", 4958 "video-mem"; 4959 4960 memory-region = <&pil_video_mem>; 4961 4962 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 4963 reset-names = "bus"; 4964 4965 iommus = <&apps_smmu 0x0880 0x0400>, 4966 <&apps_smmu 0x0887 0x0400>; 4967 dma-coherent; 4968 4969 status = "disabled"; 4970 4971 iris_opp_table: opp-table { 4972 compatible = "operating-points-v2"; 4973 4974 opp-366000000 { 4975 opp-hz = /bits/ 64 <366000000>; 4976 required-opps = <&rpmhpd_opp_svs_l1>, 4977 <&rpmhpd_opp_svs_l1>; 4978 }; 4979 4980 opp-444000000 { 4981 opp-hz = /bits/ 64 <444000000>; 4982 required-opps = <&rpmhpd_opp_svs_l1>, 4983 <&rpmhpd_opp_nom>; 4984 }; 4985 4986 opp-533000000 { 4987 opp-hz = /bits/ 64 <533000000>; 4988 required-opps = <&rpmhpd_opp_nom>, 4989 <&rpmhpd_opp_turbo>; 4990 }; 4991 4992 opp-560000000 { 4993 opp-hz = /bits/ 64 <560000000>; 4994 required-opps = <&rpmhpd_opp_nom>, 4995 <&rpmhpd_opp_turbo_l1>; 4996 }; 4997 }; 4998 }; 4999 5000 videocc: clock-controller@abf0000 { 5001 compatible = "qcom,sa8775p-videocc"; 5002 reg = <0x0 0x0abf0000 0x0 0x10000>; 5003 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 5004 <&rpmhcc RPMH_CXO_CLK>, 5005 <&rpmhcc RPMH_CXO_CLK_A>, 5006 <&sleep_clk>; 5007 power-domains = <&rpmhpd SA8775P_MMCX>; 5008 #clock-cells = <1>; 5009 #reset-cells = <1>; 5010 #power-domain-cells = <1>; 5011 }; 5012 5013 cci0: cci@ac13000 { 5014 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 5015 reg = <0x0 0x0ac13000 0x0 0x1000>; 5016 5017 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 5018 5019 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5020 5021 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5022 <&camcc CAM_CC_CPAS_AHB_CLK>, 5023 <&camcc CAM_CC_CCI_0_CLK>; 5024 clock-names = "camnoc_axi", 5025 "cpas_ahb", 5026 "cci"; 5027 5028 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 5029 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 5030 pinctrl-names = "default", "sleep"; 5031 5032 #address-cells = <1>; 5033 #size-cells = <0>; 5034 5035 status = "disabled"; 5036 5037 cci0_i2c0: i2c-bus@0 { 5038 reg = <0>; 5039 clock-frequency = <1000000>; 5040 #address-cells = <1>; 5041 #size-cells = <0>; 5042 }; 5043 5044 cci0_i2c1: i2c-bus@1 { 5045 reg = <1>; 5046 clock-frequency = <1000000>; 5047 #address-cells = <1>; 5048 #size-cells = <0>; 5049 }; 5050 }; 5051 5052 cci1: cci@ac14000 { 5053 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 5054 reg = <0x0 0x0ac14000 0x0 0x1000>; 5055 5056 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 5057 5058 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5059 5060 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5061 <&camcc CAM_CC_CPAS_AHB_CLK>, 5062 <&camcc CAM_CC_CCI_1_CLK>; 5063 clock-names = "camnoc_axi", 5064 "cpas_ahb", 5065 "cci"; 5066 5067 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 5068 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 5069 pinctrl-names = "default", "sleep"; 5070 5071 #address-cells = <1>; 5072 #size-cells = <0>; 5073 5074 status = "disabled"; 5075 5076 cci1_i2c0: i2c-bus@0 { 5077 reg = <0>; 5078 clock-frequency = <1000000>; 5079 #address-cells = <1>; 5080 #size-cells = <0>; 5081 }; 5082 5083 cci1_i2c1: i2c-bus@1 { 5084 reg = <1>; 5085 clock-frequency = <1000000>; 5086 #address-cells = <1>; 5087 #size-cells = <0>; 5088 }; 5089 }; 5090 5091 cci2: cci@ac15000 { 5092 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 5093 reg = <0x0 0x0ac15000 0x0 0x1000>; 5094 5095 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 5096 5097 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5098 5099 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5100 <&camcc CAM_CC_CPAS_AHB_CLK>, 5101 <&camcc CAM_CC_CCI_2_CLK>; 5102 clock-names = "camnoc_axi", 5103 "cpas_ahb", 5104 "cci"; 5105 5106 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 5107 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 5108 pinctrl-names = "default", "sleep"; 5109 5110 #address-cells = <1>; 5111 #size-cells = <0>; 5112 5113 status = "disabled"; 5114 5115 cci2_i2c0: i2c-bus@0 { 5116 reg = <0>; 5117 clock-frequency = <1000000>; 5118 #address-cells = <1>; 5119 #size-cells = <0>; 5120 }; 5121 5122 cci2_i2c1: i2c-bus@1 { 5123 reg = <1>; 5124 clock-frequency = <1000000>; 5125 #address-cells = <1>; 5126 #size-cells = <0>; 5127 }; 5128 }; 5129 5130 cci3: cci@ac16000 { 5131 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 5132 reg = <0x0 0x0ac16000 0x0 0x1000>; 5133 5134 interrupts = <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>; 5135 5136 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5137 5138 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5139 <&camcc CAM_CC_CPAS_AHB_CLK>, 5140 <&camcc CAM_CC_CCI_3_CLK>; 5141 clock-names = "camnoc_axi", 5142 "cpas_ahb", 5143 "cci"; 5144 5145 pinctrl-0 = <&cci3_0_default &cci3_1_default>; 5146 pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>; 5147 pinctrl-names = "default", "sleep"; 5148 5149 #address-cells = <1>; 5150 #size-cells = <0>; 5151 5152 status = "disabled"; 5153 5154 cci3_i2c0: i2c-bus@0 { 5155 reg = <0>; 5156 clock-frequency = <1000000>; 5157 #address-cells = <1>; 5158 #size-cells = <0>; 5159 }; 5160 5161 cci3_i2c1: i2c-bus@1 { 5162 reg = <1>; 5163 clock-frequency = <1000000>; 5164 #address-cells = <1>; 5165 #size-cells = <0>; 5166 }; 5167 }; 5168 5169 camss: isp@ac78000 { 5170 compatible = "qcom,sa8775p-camss"; 5171 5172 reg = <0x0 0xac78000 0x0 0x1000>, 5173 <0x0 0xac7a000 0x0 0x0f00>, 5174 <0x0 0xac7c000 0x0 0x0f00>, 5175 <0x0 0xac84000 0x0 0x0f00>, 5176 <0x0 0xac88000 0x0 0x0f00>, 5177 <0x0 0xac8c000 0x0 0x0f00>, 5178 <0x0 0xac90000 0x0 0x0f00>, 5179 <0x0 0xac94000 0x0 0x0f00>, 5180 <0x0 0xac9c000 0x0 0x2000>, 5181 <0x0 0xac9e000 0x0 0x2000>, 5182 <0x0 0xaca0000 0x0 0x2000>, 5183 <0x0 0xaca2000 0x0 0x2000>, 5184 <0x0 0xacac000 0x0 0x0400>, 5185 <0x0 0xacad000 0x0 0x0400>, 5186 <0x0 0xacae000 0x0 0x0400>, 5187 <0x0 0xac4d000 0x0 0xd000>, 5188 <0x0 0xac5a000 0x0 0xd000>, 5189 <0x0 0xac85000 0x0 0x0d00>, 5190 <0x0 0xac89000 0x0 0x0d00>, 5191 <0x0 0xac8d000 0x0 0x0d00>, 5192 <0x0 0xac91000 0x0 0x0d00>, 5193 <0x0 0xac95000 0x0 0x0d00>; 5194 reg-names = "csid_wrapper", 5195 "csid0", 5196 "csid1", 5197 "csid_lite0", 5198 "csid_lite1", 5199 "csid_lite2", 5200 "csid_lite3", 5201 "csid_lite4", 5202 "csiphy0", 5203 "csiphy1", 5204 "csiphy2", 5205 "csiphy3", 5206 "tpg0", 5207 "tpg1", 5208 "tpg2", 5209 "vfe0", 5210 "vfe1", 5211 "vfe_lite0", 5212 "vfe_lite1", 5213 "vfe_lite2", 5214 "vfe_lite3", 5215 "vfe_lite4"; 5216 5217 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5218 <&camcc CAM_CC_CORE_AHB_CLK>, 5219 <&camcc CAM_CC_CPAS_AHB_CLK>, 5220 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 5221 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 5222 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 5223 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 5224 <&camcc CAM_CC_CSID_CLK>, 5225 <&camcc CAM_CC_CSIPHY0_CLK>, 5226 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 5227 <&camcc CAM_CC_CSIPHY1_CLK>, 5228 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 5229 <&camcc CAM_CC_CSIPHY2_CLK>, 5230 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 5231 <&camcc CAM_CC_CSIPHY3_CLK>, 5232 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 5233 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 5234 <&gcc GCC_CAMERA_HF_AXI_CLK>, 5235 <&gcc GCC_CAMERA_SF_AXI_CLK>, 5236 <&camcc CAM_CC_ICP_AHB_CLK>, 5237 <&camcc CAM_CC_IFE_0_CLK>, 5238 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 5239 <&camcc CAM_CC_IFE_1_CLK>, 5240 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 5241 <&camcc CAM_CC_IFE_LITE_CLK>, 5242 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 5243 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 5244 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 5245 clock-names = "camnoc_axi", 5246 "core_ahb", 5247 "cpas_ahb", 5248 "cpas_fast_ahb_clk", 5249 "cpas_vfe_lite", 5250 "cpas_vfe0", 5251 "cpas_vfe1", 5252 "csid", 5253 "csiphy0", 5254 "csiphy0_timer", 5255 "csiphy1", 5256 "csiphy1_timer", 5257 "csiphy2", 5258 "csiphy2_timer", 5259 "csiphy3", 5260 "csiphy3_timer", 5261 "csiphy_rx", 5262 "gcc_axi_hf", 5263 "gcc_axi_sf", 5264 "icp_ahb", 5265 "vfe0", 5266 "vfe0_fast_ahb", 5267 "vfe1", 5268 "vfe1_fast_ahb", 5269 "vfe_lite", 5270 "vfe_lite_ahb", 5271 "vfe_lite_cphy_rx", 5272 "vfe_lite_csid"; 5273 5274 interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, 5275 <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, 5276 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 5277 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 5278 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 5279 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 5280 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 5281 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 5282 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 5283 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 5284 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 5285 <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, 5286 <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, 5287 <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, 5288 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 5289 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 5290 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 5291 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 5292 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 5293 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 5294 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; 5295 interrupt-names = "csid0", 5296 "csid1", 5297 "csid_lite0", 5298 "csid_lite1", 5299 "csid_lite2", 5300 "csid_lite3", 5301 "csid_lite4", 5302 "csiphy0", 5303 "csiphy1", 5304 "csiphy2", 5305 "csiphy3", 5306 "tpg0", 5307 "tpg1", 5308 "tpg2", 5309 "vfe0", 5310 "vfe1", 5311 "vfe_lite0", 5312 "vfe_lite1", 5313 "vfe_lite2", 5314 "vfe_lite3", 5315 "vfe_lite4"; 5316 5317 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5318 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5319 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 5320 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5321 interconnect-names = "ahb", 5322 "hf_0"; 5323 5324 iommus = <&apps_smmu 0x3400 0x20>; 5325 5326 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5327 power-domain-names = "top"; 5328 5329 status = "disabled"; 5330 5331 ports { 5332 #address-cells = <1>; 5333 #size-cells = <0>; 5334 5335 port@0 { 5336 reg = <0>; 5337 }; 5338 5339 port@1 { 5340 reg = <1>; 5341 }; 5342 5343 port@2 { 5344 reg = <2>; 5345 }; 5346 5347 port@3 { 5348 reg = <3>; 5349 }; 5350 }; 5351 }; 5352 5353 camcc: clock-controller@ade0000 { 5354 compatible = "qcom,sa8775p-camcc"; 5355 reg = <0x0 0x0ade0000 0x0 0x20000>; 5356 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5357 <&rpmhcc RPMH_CXO_CLK>, 5358 <&rpmhcc RPMH_CXO_CLK_A>, 5359 <&sleep_clk>; 5360 power-domains = <&rpmhpd SA8775P_MMCX>; 5361 #clock-cells = <1>; 5362 #reset-cells = <1>; 5363 #power-domain-cells = <1>; 5364 }; 5365 5366 mdss0: display-subsystem@ae00000 { 5367 compatible = "qcom,sa8775p-mdss"; 5368 reg = <0x0 0x0ae00000 0x0 0x1000>; 5369 reg-names = "mdss"; 5370 5371 /* same path used twice */ 5372 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 5373 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5374 <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS 5375 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5376 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5377 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5378 interconnect-names = "mdp0-mem", 5379 "mdp1-mem", 5380 "cpu-cfg"; 5381 5382 resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; 5383 5384 power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; 5385 5386 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5387 <&gcc GCC_DISP_HF_AXI_CLK>, 5388 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; 5389 5390 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 5391 interrupt-controller; 5392 #interrupt-cells = <1>; 5393 5394 iommus = <&apps_smmu 0x1000 0x402>; 5395 5396 #address-cells = <2>; 5397 #size-cells = <2>; 5398 ranges; 5399 5400 status = "disabled"; 5401 5402 mdss0_mdp: display-controller@ae01000 { 5403 compatible = "qcom,sa8775p-dpu"; 5404 reg = <0x0 0x0ae01000 0x0 0x8f000>, 5405 <0x0 0x0aeb0000 0x0 0x3000>; 5406 reg-names = "mdp", "vbif"; 5407 5408 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5409 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5410 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 5411 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, 5412 <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5413 clock-names = "nrt_bus", 5414 "iface", 5415 "lut", 5416 "core", 5417 "vsync"; 5418 5419 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5420 assigned-clock-rates = <19200000>; 5421 5422 operating-points-v2 = <&mdss0_mdp_opp_table>; 5423 power-domains = <&rpmhpd SA8775P_MMCX>; 5424 5425 interrupt-parent = <&mdss0>; 5426 interrupts = <0>; 5427 5428 ports { 5429 #address-cells = <1>; 5430 #size-cells = <0>; 5431 5432 port@0 { 5433 reg = <0>; 5434 5435 dpu_intf0_out: endpoint { 5436 remote-endpoint = <&mdss0_dp0_in>; 5437 }; 5438 }; 5439 5440 port@1 { 5441 reg = <1>; 5442 5443 dpu_intf4_out: endpoint { 5444 remote-endpoint = <&mdss0_dp1_in>; 5445 }; 5446 }; 5447 5448 port@2 { 5449 reg = <2>; 5450 5451 dpu_intf1_out: endpoint { 5452 remote-endpoint = <&mdss0_dsi0_in>; 5453 }; 5454 }; 5455 5456 port@3 { 5457 reg = <3>; 5458 5459 dpu_intf2_out: endpoint { 5460 remote-endpoint = <&mdss0_dsi1_in>; 5461 }; 5462 }; 5463 }; 5464 5465 mdss0_mdp_opp_table: opp-table { 5466 compatible = "operating-points-v2"; 5467 5468 opp-375000000 { 5469 opp-hz = /bits/ 64 <375000000>; 5470 required-opps = <&rpmhpd_opp_svs_l1>; 5471 }; 5472 5473 opp-500000000 { 5474 opp-hz = /bits/ 64 <500000000>; 5475 required-opps = <&rpmhpd_opp_nom>; 5476 }; 5477 5478 opp-575000000 { 5479 opp-hz = /bits/ 64 <575000000>; 5480 required-opps = <&rpmhpd_opp_turbo>; 5481 }; 5482 5483 opp-650000000 { 5484 opp-hz = /bits/ 64 <650000000>; 5485 required-opps = <&rpmhpd_opp_turbo_l1>; 5486 }; 5487 }; 5488 }; 5489 5490 mdss0_dsi0: dsi@ae94000 { 5491 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5492 reg = <0x0 0x0ae94000 0x0 0x400>; 5493 reg-names = "dsi_ctrl"; 5494 5495 interrupt-parent = <&mdss0>; 5496 interrupts = <4>; 5497 5498 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK>, 5499 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, 5500 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK>, 5501 <&dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK>, 5502 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5503 <&gcc GCC_DISP_HF_AXI_CLK>; 5504 clock-names = "byte", 5505 "byte_intf", 5506 "pixel", 5507 "core", 5508 "iface", 5509 "bus"; 5510 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, 5511 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; 5512 assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 5513 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; 5514 phys = <&mdss0_dsi0_phy>; 5515 5516 operating-points-v2 = <&mdss_dsi_opp_table>; 5517 power-domains = <&rpmhpd SA8775P_MMCX>; 5518 5519 refgen-supply = <&refgen>; 5520 5521 #address-cells = <1>; 5522 #size-cells = <0>; 5523 5524 status = "disabled"; 5525 5526 ports { 5527 #address-cells = <1>; 5528 #size-cells = <0>; 5529 5530 port@0 { 5531 reg = <0>; 5532 5533 mdss0_dsi0_in: endpoint { 5534 remote-endpoint = <&dpu_intf1_out>; 5535 }; 5536 }; 5537 5538 port@1 { 5539 reg = <1>; 5540 5541 mdss0_dsi0_out: endpoint { }; 5542 }; 5543 }; 5544 5545 mdss_dsi_opp_table: opp-table { 5546 compatible = "operating-points-v2"; 5547 5548 opp-358000000 { 5549 opp-hz = /bits/ 64 <358000000>; 5550 required-opps = <&rpmhpd_opp_svs_l1>; 5551 }; 5552 }; 5553 }; 5554 5555 mdss0_dsi0_phy: phy@ae94400 { 5556 compatible = "qcom,sa8775p-dsi-phy-5nm"; 5557 reg = <0x0 0x0ae94400 0x0 0x200>, 5558 <0x0 0x0ae94600 0x0 0x280>, 5559 <0x0 0x0ae94900 0x0 0x27c>; 5560 reg-names = "dsi_phy", 5561 "dsi_phy_lane", 5562 "dsi_pll"; 5563 5564 #clock-cells = <1>; 5565 #phy-cells = <0>; 5566 5567 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5568 <&rpmhcc RPMH_CXO_CLK>; 5569 clock-names = "iface", "ref"; 5570 5571 status = "disabled"; 5572 }; 5573 5574 mdss0_dsi1: dsi@ae96000 { 5575 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5576 reg = <0x0 0x0ae96000 0x0 0x400>; 5577 reg-names = "dsi_ctrl"; 5578 5579 interrupt-parent = <&mdss0>; 5580 interrupts = <5>; 5581 5582 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK>, 5583 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK>, 5584 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK>, 5585 <&dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK>, 5586 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5587 <&gcc GCC_DISP_HF_AXI_CLK>; 5588 clock-names = "byte", 5589 "byte_intf", 5590 "pixel", 5591 "core", 5592 "iface", 5593 "bus"; 5594 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>, 5595 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC>; 5596 assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5597 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5598 phys = <&mdss0_dsi1_phy>; 5599 5600 operating-points-v2 = <&mdss_dsi_opp_table>; 5601 power-domains = <&rpmhpd SA8775P_MMCX>; 5602 5603 refgen-supply = <&refgen>; 5604 5605 #address-cells = <1>; 5606 #size-cells = <0>; 5607 5608 status = "disabled"; 5609 5610 ports { 5611 #address-cells = <1>; 5612 #size-cells = <0>; 5613 5614 port@0 { 5615 reg = <0>; 5616 5617 mdss0_dsi1_in: endpoint { 5618 remote-endpoint = <&dpu_intf2_out>; 5619 }; 5620 }; 5621 5622 port@1 { 5623 reg = <1>; 5624 5625 mdss0_dsi1_out: endpoint { }; 5626 }; 5627 }; 5628 }; 5629 5630 mdss0_dsi1_phy: phy@ae96400 { 5631 compatible = "qcom,sa8775p-dsi-phy-5nm"; 5632 reg = <0x0 0x0ae96400 0x0 0x200>, 5633 <0x0 0x0ae96600 0x0 0x280>, 5634 <0x0 0x0ae96900 0x0 0x27c>; 5635 reg-names = "dsi_phy", 5636 "dsi_phy_lane", 5637 "dsi_pll"; 5638 5639 #clock-cells = <1>; 5640 #phy-cells = <0>; 5641 5642 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5643 <&rpmhcc RPMH_CXO_CLK>; 5644 clock-names = "iface", "ref"; 5645 5646 status = "disabled"; 5647 }; 5648 5649 mdss0_dp0_phy: phy@aec2a00 { 5650 compatible = "qcom,sa8775p-edp-phy"; 5651 5652 reg = <0x0 0x0aec2a00 0x0 0x200>, 5653 <0x0 0x0aec2200 0x0 0xd0>, 5654 <0x0 0x0aec2600 0x0 0xd0>, 5655 <0x0 0x0aec2000 0x0 0x1c8>; 5656 5657 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5658 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5659 <&gcc GCC_EDP_REF_CLKREF_EN>; 5660 clock-names = "aux", 5661 "cfg_ahb", 5662 "ref"; 5663 5664 #clock-cells = <1>; 5665 #phy-cells = <0>; 5666 5667 status = "disabled"; 5668 }; 5669 5670 mdss0_dp1_phy: phy@aec5a00 { 5671 compatible = "qcom,sa8775p-edp-phy"; 5672 5673 reg = <0x0 0x0aec5a00 0x0 0x200>, 5674 <0x0 0x0aec5200 0x0 0xd0>, 5675 <0x0 0x0aec5600 0x0 0xd0>, 5676 <0x0 0x0aec5000 0x0 0x1c8>; 5677 5678 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 5679 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5680 <&gcc GCC_EDP_REF_CLKREF_EN>; 5681 clock-names = "aux", 5682 "cfg_ahb", 5683 "ref"; 5684 5685 #clock-cells = <1>; 5686 #phy-cells = <0>; 5687 5688 status = "disabled"; 5689 }; 5690 5691 mdss0_dp0: displayport-controller@af54000 { 5692 compatible = "qcom,sa8775p-dp"; 5693 5694 reg = <0x0 0x0af54000 0x0 0x104>, 5695 <0x0 0x0af54200 0x0 0x0c0>, 5696 <0x0 0x0af55000 0x0 0x770>, 5697 <0x0 0x0af56000 0x0 0x09c>, 5698 <0x0 0x0af57000 0x0 0x09c>, 5699 <0x0 0x0af58000 0x0 0x09c>, 5700 <0x0 0x0af59000 0x0 0x09c>, 5701 <0x0 0x0af5a000 0x0 0x23c>, 5702 <0x0 0x0af5b000 0x0 0x23c>; 5703 5704 interrupt-parent = <&mdss0>; 5705 interrupts = <12>; 5706 5707 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5708 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5709 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 5710 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5711 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5712 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, 5713 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, 5714 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; 5715 clock-names = "core_iface", 5716 "core_aux", 5717 "ctrl_link", 5718 "ctrl_link_iface", 5719 "stream_pixel", 5720 "stream_1_pixel", 5721 "stream_2_pixel", 5722 "stream_3_pixel"; 5723 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5724 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5725 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, 5726 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, 5727 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; 5728 assigned-clock-parents = <&mdss0_dp0_phy 0>, 5729 <&mdss0_dp0_phy 1>, 5730 <&mdss0_dp0_phy 1>, 5731 <&mdss0_dp0_phy 1>, 5732 <&mdss0_dp0_phy 1>; 5733 phys = <&mdss0_dp0_phy>; 5734 phy-names = "dp"; 5735 5736 operating-points-v2 = <&dp_opp_table>; 5737 power-domains = <&rpmhpd SA8775P_MMCX>; 5738 5739 #sound-dai-cells = <0>; 5740 5741 status = "disabled"; 5742 5743 ports { 5744 #address-cells = <1>; 5745 #size-cells = <0>; 5746 5747 port@0 { 5748 reg = <0>; 5749 5750 mdss0_dp0_in: endpoint { 5751 remote-endpoint = <&dpu_intf0_out>; 5752 }; 5753 }; 5754 5755 port@1 { 5756 reg = <1>; 5757 5758 mdss0_dp0_out: endpoint { }; 5759 }; 5760 }; 5761 5762 dp_opp_table: opp-table { 5763 compatible = "operating-points-v2"; 5764 5765 opp-162000000 { 5766 opp-hz = /bits/ 64 <162000000>; 5767 required-opps = <&rpmhpd_opp_low_svs>; 5768 }; 5769 5770 opp-270000000 { 5771 opp-hz = /bits/ 64 <270000000>; 5772 required-opps = <&rpmhpd_opp_svs>; 5773 }; 5774 5775 opp-540000000 { 5776 opp-hz = /bits/ 64 <540000000>; 5777 required-opps = <&rpmhpd_opp_svs_l1>; 5778 }; 5779 5780 opp-810000000 { 5781 opp-hz = /bits/ 64 <810000000>; 5782 required-opps = <&rpmhpd_opp_nom>; 5783 }; 5784 }; 5785 }; 5786 5787 mdss0_dp1: displayport-controller@af5c000 { 5788 compatible = "qcom,sa8775p-dp"; 5789 5790 reg = <0x0 0x0af5c000 0x0 0x104>, 5791 <0x0 0x0af5c200 0x0 0x0c0>, 5792 <0x0 0x0af5d000 0x0 0x770>, 5793 <0x0 0x0af5e000 0x0 0x09c>, 5794 <0x0 0x0af5f000 0x0 0x09c>, 5795 <0x0 0x0af60000 0x0 0x09c>, 5796 <0x0 0x0af61000 0x0 0x09c>, 5797 <0x0 0x0af62000 0x0 0x23c>, 5798 <0x0 0x0af63000 0x0 0x23c>; 5799 5800 interrupt-parent = <&mdss0>; 5801 interrupts = <13>; 5802 5803 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5804 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 5805 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, 5806 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5807 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5808 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5809 clock-names = "core_iface", 5810 "core_aux", 5811 "ctrl_link", 5812 "ctrl_link_iface", 5813 "stream_pixel", 5814 "stream_1_pixel"; 5815 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5816 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5817 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5818 assigned-clock-parents = <&mdss0_dp1_phy 0>, 5819 <&mdss0_dp1_phy 1>, 5820 <&mdss0_dp1_phy 1>; 5821 phys = <&mdss0_dp1_phy>; 5822 phy-names = "dp"; 5823 5824 operating-points-v2 = <&dp_opp_table>; 5825 power-domains = <&rpmhpd SA8775P_MMCX>; 5826 5827 #sound-dai-cells = <0>; 5828 5829 status = "disabled"; 5830 5831 ports { 5832 #address-cells = <1>; 5833 #size-cells = <0>; 5834 5835 port@0 { 5836 reg = <0>; 5837 5838 mdss0_dp1_in: endpoint { 5839 remote-endpoint = <&dpu_intf4_out>; 5840 }; 5841 }; 5842 5843 port@1 { 5844 reg = <1>; 5845 5846 mdss0_dp1_out: endpoint { }; 5847 }; 5848 }; 5849 }; 5850 }; 5851 5852 dispcc0: clock-controller@af00000 { 5853 compatible = "qcom,sa8775p-dispcc0"; 5854 reg = <0x0 0x0af00000 0x0 0x20000>; 5855 clocks = <&gcc GCC_DISP_AHB_CLK>, 5856 <&rpmhcc RPMH_CXO_CLK>, 5857 <&rpmhcc RPMH_CXO_CLK_A>, 5858 <&sleep_clk>, 5859 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, 5860 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>, 5861 <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 5862 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, 5863 <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5864 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5865 power-domains = <&rpmhpd SA8775P_MMCX>; 5866 #clock-cells = <1>; 5867 #reset-cells = <1>; 5868 #power-domain-cells = <1>; 5869 }; 5870 5871 pdc: interrupt-controller@b220000 { 5872 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 5873 reg = <0x0 0x0b220000 0x0 0x10000>, 5874 <0x0 0x17c000f0 0x0 0x64>; 5875 qcom,pdc-ranges = <0 480 40>, 5876 <40 140 14>, 5877 <54 263 1>, 5878 <55 306 4>, 5879 <59 312 3>, 5880 <62 374 2>, 5881 <64 434 2>, 5882 <66 438 2>, 5883 <70 520 1>, 5884 <73 523 1>, 5885 <118 568 6>, 5886 <124 609 3>, 5887 <159 638 1>, 5888 <160 720 3>, 5889 <169 728 30>, 5890 <199 416 2>, 5891 <201 449 1>, 5892 <202 89 1>, 5893 <203 451 1>, 5894 <204 462 1>, 5895 <205 264 1>, 5896 <206 579 1>, 5897 <207 653 1>, 5898 <208 656 1>, 5899 <209 659 1>, 5900 <210 122 1>, 5901 <211 699 1>, 5902 <212 705 1>, 5903 <213 450 1>, 5904 <214 643 2>, 5905 <216 646 5>, 5906 <221 390 5>, 5907 <226 700 2>, 5908 <228 440 1>, 5909 <229 663 1>, 5910 <230 524 2>, 5911 <232 612 3>, 5912 <235 723 5>; 5913 #interrupt-cells = <2>; 5914 interrupt-parent = <&intc>; 5915 interrupt-controller; 5916 }; 5917 5918 tsens2: thermal-sensor@c251000 { 5919 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5920 reg = <0x0 0x0c251000 0x0 0x1ff>, 5921 <0x0 0x0c224000 0x0 0x8>; 5922 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 5923 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 5924 #qcom,sensors = <13>; 5925 interrupt-names = "uplow", "critical"; 5926 #thermal-sensor-cells = <1>; 5927 }; 5928 5929 tsens3: thermal-sensor@c252000 { 5930 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5931 reg = <0x0 0x0c252000 0x0 0x1ff>, 5932 <0x0 0x0c225000 0x0 0x8>; 5933 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 5934 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 5935 #qcom,sensors = <13>; 5936 interrupt-names = "uplow", "critical"; 5937 #thermal-sensor-cells = <1>; 5938 }; 5939 5940 tsens0: thermal-sensor@c263000 { 5941 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5942 reg = <0x0 0x0c263000 0x0 0x1ff>, 5943 <0x0 0x0c222000 0x0 0x8>; 5944 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5945 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5946 #qcom,sensors = <12>; 5947 interrupt-names = "uplow", "critical"; 5948 #thermal-sensor-cells = <1>; 5949 }; 5950 5951 tsens1: thermal-sensor@c265000 { 5952 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5953 reg = <0x0 0x0c265000 0x0 0x1ff>, 5954 <0x0 0x0c223000 0x0 0x8>; 5955 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5956 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5957 #qcom,sensors = <12>; 5958 interrupt-names = "uplow", "critical"; 5959 #thermal-sensor-cells = <1>; 5960 }; 5961 5962 aoss_qmp: power-management@c300000 { 5963 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 5964 reg = <0x0 0x0c300000 0x0 0x400>; 5965 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5966 IPCC_MPROC_SIGNAL_GLINK_QMP 5967 IRQ_TYPE_EDGE_RISING>; 5968 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5969 #clock-cells = <0>; 5970 }; 5971 5972 sram@c3f0000 { 5973 compatible = "qcom,rpmh-stats"; 5974 reg = <0x0 0x0c3f0000 0x0 0x400>; 5975 }; 5976 5977 spmi_bus: spmi@c440000 { 5978 compatible = "qcom,spmi-pmic-arb"; 5979 reg = <0x0 0x0c440000 0x0 0x1100>, 5980 <0x0 0x0c600000 0x0 0x2000000>, 5981 <0x0 0x0e600000 0x0 0x100000>, 5982 <0x0 0x0e700000 0x0 0xa0000>, 5983 <0x0 0x0c40a000 0x0 0x26000>; 5984 reg-names = "core", 5985 "chnls", 5986 "obsrvr", 5987 "intr", 5988 "cnfg"; 5989 qcom,channel = <0>; 5990 qcom,ee = <0>; 5991 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5992 interrupt-names = "periph_irq"; 5993 interrupt-controller; 5994 #interrupt-cells = <4>; 5995 #address-cells = <2>; 5996 #size-cells = <0>; 5997 }; 5998 5999 tlmm: pinctrl@f000000 { 6000 compatible = "qcom,sa8775p-tlmm"; 6001 reg = <0x0 0x0f000000 0x0 0x1000000>; 6002 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 6003 gpio-controller; 6004 #gpio-cells = <2>; 6005 interrupt-controller; 6006 #interrupt-cells = <2>; 6007 gpio-ranges = <&tlmm 0 0 149>; 6008 wakeup-parent = <&pdc>; 6009 6010 dp0_hot_plug_det: dp0-hot-plug-det-state { 6011 pins = "gpio101"; 6012 function = "edp0_hot"; 6013 bias-disable; 6014 }; 6015 6016 dp1_hot_plug_det: dp1-hot-plug-det-state { 6017 pins = "gpio102"; 6018 function = "edp1_hot"; 6019 bias-disable; 6020 }; 6021 6022 hs0_mi2s_active: hs0-mi2s-active-state { 6023 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 6024 function = "hs0_mi2s"; 6025 drive-strength = <8>; 6026 bias-disable; 6027 }; 6028 6029 hs2_mi2s_active: hs2-mi2s-active-state { 6030 pins = "gpio122", "gpio123", "gpio124", "gpio125"; 6031 function = "hs2_mi2s"; 6032 drive-strength = <8>; 6033 bias-disable; 6034 }; 6035 6036 cci0_0_default: cci0-0-default-state { 6037 pins = "gpio60", "gpio61"; 6038 function = "cci_i2c"; 6039 drive-strength = <2>; 6040 bias-pull-up = <2200>; 6041 }; 6042 6043 cci0_0_sleep: cci0-0-sleep-state { 6044 pins = "gpio60", "gpio61"; 6045 function = "cci_i2c"; 6046 drive-strength = <2>; 6047 bias-pull-down; 6048 }; 6049 6050 cci0_1_default: cci0-1-default-state { 6051 pins = "gpio52", "gpio53"; 6052 function = "cci_i2c"; 6053 drive-strength = <2>; 6054 bias-pull-up = <2200>; 6055 }; 6056 6057 cci0_1_sleep: cci0-1-sleep-state { 6058 pins = "gpio52", "gpio53"; 6059 function = "cci_i2c"; 6060 drive-strength = <2>; 6061 bias-pull-down; 6062 }; 6063 6064 cci1_0_default: cci1-0-default-state { 6065 pins = "gpio62", "gpio63"; 6066 function = "cci_i2c"; 6067 drive-strength = <2>; 6068 bias-pull-up = <2200>; 6069 }; 6070 6071 cci1_0_sleep: cci1-0-sleep-state { 6072 pins = "gpio62", "gpio63"; 6073 function = "cci_i2c"; 6074 drive-strength = <2>; 6075 bias-pull-down; 6076 }; 6077 6078 cci1_1_default: cci1-1-default-state { 6079 pins = "gpio54", "gpio55"; 6080 function = "cci_i2c"; 6081 drive-strength = <2>; 6082 bias-pull-up = <2200>; 6083 }; 6084 6085 cci1_1_sleep: cci1-1-sleep-state { 6086 pins = "gpio54", "gpio55"; 6087 function = "cci_i2c"; 6088 drive-strength = <2>; 6089 bias-pull-down; 6090 }; 6091 6092 cci2_0_default: cci2-0-default-state { 6093 pins = "gpio64", "gpio65"; 6094 function = "cci_i2c"; 6095 drive-strength = <2>; 6096 bias-pull-up = <2200>; 6097 }; 6098 6099 cci2_0_sleep: cci2-0-sleep-state { 6100 pins = "gpio64", "gpio65"; 6101 function = "cci_i2c"; 6102 drive-strength = <2>; 6103 bias-pull-down; 6104 }; 6105 6106 cci2_1_default: cci2-1-default-state { 6107 pins = "gpio56", "gpio57"; 6108 function = "cci_i2c"; 6109 drive-strength = <2>; 6110 bias-pull-up = <2200>; 6111 }; 6112 6113 cci2_1_sleep: cci2-1-sleep-state { 6114 pins = "gpio56", "gpio57"; 6115 function = "cci_i2c"; 6116 drive-strength = <2>; 6117 bias-pull-down; 6118 }; 6119 6120 cci3_0_default: cci3-0-default-state { 6121 pins = "gpio66", "gpio67"; 6122 function = "cci_i2c"; 6123 drive-strength = <2>; 6124 bias-pull-up = <2200>; 6125 }; 6126 6127 cci3_0_sleep: cci3-0-sleep-state { 6128 pins = "gpio66", "gpio67"; 6129 function = "cci_i2c"; 6130 drive-strength = <2>; 6131 bias-pull-down; 6132 }; 6133 6134 cci3_1_default: cci3-1-default-state { 6135 pins = "gpio58", "gpio59"; 6136 function = "cci_i2c"; 6137 drive-strength = <2>; 6138 bias-pull-up = <2200>; 6139 }; 6140 6141 cci3_1_sleep: cci3-1-sleep-state { 6142 pins = "gpio58", "gpio59"; 6143 function = "cci_i2c"; 6144 drive-strength = <2>; 6145 bias-pull-down; 6146 }; 6147 6148 qup_i2c0_default: qup-i2c0-state { 6149 pins = "gpio20", "gpio21"; 6150 function = "qup0_se0"; 6151 }; 6152 6153 qup_i2c1_default: qup-i2c1-state { 6154 pins = "gpio24", "gpio25"; 6155 function = "qup0_se1"; 6156 }; 6157 6158 qup_i2c2_default: qup-i2c2-state { 6159 pins = "gpio36", "gpio37"; 6160 function = "qup0_se2"; 6161 }; 6162 6163 qup_i2c3_default: qup-i2c3-state { 6164 pins = "gpio28", "gpio29"; 6165 function = "qup0_se3"; 6166 }; 6167 6168 qup_i2c4_default: qup-i2c4-state { 6169 pins = "gpio32", "gpio33"; 6170 function = "qup0_se4"; 6171 }; 6172 6173 qup_i2c5_default: qup-i2c5-state { 6174 pins = "gpio36", "gpio37"; 6175 function = "qup0_se5"; 6176 }; 6177 6178 qup_i2c7_default: qup-i2c7-state { 6179 pins = "gpio40", "gpio41"; 6180 function = "qup1_se0"; 6181 }; 6182 6183 qup_i2c8_default: qup-i2c8-state { 6184 pins = "gpio42", "gpio43"; 6185 function = "qup1_se1"; 6186 }; 6187 6188 qup_i2c9_default: qup-i2c9-state { 6189 pins = "gpio46", "gpio47"; 6190 function = "qup1_se2"; 6191 }; 6192 6193 qup_i2c10_default: qup-i2c10-state { 6194 pins = "gpio44", "gpio45"; 6195 function = "qup1_se3"; 6196 }; 6197 6198 qup_i2c11_default: qup-i2c11-state { 6199 pins = "gpio48", "gpio49"; 6200 function = "qup1_se4"; 6201 }; 6202 6203 qup_i2c12_default: qup-i2c12-state { 6204 pins = "gpio52", "gpio53"; 6205 function = "qup1_se5"; 6206 }; 6207 6208 qup_i2c13_default: qup-i2c13-state { 6209 pins = "gpio56", "gpio57"; 6210 function = "qup1_se6"; 6211 }; 6212 6213 qup_i2c14_default: qup-i2c14-state { 6214 pins = "gpio80", "gpio81"; 6215 function = "qup2_se0"; 6216 }; 6217 6218 qup_i2c15_default: qup-i2c15-state { 6219 pins = "gpio84", "gpio85"; 6220 function = "qup2_se1"; 6221 }; 6222 6223 qup_i2c16_default: qup-i2c16-state { 6224 pins = "gpio86", "gpio87"; 6225 function = "qup2_se2"; 6226 }; 6227 6228 qup_i2c17_default: qup-i2c17-state { 6229 pins = "gpio91", "gpio92"; 6230 function = "qup2_se3"; 6231 }; 6232 6233 qup_i2c18_default: qup-i2c18-state { 6234 pins = "gpio95", "gpio96"; 6235 function = "qup2_se4"; 6236 }; 6237 6238 qup_i2c19_default: qup-i2c19-state { 6239 pins = "gpio99", "gpio100"; 6240 function = "qup2_se5"; 6241 }; 6242 6243 qup_i2c20_default: qup-i2c20-state { 6244 pins = "gpio97", "gpio98"; 6245 function = "qup2_se6"; 6246 }; 6247 6248 qup_i2c21_default: qup-i2c21-state { 6249 pins = "gpio13", "gpio14"; 6250 function = "qup3_se0"; 6251 }; 6252 6253 qup_spi0_default: qup-spi0-state { 6254 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 6255 function = "qup0_se0"; 6256 }; 6257 6258 qup_spi1_default: qup-spi1-state { 6259 pins = "gpio24", "gpio25", "gpio26", "gpio27"; 6260 function = "qup0_se1"; 6261 }; 6262 6263 qup_spi2_default: qup-spi2-state { 6264 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 6265 function = "qup0_se2"; 6266 }; 6267 6268 qup_spi3_default: qup-spi3-state { 6269 pins = "gpio28", "gpio29", "gpio30", "gpio31"; 6270 function = "qup0_se3"; 6271 }; 6272 6273 qup_spi4_default: qup-spi4-state { 6274 pins = "gpio32", "gpio33", "gpio34", "gpio35"; 6275 function = "qup0_se4"; 6276 }; 6277 6278 qup_spi5_default: qup-spi5-state { 6279 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 6280 function = "qup0_se5"; 6281 }; 6282 6283 qup_spi7_default: qup-spi7-state { 6284 pins = "gpio40", "gpio41", "gpio42", "gpio43"; 6285 function = "qup1_se0"; 6286 }; 6287 6288 qup_spi8_default: qup-spi8-state { 6289 pins = "gpio42", "gpio43", "gpio40", "gpio41"; 6290 function = "qup1_se1"; 6291 }; 6292 6293 qup_spi9_default: qup-spi9-state { 6294 pins = "gpio46", "gpio47", "gpio44", "gpio45"; 6295 function = "qup1_se2"; 6296 }; 6297 6298 qup_spi10_default: qup-spi10-state { 6299 pins = "gpio44", "gpio45", "gpio46", "gpio47"; 6300 function = "qup1_se3"; 6301 }; 6302 6303 qup_spi11_default: qup-spi11-state { 6304 pins = "gpio48", "gpio49", "gpio50", "gpio51"; 6305 function = "qup1_se4"; 6306 }; 6307 6308 qup_spi12_default: qup-spi12-state { 6309 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 6310 function = "qup1_se5"; 6311 }; 6312 6313 qup_spi14_default: qup-spi14-state { 6314 pins = "gpio80", "gpio81", "gpio82", "gpio83"; 6315 function = "qup2_se0"; 6316 }; 6317 6318 qup_spi15_default: qup-spi15-state { 6319 pins = "gpio84", "gpio85", "gpio99", "gpio100"; 6320 function = "qup2_se1"; 6321 }; 6322 6323 qup_spi16_default: qup-spi16-state { 6324 pins = "gpio86", "gpio87", "gpio88", "gpio89"; 6325 function = "qup2_se2"; 6326 }; 6327 6328 qup_spi17_default: qup-spi17-state { 6329 pins = "gpio91", "gpio92", "gpio93", "gpio94"; 6330 function = "qup2_se3"; 6331 }; 6332 6333 qup_spi18_default: qup-spi18-state { 6334 pins = "gpio95", "gpio96", "gpio97", "gpio98"; 6335 function = "qup2_se4"; 6336 }; 6337 6338 qup_spi19_default: qup-spi19-state { 6339 pins = "gpio99", "gpio100", "gpio84", "gpio85"; 6340 function = "qup2_se5"; 6341 }; 6342 6343 qup_spi20_default: qup-spi20-state { 6344 pins = "gpio97", "gpio98", "gpio95", "gpio96"; 6345 function = "qup2_se6"; 6346 }; 6347 6348 qup_spi21_default: qup-spi21-state { 6349 pins = "gpio13", "gpio14", "gpio15", "gpio16"; 6350 function = "qup3_se0"; 6351 }; 6352 6353 qup_uart0_default: qup-uart0-state { 6354 qup_uart0_cts: qup-uart0-cts-pins { 6355 pins = "gpio20"; 6356 function = "qup0_se0"; 6357 }; 6358 6359 qup_uart0_rts: qup-uart0-rts-pins { 6360 pins = "gpio21"; 6361 function = "qup0_se0"; 6362 }; 6363 6364 qup_uart0_tx: qup-uart0-tx-pins { 6365 pins = "gpio22"; 6366 function = "qup0_se0"; 6367 }; 6368 6369 qup_uart0_rx: qup-uart0-rx-pins { 6370 pins = "gpio23"; 6371 function = "qup0_se0"; 6372 }; 6373 }; 6374 6375 qup_uart1_default: qup-uart1-state { 6376 qup_uart1_cts: qup-uart1-cts-pins { 6377 pins = "gpio24"; 6378 function = "qup0_se1"; 6379 }; 6380 6381 qup_uart1_rts: qup-uart1-rts-pins { 6382 pins = "gpio25"; 6383 function = "qup0_se1"; 6384 }; 6385 6386 qup_uart1_tx: qup-uart1-tx-pins { 6387 pins = "gpio26"; 6388 function = "qup0_se1"; 6389 }; 6390 6391 qup_uart1_rx: qup-uart1-rx-pins { 6392 pins = "gpio27"; 6393 function = "qup0_se1"; 6394 }; 6395 }; 6396 6397 qup_uart2_default: qup-uart2-state { 6398 qup_uart2_cts: qup-uart2-cts-pins { 6399 pins = "gpio36"; 6400 function = "qup0_se2"; 6401 }; 6402 6403 qup_uart2_rts: qup-uart2-rts-pins { 6404 pins = "gpio37"; 6405 function = "qup0_se2"; 6406 }; 6407 6408 qup_uart2_tx: qup-uart2-tx-pins { 6409 pins = "gpio38"; 6410 function = "qup0_se2"; 6411 }; 6412 6413 qup_uart2_rx: qup-uart2-rx-pins { 6414 pins = "gpio39"; 6415 function = "qup0_se2"; 6416 }; 6417 }; 6418 6419 qup_uart3_default: qup-uart3-state { 6420 qup_uart3_cts: qup-uart3-cts-pins { 6421 pins = "gpio28"; 6422 function = "qup0_se3"; 6423 }; 6424 6425 qup_uart3_rts: qup-uart3-rts-pins { 6426 pins = "gpio29"; 6427 function = "qup0_se3"; 6428 }; 6429 6430 qup_uart3_tx: qup-uart3-tx-pins { 6431 pins = "gpio30"; 6432 function = "qup0_se3"; 6433 }; 6434 6435 qup_uart3_rx: qup-uart3-rx-pins { 6436 pins = "gpio31"; 6437 function = "qup0_se3"; 6438 }; 6439 }; 6440 6441 qup_uart4_default: qup-uart4-state { 6442 qup_uart4_cts: qup-uart4-cts-pins { 6443 pins = "gpio32"; 6444 function = "qup0_se4"; 6445 }; 6446 6447 qup_uart4_rts: qup-uart4-rts-pins { 6448 pins = "gpio33"; 6449 function = "qup0_se4"; 6450 }; 6451 6452 qup_uart4_tx: qup-uart4-tx-pins { 6453 pins = "gpio34"; 6454 function = "qup0_se4"; 6455 }; 6456 6457 qup_uart4_rx: qup-uart4-rx-pins { 6458 pins = "gpio35"; 6459 function = "qup0_se4"; 6460 }; 6461 }; 6462 6463 qup_uart5_default: qup-uart5-state { 6464 qup_uart5_cts: qup-uart5-cts-pins { 6465 pins = "gpio36"; 6466 function = "qup0_se5"; 6467 }; 6468 6469 qup_uart5_rts: qup-uart5-rts-pins { 6470 pins = "gpio37"; 6471 function = "qup0_se5"; 6472 }; 6473 6474 qup_uart5_tx: qup-uart5-tx-pins { 6475 pins = "gpio38"; 6476 function = "qup0_se5"; 6477 }; 6478 6479 qup_uart5_rx: qup-uart5-rx-pins { 6480 pins = "gpio39"; 6481 function = "qup0_se5"; 6482 }; 6483 }; 6484 6485 qup_uart7_default: qup-uart7-state { 6486 qup_uart7_cts: qup-uart7-cts-pins { 6487 pins = "gpio40"; 6488 function = "qup1_se0"; 6489 }; 6490 6491 qup_uart7_rts: qup-uart7-rts-pins { 6492 pins = "gpio41"; 6493 function = "qup1_se0"; 6494 }; 6495 6496 qup_uart7_tx: qup-uart7-tx-pins { 6497 pins = "gpio42"; 6498 function = "qup1_se0"; 6499 }; 6500 6501 qup_uart7_rx: qup-uart7-rx-pins { 6502 pins = "gpio43"; 6503 function = "qup1_se0"; 6504 }; 6505 }; 6506 6507 qup_uart8_default: qup-uart8-state { 6508 qup_uart8_cts: qup-uart8-cts-pins { 6509 pins = "gpio42"; 6510 function = "qup1_se1"; 6511 }; 6512 6513 qup_uart8_rts: qup-uart8-rts-pins { 6514 pins = "gpio43"; 6515 function = "qup1_se1"; 6516 }; 6517 6518 qup_uart8_tx: qup-uart8-tx-pins { 6519 pins = "gpio40"; 6520 function = "qup1_se1"; 6521 }; 6522 6523 qup_uart8_rx: qup-uart8-rx-pins { 6524 pins = "gpio41"; 6525 function = "qup1_se1"; 6526 }; 6527 }; 6528 6529 qup_uart9_default: qup-uart9-state { 6530 qup_uart9_cts: qup-uart9-cts-pins { 6531 pins = "gpio46"; 6532 function = "qup1_se2"; 6533 }; 6534 6535 qup_uart9_rts: qup-uart9-rts-pins { 6536 pins = "gpio47"; 6537 function = "qup1_se2"; 6538 }; 6539 6540 qup_uart9_tx: qup-uart9-tx-pins { 6541 pins = "gpio44"; 6542 function = "qup1_se2"; 6543 }; 6544 6545 qup_uart9_rx: qup-uart9-rx-pins { 6546 pins = "gpio45"; 6547 function = "qup1_se2"; 6548 }; 6549 }; 6550 6551 qup_uart10_default: qup-uart10-state { 6552 pins = "gpio46", "gpio47"; 6553 function = "qup1_se3"; 6554 }; 6555 6556 qup_uart11_default: qup-uart11-state { 6557 qup_uart11_cts: qup-uart11-cts-pins { 6558 pins = "gpio48"; 6559 function = "qup1_se4"; 6560 }; 6561 6562 qup_uart11_rts: qup-uart11-rts-pins { 6563 pins = "gpio49"; 6564 function = "qup1_se4"; 6565 }; 6566 6567 qup_uart11_tx: qup-uart11-tx-pins { 6568 pins = "gpio50"; 6569 function = "qup1_se4"; 6570 }; 6571 6572 qup_uart11_rx: qup-uart11-rx-pins { 6573 pins = "gpio51"; 6574 function = "qup1_se4"; 6575 }; 6576 }; 6577 6578 qup_uart12_default: qup-uart12-state { 6579 qup_uart12_cts: qup-uart12-cts-pins { 6580 pins = "gpio52"; 6581 function = "qup1_se5"; 6582 }; 6583 6584 qup_uart12_rts: qup-uart12-rts-pins { 6585 pins = "gpio53"; 6586 function = "qup1_se5"; 6587 }; 6588 6589 qup_uart12_tx: qup-uart12-tx-pins { 6590 pins = "gpio54"; 6591 function = "qup1_se5"; 6592 }; 6593 6594 qup_uart12_rx: qup-uart12-rx-pins { 6595 pins = "gpio55"; 6596 function = "qup1_se5"; 6597 }; 6598 }; 6599 6600 qup_uart14_default: qup-uart14-state { 6601 qup_uart14_cts: qup-uart14-cts-pins { 6602 pins = "gpio80"; 6603 function = "qup2_se0"; 6604 }; 6605 6606 qup_uart14_rts: qup-uart14-rts-pins { 6607 pins = "gpio81"; 6608 function = "qup2_se0"; 6609 }; 6610 6611 qup_uart14_tx: qup-uart14-tx-pins { 6612 pins = "gpio82"; 6613 function = "qup2_se0"; 6614 }; 6615 6616 qup_uart14_rx: qup-uart14-rx-pins { 6617 pins = "gpio83"; 6618 function = "qup2_se0"; 6619 }; 6620 }; 6621 6622 qup_uart15_default: qup-uart15-state { 6623 qup_uart15_cts: qup-uart15-cts-pins { 6624 pins = "gpio84"; 6625 function = "qup2_se1"; 6626 }; 6627 6628 qup_uart15_rts: qup-uart15-rts-pins { 6629 pins = "gpio85"; 6630 function = "qup2_se1"; 6631 }; 6632 6633 qup_uart15_tx: qup-uart15-tx-pins { 6634 pins = "gpio99"; 6635 function = "qup2_se1"; 6636 }; 6637 6638 qup_uart15_rx: qup-uart15-rx-pins { 6639 pins = "gpio100"; 6640 function = "qup2_se1"; 6641 }; 6642 }; 6643 6644 qup_uart16_default: qup-uart16-state { 6645 qup_uart16_cts: qup-uart16-cts-pins { 6646 pins = "gpio86"; 6647 function = "qup2_se2"; 6648 }; 6649 6650 qup_uart16_rts: qup-uart16-rts-pins { 6651 pins = "gpio87"; 6652 function = "qup2_se2"; 6653 }; 6654 6655 qup_uart16_tx: qup-uart16-tx-pins { 6656 pins = "gpio88"; 6657 function = "qup2_se2"; 6658 }; 6659 6660 qup_uart16_rx: qup-uart16-rx-pins { 6661 pins = "gpio89"; 6662 function = "qup2_se2"; 6663 }; 6664 }; 6665 6666 qup_uart17_default: qup-uart17-state { 6667 qup_uart17_cts: qup-uart17-cts-pins { 6668 pins = "gpio91"; 6669 function = "qup2_se3"; 6670 }; 6671 6672 qup_uart17_rts: qup0-uart17-rts-pins { 6673 pins = "gpio92"; 6674 function = "qup2_se3"; 6675 }; 6676 6677 qup_uart17_tx: qup0-uart17-tx-pins { 6678 pins = "gpio93"; 6679 function = "qup2_se3"; 6680 }; 6681 6682 qup_uart17_rx: qup0-uart17-rx-pins { 6683 pins = "gpio94"; 6684 function = "qup2_se3"; 6685 }; 6686 }; 6687 6688 qup_uart18_default: qup-uart18-state { 6689 qup_uart18_cts: qup-uart18-cts-pins { 6690 pins = "gpio95"; 6691 function = "qup2_se4"; 6692 }; 6693 6694 qup_uart18_rts: qup-uart18-rts-pins { 6695 pins = "gpio96"; 6696 function = "qup2_se4"; 6697 }; 6698 6699 qup_uart18_tx: qup-uart18-tx-pins { 6700 pins = "gpio97"; 6701 function = "qup2_se4"; 6702 }; 6703 6704 qup_uart18_rx: qup-uart18-rx-pins { 6705 pins = "gpio98"; 6706 function = "qup2_se4"; 6707 }; 6708 }; 6709 6710 qup_uart19_default: qup-uart19-state { 6711 qup_uart19_cts: qup-uart19-cts-pins { 6712 pins = "gpio99"; 6713 function = "qup2_se5"; 6714 }; 6715 6716 qup_uart19_rts: qup-uart19-rts-pins { 6717 pins = "gpio100"; 6718 function = "qup2_se5"; 6719 }; 6720 6721 qup_uart19_tx: qup-uart19-tx-pins { 6722 pins = "gpio84"; 6723 function = "qup2_se5"; 6724 }; 6725 6726 qup_uart19_rx: qup-uart19-rx-pins { 6727 pins = "gpio85"; 6728 function = "qup2_se5"; 6729 }; 6730 }; 6731 6732 qup_uart20_default: qup-uart20-state { 6733 qup_uart20_cts: qup-uart20-cts-pins { 6734 pins = "gpio97"; 6735 function = "qup2_se6"; 6736 }; 6737 6738 qup_uart20_rts: qup-uart20-rts-pins { 6739 pins = "gpio98"; 6740 function = "qup2_se6"; 6741 }; 6742 6743 qup_uart20_tx: qup-uart20-tx-pins { 6744 pins = "gpio95"; 6745 function = "qup2_se6"; 6746 }; 6747 6748 qup_uart20_rx: qup-uart20-rx-pins { 6749 pins = "gpio96"; 6750 function = "qup2_se6"; 6751 }; 6752 }; 6753 6754 qup_uart21_default: qup-uart21-state { 6755 qup_uart21_cts: qup-uart21-cts-pins { 6756 pins = "gpio13"; 6757 function = "qup3_se0"; 6758 }; 6759 6760 qup_uart21_rts: qup-uart21-rts-pins { 6761 pins = "gpio14"; 6762 function = "qup3_se0"; 6763 }; 6764 6765 qup_uart21_tx: qup-uart21-tx-pins { 6766 pins = "gpio15"; 6767 function = "qup3_se0"; 6768 }; 6769 6770 qup_uart21_rx: qup-uart21-rx-pins { 6771 pins = "gpio16"; 6772 function = "qup3_se0"; 6773 }; 6774 }; 6775 6776 sdc_default: sdc-default-state { 6777 clk-pins { 6778 pins = "sdc1_clk"; 6779 drive-strength = <16>; 6780 bias-disable; 6781 }; 6782 6783 cmd-pins { 6784 pins = "sdc1_cmd"; 6785 drive-strength = <10>; 6786 bias-pull-up; 6787 }; 6788 6789 data-pins { 6790 pins = "sdc1_data"; 6791 drive-strength = <10>; 6792 bias-pull-up; 6793 }; 6794 }; 6795 6796 sdc_sleep: sdc-sleep-state { 6797 clk-pins { 6798 pins = "sdc1_clk"; 6799 drive-strength = <2>; 6800 bias-bus-hold; 6801 }; 6802 6803 cmd-pins { 6804 pins = "sdc1_cmd"; 6805 drive-strength = <2>; 6806 bias-bus-hold; 6807 }; 6808 6809 data-pins { 6810 pins = "sdc1_data"; 6811 drive-strength = <2>; 6812 bias-bus-hold; 6813 }; 6814 }; 6815 }; 6816 6817 sram: sram@146d8000 { 6818 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; 6819 reg = <0x0 0x146d8000 0x0 0x1000>; 6820 ranges = <0x0 0x0 0x146d8000 0x1000>; 6821 6822 #address-cells = <1>; 6823 #size-cells = <1>; 6824 6825 minidump_config: minidump-sram@1c { 6826 reg = <0x1c 0x4>; 6827 }; 6828 6829 pil-reloc@94c { 6830 compatible = "qcom,pil-reloc-info"; 6831 reg = <0x94c 0xc8>; 6832 }; 6833 }; 6834 6835 apps_smmu: iommu@15000000 { 6836 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6837 reg = <0x0 0x15000000 0x0 0x100000>; 6838 #iommu-cells = <2>; 6839 #global-interrupts = <2>; 6840 dma-coherent; 6841 6842 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 6843 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 6844 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6845 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6846 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6847 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6848 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6849 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6850 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6851 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6852 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6853 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6854 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6855 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6856 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6857 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6858 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6859 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6860 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6861 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6862 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6863 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6864 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6865 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6866 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6867 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6868 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6869 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6870 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6871 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6872 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6873 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6874 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6875 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6876 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6877 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6878 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6879 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6880 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6881 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6882 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6883 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6884 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6885 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6886 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6887 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6888 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6889 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6890 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6891 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6892 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6893 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6894 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6895 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6896 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6897 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6898 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6899 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6900 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6901 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6902 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6903 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6904 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6905 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6906 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6907 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6908 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6909 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6910 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6911 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6912 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6913 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6914 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6915 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6916 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6917 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 6918 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 6919 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 6920 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 6921 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 6922 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 6923 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 6924 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 6925 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 6926 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 6927 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 6928 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 6929 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 6930 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 6931 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 6932 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 6933 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 6934 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 6935 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 6936 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 6937 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 6938 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 6939 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 6940 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 6941 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 6942 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 6943 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 6944 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 6945 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 6946 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 6947 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 6948 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 6949 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 6950 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 6951 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 6952 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 6953 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 6954 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 6955 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 6956 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 6957 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 6958 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 6959 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 6960 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 6961 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 6962 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 6963 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 6964 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 6965 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 6966 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 6967 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 6968 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 6969 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 6970 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 6971 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 6972 }; 6973 6974 pcie_smmu: iommu@15200000 { 6975 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6976 reg = <0x0 0x15200000 0x0 0x80000>; 6977 #iommu-cells = <2>; 6978 #global-interrupts = <2>; 6979 dma-coherent; 6980 6981 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 6982 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 6983 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 6984 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 6985 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 6986 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 6987 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 6988 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 6989 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 6990 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 6991 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 6992 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 6993 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 6994 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 6995 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 6996 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 6997 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 6998 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 6999 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 7000 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 7001 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 7002 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 7003 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 7004 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 7005 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 7006 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 7007 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 7008 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 7009 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 7010 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 7011 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 7012 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 7013 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 7014 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 7015 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 7016 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 7017 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 7018 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 7019 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 7020 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 7021 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 7022 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 7023 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 7024 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 7025 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 7026 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 7027 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 7028 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 7029 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 7030 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 7031 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 7032 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 7033 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 7034 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 7035 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 7036 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 7037 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 7038 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 7039 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 7040 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 7041 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 7042 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 7043 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 7044 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 7045 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 7046 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 7047 }; 7048 7049 intc: interrupt-controller@17a00000 { 7050 compatible = "arm,gic-v3"; 7051 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 7052 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 7053 interrupt-controller; 7054 #address-cells = <0>; 7055 #interrupt-cells = <3>; 7056 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 7057 #redistributor-regions = <1>; 7058 redistributor-stride = <0x0 0x20000>; 7059 }; 7060 7061 watchdog@17c10000 { 7062 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 7063 reg = <0x0 0x17c10000 0x0 0x1000>; 7064 clocks = <&sleep_clk>; 7065 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 7066 }; 7067 7068 memtimer: timer@17c20000 { 7069 compatible = "arm,armv7-timer-mem"; 7070 reg = <0x0 0x17c20000 0x0 0x1000>; 7071 ranges = <0x0 0x0 0x0 0x20000000>; 7072 #address-cells = <1>; 7073 #size-cells = <1>; 7074 7075 frame@17c21000 { 7076 reg = <0x17c21000 0x1000>, 7077 <0x17c22000 0x1000>; 7078 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7079 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 7080 frame-number = <0>; 7081 }; 7082 7083 frame@17c23000 { 7084 reg = <0x17c23000 0x1000>; 7085 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 7086 frame-number = <1>; 7087 status = "disabled"; 7088 }; 7089 7090 frame@17c25000 { 7091 reg = <0x17c25000 0x1000>; 7092 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 7093 frame-number = <2>; 7094 status = "disabled"; 7095 }; 7096 7097 frame@17c27000 { 7098 reg = <0x17c27000 0x1000>; 7099 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 7100 frame-number = <3>; 7101 status = "disabled"; 7102 }; 7103 7104 frame@17c29000 { 7105 reg = <0x17c29000 0x1000>; 7106 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 7107 frame-number = <4>; 7108 status = "disabled"; 7109 }; 7110 7111 frame@17c2b000 { 7112 reg = <0x17c2b000 0x1000>; 7113 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 7114 frame-number = <5>; 7115 status = "disabled"; 7116 }; 7117 7118 frame@17c2d000 { 7119 reg = <0x17c2d000 0x1000>; 7120 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 7121 frame-number = <6>; 7122 status = "disabled"; 7123 }; 7124 }; 7125 7126 apps_rsc: rsc@18200000 { 7127 compatible = "qcom,rpmh-rsc"; 7128 reg = <0x0 0x18200000 0x0 0x10000>, 7129 <0x0 0x18210000 0x0 0x10000>, 7130 <0x0 0x18220000 0x0 0x10000>; 7131 reg-names = "drv-0", "drv-1", "drv-2"; 7132 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7133 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7134 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 7135 qcom,tcs-offset = <0xd00>; 7136 qcom,drv-id = <2>; 7137 qcom,tcs-config = <ACTIVE_TCS 2>, 7138 <SLEEP_TCS 3>, 7139 <WAKE_TCS 3>, 7140 <CONTROL_TCS 0>; 7141 label = "apps_rsc"; 7142 power-domains = <&system_pd>; 7143 7144 apps_bcm_voter: bcm-voter { 7145 compatible = "qcom,bcm-voter"; 7146 }; 7147 7148 rpmhcc: clock-controller { 7149 compatible = "qcom,sa8775p-rpmh-clk"; 7150 #clock-cells = <1>; 7151 clock-names = "xo"; 7152 clocks = <&xo_board_clk>; 7153 }; 7154 7155 rpmhpd: power-controller { 7156 compatible = "qcom,sa8775p-rpmhpd"; 7157 #power-domain-cells = <1>; 7158 operating-points-v2 = <&rpmhpd_opp_table>; 7159 7160 rpmhpd_opp_table: opp-table { 7161 compatible = "operating-points-v2"; 7162 7163 rpmhpd_opp_ret: opp-0 { 7164 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 7165 }; 7166 7167 rpmhpd_opp_min_svs: opp-1 { 7168 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 7169 }; 7170 7171 rpmhpd_opp_low_svs: opp2 { 7172 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 7173 }; 7174 7175 rpmhpd_opp_svs: opp3 { 7176 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 7177 }; 7178 7179 rpmhpd_opp_svs_l1: opp-4 { 7180 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 7181 }; 7182 7183 rpmhpd_opp_nom: opp-5 { 7184 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 7185 }; 7186 7187 rpmhpd_opp_nom_l1: opp-6 { 7188 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 7189 }; 7190 7191 rpmhpd_opp_nom_l2: opp-7 { 7192 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 7193 }; 7194 7195 rpmhpd_opp_turbo: opp-8 { 7196 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 7197 }; 7198 7199 rpmhpd_opp_turbo_l1: opp-9 { 7200 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 7201 }; 7202 }; 7203 }; 7204 }; 7205 7206 epss_l3_cl0: interconnect@18590000 { 7207 compatible = "qcom,sa8775p-epss-l3", 7208 "qcom,epss-l3"; 7209 reg = <0x0 0x18590000 0x0 0x1000>; 7210 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7211 clock-names = "xo", "alternate"; 7212 #interconnect-cells = <1>; 7213 }; 7214 7215 cpufreq_hw: cpufreq@18591000 { 7216 compatible = "qcom,sa8775p-cpufreq-epss", 7217 "qcom,cpufreq-epss"; 7218 reg = <0x0 0x18591000 0x0 0x1000>, 7219 <0x0 0x18593000 0x0 0x1000>; 7220 reg-names = "freq-domain0", "freq-domain1"; 7221 7222 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 7223 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 7224 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 7225 7226 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7227 clock-names = "xo", "alternate"; 7228 7229 #freq-domain-cells = <1>; 7230 }; 7231 7232 epss_l3_cl1: interconnect@18592000 { 7233 compatible = "qcom,sa8775p-epss-l3", 7234 "qcom,epss-l3"; 7235 reg = <0x0 0x18592000 0x0 0x1000>; 7236 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7237 clock-names = "xo", "alternate"; 7238 #interconnect-cells = <1>; 7239 }; 7240 7241 remoteproc_gpdsp0: remoteproc@20c00000 { 7242 compatible = "qcom,sa8775p-gpdsp0-pas"; 7243 reg = <0x0 0x20c00000 0x0 0x10000>; 7244 7245 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 7246 <&smp2p_gpdsp0_in 0 0>, 7247 <&smp2p_gpdsp0_in 1 0>, 7248 <&smp2p_gpdsp0_in 2 0>, 7249 <&smp2p_gpdsp0_in 3 0>; 7250 interrupt-names = "wdog", "fatal", "ready", 7251 "handover", "stop-ack"; 7252 7253 clocks = <&rpmhcc RPMH_CXO_CLK>; 7254 clock-names = "xo"; 7255 7256 power-domains = <&rpmhpd SA8775P_CX>, 7257 <&rpmhpd SA8775P_MXC>; 7258 power-domain-names = "cx", "mxc"; 7259 7260 interconnects = <&gpdsp_anoc MASTER_DSP0 0 7261 &config_noc SLAVE_CLK_CTL 0>; 7262 7263 memory-region = <&pil_gdsp0_mem>; 7264 7265 qcom,qmp = <&aoss_qmp>; 7266 7267 qcom,smem-states = <&smp2p_gpdsp0_out 0>; 7268 qcom,smem-state-names = "stop"; 7269 7270 status = "disabled"; 7271 7272 glink-edge { 7273 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 7274 IPCC_MPROC_SIGNAL_GLINK_QMP 7275 IRQ_TYPE_EDGE_RISING>; 7276 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 7277 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7278 7279 label = "gpdsp0"; 7280 qcom,remote-pid = <17>; 7281 7282 fastrpc { 7283 compatible = "qcom,fastrpc"; 7284 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7285 label = "gdsp0"; 7286 #address-cells = <1>; 7287 #size-cells = <0>; 7288 7289 compute-cb@1 { 7290 compatible = "qcom,fastrpc-compute-cb"; 7291 reg = <1>; 7292 iommus = <&apps_smmu 0x38a1 0x0>; 7293 dma-coherent; 7294 }; 7295 7296 compute-cb@2 { 7297 compatible = "qcom,fastrpc-compute-cb"; 7298 reg = <2>; 7299 iommus = <&apps_smmu 0x38a2 0x0>; 7300 dma-coherent; 7301 }; 7302 7303 compute-cb@3 { 7304 compatible = "qcom,fastrpc-compute-cb"; 7305 reg = <3>; 7306 iommus = <&apps_smmu 0x38a3 0x0>; 7307 dma-coherent; 7308 }; 7309 }; 7310 }; 7311 }; 7312 7313 remoteproc_gpdsp1: remoteproc@21c00000 { 7314 compatible = "qcom,sa8775p-gpdsp1-pas"; 7315 reg = <0x0 0x21c00000 0x0 0x10000>; 7316 7317 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 7318 <&smp2p_gpdsp1_in 0 0>, 7319 <&smp2p_gpdsp1_in 1 0>, 7320 <&smp2p_gpdsp1_in 2 0>, 7321 <&smp2p_gpdsp1_in 3 0>; 7322 interrupt-names = "wdog", "fatal", "ready", 7323 "handover", "stop-ack"; 7324 7325 clocks = <&rpmhcc RPMH_CXO_CLK>; 7326 clock-names = "xo"; 7327 7328 power-domains = <&rpmhpd SA8775P_CX>, 7329 <&rpmhpd SA8775P_MXC>; 7330 power-domain-names = "cx", "mxc"; 7331 7332 interconnects = <&gpdsp_anoc MASTER_DSP1 0 7333 &config_noc SLAVE_CLK_CTL 0>; 7334 7335 memory-region = <&pil_gdsp1_mem>; 7336 7337 qcom,qmp = <&aoss_qmp>; 7338 7339 qcom,smem-states = <&smp2p_gpdsp1_out 0>; 7340 qcom,smem-state-names = "stop"; 7341 7342 status = "disabled"; 7343 7344 glink-edge { 7345 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 7346 IPCC_MPROC_SIGNAL_GLINK_QMP 7347 IRQ_TYPE_EDGE_RISING>; 7348 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 7349 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7350 7351 label = "gpdsp1"; 7352 qcom,remote-pid = <18>; 7353 7354 fastrpc { 7355 compatible = "qcom,fastrpc"; 7356 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7357 label = "gdsp1"; 7358 #address-cells = <1>; 7359 #size-cells = <0>; 7360 7361 compute-cb@1 { 7362 compatible = "qcom,fastrpc-compute-cb"; 7363 reg = <1>; 7364 iommus = <&apps_smmu 0x38c1 0x0>; 7365 dma-coherent; 7366 }; 7367 7368 compute-cb@2 { 7369 compatible = "qcom,fastrpc-compute-cb"; 7370 reg = <2>; 7371 iommus = <&apps_smmu 0x38c2 0x0>; 7372 dma-coherent; 7373 }; 7374 7375 compute-cb@3 { 7376 compatible = "qcom,fastrpc-compute-cb"; 7377 reg = <3>; 7378 iommus = <&apps_smmu 0x38c3 0x0>; 7379 dma-coherent; 7380 }; 7381 }; 7382 }; 7383 }; 7384 7385 mdss1: display-subsystem@22000000 { 7386 compatible = "qcom,sa8775p-mdss"; 7387 reg = <0x0 0x22000000 0x0 0x1000>; 7388 reg-names = "mdss"; 7389 7390 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 QCOM_ICC_TAG_ALWAYS 7391 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 7392 <&mmss_noc MASTER_MDP_CORE1_1 QCOM_ICC_TAG_ALWAYS 7393 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 7394 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 7395 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 7396 interconnect-names = "mdp0-mem", 7397 "mdp1-mem", 7398 "cpu-cfg"; 7399 7400 resets = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_BCR>; 7401 7402 power-domains = <&dispcc1 MDSS_DISP_CC_MDSS_CORE_GDSC>; 7403 7404 clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, 7405 <&gcc GCC_DISP1_HF_AXI_CLK>, 7406 <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>; 7407 7408 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 7409 interrupt-controller; 7410 #interrupt-cells = <1>; 7411 7412 iommus = <&apps_smmu 0x1800 0x402>; 7413 7414 #address-cells = <2>; 7415 #size-cells = <2>; 7416 ranges; 7417 7418 status = "disabled"; 7419 7420 display-controller@22001000 { 7421 compatible = "qcom,sa8775p-dpu"; 7422 reg = <0x0 0x22001000 0x0 0x8f000>, 7423 <0x0 0x220b0000 0x0 0x3000>; 7424 reg-names = "mdp", "vbif"; 7425 7426 clocks = <&gcc GCC_DISP1_HF_AXI_CLK>, 7427 <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, 7428 <&dispcc1 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 7429 <&dispcc1 MDSS_DISP_CC_MDSS_MDP_CLK>, 7430 <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 7431 clock-names = "nrt_bus", 7432 "iface", 7433 "lut", 7434 "core", 7435 "vsync"; 7436 7437 assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 7438 assigned-clock-rates = <19200000>; 7439 7440 operating-points-v2 = <&mdss0_mdp_opp_table>; 7441 power-domains = <&rpmhpd SA8775P_MMCX>; 7442 7443 interrupt-parent = <&mdss1>; 7444 interrupts = <0>; 7445 7446 ports { 7447 #address-cells = <1>; 7448 #size-cells = <0>; 7449 7450 port@0 { 7451 reg = <0>; 7452 7453 dpu1_intf0_out: endpoint { 7454 remote-endpoint = <&mdss1_dp0_in>; 7455 }; 7456 }; 7457 7458 port@1 { 7459 reg = <1>; 7460 7461 dpu1_intf4_out: endpoint { 7462 remote-endpoint = <&mdss1_dp1_in>; 7463 }; 7464 }; 7465 }; 7466 }; 7467 7468 mdss1_dp0_phy: phy@220c2a00 { 7469 compatible = "qcom,sa8775p-edp-phy"; 7470 reg = <0x0 0x220c2a00 0x0 0x200>, 7471 <0x0 0x220c2200 0x0 0xd0>, 7472 <0x0 0x220c2600 0x0 0xd0>, 7473 <0x0 0x220c2000 0x0 0x1c8>; 7474 7475 clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 7476 <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, 7477 <&gcc GCC_EDP_REF_CLKREF_EN>; 7478 clock-names = "aux", 7479 "cfg_ahb", 7480 "ref"; 7481 7482 #clock-cells = <1>; 7483 #phy-cells = <0>; 7484 7485 status = "disabled"; 7486 }; 7487 7488 mdss1_dp1_phy: phy@220c5a00 { 7489 compatible = "qcom,sa8775p-edp-phy"; 7490 reg = <0x0 0x220c5a00 0x0 0x200>, 7491 <0x0 0x220c5200 0x0 0xd0>, 7492 <0x0 0x220c5600 0x0 0xd0>, 7493 <0x0 0x220c5000 0x0 0x1c8>; 7494 7495 clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 7496 <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, 7497 <&gcc GCC_EDP_REF_CLKREF_EN>; 7498 clock-names = "aux", 7499 "cfg_ahb", 7500 "ref"; 7501 7502 #clock-cells = <1>; 7503 #phy-cells = <0>; 7504 7505 status = "disabled"; 7506 }; 7507 7508 mdss1_dp0: displayport-controller@22154000 { 7509 compatible = "qcom,sa8775p-dp"; 7510 reg = <0x0 0x22154000 0x0 0x104>, 7511 <0x0 0x22154200 0x0 0x0c0>, 7512 <0x0 0x22155000 0x0 0x770>, 7513 <0x0 0x22156000 0x0 0x09c>, 7514 <0x0 0x22157000 0x0 0x09c>, 7515 <0x0 0x22158000 0x0 0x09c>, 7516 <0x0 0x22159000 0x0 0x09c>, 7517 <0x0 0x2215a000 0x0 0x23c>, 7518 <0x0 0x2215b000 0x0 0x23c>; 7519 7520 interrupt-parent = <&mdss1>; 7521 interrupts = <12>; 7522 7523 clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, 7524 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 7525 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 7526 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 7527 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 7528 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, 7529 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, 7530 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; 7531 clock-names = "core_iface", 7532 "core_aux", 7533 "ctrl_link", 7534 "ctrl_link_iface", 7535 "stream_pixel", 7536 "stream_1_pixel", 7537 "stream_2_pixel", 7538 "stream_3_pixel"; 7539 assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 7540 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 7541 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, 7542 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, 7543 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; 7544 assigned-clock-parents = <&mdss1_dp0_phy 0>, 7545 <&mdss1_dp0_phy 1>, 7546 <&mdss1_dp0_phy 1>, 7547 <&mdss1_dp0_phy 1>, 7548 <&mdss1_dp0_phy 1>; 7549 phys = <&mdss1_dp0_phy>; 7550 phy-names = "dp"; 7551 7552 operating-points-v2 = <&dp_opp_table>; 7553 power-domains = <&rpmhpd SA8775P_MMCX>; 7554 7555 #sound-dai-cells = <0>; 7556 7557 status = "disabled"; 7558 7559 ports { 7560 #address-cells = <1>; 7561 #size-cells = <0>; 7562 7563 port@0 { 7564 reg = <0>; 7565 7566 mdss1_dp0_in: endpoint { 7567 remote-endpoint = <&dpu1_intf0_out>; 7568 }; 7569 }; 7570 7571 port@1 { 7572 reg = <1>; 7573 7574 mdss1_dp0_out: endpoint { }; 7575 }; 7576 }; 7577 }; 7578 7579 mdss1_dp1: displayport-controller@2215c000 { 7580 compatible = "qcom,sa8775p-dp"; 7581 reg = <0x0 0x2215c000 0x0 0x104>, 7582 <0x0 0x2215c200 0x0 0x0c0>, 7583 <0x0 0x2215d000 0x0 0x770>, 7584 <0x0 0x2215e000 0x0 0x09c>, 7585 <0x0 0x2215f000 0x0 0x09c>, 7586 <0x0 0x22160000 0x0 0x09c>, 7587 <0x0 0x22161000 0x0 0x09c>, 7588 <0x0 0x22162000 0x0 0x23c>, 7589 <0x0 0x22163000 0x0 0x23c>; 7590 7591 interrupt-parent = <&mdss1>; 7592 interrupts = <13>; 7593 7594 clocks = <&dispcc1 MDSS_DISP_CC_MDSS_AHB_CLK>, 7595 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 7596 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, 7597 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 7598 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 7599 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 7600 clock-names = "core_iface", 7601 "core_aux", 7602 "ctrl_link", 7603 "ctrl_link_iface", 7604 "stream_pixel", 7605 "stream_1_pixel"; 7606 assigned-clocks = <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 7607 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 7608 <&dispcc1 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 7609 assigned-clock-parents = <&mdss1_dp1_phy 0>, 7610 <&mdss1_dp1_phy 1>, 7611 <&mdss1_dp1_phy 1>; 7612 phys = <&mdss1_dp1_phy>; 7613 phy-names = "dp"; 7614 7615 operating-points-v2 = <&dp_opp_table>; 7616 power-domains = <&rpmhpd SA8775P_MMCX>; 7617 7618 #sound-dai-cells = <0>; 7619 7620 status = "disabled"; 7621 7622 ports { 7623 #address-cells = <1>; 7624 #size-cells = <0>; 7625 7626 port@0 { 7627 reg = <0>; 7628 7629 mdss1_dp1_in: endpoint { 7630 remote-endpoint = <&dpu1_intf4_out>; 7631 }; 7632 }; 7633 7634 port@1 { 7635 reg = <1>; 7636 7637 mdss1_dp1_out: endpoint { }; 7638 }; 7639 }; 7640 7641 }; 7642 }; 7643 7644 dispcc1: clock-controller@22100000 { 7645 compatible = "qcom,sa8775p-dispcc1"; 7646 reg = <0x0 0x22100000 0x0 0x20000>; 7647 clocks = <&gcc GCC_DISP_AHB_CLK>, 7648 <&rpmhcc RPMH_CXO_CLK>, 7649 <&rpmhcc RPMH_CXO_CLK_A>, 7650 <&sleep_clk>, 7651 <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>, 7652 <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>, 7653 <0>, <0>, <0>, <0>; 7654 power-domains = <&rpmhpd SA8775P_MMCX>; 7655 #clock-cells = <1>; 7656 #reset-cells = <1>; 7657 #power-domain-cells = <1>; 7658 }; 7659 7660 ethernet1: ethernet@23000000 { 7661 compatible = "qcom,sa8775p-ethqos"; 7662 reg = <0x0 0x23000000 0x0 0x10000>, 7663 <0x0 0x23016000 0x0 0x100>; 7664 reg-names = "stmmaceth", "rgmii"; 7665 7666 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 7667 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 7668 interrupt-names = "macirq", "sfty"; 7669 7670 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 7671 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 7672 <&gcc GCC_EMAC1_PTP_CLK>, 7673 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 7674 clock-names = "stmmaceth", 7675 "pclk", 7676 "ptp_ref", 7677 "phyaux"; 7678 7679 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 7680 &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>, 7681 <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS 7682 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7683 interconnect-names = "cpu-mac", 7684 "mac-mem"; 7685 7686 power-domains = <&gcc EMAC1_GDSC>; 7687 7688 phys = <&serdes1>; 7689 phy-names = "serdes"; 7690 7691 iommus = <&apps_smmu 0x140 0xf>; 7692 dma-coherent; 7693 7694 snps,tso; 7695 snps,pbl = <32>; 7696 rx-fifo-depth = <16384>; 7697 tx-fifo-depth = <16384>; 7698 7699 status = "disabled"; 7700 }; 7701 7702 ethernet0: ethernet@23040000 { 7703 compatible = "qcom,sa8775p-ethqos"; 7704 reg = <0x0 0x23040000 0x0 0x10000>, 7705 <0x0 0x23056000 0x0 0x100>; 7706 reg-names = "stmmaceth", "rgmii"; 7707 7708 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 7709 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; 7710 interrupt-names = "macirq", "sfty"; 7711 7712 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 7713 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 7714 <&gcc GCC_EMAC0_PTP_CLK>, 7715 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 7716 clock-names = "stmmaceth", 7717 "pclk", 7718 "ptp_ref", 7719 "phyaux"; 7720 7721 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 7722 &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>, 7723 <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS 7724 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7725 interconnect-names = "cpu-mac", 7726 "mac-mem"; 7727 7728 power-domains = <&gcc EMAC0_GDSC>; 7729 7730 phys = <&serdes0>; 7731 phy-names = "serdes"; 7732 7733 iommus = <&apps_smmu 0x120 0xf>; 7734 dma-coherent; 7735 7736 snps,tso; 7737 snps,pbl = <32>; 7738 rx-fifo-depth = <16384>; 7739 tx-fifo-depth = <16384>; 7740 7741 status = "disabled"; 7742 }; 7743 7744 nspa_noc: interconnect@260c0000 { 7745 compatible = "qcom,sa8775p-nspa-noc"; 7746 reg = <0x0 0x260c0000 0x0 0x16080>; 7747 #interconnect-cells = <2>; 7748 qcom,bcm-voters = <&apps_bcm_voter>; 7749 }; 7750 7751 remoteproc_cdsp0: remoteproc@26300000 { 7752 compatible = "qcom,sa8775p-cdsp0-pas"; 7753 reg = <0x0 0x26300000 0x0 0x10000>; 7754 7755 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 7756 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>, 7757 <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>, 7758 <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>, 7759 <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>; 7760 interrupt-names = "wdog", "fatal", "ready", 7761 "handover", "stop-ack"; 7762 7763 clocks = <&rpmhcc RPMH_CXO_CLK>; 7764 clock-names = "xo"; 7765 7766 power-domains = <&rpmhpd SA8775P_CX>, 7767 <&rpmhpd SA8775P_MXC>, 7768 <&rpmhpd SA8775P_NSP0>; 7769 power-domain-names = "cx", "mxc", "nsp"; 7770 7771 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 7772 &mc_virt SLAVE_EBI1 0>; 7773 7774 memory-region = <&pil_cdsp0_mem>; 7775 7776 qcom,qmp = <&aoss_qmp>; 7777 7778 qcom,smem-states = <&smp2p_cdsp0_out 0>; 7779 qcom,smem-state-names = "stop"; 7780 7781 status = "disabled"; 7782 7783 glink-edge { 7784 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7785 IPCC_MPROC_SIGNAL_GLINK_QMP 7786 IRQ_TYPE_EDGE_RISING>; 7787 mboxes = <&ipcc IPCC_CLIENT_CDSP 7788 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7789 7790 label = "cdsp"; 7791 qcom,remote-pid = <5>; 7792 7793 fastrpc { 7794 compatible = "qcom,fastrpc"; 7795 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7796 label = "cdsp"; 7797 #address-cells = <1>; 7798 #size-cells = <0>; 7799 7800 compute-cb@1 { 7801 compatible = "qcom,fastrpc-compute-cb"; 7802 reg = <1>; 7803 iommus = <&apps_smmu 0x2141 0x04a0>, 7804 <&apps_smmu 0x2181 0x0400>; 7805 dma-coherent; 7806 }; 7807 7808 compute-cb@2 { 7809 compatible = "qcom,fastrpc-compute-cb"; 7810 reg = <2>; 7811 iommus = <&apps_smmu 0x2142 0x04a0>, 7812 <&apps_smmu 0x2182 0x0400>; 7813 dma-coherent; 7814 }; 7815 7816 compute-cb@3 { 7817 compatible = "qcom,fastrpc-compute-cb"; 7818 reg = <3>; 7819 iommus = <&apps_smmu 0x2143 0x04a0>, 7820 <&apps_smmu 0x2183 0x0400>; 7821 dma-coherent; 7822 }; 7823 7824 compute-cb@4 { 7825 compatible = "qcom,fastrpc-compute-cb"; 7826 reg = <4>; 7827 iommus = <&apps_smmu 0x2144 0x04a0>, 7828 <&apps_smmu 0x2184 0x0400>; 7829 dma-coherent; 7830 }; 7831 7832 compute-cb@5 { 7833 compatible = "qcom,fastrpc-compute-cb"; 7834 reg = <5>; 7835 iommus = <&apps_smmu 0x2145 0x04a0>, 7836 <&apps_smmu 0x2185 0x0400>; 7837 dma-coherent; 7838 }; 7839 7840 compute-cb@6 { 7841 compatible = "qcom,fastrpc-compute-cb"; 7842 reg = <6>; 7843 iommus = <&apps_smmu 0x2146 0x04a0>, 7844 <&apps_smmu 0x2186 0x0400>; 7845 dma-coherent; 7846 }; 7847 7848 compute-cb@7 { 7849 compatible = "qcom,fastrpc-compute-cb"; 7850 reg = <7>; 7851 iommus = <&apps_smmu 0x2147 0x04a0>, 7852 <&apps_smmu 0x2187 0x0400>; 7853 dma-coherent; 7854 }; 7855 7856 compute-cb@8 { 7857 compatible = "qcom,fastrpc-compute-cb"; 7858 reg = <8>; 7859 iommus = <&apps_smmu 0x2148 0x04a0>, 7860 <&apps_smmu 0x2188 0x0400>; 7861 dma-coherent; 7862 }; 7863 7864 compute-cb@9 { 7865 compatible = "qcom,fastrpc-compute-cb"; 7866 reg = <9>; 7867 iommus = <&apps_smmu 0x2149 0x04a0>, 7868 <&apps_smmu 0x2189 0x0400>; 7869 dma-coherent; 7870 }; 7871 7872 compute-cb@11 { 7873 compatible = "qcom,fastrpc-compute-cb"; 7874 reg = <11>; 7875 iommus = <&apps_smmu 0x214b 0x04a0>, 7876 <&apps_smmu 0x218b 0x0400>; 7877 dma-coherent; 7878 }; 7879 }; 7880 }; 7881 }; 7882 7883 nspb_noc: interconnect@2a0c0000 { 7884 compatible = "qcom,sa8775p-nspb-noc"; 7885 reg = <0x0 0x2a0c0000 0x0 0x16080>; 7886 #interconnect-cells = <2>; 7887 qcom,bcm-voters = <&apps_bcm_voter>; 7888 }; 7889 7890 remoteproc_cdsp1: remoteproc@2a300000 { 7891 compatible = "qcom,sa8775p-cdsp1-pas"; 7892 reg = <0x0 0x2a300000 0x0 0x10000>; 7893 7894 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 7895 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, 7896 <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>, 7897 <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>, 7898 <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>; 7899 interrupt-names = "wdog", "fatal", "ready", 7900 "handover", "stop-ack"; 7901 7902 clocks = <&rpmhcc RPMH_CXO_CLK>; 7903 clock-names = "xo"; 7904 7905 power-domains = <&rpmhpd SA8775P_CX>, 7906 <&rpmhpd SA8775P_MXC>, 7907 <&rpmhpd SA8775P_NSP1>; 7908 power-domain-names = "cx", "mxc", "nsp"; 7909 7910 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 7911 &mc_virt SLAVE_EBI1 0>; 7912 7913 memory-region = <&pil_cdsp1_mem>; 7914 7915 qcom,qmp = <&aoss_qmp>; 7916 7917 qcom,smem-states = <&smp2p_cdsp1_out 0>; 7918 qcom,smem-state-names = "stop"; 7919 7920 status = "disabled"; 7921 7922 glink-edge { 7923 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 7924 IPCC_MPROC_SIGNAL_GLINK_QMP 7925 IRQ_TYPE_EDGE_RISING>; 7926 mboxes = <&ipcc IPCC_CLIENT_NSP1 7927 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7928 7929 label = "cdsp"; 7930 qcom,remote-pid = <12>; 7931 7932 fastrpc { 7933 compatible = "qcom,fastrpc"; 7934 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7935 label = "cdsp1"; 7936 #address-cells = <1>; 7937 #size-cells = <0>; 7938 7939 compute-cb@1 { 7940 compatible = "qcom,fastrpc-compute-cb"; 7941 reg = <1>; 7942 iommus = <&apps_smmu 0x2941 0x04a0>, 7943 <&apps_smmu 0x2981 0x0400>; 7944 dma-coherent; 7945 }; 7946 7947 compute-cb@2 { 7948 compatible = "qcom,fastrpc-compute-cb"; 7949 reg = <2>; 7950 iommus = <&apps_smmu 0x2942 0x04a0>, 7951 <&apps_smmu 0x2982 0x0400>; 7952 dma-coherent; 7953 }; 7954 7955 compute-cb@3 { 7956 compatible = "qcom,fastrpc-compute-cb"; 7957 reg = <3>; 7958 iommus = <&apps_smmu 0x2943 0x04a0>, 7959 <&apps_smmu 0x2983 0x0400>; 7960 dma-coherent; 7961 }; 7962 7963 compute-cb@4 { 7964 compatible = "qcom,fastrpc-compute-cb"; 7965 reg = <4>; 7966 iommus = <&apps_smmu 0x2944 0x04a0>, 7967 <&apps_smmu 0x2984 0x0400>; 7968 dma-coherent; 7969 }; 7970 7971 compute-cb@5 { 7972 compatible = "qcom,fastrpc-compute-cb"; 7973 reg = <5>; 7974 iommus = <&apps_smmu 0x2945 0x04a0>, 7975 <&apps_smmu 0x2985 0x0400>; 7976 dma-coherent; 7977 }; 7978 7979 compute-cb@6 { 7980 compatible = "qcom,fastrpc-compute-cb"; 7981 reg = <6>; 7982 iommus = <&apps_smmu 0x2946 0x04a0>, 7983 <&apps_smmu 0x2986 0x0400>; 7984 dma-coherent; 7985 }; 7986 7987 compute-cb@7 { 7988 compatible = "qcom,fastrpc-compute-cb"; 7989 reg = <7>; 7990 iommus = <&apps_smmu 0x2947 0x04a0>, 7991 <&apps_smmu 0x2987 0x0400>; 7992 dma-coherent; 7993 }; 7994 7995 compute-cb@8 { 7996 compatible = "qcom,fastrpc-compute-cb"; 7997 reg = <8>; 7998 iommus = <&apps_smmu 0x2948 0x04a0>, 7999 <&apps_smmu 0x2988 0x0400>; 8000 dma-coherent; 8001 }; 8002 8003 compute-cb@9 { 8004 compatible = "qcom,fastrpc-compute-cb"; 8005 reg = <9>; 8006 iommus = <&apps_smmu 0x2949 0x04a0>, 8007 <&apps_smmu 0x2989 0x0400>; 8008 dma-coherent; 8009 }; 8010 8011 compute-cb@10 { 8012 compatible = "qcom,fastrpc-compute-cb"; 8013 reg = <10>; 8014 iommus = <&apps_smmu 0x294a 0x04a0>, 8015 <&apps_smmu 0x298a 0x0400>; 8016 dma-coherent; 8017 }; 8018 8019 compute-cb@11 { 8020 compatible = "qcom,fastrpc-compute-cb"; 8021 reg = <11>; 8022 iommus = <&apps_smmu 0x294b 0x04a0>, 8023 <&apps_smmu 0x298b 0x0400>; 8024 dma-coherent; 8025 }; 8026 8027 compute-cb@12 { 8028 compatible = "qcom,fastrpc-compute-cb"; 8029 reg = <12>; 8030 iommus = <&apps_smmu 0x294c 0x04a0>, 8031 <&apps_smmu 0x298c 0x0400>; 8032 dma-coherent; 8033 }; 8034 8035 compute-cb@13 { 8036 compatible = "qcom,fastrpc-compute-cb"; 8037 reg = <13>; 8038 iommus = <&apps_smmu 0x294d 0x04a0>, 8039 <&apps_smmu 0x298d 0x0400>; 8040 dma-coherent; 8041 }; 8042 }; 8043 }; 8044 }; 8045 8046 remoteproc_adsp: remoteproc@30000000 { 8047 compatible = "qcom,sa8775p-adsp-pas"; 8048 reg = <0x0 0x30000000 0x0 0x100>; 8049 8050 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 8051 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 8052 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 8053 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 8054 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 8055 interrupt-names = "wdog", "fatal", "ready", "handover", 8056 "stop-ack"; 8057 8058 clocks = <&rpmhcc RPMH_CXO_CLK>; 8059 clock-names = "xo"; 8060 8061 power-domains = <&rpmhpd SA8775P_LCX>, 8062 <&rpmhpd SA8775P_LMX>; 8063 power-domain-names = "lcx", "lmx"; 8064 8065 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 8066 8067 memory-region = <&pil_adsp_mem>; 8068 8069 qcom,qmp = <&aoss_qmp>; 8070 8071 qcom,smem-states = <&smp2p_adsp_out 0>; 8072 qcom,smem-state-names = "stop"; 8073 8074 status = "disabled"; 8075 8076 glink-edge { 8077 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 8078 IPCC_MPROC_SIGNAL_GLINK_QMP 8079 IRQ_TYPE_EDGE_RISING>; 8080 mboxes = <&ipcc IPCC_CLIENT_LPASS 8081 IPCC_MPROC_SIGNAL_GLINK_QMP>; 8082 8083 label = "lpass"; 8084 qcom,remote-pid = <2>; 8085 8086 fastrpc { 8087 compatible = "qcom,fastrpc"; 8088 qcom,glink-channels = "fastrpcglink-apps-dsp"; 8089 label = "adsp"; 8090 memory-region = <&adsp_rpc_remote_heap_mem>; 8091 qcom,vmids = <QCOM_SCM_VMID_LPASS 8092 QCOM_SCM_VMID_ADSP_HEAP>; 8093 #address-cells = <1>; 8094 #size-cells = <0>; 8095 8096 compute-cb@3 { 8097 compatible = "qcom,fastrpc-compute-cb"; 8098 reg = <3>; 8099 iommus = <&apps_smmu 0x3003 0x0>; 8100 dma-coherent; 8101 }; 8102 8103 compute-cb@4 { 8104 compatible = "qcom,fastrpc-compute-cb"; 8105 reg = <4>; 8106 iommus = <&apps_smmu 0x3004 0x0>; 8107 dma-coherent; 8108 }; 8109 8110 compute-cb@5 { 8111 compatible = "qcom,fastrpc-compute-cb"; 8112 reg = <5>; 8113 iommus = <&apps_smmu 0x3005 0x0>; 8114 qcom,nsessions = <5>; 8115 dma-coherent; 8116 }; 8117 }; 8118 8119 gpr { 8120 compatible = "qcom,gpr"; 8121 qcom,glink-channels = "adsp_apps"; 8122 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 8123 qcom,intents = <512 20>; 8124 #address-cells = <1>; 8125 #size-cells = <0>; 8126 8127 q6apm: service@1 { 8128 compatible = "qcom,q6apm"; 8129 reg = <GPR_APM_MODULE_IID>; 8130 #sound-dai-cells = <0>; 8131 qcom,protection-domain = "avs/audio", 8132 "msm/adsp/audio_pd"; 8133 8134 q6apmbedai: bedais { 8135 compatible = "qcom,q6apm-lpass-dais"; 8136 #sound-dai-cells = <1>; 8137 }; 8138 8139 q6apmdai: dais { 8140 compatible = "qcom,q6apm-dais"; 8141 iommus = <&apps_smmu 0x3001 0x0>; 8142 }; 8143 }; 8144 8145 q6prm: service@2 { 8146 compatible = "qcom,q6prm"; 8147 reg = <GPR_PRM_MODULE_IID>; 8148 qcom,protection-domain = "avs/audio", 8149 "msm/adsp/audio_pd"; 8150 8151 q6prmcc: clock-controller { 8152 compatible = "qcom,q6prm-lpass-clocks"; 8153 #clock-cells = <2>; 8154 }; 8155 }; 8156 }; 8157 }; 8158 }; 8159 }; 8160 8161 thermal-zones { 8162 aoss-0-thermal { 8163 thermal-sensors = <&tsens0 0>; 8164 8165 trips { 8166 trip-point0 { 8167 temperature = <105000>; 8168 hysteresis = <5000>; 8169 type = "passive"; 8170 }; 8171 8172 trip-point1 { 8173 temperature = <115000>; 8174 hysteresis = <5000>; 8175 type = "passive"; 8176 }; 8177 }; 8178 }; 8179 8180 cpu-0-0-0-thermal { 8181 polling-delay-passive = <10>; 8182 8183 thermal-sensors = <&tsens0 1>; 8184 8185 trips { 8186 trip-point0 { 8187 temperature = <105000>; 8188 hysteresis = <5000>; 8189 type = "passive"; 8190 }; 8191 8192 trip-point1 { 8193 temperature = <115000>; 8194 hysteresis = <5000>; 8195 type = "passive"; 8196 }; 8197 }; 8198 }; 8199 8200 cpu-0-1-0-thermal { 8201 polling-delay-passive = <10>; 8202 8203 thermal-sensors = <&tsens0 2>; 8204 8205 trips { 8206 trip-point0 { 8207 temperature = <105000>; 8208 hysteresis = <5000>; 8209 type = "passive"; 8210 }; 8211 8212 trip-point1 { 8213 temperature = <115000>; 8214 hysteresis = <5000>; 8215 type = "passive"; 8216 }; 8217 }; 8218 }; 8219 8220 cpu-0-2-0-thermal { 8221 polling-delay-passive = <10>; 8222 8223 thermal-sensors = <&tsens0 3>; 8224 8225 trips { 8226 trip-point0 { 8227 temperature = <105000>; 8228 hysteresis = <5000>; 8229 type = "passive"; 8230 }; 8231 8232 trip-point1 { 8233 temperature = <115000>; 8234 hysteresis = <5000>; 8235 type = "passive"; 8236 }; 8237 }; 8238 }; 8239 8240 cpu-0-3-0-thermal { 8241 polling-delay-passive = <10>; 8242 8243 thermal-sensors = <&tsens0 4>; 8244 8245 trips { 8246 trip-point0 { 8247 temperature = <105000>; 8248 hysteresis = <5000>; 8249 type = "passive"; 8250 }; 8251 8252 trip-point1 { 8253 temperature = <115000>; 8254 hysteresis = <5000>; 8255 type = "passive"; 8256 }; 8257 }; 8258 }; 8259 8260 gpuss-0-thermal { 8261 polling-delay-passive = <10>; 8262 8263 thermal-sensors = <&tsens0 5>; 8264 8265 cooling-maps { 8266 map0 { 8267 trip = <&gpuss0_alert0>; 8268 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8269 }; 8270 }; 8271 8272 trips { 8273 gpuss0_alert0: trip-point0 { 8274 temperature = <105000>; 8275 hysteresis = <5000>; 8276 type = "passive"; 8277 }; 8278 8279 trip-point1 { 8280 temperature = <115000>; 8281 hysteresis = <5000>; 8282 type = "passive"; 8283 }; 8284 }; 8285 }; 8286 8287 gpuss-1-thermal { 8288 polling-delay-passive = <10>; 8289 8290 thermal-sensors = <&tsens0 6>; 8291 8292 cooling-maps { 8293 map0 { 8294 trip = <&gpuss1_alert0>; 8295 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8296 }; 8297 }; 8298 8299 trips { 8300 gpuss1_alert0: trip-point0 { 8301 temperature = <105000>; 8302 hysteresis = <5000>; 8303 type = "passive"; 8304 }; 8305 8306 trip-point1 { 8307 temperature = <115000>; 8308 hysteresis = <5000>; 8309 type = "passive"; 8310 }; 8311 }; 8312 }; 8313 8314 gpuss-2-thermal { 8315 polling-delay-passive = <10>; 8316 8317 thermal-sensors = <&tsens0 7>; 8318 8319 cooling-maps { 8320 map0 { 8321 trip = <&gpuss2_alert0>; 8322 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8323 }; 8324 }; 8325 8326 trips { 8327 gpuss2_alert0: trip-point0 { 8328 temperature = <105000>; 8329 hysteresis = <5000>; 8330 type = "passive"; 8331 }; 8332 8333 trip-point1 { 8334 temperature = <115000>; 8335 hysteresis = <5000>; 8336 type = "passive"; 8337 }; 8338 }; 8339 }; 8340 8341 audio-thermal { 8342 thermal-sensors = <&tsens0 8>; 8343 8344 trips { 8345 trip-point0 { 8346 temperature = <105000>; 8347 hysteresis = <5000>; 8348 type = "passive"; 8349 }; 8350 8351 trip-point1 { 8352 temperature = <115000>; 8353 hysteresis = <5000>; 8354 type = "passive"; 8355 }; 8356 }; 8357 }; 8358 8359 camss-0-thermal { 8360 thermal-sensors = <&tsens0 9>; 8361 8362 trips { 8363 trip-point0 { 8364 temperature = <105000>; 8365 hysteresis = <5000>; 8366 type = "passive"; 8367 }; 8368 8369 trip-point1 { 8370 temperature = <115000>; 8371 hysteresis = <5000>; 8372 type = "passive"; 8373 }; 8374 }; 8375 }; 8376 8377 pcie-0-thermal { 8378 thermal-sensors = <&tsens0 10>; 8379 8380 trips { 8381 trip-point0 { 8382 temperature = <105000>; 8383 hysteresis = <5000>; 8384 type = "passive"; 8385 }; 8386 8387 trip-point1 { 8388 temperature = <115000>; 8389 hysteresis = <5000>; 8390 type = "passive"; 8391 }; 8392 }; 8393 }; 8394 8395 cpuss-0-0-thermal { 8396 thermal-sensors = <&tsens0 11>; 8397 8398 trips { 8399 trip-point0 { 8400 temperature = <105000>; 8401 hysteresis = <5000>; 8402 type = "passive"; 8403 }; 8404 8405 trip-point1 { 8406 temperature = <115000>; 8407 hysteresis = <5000>; 8408 type = "passive"; 8409 }; 8410 }; 8411 }; 8412 8413 aoss-1-thermal { 8414 thermal-sensors = <&tsens1 0>; 8415 8416 trips { 8417 trip-point0 { 8418 temperature = <105000>; 8419 hysteresis = <5000>; 8420 type = "passive"; 8421 }; 8422 8423 trip-point1 { 8424 temperature = <115000>; 8425 hysteresis = <5000>; 8426 type = "passive"; 8427 }; 8428 }; 8429 }; 8430 8431 cpu-0-0-1-thermal { 8432 polling-delay-passive = <10>; 8433 8434 thermal-sensors = <&tsens1 1>; 8435 8436 trips { 8437 trip-point0 { 8438 temperature = <105000>; 8439 hysteresis = <5000>; 8440 type = "passive"; 8441 }; 8442 8443 trip-point1 { 8444 temperature = <115000>; 8445 hysteresis = <5000>; 8446 type = "passive"; 8447 }; 8448 }; 8449 }; 8450 8451 cpu-0-1-1-thermal { 8452 polling-delay-passive = <10>; 8453 8454 thermal-sensors = <&tsens1 2>; 8455 8456 trips { 8457 trip-point0 { 8458 temperature = <105000>; 8459 hysteresis = <5000>; 8460 type = "passive"; 8461 }; 8462 8463 trip-point1 { 8464 temperature = <115000>; 8465 hysteresis = <5000>; 8466 type = "passive"; 8467 }; 8468 }; 8469 }; 8470 8471 cpu-0-2-1-thermal { 8472 polling-delay-passive = <10>; 8473 8474 thermal-sensors = <&tsens1 3>; 8475 8476 trips { 8477 trip-point0 { 8478 temperature = <105000>; 8479 hysteresis = <5000>; 8480 type = "passive"; 8481 }; 8482 8483 trip-point1 { 8484 temperature = <115000>; 8485 hysteresis = <5000>; 8486 type = "passive"; 8487 }; 8488 }; 8489 }; 8490 8491 cpu-0-3-1-thermal { 8492 polling-delay-passive = <10>; 8493 8494 thermal-sensors = <&tsens1 4>; 8495 8496 trips { 8497 trip-point0 { 8498 temperature = <105000>; 8499 hysteresis = <5000>; 8500 type = "passive"; 8501 }; 8502 8503 trip-point1 { 8504 temperature = <115000>; 8505 hysteresis = <5000>; 8506 type = "passive"; 8507 }; 8508 }; 8509 }; 8510 8511 gpuss-3-thermal { 8512 polling-delay-passive = <10>; 8513 8514 thermal-sensors = <&tsens1 5>; 8515 8516 cooling-maps { 8517 map0 { 8518 trip = <&gpuss3_alert0>; 8519 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8520 }; 8521 }; 8522 8523 trips { 8524 gpuss3_alert0: trip-point0 { 8525 temperature = <105000>; 8526 hysteresis = <5000>; 8527 type = "passive"; 8528 }; 8529 8530 trip-point1 { 8531 temperature = <115000>; 8532 hysteresis = <5000>; 8533 type = "passive"; 8534 }; 8535 }; 8536 }; 8537 8538 gpuss-4-thermal { 8539 polling-delay-passive = <10>; 8540 8541 thermal-sensors = <&tsens1 6>; 8542 8543 cooling-maps { 8544 map0 { 8545 trip = <&gpuss4_alert0>; 8546 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8547 }; 8548 }; 8549 8550 trips { 8551 gpuss4_alert0: trip-point0 { 8552 temperature = <105000>; 8553 hysteresis = <5000>; 8554 type = "passive"; 8555 }; 8556 8557 trip-point1 { 8558 temperature = <115000>; 8559 hysteresis = <5000>; 8560 type = "passive"; 8561 }; 8562 }; 8563 }; 8564 8565 gpuss-5-thermal { 8566 polling-delay-passive = <10>; 8567 8568 thermal-sensors = <&tsens1 7>; 8569 8570 cooling-maps { 8571 map0 { 8572 trip = <&gpuss5_alert0>; 8573 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8574 }; 8575 }; 8576 8577 trips { 8578 gpuss5_alert0: trip-point0 { 8579 temperature = <105000>; 8580 hysteresis = <5000>; 8581 type = "passive"; 8582 }; 8583 8584 trip-point1 { 8585 temperature = <115000>; 8586 hysteresis = <5000>; 8587 type = "passive"; 8588 }; 8589 }; 8590 }; 8591 8592 video-thermal { 8593 thermal-sensors = <&tsens1 8>; 8594 8595 trips { 8596 trip-point0 { 8597 temperature = <105000>; 8598 hysteresis = <5000>; 8599 type = "passive"; 8600 }; 8601 8602 trip-point1 { 8603 temperature = <115000>; 8604 hysteresis = <5000>; 8605 type = "passive"; 8606 }; 8607 }; 8608 }; 8609 8610 camss-1-thermal { 8611 thermal-sensors = <&tsens1 9>; 8612 8613 trips { 8614 trip-point0 { 8615 temperature = <105000>; 8616 hysteresis = <5000>; 8617 type = "passive"; 8618 }; 8619 8620 trip-point1 { 8621 temperature = <115000>; 8622 hysteresis = <5000>; 8623 type = "passive"; 8624 }; 8625 }; 8626 }; 8627 8628 pcie-1-thermal { 8629 thermal-sensors = <&tsens1 10>; 8630 8631 trips { 8632 trip-point0 { 8633 temperature = <105000>; 8634 hysteresis = <5000>; 8635 type = "passive"; 8636 }; 8637 8638 trip-point1 { 8639 temperature = <115000>; 8640 hysteresis = <5000>; 8641 type = "passive"; 8642 }; 8643 }; 8644 }; 8645 8646 cpuss-0-1-thermal { 8647 thermal-sensors = <&tsens1 11>; 8648 8649 trips { 8650 trip-point0 { 8651 temperature = <105000>; 8652 hysteresis = <5000>; 8653 type = "passive"; 8654 }; 8655 8656 trip-point1 { 8657 temperature = <115000>; 8658 hysteresis = <5000>; 8659 type = "passive"; 8660 }; 8661 }; 8662 }; 8663 8664 aoss-2-thermal { 8665 thermal-sensors = <&tsens2 0>; 8666 8667 trips { 8668 trip-point0 { 8669 temperature = <105000>; 8670 hysteresis = <5000>; 8671 type = "passive"; 8672 }; 8673 8674 trip-point1 { 8675 temperature = <115000>; 8676 hysteresis = <5000>; 8677 type = "passive"; 8678 }; 8679 }; 8680 }; 8681 8682 cpu-1-0-0-thermal { 8683 polling-delay-passive = <10>; 8684 8685 thermal-sensors = <&tsens2 1>; 8686 8687 trips { 8688 trip-point0 { 8689 temperature = <105000>; 8690 hysteresis = <5000>; 8691 type = "passive"; 8692 }; 8693 8694 trip-point1 { 8695 temperature = <115000>; 8696 hysteresis = <5000>; 8697 type = "passive"; 8698 }; 8699 }; 8700 }; 8701 8702 cpu-1-1-0-thermal { 8703 polling-delay-passive = <10>; 8704 8705 thermal-sensors = <&tsens2 2>; 8706 8707 trips { 8708 trip-point0 { 8709 temperature = <105000>; 8710 hysteresis = <5000>; 8711 type = "passive"; 8712 }; 8713 8714 trip-point1 { 8715 temperature = <115000>; 8716 hysteresis = <5000>; 8717 type = "passive"; 8718 }; 8719 }; 8720 }; 8721 8722 cpu-1-2-0-thermal { 8723 polling-delay-passive = <10>; 8724 8725 thermal-sensors = <&tsens2 3>; 8726 8727 trips { 8728 trip-point0 { 8729 temperature = <105000>; 8730 hysteresis = <5000>; 8731 type = "passive"; 8732 }; 8733 8734 trip-point1 { 8735 temperature = <115000>; 8736 hysteresis = <5000>; 8737 type = "passive"; 8738 }; 8739 }; 8740 }; 8741 8742 cpu-1-3-0-thermal { 8743 polling-delay-passive = <10>; 8744 8745 thermal-sensors = <&tsens2 4>; 8746 8747 trips { 8748 trip-point0 { 8749 temperature = <105000>; 8750 hysteresis = <5000>; 8751 type = "passive"; 8752 }; 8753 8754 trip-point1 { 8755 temperature = <115000>; 8756 hysteresis = <5000>; 8757 type = "passive"; 8758 }; 8759 }; 8760 }; 8761 8762 nsp-0-0-0-thermal { 8763 polling-delay-passive = <10>; 8764 8765 thermal-sensors = <&tsens2 5>; 8766 8767 trips { 8768 trip-point0 { 8769 temperature = <105000>; 8770 hysteresis = <5000>; 8771 type = "passive"; 8772 }; 8773 8774 trip-point1 { 8775 temperature = <115000>; 8776 hysteresis = <5000>; 8777 type = "passive"; 8778 }; 8779 }; 8780 }; 8781 8782 nsp-0-1-0-thermal { 8783 polling-delay-passive = <10>; 8784 8785 thermal-sensors = <&tsens2 6>; 8786 8787 trips { 8788 trip-point0 { 8789 temperature = <105000>; 8790 hysteresis = <5000>; 8791 type = "passive"; 8792 }; 8793 8794 trip-point1 { 8795 temperature = <115000>; 8796 hysteresis = <5000>; 8797 type = "passive"; 8798 }; 8799 }; 8800 }; 8801 8802 nsp-0-2-0-thermal { 8803 polling-delay-passive = <10>; 8804 8805 thermal-sensors = <&tsens2 7>; 8806 8807 trips { 8808 trip-point0 { 8809 temperature = <105000>; 8810 hysteresis = <5000>; 8811 type = "passive"; 8812 }; 8813 8814 trip-point1 { 8815 temperature = <115000>; 8816 hysteresis = <5000>; 8817 type = "passive"; 8818 }; 8819 }; 8820 }; 8821 8822 nsp-1-0-0-thermal { 8823 polling-delay-passive = <10>; 8824 8825 thermal-sensors = <&tsens2 8>; 8826 8827 trips { 8828 trip-point0 { 8829 temperature = <105000>; 8830 hysteresis = <5000>; 8831 type = "passive"; 8832 }; 8833 8834 trip-point1 { 8835 temperature = <115000>; 8836 hysteresis = <5000>; 8837 type = "passive"; 8838 }; 8839 }; 8840 }; 8841 8842 nsp-1-1-0-thermal { 8843 polling-delay-passive = <10>; 8844 8845 thermal-sensors = <&tsens2 9>; 8846 8847 trips { 8848 trip-point0 { 8849 temperature = <105000>; 8850 hysteresis = <5000>; 8851 type = "passive"; 8852 }; 8853 8854 trip-point1 { 8855 temperature = <115000>; 8856 hysteresis = <5000>; 8857 type = "passive"; 8858 }; 8859 }; 8860 }; 8861 8862 nsp-1-2-0-thermal { 8863 polling-delay-passive = <10>; 8864 8865 thermal-sensors = <&tsens2 10>; 8866 8867 trips { 8868 trip-point0 { 8869 temperature = <105000>; 8870 hysteresis = <5000>; 8871 type = "passive"; 8872 }; 8873 8874 trip-point1 { 8875 temperature = <115000>; 8876 hysteresis = <5000>; 8877 type = "passive"; 8878 }; 8879 }; 8880 }; 8881 8882 ddrss-0-thermal { 8883 thermal-sensors = <&tsens2 11>; 8884 8885 trips { 8886 trip-point0 { 8887 temperature = <105000>; 8888 hysteresis = <5000>; 8889 type = "passive"; 8890 }; 8891 8892 trip-point1 { 8893 temperature = <115000>; 8894 hysteresis = <5000>; 8895 type = "passive"; 8896 }; 8897 }; 8898 }; 8899 8900 cpuss-1-0-thermal { 8901 thermal-sensors = <&tsens2 12>; 8902 8903 trips { 8904 trip-point0 { 8905 temperature = <105000>; 8906 hysteresis = <5000>; 8907 type = "passive"; 8908 }; 8909 8910 trip-point1 { 8911 temperature = <115000>; 8912 hysteresis = <5000>; 8913 type = "passive"; 8914 }; 8915 }; 8916 }; 8917 8918 aoss-3-thermal { 8919 thermal-sensors = <&tsens3 0>; 8920 8921 trips { 8922 trip-point0 { 8923 temperature = <105000>; 8924 hysteresis = <5000>; 8925 type = "passive"; 8926 }; 8927 8928 trip-point1 { 8929 temperature = <115000>; 8930 hysteresis = <5000>; 8931 type = "passive"; 8932 }; 8933 }; 8934 }; 8935 8936 cpu-1-0-1-thermal { 8937 polling-delay-passive = <10>; 8938 8939 thermal-sensors = <&tsens3 1>; 8940 8941 trips { 8942 trip-point0 { 8943 temperature = <105000>; 8944 hysteresis = <5000>; 8945 type = "passive"; 8946 }; 8947 8948 trip-point1 { 8949 temperature = <115000>; 8950 hysteresis = <5000>; 8951 type = "passive"; 8952 }; 8953 }; 8954 }; 8955 8956 cpu-1-1-1-thermal { 8957 polling-delay-passive = <10>; 8958 8959 thermal-sensors = <&tsens3 2>; 8960 8961 trips { 8962 trip-point0 { 8963 temperature = <105000>; 8964 hysteresis = <5000>; 8965 type = "passive"; 8966 }; 8967 8968 trip-point1 { 8969 temperature = <115000>; 8970 hysteresis = <5000>; 8971 type = "passive"; 8972 }; 8973 }; 8974 }; 8975 8976 cpu-1-2-1-thermal { 8977 polling-delay-passive = <10>; 8978 8979 thermal-sensors = <&tsens3 3>; 8980 8981 trips { 8982 trip-point0 { 8983 temperature = <105000>; 8984 hysteresis = <5000>; 8985 type = "passive"; 8986 }; 8987 8988 trip-point1 { 8989 temperature = <115000>; 8990 hysteresis = <5000>; 8991 type = "passive"; 8992 }; 8993 }; 8994 }; 8995 8996 cpu-1-3-1-thermal { 8997 polling-delay-passive = <10>; 8998 8999 thermal-sensors = <&tsens3 4>; 9000 9001 trips { 9002 trip-point0 { 9003 temperature = <105000>; 9004 hysteresis = <5000>; 9005 type = "passive"; 9006 }; 9007 9008 trip-point1 { 9009 temperature = <115000>; 9010 hysteresis = <5000>; 9011 type = "passive"; 9012 }; 9013 }; 9014 }; 9015 9016 nsp-0-0-1-thermal { 9017 polling-delay-passive = <10>; 9018 9019 thermal-sensors = <&tsens3 5>; 9020 9021 trips { 9022 trip-point0 { 9023 temperature = <105000>; 9024 hysteresis = <5000>; 9025 type = "passive"; 9026 }; 9027 9028 trip-point1 { 9029 temperature = <115000>; 9030 hysteresis = <5000>; 9031 type = "passive"; 9032 }; 9033 }; 9034 }; 9035 9036 nsp-0-1-1-thermal { 9037 polling-delay-passive = <10>; 9038 9039 thermal-sensors = <&tsens3 6>; 9040 9041 trips { 9042 trip-point0 { 9043 temperature = <105000>; 9044 hysteresis = <5000>; 9045 type = "passive"; 9046 }; 9047 9048 trip-point1 { 9049 temperature = <115000>; 9050 hysteresis = <5000>; 9051 type = "passive"; 9052 }; 9053 }; 9054 }; 9055 9056 nsp-0-2-1-thermal { 9057 polling-delay-passive = <10>; 9058 9059 thermal-sensors = <&tsens3 7>; 9060 9061 trips { 9062 trip-point0 { 9063 temperature = <105000>; 9064 hysteresis = <5000>; 9065 type = "passive"; 9066 }; 9067 9068 trip-point1 { 9069 temperature = <115000>; 9070 hysteresis = <5000>; 9071 type = "passive"; 9072 }; 9073 }; 9074 }; 9075 9076 nsp-1-0-1-thermal { 9077 polling-delay-passive = <10>; 9078 9079 thermal-sensors = <&tsens3 8>; 9080 9081 trips { 9082 trip-point0 { 9083 temperature = <105000>; 9084 hysteresis = <5000>; 9085 type = "passive"; 9086 }; 9087 9088 trip-point1 { 9089 temperature = <115000>; 9090 hysteresis = <5000>; 9091 type = "passive"; 9092 }; 9093 }; 9094 }; 9095 9096 nsp-1-1-1-thermal { 9097 polling-delay-passive = <10>; 9098 9099 thermal-sensors = <&tsens3 9>; 9100 9101 trips { 9102 trip-point0 { 9103 temperature = <105000>; 9104 hysteresis = <5000>; 9105 type = "passive"; 9106 }; 9107 9108 trip-point1 { 9109 temperature = <115000>; 9110 hysteresis = <5000>; 9111 type = "passive"; 9112 }; 9113 }; 9114 }; 9115 9116 nsp-1-2-1-thermal { 9117 polling-delay-passive = <10>; 9118 9119 thermal-sensors = <&tsens3 10>; 9120 9121 trips { 9122 trip-point0 { 9123 temperature = <105000>; 9124 hysteresis = <5000>; 9125 type = "passive"; 9126 }; 9127 9128 trip-point1 { 9129 temperature = <115000>; 9130 hysteresis = <5000>; 9131 type = "passive"; 9132 }; 9133 }; 9134 }; 9135 9136 ddrss-1-thermal { 9137 thermal-sensors = <&tsens3 11>; 9138 9139 trips { 9140 trip-point0 { 9141 temperature = <105000>; 9142 hysteresis = <5000>; 9143 type = "passive"; 9144 }; 9145 9146 trip-point1 { 9147 temperature = <115000>; 9148 hysteresis = <5000>; 9149 type = "passive"; 9150 }; 9151 }; 9152 }; 9153 9154 cpuss-1-1-thermal { 9155 thermal-sensors = <&tsens3 12>; 9156 9157 trips { 9158 trip-point0 { 9159 temperature = <105000>; 9160 hysteresis = <5000>; 9161 type = "passive"; 9162 }; 9163 9164 trip-point1 { 9165 temperature = <115000>; 9166 hysteresis = <5000>; 9167 type = "passive"; 9168 }; 9169 }; 9170 }; 9171 }; 9172 9173 arch_timer: timer { 9174 compatible = "arm,armv8-timer"; 9175 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 9176 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 9177 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 9178 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 9179 }; 9180 9181 turing-llm-tpdm { 9182 compatible = "qcom,coresight-static-tpdm"; 9183 label = "tpdm_cdsp_llm_0"; 9184 9185 qcom,cmb-element-bits = <32>; 9186 9187 out-ports { 9188 port { 9189 turing_llm_tpdm_out: endpoint { 9190 remote-endpoint = <&turing0_funnel_in1>; 9191 }; 9192 }; 9193 }; 9194 }; 9195}; 9196