1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#include <dt-bindings/interconnect/qcom,icc.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 12#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 13#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 14#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 15#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/firmware/qcom,scm.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 clocks { 33 xo_board_clk: xo-board-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "qcom,kryo"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 power-domains = <&cpu_pd0>; 54 power-domain-names = "psci"; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 next-level-cache = <&l2_0>; 57 capacity-dmips-mhz = <1024>; 58 #cooling-cells = <2>; 59 dynamic-power-coefficient = <100>; 60 operating-points-v2 = <&cpu0_opp_table>; 61 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 62 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 63 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 64 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 65 l2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&l3_0>; 70 l3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 cpu1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo"; 81 reg = <0x0 0x100>; 82 enable-method = "psci"; 83 power-domains = <&cpu_pd1>; 84 power-domain-names = "psci"; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 next-level-cache = <&l2_1>; 87 capacity-dmips-mhz = <1024>; 88 #cooling-cells = <2>; 89 dynamic-power-coefficient = <100>; 90 operating-points-v2 = <&cpu0_opp_table>; 91 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 92 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 93 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 94 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 95 l2_1: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 next-level-cache = <&l3_0>; 100 }; 101 }; 102 103 cpu2: cpu@200 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo"; 106 reg = <0x0 0x200>; 107 enable-method = "psci"; 108 power-domains = <&cpu_pd2>; 109 power-domain-names = "psci"; 110 qcom,freq-domain = <&cpufreq_hw 0>; 111 next-level-cache = <&l2_2>; 112 capacity-dmips-mhz = <1024>; 113 #cooling-cells = <2>; 114 dynamic-power-coefficient = <100>; 115 operating-points-v2 = <&cpu0_opp_table>; 116 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 117 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 118 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 119 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 120 l2_2: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 cache-unified; 124 next-level-cache = <&l3_0>; 125 }; 126 }; 127 128 cpu3: cpu@300 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo"; 131 reg = <0x0 0x300>; 132 enable-method = "psci"; 133 power-domains = <&cpu_pd3>; 134 power-domain-names = "psci"; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 next-level-cache = <&l2_3>; 137 capacity-dmips-mhz = <1024>; 138 #cooling-cells = <2>; 139 dynamic-power-coefficient = <100>; 140 operating-points-v2 = <&cpu0_opp_table>; 141 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 143 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 144 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 145 l2_3: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&l3_0>; 150 }; 151 }; 152 153 cpu4: cpu@10000 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo"; 156 reg = <0x0 0x10000>; 157 enable-method = "psci"; 158 power-domains = <&cpu_pd4>; 159 power-domain-names = "psci"; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 next-level-cache = <&l2_4>; 162 capacity-dmips-mhz = <1024>; 163 #cooling-cells = <2>; 164 dynamic-power-coefficient = <100>; 165 operating-points-v2 = <&cpu4_opp_table>; 166 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 167 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 168 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 169 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 170 l2_4: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_1>; 175 l3_1: l3-cache { 176 compatible = "cache"; 177 cache-level = <3>; 178 cache-unified; 179 }; 180 181 }; 182 }; 183 184 cpu5: cpu@10100 { 185 device_type = "cpu"; 186 compatible = "qcom,kryo"; 187 reg = <0x0 0x10100>; 188 enable-method = "psci"; 189 power-domains = <&cpu_pd5>; 190 power-domain-names = "psci"; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 next-level-cache = <&l2_5>; 193 capacity-dmips-mhz = <1024>; 194 #cooling-cells = <2>; 195 dynamic-power-coefficient = <100>; 196 operating-points-v2 = <&cpu4_opp_table>; 197 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 198 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 199 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 200 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 201 l2_5: l2-cache { 202 compatible = "cache"; 203 cache-level = <2>; 204 cache-unified; 205 next-level-cache = <&l3_1>; 206 }; 207 }; 208 209 cpu6: cpu@10200 { 210 device_type = "cpu"; 211 compatible = "qcom,kryo"; 212 reg = <0x0 0x10200>; 213 enable-method = "psci"; 214 power-domains = <&cpu_pd6>; 215 power-domain-names = "psci"; 216 qcom,freq-domain = <&cpufreq_hw 1>; 217 next-level-cache = <&l2_6>; 218 capacity-dmips-mhz = <1024>; 219 #cooling-cells = <2>; 220 dynamic-power-coefficient = <100>; 221 operating-points-v2 = <&cpu4_opp_table>; 222 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 223 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 224 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 225 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 226 l2_6: l2-cache { 227 compatible = "cache"; 228 cache-level = <2>; 229 cache-unified; 230 next-level-cache = <&l3_1>; 231 }; 232 }; 233 234 cpu7: cpu@10300 { 235 device_type = "cpu"; 236 compatible = "qcom,kryo"; 237 reg = <0x0 0x10300>; 238 enable-method = "psci"; 239 power-domains = <&cpu_pd7>; 240 power-domain-names = "psci"; 241 qcom,freq-domain = <&cpufreq_hw 1>; 242 next-level-cache = <&l2_7>; 243 capacity-dmips-mhz = <1024>; 244 #cooling-cells = <2>; 245 dynamic-power-coefficient = <100>; 246 operating-points-v2 = <&cpu4_opp_table>; 247 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 248 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 249 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 250 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 251 l2_7: l2-cache { 252 compatible = "cache"; 253 cache-level = <2>; 254 cache-unified; 255 next-level-cache = <&l3_1>; 256 }; 257 }; 258 259 cpu-map { 260 cluster0 { 261 core0 { 262 cpu = <&cpu0>; 263 }; 264 265 core1 { 266 cpu = <&cpu1>; 267 }; 268 269 core2 { 270 cpu = <&cpu2>; 271 }; 272 273 core3 { 274 cpu = <&cpu3>; 275 }; 276 }; 277 278 cluster1 { 279 core0 { 280 cpu = <&cpu4>; 281 }; 282 283 core1 { 284 cpu = <&cpu5>; 285 }; 286 287 core2 { 288 cpu = <&cpu6>; 289 }; 290 291 core3 { 292 cpu = <&cpu7>; 293 }; 294 }; 295 }; 296 297 idle-states { 298 entry-method = "psci"; 299 300 gold_cpu_sleep_0: cpu-sleep-0 { 301 compatible = "arm,idle-state"; 302 idle-state-name = "gold-power-collapse"; 303 arm,psci-suspend-param = <0x40000003>; 304 entry-latency-us = <549>; 305 exit-latency-us = <901>; 306 min-residency-us = <1774>; 307 local-timer-stop; 308 }; 309 310 gold_rail_cpu_sleep_0: cpu-sleep-1 { 311 compatible = "arm,idle-state"; 312 idle-state-name = "gold-rail-power-collapse"; 313 arm,psci-suspend-param = <0x40000004>; 314 entry-latency-us = <702>; 315 exit-latency-us = <1061>; 316 min-residency-us = <4488>; 317 local-timer-stop; 318 }; 319 }; 320 321 domain-idle-states { 322 cluster_sleep_gold: cluster-sleep-0 { 323 compatible = "domain-idle-state"; 324 arm,psci-suspend-param = <0x41000044>; 325 entry-latency-us = <2752>; 326 exit-latency-us = <3048>; 327 min-residency-us = <6118>; 328 }; 329 330 cluster_sleep_apss_rsc_pc: cluster-sleep-1 { 331 compatible = "domain-idle-state"; 332 arm,psci-suspend-param = <0x42000144>; 333 entry-latency-us = <3263>; 334 exit-latency-us = <6562>; 335 min-residency-us = <9987>; 336 }; 337 }; 338 }; 339 340 cpu0_opp_table: opp-table-cpu0 { 341 compatible = "operating-points-v2"; 342 opp-shared; 343 344 opp-1267200000 { 345 opp-hz = /bits/ 64 <1267200000>; 346 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 347 }; 348 349 opp-1363200000 { 350 opp-hz = /bits/ 64 <1363200000>; 351 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 352 }; 353 354 opp-1459200000 { 355 opp-hz = /bits/ 64 <1459200000>; 356 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 357 }; 358 359 opp-1536000000 { 360 opp-hz = /bits/ 64 <1536000000>; 361 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 362 }; 363 364 opp-1632000000 { 365 opp-hz = /bits/ 64 <1632000000>; 366 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 367 }; 368 369 opp-1708800000 { 370 opp-hz = /bits/ 64 <1708800000>; 371 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 372 }; 373 374 opp-1785600000 { 375 opp-hz = /bits/ 64 <1785600000>; 376 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 377 }; 378 379 opp-1862400000 { 380 opp-hz = /bits/ 64 <1862400000>; 381 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 382 }; 383 384 opp-1939200000 { 385 opp-hz = /bits/ 64 <1939200000>; 386 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 387 }; 388 389 opp-2016000000 { 390 opp-hz = /bits/ 64 <2016000000>; 391 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 392 }; 393 394 opp-2112000000 { 395 opp-hz = /bits/ 64 <2112000000>; 396 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 397 }; 398 399 opp-2188800000 { 400 opp-hz = /bits/ 64 <2188800000>; 401 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 402 }; 403 404 opp-2265600000 { 405 opp-hz = /bits/ 64 <2265600000>; 406 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 407 }; 408 409 opp-2361600000 { 410 opp-hz = /bits/ 64 <2361600000>; 411 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 412 }; 413 414 opp-2457600000 { 415 opp-hz = /bits/ 64 <2457600000>; 416 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 417 }; 418 419 opp-2553600000 { 420 opp-hz = /bits/ 64 <2553600000>; 421 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 422 }; 423 }; 424 425 cpu4_opp_table: opp-table-cpu4 { 426 compatible = "operating-points-v2"; 427 opp-shared; 428 429 opp-1267200000 { 430 opp-hz = /bits/ 64 <1267200000>; 431 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 432 }; 433 434 opp-1363200000 { 435 opp-hz = /bits/ 64 <1363200000>; 436 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 437 }; 438 439 opp-1459200000 { 440 opp-hz = /bits/ 64 <1459200000>; 441 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 442 }; 443 444 opp-1536000000 { 445 opp-hz = /bits/ 64 <1536000000>; 446 opp-peak-kBps = <(1555200 * 4) (921600 * 32)>; 447 }; 448 449 opp-1632000000 { 450 opp-hz = /bits/ 64 <1632000000>; 451 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 452 }; 453 454 opp-1708800000 { 455 opp-hz = /bits/ 64 <1708800000>; 456 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 457 }; 458 459 opp-1785600000 { 460 opp-hz = /bits/ 64 <1785600000>; 461 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 462 }; 463 464 opp-1862400000 { 465 opp-hz = /bits/ 64 <1862400000>; 466 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 467 }; 468 469 opp-1939200000 { 470 opp-hz = /bits/ 64 <1939200000>; 471 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 472 }; 473 474 opp-2016000000 { 475 opp-hz = /bits/ 64 <2016000000>; 476 opp-peak-kBps = <(1708800 * 4) (1228800 * 32)>; 477 }; 478 479 opp-2112000000 { 480 opp-hz = /bits/ 64 <2112000000>; 481 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 482 }; 483 484 opp-2188800000 { 485 opp-hz = /bits/ 64 <2188800000>; 486 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 487 }; 488 489 opp-2265600000 { 490 opp-hz = /bits/ 64 <2265600000>; 491 opp-peak-kBps = <(2092800 * 4) (1555200 * 32)>; 492 }; 493 494 opp-2361600000 { 495 opp-hz = /bits/ 64 <2361600000>; 496 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 497 }; 498 499 opp-2457600000 { 500 opp-hz = /bits/ 64 <2457600000>; 501 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 502 }; 503 504 opp-2553600000 { 505 opp-hz = /bits/ 64 <2553600000>; 506 opp-peak-kBps = <(3196800 * 4) (1708800 * 32)>; 507 }; 508 }; 509 510 dummy-sink { 511 compatible = "arm,coresight-dummy-sink"; 512 513 in-ports { 514 port { 515 eud_in: endpoint { 516 remote-endpoint = 517 <&swao_rep_out1>; 518 }; 519 }; 520 }; 521 }; 522 523 firmware { 524 scm { 525 compatible = "qcom,scm-sa8775p", "qcom,scm"; 526 qcom,dload-mode = <&tcsr 0x13000>; 527 }; 528 }; 529 530 clk_virt: interconnect-clk-virt { 531 compatible = "qcom,sa8775p-clk-virt"; 532 #interconnect-cells = <2>; 533 qcom,bcm-voters = <&apps_bcm_voter>; 534 }; 535 536 mc_virt: interconnect-mc-virt { 537 compatible = "qcom,sa8775p-mc-virt"; 538 #interconnect-cells = <2>; 539 qcom,bcm-voters = <&apps_bcm_voter>; 540 }; 541 542 /* Will be updated by the bootloader. */ 543 memory@80000000 { 544 device_type = "memory"; 545 reg = <0x0 0x80000000 0x0 0x0>; 546 }; 547 548 qup_opp_table_100mhz: opp-table-qup100mhz { 549 compatible = "operating-points-v2"; 550 551 opp-100000000 { 552 opp-hz = /bits/ 64 <100000000>; 553 required-opps = <&rpmhpd_opp_svs_l1>; 554 }; 555 }; 556 557 pmu { 558 compatible = "arm,armv8-pmuv3"; 559 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 560 }; 561 562 psci { 563 compatible = "arm,psci-1.0"; 564 method = "smc"; 565 566 cpu_pd0: power-domain-cpu0 { 567 #power-domain-cells = <0>; 568 power-domains = <&cluster_0_pd>; 569 domain-idle-states = <&gold_cpu_sleep_0>, 570 <&gold_rail_cpu_sleep_0>; 571 }; 572 573 cpu_pd1: power-domain-cpu1 { 574 #power-domain-cells = <0>; 575 power-domains = <&cluster_0_pd>; 576 domain-idle-states = <&gold_cpu_sleep_0>, 577 <&gold_rail_cpu_sleep_0>; 578 }; 579 580 cpu_pd2: power-domain-cpu2 { 581 #power-domain-cells = <0>; 582 power-domains = <&cluster_0_pd>; 583 domain-idle-states = <&gold_cpu_sleep_0>, 584 <&gold_rail_cpu_sleep_0>; 585 }; 586 587 cpu_pd3: power-domain-cpu3 { 588 #power-domain-cells = <0>; 589 power-domains = <&cluster_0_pd>; 590 domain-idle-states = <&gold_cpu_sleep_0>, 591 <&gold_rail_cpu_sleep_0>; 592 }; 593 594 cpu_pd4: power-domain-cpu4 { 595 #power-domain-cells = <0>; 596 power-domains = <&cluster_1_pd>; 597 domain-idle-states = <&gold_cpu_sleep_0>, 598 <&gold_rail_cpu_sleep_0>; 599 }; 600 601 cpu_pd5: power-domain-cpu5 { 602 #power-domain-cells = <0>; 603 power-domains = <&cluster_1_pd>; 604 domain-idle-states = <&gold_cpu_sleep_0>, 605 <&gold_rail_cpu_sleep_0>; 606 }; 607 608 cpu_pd6: power-domain-cpu6 { 609 #power-domain-cells = <0>; 610 power-domains = <&cluster_1_pd>; 611 domain-idle-states = <&gold_cpu_sleep_0>, 612 <&gold_rail_cpu_sleep_0>; 613 }; 614 615 cpu_pd7: power-domain-cpu7 { 616 #power-domain-cells = <0>; 617 power-domains = <&cluster_1_pd>; 618 domain-idle-states = <&gold_cpu_sleep_0>, 619 <&gold_rail_cpu_sleep_0>; 620 }; 621 622 cluster_0_pd: power-domain-cluster0 { 623 #power-domain-cells = <0>; 624 domain-idle-states = <&cluster_sleep_gold>; 625 power-domains = <&system_pd>; 626 }; 627 628 cluster_1_pd: power-domain-cluster1 { 629 #power-domain-cells = <0>; 630 domain-idle-states = <&cluster_sleep_gold>; 631 power-domains = <&system_pd>; 632 }; 633 634 system_pd: power-domain-system { 635 #power-domain-cells = <0>; 636 domain-idle-states = <&cluster_sleep_apss_rsc_pc>; 637 }; 638 }; 639 640 reserved-memory { 641 #address-cells = <2>; 642 #size-cells = <2>; 643 ranges; 644 645 sail_ss_mem: sail-ss@80000000 { 646 reg = <0x0 0x80000000 0x0 0x10000000>; 647 no-map; 648 }; 649 650 hyp_mem: hyp@90000000 { 651 reg = <0x0 0x90000000 0x0 0x600000>; 652 no-map; 653 }; 654 655 xbl_boot_mem: xbl-boot@90600000 { 656 reg = <0x0 0x90600000 0x0 0x200000>; 657 no-map; 658 }; 659 660 aop_image_mem: aop-image@90800000 { 661 reg = <0x0 0x90800000 0x0 0x60000>; 662 no-map; 663 }; 664 665 aop_cmd_db_mem: aop-cmd-db@90860000 { 666 compatible = "qcom,cmd-db"; 667 reg = <0x0 0x90860000 0x0 0x20000>; 668 no-map; 669 }; 670 671 uefi_log: uefi-log@908b0000 { 672 reg = <0x0 0x908b0000 0x0 0x10000>; 673 no-map; 674 }; 675 676 ddr_training_checksum: ddr-training-checksum@908c0000 { 677 reg = <0x0 0x908c0000 0x0 0x1000>; 678 no-map; 679 }; 680 681 reserved_mem: reserved@908f0000 { 682 reg = <0x0 0x908f0000 0x0 0xe000>; 683 no-map; 684 }; 685 686 secdata_apss_mem: secdata-apss@908fe000 { 687 reg = <0x0 0x908fe000 0x0 0x2000>; 688 no-map; 689 }; 690 691 smem_mem: smem@90900000 { 692 compatible = "qcom,smem"; 693 reg = <0x0 0x90900000 0x0 0x200000>; 694 no-map; 695 hwlocks = <&tcsr_mutex 3>; 696 }; 697 698 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { 699 reg = <0x0 0x90c00000 0x0 0x100000>; 700 no-map; 701 }; 702 703 sail_mailbox_mem: sail-ss@90d00000 { 704 reg = <0x0 0x90d00000 0x0 0x100000>; 705 no-map; 706 }; 707 708 sail_ota_mem: sail-ss@90e00000 { 709 reg = <0x0 0x90e00000 0x0 0x300000>; 710 no-map; 711 }; 712 713 gunyah_md_mem: gunyah-md@91a80000 { 714 reg = <0x0 0x91a80000 0x0 0x80000>; 715 no-map; 716 }; 717 718 aoss_backup_mem: aoss-backup@91b00000 { 719 reg = <0x0 0x91b00000 0x0 0x40000>; 720 no-map; 721 }; 722 723 cpucp_backup_mem: cpucp-backup@91b40000 { 724 reg = <0x0 0x91b40000 0x0 0x40000>; 725 no-map; 726 }; 727 728 tz_config_backup_mem: tz-config-backup@91b80000 { 729 reg = <0x0 0x91b80000 0x0 0x10000>; 730 no-map; 731 }; 732 733 ddr_training_data_mem: ddr-training-data@91b90000 { 734 reg = <0x0 0x91b90000 0x0 0x10000>; 735 no-map; 736 }; 737 738 cdt_data_backup_mem: cdt-data-backup@91ba0000 { 739 reg = <0x0 0x91ba0000 0x0 0x1000>; 740 no-map; 741 }; 742 743 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 744 reg = <0x0 0x93b00000 0x0 0xf00000>; 745 no-map; 746 }; 747 748 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 749 reg = <0x0 0x94a00000 0x0 0x800000>; 750 no-map; 751 }; 752 753 pil_camera_mem: pil-camera@95200000 { 754 reg = <0x0 0x95200000 0x0 0x700000>; 755 no-map; 756 }; 757 758 pil_adsp_mem: pil-adsp@95900000 { 759 reg = <0x0 0x95900000 0x0 0x1e00000>; 760 no-map; 761 }; 762 763 q6_adsp_dtb_mem: q6-adsp-dtb@97700000 { 764 reg = <0x0 0x97700000 0x0 0x80000>; 765 no-map; 766 }; 767 768 q6_gdsp0_dtb_mem: q6-gdsp0-dtb@97780000 { 769 reg = <0x0 0x97780000 0x0 0x80000>; 770 no-map; 771 }; 772 773 pil_gdsp0_mem: pil-gdsp0@97800000 { 774 reg = <0x0 0x97800000 0x0 0x1e00000>; 775 no-map; 776 }; 777 778 pil_gdsp1_mem: pil-gdsp1@99600000 { 779 reg = <0x0 0x99600000 0x0 0x1e00000>; 780 no-map; 781 }; 782 783 q6_gdsp1_dtb_mem: q6-gdsp1-dtb@9b400000 { 784 reg = <0x0 0x9b400000 0x0 0x80000>; 785 no-map; 786 }; 787 788 q6_cdsp0_dtb_mem: q6-cdsp0-dtb@9b480000 { 789 reg = <0x0 0x9b480000 0x0 0x80000>; 790 no-map; 791 }; 792 793 pil_cdsp0_mem: pil-cdsp0@9b500000 { 794 reg = <0x0 0x9b500000 0x0 0x1e00000>; 795 no-map; 796 }; 797 798 pil_gpu_mem: pil-gpu@9d300000 { 799 reg = <0x0 0x9d300000 0x0 0x2000>; 800 no-map; 801 }; 802 803 q6_cdsp1_dtb_mem: q6-cdsp1-dtb@9d380000 { 804 reg = <0x0 0x9d380000 0x0 0x80000>; 805 no-map; 806 }; 807 808 pil_cdsp1_mem: pil-cdsp1@9d400000 { 809 reg = <0x0 0x9d400000 0x0 0x1e00000>; 810 no-map; 811 }; 812 813 pil_cvp_mem: pil-cvp@9f200000 { 814 reg = <0x0 0x9f200000 0x0 0x700000>; 815 no-map; 816 }; 817 818 pil_video_mem: pil-video@9f900000 { 819 reg = <0x0 0x9f900000 0x0 0x1000000>; 820 no-map; 821 }; 822 823 firmware_mem: firmware-region@b0000000 { 824 reg = <0x0 0xb0000000 0x0 0x800000>; 825 no-map; 826 }; 827 828 scmi_mem: scmi-region@d0000000 { 829 reg = <0x0 0xd0000000 0x0 0x40000>; 830 no-map; 831 }; 832 833 firmware_logs_mem: firmware-logs@d0040000 { 834 reg = <0x0 0xd0040000 0x0 0x10000>; 835 no-map; 836 }; 837 838 firmware_audio_mem: firmware-audio@d0050000 { 839 reg = <0x0 0xd0050000 0x0 0x4000>; 840 no-map; 841 }; 842 843 firmware_reserved_mem: firmware-reserved@d0054000 { 844 reg = <0x0 0xd0054000 0x0 0x9c000>; 845 no-map; 846 }; 847 848 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { 849 reg = <0x0 0xd00f0000 0x0 0x10000>; 850 no-map; 851 }; 852 853 tags_mem: tags@d0100000 { 854 reg = <0x0 0xd0100000 0x0 0x1200000>; 855 no-map; 856 }; 857 858 qtee_mem: qtee@d1300000 { 859 reg = <0x0 0xd1300000 0x0 0x500000>; 860 no-map; 861 }; 862 863 deepsleep_backup_mem: deepsleep-backup@d1800000 { 864 reg = <0x0 0xd1800000 0x0 0x100000>; 865 no-map; 866 }; 867 868 trusted_apps_mem: trusted-apps@d1900000 { 869 reg = <0x0 0xd1900000 0x0 0x1c00000>; 870 no-map; 871 }; 872 873 tz_stat_mem: tz-stat@db100000 { 874 reg = <0x0 0xdb100000 0x0 0x100000>; 875 no-map; 876 }; 877 878 cpucp_fw_mem: cpucp-fw@db200000 { 879 reg = <0x0 0xdb200000 0x0 0x100000>; 880 no-map; 881 }; 882 }; 883 884 smp2p-adsp { 885 compatible = "qcom,smp2p"; 886 qcom,smem = <443>, <429>; 887 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 888 IPCC_MPROC_SIGNAL_SMP2P 889 IRQ_TYPE_EDGE_RISING>; 890 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 891 892 qcom,local-pid = <0>; 893 qcom,remote-pid = <2>; 894 895 smp2p_adsp_out: master-kernel { 896 qcom,entry-name = "master-kernel"; 897 #qcom,smem-state-cells = <1>; 898 }; 899 900 smp2p_adsp_in: slave-kernel { 901 qcom,entry-name = "slave-kernel"; 902 interrupt-controller; 903 #interrupt-cells = <2>; 904 }; 905 }; 906 907 smp2p-cdsp0 { 908 compatible = "qcom,smp2p"; 909 qcom,smem = <94>, <432>; 910 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 911 IPCC_MPROC_SIGNAL_SMP2P 912 IRQ_TYPE_EDGE_RISING>; 913 mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 914 915 qcom,local-pid = <0>; 916 qcom,remote-pid = <5>; 917 918 smp2p_cdsp0_out: master-kernel { 919 qcom,entry-name = "master-kernel"; 920 #qcom,smem-state-cells = <1>; 921 }; 922 923 smp2p_cdsp0_in: slave-kernel { 924 qcom,entry-name = "slave-kernel"; 925 interrupt-controller; 926 #interrupt-cells = <2>; 927 }; 928 }; 929 930 smp2p-cdsp1 { 931 compatible = "qcom,smp2p"; 932 qcom,smem = <617>, <616>; 933 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 934 IPCC_MPROC_SIGNAL_SMP2P 935 IRQ_TYPE_EDGE_RISING>; 936 mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; 937 938 qcom,local-pid = <0>; 939 qcom,remote-pid = <12>; 940 941 smp2p_cdsp1_out: master-kernel { 942 qcom,entry-name = "master-kernel"; 943 #qcom,smem-state-cells = <1>; 944 }; 945 946 smp2p_cdsp1_in: slave-kernel { 947 qcom,entry-name = "slave-kernel"; 948 interrupt-controller; 949 #interrupt-cells = <2>; 950 }; 951 }; 952 953 smp2p-gpdsp0 { 954 compatible = "qcom,smp2p"; 955 qcom,smem = <617>, <616>; 956 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 957 IPCC_MPROC_SIGNAL_SMP2P 958 IRQ_TYPE_EDGE_RISING>; 959 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; 960 961 qcom,local-pid = <0>; 962 qcom,remote-pid = <17>; 963 964 smp2p_gpdsp0_out: master-kernel { 965 qcom,entry-name = "master-kernel"; 966 #qcom,smem-state-cells = <1>; 967 }; 968 969 smp2p_gpdsp0_in: slave-kernel { 970 qcom,entry-name = "slave-kernel"; 971 interrupt-controller; 972 #interrupt-cells = <2>; 973 }; 974 }; 975 976 smp2p-gpdsp1 { 977 compatible = "qcom,smp2p"; 978 qcom,smem = <617>, <616>; 979 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 980 IPCC_MPROC_SIGNAL_SMP2P 981 IRQ_TYPE_EDGE_RISING>; 982 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>; 983 984 qcom,local-pid = <0>; 985 qcom,remote-pid = <18>; 986 987 smp2p_gpdsp1_out: master-kernel { 988 qcom,entry-name = "master-kernel"; 989 #qcom,smem-state-cells = <1>; 990 }; 991 992 smp2p_gpdsp1_in: slave-kernel { 993 qcom,entry-name = "slave-kernel"; 994 interrupt-controller; 995 #interrupt-cells = <2>; 996 }; 997 }; 998 999 soc: soc@0 { 1000 compatible = "simple-bus"; 1001 #address-cells = <2>; 1002 #size-cells = <2>; 1003 ranges = <0 0 0 0 0x10 0>; 1004 1005 gcc: clock-controller@100000 { 1006 compatible = "qcom,sa8775p-gcc"; 1007 reg = <0x0 0x00100000 0x0 0xc7018>; 1008 #clock-cells = <1>; 1009 #reset-cells = <1>; 1010 #power-domain-cells = <1>; 1011 clocks = <&rpmhcc RPMH_CXO_CLK>, 1012 <&sleep_clk>, 1013 <0>, 1014 <0>, 1015 <0>, 1016 <&usb_0_qmpphy>, 1017 <&usb_1_qmpphy>, 1018 <0>, 1019 <0>, 1020 <0>, 1021 <&pcie0_phy>, 1022 <&pcie1_phy>, 1023 <0>, 1024 <0>, 1025 <0>; 1026 power-domains = <&rpmhpd SA8775P_CX>; 1027 }; 1028 1029 ipcc: mailbox@408000 { 1030 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 1031 reg = <0x0 0x00408000 0x0 0x1000>; 1032 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1033 interrupt-controller; 1034 #interrupt-cells = <3>; 1035 #mbox-cells = <2>; 1036 }; 1037 1038 qfprom: efuse@784000 { 1039 compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; 1040 reg = <0x0 0x00784000 0x0 0x3000>; 1041 #address-cells = <1>; 1042 #size-cells = <1>; 1043 1044 gpu_speed_bin: gpu_speed_bin@240c { 1045 reg = <0x240c 0x1>; 1046 bits = <0 8>; 1047 }; 1048 }; 1049 1050 gpi_dma2: dma-controller@800000 { 1051 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1052 reg = <0x0 0x00800000 0x0 0x60000>; 1053 #dma-cells = <3>; 1054 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1066 dma-channels = <12>; 1067 dma-channel-mask = <0xfff>; 1068 iommus = <&apps_smmu 0x5b6 0x0>; 1069 status = "disabled"; 1070 }; 1071 1072 qupv3_id_2: geniqup@8c0000 { 1073 compatible = "qcom,geni-se-qup"; 1074 reg = <0x0 0x008c0000 0x0 0x6000>; 1075 ranges; 1076 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1077 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1078 clock-names = "m-ahb", "s-ahb"; 1079 iommus = <&apps_smmu 0x5a3 0x0>; 1080 #address-cells = <2>; 1081 #size-cells = <2>; 1082 status = "disabled"; 1083 1084 i2c14: i2c@880000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0x0 0x880000 0x0 0x4000>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1091 clock-names = "se"; 1092 pinctrl-0 = <&qup_i2c14_default>; 1093 pinctrl-names = "default"; 1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1095 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1096 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1097 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1098 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1099 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1100 interconnect-names = "qup-core", 1101 "qup-config", 1102 "qup-memory"; 1103 power-domains = <&rpmhpd SA8775P_CX>; 1104 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1105 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1106 dma-names = "tx", 1107 "rx"; 1108 status = "disabled"; 1109 }; 1110 1111 spi14: spi@880000 { 1112 compatible = "qcom,geni-spi"; 1113 reg = <0x0 0x880000 0x0 0x4000>; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1118 clock-names = "se"; 1119 pinctrl-0 = <&qup_spi14_default>; 1120 pinctrl-names = "default"; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1122 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1123 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1124 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1125 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1126 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1127 interconnect-names = "qup-core", 1128 "qup-config", 1129 "qup-memory"; 1130 power-domains = <&rpmhpd SA8775P_CX>; 1131 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1132 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1133 dma-names = "tx", 1134 "rx"; 1135 status = "disabled"; 1136 }; 1137 1138 uart14: serial@880000 { 1139 compatible = "qcom,geni-uart"; 1140 reg = <0x0 0x00880000 0x0 0x4000>; 1141 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1142 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1143 clock-names = "se"; 1144 pinctrl-0 = <&qup_uart14_default>; 1145 pinctrl-names = "default"; 1146 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1147 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1148 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1149 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1150 interconnect-names = "qup-core", "qup-config"; 1151 power-domains = <&rpmhpd SA8775P_CX>; 1152 status = "disabled"; 1153 }; 1154 1155 i2c15: i2c@884000 { 1156 compatible = "qcom,geni-i2c"; 1157 reg = <0x0 0x884000 0x0 0x4000>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1162 clock-names = "se"; 1163 pinctrl-0 = <&qup_i2c15_default>; 1164 pinctrl-names = "default"; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1166 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1167 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1168 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1169 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1170 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1171 interconnect-names = "qup-core", 1172 "qup-config", 1173 "qup-memory"; 1174 power-domains = <&rpmhpd SA8775P_CX>; 1175 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1176 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1177 dma-names = "tx", 1178 "rx"; 1179 status = "disabled"; 1180 }; 1181 1182 spi15: spi@884000 { 1183 compatible = "qcom,geni-spi"; 1184 reg = <0x0 0x884000 0x0 0x4000>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1188 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1189 clock-names = "se"; 1190 pinctrl-0 = <&qup_spi15_default>; 1191 pinctrl-names = "default"; 1192 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1193 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1194 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1195 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1196 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1197 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1198 interconnect-names = "qup-core", 1199 "qup-config", 1200 "qup-memory"; 1201 power-domains = <&rpmhpd SA8775P_CX>; 1202 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1203 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1204 dma-names = "tx", 1205 "rx"; 1206 status = "disabled"; 1207 }; 1208 1209 uart15: serial@884000 { 1210 compatible = "qcom,geni-uart"; 1211 reg = <0x0 0x00884000 0x0 0x4000>; 1212 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1213 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1214 clock-names = "se"; 1215 pinctrl-0 = <&qup_uart15_default>; 1216 pinctrl-names = "default"; 1217 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1218 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1219 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1220 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1221 interconnect-names = "qup-core", "qup-config"; 1222 power-domains = <&rpmhpd SA8775P_CX>; 1223 status = "disabled"; 1224 }; 1225 1226 i2c16: i2c@888000 { 1227 compatible = "qcom,geni-i2c"; 1228 reg = <0x0 0x888000 0x0 0x4000>; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1232 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1233 clock-names = "se"; 1234 pinctrl-0 = <&qup_i2c16_default>; 1235 pinctrl-names = "default"; 1236 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1237 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1238 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1239 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1240 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1241 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1242 interconnect-names = "qup-core", 1243 "qup-config", 1244 "qup-memory"; 1245 power-domains = <&rpmhpd SA8775P_CX>; 1246 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1247 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1248 dma-names = "tx", 1249 "rx"; 1250 status = "disabled"; 1251 }; 1252 1253 spi16: spi@888000 { 1254 compatible = "qcom,geni-spi"; 1255 reg = <0x0 0x00888000 0x0 0x4000>; 1256 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1257 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1258 clock-names = "se"; 1259 pinctrl-0 = <&qup_spi16_default>; 1260 pinctrl-names = "default"; 1261 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1262 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1263 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1264 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1265 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1266 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1267 interconnect-names = "qup-core", 1268 "qup-config", 1269 "qup-memory"; 1270 power-domains = <&rpmhpd SA8775P_CX>; 1271 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1272 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1273 dma-names = "tx", 1274 "rx"; 1275 #address-cells = <1>; 1276 #size-cells = <0>; 1277 status = "disabled"; 1278 }; 1279 1280 uart16: serial@888000 { 1281 compatible = "qcom,geni-uart"; 1282 reg = <0x0 0x00888000 0x0 0x4000>; 1283 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1284 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1285 clock-names = "se"; 1286 pinctrl-0 = <&qup_uart16_default>; 1287 pinctrl-names = "default"; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1289 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1290 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1291 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1292 interconnect-names = "qup-core", "qup-config"; 1293 power-domains = <&rpmhpd SA8775P_CX>; 1294 status = "disabled"; 1295 }; 1296 1297 i2c17: i2c@88c000 { 1298 compatible = "qcom,geni-i2c"; 1299 reg = <0x0 0x88c000 0x0 0x4000>; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1304 clock-names = "se"; 1305 pinctrl-0 = <&qup_i2c17_default>; 1306 pinctrl-names = "default"; 1307 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1308 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1309 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1310 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1311 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1313 interconnect-names = "qup-core", 1314 "qup-config", 1315 "qup-memory"; 1316 power-domains = <&rpmhpd SA8775P_CX>; 1317 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1318 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1319 dma-names = "tx", 1320 "rx"; 1321 status = "disabled"; 1322 }; 1323 1324 spi17: spi@88c000 { 1325 compatible = "qcom,geni-spi"; 1326 reg = <0x0 0x88c000 0x0 0x4000>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1330 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1331 clock-names = "se"; 1332 pinctrl-0 = <&qup_spi17_default>; 1333 pinctrl-names = "default"; 1334 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1335 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1336 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1337 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1338 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1339 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1340 interconnect-names = "qup-core", 1341 "qup-config", 1342 "qup-memory"; 1343 power-domains = <&rpmhpd SA8775P_CX>; 1344 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1345 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1346 dma-names = "tx", 1347 "rx"; 1348 status = "disabled"; 1349 }; 1350 1351 uart17: serial@88c000 { 1352 compatible = "qcom,geni-uart"; 1353 reg = <0x0 0x0088c000 0x0 0x4000>; 1354 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1355 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1356 clock-names = "se"; 1357 pinctrl-0 = <&qup_uart17_default>; 1358 pinctrl-names = "default"; 1359 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1360 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1361 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1362 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1363 interconnect-names = "qup-core", "qup-config"; 1364 power-domains = <&rpmhpd SA8775P_CX>; 1365 status = "disabled"; 1366 }; 1367 1368 i2c18: i2c@890000 { 1369 compatible = "qcom,geni-i2c"; 1370 reg = <0x0 0x00890000 0x0 0x4000>; 1371 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1372 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1373 clock-names = "se"; 1374 pinctrl-0 = <&qup_i2c18_default>; 1375 pinctrl-names = "default"; 1376 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1377 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1378 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1379 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1380 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1381 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1382 interconnect-names = "qup-core", 1383 "qup-config", 1384 "qup-memory"; 1385 power-domains = <&rpmhpd SA8775P_CX>; 1386 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1387 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1388 dma-names = "tx", 1389 "rx"; 1390 #address-cells = <1>; 1391 #size-cells = <0>; 1392 status = "disabled"; 1393 }; 1394 1395 spi18: spi@890000 { 1396 compatible = "qcom,geni-spi"; 1397 reg = <0x0 0x890000 0x0 0x4000>; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1401 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1402 clock-names = "se"; 1403 pinctrl-0 = <&qup_spi18_default>; 1404 pinctrl-names = "default"; 1405 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1406 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1407 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1408 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1409 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1410 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1411 interconnect-names = "qup-core", 1412 "qup-config", 1413 "qup-memory"; 1414 power-domains = <&rpmhpd SA8775P_CX>; 1415 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1416 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1417 dma-names = "tx", 1418 "rx"; 1419 status = "disabled"; 1420 }; 1421 1422 uart18: serial@890000 { 1423 compatible = "qcom,geni-uart"; 1424 reg = <0x0 0x00890000 0x0 0x4000>; 1425 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1426 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1427 clock-names = "se"; 1428 pinctrl-0 = <&qup_uart18_default>; 1429 pinctrl-names = "default"; 1430 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1431 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1432 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1433 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1434 interconnect-names = "qup-core", "qup-config"; 1435 power-domains = <&rpmhpd SA8775P_CX>; 1436 status = "disabled"; 1437 }; 1438 1439 i2c19: i2c@894000 { 1440 compatible = "qcom,geni-i2c"; 1441 reg = <0x0 0x894000 0x0 0x4000>; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1445 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1446 clock-names = "se"; 1447 pinctrl-0 = <&qup_i2c19_default>; 1448 pinctrl-names = "default"; 1449 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1450 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1451 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1452 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1453 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1454 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1455 interconnect-names = "qup-core", 1456 "qup-config", 1457 "qup-memory"; 1458 power-domains = <&rpmhpd SA8775P_CX>; 1459 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1460 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1461 dma-names = "tx", 1462 "rx"; 1463 status = "disabled"; 1464 }; 1465 1466 spi19: spi@894000 { 1467 compatible = "qcom,geni-spi"; 1468 reg = <0x0 0x894000 0x0 0x4000>; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1472 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1473 clock-names = "se"; 1474 pinctrl-0 = <&qup_spi19_default>; 1475 pinctrl-names = "default"; 1476 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1477 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1478 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1479 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1480 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1481 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1482 interconnect-names = "qup-core", 1483 "qup-config", 1484 "qup-memory"; 1485 power-domains = <&rpmhpd SA8775P_CX>; 1486 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1487 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1488 dma-names = "tx", 1489 "rx"; 1490 status = "disabled"; 1491 }; 1492 1493 uart19: serial@894000 { 1494 compatible = "qcom,geni-uart"; 1495 reg = <0x0 0x00894000 0x0 0x4000>; 1496 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1497 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1498 clock-names = "se"; 1499 pinctrl-0 = <&qup_uart19_default>; 1500 pinctrl-names = "default"; 1501 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1502 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1503 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1504 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1505 interconnect-names = "qup-core", "qup-config"; 1506 power-domains = <&rpmhpd SA8775P_CX>; 1507 status = "disabled"; 1508 }; 1509 1510 i2c20: i2c@898000 { 1511 compatible = "qcom,geni-i2c"; 1512 reg = <0x0 0x898000 0x0 0x4000>; 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1516 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1517 clock-names = "se"; 1518 pinctrl-0 = <&qup_i2c20_default>; 1519 pinctrl-names = "default"; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1521 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1522 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1523 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1524 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1525 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1526 interconnect-names = "qup-core", 1527 "qup-config", 1528 "qup-memory"; 1529 power-domains = <&rpmhpd SA8775P_CX>; 1530 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1531 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1532 dma-names = "tx", 1533 "rx"; 1534 status = "disabled"; 1535 }; 1536 1537 spi20: spi@898000 { 1538 compatible = "qcom,geni-spi"; 1539 reg = <0x0 0x898000 0x0 0x4000>; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1543 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1544 clock-names = "se"; 1545 pinctrl-0 = <&qup_spi20_default>; 1546 pinctrl-names = "default"; 1547 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1548 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1549 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1550 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1551 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1552 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1553 interconnect-names = "qup-core", 1554 "qup-config", 1555 "qup-memory"; 1556 power-domains = <&rpmhpd SA8775P_CX>; 1557 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1558 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1559 dma-names = "tx", 1560 "rx"; 1561 status = "disabled"; 1562 }; 1563 1564 uart20: serial@898000 { 1565 compatible = "qcom,geni-uart"; 1566 reg = <0x0 0x00898000 0x0 0x4000>; 1567 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1568 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1569 clock-names = "se"; 1570 pinctrl-0 = <&qup_uart20_default>; 1571 pinctrl-names = "default"; 1572 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1573 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1574 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1575 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1576 interconnect-names = "qup-core", "qup-config"; 1577 power-domains = <&rpmhpd SA8775P_CX>; 1578 status = "disabled"; 1579 }; 1580 1581 }; 1582 1583 gpi_dma0: dma-controller@900000 { 1584 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1585 reg = <0x0 0x00900000 0x0 0x60000>; 1586 #dma-cells = <3>; 1587 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1599 dma-channels = <12>; 1600 dma-channel-mask = <0xfff>; 1601 iommus = <&apps_smmu 0x416 0x0>; 1602 status = "disabled"; 1603 }; 1604 1605 qupv3_id_0: geniqup@9c0000 { 1606 compatible = "qcom,geni-se-qup"; 1607 reg = <0x0 0x9c0000 0x0 0x6000>; 1608 #address-cells = <2>; 1609 #size-cells = <2>; 1610 ranges; 1611 clock-names = "m-ahb", "s-ahb"; 1612 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1613 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1614 iommus = <&apps_smmu 0x403 0x0>; 1615 status = "disabled"; 1616 1617 i2c0: i2c@980000 { 1618 compatible = "qcom,geni-i2c"; 1619 reg = <0x0 0x980000 0x0 0x4000>; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1624 clock-names = "se"; 1625 pinctrl-0 = <&qup_i2c0_default>; 1626 pinctrl-names = "default"; 1627 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1628 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1629 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1630 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1631 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1632 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1633 interconnect-names = "qup-core", 1634 "qup-config", 1635 "qup-memory"; 1636 power-domains = <&rpmhpd SA8775P_CX>; 1637 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1638 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1639 dma-names = "tx", 1640 "rx"; 1641 status = "disabled"; 1642 }; 1643 1644 spi0: spi@980000 { 1645 compatible = "qcom,geni-spi"; 1646 reg = <0x0 0x980000 0x0 0x4000>; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1650 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1651 clock-names = "se"; 1652 pinctrl-0 = <&qup_spi0_default>; 1653 pinctrl-names = "default"; 1654 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1655 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1656 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1657 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1658 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1659 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1660 interconnect-names = "qup-core", 1661 "qup-config", 1662 "qup-memory"; 1663 power-domains = <&rpmhpd SA8775P_CX>; 1664 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1665 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1666 dma-names = "tx", 1667 "rx"; 1668 status = "disabled"; 1669 }; 1670 1671 uart0: serial@980000 { 1672 compatible = "qcom,geni-uart"; 1673 reg = <0x0 0x980000 0x0 0x4000>; 1674 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1675 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1676 clock-names = "se"; 1677 pinctrl-0 = <&qup_uart0_default>; 1678 pinctrl-names = "default"; 1679 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1680 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1681 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1682 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1683 interconnect-names = "qup-core", "qup-config"; 1684 power-domains = <&rpmhpd SA8775P_CX>; 1685 status = "disabled"; 1686 }; 1687 1688 i2c1: i2c@984000 { 1689 compatible = "qcom,geni-i2c"; 1690 reg = <0x0 0x984000 0x0 0x4000>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1694 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1695 clock-names = "se"; 1696 pinctrl-0 = <&qup_i2c1_default>; 1697 pinctrl-names = "default"; 1698 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1699 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1700 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1701 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1702 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1703 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1704 interconnect-names = "qup-core", 1705 "qup-config", 1706 "qup-memory"; 1707 power-domains = <&rpmhpd SA8775P_CX>; 1708 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1709 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1710 dma-names = "tx", 1711 "rx"; 1712 status = "disabled"; 1713 }; 1714 1715 spi1: spi@984000 { 1716 compatible = "qcom,geni-spi"; 1717 reg = <0x0 0x984000 0x0 0x4000>; 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1721 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1722 clock-names = "se"; 1723 pinctrl-0 = <&qup_spi1_default>; 1724 pinctrl-names = "default"; 1725 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1726 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1727 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1728 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1729 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1730 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1731 interconnect-names = "qup-core", 1732 "qup-config", 1733 "qup-memory"; 1734 power-domains = <&rpmhpd SA8775P_CX>; 1735 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1736 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1737 dma-names = "tx", 1738 "rx"; 1739 status = "disabled"; 1740 }; 1741 1742 uart1: serial@984000 { 1743 compatible = "qcom,geni-uart"; 1744 reg = <0x0 0x984000 0x0 0x4000>; 1745 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1746 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1747 clock-names = "se"; 1748 pinctrl-0 = <&qup_uart1_default>; 1749 pinctrl-names = "default"; 1750 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1751 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1752 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1753 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1754 interconnect-names = "qup-core", "qup-config"; 1755 power-domains = <&rpmhpd SA8775P_CX>; 1756 status = "disabled"; 1757 }; 1758 1759 i2c2: i2c@988000 { 1760 compatible = "qcom,geni-i2c"; 1761 reg = <0x0 0x988000 0x0 0x4000>; 1762 #address-cells = <1>; 1763 #size-cells = <0>; 1764 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1765 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1766 clock-names = "se"; 1767 pinctrl-0 = <&qup_i2c2_default>; 1768 pinctrl-names = "default"; 1769 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1770 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1771 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1772 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1773 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1774 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1775 interconnect-names = "qup-core", 1776 "qup-config", 1777 "qup-memory"; 1778 power-domains = <&rpmhpd SA8775P_CX>; 1779 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1780 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1781 dma-names = "tx", 1782 "rx"; 1783 status = "disabled"; 1784 }; 1785 1786 spi2: spi@988000 { 1787 compatible = "qcom,geni-spi"; 1788 reg = <0x0 0x988000 0x0 0x4000>; 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1792 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1793 clock-names = "se"; 1794 pinctrl-0 = <&qup_spi2_default>; 1795 pinctrl-names = "default"; 1796 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1797 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1798 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1799 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1800 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1801 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1802 interconnect-names = "qup-core", 1803 "qup-config", 1804 "qup-memory"; 1805 power-domains = <&rpmhpd SA8775P_CX>; 1806 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1807 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1808 dma-names = "tx", 1809 "rx"; 1810 status = "disabled"; 1811 }; 1812 1813 uart2: serial@988000 { 1814 compatible = "qcom,geni-uart"; 1815 reg = <0x0 0x988000 0x0 0x4000>; 1816 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1817 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1818 clock-names = "se"; 1819 pinctrl-0 = <&qup_uart2_default>; 1820 pinctrl-names = "default"; 1821 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1822 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1823 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1824 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1825 interconnect-names = "qup-core", "qup-config"; 1826 power-domains = <&rpmhpd SA8775P_CX>; 1827 status = "disabled"; 1828 }; 1829 1830 i2c3: i2c@98c000 { 1831 compatible = "qcom,geni-i2c"; 1832 reg = <0x0 0x98c000 0x0 0x4000>; 1833 #address-cells = <1>; 1834 #size-cells = <0>; 1835 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1836 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1837 clock-names = "se"; 1838 pinctrl-0 = <&qup_i2c3_default>; 1839 pinctrl-names = "default"; 1840 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1841 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1842 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1843 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1844 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1845 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1846 interconnect-names = "qup-core", 1847 "qup-config", 1848 "qup-memory"; 1849 power-domains = <&rpmhpd SA8775P_CX>; 1850 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1851 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1852 dma-names = "tx", 1853 "rx"; 1854 status = "disabled"; 1855 }; 1856 1857 spi3: spi@98c000 { 1858 compatible = "qcom,geni-spi"; 1859 reg = <0x0 0x98c000 0x0 0x4000>; 1860 #address-cells = <1>; 1861 #size-cells = <0>; 1862 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1863 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1864 clock-names = "se"; 1865 pinctrl-0 = <&qup_spi3_default>; 1866 pinctrl-names = "default"; 1867 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1868 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1869 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1870 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1871 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1872 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1873 interconnect-names = "qup-core", 1874 "qup-config", 1875 "qup-memory"; 1876 power-domains = <&rpmhpd SA8775P_CX>; 1877 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1878 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1879 dma-names = "tx", 1880 "rx"; 1881 status = "disabled"; 1882 }; 1883 1884 uart3: serial@98c000 { 1885 compatible = "qcom,geni-uart"; 1886 reg = <0x0 0x98c000 0x0 0x4000>; 1887 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1888 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1889 clock-names = "se"; 1890 pinctrl-0 = <&qup_uart3_default>; 1891 pinctrl-names = "default"; 1892 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1893 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1894 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1895 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1896 interconnect-names = "qup-core", "qup-config"; 1897 power-domains = <&rpmhpd SA8775P_CX>; 1898 status = "disabled"; 1899 }; 1900 1901 i2c4: i2c@990000 { 1902 compatible = "qcom,geni-i2c"; 1903 reg = <0x0 0x990000 0x0 0x4000>; 1904 #address-cells = <1>; 1905 #size-cells = <0>; 1906 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1907 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1908 clock-names = "se"; 1909 pinctrl-0 = <&qup_i2c4_default>; 1910 pinctrl-names = "default"; 1911 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1912 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1913 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1914 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1915 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1916 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1917 interconnect-names = "qup-core", 1918 "qup-config", 1919 "qup-memory"; 1920 power-domains = <&rpmhpd SA8775P_CX>; 1921 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1922 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1923 dma-names = "tx", 1924 "rx"; 1925 status = "disabled"; 1926 }; 1927 1928 spi4: spi@990000 { 1929 compatible = "qcom,geni-spi"; 1930 reg = <0x0 0x990000 0x0 0x4000>; 1931 #address-cells = <1>; 1932 #size-cells = <0>; 1933 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1934 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1935 clock-names = "se"; 1936 pinctrl-0 = <&qup_spi4_default>; 1937 pinctrl-names = "default"; 1938 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1939 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1940 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1941 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1942 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1943 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1944 interconnect-names = "qup-core", 1945 "qup-config", 1946 "qup-memory"; 1947 power-domains = <&rpmhpd SA8775P_CX>; 1948 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1949 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1950 dma-names = "tx", 1951 "rx"; 1952 status = "disabled"; 1953 }; 1954 1955 uart4: serial@990000 { 1956 compatible = "qcom,geni-uart"; 1957 reg = <0x0 0x990000 0x0 0x4000>; 1958 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1959 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1960 clock-names = "se"; 1961 pinctrl-0 = <&qup_uart4_default>; 1962 pinctrl-names = "default"; 1963 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1964 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1965 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1966 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1967 interconnect-names = "qup-core", "qup-config"; 1968 power-domains = <&rpmhpd SA8775P_CX>; 1969 status = "disabled"; 1970 }; 1971 1972 i2c5: i2c@994000 { 1973 compatible = "qcom,geni-i2c"; 1974 reg = <0x0 0x994000 0x0 0x4000>; 1975 #address-cells = <1>; 1976 #size-cells = <0>; 1977 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1978 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1979 clock-names = "se"; 1980 pinctrl-0 = <&qup_i2c5_default>; 1981 pinctrl-names = "default"; 1982 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1983 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1984 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1985 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1986 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1987 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1988 interconnect-names = "qup-core", 1989 "qup-config", 1990 "qup-memory"; 1991 power-domains = <&rpmhpd SA8775P_CX>; 1992 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1993 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1994 dma-names = "tx", 1995 "rx"; 1996 status = "disabled"; 1997 }; 1998 1999 spi5: spi@994000 { 2000 compatible = "qcom,geni-spi"; 2001 reg = <0x0 0x994000 0x0 0x4000>; 2002 #address-cells = <1>; 2003 #size-cells = <0>; 2004 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2005 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2006 clock-names = "se"; 2007 pinctrl-0 = <&qup_spi5_default>; 2008 pinctrl-names = "default"; 2009 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2010 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2011 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2012 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2013 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2014 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2015 interconnect-names = "qup-core", 2016 "qup-config", 2017 "qup-memory"; 2018 power-domains = <&rpmhpd SA8775P_CX>; 2019 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2020 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2021 dma-names = "tx", 2022 "rx"; 2023 status = "disabled"; 2024 }; 2025 2026 uart5: serial@994000 { 2027 compatible = "qcom,geni-uart"; 2028 reg = <0x0 0x994000 0x0 0x4000>; 2029 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 2030 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2031 clock-names = "se"; 2032 pinctrl-0 = <&qup_uart5_default>; 2033 pinctrl-names = "default"; 2034 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2035 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2036 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2037 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2038 interconnect-names = "qup-core", "qup-config"; 2039 power-domains = <&rpmhpd SA8775P_CX>; 2040 status = "disabled"; 2041 }; 2042 }; 2043 2044 gpi_dma1: dma-controller@a00000 { 2045 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2046 reg = <0x0 0x00a00000 0x0 0x60000>; 2047 #dma-cells = <3>; 2048 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 2052 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 2053 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 2054 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 2055 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2060 iommus = <&apps_smmu 0x456 0x0>; 2061 dma-channels = <12>; 2062 dma-channel-mask = <0xfff>; 2063 status = "disabled"; 2064 }; 2065 2066 qupv3_id_1: geniqup@ac0000 { 2067 compatible = "qcom,geni-se-qup"; 2068 reg = <0x0 0x00ac0000 0x0 0x6000>; 2069 #address-cells = <2>; 2070 #size-cells = <2>; 2071 ranges; 2072 clock-names = "m-ahb", "s-ahb"; 2073 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 2074 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 2075 iommus = <&apps_smmu 0x443 0x0>; 2076 status = "disabled"; 2077 2078 i2c7: i2c@a80000 { 2079 compatible = "qcom,geni-i2c"; 2080 reg = <0x0 0xa80000 0x0 0x4000>; 2081 #address-cells = <1>; 2082 #size-cells = <0>; 2083 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2084 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2085 clock-names = "se"; 2086 pinctrl-0 = <&qup_i2c7_default>; 2087 pinctrl-names = "default"; 2088 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2089 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2090 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2091 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2092 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2093 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2094 interconnect-names = "qup-core", 2095 "qup-config", 2096 "qup-memory"; 2097 power-domains = <&rpmhpd SA8775P_CX>; 2098 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 2099 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 2100 dma-names = "tx", 2101 "rx"; 2102 status = "disabled"; 2103 }; 2104 2105 spi7: spi@a80000 { 2106 compatible = "qcom,geni-spi"; 2107 reg = <0x0 0xa80000 0x0 0x4000>; 2108 #address-cells = <1>; 2109 #size-cells = <0>; 2110 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2111 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2112 clock-names = "se"; 2113 pinctrl-0 = <&qup_spi7_default>; 2114 pinctrl-names = "default"; 2115 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2116 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2117 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2118 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2119 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2120 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2121 interconnect-names = "qup-core", 2122 "qup-config", 2123 "qup-memory"; 2124 power-domains = <&rpmhpd SA8775P_CX>; 2125 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 2126 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 2127 dma-names = "tx", 2128 "rx"; 2129 status = "disabled"; 2130 }; 2131 2132 uart7: serial@a80000 { 2133 compatible = "qcom,geni-uart"; 2134 reg = <0x0 0x00a80000 0x0 0x4000>; 2135 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2136 clock-names = "se"; 2137 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 2138 pinctrl-0 = <&qup_uart7_default>; 2139 pinctrl-names = "default"; 2140 interconnect-names = "qup-core", "qup-config"; 2141 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2142 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2143 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2144 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2145 power-domains = <&rpmhpd SA8775P_CX>; 2146 operating-points-v2 = <&qup_opp_table_100mhz>; 2147 status = "disabled"; 2148 }; 2149 2150 i2c8: i2c@a84000 { 2151 compatible = "qcom,geni-i2c"; 2152 reg = <0x0 0xa84000 0x0 0x4000>; 2153 #address-cells = <1>; 2154 #size-cells = <0>; 2155 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2156 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2157 clock-names = "se"; 2158 pinctrl-0 = <&qup_i2c8_default>; 2159 pinctrl-names = "default"; 2160 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2161 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2162 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2163 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2164 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2165 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2166 interconnect-names = "qup-core", 2167 "qup-config", 2168 "qup-memory"; 2169 power-domains = <&rpmhpd SA8775P_CX>; 2170 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 2171 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 2172 dma-names = "tx", 2173 "rx"; 2174 status = "disabled"; 2175 }; 2176 2177 spi8: spi@a84000 { 2178 compatible = "qcom,geni-spi"; 2179 reg = <0x0 0xa84000 0x0 0x4000>; 2180 #address-cells = <1>; 2181 #size-cells = <0>; 2182 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2183 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2184 clock-names = "se"; 2185 pinctrl-0 = <&qup_spi8_default>; 2186 pinctrl-names = "default"; 2187 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2188 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2189 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2190 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2191 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2193 interconnect-names = "qup-core", 2194 "qup-config", 2195 "qup-memory"; 2196 power-domains = <&rpmhpd SA8775P_CX>; 2197 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 2198 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 2199 dma-names = "tx", 2200 "rx"; 2201 status = "disabled"; 2202 }; 2203 2204 uart8: serial@a84000 { 2205 compatible = "qcom,geni-uart"; 2206 reg = <0x0 0x00a84000 0x0 0x4000>; 2207 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2208 clock-names = "se"; 2209 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 2210 pinctrl-0 = <&qup_uart8_default>; 2211 pinctrl-names = "default"; 2212 interconnect-names = "qup-core", "qup-config"; 2213 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2214 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2215 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2216 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2217 power-domains = <&rpmhpd SA8775P_CX>; 2218 operating-points-v2 = <&qup_opp_table_100mhz>; 2219 status = "disabled"; 2220 }; 2221 2222 i2c9: i2c@a88000 { 2223 compatible = "qcom,geni-i2c"; 2224 reg = <0x0 0xa88000 0x0 0x4000>; 2225 #address-cells = <1>; 2226 #size-cells = <0>; 2227 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2228 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2229 clock-names = "se"; 2230 pinctrl-0 = <&qup_i2c9_default>; 2231 pinctrl-names = "default"; 2232 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2233 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2234 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2235 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2236 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2237 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2238 interconnect-names = "qup-core", 2239 "qup-config", 2240 "qup-memory"; 2241 power-domains = <&rpmhpd SA8775P_CX>; 2242 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 2243 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 2244 dma-names = "tx", 2245 "rx"; 2246 status = "disabled"; 2247 }; 2248 2249 spi9: spi@a88000 { 2250 compatible = "qcom,geni-spi"; 2251 reg = <0x0 0xa88000 0x0 0x4000>; 2252 #address-cells = <1>; 2253 #size-cells = <0>; 2254 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2255 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2256 clock-names = "se"; 2257 pinctrl-0 = <&qup_spi9_default>; 2258 pinctrl-names = "default"; 2259 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2260 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2261 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2262 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2263 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2264 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2265 interconnect-names = "qup-core", 2266 "qup-config", 2267 "qup-memory"; 2268 power-domains = <&rpmhpd SA8775P_CX>; 2269 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 2270 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 2271 dma-names = "tx", 2272 "rx"; 2273 status = "disabled"; 2274 }; 2275 2276 uart9: serial@a88000 { 2277 compatible = "qcom,geni-uart"; 2278 reg = <0x0 0xa88000 0x0 0x4000>; 2279 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2280 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2281 clock-names = "se"; 2282 pinctrl-0 = <&qup_uart9_default>; 2283 pinctrl-names = "default"; 2284 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2285 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2286 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2287 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2288 interconnect-names = "qup-core", "qup-config"; 2289 power-domains = <&rpmhpd SA8775P_CX>; 2290 status = "disabled"; 2291 }; 2292 2293 i2c10: i2c@a8c000 { 2294 compatible = "qcom,geni-i2c"; 2295 reg = <0x0 0xa8c000 0x0 0x4000>; 2296 #address-cells = <1>; 2297 #size-cells = <0>; 2298 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2299 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2300 clock-names = "se"; 2301 pinctrl-0 = <&qup_i2c10_default>; 2302 pinctrl-names = "default"; 2303 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2304 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2305 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2306 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2307 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2308 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2309 interconnect-names = "qup-core", 2310 "qup-config", 2311 "qup-memory"; 2312 power-domains = <&rpmhpd SA8775P_CX>; 2313 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 2314 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 2315 dma-names = "tx", 2316 "rx"; 2317 status = "disabled"; 2318 }; 2319 2320 spi10: spi@a8c000 { 2321 compatible = "qcom,geni-spi"; 2322 reg = <0x0 0xa8c000 0x0 0x4000>; 2323 #address-cells = <1>; 2324 #size-cells = <0>; 2325 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2326 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2327 clock-names = "se"; 2328 pinctrl-0 = <&qup_spi10_default>; 2329 pinctrl-names = "default"; 2330 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2331 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2332 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2333 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2334 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2335 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2336 interconnect-names = "qup-core", 2337 "qup-config", 2338 "qup-memory"; 2339 power-domains = <&rpmhpd SA8775P_CX>; 2340 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 2341 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 2342 dma-names = "tx", 2343 "rx"; 2344 status = "disabled"; 2345 }; 2346 2347 uart10: serial@a8c000 { 2348 compatible = "qcom,geni-uart"; 2349 reg = <0x0 0x00a8c000 0x0 0x4000>; 2350 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2351 clock-names = "se"; 2352 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2353 pinctrl-0 = <&qup_uart10_default>; 2354 pinctrl-names = "default"; 2355 interconnect-names = "qup-core", "qup-config"; 2356 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 2357 &clk_virt SLAVE_QUP_CORE_1 0>, 2358 <&gem_noc MASTER_APPSS_PROC 0 2359 &config_noc SLAVE_QUP_1 0>; 2360 power-domains = <&rpmhpd SA8775P_CX>; 2361 operating-points-v2 = <&qup_opp_table_100mhz>; 2362 status = "disabled"; 2363 }; 2364 2365 i2c11: i2c@a90000 { 2366 compatible = "qcom,geni-i2c"; 2367 reg = <0x0 0xa90000 0x0 0x4000>; 2368 #address-cells = <1>; 2369 #size-cells = <0>; 2370 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2371 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2372 clock-names = "se"; 2373 pinctrl-0 = <&qup_i2c11_default>; 2374 pinctrl-names = "default"; 2375 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2376 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2377 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2378 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2379 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2380 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2381 interconnect-names = "qup-core", 2382 "qup-config", 2383 "qup-memory"; 2384 power-domains = <&rpmhpd SA8775P_CX>; 2385 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2386 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2387 dma-names = "tx", 2388 "rx"; 2389 status = "disabled"; 2390 }; 2391 2392 spi11: spi@a90000 { 2393 compatible = "qcom,geni-spi"; 2394 reg = <0x0 0xa90000 0x0 0x4000>; 2395 #address-cells = <1>; 2396 #size-cells = <0>; 2397 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2398 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2399 clock-names = "se"; 2400 pinctrl-0 = <&qup_spi11_default>; 2401 pinctrl-names = "default"; 2402 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2403 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2404 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2405 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2406 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2407 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2408 interconnect-names = "qup-core", 2409 "qup-config", 2410 "qup-memory"; 2411 power-domains = <&rpmhpd SA8775P_CX>; 2412 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2413 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2414 dma-names = "tx", 2415 "rx"; 2416 status = "disabled"; 2417 }; 2418 2419 uart11: serial@a90000 { 2420 compatible = "qcom,geni-uart"; 2421 reg = <0x0 0x00a90000 0x0 0x4000>; 2422 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2423 clock-names = "se"; 2424 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2425 pinctrl-0 = <&qup_uart11_default>; 2426 pinctrl-names = "default"; 2427 interconnect-names = "qup-core", "qup-config"; 2428 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2429 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2430 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2431 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2432 power-domains = <&rpmhpd SA8775P_CX>; 2433 operating-points-v2 = <&qup_opp_table_100mhz>; 2434 status = "disabled"; 2435 }; 2436 2437 i2c12: i2c@a94000 { 2438 compatible = "qcom,geni-i2c"; 2439 reg = <0x0 0xa94000 0x0 0x4000>; 2440 #address-cells = <1>; 2441 #size-cells = <0>; 2442 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2443 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2444 clock-names = "se"; 2445 pinctrl-0 = <&qup_i2c12_default>; 2446 pinctrl-names = "default"; 2447 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2448 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2449 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2450 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2451 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2452 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2453 interconnect-names = "qup-core", 2454 "qup-config", 2455 "qup-memory"; 2456 power-domains = <&rpmhpd SA8775P_CX>; 2457 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2458 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2459 dma-names = "tx", 2460 "rx"; 2461 status = "disabled"; 2462 }; 2463 2464 spi12: spi@a94000 { 2465 compatible = "qcom,geni-spi"; 2466 reg = <0x0 0xa94000 0x0 0x4000>; 2467 #address-cells = <1>; 2468 #size-cells = <0>; 2469 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2470 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2471 clock-names = "se"; 2472 pinctrl-0 = <&qup_spi12_default>; 2473 pinctrl-names = "default"; 2474 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2475 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2476 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2477 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2478 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2479 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2480 interconnect-names = "qup-core", 2481 "qup-config", 2482 "qup-memory"; 2483 power-domains = <&rpmhpd SA8775P_CX>; 2484 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2485 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2486 dma-names = "tx", 2487 "rx"; 2488 status = "disabled"; 2489 }; 2490 2491 uart12: serial@a94000 { 2492 compatible = "qcom,geni-uart"; 2493 reg = <0x0 0x00a94000 0x0 0x4000>; 2494 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2495 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2496 clock-names = "se"; 2497 pinctrl-0 = <&qup_uart12_default>; 2498 pinctrl-names = "default"; 2499 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2500 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2501 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2502 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2503 interconnect-names = "qup-core", "qup-config"; 2504 power-domains = <&rpmhpd SA8775P_CX>; 2505 status = "disabled"; 2506 }; 2507 2508 i2c13: i2c@a98000 { 2509 compatible = "qcom,geni-i2c"; 2510 reg = <0x0 0xa98000 0x0 0x4000>; 2511 #address-cells = <1>; 2512 #size-cells = <0>; 2513 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2514 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2515 clock-names = "se"; 2516 pinctrl-0 = <&qup_i2c13_default>; 2517 pinctrl-names = "default"; 2518 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2519 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2520 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2521 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2522 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2523 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2524 interconnect-names = "qup-core", 2525 "qup-config", 2526 "qup-memory"; 2527 power-domains = <&rpmhpd SA8775P_CX>; 2528 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2529 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2530 dma-names = "tx", 2531 "rx"; 2532 status = "disabled"; 2533 2534 }; 2535 }; 2536 2537 gpi_dma3: dma-controller@b00000 { 2538 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2539 reg = <0x0 0x00b00000 0x0 0x58000>; 2540 #dma-cells = <3>; 2541 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2542 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2543 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2544 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2545 iommus = <&apps_smmu 0x056 0x0>; 2546 dma-channels = <4>; 2547 dma-channel-mask = <0xf>; 2548 status = "disabled"; 2549 }; 2550 2551 qupv3_id_3: geniqup@bc0000 { 2552 compatible = "qcom,geni-se-qup"; 2553 reg = <0x0 0xbc0000 0x0 0x6000>; 2554 #address-cells = <2>; 2555 #size-cells = <2>; 2556 ranges; 2557 clock-names = "m-ahb", "s-ahb"; 2558 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2559 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2560 iommus = <&apps_smmu 0x43 0x0>; 2561 status = "disabled"; 2562 2563 i2c21: i2c@b80000 { 2564 compatible = "qcom,geni-i2c"; 2565 reg = <0x0 0xb80000 0x0 0x4000>; 2566 #address-cells = <1>; 2567 #size-cells = <0>; 2568 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2569 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2570 clock-names = "se"; 2571 pinctrl-0 = <&qup_i2c21_default>; 2572 pinctrl-names = "default"; 2573 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2574 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2575 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2576 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2577 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2578 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2579 interconnect-names = "qup-core", 2580 "qup-config", 2581 "qup-memory"; 2582 power-domains = <&rpmhpd SA8775P_CX>; 2583 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2584 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2585 dma-names = "tx", 2586 "rx"; 2587 status = "disabled"; 2588 }; 2589 2590 spi21: spi@b80000 { 2591 compatible = "qcom,geni-spi"; 2592 reg = <0x0 0xb80000 0x0 0x4000>; 2593 #address-cells = <1>; 2594 #size-cells = <0>; 2595 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2596 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2597 clock-names = "se"; 2598 pinctrl-0 = <&qup_spi21_default>; 2599 pinctrl-names = "default"; 2600 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2601 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2602 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2603 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2604 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2605 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2606 interconnect-names = "qup-core", 2607 "qup-config", 2608 "qup-memory"; 2609 power-domains = <&rpmhpd SA8775P_CX>; 2610 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2611 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2612 dma-names = "tx", 2613 "rx"; 2614 status = "disabled"; 2615 }; 2616 2617 uart21: serial@b80000 { 2618 compatible = "qcom,geni-uart"; 2619 reg = <0x0 0x00b80000 0x0 0x4000>; 2620 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2621 clock-names = "se"; 2622 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2623 interconnect-names = "qup-core", "qup-config"; 2624 pinctrl-0 = <&qup_uart21_default>; 2625 pinctrl-names = "default"; 2626 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2627 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2628 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2629 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2630 power-domains = <&rpmhpd SA8775P_CX>; 2631 operating-points-v2 = <&qup_opp_table_100mhz>; 2632 status = "disabled"; 2633 }; 2634 }; 2635 2636 rng: rng@10d2000 { 2637 compatible = "qcom,sa8775p-trng", "qcom,trng"; 2638 reg = <0 0x010d2000 0 0x1000>; 2639 }; 2640 2641 config_noc: interconnect@14c0000 { 2642 compatible = "qcom,sa8775p-config-noc"; 2643 reg = <0x0 0x014c0000 0x0 0x13080>; 2644 #interconnect-cells = <2>; 2645 qcom,bcm-voters = <&apps_bcm_voter>; 2646 }; 2647 2648 system_noc: interconnect@1680000 { 2649 compatible = "qcom,sa8775p-system-noc"; 2650 reg = <0x0 0x01680000 0x0 0x15080>; 2651 #interconnect-cells = <2>; 2652 qcom,bcm-voters = <&apps_bcm_voter>; 2653 }; 2654 2655 aggre1_noc: interconnect@16c0000 { 2656 compatible = "qcom,sa8775p-aggre1-noc"; 2657 reg = <0x0 0x016c0000 0x0 0x18080>; 2658 #interconnect-cells = <2>; 2659 qcom,bcm-voters = <&apps_bcm_voter>; 2660 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2661 <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, 2662 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 2663 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2664 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>; 2665 }; 2666 2667 aggre2_noc: interconnect@1700000 { 2668 compatible = "qcom,sa8775p-aggre2-noc"; 2669 reg = <0x0 0x01700000 0x0 0x1b080>; 2670 #interconnect-cells = <2>; 2671 qcom,bcm-voters = <&apps_bcm_voter>; 2672 clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2673 <&rpmhcc RPMH_IPA_CLK>; 2674 }; 2675 2676 pcie_anoc: interconnect@1760000 { 2677 compatible = "qcom,sa8775p-pcie-anoc"; 2678 reg = <0x0 0x01760000 0x0 0xc080>; 2679 #interconnect-cells = <2>; 2680 qcom,bcm-voters = <&apps_bcm_voter>; 2681 }; 2682 2683 gpdsp_anoc: interconnect@1780000 { 2684 compatible = "qcom,sa8775p-gpdsp-anoc"; 2685 reg = <0x0 0x01780000 0x0 0xe080>; 2686 #interconnect-cells = <2>; 2687 qcom,bcm-voters = <&apps_bcm_voter>; 2688 }; 2689 2690 mmss_noc: interconnect@17a0000 { 2691 compatible = "qcom,sa8775p-mmss-noc"; 2692 reg = <0x0 0x017a0000 0x0 0x40000>; 2693 #interconnect-cells = <2>; 2694 qcom,bcm-voters = <&apps_bcm_voter>; 2695 }; 2696 2697 ufs_mem_hc: ufshc@1d84000 { 2698 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2699 reg = <0x0 0x01d84000 0x0 0x3000>; 2700 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2701 phys = <&ufs_mem_phy>; 2702 phy-names = "ufsphy"; 2703 lanes-per-direction = <2>; 2704 #reset-cells = <1>; 2705 resets = <&gcc GCC_UFS_PHY_BCR>; 2706 reset-names = "rst"; 2707 power-domains = <&gcc UFS_PHY_GDSC>; 2708 required-opps = <&rpmhpd_opp_nom>; 2709 iommus = <&apps_smmu 0x100 0x0>; 2710 dma-coherent; 2711 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2712 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2713 <&gcc GCC_UFS_PHY_AHB_CLK>, 2714 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2715 <&rpmhcc RPMH_CXO_CLK>, 2716 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2717 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2718 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2719 clock-names = "core_clk", 2720 "bus_aggr_clk", 2721 "iface_clk", 2722 "core_clk_unipro", 2723 "ref_clk", 2724 "tx_lane0_sync_clk", 2725 "rx_lane0_sync_clk", 2726 "rx_lane1_sync_clk"; 2727 freq-table-hz = <75000000 300000000>, 2728 <0 0>, 2729 <0 0>, 2730 <75000000 300000000>, 2731 <0 0>, 2732 <0 0>, 2733 <0 0>, 2734 <0 0>; 2735 qcom,ice = <&ice>; 2736 status = "disabled"; 2737 }; 2738 2739 ufs_mem_phy: phy@1d87000 { 2740 compatible = "qcom,sa8775p-qmp-ufs-phy"; 2741 reg = <0x0 0x01d87000 0x0 0xe10>; 2742 /* 2743 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2744 * enables the CXO clock to eDP *and* UFS PHY. 2745 */ 2746 clocks = <&rpmhcc RPMH_CXO_CLK>, 2747 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2748 <&gcc GCC_EDP_REF_CLKREF_EN>; 2749 clock-names = "ref", "ref_aux", "qref"; 2750 power-domains = <&gcc UFS_PHY_GDSC>; 2751 resets = <&ufs_mem_hc 0>; 2752 reset-names = "ufsphy"; 2753 #phy-cells = <0>; 2754 status = "disabled"; 2755 }; 2756 2757 ice: crypto@1d88000 { 2758 compatible = "qcom,sa8775p-inline-crypto-engine", 2759 "qcom,inline-crypto-engine"; 2760 reg = <0x0 0x01d88000 0x0 0x18000>; 2761 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2762 }; 2763 2764 cryptobam: dma-controller@1dc4000 { 2765 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2766 reg = <0x0 0x01dc4000 0x0 0x28000>; 2767 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2768 #dma-cells = <1>; 2769 qcom,ee = <0>; 2770 qcom,num-ees = <4>; 2771 num-channels = <20>; 2772 qcom,controlled-remotely; 2773 iommus = <&apps_smmu 0x480 0x00>, 2774 <&apps_smmu 0x481 0x00>; 2775 }; 2776 2777 crypto: crypto@1dfa000 { 2778 compatible = "qcom,sa8775p-qce", "qcom,sm8150-qce", "qcom,qce"; 2779 reg = <0x0 0x01dfa000 0x0 0x6000>; 2780 dmas = <&cryptobam 4>, <&cryptobam 5>; 2781 dma-names = "rx", "tx"; 2782 iommus = <&apps_smmu 0x480 0x0>, 2783 <&apps_smmu 0x481 0x0>; 2784 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS 2785 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2786 interconnect-names = "memory"; 2787 }; 2788 2789 lpass_ag_noc: interconnect@3c40000 { 2790 compatible = "qcom,sa8775p-lpass-ag-noc"; 2791 reg = <0x0 0x03c40000 0x0 0x17200>; 2792 #interconnect-cells = <2>; 2793 qcom,bcm-voters = <&apps_bcm_voter>; 2794 }; 2795 2796 ctcu@4001000 { 2797 compatible = "qcom,sa8775p-ctcu"; 2798 reg = <0x0 0x04001000 0x0 0x1000>; 2799 2800 clocks = <&aoss_qmp>; 2801 clock-names = "apb"; 2802 2803 in-ports { 2804 #address-cells = <1>; 2805 #size-cells = <0>; 2806 2807 port@0 { 2808 reg = <0>; 2809 2810 ctcu_in0: endpoint { 2811 remote-endpoint = <&etr0_out>; 2812 }; 2813 }; 2814 2815 port@1 { 2816 reg = <1>; 2817 2818 ctcu_in1: endpoint { 2819 remote-endpoint = <&etr1_out>; 2820 }; 2821 }; 2822 }; 2823 }; 2824 2825 stm: stm@4002000 { 2826 compatible = "arm,coresight-stm", "arm,primecell"; 2827 reg = <0x0 0x4002000 0x0 0x1000>, 2828 <0x0 0x16280000 0x0 0x180000>; 2829 reg-names = "stm-base", "stm-stimulus-base"; 2830 2831 clocks = <&aoss_qmp>; 2832 clock-names = "apb_pclk"; 2833 2834 out-ports { 2835 port { 2836 stm_out: endpoint { 2837 remote-endpoint = 2838 <&funnel0_in7>; 2839 }; 2840 }; 2841 }; 2842 }; 2843 2844 tpdm@4003000 { 2845 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2846 reg = <0x0 0x4003000 0x0 0x1000>; 2847 2848 clocks = <&aoss_qmp>; 2849 clock-names = "apb_pclk"; 2850 2851 qcom,cmb-element-bits = <32>; 2852 qcom,cmb-msrs-num = <32>; 2853 status = "disabled"; 2854 2855 out-ports { 2856 port { 2857 qdss_tpdm0_out: endpoint { 2858 remote-endpoint = 2859 <&qdss_tpda_in0>; 2860 }; 2861 }; 2862 }; 2863 }; 2864 2865 tpda@4004000 { 2866 compatible = "qcom,coresight-tpda", "arm,primecell"; 2867 reg = <0x0 0x4004000 0x0 0x1000>; 2868 2869 clocks = <&aoss_qmp>; 2870 clock-names = "apb_pclk"; 2871 2872 out-ports { 2873 port { 2874 qdss_tpda_out: endpoint { 2875 remote-endpoint = 2876 <&funnel0_in6>; 2877 }; 2878 }; 2879 }; 2880 2881 in-ports { 2882 #address-cells = <1>; 2883 #size-cells = <0>; 2884 2885 port@0 { 2886 reg = <0>; 2887 qdss_tpda_in0: endpoint { 2888 remote-endpoint = 2889 <&qdss_tpdm0_out>; 2890 }; 2891 }; 2892 2893 port@1 { 2894 reg = <1>; 2895 qdss_tpda_in1: endpoint { 2896 remote-endpoint = 2897 <&qdss_tpdm1_out>; 2898 }; 2899 }; 2900 }; 2901 }; 2902 2903 tpdm@400f000 { 2904 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2905 reg = <0x0 0x400f000 0x0 0x1000>; 2906 2907 clocks = <&aoss_qmp>; 2908 clock-names = "apb_pclk"; 2909 2910 qcom,cmb-element-bits = <32>; 2911 qcom,cmb-msrs-num = <32>; 2912 2913 out-ports { 2914 port { 2915 qdss_tpdm1_out: endpoint { 2916 remote-endpoint = 2917 <&qdss_tpda_in1>; 2918 }; 2919 }; 2920 }; 2921 }; 2922 2923 funnel@4041000 { 2924 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2925 reg = <0x0 0x4041000 0x0 0x1000>; 2926 2927 clocks = <&aoss_qmp>; 2928 clock-names = "apb_pclk"; 2929 2930 out-ports { 2931 port { 2932 funnel0_out: endpoint { 2933 remote-endpoint = 2934 <&qdss_funnel_in0>; 2935 }; 2936 }; 2937 }; 2938 2939 in-ports { 2940 #address-cells = <1>; 2941 #size-cells = <0>; 2942 2943 port@6 { 2944 reg = <6>; 2945 funnel0_in6: endpoint { 2946 remote-endpoint = 2947 <&qdss_tpda_out>; 2948 }; 2949 }; 2950 2951 port@7 { 2952 reg = <7>; 2953 funnel0_in7: endpoint { 2954 remote-endpoint = 2955 <&stm_out>; 2956 }; 2957 }; 2958 }; 2959 }; 2960 2961 funnel@4042000 { 2962 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2963 reg = <0x0 0x4042000 0x0 0x1000>; 2964 2965 clocks = <&aoss_qmp>; 2966 clock-names = "apb_pclk"; 2967 2968 out-ports { 2969 port { 2970 funnel1_out: endpoint { 2971 remote-endpoint = 2972 <&qdss_funnel_in1>; 2973 }; 2974 }; 2975 }; 2976 2977 in-ports { 2978 #address-cells = <1>; 2979 #size-cells = <0>; 2980 2981 port@4 { 2982 reg = <4>; 2983 funnel1_in4: endpoint { 2984 remote-endpoint = 2985 <&apss_funnel1_out>; 2986 }; 2987 }; 2988 2989 port@5 { 2990 reg = <5>; 2991 2992 funnel1_in5: endpoint { 2993 remote-endpoint = <&dlct0_funnel_out>; 2994 }; 2995 }; 2996 }; 2997 }; 2998 2999 funnel@4045000 { 3000 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3001 reg = <0x0 0x4045000 0x0 0x1000>; 3002 3003 clocks = <&aoss_qmp>; 3004 clock-names = "apb_pclk"; 3005 3006 out-ports { 3007 port { 3008 qdss_funnel_out: endpoint { 3009 remote-endpoint = 3010 <&aoss_funnel_in7>; 3011 }; 3012 }; 3013 }; 3014 3015 in-ports { 3016 #address-cells = <1>; 3017 #size-cells = <0>; 3018 3019 port@0 { 3020 reg = <0>; 3021 qdss_funnel_in0: endpoint { 3022 remote-endpoint = 3023 <&funnel0_out>; 3024 }; 3025 }; 3026 3027 port@1 { 3028 reg = <1>; 3029 qdss_funnel_in1: endpoint { 3030 remote-endpoint = 3031 <&funnel1_out>; 3032 }; 3033 }; 3034 }; 3035 }; 3036 3037 replicator@4046000 { 3038 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3039 reg = <0x0 0x04046000 0x0 0x1000>; 3040 3041 clocks = <&aoss_qmp>; 3042 clock-names = "apb_pclk"; 3043 3044 in-ports { 3045 port { 3046 qdss_rep_in: endpoint { 3047 remote-endpoint = <&swao_rep_out0>; 3048 }; 3049 }; 3050 }; 3051 3052 out-ports { 3053 port { 3054 qdss_rep_out0: endpoint { 3055 remote-endpoint = <&etr_rep_in>; 3056 }; 3057 }; 3058 }; 3059 }; 3060 3061 tmc_etr: tmc@4048000 { 3062 compatible = "arm,coresight-tmc", "arm,primecell"; 3063 reg = <0x0 0x04048000 0x0 0x1000>; 3064 3065 clocks = <&aoss_qmp>; 3066 clock-names = "apb_pclk"; 3067 iommus = <&apps_smmu 0x04c0 0x00>; 3068 3069 arm,scatter-gather; 3070 3071 in-ports { 3072 port { 3073 etr0_in: endpoint { 3074 remote-endpoint = <&etr_rep_out0>; 3075 }; 3076 }; 3077 }; 3078 3079 out-ports { 3080 port { 3081 etr0_out: endpoint { 3082 remote-endpoint = <&ctcu_in0>; 3083 }; 3084 }; 3085 }; 3086 }; 3087 3088 replicator@404e000 { 3089 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3090 reg = <0x0 0x0404e000 0x0 0x1000>; 3091 3092 clocks = <&aoss_qmp>; 3093 clock-names = "apb_pclk"; 3094 3095 in-ports { 3096 port { 3097 etr_rep_in: endpoint { 3098 remote-endpoint = <&qdss_rep_out0>; 3099 }; 3100 }; 3101 }; 3102 3103 out-ports { 3104 #address-cells = <1>; 3105 #size-cells = <0>; 3106 3107 port@0 { 3108 reg = <0>; 3109 3110 etr_rep_out0: endpoint { 3111 remote-endpoint = <&etr0_in>; 3112 }; 3113 }; 3114 3115 port@1 { 3116 reg = <1>; 3117 3118 etr_rep_out1: endpoint { 3119 remote-endpoint = <&etr1_in>; 3120 }; 3121 }; 3122 }; 3123 }; 3124 3125 tmc_etr1: tmc@404f000 { 3126 compatible = "arm,coresight-tmc", "arm,primecell"; 3127 reg = <0x0 0x0404f000 0x0 0x1000>; 3128 3129 clocks = <&aoss_qmp>; 3130 clock-names = "apb_pclk"; 3131 iommus = <&apps_smmu 0x04a0 0x40>; 3132 3133 arm,scatter-gather; 3134 arm,buffer-size = <0x400000>; 3135 3136 in-ports { 3137 port { 3138 etr1_in: endpoint { 3139 remote-endpoint = <&etr_rep_out1>; 3140 }; 3141 }; 3142 }; 3143 3144 out-ports { 3145 port { 3146 etr1_out: endpoint { 3147 remote-endpoint = <&ctcu_in1>; 3148 }; 3149 }; 3150 }; 3151 }; 3152 3153 tpda@4ad3000 { 3154 compatible = "qcom,coresight-tpda", "arm,primecell"; 3155 reg = <0x0 0x4ad3000 0x0 0x1000>; 3156 3157 clocks = <&aoss_qmp>; 3158 clock-names = "apb_pclk"; 3159 3160 in-ports { 3161 #address-cells = <1>; 3162 #size-cells = <0>; 3163 3164 port@10 { 3165 reg = <16>; 3166 dlct0_tpda_in16: endpoint { 3167 remote-endpoint = <&turing0_funnel_out>; 3168 }; 3169 }; 3170 }; 3171 3172 out-ports { 3173 port { 3174 dlct0_tpda_out: endpoint { 3175 remote-endpoint = 3176 <&dlct0_funnel_in0>; 3177 }; 3178 }; 3179 }; 3180 3181 }; 3182 3183 funnel@4ad4000 { 3184 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3185 reg = <0x0 0x4ad4000 0x0 0x1000>; 3186 3187 clocks = <&aoss_qmp>; 3188 clock-names = "apb_pclk"; 3189 3190 in-ports { 3191 port { 3192 dlct0_funnel_in0: endpoint { 3193 remote-endpoint = <&dlct0_tpda_out>; 3194 }; 3195 }; 3196 }; 3197 3198 out-ports { 3199 port { 3200 dlct0_funnel_out: endpoint { 3201 remote-endpoint = <&funnel1_in5>; 3202 }; 3203 }; 3204 }; 3205 }; 3206 3207 funnel@4b04000 { 3208 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3209 reg = <0x0 0x4b04000 0x0 0x1000>; 3210 3211 clocks = <&aoss_qmp>; 3212 clock-names = "apb_pclk"; 3213 3214 out-ports { 3215 port { 3216 aoss_funnel_out: endpoint { 3217 remote-endpoint = 3218 <&etf0_in>; 3219 }; 3220 }; 3221 }; 3222 3223 in-ports { 3224 #address-cells = <1>; 3225 #size-cells = <0>; 3226 3227 port@6 { 3228 reg = <6>; 3229 aoss_funnel_in6: endpoint { 3230 remote-endpoint = 3231 <&aoss_tpda_out>; 3232 }; 3233 }; 3234 3235 port@7 { 3236 reg = <7>; 3237 aoss_funnel_in7: endpoint { 3238 remote-endpoint = 3239 <&qdss_funnel_out>; 3240 }; 3241 }; 3242 }; 3243 }; 3244 3245 tmc_etf: tmc@4b05000 { 3246 compatible = "arm,coresight-tmc", "arm,primecell"; 3247 reg = <0x0 0x4b05000 0x0 0x1000>; 3248 3249 clocks = <&aoss_qmp>; 3250 clock-names = "apb_pclk"; 3251 3252 out-ports { 3253 port { 3254 etf0_out: endpoint { 3255 remote-endpoint = 3256 <&swao_rep_in>; 3257 }; 3258 }; 3259 }; 3260 3261 in-ports { 3262 port { 3263 etf0_in: endpoint { 3264 remote-endpoint = 3265 <&aoss_funnel_out>; 3266 }; 3267 }; 3268 }; 3269 }; 3270 3271 replicator@4b06000 { 3272 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3273 reg = <0x0 0x4b06000 0x0 0x1000>; 3274 3275 clocks = <&aoss_qmp>; 3276 clock-names = "apb_pclk"; 3277 3278 out-ports { 3279 #address-cells = <1>; 3280 #size-cells = <0>; 3281 3282 port@0 { 3283 reg = <0>; 3284 3285 swao_rep_out0: endpoint { 3286 remote-endpoint = <&qdss_rep_in>; 3287 }; 3288 }; 3289 3290 port@1 { 3291 reg = <1>; 3292 swao_rep_out1: endpoint { 3293 remote-endpoint = 3294 <&eud_in>; 3295 }; 3296 }; 3297 }; 3298 3299 in-ports { 3300 port { 3301 swao_rep_in: endpoint { 3302 remote-endpoint = 3303 <&etf0_out>; 3304 }; 3305 }; 3306 }; 3307 }; 3308 3309 tpda@4b08000 { 3310 compatible = "qcom,coresight-tpda", "arm,primecell"; 3311 reg = <0x0 0x4b08000 0x0 0x1000>; 3312 3313 clocks = <&aoss_qmp>; 3314 clock-names = "apb_pclk"; 3315 3316 out-ports { 3317 port { 3318 aoss_tpda_out: endpoint { 3319 remote-endpoint = 3320 <&aoss_funnel_in6>; 3321 }; 3322 }; 3323 }; 3324 3325 in-ports { 3326 #address-cells = <1>; 3327 #size-cells = <0>; 3328 3329 port@0 { 3330 reg = <0>; 3331 aoss_tpda_in0: endpoint { 3332 remote-endpoint = 3333 <&aoss_tpdm0_out>; 3334 }; 3335 }; 3336 3337 port@1 { 3338 reg = <1>; 3339 aoss_tpda_in1: endpoint { 3340 remote-endpoint = 3341 <&aoss_tpdm1_out>; 3342 }; 3343 }; 3344 3345 port@2 { 3346 reg = <2>; 3347 aoss_tpda_in2: endpoint { 3348 remote-endpoint = 3349 <&aoss_tpdm2_out>; 3350 }; 3351 }; 3352 3353 port@3 { 3354 reg = <3>; 3355 aoss_tpda_in3: endpoint { 3356 remote-endpoint = 3357 <&aoss_tpdm3_out>; 3358 }; 3359 }; 3360 3361 port@4 { 3362 reg = <4>; 3363 aoss_tpda_in4: endpoint { 3364 remote-endpoint = 3365 <&aoss_tpdm4_out>; 3366 }; 3367 }; 3368 }; 3369 }; 3370 3371 tpdm@4b09000 { 3372 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3373 reg = <0x0 0x4b09000 0x0 0x1000>; 3374 3375 clocks = <&aoss_qmp>; 3376 clock-names = "apb_pclk"; 3377 3378 qcom,cmb-element-bits = <64>; 3379 qcom,cmb-msrs-num = <32>; 3380 3381 out-ports { 3382 port { 3383 aoss_tpdm0_out: endpoint { 3384 remote-endpoint = 3385 <&aoss_tpda_in0>; 3386 }; 3387 }; 3388 }; 3389 }; 3390 3391 tpdm@4b0a000 { 3392 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3393 reg = <0x0 0x4b0a000 0x0 0x1000>; 3394 3395 clocks = <&aoss_qmp>; 3396 clock-names = "apb_pclk"; 3397 3398 qcom,cmb-element-bits = <64>; 3399 qcom,cmb-msrs-num = <32>; 3400 3401 out-ports { 3402 port { 3403 aoss_tpdm1_out: endpoint { 3404 remote-endpoint = 3405 <&aoss_tpda_in1>; 3406 }; 3407 }; 3408 }; 3409 }; 3410 3411 tpdm@4b0b000 { 3412 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3413 reg = <0x0 0x4b0b000 0x0 0x1000>; 3414 3415 clocks = <&aoss_qmp>; 3416 clock-names = "apb_pclk"; 3417 3418 qcom,cmb-element-bits = <64>; 3419 qcom,cmb-msrs-num = <32>; 3420 3421 out-ports { 3422 port { 3423 aoss_tpdm2_out: endpoint { 3424 remote-endpoint = 3425 <&aoss_tpda_in2>; 3426 }; 3427 }; 3428 }; 3429 }; 3430 3431 tpdm@4b0c000 { 3432 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3433 reg = <0x0 0x4b0c000 0x0 0x1000>; 3434 3435 clocks = <&aoss_qmp>; 3436 clock-names = "apb_pclk"; 3437 3438 qcom,cmb-element-bits = <64>; 3439 qcom,cmb-msrs-num = <32>; 3440 3441 out-ports { 3442 port { 3443 aoss_tpdm3_out: endpoint { 3444 remote-endpoint = 3445 <&aoss_tpda_in3>; 3446 }; 3447 }; 3448 }; 3449 }; 3450 3451 tpdm@4b0d000 { 3452 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3453 reg = <0x0 0x4b0d000 0x0 0x1000>; 3454 3455 clocks = <&aoss_qmp>; 3456 clock-names = "apb_pclk"; 3457 3458 qcom,dsb-element-bits = <32>; 3459 qcom,dsb-msrs-num = <32>; 3460 3461 out-ports { 3462 port { 3463 aoss_tpdm4_out: endpoint { 3464 remote-endpoint = 3465 <&aoss_tpda_in4>; 3466 }; 3467 }; 3468 }; 3469 }; 3470 3471 aoss_cti: cti@4b13000 { 3472 compatible = "arm,coresight-cti", "arm,primecell"; 3473 reg = <0x0 0x4b13000 0x0 0x1000>; 3474 3475 clocks = <&aoss_qmp>; 3476 clock-names = "apb_pclk"; 3477 }; 3478 3479 funnel@4b83000 { 3480 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3481 reg = <0x0 0x4b83000 0x0 0x1000>; 3482 3483 clocks = <&aoss_qmp>; 3484 clock-names = "apb_pclk"; 3485 3486 in-ports { 3487 #address-cells = <1>; 3488 #size-cells = <0>; 3489 3490 port@1 { 3491 reg = <1>; 3492 3493 turing0_funnel_in1: endpoint { 3494 remote-endpoint = <&turing_llm_tpdm_out>; 3495 }; 3496 }; 3497 }; 3498 3499 out-ports { 3500 port { 3501 turing0_funnel_out: endpoint { 3502 remote-endpoint = <&dlct0_tpda_in16>; 3503 }; 3504 }; 3505 }; 3506 }; 3507 3508 etm@6040000 { 3509 compatible = "arm,primecell"; 3510 reg = <0x0 0x6040000 0x0 0x1000>; 3511 cpu = <&cpu0>; 3512 3513 clocks = <&aoss_qmp>; 3514 clock-names = "apb_pclk"; 3515 arm,coresight-loses-context-with-cpu; 3516 qcom,skip-power-up; 3517 3518 out-ports { 3519 port { 3520 etm0_out: endpoint { 3521 remote-endpoint = 3522 <&apss_funnel0_in0>; 3523 }; 3524 }; 3525 }; 3526 }; 3527 3528 etm@6140000 { 3529 compatible = "arm,primecell"; 3530 reg = <0x0 0x6140000 0x0 0x1000>; 3531 cpu = <&cpu1>; 3532 3533 clocks = <&aoss_qmp>; 3534 clock-names = "apb_pclk"; 3535 arm,coresight-loses-context-with-cpu; 3536 qcom,skip-power-up; 3537 3538 out-ports { 3539 port { 3540 etm1_out: endpoint { 3541 remote-endpoint = 3542 <&apss_funnel0_in1>; 3543 }; 3544 }; 3545 }; 3546 }; 3547 3548 etm@6240000 { 3549 compatible = "arm,primecell"; 3550 reg = <0x0 0x6240000 0x0 0x1000>; 3551 cpu = <&cpu2>; 3552 3553 clocks = <&aoss_qmp>; 3554 clock-names = "apb_pclk"; 3555 arm,coresight-loses-context-with-cpu; 3556 qcom,skip-power-up; 3557 3558 out-ports { 3559 port { 3560 etm2_out: endpoint { 3561 remote-endpoint = 3562 <&apss_funnel0_in2>; 3563 }; 3564 }; 3565 }; 3566 }; 3567 3568 etm@6340000 { 3569 compatible = "arm,primecell"; 3570 reg = <0x0 0x6340000 0x0 0x1000>; 3571 cpu = <&cpu3>; 3572 3573 clocks = <&aoss_qmp>; 3574 clock-names = "apb_pclk"; 3575 arm,coresight-loses-context-with-cpu; 3576 qcom,skip-power-up; 3577 3578 out-ports { 3579 port { 3580 etm3_out: endpoint { 3581 remote-endpoint = 3582 <&apss_funnel0_in3>; 3583 }; 3584 }; 3585 }; 3586 }; 3587 3588 etm@6440000 { 3589 compatible = "arm,primecell"; 3590 reg = <0x0 0x6440000 0x0 0x1000>; 3591 cpu = <&cpu4>; 3592 3593 clocks = <&aoss_qmp>; 3594 clock-names = "apb_pclk"; 3595 arm,coresight-loses-context-with-cpu; 3596 qcom,skip-power-up; 3597 3598 out-ports { 3599 port { 3600 etm4_out: endpoint { 3601 remote-endpoint = 3602 <&apss_funnel0_in4>; 3603 }; 3604 }; 3605 }; 3606 }; 3607 3608 etm@6540000 { 3609 compatible = "arm,primecell"; 3610 reg = <0x0 0x6540000 0x0 0x1000>; 3611 cpu = <&cpu5>; 3612 3613 clocks = <&aoss_qmp>; 3614 clock-names = "apb_pclk"; 3615 arm,coresight-loses-context-with-cpu; 3616 qcom,skip-power-up; 3617 3618 out-ports { 3619 port { 3620 etm5_out: endpoint { 3621 remote-endpoint = 3622 <&apss_funnel0_in5>; 3623 }; 3624 }; 3625 }; 3626 }; 3627 3628 etm@6640000 { 3629 compatible = "arm,primecell"; 3630 reg = <0x0 0x6640000 0x0 0x1000>; 3631 cpu = <&cpu6>; 3632 3633 clocks = <&aoss_qmp>; 3634 clock-names = "apb_pclk"; 3635 arm,coresight-loses-context-with-cpu; 3636 qcom,skip-power-up; 3637 3638 out-ports { 3639 port { 3640 etm6_out: endpoint { 3641 remote-endpoint = 3642 <&apss_funnel0_in6>; 3643 }; 3644 }; 3645 }; 3646 }; 3647 3648 etm@6740000 { 3649 compatible = "arm,primecell"; 3650 reg = <0x0 0x6740000 0x0 0x1000>; 3651 cpu = <&cpu7>; 3652 3653 clocks = <&aoss_qmp>; 3654 clock-names = "apb_pclk"; 3655 arm,coresight-loses-context-with-cpu; 3656 qcom,skip-power-up; 3657 3658 out-ports { 3659 port { 3660 etm7_out: endpoint { 3661 remote-endpoint = 3662 <&apss_funnel0_in7>; 3663 }; 3664 }; 3665 }; 3666 }; 3667 3668 funnel@6800000 { 3669 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3670 reg = <0x0 0x6800000 0x0 0x1000>; 3671 3672 clocks = <&aoss_qmp>; 3673 clock-names = "apb_pclk"; 3674 3675 out-ports { 3676 port { 3677 apss_funnel0_out: endpoint { 3678 remote-endpoint = 3679 <&apss_funnel1_in0>; 3680 }; 3681 }; 3682 }; 3683 3684 in-ports { 3685 #address-cells = <1>; 3686 #size-cells = <0>; 3687 3688 port@0 { 3689 reg = <0>; 3690 apss_funnel0_in0: endpoint { 3691 remote-endpoint = 3692 <&etm0_out>; 3693 }; 3694 }; 3695 3696 port@1 { 3697 reg = <1>; 3698 apss_funnel0_in1: endpoint { 3699 remote-endpoint = 3700 <&etm1_out>; 3701 }; 3702 }; 3703 3704 port@2 { 3705 reg = <2>; 3706 apss_funnel0_in2: endpoint { 3707 remote-endpoint = 3708 <&etm2_out>; 3709 }; 3710 }; 3711 3712 port@3 { 3713 reg = <3>; 3714 apss_funnel0_in3: endpoint { 3715 remote-endpoint = 3716 <&etm3_out>; 3717 }; 3718 }; 3719 3720 port@4 { 3721 reg = <4>; 3722 apss_funnel0_in4: endpoint { 3723 remote-endpoint = 3724 <&etm4_out>; 3725 }; 3726 }; 3727 3728 port@5 { 3729 reg = <5>; 3730 apss_funnel0_in5: endpoint { 3731 remote-endpoint = 3732 <&etm5_out>; 3733 }; 3734 }; 3735 3736 port@6 { 3737 reg = <6>; 3738 apss_funnel0_in6: endpoint { 3739 remote-endpoint = 3740 <&etm6_out>; 3741 }; 3742 }; 3743 3744 port@7 { 3745 reg = <7>; 3746 apss_funnel0_in7: endpoint { 3747 remote-endpoint = 3748 <&etm7_out>; 3749 }; 3750 }; 3751 }; 3752 }; 3753 3754 funnel@6810000 { 3755 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3756 reg = <0x0 0x6810000 0x0 0x1000>; 3757 3758 clocks = <&aoss_qmp>; 3759 clock-names = "apb_pclk"; 3760 3761 out-ports { 3762 port { 3763 apss_funnel1_out: endpoint { 3764 remote-endpoint = 3765 <&funnel1_in4>; 3766 }; 3767 }; 3768 }; 3769 3770 in-ports { 3771 #address-cells = <1>; 3772 #size-cells = <0>; 3773 3774 port@0 { 3775 reg = <0>; 3776 apss_funnel1_in0: endpoint { 3777 remote-endpoint = 3778 <&apss_funnel0_out>; 3779 }; 3780 }; 3781 3782 port@3 { 3783 reg = <3>; 3784 apss_funnel1_in3: endpoint { 3785 remote-endpoint = 3786 <&apss_tpda_out>; 3787 }; 3788 }; 3789 }; 3790 }; 3791 3792 tpdm@6860000 { 3793 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3794 reg = <0x0 0x6860000 0x0 0x1000>; 3795 3796 clocks = <&aoss_qmp>; 3797 clock-names = "apb_pclk"; 3798 3799 qcom,cmb-element-bits = <64>; 3800 qcom,cmb-msrs-num = <32>; 3801 3802 out-ports { 3803 port { 3804 apss_tpdm3_out: endpoint { 3805 remote-endpoint = 3806 <&apss_tpda_in3>; 3807 }; 3808 }; 3809 }; 3810 }; 3811 3812 tpdm@6861000 { 3813 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3814 reg = <0x0 0x6861000 0x0 0x1000>; 3815 3816 clocks = <&aoss_qmp>; 3817 clock-names = "apb_pclk"; 3818 3819 qcom,dsb-element-bits = <32>; 3820 qcom,dsb-msrs-num = <32>; 3821 3822 out-ports { 3823 port { 3824 apss_tpdm4_out: endpoint { 3825 remote-endpoint = 3826 <&apss_tpda_in4>; 3827 }; 3828 }; 3829 }; 3830 }; 3831 3832 tpda@6863000 { 3833 compatible = "qcom,coresight-tpda", "arm,primecell"; 3834 reg = <0x0 0x6863000 0x0 0x1000>; 3835 3836 clocks = <&aoss_qmp>; 3837 clock-names = "apb_pclk"; 3838 3839 out-ports { 3840 port { 3841 apss_tpda_out: endpoint { 3842 remote-endpoint = 3843 <&apss_funnel1_in3>; 3844 }; 3845 }; 3846 }; 3847 3848 in-ports { 3849 #address-cells = <1>; 3850 #size-cells = <0>; 3851 3852 port@0 { 3853 reg = <0>; 3854 apss_tpda_in0: endpoint { 3855 remote-endpoint = 3856 <&apss_tpdm0_out>; 3857 }; 3858 }; 3859 3860 port@1 { 3861 reg = <1>; 3862 apss_tpda_in1: endpoint { 3863 remote-endpoint = 3864 <&apss_tpdm1_out>; 3865 }; 3866 }; 3867 3868 port@2 { 3869 reg = <2>; 3870 apss_tpda_in2: endpoint { 3871 remote-endpoint = 3872 <&apss_tpdm2_out>; 3873 }; 3874 }; 3875 3876 port@3 { 3877 reg = <3>; 3878 apss_tpda_in3: endpoint { 3879 remote-endpoint = 3880 <&apss_tpdm3_out>; 3881 }; 3882 }; 3883 3884 port@4 { 3885 reg = <4>; 3886 apss_tpda_in4: endpoint { 3887 remote-endpoint = 3888 <&apss_tpdm4_out>; 3889 }; 3890 }; 3891 }; 3892 }; 3893 3894 tpdm@68a0000 { 3895 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3896 reg = <0x0 0x68a0000 0x0 0x1000>; 3897 3898 clocks = <&aoss_qmp>; 3899 clock-names = "apb_pclk"; 3900 3901 qcom,cmb-element-bits = <32>; 3902 qcom,cmb-msrs-num = <32>; 3903 3904 out-ports { 3905 port { 3906 apss_tpdm0_out: endpoint { 3907 remote-endpoint = 3908 <&apss_tpda_in0>; 3909 }; 3910 }; 3911 }; 3912 }; 3913 3914 tpdm@68b0000 { 3915 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3916 reg = <0x0 0x68b0000 0x0 0x1000>; 3917 3918 clocks = <&aoss_qmp>; 3919 clock-names = "apb_pclk"; 3920 3921 qcom,cmb-element-bits = <32>; 3922 qcom,cmb-msrs-num = <32>; 3923 3924 out-ports { 3925 port { 3926 apss_tpdm1_out: endpoint { 3927 remote-endpoint = 3928 <&apss_tpda_in1>; 3929 }; 3930 }; 3931 }; 3932 }; 3933 3934 tpdm@68c0000 { 3935 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3936 reg = <0x0 0x68c0000 0x0 0x1000>; 3937 3938 clocks = <&aoss_qmp>; 3939 clock-names = "apb_pclk"; 3940 3941 qcom,dsb-element-bits = <32>; 3942 qcom,dsb-msrs-num = <32>; 3943 3944 out-ports { 3945 port { 3946 apss_tpdm2_out: endpoint { 3947 remote-endpoint = 3948 <&apss_tpda_in2>; 3949 }; 3950 }; 3951 }; 3952 }; 3953 3954 sdhc: mmc@87c4000 { 3955 compatible = "qcom,sa8775p-sdhci", "qcom,sdhci-msm-v5"; 3956 reg = <0x0 0x087c4000 0x0 0x1000>; 3957 3958 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 3959 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; 3960 interrupt-names = "hc_irq", 3961 "pwr_irq"; 3962 3963 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 3964 <&gcc GCC_SDCC1_APPS_CLK>; 3965 clock-names = "iface", 3966 "core"; 3967 3968 interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS 3969 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3970 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3971 &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3972 interconnect-names = "sdhc-ddr", 3973 "cpu-sdhc"; 3974 3975 iommus = <&apps_smmu 0x0 0x0>; 3976 dma-coherent; 3977 3978 operating-points-v2 = <&sdhc_opp_table>; 3979 power-domains = <&rpmhpd SA8775P_CX>; 3980 resets = <&gcc GCC_SDCC1_BCR>; 3981 3982 qcom,dll-config = <0x0007642c>; 3983 qcom,ddr-config = <0x80040868>; 3984 3985 status = "disabled"; 3986 3987 sdhc_opp_table: opp-table { 3988 compatible = "operating-points-v2"; 3989 3990 opp-100000000 { 3991 opp-hz = /bits/ 64 <100000000>; 3992 required-opps = <&rpmhpd_opp_low_svs>; 3993 opp-peak-kBps = <1800000 400000>; 3994 opp-avg-kBps = <100000 0>; 3995 }; 3996 3997 opp-384000000 { 3998 opp-hz = /bits/ 64 <384000000>; 3999 required-opps = <&rpmhpd_opp_nom>; 4000 opp-peak-kBps = <5400000 1600000>; 4001 opp-avg-kBps = <390000 0>; 4002 }; 4003 }; 4004 }; 4005 4006 usb_0_hsphy: phy@88e4000 { 4007 compatible = "qcom,sa8775p-usb-hs-phy", 4008 "qcom,usb-snps-hs-5nm-phy"; 4009 reg = <0 0x088e4000 0 0x120>; 4010 clocks = <&rpmhcc RPMH_CXO_CLK>; 4011 clock-names = "ref"; 4012 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 4013 4014 #phy-cells = <0>; 4015 4016 status = "disabled"; 4017 }; 4018 4019 usb_1_hsphy: phy@88e6000 { 4020 compatible = "qcom,sa8775p-usb-hs-phy", 4021 "qcom,usb-snps-hs-5nm-phy"; 4022 reg = <0 0x088e6000 0 0x120>; 4023 clocks = <&gcc GCC_USB_CLKREF_EN>; 4024 clock-names = "ref"; 4025 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 4026 4027 #phy-cells = <0>; 4028 4029 status = "disabled"; 4030 }; 4031 4032 usb_2_hsphy: phy@88e7000 { 4033 compatible = "qcom,sa8775p-usb-hs-phy", 4034 "qcom,usb-snps-hs-5nm-phy"; 4035 reg = <0 0x088e7000 0 0x120>; 4036 clocks = <&gcc GCC_USB_CLKREF_EN>; 4037 clock-names = "ref"; 4038 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 4039 4040 #phy-cells = <0>; 4041 4042 status = "disabled"; 4043 }; 4044 4045 usb_0_qmpphy: phy@88e8000 { 4046 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 4047 reg = <0 0x088e8000 0 0x2000>; 4048 4049 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4050 <&gcc GCC_USB_CLKREF_EN>, 4051 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4052 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4053 clock-names = "aux", "ref", "com_aux", "pipe"; 4054 4055 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4056 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 4057 reset-names = "phy", "phy_phy"; 4058 4059 power-domains = <&gcc USB30_PRIM_GDSC>; 4060 4061 #clock-cells = <0>; 4062 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 4063 4064 #phy-cells = <0>; 4065 4066 status = "disabled"; 4067 }; 4068 4069 usb_1_qmpphy: phy@88ea000 { 4070 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 4071 reg = <0 0x088ea000 0 0x2000>; 4072 4073 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 4074 <&gcc GCC_USB_CLKREF_EN>, 4075 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 4076 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 4077 clock-names = "aux", "ref", "com_aux", "pipe"; 4078 4079 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 4080 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 4081 reset-names = "phy", "phy_phy"; 4082 4083 power-domains = <&gcc USB30_SEC_GDSC>; 4084 4085 #clock-cells = <0>; 4086 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 4087 4088 #phy-cells = <0>; 4089 4090 status = "disabled"; 4091 }; 4092 4093 refgen: regulator@891c000 { 4094 compatible = "qcom,sa8775p-refgen-regulator", 4095 "qcom,sm8250-refgen-regulator"; 4096 reg = <0x0 0x0891c000 0x0 0x84>; 4097 }; 4098 4099 dc_noc: interconnect@90e0000 { 4100 compatible = "qcom,sa8775p-dc-noc"; 4101 reg = <0x0 0x090e0000 0x0 0x5080>; 4102 #interconnect-cells = <2>; 4103 qcom,bcm-voters = <&apps_bcm_voter>; 4104 }; 4105 4106 gem_noc: interconnect@9100000 { 4107 compatible = "qcom,sa8775p-gem-noc"; 4108 reg = <0x0 0x09100000 0x0 0xf6080>; 4109 #interconnect-cells = <2>; 4110 qcom,bcm-voters = <&apps_bcm_voter>; 4111 }; 4112 4113 usb_0: usb@a600000 { 4114 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4115 reg = <0 0x0a600000 0 0xfc100>; 4116 4117 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4118 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4119 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4120 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4121 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4122 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4123 4124 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4125 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4126 assigned-clock-rates = <19200000>, <200000000>; 4127 4128 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 4129 <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 4130 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4131 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4132 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4133 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 4134 interrupt-names = "dwc_usb3", 4135 "pwr_event", 4136 "hs_phy_irq", 4137 "dp_hs_phy_irq", 4138 "dm_hs_phy_irq", 4139 "ss_phy_irq"; 4140 4141 power-domains = <&gcc USB30_PRIM_GDSC>; 4142 required-opps = <&rpmhpd_opp_nom>; 4143 4144 resets = <&gcc GCC_USB30_PRIM_BCR>; 4145 4146 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4147 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4148 interconnect-names = "usb-ddr", "apps-usb"; 4149 4150 wakeup-source; 4151 4152 iommus = <&apps_smmu 0x080 0x0>; 4153 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 4154 phy-names = "usb2-phy", "usb3-phy"; 4155 snps,dis-u1-entry-quirk; 4156 snps,dis-u2-entry-quirk; 4157 4158 usb-role-switch; 4159 status = "disabled"; 4160 4161 ports { 4162 #address-cells = <1>; 4163 #size-cells = <0>; 4164 4165 port@0 { 4166 reg = <0>; 4167 4168 usb_0_dwc3_hs: endpoint { 4169 }; 4170 }; 4171 4172 port@1 { 4173 reg = <1>; 4174 4175 usb_0_dwc3_ss: endpoint { 4176 }; 4177 }; 4178 }; 4179 }; 4180 4181 usb_1: usb@a800000 { 4182 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4183 reg = <0 0x0a800000 0 0xfc100>; 4184 4185 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4186 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4187 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4188 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4189 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4190 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4191 4192 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4193 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4194 assigned-clock-rates = <19200000>, <200000000>; 4195 4196 interrupts-extended = <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 4197 <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 4198 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 4199 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 4200 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 4201 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 4202 interrupt-names = "dwc_usb3", 4203 "pwr_event", 4204 "hs_phy_irq", 4205 "dp_hs_phy_irq", 4206 "dm_hs_phy_irq", 4207 "ss_phy_irq"; 4208 4209 power-domains = <&gcc USB30_SEC_GDSC>; 4210 required-opps = <&rpmhpd_opp_nom>; 4211 4212 resets = <&gcc GCC_USB30_SEC_BCR>; 4213 4214 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 4215 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4216 interconnect-names = "usb-ddr", "apps-usb"; 4217 4218 wakeup-source; 4219 4220 iommus = <&apps_smmu 0x0a0 0x0>; 4221 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 4222 phy-names = "usb2-phy", "usb3-phy"; 4223 snps,dis-u1-entry-quirk; 4224 snps,dis-u2-entry-quirk; 4225 4226 status = "disabled"; 4227 }; 4228 4229 usb_2: usb@a400000 { 4230 compatible = "qcom,sa8775p-dwc3", "qcom,snps-dwc3"; 4231 reg = <0 0x0a400000 0 0xfc100>; 4232 4233 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4234 <&gcc GCC_USB20_MASTER_CLK>, 4235 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4236 <&gcc GCC_USB20_SLEEP_CLK>, 4237 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 4238 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 4239 4240 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4241 <&gcc GCC_USB20_MASTER_CLK>; 4242 assigned-clock-rates = <19200000>, <200000000>; 4243 4244 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 4245 <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 4246 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 4247 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 4248 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 4249 interrupt-names = "dwc_usb3", 4250 "pwr_event", 4251 "hs_phy_irq", 4252 "dp_hs_phy_irq", 4253 "dm_hs_phy_irq"; 4254 4255 power-domains = <&gcc USB20_PRIM_GDSC>; 4256 required-opps = <&rpmhpd_opp_nom>; 4257 4258 resets = <&gcc GCC_USB20_PRIM_BCR>; 4259 4260 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 4261 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 4262 interconnect-names = "usb-ddr", "apps-usb"; 4263 4264 qcom,select-utmi-as-pipe-clk; 4265 wakeup-source; 4266 4267 iommus = <&apps_smmu 0x020 0x0>; 4268 phys = <&usb_2_hsphy>; 4269 phy-names = "usb2-phy"; 4270 snps,dis-u1-entry-quirk; 4271 snps,dis-u2-entry-quirk; 4272 4273 status = "disabled"; 4274 }; 4275 4276 tcsr_mutex: hwlock@1f40000 { 4277 compatible = "qcom,tcsr-mutex"; 4278 reg = <0x0 0x01f40000 0x0 0x20000>; 4279 #hwlock-cells = <1>; 4280 }; 4281 4282 tcsr: syscon@1fc0000 { 4283 compatible = "qcom,sa8775p-tcsr", "syscon"; 4284 reg = <0x0 0x1fc0000 0x0 0x30000>; 4285 }; 4286 4287 gpu: gpu@3d00000 { 4288 compatible = "qcom,adreno-663.0", "qcom,adreno"; 4289 reg = <0x0 0x03d00000 0x0 0x40000>, 4290 <0x0 0x03d9e000 0x0 0x1000>, 4291 <0x0 0x03d61000 0x0 0x800>; 4292 reg-names = "kgsl_3d0_reg_memory", 4293 "cx_mem", 4294 "cx_dbgc"; 4295 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4296 iommus = <&adreno_smmu 0 0xc00>, 4297 <&adreno_smmu 1 0xc00>; 4298 operating-points-v2 = <&gpu_opp_table>; 4299 qcom,gmu = <&gmu>; 4300 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4301 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4302 interconnect-names = "gfx-mem"; 4303 #cooling-cells = <2>; 4304 4305 nvmem-cells = <&gpu_speed_bin>; 4306 nvmem-cell-names = "speed_bin"; 4307 4308 status = "disabled"; 4309 4310 gpu_zap_shader: zap-shader { 4311 memory-region = <&pil_gpu_mem>; 4312 }; 4313 4314 gpu_opp_table: opp-table { 4315 compatible = "operating-points-v2"; 4316 4317 opp-405000000 { 4318 opp-hz = /bits/ 64 <405000000>; 4319 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4320 opp-peak-kBps = <5285156>; 4321 opp-supported-hw = <0x3>; 4322 }; 4323 4324 opp-530000000 { 4325 opp-hz = /bits/ 64 <530000000>; 4326 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4327 opp-peak-kBps = <12484375>; 4328 opp-supported-hw = <0x2>; 4329 }; 4330 4331 opp-676000000 { 4332 opp-hz = /bits/ 64 <676000000>; 4333 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4334 opp-peak-kBps = <8171875>; 4335 opp-supported-hw = <0x1>; 4336 }; 4337 4338 opp-778000000 { 4339 opp-hz = /bits/ 64 <778000000>; 4340 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4341 opp-peak-kBps = <10687500>; 4342 opp-supported-hw = <0x1>; 4343 }; 4344 4345 opp-800000000 { 4346 opp-hz = /bits/ 64 <800000000>; 4347 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4348 opp-peak-kBps = <12484375>; 4349 opp-supported-hw = <0x1>; 4350 }; 4351 }; 4352 }; 4353 4354 gmu: gmu@3d6a000 { 4355 compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; 4356 reg = <0x0 0x03d6a000 0x0 0x34000>, 4357 <0x0 0x03de0000 0x0 0x10000>, 4358 <0x0 0x0b290000 0x0 0x10000>; 4359 reg-names = "gmu", "rscc", "gmu_pdc"; 4360 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4361 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4362 interrupt-names = "hfi", "gmu"; 4363 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4364 <&gpucc GPU_CC_CXO_CLK>, 4365 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4366 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4367 <&gpucc GPU_CC_AHB_CLK>, 4368 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4369 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 4370 clock-names = "gmu", 4371 "cxo", 4372 "axi", 4373 "memnoc", 4374 "ahb", 4375 "hub", 4376 "smmu_vote"; 4377 power-domains = <&gpucc GPU_CC_CX_GDSC>, 4378 <&gpucc GPU_CC_GX_GDSC>; 4379 power-domain-names = "cx", 4380 "gx"; 4381 iommus = <&adreno_smmu 5 0xc00>; 4382 operating-points-v2 = <&gmu_opp_table>; 4383 4384 gmu_opp_table: opp-table { 4385 compatible = "operating-points-v2"; 4386 4387 opp-500000000 { 4388 opp-hz = /bits/ 64 <500000000>; 4389 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4390 }; 4391 }; 4392 }; 4393 4394 gpucc: clock-controller@3d90000 { 4395 compatible = "qcom,sa8775p-gpucc"; 4396 reg = <0x0 0x03d90000 0x0 0xa000>; 4397 clocks = <&rpmhcc RPMH_CXO_CLK>, 4398 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4399 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4400 clock-names = "bi_tcxo", 4401 "gcc_gpu_gpll0_clk_src", 4402 "gcc_gpu_gpll0_div_clk_src"; 4403 #clock-cells = <1>; 4404 #reset-cells = <1>; 4405 #power-domain-cells = <1>; 4406 }; 4407 4408 adreno_smmu: iommu@3da0000 { 4409 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 4410 "qcom,smmu-500", "arm,mmu-500"; 4411 reg = <0x0 0x03da0000 0x0 0x20000>; 4412 #iommu-cells = <2>; 4413 #global-interrupts = <2>; 4414 dma-coherent; 4415 power-domains = <&gpucc GPU_CC_CX_GDSC>; 4416 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4417 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4418 <&gpucc GPU_CC_AHB_CLK>, 4419 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4420 <&gpucc GPU_CC_CX_GMU_CLK>, 4421 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4422 <&gpucc GPU_CC_HUB_AON_CLK>; 4423 clock-names = "gcc_gpu_memnoc_gfx_clk", 4424 "gcc_gpu_snoc_dvm_gfx_clk", 4425 "gpu_cc_ahb_clk", 4426 "gpu_cc_hlos1_vote_gpu_smmu_clk", 4427 "gpu_cc_cx_gmu_clk", 4428 "gpu_cc_hub_cx_int_clk", 4429 "gpu_cc_hub_aon_clk"; 4430 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 4431 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4432 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4433 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4434 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4435 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4436 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4437 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4438 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4439 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4440 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4441 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 4442 }; 4443 4444 serdes0: phy@8901000 { 4445 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4446 reg = <0x0 0x08901000 0x0 0xe10>; 4447 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4448 clock-names = "sgmi_ref"; 4449 #phy-cells = <0>; 4450 status = "disabled"; 4451 }; 4452 4453 serdes1: phy@8902000 { 4454 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 4455 reg = <0x0 0x08902000 0x0 0xe10>; 4456 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4457 clock-names = "sgmi_ref"; 4458 #phy-cells = <0>; 4459 status = "disabled"; 4460 }; 4461 4462 pmu@9091000 { 4463 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4464 reg = <0x0 0x9091000 0x0 0x1000>; 4465 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 4466 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 4467 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4468 4469 operating-points-v2 = <&llcc_bwmon_opp_table>; 4470 4471 llcc_bwmon_opp_table: opp-table { 4472 compatible = "operating-points-v2"; 4473 4474 opp-0 { 4475 opp-peak-kBps = <762000>; 4476 }; 4477 4478 opp-1 { 4479 opp-peak-kBps = <1720000>; 4480 }; 4481 4482 opp-2 { 4483 opp-peak-kBps = <2086000>; 4484 }; 4485 4486 opp-3 { 4487 opp-peak-kBps = <2601000>; 4488 }; 4489 4490 opp-4 { 4491 opp-peak-kBps = <2929000>; 4492 }; 4493 4494 opp-5 { 4495 opp-peak-kBps = <5931000>; 4496 }; 4497 4498 opp-6 { 4499 opp-peak-kBps = <6515000>; 4500 }; 4501 4502 opp-7 { 4503 opp-peak-kBps = <7984000>; 4504 }; 4505 4506 opp-8 { 4507 opp-peak-kBps = <10437000>; 4508 }; 4509 4510 opp-9 { 4511 opp-peak-kBps = <12195000>; 4512 }; 4513 }; 4514 }; 4515 4516 pmu@90b5400 { 4517 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4518 reg = <0x0 0x90b5400 0x0 0x600>; 4519 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4520 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4521 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4522 4523 operating-points-v2 = <&cpu_bwmon_opp_table>; 4524 4525 cpu_bwmon_opp_table: opp-table { 4526 compatible = "operating-points-v2"; 4527 4528 opp-0 { 4529 opp-peak-kBps = <9155000>; 4530 }; 4531 4532 opp-1 { 4533 opp-peak-kBps = <12298000>; 4534 }; 4535 4536 opp-2 { 4537 opp-peak-kBps = <14236000>; 4538 }; 4539 4540 opp-3 { 4541 opp-peak-kBps = <16265000>; 4542 }; 4543 }; 4544 4545 }; 4546 4547 pmu@90b6400 { 4548 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 4549 reg = <0x0 0x90b6400 0x0 0x600>; 4550 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4551 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4552 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4553 4554 operating-points-v2 = <&cpu_bwmon_opp_table>; 4555 }; 4556 4557 llcc: system-cache-controller@9200000 { 4558 compatible = "qcom,sa8775p-llcc"; 4559 reg = <0x0 0x09200000 0x0 0x80000>, 4560 <0x0 0x09300000 0x0 0x80000>, 4561 <0x0 0x09400000 0x0 0x80000>, 4562 <0x0 0x09500000 0x0 0x80000>, 4563 <0x0 0x09600000 0x0 0x80000>, 4564 <0x0 0x09700000 0x0 0x80000>, 4565 <0x0 0x09a00000 0x0 0x80000>; 4566 reg-names = "llcc0_base", 4567 "llcc1_base", 4568 "llcc2_base", 4569 "llcc3_base", 4570 "llcc4_base", 4571 "llcc5_base", 4572 "llcc_broadcast_base"; 4573 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 4574 }; 4575 4576 iris: video-codec@aa00000 { 4577 compatible = "qcom,sa8775p-iris", "qcom,sm8550-iris"; 4578 4579 reg = <0x0 0x0aa00000 0x0 0xf0000>; 4580 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4581 4582 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 4583 <&videocc VIDEO_CC_MVS0_GDSC>, 4584 <&rpmhpd SA8775P_MX>, 4585 <&rpmhpd SA8775P_MMCX>; 4586 power-domain-names = "venus", 4587 "vcodec0", 4588 "mxc", 4589 "mmcx"; 4590 operating-points-v2 = <&iris_opp_table>; 4591 4592 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4593 <&videocc VIDEO_CC_MVS0C_CLK>, 4594 <&videocc VIDEO_CC_MVS0_CLK>; 4595 clock-names = "iface", 4596 "core", 4597 "vcodec0_core"; 4598 4599 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4600 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4601 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4602 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4603 interconnect-names = "cpu-cfg", 4604 "video-mem"; 4605 4606 memory-region = <&pil_video_mem>; 4607 4608 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 4609 reset-names = "bus"; 4610 4611 iommus = <&apps_smmu 0x0880 0x0400>, 4612 <&apps_smmu 0x0887 0x0400>; 4613 dma-coherent; 4614 4615 status = "disabled"; 4616 4617 iris_opp_table: opp-table { 4618 compatible = "operating-points-v2"; 4619 4620 opp-366000000 { 4621 opp-hz = /bits/ 64 <366000000>; 4622 required-opps = <&rpmhpd_opp_svs_l1>, 4623 <&rpmhpd_opp_svs_l1>; 4624 }; 4625 4626 opp-444000000 { 4627 opp-hz = /bits/ 64 <444000000>; 4628 required-opps = <&rpmhpd_opp_nom>, 4629 <&rpmhpd_opp_nom>; 4630 }; 4631 4632 opp-533000000 { 4633 opp-hz = /bits/ 64 <533000000>; 4634 required-opps = <&rpmhpd_opp_turbo>, 4635 <&rpmhpd_opp_turbo>; 4636 }; 4637 4638 opp-560000000 { 4639 opp-hz = /bits/ 64 <560000000>; 4640 required-opps = <&rpmhpd_opp_turbo_l1>, 4641 <&rpmhpd_opp_turbo_l1>; 4642 }; 4643 }; 4644 }; 4645 4646 videocc: clock-controller@abf0000 { 4647 compatible = "qcom,sa8775p-videocc"; 4648 reg = <0x0 0x0abf0000 0x0 0x10000>; 4649 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4650 <&rpmhcc RPMH_CXO_CLK>, 4651 <&rpmhcc RPMH_CXO_CLK_A>, 4652 <&sleep_clk>; 4653 power-domains = <&rpmhpd SA8775P_MMCX>; 4654 #clock-cells = <1>; 4655 #reset-cells = <1>; 4656 #power-domain-cells = <1>; 4657 }; 4658 4659 cci0: cci@ac13000 { 4660 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4661 reg = <0x0 0x0ac13000 0x0 0x1000>; 4662 4663 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4664 4665 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4666 4667 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4668 <&camcc CAM_CC_CPAS_AHB_CLK>, 4669 <&camcc CAM_CC_CCI_0_CLK>; 4670 clock-names = "camnoc_axi", 4671 "cpas_ahb", 4672 "cci"; 4673 4674 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 4675 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 4676 pinctrl-names = "default", "sleep"; 4677 4678 #address-cells = <1>; 4679 #size-cells = <0>; 4680 4681 status = "disabled"; 4682 4683 cci0_i2c0: i2c-bus@0 { 4684 reg = <0>; 4685 clock-frequency = <1000000>; 4686 #address-cells = <1>; 4687 #size-cells = <0>; 4688 }; 4689 4690 cci0_i2c1: i2c-bus@1 { 4691 reg = <1>; 4692 clock-frequency = <1000000>; 4693 #address-cells = <1>; 4694 #size-cells = <0>; 4695 }; 4696 }; 4697 4698 cci1: cci@ac14000 { 4699 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4700 reg = <0x0 0x0ac14000 0x0 0x1000>; 4701 4702 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4703 4704 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4705 4706 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4707 <&camcc CAM_CC_CPAS_AHB_CLK>, 4708 <&camcc CAM_CC_CCI_1_CLK>; 4709 clock-names = "camnoc_axi", 4710 "cpas_ahb", 4711 "cci"; 4712 4713 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 4714 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 4715 pinctrl-names = "default", "sleep"; 4716 4717 #address-cells = <1>; 4718 #size-cells = <0>; 4719 4720 status = "disabled"; 4721 4722 cci1_i2c0: i2c-bus@0 { 4723 reg = <0>; 4724 clock-frequency = <1000000>; 4725 #address-cells = <1>; 4726 #size-cells = <0>; 4727 }; 4728 4729 cci1_i2c1: i2c-bus@1 { 4730 reg = <1>; 4731 clock-frequency = <1000000>; 4732 #address-cells = <1>; 4733 #size-cells = <0>; 4734 }; 4735 }; 4736 4737 cci2: cci@ac15000 { 4738 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4739 reg = <0x0 0x0ac15000 0x0 0x1000>; 4740 4741 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 4742 4743 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4744 4745 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4746 <&camcc CAM_CC_CPAS_AHB_CLK>, 4747 <&camcc CAM_CC_CCI_2_CLK>; 4748 clock-names = "camnoc_axi", 4749 "cpas_ahb", 4750 "cci"; 4751 4752 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 4753 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 4754 pinctrl-names = "default", "sleep"; 4755 4756 #address-cells = <1>; 4757 #size-cells = <0>; 4758 4759 status = "disabled"; 4760 4761 cci2_i2c0: i2c-bus@0 { 4762 reg = <0>; 4763 clock-frequency = <1000000>; 4764 #address-cells = <1>; 4765 #size-cells = <0>; 4766 }; 4767 4768 cci2_i2c1: i2c-bus@1 { 4769 reg = <1>; 4770 clock-frequency = <1000000>; 4771 #address-cells = <1>; 4772 #size-cells = <0>; 4773 }; 4774 }; 4775 4776 cci3: cci@ac16000 { 4777 compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci"; 4778 reg = <0x0 0x0ac16000 0x0 0x1000>; 4779 4780 interrupts = <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>; 4781 4782 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4783 4784 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4785 <&camcc CAM_CC_CPAS_AHB_CLK>, 4786 <&camcc CAM_CC_CCI_3_CLK>; 4787 clock-names = "camnoc_axi", 4788 "cpas_ahb", 4789 "cci"; 4790 4791 pinctrl-0 = <&cci3_0_default &cci3_1_default>; 4792 pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>; 4793 pinctrl-names = "default", "sleep"; 4794 4795 #address-cells = <1>; 4796 #size-cells = <0>; 4797 4798 status = "disabled"; 4799 4800 cci3_i2c0: i2c-bus@0 { 4801 reg = <0>; 4802 clock-frequency = <1000000>; 4803 #address-cells = <1>; 4804 #size-cells = <0>; 4805 }; 4806 4807 cci3_i2c1: i2c-bus@1 { 4808 reg = <1>; 4809 clock-frequency = <1000000>; 4810 #address-cells = <1>; 4811 #size-cells = <0>; 4812 }; 4813 }; 4814 4815 camss: isp@ac78000 { 4816 compatible = "qcom,sa8775p-camss"; 4817 4818 reg = <0x0 0xac78000 0x0 0x1000>, 4819 <0x0 0xac7a000 0x0 0x0f00>, 4820 <0x0 0xac7c000 0x0 0x0f00>, 4821 <0x0 0xac84000 0x0 0x0f00>, 4822 <0x0 0xac88000 0x0 0x0f00>, 4823 <0x0 0xac8c000 0x0 0x0f00>, 4824 <0x0 0xac90000 0x0 0x0f00>, 4825 <0x0 0xac94000 0x0 0x0f00>, 4826 <0x0 0xac9c000 0x0 0x2000>, 4827 <0x0 0xac9e000 0x0 0x2000>, 4828 <0x0 0xaca0000 0x0 0x2000>, 4829 <0x0 0xaca2000 0x0 0x2000>, 4830 <0x0 0xacac000 0x0 0x0400>, 4831 <0x0 0xacad000 0x0 0x0400>, 4832 <0x0 0xacae000 0x0 0x0400>, 4833 <0x0 0xac4d000 0x0 0xd000>, 4834 <0x0 0xac5a000 0x0 0xd000>, 4835 <0x0 0xac85000 0x0 0x0d00>, 4836 <0x0 0xac89000 0x0 0x0d00>, 4837 <0x0 0xac8d000 0x0 0x0d00>, 4838 <0x0 0xac91000 0x0 0x0d00>, 4839 <0x0 0xac95000 0x0 0x0d00>; 4840 reg-names = "csid_wrapper", 4841 "csid0", 4842 "csid1", 4843 "csid_lite0", 4844 "csid_lite1", 4845 "csid_lite2", 4846 "csid_lite3", 4847 "csid_lite4", 4848 "csiphy0", 4849 "csiphy1", 4850 "csiphy2", 4851 "csiphy3", 4852 "tpg0", 4853 "tpg1", 4854 "tpg2", 4855 "vfe0", 4856 "vfe1", 4857 "vfe_lite0", 4858 "vfe_lite1", 4859 "vfe_lite2", 4860 "vfe_lite3", 4861 "vfe_lite4"; 4862 4863 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4864 <&camcc CAM_CC_CORE_AHB_CLK>, 4865 <&camcc CAM_CC_CPAS_AHB_CLK>, 4866 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 4867 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 4868 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 4869 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 4870 <&camcc CAM_CC_CSID_CLK>, 4871 <&camcc CAM_CC_CSIPHY0_CLK>, 4872 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4873 <&camcc CAM_CC_CSIPHY1_CLK>, 4874 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4875 <&camcc CAM_CC_CSIPHY2_CLK>, 4876 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4877 <&camcc CAM_CC_CSIPHY3_CLK>, 4878 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4879 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 4880 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4881 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4882 <&camcc CAM_CC_ICP_AHB_CLK>, 4883 <&camcc CAM_CC_IFE_0_CLK>, 4884 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 4885 <&camcc CAM_CC_IFE_1_CLK>, 4886 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 4887 <&camcc CAM_CC_IFE_LITE_CLK>, 4888 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4889 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4890 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4891 clock-names = "camnoc_axi", 4892 "core_ahb", 4893 "cpas_ahb", 4894 "cpas_fast_ahb_clk", 4895 "cpas_vfe_lite", 4896 "cpas_vfe0", 4897 "cpas_vfe1", 4898 "csid", 4899 "csiphy0", 4900 "csiphy0_timer", 4901 "csiphy1", 4902 "csiphy1_timer", 4903 "csiphy2", 4904 "csiphy2_timer", 4905 "csiphy3", 4906 "csiphy3_timer", 4907 "csiphy_rx", 4908 "gcc_axi_hf", 4909 "gcc_axi_sf", 4910 "icp_ahb", 4911 "vfe0", 4912 "vfe0_fast_ahb", 4913 "vfe1", 4914 "vfe1_fast_ahb", 4915 "vfe_lite", 4916 "vfe_lite_ahb", 4917 "vfe_lite_cphy_rx", 4918 "vfe_lite_csid"; 4919 4920 interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, 4921 <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, 4922 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4923 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4924 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 4925 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 4926 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 4927 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4928 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4929 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4930 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4931 <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, 4932 <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, 4933 <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, 4934 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4935 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4936 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4937 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 4938 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 4939 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 4940 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; 4941 interrupt-names = "csid0", 4942 "csid1", 4943 "csid_lite0", 4944 "csid_lite1", 4945 "csid_lite2", 4946 "csid_lite3", 4947 "csid_lite4", 4948 "csiphy0", 4949 "csiphy1", 4950 "csiphy2", 4951 "csiphy3", 4952 "tpg0", 4953 "tpg1", 4954 "tpg2", 4955 "vfe0", 4956 "vfe1", 4957 "vfe_lite0", 4958 "vfe_lite1", 4959 "vfe_lite2", 4960 "vfe_lite3", 4961 "vfe_lite4"; 4962 4963 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4964 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4965 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 4966 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4967 interconnect-names = "ahb", 4968 "hf_0"; 4969 4970 iommus = <&apps_smmu 0x3400 0x20>; 4971 4972 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4973 power-domain-names = "top"; 4974 4975 status = "disabled"; 4976 4977 ports { 4978 #address-cells = <1>; 4979 #size-cells = <0>; 4980 4981 port@0 { 4982 reg = <0>; 4983 }; 4984 4985 port@1 { 4986 reg = <1>; 4987 }; 4988 4989 port@2 { 4990 reg = <2>; 4991 }; 4992 4993 port@3 { 4994 reg = <3>; 4995 }; 4996 }; 4997 }; 4998 4999 camcc: clock-controller@ade0000 { 5000 compatible = "qcom,sa8775p-camcc"; 5001 reg = <0x0 0x0ade0000 0x0 0x20000>; 5002 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5003 <&rpmhcc RPMH_CXO_CLK>, 5004 <&rpmhcc RPMH_CXO_CLK_A>, 5005 <&sleep_clk>; 5006 power-domains = <&rpmhpd SA8775P_MMCX>; 5007 #clock-cells = <1>; 5008 #reset-cells = <1>; 5009 #power-domain-cells = <1>; 5010 }; 5011 5012 mdss0: display-subsystem@ae00000 { 5013 compatible = "qcom,sa8775p-mdss"; 5014 reg = <0x0 0x0ae00000 0x0 0x1000>; 5015 reg-names = "mdss"; 5016 5017 /* same path used twice */ 5018 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 5019 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5020 <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS 5021 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5022 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5023 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5024 interconnect-names = "mdp0-mem", 5025 "mdp1-mem", 5026 "cpu-cfg"; 5027 5028 resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; 5029 5030 power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; 5031 5032 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5033 <&gcc GCC_DISP_HF_AXI_CLK>, 5034 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; 5035 5036 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 5037 interrupt-controller; 5038 #interrupt-cells = <1>; 5039 5040 iommus = <&apps_smmu 0x1000 0x402>; 5041 5042 #address-cells = <2>; 5043 #size-cells = <2>; 5044 ranges; 5045 5046 status = "disabled"; 5047 5048 mdss0_mdp: display-controller@ae01000 { 5049 compatible = "qcom,sa8775p-dpu"; 5050 reg = <0x0 0x0ae01000 0x0 0x8f000>, 5051 <0x0 0x0aeb0000 0x0 0x3000>; 5052 reg-names = "mdp", "vbif"; 5053 5054 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5055 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5056 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 5057 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, 5058 <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5059 clock-names = "nrt_bus", 5060 "iface", 5061 "lut", 5062 "core", 5063 "vsync"; 5064 5065 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5066 assigned-clock-rates = <19200000>; 5067 5068 operating-points-v2 = <&mdss0_mdp_opp_table>; 5069 power-domains = <&rpmhpd SA8775P_MMCX>; 5070 5071 interrupt-parent = <&mdss0>; 5072 interrupts = <0>; 5073 5074 ports { 5075 #address-cells = <1>; 5076 #size-cells = <0>; 5077 5078 port@0 { 5079 reg = <0>; 5080 5081 dpu_intf0_out: endpoint { 5082 remote-endpoint = <&mdss0_dp0_in>; 5083 }; 5084 }; 5085 5086 port@1 { 5087 reg = <1>; 5088 5089 dpu_intf4_out: endpoint { 5090 remote-endpoint = <&mdss0_dp1_in>; 5091 }; 5092 }; 5093 5094 port@2 { 5095 reg = <2>; 5096 5097 dpu_intf1_out: endpoint { 5098 remote-endpoint = <&mdss0_dsi0_in>; 5099 }; 5100 }; 5101 5102 port@3 { 5103 reg = <3>; 5104 5105 dpu_intf2_out: endpoint { 5106 remote-endpoint = <&mdss0_dsi1_in>; 5107 }; 5108 }; 5109 }; 5110 5111 mdss0_mdp_opp_table: opp-table { 5112 compatible = "operating-points-v2"; 5113 5114 opp-375000000 { 5115 opp-hz = /bits/ 64 <375000000>; 5116 required-opps = <&rpmhpd_opp_svs_l1>; 5117 }; 5118 5119 opp-500000000 { 5120 opp-hz = /bits/ 64 <500000000>; 5121 required-opps = <&rpmhpd_opp_nom>; 5122 }; 5123 5124 opp-575000000 { 5125 opp-hz = /bits/ 64 <575000000>; 5126 required-opps = <&rpmhpd_opp_turbo>; 5127 }; 5128 5129 opp-650000000 { 5130 opp-hz = /bits/ 64 <650000000>; 5131 required-opps = <&rpmhpd_opp_turbo_l1>; 5132 }; 5133 }; 5134 }; 5135 5136 mdss0_dsi0: dsi@ae94000 { 5137 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5138 reg = <0x0 0x0ae94000 0x0 0x400>; 5139 reg-names = "dsi_ctrl"; 5140 5141 interrupt-parent = <&mdss0>; 5142 interrupts = <4>; 5143 5144 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK>, 5145 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, 5146 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK>, 5147 <&dispcc0 MDSS_DISP_CC_MDSS_ESC0_CLK>, 5148 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5149 <&gcc GCC_DISP_HF_AXI_CLK>; 5150 clock-names = "byte", 5151 "byte_intf", 5152 "pixel", 5153 "core", 5154 "iface", 5155 "bus"; 5156 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, 5157 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; 5158 assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 5159 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; 5160 phys = <&mdss0_dsi0_phy>; 5161 5162 operating-points-v2 = <&mdss_dsi_opp_table>; 5163 power-domains = <&rpmhpd SA8775P_MMCX>; 5164 5165 refgen-supply = <&refgen>; 5166 5167 #address-cells = <1>; 5168 #size-cells = <0>; 5169 5170 status = "disabled"; 5171 5172 ports { 5173 #address-cells = <1>; 5174 #size-cells = <0>; 5175 5176 port@0 { 5177 reg = <0>; 5178 5179 mdss0_dsi0_in: endpoint { 5180 remote-endpoint = <&dpu_intf1_out>; 5181 }; 5182 }; 5183 5184 port@1 { 5185 reg = <1>; 5186 5187 mdss0_dsi0_out: endpoint { }; 5188 }; 5189 }; 5190 5191 mdss_dsi_opp_table: opp-table { 5192 compatible = "operating-points-v2"; 5193 5194 opp-358000000 { 5195 opp-hz = /bits/ 64 <358000000>; 5196 required-opps = <&rpmhpd_opp_svs_l1>; 5197 }; 5198 }; 5199 }; 5200 5201 mdss0_dsi0_phy: phy@ae94400 { 5202 compatible = "qcom,sa8775p-dsi-phy-5nm"; 5203 reg = <0x0 0x0ae94400 0x0 0x200>, 5204 <0x0 0x0ae94600 0x0 0x280>, 5205 <0x0 0x0ae94900 0x0 0x27c>; 5206 reg-names = "dsi_phy", 5207 "dsi_phy_lane", 5208 "dsi_pll"; 5209 5210 #clock-cells = <1>; 5211 #phy-cells = <0>; 5212 5213 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5214 <&rpmhcc RPMH_CXO_CLK>; 5215 clock-names = "iface", "ref"; 5216 5217 status = "disabled"; 5218 }; 5219 5220 mdss0_dsi1: dsi@ae96000 { 5221 compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 5222 reg = <0x0 0x0ae96000 0x0 0x400>; 5223 reg-names = "dsi_ctrl"; 5224 5225 interrupt-parent = <&mdss0>; 5226 interrupts = <5>; 5227 5228 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK>, 5229 <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK>, 5230 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK>, 5231 <&dispcc0 MDSS_DISP_CC_MDSS_ESC1_CLK>, 5232 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5233 <&gcc GCC_DISP_HF_AXI_CLK>; 5234 clock-names = "byte", 5235 "byte_intf", 5236 "pixel", 5237 "core", 5238 "iface", 5239 "bus"; 5240 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC>, 5241 <&dispcc0 MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC>; 5242 assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5243 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5244 phys = <&mdss0_dsi1_phy>; 5245 5246 operating-points-v2 = <&mdss_dsi_opp_table>; 5247 power-domains = <&rpmhpd SA8775P_MMCX>; 5248 5249 refgen-supply = <&refgen>; 5250 5251 #address-cells = <1>; 5252 #size-cells = <0>; 5253 5254 status = "disabled"; 5255 5256 ports { 5257 #address-cells = <1>; 5258 #size-cells = <0>; 5259 5260 port@0 { 5261 reg = <0>; 5262 5263 mdss0_dsi1_in: endpoint { 5264 remote-endpoint = <&dpu_intf2_out>; 5265 }; 5266 }; 5267 5268 port@1 { 5269 reg = <1>; 5270 5271 mdss0_dsi1_out: endpoint { }; 5272 }; 5273 }; 5274 }; 5275 5276 mdss0_dsi1_phy: phy@ae96400 { 5277 compatible = "qcom,sa8775p-dsi-phy-5nm"; 5278 reg = <0x0 0x0ae96400 0x0 0x200>, 5279 <0x0 0x0ae96600 0x0 0x280>, 5280 <0x0 0x0ae96900 0x0 0x27c>; 5281 reg-names = "dsi_phy", 5282 "dsi_phy_lane", 5283 "dsi_pll"; 5284 5285 #clock-cells = <1>; 5286 #phy-cells = <0>; 5287 5288 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5289 <&rpmhcc RPMH_CXO_CLK>; 5290 clock-names = "iface", "ref"; 5291 5292 status = "disabled"; 5293 }; 5294 5295 mdss0_dp0_phy: phy@aec2a00 { 5296 compatible = "qcom,sa8775p-edp-phy"; 5297 5298 reg = <0x0 0x0aec2a00 0x0 0x200>, 5299 <0x0 0x0aec2200 0x0 0xd0>, 5300 <0x0 0x0aec2600 0x0 0xd0>, 5301 <0x0 0x0aec2000 0x0 0x1c8>; 5302 5303 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5304 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; 5305 clock-names = "aux", 5306 "cfg_ahb"; 5307 5308 #clock-cells = <1>; 5309 #phy-cells = <0>; 5310 5311 status = "disabled"; 5312 }; 5313 5314 mdss0_dp1_phy: phy@aec5a00 { 5315 compatible = "qcom,sa8775p-edp-phy"; 5316 5317 reg = <0x0 0x0aec5a00 0x0 0x200>, 5318 <0x0 0x0aec5200 0x0 0xd0>, 5319 <0x0 0x0aec5600 0x0 0xd0>, 5320 <0x0 0x0aec5000 0x0 0x1c8>; 5321 5322 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 5323 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; 5324 clock-names = "aux", 5325 "cfg_ahb"; 5326 5327 #clock-cells = <1>; 5328 #phy-cells = <0>; 5329 5330 status = "disabled"; 5331 }; 5332 5333 mdss0_dp0: displayport-controller@af54000 { 5334 compatible = "qcom,sa8775p-dp"; 5335 5336 reg = <0x0 0x0af54000 0x0 0x104>, 5337 <0x0 0x0af54200 0x0 0x0c0>, 5338 <0x0 0x0af55000 0x0 0x770>, 5339 <0x0 0x0af56000 0x0 0x09c>, 5340 <0x0 0x0af57000 0x0 0x09c>, 5341 <0x0 0x0af58000 0x0 0x09c>, 5342 <0x0 0x0af59000 0x0 0x09c>, 5343 <0x0 0x0af5a000 0x0 0x23c>, 5344 <0x0 0x0af5b000 0x0 0x23c>; 5345 5346 interrupt-parent = <&mdss0>; 5347 interrupts = <12>; 5348 5349 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5350 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5351 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 5352 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5353 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5354 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, 5355 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, 5356 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; 5357 clock-names = "core_iface", 5358 "core_aux", 5359 "ctrl_link", 5360 "ctrl_link_iface", 5361 "stream_pixel", 5362 "stream_1_pixel", 5363 "stream_2_pixel", 5364 "stream_3_pixel"; 5365 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5366 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5367 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, 5368 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, 5369 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; 5370 assigned-clock-parents = <&mdss0_dp0_phy 0>, 5371 <&mdss0_dp0_phy 1>, 5372 <&mdss0_dp0_phy 1>, 5373 <&mdss0_dp0_phy 1>, 5374 <&mdss0_dp0_phy 1>; 5375 phys = <&mdss0_dp0_phy>; 5376 phy-names = "dp"; 5377 5378 operating-points-v2 = <&dp_opp_table>; 5379 power-domains = <&rpmhpd SA8775P_MMCX>; 5380 5381 #sound-dai-cells = <0>; 5382 5383 status = "disabled"; 5384 5385 ports { 5386 #address-cells = <1>; 5387 #size-cells = <0>; 5388 5389 port@0 { 5390 reg = <0>; 5391 5392 mdss0_dp0_in: endpoint { 5393 remote-endpoint = <&dpu_intf0_out>; 5394 }; 5395 }; 5396 5397 port@1 { 5398 reg = <1>; 5399 5400 mdss0_dp0_out: endpoint { }; 5401 }; 5402 }; 5403 5404 dp_opp_table: opp-table { 5405 compatible = "operating-points-v2"; 5406 5407 opp-160000000 { 5408 opp-hz = /bits/ 64 <160000000>; 5409 required-opps = <&rpmhpd_opp_low_svs>; 5410 }; 5411 5412 opp-270000000 { 5413 opp-hz = /bits/ 64 <270000000>; 5414 required-opps = <&rpmhpd_opp_svs>; 5415 }; 5416 5417 opp-540000000 { 5418 opp-hz = /bits/ 64 <540000000>; 5419 required-opps = <&rpmhpd_opp_svs_l1>; 5420 }; 5421 5422 opp-810000000 { 5423 opp-hz = /bits/ 64 <810000000>; 5424 required-opps = <&rpmhpd_opp_nom>; 5425 }; 5426 }; 5427 }; 5428 5429 mdss0_dp1: displayport-controller@af5c000 { 5430 compatible = "qcom,sa8775p-dp"; 5431 5432 reg = <0x0 0x0af5c000 0x0 0x104>, 5433 <0x0 0x0af5c200 0x0 0x0c0>, 5434 <0x0 0x0af5d000 0x0 0x770>, 5435 <0x0 0x0af5e000 0x0 0x09c>, 5436 <0x0 0x0af5f000 0x0 0x09c>, 5437 <0x0 0x0af60000 0x0 0x09c>, 5438 <0x0 0x0af61000 0x0 0x09c>, 5439 <0x0 0x0af62000 0x0 0x23c>, 5440 <0x0 0x0af63000 0x0 0x23c>; 5441 5442 interrupt-parent = <&mdss0>; 5443 interrupts = <13>; 5444 5445 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 5446 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 5447 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, 5448 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5449 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5450 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5451 clock-names = "core_iface", 5452 "core_aux", 5453 "ctrl_link", 5454 "ctrl_link_iface", 5455 "stream_pixel", 5456 "stream_1_pixel"; 5457 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5458 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5459 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5460 assigned-clock-parents = <&mdss0_dp1_phy 0>, 5461 <&mdss0_dp1_phy 1>, 5462 <&mdss0_dp1_phy 1>; 5463 phys = <&mdss0_dp1_phy>; 5464 phy-names = "dp"; 5465 5466 operating-points-v2 = <&dp1_opp_table>; 5467 power-domains = <&rpmhpd SA8775P_MMCX>; 5468 5469 #sound-dai-cells = <0>; 5470 5471 status = "disabled"; 5472 5473 ports { 5474 #address-cells = <1>; 5475 #size-cells = <0>; 5476 5477 port@0 { 5478 reg = <0>; 5479 5480 mdss0_dp1_in: endpoint { 5481 remote-endpoint = <&dpu_intf4_out>; 5482 }; 5483 }; 5484 5485 port@1 { 5486 reg = <1>; 5487 5488 mdss0_dp1_out: endpoint { }; 5489 }; 5490 }; 5491 5492 dp1_opp_table: opp-table { 5493 compatible = "operating-points-v2"; 5494 5495 opp-160000000 { 5496 opp-hz = /bits/ 64 <160000000>; 5497 required-opps = <&rpmhpd_opp_low_svs>; 5498 }; 5499 5500 opp-270000000 { 5501 opp-hz = /bits/ 64 <270000000>; 5502 required-opps = <&rpmhpd_opp_svs>; 5503 }; 5504 5505 opp-540000000 { 5506 opp-hz = /bits/ 64 <540000000>; 5507 required-opps = <&rpmhpd_opp_svs_l1>; 5508 }; 5509 5510 opp-810000000 { 5511 opp-hz = /bits/ 64 <810000000>; 5512 required-opps = <&rpmhpd_opp_nom>; 5513 }; 5514 }; 5515 }; 5516 }; 5517 5518 dispcc0: clock-controller@af00000 { 5519 compatible = "qcom,sa8775p-dispcc0"; 5520 reg = <0x0 0x0af00000 0x0 0x20000>; 5521 clocks = <&gcc GCC_DISP_AHB_CLK>, 5522 <&rpmhcc RPMH_CXO_CLK>, 5523 <&rpmhcc RPMH_CXO_CLK_A>, 5524 <&sleep_clk>, 5525 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, 5526 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>, 5527 <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 5528 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, 5529 <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5530 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5531 power-domains = <&rpmhpd SA8775P_MMCX>; 5532 #clock-cells = <1>; 5533 #reset-cells = <1>; 5534 #power-domain-cells = <1>; 5535 }; 5536 5537 pdc: interrupt-controller@b220000 { 5538 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 5539 reg = <0x0 0x0b220000 0x0 0x30000>, 5540 <0x0 0x17c000f0 0x0 0x64>; 5541 qcom,pdc-ranges = <0 480 40>, 5542 <40 140 14>, 5543 <54 263 1>, 5544 <55 306 4>, 5545 <59 312 3>, 5546 <62 374 2>, 5547 <64 434 2>, 5548 <66 438 2>, 5549 <70 520 1>, 5550 <73 523 1>, 5551 <118 568 6>, 5552 <124 609 3>, 5553 <159 638 1>, 5554 <160 720 3>, 5555 <169 728 30>, 5556 <199 416 2>, 5557 <201 449 1>, 5558 <202 89 1>, 5559 <203 451 1>, 5560 <204 462 1>, 5561 <205 264 1>, 5562 <206 579 1>, 5563 <207 653 1>, 5564 <208 656 1>, 5565 <209 659 1>, 5566 <210 122 1>, 5567 <211 699 1>, 5568 <212 705 1>, 5569 <213 450 1>, 5570 <214 643 2>, 5571 <216 646 5>, 5572 <221 390 5>, 5573 <226 700 2>, 5574 <228 440 1>, 5575 <229 663 1>, 5576 <230 524 2>, 5577 <232 612 3>, 5578 <235 723 5>; 5579 #interrupt-cells = <2>; 5580 interrupt-parent = <&intc>; 5581 interrupt-controller; 5582 }; 5583 5584 tsens2: thermal-sensor@c251000 { 5585 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5586 reg = <0x0 0x0c251000 0x0 0x1ff>, 5587 <0x0 0x0c224000 0x0 0x8>; 5588 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 5589 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 5590 #qcom,sensors = <13>; 5591 interrupt-names = "uplow", "critical"; 5592 #thermal-sensor-cells = <1>; 5593 }; 5594 5595 tsens3: thermal-sensor@c252000 { 5596 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5597 reg = <0x0 0x0c252000 0x0 0x1ff>, 5598 <0x0 0x0c225000 0x0 0x8>; 5599 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 5600 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 5601 #qcom,sensors = <13>; 5602 interrupt-names = "uplow", "critical"; 5603 #thermal-sensor-cells = <1>; 5604 }; 5605 5606 tsens0: thermal-sensor@c263000 { 5607 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5608 reg = <0x0 0x0c263000 0x0 0x1ff>, 5609 <0x0 0x0c222000 0x0 0x8>; 5610 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5611 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5612 #qcom,sensors = <12>; 5613 interrupt-names = "uplow", "critical"; 5614 #thermal-sensor-cells = <1>; 5615 }; 5616 5617 tsens1: thermal-sensor@c265000 { 5618 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 5619 reg = <0x0 0x0c265000 0x0 0x1ff>, 5620 <0x0 0x0c223000 0x0 0x8>; 5621 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5622 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5623 #qcom,sensors = <12>; 5624 interrupt-names = "uplow", "critical"; 5625 #thermal-sensor-cells = <1>; 5626 }; 5627 5628 aoss_qmp: power-management@c300000 { 5629 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 5630 reg = <0x0 0x0c300000 0x0 0x400>; 5631 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5632 IPCC_MPROC_SIGNAL_GLINK_QMP 5633 IRQ_TYPE_EDGE_RISING>; 5634 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5635 #clock-cells = <0>; 5636 }; 5637 5638 sram@c3f0000 { 5639 compatible = "qcom,rpmh-stats"; 5640 reg = <0x0 0x0c3f0000 0x0 0x400>; 5641 }; 5642 5643 spmi_bus: spmi@c440000 { 5644 compatible = "qcom,spmi-pmic-arb"; 5645 reg = <0x0 0x0c440000 0x0 0x1100>, 5646 <0x0 0x0c600000 0x0 0x2000000>, 5647 <0x0 0x0e600000 0x0 0x100000>, 5648 <0x0 0x0e700000 0x0 0xa0000>, 5649 <0x0 0x0c40a000 0x0 0x26000>; 5650 reg-names = "core", 5651 "chnls", 5652 "obsrvr", 5653 "intr", 5654 "cnfg"; 5655 qcom,channel = <0>; 5656 qcom,ee = <0>; 5657 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5658 interrupt-names = "periph_irq"; 5659 interrupt-controller; 5660 #interrupt-cells = <4>; 5661 #address-cells = <2>; 5662 #size-cells = <0>; 5663 }; 5664 5665 tlmm: pinctrl@f000000 { 5666 compatible = "qcom,sa8775p-tlmm"; 5667 reg = <0x0 0x0f000000 0x0 0x1000000>; 5668 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5669 gpio-controller; 5670 #gpio-cells = <2>; 5671 interrupt-controller; 5672 #interrupt-cells = <2>; 5673 gpio-ranges = <&tlmm 0 0 149>; 5674 wakeup-parent = <&pdc>; 5675 5676 dp0_hot_plug_det: dp0-hot-plug-det-state { 5677 pins = "gpio101"; 5678 function = "edp0_hot"; 5679 bias-disable; 5680 }; 5681 5682 dp1_hot_plug_det: dp1-hot-plug-det-state { 5683 pins = "gpio102"; 5684 function = "edp1_hot"; 5685 bias-disable; 5686 }; 5687 5688 hs0_mi2s_active: hs0-mi2s-active-state { 5689 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 5690 function = "hs0_mi2s"; 5691 drive-strength = <8>; 5692 bias-disable; 5693 }; 5694 5695 hs2_mi2s_active: hs2-mi2s-active-state { 5696 pins = "gpio122", "gpio123", "gpio124", "gpio125"; 5697 function = "hs2_mi2s"; 5698 drive-strength = <8>; 5699 bias-disable; 5700 }; 5701 5702 cci0_0_default: cci0-0-default-state { 5703 pins = "gpio60", "gpio61"; 5704 function = "cci_i2c"; 5705 drive-strength = <2>; 5706 bias-pull-up = <2200>; 5707 }; 5708 5709 cci0_0_sleep: cci0-0-sleep-state { 5710 pins = "gpio60", "gpio61"; 5711 function = "cci_i2c"; 5712 drive-strength = <2>; 5713 bias-pull-down; 5714 }; 5715 5716 cci0_1_default: cci0-1-default-state { 5717 pins = "gpio52", "gpio53"; 5718 function = "cci_i2c"; 5719 drive-strength = <2>; 5720 bias-pull-up = <2200>; 5721 }; 5722 5723 cci0_1_sleep: cci0-1-sleep-state { 5724 pins = "gpio52", "gpio53"; 5725 function = "cci_i2c"; 5726 drive-strength = <2>; 5727 bias-pull-down; 5728 }; 5729 5730 cci1_0_default: cci1-0-default-state { 5731 pins = "gpio62", "gpio63"; 5732 function = "cci_i2c"; 5733 drive-strength = <2>; 5734 bias-pull-up = <2200>; 5735 }; 5736 5737 cci1_0_sleep: cci1-0-sleep-state { 5738 pins = "gpio62", "gpio63"; 5739 function = "cci_i2c"; 5740 drive-strength = <2>; 5741 bias-pull-down; 5742 }; 5743 5744 cci1_1_default: cci1-1-default-state { 5745 pins = "gpio54", "gpio55"; 5746 function = "cci_i2c"; 5747 drive-strength = <2>; 5748 bias-pull-up = <2200>; 5749 }; 5750 5751 cci1_1_sleep: cci1-1-sleep-state { 5752 pins = "gpio54", "gpio55"; 5753 function = "cci_i2c"; 5754 drive-strength = <2>; 5755 bias-pull-down; 5756 }; 5757 5758 cci2_0_default: cci2-0-default-state { 5759 pins = "gpio64", "gpio65"; 5760 function = "cci_i2c"; 5761 drive-strength = <2>; 5762 bias-pull-up = <2200>; 5763 }; 5764 5765 cci2_0_sleep: cci2-0-sleep-state { 5766 pins = "gpio64", "gpio65"; 5767 function = "cci_i2c"; 5768 drive-strength = <2>; 5769 bias-pull-down; 5770 }; 5771 5772 cci2_1_default: cci2-1-default-state { 5773 pins = "gpio56", "gpio57"; 5774 function = "cci_i2c"; 5775 drive-strength = <2>; 5776 bias-pull-up = <2200>; 5777 }; 5778 5779 cci2_1_sleep: cci2-1-sleep-state { 5780 pins = "gpio56", "gpio57"; 5781 function = "cci_i2c"; 5782 drive-strength = <2>; 5783 bias-pull-down; 5784 }; 5785 5786 cci3_0_default: cci3-0-default-state { 5787 pins = "gpio66", "gpio67"; 5788 function = "cci_i2c"; 5789 drive-strength = <2>; 5790 bias-pull-up = <2200>; 5791 }; 5792 5793 cci3_0_sleep: cci3-0-sleep-state { 5794 pins = "gpio66", "gpio67"; 5795 function = "cci_i2c"; 5796 drive-strength = <2>; 5797 bias-pull-down; 5798 }; 5799 5800 cci3_1_default: cci3-1-default-state { 5801 pins = "gpio58", "gpio59"; 5802 function = "cci_i2c"; 5803 drive-strength = <2>; 5804 bias-pull-up = <2200>; 5805 }; 5806 5807 cci3_1_sleep: cci3-1-sleep-state { 5808 pins = "gpio58", "gpio59"; 5809 function = "cci_i2c"; 5810 drive-strength = <2>; 5811 bias-pull-down; 5812 }; 5813 5814 qup_i2c0_default: qup-i2c0-state { 5815 pins = "gpio20", "gpio21"; 5816 function = "qup0_se0"; 5817 }; 5818 5819 qup_i2c1_default: qup-i2c1-state { 5820 pins = "gpio24", "gpio25"; 5821 function = "qup0_se1"; 5822 }; 5823 5824 qup_i2c2_default: qup-i2c2-state { 5825 pins = "gpio36", "gpio37"; 5826 function = "qup0_se2"; 5827 }; 5828 5829 qup_i2c3_default: qup-i2c3-state { 5830 pins = "gpio28", "gpio29"; 5831 function = "qup0_se3"; 5832 }; 5833 5834 qup_i2c4_default: qup-i2c4-state { 5835 pins = "gpio32", "gpio33"; 5836 function = "qup0_se4"; 5837 }; 5838 5839 qup_i2c5_default: qup-i2c5-state { 5840 pins = "gpio36", "gpio37"; 5841 function = "qup0_se5"; 5842 }; 5843 5844 qup_i2c7_default: qup-i2c7-state { 5845 pins = "gpio40", "gpio41"; 5846 function = "qup1_se0"; 5847 }; 5848 5849 qup_i2c8_default: qup-i2c8-state { 5850 pins = "gpio42", "gpio43"; 5851 function = "qup1_se1"; 5852 }; 5853 5854 qup_i2c9_default: qup-i2c9-state { 5855 pins = "gpio46", "gpio47"; 5856 function = "qup1_se2"; 5857 }; 5858 5859 qup_i2c10_default: qup-i2c10-state { 5860 pins = "gpio44", "gpio45"; 5861 function = "qup1_se3"; 5862 }; 5863 5864 qup_i2c11_default: qup-i2c11-state { 5865 pins = "gpio48", "gpio49"; 5866 function = "qup1_se4"; 5867 }; 5868 5869 qup_i2c12_default: qup-i2c12-state { 5870 pins = "gpio52", "gpio53"; 5871 function = "qup1_se5"; 5872 }; 5873 5874 qup_i2c13_default: qup-i2c13-state { 5875 pins = "gpio56", "gpio57"; 5876 function = "qup1_se6"; 5877 }; 5878 5879 qup_i2c14_default: qup-i2c14-state { 5880 pins = "gpio80", "gpio81"; 5881 function = "qup2_se0"; 5882 }; 5883 5884 qup_i2c15_default: qup-i2c15-state { 5885 pins = "gpio84", "gpio85"; 5886 function = "qup2_se1"; 5887 }; 5888 5889 qup_i2c16_default: qup-i2c16-state { 5890 pins = "gpio86", "gpio87"; 5891 function = "qup2_se2"; 5892 }; 5893 5894 qup_i2c17_default: qup-i2c17-state { 5895 pins = "gpio91", "gpio92"; 5896 function = "qup2_se3"; 5897 }; 5898 5899 qup_i2c18_default: qup-i2c18-state { 5900 pins = "gpio95", "gpio96"; 5901 function = "qup2_se4"; 5902 }; 5903 5904 qup_i2c19_default: qup-i2c19-state { 5905 pins = "gpio99", "gpio100"; 5906 function = "qup2_se5"; 5907 }; 5908 5909 qup_i2c20_default: qup-i2c20-state { 5910 pins = "gpio97", "gpio98"; 5911 function = "qup2_se6"; 5912 }; 5913 5914 qup_i2c21_default: qup-i2c21-state { 5915 pins = "gpio13", "gpio14"; 5916 function = "qup3_se0"; 5917 }; 5918 5919 qup_spi0_default: qup-spi0-state { 5920 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 5921 function = "qup0_se0"; 5922 }; 5923 5924 qup_spi1_default: qup-spi1-state { 5925 pins = "gpio24", "gpio25", "gpio26", "gpio27"; 5926 function = "qup0_se1"; 5927 }; 5928 5929 qup_spi2_default: qup-spi2-state { 5930 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 5931 function = "qup0_se2"; 5932 }; 5933 5934 qup_spi3_default: qup-spi3-state { 5935 pins = "gpio28", "gpio29", "gpio30", "gpio31"; 5936 function = "qup0_se3"; 5937 }; 5938 5939 qup_spi4_default: qup-spi4-state { 5940 pins = "gpio32", "gpio33", "gpio34", "gpio35"; 5941 function = "qup0_se4"; 5942 }; 5943 5944 qup_spi5_default: qup-spi5-state { 5945 pins = "gpio36", "gpio37", "gpio38", "gpio39"; 5946 function = "qup0_se5"; 5947 }; 5948 5949 qup_spi7_default: qup-spi7-state { 5950 pins = "gpio40", "gpio41", "gpio42", "gpio43"; 5951 function = "qup1_se0"; 5952 }; 5953 5954 qup_spi8_default: qup-spi8-state { 5955 pins = "gpio42", "gpio43", "gpio40", "gpio41"; 5956 function = "qup1_se1"; 5957 }; 5958 5959 qup_spi9_default: qup-spi9-state { 5960 pins = "gpio46", "gpio47", "gpio44", "gpio45"; 5961 function = "qup1_se2"; 5962 }; 5963 5964 qup_spi10_default: qup-spi10-state { 5965 pins = "gpio44", "gpio45", "gpio46", "gpio47"; 5966 function = "qup1_se3"; 5967 }; 5968 5969 qup_spi11_default: qup-spi11-state { 5970 pins = "gpio48", "gpio49", "gpio50", "gpio51"; 5971 function = "qup1_se4"; 5972 }; 5973 5974 qup_spi12_default: qup-spi12-state { 5975 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5976 function = "qup1_se5"; 5977 }; 5978 5979 qup_spi14_default: qup-spi14-state { 5980 pins = "gpio80", "gpio81", "gpio82", "gpio83"; 5981 function = "qup2_se0"; 5982 }; 5983 5984 qup_spi15_default: qup-spi15-state { 5985 pins = "gpio84", "gpio85", "gpio99", "gpio100"; 5986 function = "qup2_se1"; 5987 }; 5988 5989 qup_spi16_default: qup-spi16-state { 5990 pins = "gpio86", "gpio87", "gpio88", "gpio89"; 5991 function = "qup2_se2"; 5992 }; 5993 5994 qup_spi17_default: qup-spi17-state { 5995 pins = "gpio91", "gpio92", "gpio93", "gpio94"; 5996 function = "qup2_se3"; 5997 }; 5998 5999 qup_spi18_default: qup-spi18-state { 6000 pins = "gpio95", "gpio96", "gpio97", "gpio98"; 6001 function = "qup2_se4"; 6002 }; 6003 6004 qup_spi19_default: qup-spi19-state { 6005 pins = "gpio99", "gpio100", "gpio84", "gpio85"; 6006 function = "qup2_se5"; 6007 }; 6008 6009 qup_spi20_default: qup-spi20-state { 6010 pins = "gpio97", "gpio98", "gpio95", "gpio96"; 6011 function = "qup2_se6"; 6012 }; 6013 6014 qup_spi21_default: qup-spi21-state { 6015 pins = "gpio13", "gpio14", "gpio15", "gpio16"; 6016 function = "qup3_se0"; 6017 }; 6018 6019 qup_uart0_default: qup-uart0-state { 6020 qup_uart0_cts: qup-uart0-cts-pins { 6021 pins = "gpio20"; 6022 function = "qup0_se0"; 6023 }; 6024 6025 qup_uart0_rts: qup-uart0-rts-pins { 6026 pins = "gpio21"; 6027 function = "qup0_se0"; 6028 }; 6029 6030 qup_uart0_tx: qup-uart0-tx-pins { 6031 pins = "gpio22"; 6032 function = "qup0_se0"; 6033 }; 6034 6035 qup_uart0_rx: qup-uart0-rx-pins { 6036 pins = "gpio23"; 6037 function = "qup0_se0"; 6038 }; 6039 }; 6040 6041 qup_uart1_default: qup-uart1-state { 6042 qup_uart1_cts: qup-uart1-cts-pins { 6043 pins = "gpio24"; 6044 function = "qup0_se1"; 6045 }; 6046 6047 qup_uart1_rts: qup-uart1-rts-pins { 6048 pins = "gpio25"; 6049 function = "qup0_se1"; 6050 }; 6051 6052 qup_uart1_tx: qup-uart1-tx-pins { 6053 pins = "gpio26"; 6054 function = "qup0_se1"; 6055 }; 6056 6057 qup_uart1_rx: qup-uart1-rx-pins { 6058 pins = "gpio27"; 6059 function = "qup0_se1"; 6060 }; 6061 }; 6062 6063 qup_uart2_default: qup-uart2-state { 6064 qup_uart2_cts: qup-uart2-cts-pins { 6065 pins = "gpio36"; 6066 function = "qup0_se2"; 6067 }; 6068 6069 qup_uart2_rts: qup-uart2-rts-pins { 6070 pins = "gpio37"; 6071 function = "qup0_se2"; 6072 }; 6073 6074 qup_uart2_tx: qup-uart2-tx-pins { 6075 pins = "gpio38"; 6076 function = "qup0_se2"; 6077 }; 6078 6079 qup_uart2_rx: qup-uart2-rx-pins { 6080 pins = "gpio39"; 6081 function = "qup0_se2"; 6082 }; 6083 }; 6084 6085 qup_uart3_default: qup-uart3-state { 6086 qup_uart3_cts: qup-uart3-cts-pins { 6087 pins = "gpio28"; 6088 function = "qup0_se3"; 6089 }; 6090 6091 qup_uart3_rts: qup-uart3-rts-pins { 6092 pins = "gpio29"; 6093 function = "qup0_se3"; 6094 }; 6095 6096 qup_uart3_tx: qup-uart3-tx-pins { 6097 pins = "gpio30"; 6098 function = "qup0_se3"; 6099 }; 6100 6101 qup_uart3_rx: qup-uart3-rx-pins { 6102 pins = "gpio31"; 6103 function = "qup0_se3"; 6104 }; 6105 }; 6106 6107 qup_uart4_default: qup-uart4-state { 6108 qup_uart4_cts: qup-uart4-cts-pins { 6109 pins = "gpio32"; 6110 function = "qup0_se4"; 6111 }; 6112 6113 qup_uart4_rts: qup-uart4-rts-pins { 6114 pins = "gpio33"; 6115 function = "qup0_se4"; 6116 }; 6117 6118 qup_uart4_tx: qup-uart4-tx-pins { 6119 pins = "gpio34"; 6120 function = "qup0_se4"; 6121 }; 6122 6123 qup_uart4_rx: qup-uart4-rx-pins { 6124 pins = "gpio35"; 6125 function = "qup0_se4"; 6126 }; 6127 }; 6128 6129 qup_uart5_default: qup-uart5-state { 6130 qup_uart5_cts: qup-uart5-cts-pins { 6131 pins = "gpio36"; 6132 function = "qup0_se5"; 6133 }; 6134 6135 qup_uart5_rts: qup-uart5-rts-pins { 6136 pins = "gpio37"; 6137 function = "qup0_se5"; 6138 }; 6139 6140 qup_uart5_tx: qup-uart5-tx-pins { 6141 pins = "gpio38"; 6142 function = "qup0_se5"; 6143 }; 6144 6145 qup_uart5_rx: qup-uart5-rx-pins { 6146 pins = "gpio39"; 6147 function = "qup0_se5"; 6148 }; 6149 }; 6150 6151 qup_uart7_default: qup-uart7-state { 6152 qup_uart7_cts: qup-uart7-cts-pins { 6153 pins = "gpio40"; 6154 function = "qup1_se0"; 6155 }; 6156 6157 qup_uart7_rts: qup-uart7-rts-pins { 6158 pins = "gpio41"; 6159 function = "qup1_se0"; 6160 }; 6161 6162 qup_uart7_tx: qup-uart7-tx-pins { 6163 pins = "gpio42"; 6164 function = "qup1_se0"; 6165 }; 6166 6167 qup_uart7_rx: qup-uart7-rx-pins { 6168 pins = "gpio43"; 6169 function = "qup1_se0"; 6170 }; 6171 }; 6172 6173 qup_uart8_default: qup-uart8-state { 6174 qup_uart8_cts: qup-uart8-cts-pins { 6175 pins = "gpio42"; 6176 function = "qup1_se1"; 6177 }; 6178 6179 qup_uart8_rts: qup-uart8-rts-pins { 6180 pins = "gpio43"; 6181 function = "qup1_se1"; 6182 }; 6183 6184 qup_uart8_tx: qup-uart8-tx-pins { 6185 pins = "gpio40"; 6186 function = "qup1_se1"; 6187 }; 6188 6189 qup_uart8_rx: qup-uart8-rx-pins { 6190 pins = "gpio41"; 6191 function = "qup1_se1"; 6192 }; 6193 }; 6194 6195 qup_uart9_default: qup-uart9-state { 6196 qup_uart9_cts: qup-uart9-cts-pins { 6197 pins = "gpio46"; 6198 function = "qup1_se2"; 6199 }; 6200 6201 qup_uart9_rts: qup-uart9-rts-pins { 6202 pins = "gpio47"; 6203 function = "qup1_se2"; 6204 }; 6205 6206 qup_uart9_tx: qup-uart9-tx-pins { 6207 pins = "gpio44"; 6208 function = "qup1_se2"; 6209 }; 6210 6211 qup_uart9_rx: qup-uart9-rx-pins { 6212 pins = "gpio45"; 6213 function = "qup1_se2"; 6214 }; 6215 }; 6216 6217 qup_uart10_default: qup-uart10-state { 6218 pins = "gpio46", "gpio47"; 6219 function = "qup1_se3"; 6220 }; 6221 6222 qup_uart11_default: qup-uart11-state { 6223 qup_uart11_cts: qup-uart11-cts-pins { 6224 pins = "gpio48"; 6225 function = "qup1_se4"; 6226 }; 6227 6228 qup_uart11_rts: qup-uart11-rts-pins { 6229 pins = "gpio49"; 6230 function = "qup1_se4"; 6231 }; 6232 6233 qup_uart11_tx: qup-uart11-tx-pins { 6234 pins = "gpio50"; 6235 function = "qup1_se4"; 6236 }; 6237 6238 qup_uart11_rx: qup-uart11-rx-pins { 6239 pins = "gpio51"; 6240 function = "qup1_se4"; 6241 }; 6242 }; 6243 6244 qup_uart12_default: qup-uart12-state { 6245 qup_uart12_cts: qup-uart12-cts-pins { 6246 pins = "gpio52"; 6247 function = "qup1_se5"; 6248 }; 6249 6250 qup_uart12_rts: qup-uart12-rts-pins { 6251 pins = "gpio53"; 6252 function = "qup1_se5"; 6253 }; 6254 6255 qup_uart12_tx: qup-uart12-tx-pins { 6256 pins = "gpio54"; 6257 function = "qup1_se5"; 6258 }; 6259 6260 qup_uart12_rx: qup-uart12-rx-pins { 6261 pins = "gpio55"; 6262 function = "qup1_se5"; 6263 }; 6264 }; 6265 6266 qup_uart14_default: qup-uart14-state { 6267 qup_uart14_cts: qup-uart14-cts-pins { 6268 pins = "gpio80"; 6269 function = "qup2_se0"; 6270 }; 6271 6272 qup_uart14_rts: qup-uart14-rts-pins { 6273 pins = "gpio81"; 6274 function = "qup2_se0"; 6275 }; 6276 6277 qup_uart14_tx: qup-uart14-tx-pins { 6278 pins = "gpio82"; 6279 function = "qup2_se0"; 6280 }; 6281 6282 qup_uart14_rx: qup-uart14-rx-pins { 6283 pins = "gpio83"; 6284 function = "qup2_se0"; 6285 }; 6286 }; 6287 6288 qup_uart15_default: qup-uart15-state { 6289 qup_uart15_cts: qup-uart15-cts-pins { 6290 pins = "gpio84"; 6291 function = "qup2_se1"; 6292 }; 6293 6294 qup_uart15_rts: qup-uart15-rts-pins { 6295 pins = "gpio85"; 6296 function = "qup2_se1"; 6297 }; 6298 6299 qup_uart15_tx: qup-uart15-tx-pins { 6300 pins = "gpio99"; 6301 function = "qup2_se1"; 6302 }; 6303 6304 qup_uart15_rx: qup-uart15-rx-pins { 6305 pins = "gpio100"; 6306 function = "qup2_se1"; 6307 }; 6308 }; 6309 6310 qup_uart16_default: qup-uart16-state { 6311 qup_uart16_cts: qup-uart16-cts-pins { 6312 pins = "gpio86"; 6313 function = "qup2_se2"; 6314 }; 6315 6316 qup_uart16_rts: qup-uart16-rts-pins { 6317 pins = "gpio87"; 6318 function = "qup2_se2"; 6319 }; 6320 6321 qup_uart16_tx: qup-uart16-tx-pins { 6322 pins = "gpio88"; 6323 function = "qup2_se2"; 6324 }; 6325 6326 qup_uart16_rx: qup-uart16-rx-pins { 6327 pins = "gpio89"; 6328 function = "qup2_se2"; 6329 }; 6330 }; 6331 6332 qup_uart17_default: qup-uart17-state { 6333 qup_uart17_cts: qup-uart17-cts-pins { 6334 pins = "gpio91"; 6335 function = "qup2_se3"; 6336 }; 6337 6338 qup_uart17_rts: qup0-uart17-rts-pins { 6339 pins = "gpio92"; 6340 function = "qup2_se3"; 6341 }; 6342 6343 qup_uart17_tx: qup0-uart17-tx-pins { 6344 pins = "gpio93"; 6345 function = "qup2_se3"; 6346 }; 6347 6348 qup_uart17_rx: qup0-uart17-rx-pins { 6349 pins = "gpio94"; 6350 function = "qup2_se3"; 6351 }; 6352 }; 6353 6354 qup_uart18_default: qup-uart18-state { 6355 qup_uart18_cts: qup-uart18-cts-pins { 6356 pins = "gpio95"; 6357 function = "qup2_se4"; 6358 }; 6359 6360 qup_uart18_rts: qup-uart18-rts-pins { 6361 pins = "gpio96"; 6362 function = "qup2_se4"; 6363 }; 6364 6365 qup_uart18_tx: qup-uart18-tx-pins { 6366 pins = "gpio97"; 6367 function = "qup2_se4"; 6368 }; 6369 6370 qup_uart18_rx: qup-uart18-rx-pins { 6371 pins = "gpio98"; 6372 function = "qup2_se4"; 6373 }; 6374 }; 6375 6376 qup_uart19_default: qup-uart19-state { 6377 qup_uart19_cts: qup-uart19-cts-pins { 6378 pins = "gpio99"; 6379 function = "qup2_se5"; 6380 }; 6381 6382 qup_uart19_rts: qup-uart19-rts-pins { 6383 pins = "gpio100"; 6384 function = "qup2_se5"; 6385 }; 6386 6387 qup_uart19_tx: qup-uart19-tx-pins { 6388 pins = "gpio84"; 6389 function = "qup2_se5"; 6390 }; 6391 6392 qup_uart19_rx: qup-uart19-rx-pins { 6393 pins = "gpio85"; 6394 function = "qup2_se5"; 6395 }; 6396 }; 6397 6398 qup_uart20_default: qup-uart20-state { 6399 qup_uart20_cts: qup-uart20-cts-pins { 6400 pins = "gpio97"; 6401 function = "qup2_se6"; 6402 }; 6403 6404 qup_uart20_rts: qup-uart20-rts-pins { 6405 pins = "gpio98"; 6406 function = "qup2_se6"; 6407 }; 6408 6409 qup_uart20_tx: qup-uart20-tx-pins { 6410 pins = "gpio95"; 6411 function = "qup2_se6"; 6412 }; 6413 6414 qup_uart20_rx: qup-uart20-rx-pins { 6415 pins = "gpio96"; 6416 function = "qup2_se6"; 6417 }; 6418 }; 6419 6420 qup_uart21_default: qup-uart21-state { 6421 qup_uart21_cts: qup-uart21-cts-pins { 6422 pins = "gpio13"; 6423 function = "qup3_se0"; 6424 }; 6425 6426 qup_uart21_rts: qup-uart21-rts-pins { 6427 pins = "gpio14"; 6428 function = "qup3_se0"; 6429 }; 6430 6431 qup_uart21_tx: qup-uart21-tx-pins { 6432 pins = "gpio15"; 6433 function = "qup3_se0"; 6434 }; 6435 6436 qup_uart21_rx: qup-uart21-rx-pins { 6437 pins = "gpio16"; 6438 function = "qup3_se0"; 6439 }; 6440 }; 6441 6442 sdc_default: sdc-default-state { 6443 clk-pins { 6444 pins = "sdc1_clk"; 6445 drive-strength = <16>; 6446 bias-disable; 6447 }; 6448 6449 cmd-pins { 6450 pins = "sdc1_cmd"; 6451 drive-strength = <10>; 6452 bias-pull-up; 6453 }; 6454 6455 data-pins { 6456 pins = "sdc1_data"; 6457 drive-strength = <10>; 6458 bias-pull-up; 6459 }; 6460 }; 6461 6462 sdc_sleep: sdc-sleep-state { 6463 clk-pins { 6464 pins = "sdc1_clk"; 6465 drive-strength = <2>; 6466 bias-bus-hold; 6467 }; 6468 6469 cmd-pins { 6470 pins = "sdc1_cmd"; 6471 drive-strength = <2>; 6472 bias-bus-hold; 6473 }; 6474 6475 data-pins { 6476 pins = "sdc1_data"; 6477 drive-strength = <2>; 6478 bias-bus-hold; 6479 }; 6480 }; 6481 }; 6482 6483 sram: sram@146d8000 { 6484 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; 6485 reg = <0x0 0x146d8000 0x0 0x1000>; 6486 ranges = <0x0 0x0 0x146d8000 0x1000>; 6487 6488 #address-cells = <1>; 6489 #size-cells = <1>; 6490 6491 pil-reloc@94c { 6492 compatible = "qcom,pil-reloc-info"; 6493 reg = <0x94c 0xc8>; 6494 }; 6495 }; 6496 6497 apps_smmu: iommu@15000000 { 6498 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6499 reg = <0x0 0x15000000 0x0 0x100000>; 6500 #iommu-cells = <2>; 6501 #global-interrupts = <2>; 6502 dma-coherent; 6503 6504 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 6505 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 6506 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6507 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6508 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6509 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6510 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6511 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6512 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6513 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6514 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6515 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6516 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6517 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6518 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6519 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6520 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6521 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6522 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6523 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6524 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6525 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6526 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6527 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6528 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6529 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6530 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6531 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6532 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6533 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6534 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6535 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6536 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6537 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6538 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6539 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6540 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6541 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6542 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6543 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6544 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6545 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6546 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6547 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6548 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6549 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6550 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6551 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6552 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6553 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6554 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6555 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6556 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6557 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6558 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6559 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6560 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6561 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6562 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6563 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6564 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6565 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6566 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6567 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6568 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6569 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6570 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6571 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6572 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6573 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6574 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6575 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6576 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6577 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6578 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6579 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 6580 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 6581 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 6582 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 6583 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 6584 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 6585 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 6586 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 6587 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 6588 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 6589 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 6590 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 6591 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 6592 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 6593 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 6594 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 6595 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 6596 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 6597 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 6598 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 6599 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 6600 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 6601 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 6602 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 6603 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 6604 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 6605 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 6606 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 6607 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 6608 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 6609 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 6610 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 6611 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 6612 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 6613 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 6614 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 6615 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 6616 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 6617 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 6618 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 6619 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 6620 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 6621 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 6622 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 6623 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 6624 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 6625 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 6626 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 6627 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 6628 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 6629 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 6630 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 6631 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 6632 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 6633 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 6634 }; 6635 6636 pcie_smmu: iommu@15200000 { 6637 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 6638 reg = <0x0 0x15200000 0x0 0x80000>; 6639 #iommu-cells = <2>; 6640 #global-interrupts = <2>; 6641 dma-coherent; 6642 6643 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 6644 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 6645 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 6646 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 6647 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 6648 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 6649 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 6650 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 6651 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 6652 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 6653 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 6654 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 6655 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 6656 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 6657 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 6658 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 6659 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 6660 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 6661 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 6662 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 6663 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 6664 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 6665 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 6666 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 6667 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 6668 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 6669 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 6670 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 6671 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 6672 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 6673 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 6674 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 6675 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 6676 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 6677 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 6678 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 6679 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 6680 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 6681 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 6682 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 6683 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 6684 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 6685 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 6686 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 6687 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 6688 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 6689 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 6690 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 6691 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 6692 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 6693 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 6694 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 6695 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 6696 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 6697 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 6698 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 6699 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 6700 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 6701 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 6702 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 6703 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 6704 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 6705 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 6706 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 6707 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 6708 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 6709 }; 6710 6711 intc: interrupt-controller@17a00000 { 6712 compatible = "arm,gic-v3"; 6713 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 6714 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 6715 interrupt-controller; 6716 #address-cells = <0>; 6717 #interrupt-cells = <3>; 6718 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 6719 #redistributor-regions = <1>; 6720 redistributor-stride = <0x0 0x20000>; 6721 }; 6722 6723 watchdog@17c10000 { 6724 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 6725 reg = <0x0 0x17c10000 0x0 0x1000>; 6726 clocks = <&sleep_clk>; 6727 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6728 }; 6729 6730 memtimer: timer@17c20000 { 6731 compatible = "arm,armv7-timer-mem"; 6732 reg = <0x0 0x17c20000 0x0 0x1000>; 6733 ranges = <0x0 0x0 0x0 0x20000000>; 6734 #address-cells = <1>; 6735 #size-cells = <1>; 6736 6737 frame@17c21000 { 6738 reg = <0x17c21000 0x1000>, 6739 <0x17c22000 0x1000>; 6740 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6741 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6742 frame-number = <0>; 6743 }; 6744 6745 frame@17c23000 { 6746 reg = <0x17c23000 0x1000>; 6747 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6748 frame-number = <1>; 6749 status = "disabled"; 6750 }; 6751 6752 frame@17c25000 { 6753 reg = <0x17c25000 0x1000>; 6754 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6755 frame-number = <2>; 6756 status = "disabled"; 6757 }; 6758 6759 frame@17c27000 { 6760 reg = <0x17c27000 0x1000>; 6761 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6762 frame-number = <3>; 6763 status = "disabled"; 6764 }; 6765 6766 frame@17c29000 { 6767 reg = <0x17c29000 0x1000>; 6768 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6769 frame-number = <4>; 6770 status = "disabled"; 6771 }; 6772 6773 frame@17c2b000 { 6774 reg = <0x17c2b000 0x1000>; 6775 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6776 frame-number = <5>; 6777 status = "disabled"; 6778 }; 6779 6780 frame@17c2d000 { 6781 reg = <0x17c2d000 0x1000>; 6782 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6783 frame-number = <6>; 6784 status = "disabled"; 6785 }; 6786 }; 6787 6788 apps_rsc: rsc@18200000 { 6789 compatible = "qcom,rpmh-rsc"; 6790 reg = <0x0 0x18200000 0x0 0x10000>, 6791 <0x0 0x18210000 0x0 0x10000>, 6792 <0x0 0x18220000 0x0 0x10000>; 6793 reg-names = "drv-0", "drv-1", "drv-2"; 6794 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6795 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6796 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6797 qcom,tcs-offset = <0xd00>; 6798 qcom,drv-id = <2>; 6799 qcom,tcs-config = <ACTIVE_TCS 2>, 6800 <SLEEP_TCS 3>, 6801 <WAKE_TCS 3>, 6802 <CONTROL_TCS 0>; 6803 label = "apps_rsc"; 6804 power-domains = <&system_pd>; 6805 6806 apps_bcm_voter: bcm-voter { 6807 compatible = "qcom,bcm-voter"; 6808 }; 6809 6810 rpmhcc: clock-controller { 6811 compatible = "qcom,sa8775p-rpmh-clk"; 6812 #clock-cells = <1>; 6813 clock-names = "xo"; 6814 clocks = <&xo_board_clk>; 6815 }; 6816 6817 rpmhpd: power-controller { 6818 compatible = "qcom,sa8775p-rpmhpd"; 6819 #power-domain-cells = <1>; 6820 operating-points-v2 = <&rpmhpd_opp_table>; 6821 6822 rpmhpd_opp_table: opp-table { 6823 compatible = "operating-points-v2"; 6824 6825 rpmhpd_opp_ret: opp-0 { 6826 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6827 }; 6828 6829 rpmhpd_opp_min_svs: opp-1 { 6830 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6831 }; 6832 6833 rpmhpd_opp_low_svs: opp2 { 6834 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6835 }; 6836 6837 rpmhpd_opp_svs: opp3 { 6838 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6839 }; 6840 6841 rpmhpd_opp_svs_l1: opp-4 { 6842 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6843 }; 6844 6845 rpmhpd_opp_nom: opp-5 { 6846 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6847 }; 6848 6849 rpmhpd_opp_nom_l1: opp-6 { 6850 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6851 }; 6852 6853 rpmhpd_opp_nom_l2: opp-7 { 6854 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6855 }; 6856 6857 rpmhpd_opp_turbo: opp-8 { 6858 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6859 }; 6860 6861 rpmhpd_opp_turbo_l1: opp-9 { 6862 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6863 }; 6864 }; 6865 }; 6866 }; 6867 6868 epss_l3_cl0: interconnect@18590000 { 6869 compatible = "qcom,sa8775p-epss-l3", 6870 "qcom,epss-l3"; 6871 reg = <0x0 0x18590000 0x0 0x1000>; 6872 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6873 clock-names = "xo", "alternate"; 6874 #interconnect-cells = <1>; 6875 }; 6876 6877 cpufreq_hw: cpufreq@18591000 { 6878 compatible = "qcom,sa8775p-cpufreq-epss", 6879 "qcom,cpufreq-epss"; 6880 reg = <0x0 0x18591000 0x0 0x1000>, 6881 <0x0 0x18593000 0x0 0x1000>; 6882 reg-names = "freq-domain0", "freq-domain1"; 6883 6884 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6885 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 6886 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 6887 6888 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6889 clock-names = "xo", "alternate"; 6890 6891 #freq-domain-cells = <1>; 6892 }; 6893 6894 epss_l3_cl1: interconnect@18592000 { 6895 compatible = "qcom,sa8775p-epss-l3", 6896 "qcom,epss-l3"; 6897 reg = <0x0 0x18592000 0x0 0x1000>; 6898 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6899 clock-names = "xo", "alternate"; 6900 #interconnect-cells = <1>; 6901 }; 6902 6903 remoteproc_gpdsp0: remoteproc@20c00000 { 6904 compatible = "qcom,sa8775p-gpdsp0-pas"; 6905 reg = <0x0 0x20c00000 0x0 0x10000>; 6906 6907 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 6908 <&smp2p_gpdsp0_in 0 0>, 6909 <&smp2p_gpdsp0_in 1 0>, 6910 <&smp2p_gpdsp0_in 2 0>, 6911 <&smp2p_gpdsp0_in 3 0>; 6912 interrupt-names = "wdog", "fatal", "ready", 6913 "handover", "stop-ack"; 6914 6915 clocks = <&rpmhcc RPMH_CXO_CLK>; 6916 clock-names = "xo"; 6917 6918 power-domains = <&rpmhpd SA8775P_CX>, 6919 <&rpmhpd SA8775P_MXC>; 6920 power-domain-names = "cx", "mxc"; 6921 6922 interconnects = <&gpdsp_anoc MASTER_DSP0 0 6923 &config_noc SLAVE_CLK_CTL 0>; 6924 6925 memory-region = <&pil_gdsp0_mem>; 6926 6927 qcom,qmp = <&aoss_qmp>; 6928 6929 qcom,smem-states = <&smp2p_gpdsp0_out 0>; 6930 qcom,smem-state-names = "stop"; 6931 6932 status = "disabled"; 6933 6934 glink-edge { 6935 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 6936 IPCC_MPROC_SIGNAL_GLINK_QMP 6937 IRQ_TYPE_EDGE_RISING>; 6938 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 6939 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6940 6941 label = "gpdsp0"; 6942 qcom,remote-pid = <17>; 6943 6944 fastrpc { 6945 compatible = "qcom,fastrpc"; 6946 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6947 label = "gdsp0"; 6948 #address-cells = <1>; 6949 #size-cells = <0>; 6950 6951 compute-cb@1 { 6952 compatible = "qcom,fastrpc-compute-cb"; 6953 reg = <1>; 6954 iommus = <&apps_smmu 0x38a1 0x0>; 6955 dma-coherent; 6956 }; 6957 6958 compute-cb@2 { 6959 compatible = "qcom,fastrpc-compute-cb"; 6960 reg = <2>; 6961 iommus = <&apps_smmu 0x38a2 0x0>; 6962 dma-coherent; 6963 }; 6964 6965 compute-cb@3 { 6966 compatible = "qcom,fastrpc-compute-cb"; 6967 reg = <3>; 6968 iommus = <&apps_smmu 0x38a3 0x0>; 6969 dma-coherent; 6970 }; 6971 }; 6972 }; 6973 }; 6974 6975 remoteproc_gpdsp1: remoteproc@21c00000 { 6976 compatible = "qcom,sa8775p-gpdsp1-pas"; 6977 reg = <0x0 0x21c00000 0x0 0x10000>; 6978 6979 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 6980 <&smp2p_gpdsp1_in 0 0>, 6981 <&smp2p_gpdsp1_in 1 0>, 6982 <&smp2p_gpdsp1_in 2 0>, 6983 <&smp2p_gpdsp1_in 3 0>; 6984 interrupt-names = "wdog", "fatal", "ready", 6985 "handover", "stop-ack"; 6986 6987 clocks = <&rpmhcc RPMH_CXO_CLK>; 6988 clock-names = "xo"; 6989 6990 power-domains = <&rpmhpd SA8775P_CX>, 6991 <&rpmhpd SA8775P_MXC>; 6992 power-domain-names = "cx", "mxc"; 6993 6994 interconnects = <&gpdsp_anoc MASTER_DSP1 0 6995 &config_noc SLAVE_CLK_CTL 0>; 6996 6997 memory-region = <&pil_gdsp1_mem>; 6998 6999 qcom,qmp = <&aoss_qmp>; 7000 7001 qcom,smem-states = <&smp2p_gpdsp1_out 0>; 7002 qcom,smem-state-names = "stop"; 7003 7004 status = "disabled"; 7005 7006 glink-edge { 7007 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 7008 IPCC_MPROC_SIGNAL_GLINK_QMP 7009 IRQ_TYPE_EDGE_RISING>; 7010 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 7011 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7012 7013 label = "gpdsp1"; 7014 qcom,remote-pid = <18>; 7015 7016 fastrpc { 7017 compatible = "qcom,fastrpc"; 7018 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7019 label = "gdsp1"; 7020 #address-cells = <1>; 7021 #size-cells = <0>; 7022 7023 compute-cb@1 { 7024 compatible = "qcom,fastrpc-compute-cb"; 7025 reg = <1>; 7026 iommus = <&apps_smmu 0x38c1 0x0>; 7027 dma-coherent; 7028 }; 7029 7030 compute-cb@2 { 7031 compatible = "qcom,fastrpc-compute-cb"; 7032 reg = <2>; 7033 iommus = <&apps_smmu 0x38c2 0x0>; 7034 dma-coherent; 7035 }; 7036 7037 compute-cb@3 { 7038 compatible = "qcom,fastrpc-compute-cb"; 7039 reg = <3>; 7040 iommus = <&apps_smmu 0x38c3 0x0>; 7041 dma-coherent; 7042 }; 7043 }; 7044 }; 7045 }; 7046 7047 dispcc1: clock-controller@22100000 { 7048 compatible = "qcom,sa8775p-dispcc1"; 7049 reg = <0x0 0x22100000 0x0 0x20000>; 7050 clocks = <&gcc GCC_DISP_AHB_CLK>, 7051 <&rpmhcc RPMH_CXO_CLK>, 7052 <&rpmhcc RPMH_CXO_CLK_A>, 7053 <&sleep_clk>, 7054 <0>, <0>, <0>, <0>, 7055 <0>, <0>, <0>, <0>; 7056 power-domains = <&rpmhpd SA8775P_MMCX>; 7057 #clock-cells = <1>; 7058 #reset-cells = <1>; 7059 #power-domain-cells = <1>; 7060 status = "disabled"; 7061 }; 7062 7063 ethernet1: ethernet@23000000 { 7064 compatible = "qcom,sa8775p-ethqos"; 7065 reg = <0x0 0x23000000 0x0 0x10000>, 7066 <0x0 0x23016000 0x0 0x100>; 7067 reg-names = "stmmaceth", "rgmii"; 7068 7069 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 7070 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 7071 interrupt-names = "macirq", "sfty"; 7072 7073 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 7074 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 7075 <&gcc GCC_EMAC1_PTP_CLK>, 7076 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 7077 clock-names = "stmmaceth", 7078 "pclk", 7079 "ptp_ref", 7080 "phyaux"; 7081 7082 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 7083 &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>, 7084 <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS 7085 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7086 interconnect-names = "cpu-mac", 7087 "mac-mem"; 7088 7089 power-domains = <&gcc EMAC1_GDSC>; 7090 7091 phys = <&serdes1>; 7092 phy-names = "serdes"; 7093 7094 iommus = <&apps_smmu 0x140 0xf>; 7095 dma-coherent; 7096 7097 snps,tso; 7098 snps,pbl = <32>; 7099 rx-fifo-depth = <16384>; 7100 tx-fifo-depth = <16384>; 7101 7102 status = "disabled"; 7103 }; 7104 7105 ethernet0: ethernet@23040000 { 7106 compatible = "qcom,sa8775p-ethqos"; 7107 reg = <0x0 0x23040000 0x0 0x10000>, 7108 <0x0 0x23056000 0x0 0x100>; 7109 reg-names = "stmmaceth", "rgmii"; 7110 7111 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 7112 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; 7113 interrupt-names = "macirq", "sfty"; 7114 7115 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 7116 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 7117 <&gcc GCC_EMAC0_PTP_CLK>, 7118 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 7119 clock-names = "stmmaceth", 7120 "pclk", 7121 "ptp_ref", 7122 "phyaux"; 7123 7124 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 7125 &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>, 7126 <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS 7127 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7128 interconnect-names = "cpu-mac", 7129 "mac-mem"; 7130 7131 power-domains = <&gcc EMAC0_GDSC>; 7132 7133 phys = <&serdes0>; 7134 phy-names = "serdes"; 7135 7136 iommus = <&apps_smmu 0x120 0xf>; 7137 dma-coherent; 7138 7139 snps,tso; 7140 snps,pbl = <32>; 7141 rx-fifo-depth = <16384>; 7142 tx-fifo-depth = <16384>; 7143 7144 status = "disabled"; 7145 }; 7146 7147 nspa_noc: interconnect@260c0000 { 7148 compatible = "qcom,sa8775p-nspa-noc"; 7149 reg = <0x0 0x260c0000 0x0 0x16080>; 7150 #interconnect-cells = <2>; 7151 qcom,bcm-voters = <&apps_bcm_voter>; 7152 }; 7153 7154 remoteproc_cdsp0: remoteproc@26300000 { 7155 compatible = "qcom,sa8775p-cdsp0-pas"; 7156 reg = <0x0 0x26300000 0x0 0x10000>; 7157 7158 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 7159 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>, 7160 <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>, 7161 <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>, 7162 <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>; 7163 interrupt-names = "wdog", "fatal", "ready", 7164 "handover", "stop-ack"; 7165 7166 clocks = <&rpmhcc RPMH_CXO_CLK>; 7167 clock-names = "xo"; 7168 7169 power-domains = <&rpmhpd SA8775P_CX>, 7170 <&rpmhpd SA8775P_MXC>, 7171 <&rpmhpd SA8775P_NSP0>; 7172 power-domain-names = "cx", "mxc", "nsp"; 7173 7174 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 7175 &mc_virt SLAVE_EBI1 0>; 7176 7177 memory-region = <&pil_cdsp0_mem>; 7178 7179 qcom,qmp = <&aoss_qmp>; 7180 7181 qcom,smem-states = <&smp2p_cdsp0_out 0>; 7182 qcom,smem-state-names = "stop"; 7183 7184 status = "disabled"; 7185 7186 glink-edge { 7187 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7188 IPCC_MPROC_SIGNAL_GLINK_QMP 7189 IRQ_TYPE_EDGE_RISING>; 7190 mboxes = <&ipcc IPCC_CLIENT_CDSP 7191 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7192 7193 label = "cdsp"; 7194 qcom,remote-pid = <5>; 7195 7196 fastrpc { 7197 compatible = "qcom,fastrpc"; 7198 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7199 label = "cdsp"; 7200 #address-cells = <1>; 7201 #size-cells = <0>; 7202 7203 compute-cb@1 { 7204 compatible = "qcom,fastrpc-compute-cb"; 7205 reg = <1>; 7206 iommus = <&apps_smmu 0x2141 0x04a0>, 7207 <&apps_smmu 0x2181 0x0400>; 7208 dma-coherent; 7209 }; 7210 7211 compute-cb@2 { 7212 compatible = "qcom,fastrpc-compute-cb"; 7213 reg = <2>; 7214 iommus = <&apps_smmu 0x2142 0x04a0>, 7215 <&apps_smmu 0x2182 0x0400>; 7216 dma-coherent; 7217 }; 7218 7219 compute-cb@3 { 7220 compatible = "qcom,fastrpc-compute-cb"; 7221 reg = <3>; 7222 iommus = <&apps_smmu 0x2143 0x04a0>, 7223 <&apps_smmu 0x2183 0x0400>; 7224 dma-coherent; 7225 }; 7226 7227 compute-cb@4 { 7228 compatible = "qcom,fastrpc-compute-cb"; 7229 reg = <4>; 7230 iommus = <&apps_smmu 0x2144 0x04a0>, 7231 <&apps_smmu 0x2184 0x0400>; 7232 dma-coherent; 7233 }; 7234 7235 compute-cb@5 { 7236 compatible = "qcom,fastrpc-compute-cb"; 7237 reg = <5>; 7238 iommus = <&apps_smmu 0x2145 0x04a0>, 7239 <&apps_smmu 0x2185 0x0400>; 7240 dma-coherent; 7241 }; 7242 7243 compute-cb@6 { 7244 compatible = "qcom,fastrpc-compute-cb"; 7245 reg = <6>; 7246 iommus = <&apps_smmu 0x2146 0x04a0>, 7247 <&apps_smmu 0x2186 0x0400>; 7248 dma-coherent; 7249 }; 7250 7251 compute-cb@7 { 7252 compatible = "qcom,fastrpc-compute-cb"; 7253 reg = <7>; 7254 iommus = <&apps_smmu 0x2147 0x04a0>, 7255 <&apps_smmu 0x2187 0x0400>; 7256 dma-coherent; 7257 }; 7258 7259 compute-cb@8 { 7260 compatible = "qcom,fastrpc-compute-cb"; 7261 reg = <8>; 7262 iommus = <&apps_smmu 0x2148 0x04a0>, 7263 <&apps_smmu 0x2188 0x0400>; 7264 dma-coherent; 7265 }; 7266 7267 compute-cb@9 { 7268 compatible = "qcom,fastrpc-compute-cb"; 7269 reg = <9>; 7270 iommus = <&apps_smmu 0x2149 0x04a0>, 7271 <&apps_smmu 0x2189 0x0400>; 7272 dma-coherent; 7273 }; 7274 7275 compute-cb@11 { 7276 compatible = "qcom,fastrpc-compute-cb"; 7277 reg = <11>; 7278 iommus = <&apps_smmu 0x214b 0x04a0>, 7279 <&apps_smmu 0x218b 0x0400>; 7280 dma-coherent; 7281 }; 7282 }; 7283 }; 7284 }; 7285 7286 nspb_noc: interconnect@2a0c0000 { 7287 compatible = "qcom,sa8775p-nspb-noc"; 7288 reg = <0x0 0x2a0c0000 0x0 0x16080>; 7289 #interconnect-cells = <2>; 7290 qcom,bcm-voters = <&apps_bcm_voter>; 7291 }; 7292 7293 remoteproc_cdsp1: remoteproc@2a300000 { 7294 compatible = "qcom,sa8775p-cdsp1-pas"; 7295 reg = <0x0 0x2a300000 0x0 0x10000>; 7296 7297 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 7298 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, 7299 <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>, 7300 <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>, 7301 <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>; 7302 interrupt-names = "wdog", "fatal", "ready", 7303 "handover", "stop-ack"; 7304 7305 clocks = <&rpmhcc RPMH_CXO_CLK>; 7306 clock-names = "xo"; 7307 7308 power-domains = <&rpmhpd SA8775P_CX>, 7309 <&rpmhpd SA8775P_MXC>, 7310 <&rpmhpd SA8775P_NSP1>; 7311 power-domain-names = "cx", "mxc", "nsp"; 7312 7313 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 7314 &mc_virt SLAVE_EBI1 0>; 7315 7316 memory-region = <&pil_cdsp1_mem>; 7317 7318 qcom,qmp = <&aoss_qmp>; 7319 7320 qcom,smem-states = <&smp2p_cdsp1_out 0>; 7321 qcom,smem-state-names = "stop"; 7322 7323 status = "disabled"; 7324 7325 glink-edge { 7326 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 7327 IPCC_MPROC_SIGNAL_GLINK_QMP 7328 IRQ_TYPE_EDGE_RISING>; 7329 mboxes = <&ipcc IPCC_CLIENT_NSP1 7330 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7331 7332 label = "cdsp"; 7333 qcom,remote-pid = <12>; 7334 7335 fastrpc { 7336 compatible = "qcom,fastrpc"; 7337 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7338 label = "cdsp1"; 7339 #address-cells = <1>; 7340 #size-cells = <0>; 7341 7342 compute-cb@1 { 7343 compatible = "qcom,fastrpc-compute-cb"; 7344 reg = <1>; 7345 iommus = <&apps_smmu 0x2941 0x04a0>, 7346 <&apps_smmu 0x2981 0x0400>; 7347 dma-coherent; 7348 }; 7349 7350 compute-cb@2 { 7351 compatible = "qcom,fastrpc-compute-cb"; 7352 reg = <2>; 7353 iommus = <&apps_smmu 0x2942 0x04a0>, 7354 <&apps_smmu 0x2982 0x0400>; 7355 dma-coherent; 7356 }; 7357 7358 compute-cb@3 { 7359 compatible = "qcom,fastrpc-compute-cb"; 7360 reg = <3>; 7361 iommus = <&apps_smmu 0x2943 0x04a0>, 7362 <&apps_smmu 0x2983 0x0400>; 7363 dma-coherent; 7364 }; 7365 7366 compute-cb@4 { 7367 compatible = "qcom,fastrpc-compute-cb"; 7368 reg = <4>; 7369 iommus = <&apps_smmu 0x2944 0x04a0>, 7370 <&apps_smmu 0x2984 0x0400>; 7371 dma-coherent; 7372 }; 7373 7374 compute-cb@5 { 7375 compatible = "qcom,fastrpc-compute-cb"; 7376 reg = <5>; 7377 iommus = <&apps_smmu 0x2945 0x04a0>, 7378 <&apps_smmu 0x2985 0x0400>; 7379 dma-coherent; 7380 }; 7381 7382 compute-cb@6 { 7383 compatible = "qcom,fastrpc-compute-cb"; 7384 reg = <6>; 7385 iommus = <&apps_smmu 0x2946 0x04a0>, 7386 <&apps_smmu 0x2986 0x0400>; 7387 dma-coherent; 7388 }; 7389 7390 compute-cb@7 { 7391 compatible = "qcom,fastrpc-compute-cb"; 7392 reg = <7>; 7393 iommus = <&apps_smmu 0x2947 0x04a0>, 7394 <&apps_smmu 0x2987 0x0400>; 7395 dma-coherent; 7396 }; 7397 7398 compute-cb@8 { 7399 compatible = "qcom,fastrpc-compute-cb"; 7400 reg = <8>; 7401 iommus = <&apps_smmu 0x2948 0x04a0>, 7402 <&apps_smmu 0x2988 0x0400>; 7403 dma-coherent; 7404 }; 7405 7406 compute-cb@9 { 7407 compatible = "qcom,fastrpc-compute-cb"; 7408 reg = <9>; 7409 iommus = <&apps_smmu 0x2949 0x04a0>, 7410 <&apps_smmu 0x2989 0x0400>; 7411 dma-coherent; 7412 }; 7413 7414 compute-cb@10 { 7415 compatible = "qcom,fastrpc-compute-cb"; 7416 reg = <10>; 7417 iommus = <&apps_smmu 0x294a 0x04a0>, 7418 <&apps_smmu 0x298a 0x0400>; 7419 dma-coherent; 7420 }; 7421 7422 compute-cb@11 { 7423 compatible = "qcom,fastrpc-compute-cb"; 7424 reg = <11>; 7425 iommus = <&apps_smmu 0x294b 0x04a0>, 7426 <&apps_smmu 0x298b 0x0400>; 7427 dma-coherent; 7428 }; 7429 7430 compute-cb@12 { 7431 compatible = "qcom,fastrpc-compute-cb"; 7432 reg = <12>; 7433 iommus = <&apps_smmu 0x294c 0x04a0>, 7434 <&apps_smmu 0x298c 0x0400>; 7435 dma-coherent; 7436 }; 7437 7438 compute-cb@13 { 7439 compatible = "qcom,fastrpc-compute-cb"; 7440 reg = <13>; 7441 iommus = <&apps_smmu 0x294d 0x04a0>, 7442 <&apps_smmu 0x298d 0x0400>; 7443 dma-coherent; 7444 }; 7445 }; 7446 }; 7447 }; 7448 7449 remoteproc_adsp: remoteproc@30000000 { 7450 compatible = "qcom,sa8775p-adsp-pas"; 7451 reg = <0x0 0x30000000 0x0 0x100>; 7452 7453 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 7454 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 7455 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 7456 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 7457 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 7458 interrupt-names = "wdog", "fatal", "ready", "handover", 7459 "stop-ack"; 7460 7461 clocks = <&rpmhcc RPMH_CXO_CLK>; 7462 clock-names = "xo"; 7463 7464 power-domains = <&rpmhpd SA8775P_LCX>, 7465 <&rpmhpd SA8775P_LMX>; 7466 power-domain-names = "lcx", "lmx"; 7467 7468 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 7469 7470 memory-region = <&pil_adsp_mem>; 7471 7472 qcom,qmp = <&aoss_qmp>; 7473 7474 qcom,smem-states = <&smp2p_adsp_out 0>; 7475 qcom,smem-state-names = "stop"; 7476 7477 status = "disabled"; 7478 7479 remoteproc_adsp_glink: glink-edge { 7480 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 7481 IPCC_MPROC_SIGNAL_GLINK_QMP 7482 IRQ_TYPE_EDGE_RISING>; 7483 mboxes = <&ipcc IPCC_CLIENT_LPASS 7484 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7485 7486 label = "lpass"; 7487 qcom,remote-pid = <2>; 7488 7489 fastrpc { 7490 compatible = "qcom,fastrpc"; 7491 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7492 label = "adsp"; 7493 memory-region = <&adsp_rpc_remote_heap_mem>; 7494 qcom,vmids = <QCOM_SCM_VMID_LPASS 7495 QCOM_SCM_VMID_ADSP_HEAP>; 7496 #address-cells = <1>; 7497 #size-cells = <0>; 7498 7499 compute-cb@3 { 7500 compatible = "qcom,fastrpc-compute-cb"; 7501 reg = <3>; 7502 iommus = <&apps_smmu 0x3003 0x0>; 7503 dma-coherent; 7504 }; 7505 7506 compute-cb@4 { 7507 compatible = "qcom,fastrpc-compute-cb"; 7508 reg = <4>; 7509 iommus = <&apps_smmu 0x3004 0x0>; 7510 dma-coherent; 7511 }; 7512 7513 compute-cb@5 { 7514 compatible = "qcom,fastrpc-compute-cb"; 7515 reg = <5>; 7516 iommus = <&apps_smmu 0x3005 0x0>; 7517 qcom,nsessions = <5>; 7518 dma-coherent; 7519 }; 7520 }; 7521 7522 gpr { 7523 compatible = "qcom,gpr"; 7524 qcom,glink-channels = "adsp_apps"; 7525 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 7526 qcom,intents = <512 20>; 7527 #address-cells = <1>; 7528 #size-cells = <0>; 7529 7530 q6apm: service@1 { 7531 compatible = "qcom,q6apm"; 7532 reg = <GPR_APM_MODULE_IID>; 7533 #sound-dai-cells = <0>; 7534 qcom,protection-domain = "avs/audio", 7535 "msm/adsp/audio_pd"; 7536 7537 q6apmbedai: bedais { 7538 compatible = "qcom,q6apm-lpass-dais"; 7539 #sound-dai-cells = <1>; 7540 }; 7541 7542 q6apmdai: dais { 7543 compatible = "qcom,q6apm-dais"; 7544 iommus = <&apps_smmu 0x3001 0x0>; 7545 }; 7546 }; 7547 7548 q6prm: service@2 { 7549 compatible = "qcom,q6prm"; 7550 reg = <GPR_PRM_MODULE_IID>; 7551 qcom,protection-domain = "avs/audio", 7552 "msm/adsp/audio_pd"; 7553 7554 q6prmcc: clock-controller { 7555 compatible = "qcom,q6prm-lpass-clocks"; 7556 #clock-cells = <2>; 7557 }; 7558 }; 7559 }; 7560 }; 7561 }; 7562 }; 7563 7564 thermal-zones { 7565 aoss-0-thermal { 7566 thermal-sensors = <&tsens0 0>; 7567 7568 trips { 7569 trip-point0 { 7570 temperature = <105000>; 7571 hysteresis = <5000>; 7572 type = "passive"; 7573 }; 7574 7575 trip-point1 { 7576 temperature = <115000>; 7577 hysteresis = <5000>; 7578 type = "passive"; 7579 }; 7580 }; 7581 }; 7582 7583 cpu-0-0-0-thermal { 7584 polling-delay-passive = <10>; 7585 7586 thermal-sensors = <&tsens0 1>; 7587 7588 trips { 7589 trip-point0 { 7590 temperature = <105000>; 7591 hysteresis = <5000>; 7592 type = "passive"; 7593 }; 7594 7595 trip-point1 { 7596 temperature = <115000>; 7597 hysteresis = <5000>; 7598 type = "passive"; 7599 }; 7600 }; 7601 }; 7602 7603 cpu-0-1-0-thermal { 7604 polling-delay-passive = <10>; 7605 7606 thermal-sensors = <&tsens0 2>; 7607 7608 trips { 7609 trip-point0 { 7610 temperature = <105000>; 7611 hysteresis = <5000>; 7612 type = "passive"; 7613 }; 7614 7615 trip-point1 { 7616 temperature = <115000>; 7617 hysteresis = <5000>; 7618 type = "passive"; 7619 }; 7620 }; 7621 }; 7622 7623 cpu-0-2-0-thermal { 7624 polling-delay-passive = <10>; 7625 7626 thermal-sensors = <&tsens0 3>; 7627 7628 trips { 7629 trip-point0 { 7630 temperature = <105000>; 7631 hysteresis = <5000>; 7632 type = "passive"; 7633 }; 7634 7635 trip-point1 { 7636 temperature = <115000>; 7637 hysteresis = <5000>; 7638 type = "passive"; 7639 }; 7640 }; 7641 }; 7642 7643 cpu-0-3-0-thermal { 7644 polling-delay-passive = <10>; 7645 7646 thermal-sensors = <&tsens0 4>; 7647 7648 trips { 7649 trip-point0 { 7650 temperature = <105000>; 7651 hysteresis = <5000>; 7652 type = "passive"; 7653 }; 7654 7655 trip-point1 { 7656 temperature = <115000>; 7657 hysteresis = <5000>; 7658 type = "passive"; 7659 }; 7660 }; 7661 }; 7662 7663 gpuss-0-thermal { 7664 polling-delay-passive = <10>; 7665 7666 thermal-sensors = <&tsens0 5>; 7667 7668 cooling-maps { 7669 map0 { 7670 trip = <&gpuss0_alert0>; 7671 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7672 }; 7673 }; 7674 7675 trips { 7676 gpuss0_alert0: trip-point0 { 7677 temperature = <105000>; 7678 hysteresis = <5000>; 7679 type = "passive"; 7680 }; 7681 7682 trip-point1 { 7683 temperature = <115000>; 7684 hysteresis = <5000>; 7685 type = "passive"; 7686 }; 7687 }; 7688 }; 7689 7690 gpuss-1-thermal { 7691 polling-delay-passive = <10>; 7692 7693 thermal-sensors = <&tsens0 6>; 7694 7695 cooling-maps { 7696 map0 { 7697 trip = <&gpuss1_alert0>; 7698 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7699 }; 7700 }; 7701 7702 trips { 7703 gpuss1_alert0: trip-point0 { 7704 temperature = <105000>; 7705 hysteresis = <5000>; 7706 type = "passive"; 7707 }; 7708 7709 trip-point1 { 7710 temperature = <115000>; 7711 hysteresis = <5000>; 7712 type = "passive"; 7713 }; 7714 }; 7715 }; 7716 7717 gpuss-2-thermal { 7718 polling-delay-passive = <10>; 7719 7720 thermal-sensors = <&tsens0 7>; 7721 7722 cooling-maps { 7723 map0 { 7724 trip = <&gpuss2_alert0>; 7725 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7726 }; 7727 }; 7728 7729 trips { 7730 gpuss2_alert0: trip-point0 { 7731 temperature = <105000>; 7732 hysteresis = <5000>; 7733 type = "passive"; 7734 }; 7735 7736 trip-point1 { 7737 temperature = <115000>; 7738 hysteresis = <5000>; 7739 type = "passive"; 7740 }; 7741 }; 7742 }; 7743 7744 audio-thermal { 7745 thermal-sensors = <&tsens0 8>; 7746 7747 trips { 7748 trip-point0 { 7749 temperature = <105000>; 7750 hysteresis = <5000>; 7751 type = "passive"; 7752 }; 7753 7754 trip-point1 { 7755 temperature = <115000>; 7756 hysteresis = <5000>; 7757 type = "passive"; 7758 }; 7759 }; 7760 }; 7761 7762 camss-0-thermal { 7763 thermal-sensors = <&tsens0 9>; 7764 7765 trips { 7766 trip-point0 { 7767 temperature = <105000>; 7768 hysteresis = <5000>; 7769 type = "passive"; 7770 }; 7771 7772 trip-point1 { 7773 temperature = <115000>; 7774 hysteresis = <5000>; 7775 type = "passive"; 7776 }; 7777 }; 7778 }; 7779 7780 pcie-0-thermal { 7781 thermal-sensors = <&tsens0 10>; 7782 7783 trips { 7784 trip-point0 { 7785 temperature = <105000>; 7786 hysteresis = <5000>; 7787 type = "passive"; 7788 }; 7789 7790 trip-point1 { 7791 temperature = <115000>; 7792 hysteresis = <5000>; 7793 type = "passive"; 7794 }; 7795 }; 7796 }; 7797 7798 cpuss-0-0-thermal { 7799 thermal-sensors = <&tsens0 11>; 7800 7801 trips { 7802 trip-point0 { 7803 temperature = <105000>; 7804 hysteresis = <5000>; 7805 type = "passive"; 7806 }; 7807 7808 trip-point1 { 7809 temperature = <115000>; 7810 hysteresis = <5000>; 7811 type = "passive"; 7812 }; 7813 }; 7814 }; 7815 7816 aoss-1-thermal { 7817 thermal-sensors = <&tsens1 0>; 7818 7819 trips { 7820 trip-point0 { 7821 temperature = <105000>; 7822 hysteresis = <5000>; 7823 type = "passive"; 7824 }; 7825 7826 trip-point1 { 7827 temperature = <115000>; 7828 hysteresis = <5000>; 7829 type = "passive"; 7830 }; 7831 }; 7832 }; 7833 7834 cpu-0-0-1-thermal { 7835 polling-delay-passive = <10>; 7836 7837 thermal-sensors = <&tsens1 1>; 7838 7839 trips { 7840 trip-point0 { 7841 temperature = <105000>; 7842 hysteresis = <5000>; 7843 type = "passive"; 7844 }; 7845 7846 trip-point1 { 7847 temperature = <115000>; 7848 hysteresis = <5000>; 7849 type = "passive"; 7850 }; 7851 }; 7852 }; 7853 7854 cpu-0-1-1-thermal { 7855 polling-delay-passive = <10>; 7856 7857 thermal-sensors = <&tsens1 2>; 7858 7859 trips { 7860 trip-point0 { 7861 temperature = <105000>; 7862 hysteresis = <5000>; 7863 type = "passive"; 7864 }; 7865 7866 trip-point1 { 7867 temperature = <115000>; 7868 hysteresis = <5000>; 7869 type = "passive"; 7870 }; 7871 }; 7872 }; 7873 7874 cpu-0-2-1-thermal { 7875 polling-delay-passive = <10>; 7876 7877 thermal-sensors = <&tsens1 3>; 7878 7879 trips { 7880 trip-point0 { 7881 temperature = <105000>; 7882 hysteresis = <5000>; 7883 type = "passive"; 7884 }; 7885 7886 trip-point1 { 7887 temperature = <115000>; 7888 hysteresis = <5000>; 7889 type = "passive"; 7890 }; 7891 }; 7892 }; 7893 7894 cpu-0-3-1-thermal { 7895 polling-delay-passive = <10>; 7896 7897 thermal-sensors = <&tsens1 4>; 7898 7899 trips { 7900 trip-point0 { 7901 temperature = <105000>; 7902 hysteresis = <5000>; 7903 type = "passive"; 7904 }; 7905 7906 trip-point1 { 7907 temperature = <115000>; 7908 hysteresis = <5000>; 7909 type = "passive"; 7910 }; 7911 }; 7912 }; 7913 7914 gpuss-3-thermal { 7915 polling-delay-passive = <10>; 7916 7917 thermal-sensors = <&tsens1 5>; 7918 7919 cooling-maps { 7920 map0 { 7921 trip = <&gpuss3_alert0>; 7922 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7923 }; 7924 }; 7925 7926 trips { 7927 gpuss3_alert0: trip-point0 { 7928 temperature = <105000>; 7929 hysteresis = <5000>; 7930 type = "passive"; 7931 }; 7932 7933 trip-point1 { 7934 temperature = <115000>; 7935 hysteresis = <5000>; 7936 type = "passive"; 7937 }; 7938 }; 7939 }; 7940 7941 gpuss-4-thermal { 7942 polling-delay-passive = <10>; 7943 7944 thermal-sensors = <&tsens1 6>; 7945 7946 cooling-maps { 7947 map0 { 7948 trip = <&gpuss4_alert0>; 7949 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7950 }; 7951 }; 7952 7953 trips { 7954 gpuss4_alert0: trip-point0 { 7955 temperature = <105000>; 7956 hysteresis = <5000>; 7957 type = "passive"; 7958 }; 7959 7960 trip-point1 { 7961 temperature = <115000>; 7962 hysteresis = <5000>; 7963 type = "passive"; 7964 }; 7965 }; 7966 }; 7967 7968 gpuss-5-thermal { 7969 polling-delay-passive = <10>; 7970 7971 thermal-sensors = <&tsens1 7>; 7972 7973 cooling-maps { 7974 map0 { 7975 trip = <&gpuss5_alert0>; 7976 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7977 }; 7978 }; 7979 7980 trips { 7981 gpuss5_alert0: trip-point0 { 7982 temperature = <105000>; 7983 hysteresis = <5000>; 7984 type = "passive"; 7985 }; 7986 7987 trip-point1 { 7988 temperature = <115000>; 7989 hysteresis = <5000>; 7990 type = "passive"; 7991 }; 7992 }; 7993 }; 7994 7995 video-thermal { 7996 thermal-sensors = <&tsens1 8>; 7997 7998 trips { 7999 trip-point0 { 8000 temperature = <105000>; 8001 hysteresis = <5000>; 8002 type = "passive"; 8003 }; 8004 8005 trip-point1 { 8006 temperature = <115000>; 8007 hysteresis = <5000>; 8008 type = "passive"; 8009 }; 8010 }; 8011 }; 8012 8013 camss-1-thermal { 8014 thermal-sensors = <&tsens1 9>; 8015 8016 trips { 8017 trip-point0 { 8018 temperature = <105000>; 8019 hysteresis = <5000>; 8020 type = "passive"; 8021 }; 8022 8023 trip-point1 { 8024 temperature = <115000>; 8025 hysteresis = <5000>; 8026 type = "passive"; 8027 }; 8028 }; 8029 }; 8030 8031 pcie-1-thermal { 8032 thermal-sensors = <&tsens1 10>; 8033 8034 trips { 8035 trip-point0 { 8036 temperature = <105000>; 8037 hysteresis = <5000>; 8038 type = "passive"; 8039 }; 8040 8041 trip-point1 { 8042 temperature = <115000>; 8043 hysteresis = <5000>; 8044 type = "passive"; 8045 }; 8046 }; 8047 }; 8048 8049 cpuss-0-1-thermal { 8050 thermal-sensors = <&tsens1 11>; 8051 8052 trips { 8053 trip-point0 { 8054 temperature = <105000>; 8055 hysteresis = <5000>; 8056 type = "passive"; 8057 }; 8058 8059 trip-point1 { 8060 temperature = <115000>; 8061 hysteresis = <5000>; 8062 type = "passive"; 8063 }; 8064 }; 8065 }; 8066 8067 aoss-2-thermal { 8068 thermal-sensors = <&tsens2 0>; 8069 8070 trips { 8071 trip-point0 { 8072 temperature = <105000>; 8073 hysteresis = <5000>; 8074 type = "passive"; 8075 }; 8076 8077 trip-point1 { 8078 temperature = <115000>; 8079 hysteresis = <5000>; 8080 type = "passive"; 8081 }; 8082 }; 8083 }; 8084 8085 cpu-1-0-0-thermal { 8086 polling-delay-passive = <10>; 8087 8088 thermal-sensors = <&tsens2 1>; 8089 8090 trips { 8091 trip-point0 { 8092 temperature = <105000>; 8093 hysteresis = <5000>; 8094 type = "passive"; 8095 }; 8096 8097 trip-point1 { 8098 temperature = <115000>; 8099 hysteresis = <5000>; 8100 type = "passive"; 8101 }; 8102 }; 8103 }; 8104 8105 cpu-1-1-0-thermal { 8106 polling-delay-passive = <10>; 8107 8108 thermal-sensors = <&tsens2 2>; 8109 8110 trips { 8111 trip-point0 { 8112 temperature = <105000>; 8113 hysteresis = <5000>; 8114 type = "passive"; 8115 }; 8116 8117 trip-point1 { 8118 temperature = <115000>; 8119 hysteresis = <5000>; 8120 type = "passive"; 8121 }; 8122 }; 8123 }; 8124 8125 cpu-1-2-0-thermal { 8126 polling-delay-passive = <10>; 8127 8128 thermal-sensors = <&tsens2 3>; 8129 8130 trips { 8131 trip-point0 { 8132 temperature = <105000>; 8133 hysteresis = <5000>; 8134 type = "passive"; 8135 }; 8136 8137 trip-point1 { 8138 temperature = <115000>; 8139 hysteresis = <5000>; 8140 type = "passive"; 8141 }; 8142 }; 8143 }; 8144 8145 cpu-1-3-0-thermal { 8146 polling-delay-passive = <10>; 8147 8148 thermal-sensors = <&tsens2 4>; 8149 8150 trips { 8151 trip-point0 { 8152 temperature = <105000>; 8153 hysteresis = <5000>; 8154 type = "passive"; 8155 }; 8156 8157 trip-point1 { 8158 temperature = <115000>; 8159 hysteresis = <5000>; 8160 type = "passive"; 8161 }; 8162 }; 8163 }; 8164 8165 nsp-0-0-0-thermal { 8166 polling-delay-passive = <10>; 8167 8168 thermal-sensors = <&tsens2 5>; 8169 8170 trips { 8171 trip-point0 { 8172 temperature = <105000>; 8173 hysteresis = <5000>; 8174 type = "passive"; 8175 }; 8176 8177 trip-point1 { 8178 temperature = <115000>; 8179 hysteresis = <5000>; 8180 type = "passive"; 8181 }; 8182 }; 8183 }; 8184 8185 nsp-0-1-0-thermal { 8186 polling-delay-passive = <10>; 8187 8188 thermal-sensors = <&tsens2 6>; 8189 8190 trips { 8191 trip-point0 { 8192 temperature = <105000>; 8193 hysteresis = <5000>; 8194 type = "passive"; 8195 }; 8196 8197 trip-point1 { 8198 temperature = <115000>; 8199 hysteresis = <5000>; 8200 type = "passive"; 8201 }; 8202 }; 8203 }; 8204 8205 nsp-0-2-0-thermal { 8206 polling-delay-passive = <10>; 8207 8208 thermal-sensors = <&tsens2 7>; 8209 8210 trips { 8211 trip-point0 { 8212 temperature = <105000>; 8213 hysteresis = <5000>; 8214 type = "passive"; 8215 }; 8216 8217 trip-point1 { 8218 temperature = <115000>; 8219 hysteresis = <5000>; 8220 type = "passive"; 8221 }; 8222 }; 8223 }; 8224 8225 nsp-1-0-0-thermal { 8226 polling-delay-passive = <10>; 8227 8228 thermal-sensors = <&tsens2 8>; 8229 8230 trips { 8231 trip-point0 { 8232 temperature = <105000>; 8233 hysteresis = <5000>; 8234 type = "passive"; 8235 }; 8236 8237 trip-point1 { 8238 temperature = <115000>; 8239 hysteresis = <5000>; 8240 type = "passive"; 8241 }; 8242 }; 8243 }; 8244 8245 nsp-1-1-0-thermal { 8246 polling-delay-passive = <10>; 8247 8248 thermal-sensors = <&tsens2 9>; 8249 8250 trips { 8251 trip-point0 { 8252 temperature = <105000>; 8253 hysteresis = <5000>; 8254 type = "passive"; 8255 }; 8256 8257 trip-point1 { 8258 temperature = <115000>; 8259 hysteresis = <5000>; 8260 type = "passive"; 8261 }; 8262 }; 8263 }; 8264 8265 nsp-1-2-0-thermal { 8266 polling-delay-passive = <10>; 8267 8268 thermal-sensors = <&tsens2 10>; 8269 8270 trips { 8271 trip-point0 { 8272 temperature = <105000>; 8273 hysteresis = <5000>; 8274 type = "passive"; 8275 }; 8276 8277 trip-point1 { 8278 temperature = <115000>; 8279 hysteresis = <5000>; 8280 type = "passive"; 8281 }; 8282 }; 8283 }; 8284 8285 ddrss-0-thermal { 8286 thermal-sensors = <&tsens2 11>; 8287 8288 trips { 8289 trip-point0 { 8290 temperature = <105000>; 8291 hysteresis = <5000>; 8292 type = "passive"; 8293 }; 8294 8295 trip-point1 { 8296 temperature = <115000>; 8297 hysteresis = <5000>; 8298 type = "passive"; 8299 }; 8300 }; 8301 }; 8302 8303 cpuss-1-0-thermal { 8304 thermal-sensors = <&tsens2 12>; 8305 8306 trips { 8307 trip-point0 { 8308 temperature = <105000>; 8309 hysteresis = <5000>; 8310 type = "passive"; 8311 }; 8312 8313 trip-point1 { 8314 temperature = <115000>; 8315 hysteresis = <5000>; 8316 type = "passive"; 8317 }; 8318 }; 8319 }; 8320 8321 aoss-3-thermal { 8322 thermal-sensors = <&tsens3 0>; 8323 8324 trips { 8325 trip-point0 { 8326 temperature = <105000>; 8327 hysteresis = <5000>; 8328 type = "passive"; 8329 }; 8330 8331 trip-point1 { 8332 temperature = <115000>; 8333 hysteresis = <5000>; 8334 type = "passive"; 8335 }; 8336 }; 8337 }; 8338 8339 cpu-1-0-1-thermal { 8340 polling-delay-passive = <10>; 8341 8342 thermal-sensors = <&tsens3 1>; 8343 8344 trips { 8345 trip-point0 { 8346 temperature = <105000>; 8347 hysteresis = <5000>; 8348 type = "passive"; 8349 }; 8350 8351 trip-point1 { 8352 temperature = <115000>; 8353 hysteresis = <5000>; 8354 type = "passive"; 8355 }; 8356 }; 8357 }; 8358 8359 cpu-1-1-1-thermal { 8360 polling-delay-passive = <10>; 8361 8362 thermal-sensors = <&tsens3 2>; 8363 8364 trips { 8365 trip-point0 { 8366 temperature = <105000>; 8367 hysteresis = <5000>; 8368 type = "passive"; 8369 }; 8370 8371 trip-point1 { 8372 temperature = <115000>; 8373 hysteresis = <5000>; 8374 type = "passive"; 8375 }; 8376 }; 8377 }; 8378 8379 cpu-1-2-1-thermal { 8380 polling-delay-passive = <10>; 8381 8382 thermal-sensors = <&tsens3 3>; 8383 8384 trips { 8385 trip-point0 { 8386 temperature = <105000>; 8387 hysteresis = <5000>; 8388 type = "passive"; 8389 }; 8390 8391 trip-point1 { 8392 temperature = <115000>; 8393 hysteresis = <5000>; 8394 type = "passive"; 8395 }; 8396 }; 8397 }; 8398 8399 cpu-1-3-1-thermal { 8400 polling-delay-passive = <10>; 8401 8402 thermal-sensors = <&tsens3 4>; 8403 8404 trips { 8405 trip-point0 { 8406 temperature = <105000>; 8407 hysteresis = <5000>; 8408 type = "passive"; 8409 }; 8410 8411 trip-point1 { 8412 temperature = <115000>; 8413 hysteresis = <5000>; 8414 type = "passive"; 8415 }; 8416 }; 8417 }; 8418 8419 nsp-0-0-1-thermal { 8420 polling-delay-passive = <10>; 8421 8422 thermal-sensors = <&tsens3 5>; 8423 8424 trips { 8425 trip-point0 { 8426 temperature = <105000>; 8427 hysteresis = <5000>; 8428 type = "passive"; 8429 }; 8430 8431 trip-point1 { 8432 temperature = <115000>; 8433 hysteresis = <5000>; 8434 type = "passive"; 8435 }; 8436 }; 8437 }; 8438 8439 nsp-0-1-1-thermal { 8440 polling-delay-passive = <10>; 8441 8442 thermal-sensors = <&tsens3 6>; 8443 8444 trips { 8445 trip-point0 { 8446 temperature = <105000>; 8447 hysteresis = <5000>; 8448 type = "passive"; 8449 }; 8450 8451 trip-point1 { 8452 temperature = <115000>; 8453 hysteresis = <5000>; 8454 type = "passive"; 8455 }; 8456 }; 8457 }; 8458 8459 nsp-0-2-1-thermal { 8460 polling-delay-passive = <10>; 8461 8462 thermal-sensors = <&tsens3 7>; 8463 8464 trips { 8465 trip-point0 { 8466 temperature = <105000>; 8467 hysteresis = <5000>; 8468 type = "passive"; 8469 }; 8470 8471 trip-point1 { 8472 temperature = <115000>; 8473 hysteresis = <5000>; 8474 type = "passive"; 8475 }; 8476 }; 8477 }; 8478 8479 nsp-1-0-1-thermal { 8480 polling-delay-passive = <10>; 8481 8482 thermal-sensors = <&tsens3 8>; 8483 8484 trips { 8485 trip-point0 { 8486 temperature = <105000>; 8487 hysteresis = <5000>; 8488 type = "passive"; 8489 }; 8490 8491 trip-point1 { 8492 temperature = <115000>; 8493 hysteresis = <5000>; 8494 type = "passive"; 8495 }; 8496 }; 8497 }; 8498 8499 nsp-1-1-1-thermal { 8500 polling-delay-passive = <10>; 8501 8502 thermal-sensors = <&tsens3 9>; 8503 8504 trips { 8505 trip-point0 { 8506 temperature = <105000>; 8507 hysteresis = <5000>; 8508 type = "passive"; 8509 }; 8510 8511 trip-point1 { 8512 temperature = <115000>; 8513 hysteresis = <5000>; 8514 type = "passive"; 8515 }; 8516 }; 8517 }; 8518 8519 nsp-1-2-1-thermal { 8520 polling-delay-passive = <10>; 8521 8522 thermal-sensors = <&tsens3 10>; 8523 8524 trips { 8525 trip-point0 { 8526 temperature = <105000>; 8527 hysteresis = <5000>; 8528 type = "passive"; 8529 }; 8530 8531 trip-point1 { 8532 temperature = <115000>; 8533 hysteresis = <5000>; 8534 type = "passive"; 8535 }; 8536 }; 8537 }; 8538 8539 ddrss-1-thermal { 8540 thermal-sensors = <&tsens3 11>; 8541 8542 trips { 8543 trip-point0 { 8544 temperature = <105000>; 8545 hysteresis = <5000>; 8546 type = "passive"; 8547 }; 8548 8549 trip-point1 { 8550 temperature = <115000>; 8551 hysteresis = <5000>; 8552 type = "passive"; 8553 }; 8554 }; 8555 }; 8556 8557 cpuss-1-1-thermal { 8558 thermal-sensors = <&tsens3 12>; 8559 8560 trips { 8561 trip-point0 { 8562 temperature = <105000>; 8563 hysteresis = <5000>; 8564 type = "passive"; 8565 }; 8566 8567 trip-point1 { 8568 temperature = <115000>; 8569 hysteresis = <5000>; 8570 type = "passive"; 8571 }; 8572 }; 8573 }; 8574 }; 8575 8576 arch_timer: timer { 8577 compatible = "arm,armv8-timer"; 8578 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 8579 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 8580 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 8581 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 8582 }; 8583 8584 turing-llm-tpdm { 8585 compatible = "qcom,coresight-static-tpdm"; 8586 8587 qcom,cmb-element-bits = <32>; 8588 8589 out-ports { 8590 port { 8591 turing_llm_tpdm_out: endpoint { 8592 remote-endpoint = <&turing0_funnel_in1>; 8593 }; 8594 }; 8595 }; 8596 }; 8597 8598 pcie0: pcie@1c00000 { 8599 compatible = "qcom,pcie-sa8775p"; 8600 reg = <0x0 0x01c00000 0x0 0x3000>, 8601 <0x0 0x40000000 0x0 0xf20>, 8602 <0x0 0x40000f20 0x0 0xa8>, 8603 <0x0 0x40001000 0x0 0x4000>, 8604 <0x0 0x40100000 0x0 0x100000>, 8605 <0x0 0x01c03000 0x0 0x1000>; 8606 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 8607 device_type = "pci"; 8608 8609 #address-cells = <3>; 8610 #size-cells = <2>; 8611 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 8612 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 8613 bus-range = <0x00 0xff>; 8614 8615 dma-coherent; 8616 8617 linux,pci-domain = <0>; 8618 num-lanes = <2>; 8619 8620 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 8621 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 8622 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 8623 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 8624 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 8625 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 8626 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 8627 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 8628 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 8629 interrupt-names = "msi0", 8630 "msi1", 8631 "msi2", 8632 "msi3", 8633 "msi4", 8634 "msi5", 8635 "msi6", 8636 "msi7", 8637 "global"; 8638 #interrupt-cells = <1>; 8639 interrupt-map-mask = <0 0 0 0x7>; 8640 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 8641 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 8642 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 8643 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 8644 8645 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 8646 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 8647 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 8648 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 8649 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 8650 8651 clock-names = "aux", 8652 "cfg", 8653 "bus_master", 8654 "bus_slave", 8655 "slave_q2a"; 8656 8657 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 8658 assigned-clock-rates = <19200000>; 8659 8660 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 8661 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 8662 interconnect-names = "pcie-mem", "cpu-pcie"; 8663 8664 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 8665 <0x100 &pcie_smmu 0x0001 0x1>; 8666 8667 resets = <&gcc GCC_PCIE_0_BCR>, 8668 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; 8669 reset-names = "pci", 8670 "link_down"; 8671 8672 power-domains = <&gcc PCIE_0_GDSC>; 8673 8674 phys = <&pcie0_phy>; 8675 phy-names = "pciephy"; 8676 8677 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 8678 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 8679 8680 status = "disabled"; 8681 8682 pcieport0: pcie@0 { 8683 device_type = "pci"; 8684 reg = <0x0 0x0 0x0 0x0 0x0>; 8685 bus-range = <0x01 0xff>; 8686 8687 #address-cells = <3>; 8688 #size-cells = <2>; 8689 ranges; 8690 }; 8691 }; 8692 8693 pcie0_ep: pcie-ep@1c00000 { 8694 compatible = "qcom,sa8775p-pcie-ep"; 8695 reg = <0x0 0x01c00000 0x0 0x3000>, 8696 <0x0 0x40000000 0x0 0xf20>, 8697 <0x0 0x40000f20 0x0 0xa8>, 8698 <0x0 0x40001000 0x0 0x4000>, 8699 <0x0 0x40200000 0x0 0x1fe00000>, 8700 <0x0 0x01c03000 0x0 0x1000>, 8701 <0x0 0x40005000 0x0 0x2000>; 8702 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 8703 "mmio", "dma"; 8704 8705 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 8706 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 8707 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 8708 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 8709 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 8710 8711 clock-names = "aux", 8712 "cfg", 8713 "bus_master", 8714 "bus_slave", 8715 "slave_q2a"; 8716 8717 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 8718 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 8719 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; 8720 8721 interrupt-names = "global", "doorbell", "dma"; 8722 8723 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 8724 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 8725 interconnect-names = "pcie-mem", "cpu-pcie"; 8726 8727 dma-coherent; 8728 iommus = <&pcie_smmu 0x0000 0x7f>; 8729 resets = <&gcc GCC_PCIE_0_BCR>; 8730 reset-names = "core"; 8731 power-domains = <&gcc PCIE_0_GDSC>; 8732 phys = <&pcie0_phy>; 8733 phy-names = "pciephy"; 8734 num-lanes = <2>; 8735 linux,pci-domain = <0>; 8736 8737 status = "disabled"; 8738 }; 8739 8740 pcie0_phy: phy@1c04000 { 8741 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 8742 reg = <0x0 0x1c04000 0x0 0x2000>; 8743 8744 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, 8745 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 8746 <&gcc GCC_PCIE_CLKREF_EN>, 8747 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 8748 <&gcc GCC_PCIE_0_PIPE_CLK>, 8749 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; 8750 clock-names = "aux", 8751 "cfg_ahb", 8752 "ref", 8753 "rchng", 8754 "pipe", 8755 "pipediv2"; 8756 8757 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 8758 assigned-clock-rates = <100000000>; 8759 8760 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 8761 reset-names = "phy"; 8762 8763 #clock-cells = <0>; 8764 clock-output-names = "pcie_0_pipe_clk"; 8765 8766 #phy-cells = <0>; 8767 8768 status = "disabled"; 8769 }; 8770 8771 pcie1: pcie@1c10000 { 8772 compatible = "qcom,pcie-sa8775p"; 8773 reg = <0x0 0x01c10000 0x0 0x3000>, 8774 <0x0 0x60000000 0x0 0xf20>, 8775 <0x0 0x60000f20 0x0 0xa8>, 8776 <0x0 0x60001000 0x0 0x4000>, 8777 <0x0 0x60100000 0x0 0x100000>, 8778 <0x0 0x01c13000 0x0 0x1000>; 8779 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 8780 device_type = "pci"; 8781 8782 #address-cells = <3>; 8783 #size-cells = <2>; 8784 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 8785 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 8786 bus-range = <0x00 0xff>; 8787 8788 dma-coherent; 8789 8790 linux,pci-domain = <1>; 8791 num-lanes = <4>; 8792 8793 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 8794 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 8795 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 8796 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 8797 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 8798 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 8799 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 8800 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 8801 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; 8802 interrupt-names = "msi0", 8803 "msi1", 8804 "msi2", 8805 "msi3", 8806 "msi4", 8807 "msi5", 8808 "msi6", 8809 "msi7", 8810 "global"; 8811 #interrupt-cells = <1>; 8812 interrupt-map-mask = <0 0 0 0x7>; 8813 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 8814 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 8815 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 8816 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 8817 8818 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 8819 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 8820 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 8821 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 8822 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 8823 8824 clock-names = "aux", 8825 "cfg", 8826 "bus_master", 8827 "bus_slave", 8828 "slave_q2a"; 8829 8830 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 8831 assigned-clock-rates = <19200000>; 8832 8833 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 8834 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 8835 interconnect-names = "pcie-mem", "cpu-pcie"; 8836 8837 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 8838 <0x100 &pcie_smmu 0x0081 0x1>; 8839 8840 resets = <&gcc GCC_PCIE_1_BCR>, 8841 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 8842 reset-names = "pci", 8843 "link_down"; 8844 8845 power-domains = <&gcc PCIE_1_GDSC>; 8846 8847 phys = <&pcie1_phy>; 8848 phy-names = "pciephy"; 8849 8850 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 8851 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 8852 8853 status = "disabled"; 8854 8855 pcie@0 { 8856 device_type = "pci"; 8857 reg = <0x0 0x0 0x0 0x0 0x0>; 8858 bus-range = <0x01 0xff>; 8859 8860 #address-cells = <3>; 8861 #size-cells = <2>; 8862 ranges; 8863 }; 8864 }; 8865 8866 pcie1_ep: pcie-ep@1c10000 { 8867 compatible = "qcom,sa8775p-pcie-ep"; 8868 reg = <0x0 0x01c10000 0x0 0x3000>, 8869 <0x0 0x60000000 0x0 0xf20>, 8870 <0x0 0x60000f20 0x0 0xa8>, 8871 <0x0 0x60001000 0x0 0x4000>, 8872 <0x0 0x60200000 0x0 0x1fe00000>, 8873 <0x0 0x01c13000 0x0 0x1000>, 8874 <0x0 0x60005000 0x0 0x2000>; 8875 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 8876 "mmio", "dma"; 8877 8878 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 8879 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 8880 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 8881 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 8882 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 8883 8884 clock-names = "aux", 8885 "cfg", 8886 "bus_master", 8887 "bus_slave", 8888 "slave_q2a"; 8889 8890 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 8891 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 8892 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 8893 8894 interrupt-names = "global", "doorbell", "dma"; 8895 8896 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 8897 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 8898 interconnect-names = "pcie-mem", "cpu-pcie"; 8899 8900 dma-coherent; 8901 iommus = <&pcie_smmu 0x80 0x7f>; 8902 resets = <&gcc GCC_PCIE_1_BCR>; 8903 reset-names = "core"; 8904 power-domains = <&gcc PCIE_1_GDSC>; 8905 phys = <&pcie1_phy>; 8906 phy-names = "pciephy"; 8907 num-lanes = <4>; 8908 linux,pci-domain = <1>; 8909 8910 status = "disabled"; 8911 }; 8912 8913 pcie1_phy: phy@1c14000 { 8914 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 8915 reg = <0x0 0x1c14000 0x0 0x4000>; 8916 8917 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 8918 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 8919 <&gcc GCC_PCIE_CLKREF_EN>, 8920 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 8921 <&gcc GCC_PCIE_1_PIPE_CLK>, 8922 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; 8923 clock-names = "aux", 8924 "cfg_ahb", 8925 "ref", 8926 "rchng", 8927 "pipe", 8928 "pipediv2"; 8929 8930 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 8931 assigned-clock-rates = <100000000>; 8932 8933 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 8934 reset-names = "phy"; 8935 8936 #clock-cells = <0>; 8937 clock-output-names = "pcie_1_pipe_clk"; 8938 8939 #phy-cells = <0>; 8940 8941 status = "disabled"; 8942 }; 8943}; 8944