1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ9574 SoC device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,apss-ipq.h> 10#include <dt-bindings/clock/qcom,ipq-cmn-pll.h> 11#include <dt-bindings/clock/qcom,ipq9574-gcc.h> 12#include <dt-bindings/interconnect/qcom,ipq9574.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/reset/qcom,ipq9574-gcc.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 clocks { 23 ref_48mhz_clk: ref-48mhz-clk { 24 compatible = "fixed-factor-clock"; 25 clocks = <&xo_clk>; 26 #clock-cells = <0>; 27 }; 28 29 sleep_clk: sleep-clk { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 }; 33 34 xo_board_clk: xo-board-clk { 35 compatible = "fixed-factor-clock"; 36 clocks = <&ref_48mhz_clk>; 37 #clock-cells = <0>; 38 }; 39 40 xo_clk: xo-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a73"; 53 reg = <0x0>; 54 enable-method = "psci"; 55 next-level-cache = <&l2_0>; 56 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 57 clock-names = "cpu"; 58 operating-points-v2 = <&cpu_opp_table>; 59 #cooling-cells = <2>; 60 }; 61 62 cpu1: cpu@1 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a73"; 65 reg = <0x1>; 66 enable-method = "psci"; 67 next-level-cache = <&l2_0>; 68 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 69 clock-names = "cpu"; 70 operating-points-v2 = <&cpu_opp_table>; 71 #cooling-cells = <2>; 72 }; 73 74 cpu2: cpu@2 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a73"; 77 reg = <0x2>; 78 enable-method = "psci"; 79 next-level-cache = <&l2_0>; 80 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 81 clock-names = "cpu"; 82 operating-points-v2 = <&cpu_opp_table>; 83 #cooling-cells = <2>; 84 }; 85 86 cpu3: cpu@3 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a73"; 89 reg = <0x3>; 90 enable-method = "psci"; 91 next-level-cache = <&l2_0>; 92 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 93 clock-names = "cpu"; 94 operating-points-v2 = <&cpu_opp_table>; 95 #cooling-cells = <2>; 96 }; 97 98 l2_0: l2-cache { 99 compatible = "cache"; 100 cache-level = <2>; 101 cache-unified; 102 }; 103 }; 104 105 firmware { 106 scm { 107 compatible = "qcom,scm-ipq9574", "qcom,scm"; 108 qcom,dload-mode = <&tcsr 0x6100>; 109 }; 110 }; 111 112 memory@40000000 { 113 device_type = "memory"; 114 /* We expect the bootloader to fill in the size */ 115 reg = <0x0 0x40000000 0x0 0x0>; 116 }; 117 118 cpu_opp_table: opp-table-cpu { 119 compatible = "operating-points-v2-kryo-cpu"; 120 opp-shared; 121 nvmem-cells = <&cpu_speed_bin>; 122 123 opp-936000000 { 124 opp-hz = /bits/ 64 <936000000>; 125 opp-microvolt = <725000>; 126 opp-supported-hw = <0xf>; 127 clock-latency-ns = <200000>; 128 }; 129 130 opp-1104000000 { 131 opp-hz = /bits/ 64 <1104000000>; 132 opp-microvolt = <787500>; 133 opp-supported-hw = <0xf>; 134 clock-latency-ns = <200000>; 135 }; 136 137 opp-1200000000 { 138 opp-hz = /bits/ 64 <1200000000>; 139 opp-microvolt = <862500>; 140 opp-supported-hw = <0xf>; 141 clock-latency-ns = <200000>; 142 }; 143 144 opp-1416000000 { 145 opp-hz = /bits/ 64 <1416000000>; 146 opp-microvolt = <862500>; 147 opp-supported-hw = <0x7>; 148 clock-latency-ns = <200000>; 149 }; 150 151 opp-1488000000 { 152 opp-hz = /bits/ 64 <1488000000>; 153 opp-microvolt = <925000>; 154 opp-supported-hw = <0x7>; 155 clock-latency-ns = <200000>; 156 }; 157 158 opp-1800000000 { 159 opp-hz = /bits/ 64 <1800000000>; 160 opp-microvolt = <987500>; 161 opp-supported-hw = <0x5>; 162 clock-latency-ns = <200000>; 163 }; 164 165 opp-2208000000 { 166 opp-hz = /bits/ 64 <2208000000>; 167 opp-microvolt = <1062500>; 168 opp-supported-hw = <0x1>; 169 clock-latency-ns = <200000>; 170 }; 171 }; 172 173 pmu { 174 compatible = "arm,cortex-a73-pmu"; 175 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 176 }; 177 178 psci { 179 compatible = "arm,psci-1.0"; 180 method = "smc"; 181 }; 182 183 rpm: remoteproc { 184 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc"; 185 186 glink-edge { 187 compatible = "qcom,glink-rpm"; 188 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 189 qcom,rpm-msg-ram = <&rpm_msg_ram>; 190 mboxes = <&apcs_glb 0>; 191 192 rpm_requests: rpm-requests { 193 compatible = "qcom,rpm-ipq9574", "qcom,glink-smd-rpm"; 194 qcom,glink-channels = "rpm_requests"; 195 }; 196 }; 197 }; 198 199 reserved-memory { 200 #address-cells = <2>; 201 #size-cells = <2>; 202 ranges; 203 204 bootloader@4a100000 { 205 reg = <0x0 0x4a100000 0x0 0x400000>; 206 no-map; 207 }; 208 209 sbl@4a500000 { 210 reg = <0x0 0x4a500000 0x0 0x100000>; 211 no-map; 212 }; 213 214 tz_region: tz@4a600000 { 215 reg = <0x0 0x4a600000 0x0 0x400000>; 216 no-map; 217 }; 218 219 smem@4aa00000 { 220 compatible = "qcom,smem"; 221 reg = <0x0 0x4aa00000 0x0 0x100000>; 222 hwlocks = <&tcsr_mutex 3>; 223 no-map; 224 }; 225 }; 226 227 soc: soc@0 { 228 compatible = "simple-bus"; 229 #address-cells = <1>; 230 #size-cells = <1>; 231 ranges = <0 0 0 0xffffffff>; 232 233 rpm_msg_ram: sram@60000 { 234 compatible = "qcom,rpm-msg-ram"; 235 reg = <0x00060000 0x6000>; 236 }; 237 238 pcie0_phy: phy@84000 { 239 compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; 240 reg = <0x00084000 0x1000>; 241 242 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 243 <&gcc GCC_PCIE0_AHB_CLK>, 244 <&gcc GCC_PCIE0_PIPE_CLK>; 245 clock-names = "aux", "cfg_ahb", "pipe"; 246 247 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; 248 assigned-clock-rates = <20000000>; 249 250 resets = <&gcc GCC_PCIE0_PHY_BCR>, 251 <&gcc GCC_PCIE0PHY_PHY_BCR>; 252 reset-names = "phy", "common"; 253 254 #clock-cells = <0>; 255 clock-output-names = "gcc_pcie0_pipe_clk_src"; 256 257 #phy-cells = <0>; 258 status = "disabled"; 259 }; 260 261 pcie2_phy: phy@8c000 { 262 compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; 263 reg = <0x0008c000 0x2000>; 264 265 clocks = <&gcc GCC_PCIE2_AUX_CLK>, 266 <&gcc GCC_PCIE2_AHB_CLK>, 267 <&gcc GCC_PCIE2_PIPE_CLK>; 268 clock-names = "aux", "cfg_ahb", "pipe"; 269 270 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; 271 assigned-clock-rates = <20000000>; 272 273 resets = <&gcc GCC_PCIE2_PHY_BCR>, 274 <&gcc GCC_PCIE2PHY_PHY_BCR>; 275 reset-names = "phy", "common"; 276 277 #clock-cells = <0>; 278 clock-output-names = "gcc_pcie2_pipe_clk_src"; 279 280 #phy-cells = <0>; 281 status = "disabled"; 282 }; 283 284 rng: rng@e3000 { 285 compatible = "qcom,ipq9574-trng", "qcom,trng"; 286 reg = <0x000e3000 0x1000>; 287 clocks = <&gcc GCC_PRNG_AHB_CLK>; 288 clock-names = "core"; 289 }; 290 291 mdio: mdio@90000 { 292 compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio"; 293 reg = <0x00090000 0x64>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 clocks = <&gcc GCC_MDIO_AHB_CLK>; 297 clock-names = "gcc_mdio_ahb_clk"; 298 status = "disabled"; 299 }; 300 301 pcie3_phy: phy@f4000 { 302 compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; 303 reg = <0x000f4000 0x2000>; 304 305 clocks = <&gcc GCC_PCIE3_AUX_CLK>, 306 <&gcc GCC_PCIE3_AHB_CLK>, 307 <&gcc GCC_PCIE3_PIPE_CLK>; 308 clock-names = "aux", "cfg_ahb", "pipe"; 309 310 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; 311 assigned-clock-rates = <20000000>; 312 313 resets = <&gcc GCC_PCIE3_PHY_BCR>, 314 <&gcc GCC_PCIE3PHY_PHY_BCR>; 315 reset-names = "phy", "common"; 316 317 #clock-cells = <0>; 318 clock-output-names = "gcc_pcie3_pipe_clk_src"; 319 320 #phy-cells = <0>; 321 status = "disabled"; 322 }; 323 324 pcie1_phy: phy@fc000 { 325 compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; 326 reg = <0x000fc000 0x1000>; 327 328 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 329 <&gcc GCC_PCIE1_AHB_CLK>, 330 <&gcc GCC_PCIE1_PIPE_CLK>; 331 clock-names = "aux", "cfg_ahb", "pipe"; 332 333 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; 334 assigned-clock-rates = <20000000>; 335 336 resets = <&gcc GCC_PCIE1_PHY_BCR>, 337 <&gcc GCC_PCIE1PHY_PHY_BCR>; 338 reset-names = "phy", "common"; 339 340 #clock-cells = <0>; 341 clock-output-names = "gcc_pcie1_pipe_clk_src"; 342 343 #phy-cells = <0>; 344 status = "disabled"; 345 }; 346 347 cmn_pll: clock-controller@9b000 { 348 compatible = "qcom,ipq9574-cmn-pll"; 349 reg = <0x0009b000 0x800>; 350 clocks = <&ref_48mhz_clk>, 351 <&gcc GCC_CMN_12GPLL_AHB_CLK>, 352 <&gcc GCC_CMN_12GPLL_SYS_CLK>; 353 clock-names = "ref", "ahb", "sys"; 354 #clock-cells = <1>; 355 assigned-clocks = <&cmn_pll CMN_PLL_CLK>; 356 assigned-clock-rates-u64 = /bits/ 64 <12000000000>; 357 }; 358 359 qfprom: efuse@a4000 { 360 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; 361 reg = <0x000a4000 0x5a1>; 362 #address-cells = <1>; 363 #size-cells = <1>; 364 365 cpu_speed_bin: cpu-speed-bin@15 { 366 reg = <0x15 0x2>; 367 bits = <7 2>; 368 }; 369 }; 370 371 cryptobam: dma-controller@704000 { 372 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 373 reg = <0x00704000 0x20000>; 374 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 375 #dma-cells = <1>; 376 qcom,ee = <1>; 377 qcom,num-ees = <4>; 378 num-channels = <16>; 379 qcom,controlled-remotely; 380 }; 381 382 crypto: crypto@73a000 { 383 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce"; 384 reg = <0x0073a000 0x6000>; 385 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 386 <&gcc GCC_CRYPTO_AXI_CLK>, 387 <&gcc GCC_CRYPTO_CLK>; 388 clock-names = "iface", "bus", "core"; 389 dmas = <&cryptobam 2>, <&cryptobam 3>; 390 dma-names = "rx", "tx"; 391 }; 392 393 tsens: thermal-sensor@4a9000 { 394 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens"; 395 reg = <0x004a9000 0x1000>, 396 <0x004a8000 0x1000>; 397 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 398 interrupt-names = "combined"; 399 #qcom,sensors = <16>; 400 #thermal-sensor-cells = <1>; 401 }; 402 403 tlmm: pinctrl@1000000 { 404 compatible = "qcom,ipq9574-tlmm"; 405 reg = <0x01000000 0x300000>; 406 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 407 gpio-controller; 408 #gpio-cells = <2>; 409 gpio-ranges = <&tlmm 0 0 65>; 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 413 uart2_pins: uart2-state { 414 pins = "gpio34", "gpio35"; 415 function = "blsp2_uart"; 416 drive-strength = <8>; 417 bias-disable; 418 }; 419 }; 420 421 gcc: clock-controller@1800000 { 422 compatible = "qcom,ipq9574-gcc"; 423 reg = <0x01800000 0x80000>; 424 clocks = <&xo_board_clk>, 425 <&sleep_clk>, 426 <0>, 427 <&pcie0_phy>, 428 <&pcie1_phy>, 429 <&pcie2_phy>, 430 <&pcie3_phy>, 431 <0>; 432 #clock-cells = <1>; 433 #reset-cells = <1>; 434 #interconnect-cells = <1>; 435 }; 436 437 tcsr_mutex: hwlock@1905000 { 438 compatible = "qcom,tcsr-mutex"; 439 reg = <0x01905000 0x20000>; 440 #hwlock-cells = <1>; 441 }; 442 443 tcsr: syscon@1937000 { 444 compatible = "qcom,tcsr-ipq9574", "syscon"; 445 reg = <0x01937000 0x21000>; 446 }; 447 448 sdhc_1: mmc@7804000 { 449 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; 450 reg = <0x07804000 0x1000>, 451 <0x07805000 0x1000>, 452 <0x07808000 0x2000>; 453 reg-names = "hc", "cqhci", "ice"; 454 455 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 457 interrupt-names = "hc_irq", "pwr_irq"; 458 459 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 460 <&gcc GCC_SDCC1_APPS_CLK>, 461 <&xo_board_clk>, 462 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 463 clock-names = "iface", "core", "xo", "ice"; 464 non-removable; 465 supports-cqe; 466 pinctrl-0 = <&sdc_default_state>; 467 pinctrl-names = "default"; 468 mmc-ddr-1_8v; 469 mmc-hs200-1_8v; 470 mmc-hs400-1_8v; 471 mmc-hs400-enhanced-strobe; 472 max-frequency = <384000000>; 473 bus-width = <8>; 474 475 status = "disabled"; 476 }; 477 478 blsp_dma: dma-controller@7884000 { 479 compatible = "qcom,bam-v1.7.0"; 480 reg = <0x07884000 0x2b000>; 481 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 483 clock-names = "bam_clk"; 484 #dma-cells = <1>; 485 qcom,ee = <0>; 486 }; 487 488 blsp1_uart0: serial@78af000 { 489 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 490 reg = <0x078af000 0x200>; 491 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 493 <&gcc GCC_BLSP1_AHB_CLK>; 494 clock-names = "core", "iface"; 495 status = "disabled"; 496 }; 497 498 blsp1_uart1: serial@78b0000 { 499 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 500 reg = <0x078b0000 0x200>; 501 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 503 <&gcc GCC_BLSP1_AHB_CLK>; 504 clock-names = "core", "iface"; 505 status = "disabled"; 506 }; 507 508 blsp1_uart2: serial@78b1000 { 509 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 510 reg = <0x078b1000 0x200>; 511 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 513 <&gcc GCC_BLSP1_AHB_CLK>; 514 clock-names = "core", "iface"; 515 status = "disabled"; 516 }; 517 518 blsp1_uart3: serial@78b2000 { 519 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 520 reg = <0x078b2000 0x200>; 521 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, 523 <&gcc GCC_BLSP1_AHB_CLK>; 524 clock-names = "core", "iface"; 525 status = "disabled"; 526 }; 527 528 blsp1_uart4: serial@78b3000 { 529 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 530 reg = <0x078b3000 0x200>; 531 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 533 <&gcc GCC_BLSP1_AHB_CLK>; 534 clock-names = "core", "iface"; 535 status = "disabled"; 536 }; 537 538 blsp1_uart5: serial@78b4000 { 539 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 540 reg = <0x078b4000 0x200>; 541 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, 543 <&gcc GCC_BLSP1_AHB_CLK>; 544 clock-names = "core", "iface"; 545 status = "disabled"; 546 }; 547 548 blsp1_spi0: spi@78b5000 { 549 compatible = "qcom,spi-qup-v2.2.1"; 550 reg = <0x078b5000 0x600>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 555 <&gcc GCC_BLSP1_AHB_CLK>; 556 clock-names = "core", "iface"; 557 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 558 dma-names = "tx", "rx"; 559 status = "disabled"; 560 }; 561 562 blsp1_i2c1: i2c@78b6000 { 563 compatible = "qcom,i2c-qup-v2.2.1"; 564 reg = <0x078b6000 0x600>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 569 <&gcc GCC_BLSP1_AHB_CLK>; 570 clock-names = "core", "iface"; 571 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 572 assigned-clock-rates = <50000000>; 573 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 574 dma-names = "tx", "rx"; 575 status = "disabled"; 576 }; 577 578 blsp1_spi1: spi@78b6000 { 579 compatible = "qcom,spi-qup-v2.2.1"; 580 reg = <0x078b6000 0x600>; 581 #address-cells = <1>; 582 #size-cells = <0>; 583 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 585 <&gcc GCC_BLSP1_AHB_CLK>; 586 clock-names = "core", "iface"; 587 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 588 dma-names = "tx", "rx"; 589 status = "disabled"; 590 }; 591 592 blsp1_i2c2: i2c@78b7000 { 593 compatible = "qcom,i2c-qup-v2.2.1"; 594 reg = <0x078b7000 0x600>; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 599 <&gcc GCC_BLSP1_AHB_CLK>; 600 clock-names = "core", "iface"; 601 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 602 assigned-clock-rates = <50000000>; 603 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 604 dma-names = "tx", "rx"; 605 status = "disabled"; 606 }; 607 608 blsp1_spi2: spi@78b7000 { 609 compatible = "qcom,spi-qup-v2.2.1"; 610 reg = <0x078b7000 0x600>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 615 <&gcc GCC_BLSP1_AHB_CLK>; 616 clock-names = "core", "iface"; 617 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 618 dma-names = "tx", "rx"; 619 status = "disabled"; 620 }; 621 622 blsp1_i2c3: i2c@78b8000 { 623 compatible = "qcom,i2c-qup-v2.2.1"; 624 reg = <0x078b8000 0x600>; 625 #address-cells = <1>; 626 #size-cells = <0>; 627 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 629 <&gcc GCC_BLSP1_AHB_CLK>; 630 clock-names = "core", "iface"; 631 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 632 assigned-clock-rates = <50000000>; 633 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 634 dma-names = "tx", "rx"; 635 status = "disabled"; 636 }; 637 638 blsp1_spi3: spi@78b8000 { 639 compatible = "qcom,spi-qup-v2.2.1"; 640 reg = <0x078b8000 0x600>; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 644 spi-max-frequency = <50000000>; 645 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 646 <&gcc GCC_BLSP1_AHB_CLK>; 647 clock-names = "core", "iface"; 648 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 649 dma-names = "tx", "rx"; 650 status = "disabled"; 651 }; 652 653 blsp1_i2c4: i2c@78b9000 { 654 compatible = "qcom,i2c-qup-v2.2.1"; 655 reg = <0x078b9000 0x600>; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 660 <&gcc GCC_BLSP1_AHB_CLK>; 661 clock-names = "core", "iface"; 662 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 663 assigned-clock-rates = <50000000>; 664 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 665 dma-names = "tx", "rx"; 666 status = "disabled"; 667 }; 668 669 blsp1_spi4: spi@78b9000 { 670 compatible = "qcom,spi-qup-v2.2.1"; 671 reg = <0x078b9000 0x600>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 676 <&gcc GCC_BLSP1_AHB_CLK>; 677 clock-names = "core", "iface"; 678 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 679 dma-names = "tx", "rx"; 680 status = "disabled"; 681 }; 682 683 qpic_bam: dma-controller@7984000 { 684 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 685 reg = <0x07984000 0x1c000>; 686 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&gcc GCC_QPIC_AHB_CLK>; 688 clock-names = "bam_clk"; 689 #dma-cells = <1>; 690 qcom,ee = <0>; 691 status = "disabled"; 692 }; 693 694 qpic_nand: spi@79b0000 { 695 compatible = "qcom,ipq9574-snand"; 696 reg = <0x079b0000 0x10000>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 clocks = <&gcc GCC_QPIC_CLK>, 700 <&gcc GCC_QPIC_AHB_CLK>, 701 <&gcc GCC_QPIC_IO_MACRO_CLK>; 702 clock-names = "core", "aon", "iom"; 703 dmas = <&qpic_bam 0>, 704 <&qpic_bam 1>, 705 <&qpic_bam 2>; 706 dma-names = "tx", "rx", "cmd"; 707 status = "disabled"; 708 }; 709 710 usb_0_qusbphy: phy@7b000 { 711 compatible = "qcom,ipq9574-qusb2-phy"; 712 reg = <0x0007b000 0x180>; 713 #phy-cells = <0>; 714 715 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 716 <&xo_board_clk>; 717 clock-names = "cfg_ahb", 718 "ref"; 719 720 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 721 status = "disabled"; 722 }; 723 724 usb_0_qmpphy: phy@7d000 { 725 compatible = "qcom,ipq9574-qmp-usb3-phy"; 726 reg = <0x0007d000 0xa00>; 727 #phy-cells = <0>; 728 729 clocks = <&gcc GCC_USB0_AUX_CLK>, 730 <&xo_board_clk>, 731 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 732 <&gcc GCC_USB0_PIPE_CLK>; 733 clock-names = "aux", 734 "ref", 735 "cfg_ahb", 736 "pipe"; 737 738 resets = <&gcc GCC_USB0_PHY_BCR>, 739 <&gcc GCC_USB3PHY_0_PHY_BCR>; 740 reset-names = "phy", 741 "phy_phy"; 742 743 #clock-cells = <0>; 744 clock-output-names = "usb0_pipe_clk"; 745 746 status = "disabled"; 747 }; 748 749 usb3: usb@8af8800 { 750 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; 751 reg = <0x08af8800 0x400>; 752 #address-cells = <1>; 753 #size-cells = <1>; 754 ranges; 755 756 clocks = <&gcc GCC_SNOC_USB_CLK>, 757 <&gcc GCC_USB0_MASTER_CLK>, 758 <&gcc GCC_ANOC_USB_AXI_CLK>, 759 <&gcc GCC_USB0_SLEEP_CLK>, 760 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 761 762 clock-names = "cfg_noc", 763 "core", 764 "iface", 765 "sleep", 766 "mock_utmi"; 767 768 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, 769 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 770 assigned-clock-rates = <200000000>, 771 <24000000>; 772 773 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 774 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 775 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 776 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 777 interrupt-names = "pwr_event", 778 "qusb2_phy", 779 "dm_hs_phy_irq", 780 "dp_hs_phy_irq"; 781 782 resets = <&gcc GCC_USB_BCR>; 783 status = "disabled"; 784 785 usb_0_dwc3: usb@8a00000 { 786 compatible = "snps,dwc3"; 787 reg = <0x8a00000 0xcd00>; 788 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 789 clock-names = "ref"; 790 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 791 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>; 792 phy-names = "usb2-phy", "usb3-phy"; 793 tx-fifo-resize; 794 snps,is-utmi-l1-suspend; 795 snps,hird-threshold = /bits/ 8 <0x0>; 796 snps,dis_u2_susphy_quirk; 797 snps,dis_u3_susphy_quirk; 798 }; 799 }; 800 801 intc: interrupt-controller@b000000 { 802 compatible = "qcom,msm-qgic2"; 803 reg = <0x0b000000 0x1000>, /* GICD */ 804 <0x0b002000 0x2000>, /* GICC */ 805 <0x0b001000 0x1000>, /* GICH */ 806 <0x0b004000 0x2000>; /* GICV */ 807 #address-cells = <1>; 808 #size-cells = <1>; 809 interrupt-controller; 810 #interrupt-cells = <3>; 811 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 812 ranges = <0 0x0b00c000 0x3000>; 813 814 v2m0: v2m@0 { 815 compatible = "arm,gic-v2m-frame"; 816 reg = <0x00000000 0xffd>; 817 msi-controller; 818 }; 819 820 v2m1: v2m@1000 { 821 compatible = "arm,gic-v2m-frame"; 822 reg = <0x00001000 0xffd>; 823 msi-controller; 824 }; 825 826 v2m2: v2m@2000 { 827 compatible = "arm,gic-v2m-frame"; 828 reg = <0x00002000 0xffd>; 829 msi-controller; 830 }; 831 }; 832 833 watchdog: watchdog@b017000 { 834 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt"; 835 reg = <0x0b017000 0x1000>; 836 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 837 clocks = <&sleep_clk>; 838 timeout-sec = <30>; 839 }; 840 841 apcs_glb: mailbox@b111000 { 842 compatible = "qcom,ipq9574-apcs-apps-global", 843 "qcom,ipq6018-apcs-apps-global"; 844 reg = <0x0b111000 0x1000>; 845 #clock-cells = <1>; 846 clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>; 847 clock-names = "pll", "xo", "gpll0"; 848 #mbox-cells = <1>; 849 }; 850 851 a73pll: clock@b116000 { 852 compatible = "qcom,ipq9574-a73pll"; 853 reg = <0x0b116000 0x40>; 854 #clock-cells = <0>; 855 clocks = <&xo_board_clk>; 856 clock-names = "xo"; 857 }; 858 859 timer@b120000 { 860 compatible = "arm,armv7-timer-mem"; 861 reg = <0x0b120000 0x1000>; 862 #address-cells = <1>; 863 #size-cells = <1>; 864 ranges; 865 866 frame@b120000 { 867 reg = <0x0b121000 0x1000>, 868 <0x0b122000 0x1000>; 869 frame-number = <0>; 870 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 872 }; 873 874 frame@b123000 { 875 reg = <0x0b123000 0x1000>; 876 frame-number = <1>; 877 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 878 status = "disabled"; 879 }; 880 881 frame@b124000 { 882 reg = <0x0b124000 0x1000>; 883 frame-number = <2>; 884 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 885 status = "disabled"; 886 }; 887 888 frame@b125000 { 889 reg = <0x0b125000 0x1000>; 890 frame-number = <3>; 891 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 892 status = "disabled"; 893 }; 894 895 frame@b126000 { 896 reg = <0x0b126000 0x1000>; 897 frame-number = <4>; 898 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 899 status = "disabled"; 900 }; 901 902 frame@b127000 { 903 reg = <0x0b127000 0x1000>; 904 frame-number = <5>; 905 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 906 status = "disabled"; 907 }; 908 909 frame@b128000 { 910 reg = <0x0b128000 0x1000>; 911 frame-number = <6>; 912 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 913 status = "disabled"; 914 }; 915 }; 916 917 pcie1: pcie@10000000 { 918 compatible = "qcom,pcie-ipq9574"; 919 reg = <0x10000000 0xf1d>, 920 <0x10000f20 0xa8>, 921 <0x10001000 0x1000>, 922 <0x000f8000 0x4000>, 923 <0x10100000 0x1000>, 924 <0x000fe000 0x1000>; 925 reg-names = "dbi", 926 "elbi", 927 "atu", 928 "parf", 929 "config", 930 "mhi"; 931 device_type = "pci"; 932 linux,pci-domain = <1>; 933 bus-range = <0x00 0xff>; 934 num-lanes = <1>; 935 #address-cells = <3>; 936 #size-cells = <2>; 937 938 ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>, 939 <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>; 940 941 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 949 interrupt-names = "msi0", 950 "msi1", 951 "msi2", 952 "msi3", 953 "msi4", 954 "msi5", 955 "msi6", 956 "msi7"; 957 958 #interrupt-cells = <1>; 959 interrupt-map-mask = <0 0 0 0x7>; 960 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 961 <0 0 0 2 &intc 0 GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 962 <0 0 0 3 &intc 0 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 963 <0 0 0 4 &intc 0 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 964 965 clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, 966 <&gcc GCC_PCIE1_AXI_S_CLK>, 967 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, 968 <&gcc GCC_PCIE1_RCHNG_CLK>, 969 <&gcc GCC_PCIE1_AHB_CLK>, 970 <&gcc GCC_PCIE1_AUX_CLK>; 971 clock-names = "axi_m", 972 "axi_s", 973 "axi_bridge", 974 "rchng", 975 "ahb", 976 "aux"; 977 978 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 979 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 980 <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>, 981 <&gcc GCC_PCIE1_AXI_S_ARES>, 982 <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>, 983 <&gcc GCC_PCIE1_AXI_M_ARES>, 984 <&gcc GCC_PCIE1_AUX_ARES>, 985 <&gcc GCC_PCIE1_AHB_ARES>; 986 reset-names = "pipe", 987 "sticky", 988 "axi_s_sticky", 989 "axi_s", 990 "axi_m_sticky", 991 "axi_m", 992 "aux", 993 "ahb"; 994 995 phys = <&pcie1_phy>; 996 phy-names = "pciephy"; 997 interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, 998 <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; 999 interconnect-names = "pcie-mem", "cpu-pcie"; 1000 status = "disabled"; 1001 }; 1002 1003 pcie3: pcie@18000000 { 1004 compatible = "qcom,pcie-ipq9574"; 1005 reg = <0x18000000 0xf1d>, 1006 <0x18000f20 0xa8>, 1007 <0x18001000 0x1000>, 1008 <0x000f0000 0x4000>, 1009 <0x18100000 0x1000>, 1010 <0x000f6000 0x1000>; 1011 reg-names = "dbi", 1012 "elbi", 1013 "atu", 1014 "parf", 1015 "config", 1016 "mhi"; 1017 device_type = "pci"; 1018 linux,pci-domain = <3>; 1019 bus-range = <0x00 0xff>; 1020 num-lanes = <2>; 1021 #address-cells = <3>; 1022 #size-cells = <2>; 1023 1024 ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>, 1025 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>; 1026 1027 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>; 1035 interrupt-names = "msi0", 1036 "msi1", 1037 "msi2", 1038 "msi3", 1039 "msi4", 1040 "msi5", 1041 "msi6", 1042 "msi7"; 1043 1044 #interrupt-cells = <1>; 1045 interrupt-map-mask = <0 0 0 0x7>; 1046 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1047 <0 0 0 2 &intc 0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1048 <0 0 0 3 &intc 0 GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1049 <0 0 0 4 &intc 0 GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1050 1051 clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, 1052 <&gcc GCC_PCIE3_AXI_S_CLK>, 1053 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, 1054 <&gcc GCC_PCIE3_RCHNG_CLK>, 1055 <&gcc GCC_PCIE3_AHB_CLK>, 1056 <&gcc GCC_PCIE3_AUX_CLK>; 1057 clock-names = "axi_m", 1058 "axi_s", 1059 "axi_bridge", 1060 "rchng", 1061 "ahb", 1062 "aux"; 1063 1064 resets = <&gcc GCC_PCIE3_PIPE_ARES>, 1065 <&gcc GCC_PCIE3_CORE_STICKY_ARES>, 1066 <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>, 1067 <&gcc GCC_PCIE3_AXI_S_ARES>, 1068 <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>, 1069 <&gcc GCC_PCIE3_AXI_M_ARES>, 1070 <&gcc GCC_PCIE3_AUX_ARES>, 1071 <&gcc GCC_PCIE3_AHB_ARES>; 1072 reset-names = "pipe", 1073 "sticky", 1074 "axi_s_sticky", 1075 "axi_s", 1076 "axi_m_sticky", 1077 "axi_m", 1078 "aux", 1079 "ahb"; 1080 1081 phys = <&pcie3_phy>; 1082 phy-names = "pciephy"; 1083 interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, 1084 <&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>; 1085 interconnect-names = "pcie-mem", "cpu-pcie"; 1086 status = "disabled"; 1087 }; 1088 1089 pcie2: pcie@20000000 { 1090 compatible = "qcom,pcie-ipq9574"; 1091 reg = <0x20000000 0xf1d>, 1092 <0x20000f20 0xa8>, 1093 <0x20001000 0x1000>, 1094 <0x00088000 0x4000>, 1095 <0x20100000 0x1000>, 1096 <0x0008e000 0x1000>; 1097 reg-names = "dbi", 1098 "elbi", 1099 "atu", 1100 "parf", 1101 "config", 1102 "mhi"; 1103 device_type = "pci"; 1104 linux,pci-domain = <2>; 1105 bus-range = <0x00 0xff>; 1106 num-lanes = <2>; 1107 #address-cells = <3>; 1108 #size-cells = <2>; 1109 1110 ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>, 1111 <0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>; 1112 1113 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1121 interrupt-names = "msi0", 1122 "msi1", 1123 "msi2", 1124 "msi3", 1125 "msi4", 1126 "msi5", 1127 "msi6", 1128 "msi7"; 1129 1130 #interrupt-cells = <1>; 1131 interrupt-map-mask = <0 0 0 0x7>; 1132 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1133 <0 0 0 2 &intc 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1134 <0 0 0 3 &intc 0 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1135 <0 0 0 4 &intc 0 GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1136 1137 clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, 1138 <&gcc GCC_PCIE2_AXI_S_CLK>, 1139 <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, 1140 <&gcc GCC_PCIE2_RCHNG_CLK>, 1141 <&gcc GCC_PCIE2_AHB_CLK>, 1142 <&gcc GCC_PCIE2_AUX_CLK>; 1143 clock-names = "axi_m", 1144 "axi_s", 1145 "axi_bridge", 1146 "rchng", 1147 "ahb", 1148 "aux"; 1149 1150 resets = <&gcc GCC_PCIE2_PIPE_ARES>, 1151 <&gcc GCC_PCIE2_CORE_STICKY_ARES>, 1152 <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>, 1153 <&gcc GCC_PCIE2_AXI_S_ARES>, 1154 <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>, 1155 <&gcc GCC_PCIE2_AXI_M_ARES>, 1156 <&gcc GCC_PCIE2_AUX_ARES>, 1157 <&gcc GCC_PCIE2_AHB_ARES>; 1158 reset-names = "pipe", 1159 "sticky", 1160 "axi_s_sticky", 1161 "axi_s", 1162 "axi_m_sticky", 1163 "axi_m", 1164 "aux", 1165 "ahb"; 1166 1167 phys = <&pcie2_phy>; 1168 phy-names = "pciephy"; 1169 interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, 1170 <&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>; 1171 interconnect-names = "pcie-mem", "cpu-pcie"; 1172 status = "disabled"; 1173 }; 1174 1175 pcie0: pcie@28000000 { 1176 compatible = "qcom,pcie-ipq9574"; 1177 reg = <0x28000000 0xf1d>, 1178 <0x28000f20 0xa8>, 1179 <0x28001000 0x1000>, 1180 <0x00080000 0x4000>, 1181 <0x28100000 0x1000>, 1182 <0x00086000 0x1000>; 1183 reg-names = "dbi", 1184 "elbi", 1185 "atu", 1186 "parf", 1187 "config", 1188 "mhi"; 1189 device_type = "pci"; 1190 linux,pci-domain = <0>; 1191 bus-range = <0x00 0xff>; 1192 num-lanes = <1>; 1193 #address-cells = <3>; 1194 #size-cells = <2>; 1195 1196 ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>, 1197 <0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>; 1198 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1206 interrupt-names = "msi0", 1207 "msi1", 1208 "msi2", 1209 "msi3", 1210 "msi4", 1211 "msi5", 1212 "msi6", 1213 "msi7"; 1214 1215 #interrupt-cells = <1>; 1216 interrupt-map-mask = <0 0 0 0x7>; 1217 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1218 <0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 1219 <0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 1220 <0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1221 1222 clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, 1223 <&gcc GCC_PCIE0_AXI_S_CLK>, 1224 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 1225 <&gcc GCC_PCIE0_RCHNG_CLK>, 1226 <&gcc GCC_PCIE0_AHB_CLK>, 1227 <&gcc GCC_PCIE0_AUX_CLK>; 1228 clock-names = "axi_m", 1229 "axi_s", 1230 "axi_bridge", 1231 "rchng", 1232 "ahb", 1233 "aux"; 1234 1235 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 1236 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 1237 <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>, 1238 <&gcc GCC_PCIE0_AXI_S_ARES>, 1239 <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>, 1240 <&gcc GCC_PCIE0_AXI_M_ARES>, 1241 <&gcc GCC_PCIE0_AUX_ARES>, 1242 <&gcc GCC_PCIE0_AHB_ARES>; 1243 reset-names = "pipe", 1244 "sticky", 1245 "axi_s_sticky", 1246 "axi_s", 1247 "axi_m_sticky", 1248 "axi_m", 1249 "aux", 1250 "ahb"; 1251 1252 phys = <&pcie0_phy>; 1253 phy-names = "pciephy"; 1254 interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, 1255 <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; 1256 interconnect-names = "pcie-mem", "cpu-pcie"; 1257 status = "disabled"; 1258 }; 1259 1260 nsscc: clock-controller@39b00000 { 1261 compatible = "qcom,ipq9574-nsscc"; 1262 reg = <0x39b00000 0x80000>; 1263 clocks = <&xo_board_clk>, 1264 <&cmn_pll NSS_1200MHZ_CLK>, 1265 <&cmn_pll PPE_353MHZ_CLK>, 1266 <&gcc GPLL0_OUT_AUX>, 1267 <0>, 1268 <0>, 1269 <0>, 1270 <0>, 1271 <0>, 1272 <0>, 1273 <&gcc GCC_NSSCC_CLK>; 1274 clock-names = "xo", 1275 "nss_1200", 1276 "ppe_353", 1277 "gpll0_out", 1278 "uniphy0_rx", 1279 "uniphy0_tx", 1280 "uniphy1_rx", 1281 "uniphy1_tx", 1282 "uniphy2_rx", 1283 "uniphy2_tx", 1284 "bus"; 1285 #clock-cells = <1>; 1286 #reset-cells = <1>; 1287 #interconnect-cells = <1>; 1288 }; 1289 }; 1290 1291 thermal-zones { 1292 nss-top-thermal { 1293 thermal-sensors = <&tsens 3>; 1294 1295 trips { 1296 nss-top-critical { 1297 temperature = <125000>; 1298 hysteresis = <1000>; 1299 type = "critical"; 1300 }; 1301 }; 1302 }; 1303 1304 ubi-0-thermal { 1305 thermal-sensors = <&tsens 4>; 1306 1307 trips { 1308 ubi_0-critical { 1309 temperature = <125000>; 1310 hysteresis = <1000>; 1311 type = "critical"; 1312 }; 1313 }; 1314 }; 1315 1316 ubi-1-thermal { 1317 thermal-sensors = <&tsens 5>; 1318 1319 trips { 1320 ubi_1-critical { 1321 temperature = <125000>; 1322 hysteresis = <1000>; 1323 type = "critical"; 1324 }; 1325 }; 1326 }; 1327 1328 ubi-2-thermal { 1329 thermal-sensors = <&tsens 6>; 1330 1331 trips { 1332 ubi_2-critical { 1333 temperature = <125000>; 1334 hysteresis = <1000>; 1335 type = "critical"; 1336 }; 1337 }; 1338 }; 1339 1340 ubi-3-thermal { 1341 thermal-sensors = <&tsens 7>; 1342 1343 trips { 1344 ubi_3-critical { 1345 temperature = <125000>; 1346 hysteresis = <1000>; 1347 type = "critical"; 1348 }; 1349 }; 1350 }; 1351 1352 cpuss0-thermal { 1353 thermal-sensors = <&tsens 8>; 1354 1355 trips { 1356 cpu-critical { 1357 temperature = <125000>; 1358 hysteresis = <1000>; 1359 type = "critical"; 1360 }; 1361 }; 1362 }; 1363 1364 cpuss1-thermal { 1365 thermal-sensors = <&tsens 9>; 1366 1367 trips { 1368 cpu-critical { 1369 temperature = <125000>; 1370 hysteresis = <1000>; 1371 type = "critical"; 1372 }; 1373 }; 1374 }; 1375 1376 cpu0-thermal { 1377 thermal-sensors = <&tsens 10>; 1378 1379 trips { 1380 cpu0_crit: cpu-critical { 1381 temperature = <120000>; 1382 hysteresis = <10000>; 1383 type = "critical"; 1384 }; 1385 1386 cpu0_alert: cpu-passive { 1387 temperature = <110000>; 1388 hysteresis = <1000>; 1389 type = "passive"; 1390 }; 1391 }; 1392 1393 cooling-maps { 1394 map0 { 1395 trip = <&cpu0_alert>; 1396 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1397 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1398 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1399 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1400 }; 1401 }; 1402 }; 1403 1404 cpu1-thermal { 1405 thermal-sensors = <&tsens 11>; 1406 1407 trips { 1408 cpu1_crit: cpu-critical { 1409 temperature = <120000>; 1410 hysteresis = <10000>; 1411 type = "critical"; 1412 }; 1413 1414 cpu1_alert: cpu-passive { 1415 temperature = <110000>; 1416 hysteresis = <1000>; 1417 type = "passive"; 1418 }; 1419 }; 1420 1421 cooling-maps { 1422 map0 { 1423 trip = <&cpu1_alert>; 1424 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1425 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1426 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1427 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1428 }; 1429 }; 1430 }; 1431 1432 cpu2-thermal { 1433 thermal-sensors = <&tsens 12>; 1434 1435 trips { 1436 cpu2_crit: cpu-critical { 1437 temperature = <120000>; 1438 hysteresis = <10000>; 1439 type = "critical"; 1440 }; 1441 1442 cpu2_alert: cpu-passive { 1443 temperature = <110000>; 1444 hysteresis = <1000>; 1445 type = "passive"; 1446 }; 1447 }; 1448 1449 cooling-maps { 1450 map0 { 1451 trip = <&cpu2_alert>; 1452 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1453 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1454 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1455 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1456 }; 1457 }; 1458 }; 1459 1460 cpu3-thermal { 1461 thermal-sensors = <&tsens 13>; 1462 1463 trips { 1464 cpu3_crit: cpu-critical { 1465 temperature = <120000>; 1466 hysteresis = <10000>; 1467 type = "critical"; 1468 }; 1469 1470 cpu3_alert: cpu-passive { 1471 temperature = <110000>; 1472 hysteresis = <1000>; 1473 type = "passive"; 1474 }; 1475 }; 1476 1477 cooling-maps { 1478 map0 { 1479 trip = <&cpu3_alert>; 1480 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1481 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1482 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1483 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1484 }; 1485 }; 1486 }; 1487 1488 wcss-phyb-thermal { 1489 thermal-sensors = <&tsens 14>; 1490 1491 trips { 1492 wcss_phyb-critical { 1493 temperature = <125000>; 1494 hysteresis = <1000>; 1495 type = "critical"; 1496 }; 1497 }; 1498 }; 1499 1500 top-glue-thermal { 1501 thermal-sensors = <&tsens 15>; 1502 1503 trips { 1504 top_glue-critical { 1505 temperature = <125000>; 1506 hysteresis = <1000>; 1507 type = "critical"; 1508 }; 1509 }; 1510 }; 1511 }; 1512 1513 timer { 1514 compatible = "arm,armv8-timer"; 1515 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1516 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1517 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1518 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1519 }; 1520}; 1521