1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ9574 SoC device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,apss-ipq.h> 10#include <dt-bindings/clock/qcom,ipq-cmn-pll.h> 11#include <dt-bindings/clock/qcom,ipq9574-gcc.h> 12#include <dt-bindings/interconnect/qcom,ipq9574.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/reset/qcom,ipq9574-gcc.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 clocks { 23 ref_48mhz_clk: ref-48mhz-clk { 24 compatible = "fixed-factor-clock"; 25 clocks = <&xo_clk>; 26 #clock-cells = <0>; 27 }; 28 29 sleep_clk: sleep-clk { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 }; 33 34 xo_board_clk: xo-board-clk { 35 compatible = "fixed-factor-clock"; 36 clocks = <&ref_48mhz_clk>; 37 #clock-cells = <0>; 38 }; 39 40 xo_clk: xo-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a73"; 53 reg = <0x0>; 54 enable-method = "psci"; 55 next-level-cache = <&l2_0>; 56 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 57 clock-names = "cpu"; 58 operating-points-v2 = <&cpu_opp_table>; 59 cpu-supply = <&ipq9574_s1>; 60 #cooling-cells = <2>; 61 }; 62 63 cpu1: cpu@1 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a73"; 66 reg = <0x1>; 67 enable-method = "psci"; 68 next-level-cache = <&l2_0>; 69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 70 clock-names = "cpu"; 71 operating-points-v2 = <&cpu_opp_table>; 72 cpu-supply = <&ipq9574_s1>; 73 #cooling-cells = <2>; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a73"; 79 reg = <0x2>; 80 enable-method = "psci"; 81 next-level-cache = <&l2_0>; 82 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 83 clock-names = "cpu"; 84 operating-points-v2 = <&cpu_opp_table>; 85 cpu-supply = <&ipq9574_s1>; 86 #cooling-cells = <2>; 87 }; 88 89 cpu3: cpu@3 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a73"; 92 reg = <0x3>; 93 enable-method = "psci"; 94 next-level-cache = <&l2_0>; 95 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 96 clock-names = "cpu"; 97 operating-points-v2 = <&cpu_opp_table>; 98 cpu-supply = <&ipq9574_s1>; 99 #cooling-cells = <2>; 100 }; 101 102 l2_0: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 cache-unified; 106 }; 107 }; 108 109 firmware { 110 scm { 111 compatible = "qcom,scm-ipq9574", "qcom,scm"; 112 qcom,dload-mode = <&tcsr 0x6100>; 113 }; 114 }; 115 116 memory@40000000 { 117 device_type = "memory"; 118 /* We expect the bootloader to fill in the size */ 119 reg = <0x0 0x40000000 0x0 0x0>; 120 }; 121 122 cpu_opp_table: opp-table-cpu { 123 compatible = "operating-points-v2-kryo-cpu"; 124 opp-shared; 125 nvmem-cells = <&cpu_speed_bin>; 126 127 opp-936000000 { 128 opp-hz = /bits/ 64 <936000000>; 129 opp-microvolt = <725000>; 130 opp-supported-hw = <0xf>; 131 clock-latency-ns = <200000>; 132 }; 133 134 opp-1104000000 { 135 opp-hz = /bits/ 64 <1104000000>; 136 opp-microvolt = <787500>; 137 opp-supported-hw = <0xf>; 138 clock-latency-ns = <200000>; 139 }; 140 141 opp-1200000000 { 142 opp-hz = /bits/ 64 <1200000000>; 143 opp-microvolt = <862500>; 144 opp-supported-hw = <0xf>; 145 clock-latency-ns = <200000>; 146 }; 147 148 opp-1416000000 { 149 opp-hz = /bits/ 64 <1416000000>; 150 opp-microvolt = <862500>; 151 opp-supported-hw = <0x7>; 152 clock-latency-ns = <200000>; 153 }; 154 155 opp-1488000000 { 156 opp-hz = /bits/ 64 <1488000000>; 157 opp-microvolt = <925000>; 158 opp-supported-hw = <0x7>; 159 clock-latency-ns = <200000>; 160 }; 161 162 opp-1800000000 { 163 opp-hz = /bits/ 64 <1800000000>; 164 opp-microvolt = <987500>; 165 opp-supported-hw = <0x5>; 166 clock-latency-ns = <200000>; 167 }; 168 169 opp-2208000000 { 170 opp-hz = /bits/ 64 <2208000000>; 171 opp-microvolt = <1062500>; 172 opp-supported-hw = <0x1>; 173 clock-latency-ns = <200000>; 174 }; 175 }; 176 177 pmu { 178 compatible = "arm,cortex-a73-pmu"; 179 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 180 }; 181 182 psci { 183 compatible = "arm,psci-1.0"; 184 method = "smc"; 185 }; 186 187 rpm: remoteproc { 188 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc"; 189 190 glink-edge { 191 compatible = "qcom,glink-rpm"; 192 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 193 qcom,rpm-msg-ram = <&rpm_msg_ram>; 194 mboxes = <&apcs_glb 0>; 195 196 rpm_requests: rpm-requests { 197 compatible = "qcom,rpm-ipq9574", "qcom,glink-smd-rpm"; 198 qcom,glink-channels = "rpm_requests"; 199 }; 200 }; 201 }; 202 203 reserved-memory { 204 #address-cells = <2>; 205 #size-cells = <2>; 206 ranges; 207 208 bootloader@4a100000 { 209 reg = <0x0 0x4a100000 0x0 0x400000>; 210 no-map; 211 }; 212 213 sbl@4a500000 { 214 reg = <0x0 0x4a500000 0x0 0x100000>; 215 no-map; 216 }; 217 218 tz_region: tz@4a600000 { 219 reg = <0x0 0x4a600000 0x0 0x400000>; 220 no-map; 221 }; 222 223 smem@4aa00000 { 224 compatible = "qcom,smem"; 225 reg = <0x0 0x4aa00000 0x0 0x100000>; 226 hwlocks = <&tcsr_mutex 3>; 227 no-map; 228 }; 229 }; 230 231 soc: soc@0 { 232 compatible = "simple-bus"; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 ranges = <0 0 0 0xffffffff>; 236 237 rpm_msg_ram: sram@60000 { 238 compatible = "qcom,rpm-msg-ram"; 239 reg = <0x00060000 0x6000>; 240 }; 241 242 pcie0_phy: phy@84000 { 243 compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; 244 reg = <0x00084000 0x1000>; 245 246 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 247 <&gcc GCC_PCIE0_AHB_CLK>, 248 <&gcc GCC_PCIE0_PIPE_CLK>; 249 clock-names = "aux", "cfg_ahb", "pipe"; 250 251 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; 252 assigned-clock-rates = <20000000>; 253 254 resets = <&gcc GCC_PCIE0_PHY_BCR>, 255 <&gcc GCC_PCIE0PHY_PHY_BCR>; 256 reset-names = "phy", "common"; 257 258 #clock-cells = <0>; 259 clock-output-names = "gcc_pcie0_pipe_clk_src"; 260 261 #phy-cells = <0>; 262 status = "disabled"; 263 }; 264 265 pcie2_phy: phy@8c000 { 266 compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; 267 reg = <0x0008c000 0x2000>; 268 269 clocks = <&gcc GCC_PCIE2_AUX_CLK>, 270 <&gcc GCC_PCIE2_AHB_CLK>, 271 <&gcc GCC_PCIE2_PIPE_CLK>; 272 clock-names = "aux", "cfg_ahb", "pipe"; 273 274 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; 275 assigned-clock-rates = <20000000>; 276 277 resets = <&gcc GCC_PCIE2_PHY_BCR>, 278 <&gcc GCC_PCIE2PHY_PHY_BCR>; 279 reset-names = "phy", "common"; 280 281 #clock-cells = <0>; 282 clock-output-names = "gcc_pcie2_pipe_clk_src"; 283 284 #phy-cells = <0>; 285 status = "disabled"; 286 }; 287 288 rng: rng@e3000 { 289 compatible = "qcom,ipq9574-trng", "qcom,trng"; 290 reg = <0x000e3000 0x1000>; 291 clocks = <&gcc GCC_PRNG_AHB_CLK>; 292 clock-names = "core"; 293 }; 294 295 mdio: mdio@90000 { 296 compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio"; 297 reg = <0x00090000 0x64>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 clocks = <&gcc GCC_MDIO_AHB_CLK>; 301 clock-names = "gcc_mdio_ahb_clk"; 302 status = "disabled"; 303 }; 304 305 pcie3_phy: phy@f4000 { 306 compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; 307 reg = <0x000f4000 0x2000>; 308 309 clocks = <&gcc GCC_PCIE3_AUX_CLK>, 310 <&gcc GCC_PCIE3_AHB_CLK>, 311 <&gcc GCC_PCIE3_PIPE_CLK>; 312 clock-names = "aux", "cfg_ahb", "pipe"; 313 314 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; 315 assigned-clock-rates = <20000000>; 316 317 resets = <&gcc GCC_PCIE3_PHY_BCR>, 318 <&gcc GCC_PCIE3PHY_PHY_BCR>; 319 reset-names = "phy", "common"; 320 321 #clock-cells = <0>; 322 clock-output-names = "gcc_pcie3_pipe_clk_src"; 323 324 #phy-cells = <0>; 325 status = "disabled"; 326 }; 327 328 pcie1_phy: phy@fc000 { 329 compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy"; 330 reg = <0x000fc000 0x1000>; 331 332 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 333 <&gcc GCC_PCIE1_AHB_CLK>, 334 <&gcc GCC_PCIE1_PIPE_CLK>; 335 clock-names = "aux", "cfg_ahb", "pipe"; 336 337 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; 338 assigned-clock-rates = <20000000>; 339 340 resets = <&gcc GCC_PCIE1_PHY_BCR>, 341 <&gcc GCC_PCIE1PHY_PHY_BCR>; 342 reset-names = "phy", "common"; 343 344 #clock-cells = <0>; 345 clock-output-names = "gcc_pcie1_pipe_clk_src"; 346 347 #phy-cells = <0>; 348 status = "disabled"; 349 }; 350 351 cmn_pll: clock-controller@9b000 { 352 compatible = "qcom,ipq9574-cmn-pll"; 353 reg = <0x0009b000 0x800>; 354 clocks = <&ref_48mhz_clk>, 355 <&gcc GCC_CMN_12GPLL_AHB_CLK>, 356 <&gcc GCC_CMN_12GPLL_SYS_CLK>; 357 clock-names = "ref", "ahb", "sys"; 358 #clock-cells = <1>; 359 assigned-clocks = <&cmn_pll CMN_PLL_CLK>; 360 assigned-clock-rates-u64 = /bits/ 64 <12000000000>; 361 }; 362 363 qfprom: efuse@a4000 { 364 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; 365 reg = <0x000a4000 0x5a1>; 366 #address-cells = <1>; 367 #size-cells = <1>; 368 369 cpu_speed_bin: cpu-speed-bin@15 { 370 reg = <0x15 0x2>; 371 bits = <7 2>; 372 }; 373 }; 374 375 cryptobam: dma-controller@704000 { 376 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 377 reg = <0x00704000 0x20000>; 378 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 379 #dma-cells = <1>; 380 qcom,ee = <1>; 381 qcom,num-ees = <4>; 382 num-channels = <16>; 383 qcom,controlled-remotely; 384 }; 385 386 crypto: crypto@73a000 { 387 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce"; 388 reg = <0x0073a000 0x6000>; 389 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 390 <&gcc GCC_CRYPTO_AXI_CLK>, 391 <&gcc GCC_CRYPTO_CLK>; 392 clock-names = "iface", "bus", "core"; 393 dmas = <&cryptobam 2>, <&cryptobam 3>; 394 dma-names = "rx", "tx"; 395 }; 396 397 tsens: thermal-sensor@4a9000 { 398 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens"; 399 reg = <0x004a9000 0x1000>, 400 <0x004a8000 0x1000>; 401 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 402 interrupt-names = "combined"; 403 #qcom,sensors = <16>; 404 #thermal-sensor-cells = <1>; 405 }; 406 407 tlmm: pinctrl@1000000 { 408 compatible = "qcom,ipq9574-tlmm"; 409 reg = <0x01000000 0x300000>; 410 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 411 gpio-controller; 412 #gpio-cells = <2>; 413 gpio-ranges = <&tlmm 0 0 65>; 414 interrupt-controller; 415 #interrupt-cells = <2>; 416 417 uart2_pins: uart2-state { 418 pins = "gpio34", "gpio35"; 419 function = "blsp2_uart"; 420 drive-strength = <8>; 421 bias-disable; 422 }; 423 }; 424 425 gcc: clock-controller@1800000 { 426 compatible = "qcom,ipq9574-gcc"; 427 reg = <0x01800000 0x80000>; 428 clocks = <&xo_board_clk>, 429 <&sleep_clk>, 430 <0>, 431 <&pcie0_phy>, 432 <&pcie1_phy>, 433 <&pcie2_phy>, 434 <&pcie3_phy>, 435 <0>; 436 #clock-cells = <1>; 437 #reset-cells = <1>; 438 #interconnect-cells = <1>; 439 }; 440 441 tcsr_mutex: hwlock@1905000 { 442 compatible = "qcom,tcsr-mutex"; 443 reg = <0x01905000 0x20000>; 444 #hwlock-cells = <1>; 445 }; 446 447 tcsr: syscon@1937000 { 448 compatible = "qcom,tcsr-ipq9574", "syscon"; 449 reg = <0x01937000 0x21000>; 450 }; 451 452 sdhc_1: mmc@7804000 { 453 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; 454 reg = <0x07804000 0x1000>, 455 <0x07805000 0x1000>, 456 <0x07808000 0x2000>; 457 reg-names = "hc", "cqhci", "ice"; 458 459 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 461 interrupt-names = "hc_irq", "pwr_irq"; 462 463 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 464 <&gcc GCC_SDCC1_APPS_CLK>, 465 <&xo_board_clk>, 466 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 467 clock-names = "iface", "core", "xo", "ice"; 468 non-removable; 469 supports-cqe; 470 status = "disabled"; 471 }; 472 473 blsp_dma: dma-controller@7884000 { 474 compatible = "qcom,bam-v1.7.0"; 475 reg = <0x07884000 0x2b000>; 476 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 478 clock-names = "bam_clk"; 479 #dma-cells = <1>; 480 qcom,ee = <0>; 481 }; 482 483 blsp1_uart0: serial@78af000 { 484 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 485 reg = <0x078af000 0x200>; 486 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 488 <&gcc GCC_BLSP1_AHB_CLK>; 489 clock-names = "core", "iface"; 490 status = "disabled"; 491 }; 492 493 blsp1_uart1: serial@78b0000 { 494 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 495 reg = <0x078b0000 0x200>; 496 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 498 <&gcc GCC_BLSP1_AHB_CLK>; 499 clock-names = "core", "iface"; 500 status = "disabled"; 501 }; 502 503 blsp1_uart2: serial@78b1000 { 504 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 505 reg = <0x078b1000 0x200>; 506 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 508 <&gcc GCC_BLSP1_AHB_CLK>; 509 clock-names = "core", "iface"; 510 status = "disabled"; 511 }; 512 513 blsp1_uart3: serial@78b2000 { 514 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 515 reg = <0x078b2000 0x200>; 516 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, 518 <&gcc GCC_BLSP1_AHB_CLK>; 519 clock-names = "core", "iface"; 520 status = "disabled"; 521 }; 522 523 blsp1_uart4: serial@78b3000 { 524 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 525 reg = <0x078b3000 0x200>; 526 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 528 <&gcc GCC_BLSP1_AHB_CLK>; 529 clock-names = "core", "iface"; 530 status = "disabled"; 531 }; 532 533 blsp1_uart5: serial@78b4000 { 534 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 535 reg = <0x078b4000 0x200>; 536 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, 538 <&gcc GCC_BLSP1_AHB_CLK>; 539 clock-names = "core", "iface"; 540 status = "disabled"; 541 }; 542 543 blsp1_spi0: spi@78b5000 { 544 compatible = "qcom,spi-qup-v2.2.1"; 545 reg = <0x078b5000 0x600>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 550 <&gcc GCC_BLSP1_AHB_CLK>; 551 clock-names = "core", "iface"; 552 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 553 dma-names = "tx", "rx"; 554 status = "disabled"; 555 }; 556 557 blsp1_i2c1: i2c@78b6000 { 558 compatible = "qcom,i2c-qup-v2.2.1"; 559 reg = <0x078b6000 0x600>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 564 <&gcc GCC_BLSP1_AHB_CLK>; 565 clock-names = "core", "iface"; 566 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 567 assigned-clock-rates = <50000000>; 568 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 569 dma-names = "tx", "rx"; 570 status = "disabled"; 571 }; 572 573 blsp1_spi1: spi@78b6000 { 574 compatible = "qcom,spi-qup-v2.2.1"; 575 reg = <0x078b6000 0x600>; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 580 <&gcc GCC_BLSP1_AHB_CLK>; 581 clock-names = "core", "iface"; 582 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 583 dma-names = "tx", "rx"; 584 status = "disabled"; 585 }; 586 587 blsp1_i2c2: i2c@78b7000 { 588 compatible = "qcom,i2c-qup-v2.2.1"; 589 reg = <0x078b7000 0x600>; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 594 <&gcc GCC_BLSP1_AHB_CLK>; 595 clock-names = "core", "iface"; 596 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 597 assigned-clock-rates = <50000000>; 598 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 599 dma-names = "tx", "rx"; 600 status = "disabled"; 601 }; 602 603 blsp1_spi2: spi@78b7000 { 604 compatible = "qcom,spi-qup-v2.2.1"; 605 reg = <0x078b7000 0x600>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 610 <&gcc GCC_BLSP1_AHB_CLK>; 611 clock-names = "core", "iface"; 612 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 613 dma-names = "tx", "rx"; 614 status = "disabled"; 615 }; 616 617 blsp1_i2c3: i2c@78b8000 { 618 compatible = "qcom,i2c-qup-v2.2.1"; 619 reg = <0x078b8000 0x600>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 624 <&gcc GCC_BLSP1_AHB_CLK>; 625 clock-names = "core", "iface"; 626 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 627 assigned-clock-rates = <50000000>; 628 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 629 dma-names = "tx", "rx"; 630 status = "disabled"; 631 }; 632 633 blsp1_spi3: spi@78b8000 { 634 compatible = "qcom,spi-qup-v2.2.1"; 635 reg = <0x078b8000 0x600>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 639 spi-max-frequency = <50000000>; 640 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 641 <&gcc GCC_BLSP1_AHB_CLK>; 642 clock-names = "core", "iface"; 643 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 644 dma-names = "tx", "rx"; 645 status = "disabled"; 646 }; 647 648 blsp1_i2c4: i2c@78b9000 { 649 compatible = "qcom,i2c-qup-v2.2.1"; 650 reg = <0x078b9000 0x600>; 651 #address-cells = <1>; 652 #size-cells = <0>; 653 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 655 <&gcc GCC_BLSP1_AHB_CLK>; 656 clock-names = "core", "iface"; 657 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 658 assigned-clock-rates = <50000000>; 659 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 660 dma-names = "tx", "rx"; 661 status = "disabled"; 662 }; 663 664 blsp1_spi4: spi@78b9000 { 665 compatible = "qcom,spi-qup-v2.2.1"; 666 reg = <0x078b9000 0x600>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 671 <&gcc GCC_BLSP1_AHB_CLK>; 672 clock-names = "core", "iface"; 673 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 674 dma-names = "tx", "rx"; 675 status = "disabled"; 676 }; 677 678 qpic_bam: dma-controller@7984000 { 679 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 680 reg = <0x07984000 0x1c000>; 681 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&gcc GCC_QPIC_AHB_CLK>; 683 clock-names = "bam_clk"; 684 #dma-cells = <1>; 685 qcom,ee = <0>; 686 status = "disabled"; 687 }; 688 689 qpic_nand: spi@79b0000 { 690 compatible = "qcom,ipq9574-snand"; 691 reg = <0x079b0000 0x10000>; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 clocks = <&gcc GCC_QPIC_CLK>, 695 <&gcc GCC_QPIC_AHB_CLK>, 696 <&gcc GCC_QPIC_IO_MACRO_CLK>; 697 clock-names = "core", "aon", "iom"; 698 dmas = <&qpic_bam 0>, 699 <&qpic_bam 1>, 700 <&qpic_bam 2>; 701 dma-names = "tx", "rx", "cmd"; 702 status = "disabled"; 703 }; 704 705 usb_0_qusbphy: phy@7b000 { 706 compatible = "qcom,ipq9574-qusb2-phy"; 707 reg = <0x0007b000 0x180>; 708 #phy-cells = <0>; 709 710 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 711 <&xo_board_clk>; 712 clock-names = "cfg_ahb", 713 "ref"; 714 715 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 716 status = "disabled"; 717 }; 718 719 usb_0_qmpphy: phy@7d000 { 720 compatible = "qcom,ipq9574-qmp-usb3-phy"; 721 reg = <0x0007d000 0xa00>; 722 #phy-cells = <0>; 723 724 clocks = <&gcc GCC_USB0_AUX_CLK>, 725 <&xo_board_clk>, 726 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 727 <&gcc GCC_USB0_PIPE_CLK>; 728 clock-names = "aux", 729 "ref", 730 "cfg_ahb", 731 "pipe"; 732 733 resets = <&gcc GCC_USB0_PHY_BCR>, 734 <&gcc GCC_USB3PHY_0_PHY_BCR>; 735 reset-names = "phy", 736 "phy_phy"; 737 738 #clock-cells = <0>; 739 clock-output-names = "usb0_pipe_clk"; 740 741 status = "disabled"; 742 }; 743 744 usb3: usb@8af8800 { 745 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; 746 reg = <0x08af8800 0x400>; 747 #address-cells = <1>; 748 #size-cells = <1>; 749 ranges; 750 751 clocks = <&gcc GCC_SNOC_USB_CLK>, 752 <&gcc GCC_USB0_MASTER_CLK>, 753 <&gcc GCC_ANOC_USB_AXI_CLK>, 754 <&gcc GCC_USB0_SLEEP_CLK>, 755 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 756 757 clock-names = "cfg_noc", 758 "core", 759 "iface", 760 "sleep", 761 "mock_utmi"; 762 763 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, 764 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 765 assigned-clock-rates = <200000000>, 766 <24000000>; 767 768 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 769 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 770 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 771 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 772 interrupt-names = "pwr_event", 773 "qusb2_phy", 774 "dm_hs_phy_irq", 775 "dp_hs_phy_irq"; 776 777 resets = <&gcc GCC_USB_BCR>; 778 status = "disabled"; 779 780 usb_0_dwc3: usb@8a00000 { 781 compatible = "snps,dwc3"; 782 reg = <0x8a00000 0xcd00>; 783 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 784 clock-names = "ref"; 785 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 786 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>; 787 phy-names = "usb2-phy", "usb3-phy"; 788 tx-fifo-resize; 789 snps,is-utmi-l1-suspend; 790 snps,hird-threshold = /bits/ 8 <0x0>; 791 snps,dis_u2_susphy_quirk; 792 snps,dis_u3_susphy_quirk; 793 }; 794 }; 795 796 intc: interrupt-controller@b000000 { 797 compatible = "qcom,msm-qgic2"; 798 reg = <0x0b000000 0x1000>, /* GICD */ 799 <0x0b002000 0x2000>, /* GICC */ 800 <0x0b001000 0x1000>, /* GICH */ 801 <0x0b004000 0x2000>; /* GICV */ 802 #address-cells = <1>; 803 #size-cells = <1>; 804 interrupt-controller; 805 #interrupt-cells = <3>; 806 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 807 ranges = <0 0x0b00c000 0x3000>; 808 809 v2m0: v2m@0 { 810 compatible = "arm,gic-v2m-frame"; 811 reg = <0x00000000 0xffd>; 812 msi-controller; 813 }; 814 815 v2m1: v2m@1000 { 816 compatible = "arm,gic-v2m-frame"; 817 reg = <0x00001000 0xffd>; 818 msi-controller; 819 }; 820 821 v2m2: v2m@2000 { 822 compatible = "arm,gic-v2m-frame"; 823 reg = <0x00002000 0xffd>; 824 msi-controller; 825 }; 826 }; 827 828 watchdog: watchdog@b017000 { 829 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt"; 830 reg = <0x0b017000 0x1000>; 831 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 832 clocks = <&sleep_clk>; 833 timeout-sec = <30>; 834 }; 835 836 apcs_glb: mailbox@b111000 { 837 compatible = "qcom,ipq9574-apcs-apps-global", 838 "qcom,ipq6018-apcs-apps-global"; 839 reg = <0x0b111000 0x1000>; 840 #clock-cells = <1>; 841 clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>; 842 clock-names = "pll", "xo", "gpll0"; 843 #mbox-cells = <1>; 844 }; 845 846 a73pll: clock@b116000 { 847 compatible = "qcom,ipq9574-a73pll"; 848 reg = <0x0b116000 0x40>; 849 #clock-cells = <0>; 850 clocks = <&xo_board_clk>; 851 clock-names = "xo"; 852 }; 853 854 timer@b120000 { 855 compatible = "arm,armv7-timer-mem"; 856 reg = <0x0b120000 0x1000>; 857 #address-cells = <1>; 858 #size-cells = <1>; 859 ranges; 860 861 frame@b120000 { 862 reg = <0x0b121000 0x1000>, 863 <0x0b122000 0x1000>; 864 frame-number = <0>; 865 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 867 }; 868 869 frame@b123000 { 870 reg = <0x0b123000 0x1000>; 871 frame-number = <1>; 872 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 873 status = "disabled"; 874 }; 875 876 frame@b124000 { 877 reg = <0x0b124000 0x1000>; 878 frame-number = <2>; 879 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 880 status = "disabled"; 881 }; 882 883 frame@b125000 { 884 reg = <0x0b125000 0x1000>; 885 frame-number = <3>; 886 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 887 status = "disabled"; 888 }; 889 890 frame@b126000 { 891 reg = <0x0b126000 0x1000>; 892 frame-number = <4>; 893 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 894 status = "disabled"; 895 }; 896 897 frame@b127000 { 898 reg = <0x0b127000 0x1000>; 899 frame-number = <5>; 900 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 901 status = "disabled"; 902 }; 903 904 frame@b128000 { 905 reg = <0x0b128000 0x1000>; 906 frame-number = <6>; 907 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 908 status = "disabled"; 909 }; 910 }; 911 912 pcie1: pcie@10000000 { 913 compatible = "qcom,pcie-ipq9574"; 914 reg = <0x10000000 0xf1d>, 915 <0x10000f20 0xa8>, 916 <0x10001000 0x1000>, 917 <0x000f8000 0x4000>, 918 <0x10100000 0x1000>, 919 <0x000fe000 0x1000>; 920 reg-names = "dbi", 921 "elbi", 922 "atu", 923 "parf", 924 "config", 925 "mhi"; 926 device_type = "pci"; 927 linux,pci-domain = <1>; 928 bus-range = <0x00 0xff>; 929 num-lanes = <1>; 930 #address-cells = <3>; 931 #size-cells = <2>; 932 933 ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>, 934 <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>; 935 936 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 944 interrupt-names = "msi0", 945 "msi1", 946 "msi2", 947 "msi3", 948 "msi4", 949 "msi5", 950 "msi6", 951 "msi7"; 952 953 #interrupt-cells = <1>; 954 interrupt-map-mask = <0 0 0 0x7>; 955 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 956 <0 0 0 2 &intc 0 GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 957 <0 0 0 3 &intc 0 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 958 <0 0 0 4 &intc 0 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 959 960 clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, 961 <&gcc GCC_PCIE1_AXI_S_CLK>, 962 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, 963 <&gcc GCC_PCIE1_RCHNG_CLK>, 964 <&gcc GCC_PCIE1_AHB_CLK>, 965 <&gcc GCC_PCIE1_AUX_CLK>; 966 clock-names = "axi_m", 967 "axi_s", 968 "axi_bridge", 969 "rchng", 970 "ahb", 971 "aux"; 972 973 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 974 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 975 <&gcc GCC_PCIE1_AXI_S_STICKY_ARES>, 976 <&gcc GCC_PCIE1_AXI_S_ARES>, 977 <&gcc GCC_PCIE1_AXI_M_STICKY_ARES>, 978 <&gcc GCC_PCIE1_AXI_M_ARES>, 979 <&gcc GCC_PCIE1_AUX_ARES>, 980 <&gcc GCC_PCIE1_AHB_ARES>; 981 reset-names = "pipe", 982 "sticky", 983 "axi_s_sticky", 984 "axi_s", 985 "axi_m_sticky", 986 "axi_m", 987 "aux", 988 "ahb"; 989 990 phys = <&pcie1_phy>; 991 phy-names = "pciephy"; 992 interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, 993 <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; 994 interconnect-names = "pcie-mem", "cpu-pcie"; 995 status = "disabled"; 996 }; 997 998 pcie3: pcie@18000000 { 999 compatible = "qcom,pcie-ipq9574"; 1000 reg = <0x18000000 0xf1d>, 1001 <0x18000f20 0xa8>, 1002 <0x18001000 0x1000>, 1003 <0x000f0000 0x4000>, 1004 <0x18100000 0x1000>, 1005 <0x000f6000 0x1000>; 1006 reg-names = "dbi", 1007 "elbi", 1008 "atu", 1009 "parf", 1010 "config", 1011 "mhi"; 1012 device_type = "pci"; 1013 linux,pci-domain = <3>; 1014 bus-range = <0x00 0xff>; 1015 num-lanes = <2>; 1016 #address-cells = <3>; 1017 #size-cells = <2>; 1018 1019 ranges = <0x01000000 0x0 0x00000000 0x18200000 0x0 0x100000>, 1020 <0x02000000 0x0 0x18300000 0x18300000 0x0 0x7d00000>; 1021 1022 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>; 1030 interrupt-names = "msi0", 1031 "msi1", 1032 "msi2", 1033 "msi3", 1034 "msi4", 1035 "msi5", 1036 "msi6", 1037 "msi7"; 1038 1039 #interrupt-cells = <1>; 1040 interrupt-map-mask = <0 0 0 0x7>; 1041 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1042 <0 0 0 2 &intc 0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1043 <0 0 0 3 &intc 0 GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1044 <0 0 0 4 &intc 0 GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1045 1046 clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, 1047 <&gcc GCC_PCIE3_AXI_S_CLK>, 1048 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, 1049 <&gcc GCC_PCIE3_RCHNG_CLK>, 1050 <&gcc GCC_PCIE3_AHB_CLK>, 1051 <&gcc GCC_PCIE3_AUX_CLK>; 1052 clock-names = "axi_m", 1053 "axi_s", 1054 "axi_bridge", 1055 "rchng", 1056 "ahb", 1057 "aux"; 1058 1059 resets = <&gcc GCC_PCIE3_PIPE_ARES>, 1060 <&gcc GCC_PCIE3_CORE_STICKY_ARES>, 1061 <&gcc GCC_PCIE3_AXI_S_STICKY_ARES>, 1062 <&gcc GCC_PCIE3_AXI_S_ARES>, 1063 <&gcc GCC_PCIE3_AXI_M_STICKY_ARES>, 1064 <&gcc GCC_PCIE3_AXI_M_ARES>, 1065 <&gcc GCC_PCIE3_AUX_ARES>, 1066 <&gcc GCC_PCIE3_AHB_ARES>; 1067 reset-names = "pipe", 1068 "sticky", 1069 "axi_s_sticky", 1070 "axi_s", 1071 "axi_m_sticky", 1072 "axi_m", 1073 "aux", 1074 "ahb"; 1075 1076 phys = <&pcie3_phy>; 1077 phy-names = "pciephy"; 1078 interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, 1079 <&gcc MASTER_SNOC_PCIE3 &gcc SLAVE_SNOC_PCIE3>; 1080 interconnect-names = "pcie-mem", "cpu-pcie"; 1081 status = "disabled"; 1082 }; 1083 1084 pcie2: pcie@20000000 { 1085 compatible = "qcom,pcie-ipq9574"; 1086 reg = <0x20000000 0xf1d>, 1087 <0x20000f20 0xa8>, 1088 <0x20001000 0x1000>, 1089 <0x00088000 0x4000>, 1090 <0x20100000 0x1000>, 1091 <0x0008e000 0x1000>; 1092 reg-names = "dbi", 1093 "elbi", 1094 "atu", 1095 "parf", 1096 "config", 1097 "mhi"; 1098 device_type = "pci"; 1099 linux,pci-domain = <2>; 1100 bus-range = <0x00 0xff>; 1101 num-lanes = <2>; 1102 #address-cells = <3>; 1103 #size-cells = <2>; 1104 1105 ranges = <0x01000000 0x0 0x00000000 0x20200000 0x0 0x100000>, 1106 <0x02000000 0x0 0x20300000 0x20300000 0x0 0x7d00000>; 1107 1108 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1116 interrupt-names = "msi0", 1117 "msi1", 1118 "msi2", 1119 "msi3", 1120 "msi4", 1121 "msi5", 1122 "msi6", 1123 "msi7"; 1124 1125 #interrupt-cells = <1>; 1126 interrupt-map-mask = <0 0 0 0x7>; 1127 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1128 <0 0 0 2 &intc 0 GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1129 <0 0 0 3 &intc 0 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1130 <0 0 0 4 &intc 0 GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1131 1132 clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, 1133 <&gcc GCC_PCIE2_AXI_S_CLK>, 1134 <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, 1135 <&gcc GCC_PCIE2_RCHNG_CLK>, 1136 <&gcc GCC_PCIE2_AHB_CLK>, 1137 <&gcc GCC_PCIE2_AUX_CLK>; 1138 clock-names = "axi_m", 1139 "axi_s", 1140 "axi_bridge", 1141 "rchng", 1142 "ahb", 1143 "aux"; 1144 1145 resets = <&gcc GCC_PCIE2_PIPE_ARES>, 1146 <&gcc GCC_PCIE2_CORE_STICKY_ARES>, 1147 <&gcc GCC_PCIE2_AXI_S_STICKY_ARES>, 1148 <&gcc GCC_PCIE2_AXI_S_ARES>, 1149 <&gcc GCC_PCIE2_AXI_M_STICKY_ARES>, 1150 <&gcc GCC_PCIE2_AXI_M_ARES>, 1151 <&gcc GCC_PCIE2_AUX_ARES>, 1152 <&gcc GCC_PCIE2_AHB_ARES>; 1153 reset-names = "pipe", 1154 "sticky", 1155 "axi_s_sticky", 1156 "axi_s", 1157 "axi_m_sticky", 1158 "axi_m", 1159 "aux", 1160 "ahb"; 1161 1162 phys = <&pcie2_phy>; 1163 phy-names = "pciephy"; 1164 interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, 1165 <&gcc MASTER_SNOC_PCIE2 &gcc SLAVE_SNOC_PCIE2>; 1166 interconnect-names = "pcie-mem", "cpu-pcie"; 1167 status = "disabled"; 1168 }; 1169 1170 pcie0: pcie@28000000 { 1171 compatible = "qcom,pcie-ipq9574"; 1172 reg = <0x28000000 0xf1d>, 1173 <0x28000f20 0xa8>, 1174 <0x28001000 0x1000>, 1175 <0x00080000 0x4000>, 1176 <0x28100000 0x1000>, 1177 <0x00086000 0x1000>; 1178 reg-names = "dbi", 1179 "elbi", 1180 "atu", 1181 "parf", 1182 "config", 1183 "mhi"; 1184 device_type = "pci"; 1185 linux,pci-domain = <0>; 1186 bus-range = <0x00 0xff>; 1187 num-lanes = <1>; 1188 #address-cells = <3>; 1189 #size-cells = <2>; 1190 1191 ranges = <0x01000000 0x0 0x00000000 0x28200000 0x0 0x100000>, 1192 <0x02000000 0x0 0x28300000 0x28300000 0x0 0x7d00000>; 1193 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1201 interrupt-names = "msi0", 1202 "msi1", 1203 "msi2", 1204 "msi3", 1205 "msi4", 1206 "msi5", 1207 "msi6", 1208 "msi7"; 1209 1210 #interrupt-cells = <1>; 1211 interrupt-map-mask = <0 0 0 0x7>; 1212 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1213 <0 0 0 2 &intc 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 1214 <0 0 0 3 &intc 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 1215 <0 0 0 4 &intc 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1216 1217 clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, 1218 <&gcc GCC_PCIE0_AXI_S_CLK>, 1219 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 1220 <&gcc GCC_PCIE0_RCHNG_CLK>, 1221 <&gcc GCC_PCIE0_AHB_CLK>, 1222 <&gcc GCC_PCIE0_AUX_CLK>; 1223 clock-names = "axi_m", 1224 "axi_s", 1225 "axi_bridge", 1226 "rchng", 1227 "ahb", 1228 "aux"; 1229 1230 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 1231 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 1232 <&gcc GCC_PCIE0_AXI_S_STICKY_ARES>, 1233 <&gcc GCC_PCIE0_AXI_S_ARES>, 1234 <&gcc GCC_PCIE0_AXI_M_STICKY_ARES>, 1235 <&gcc GCC_PCIE0_AXI_M_ARES>, 1236 <&gcc GCC_PCIE0_AUX_ARES>, 1237 <&gcc GCC_PCIE0_AHB_ARES>; 1238 reset-names = "pipe", 1239 "sticky", 1240 "axi_s_sticky", 1241 "axi_s", 1242 "axi_m_sticky", 1243 "axi_m", 1244 "aux", 1245 "ahb"; 1246 1247 phys = <&pcie0_phy>; 1248 phy-names = "pciephy"; 1249 interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, 1250 <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; 1251 interconnect-names = "pcie-mem", "cpu-pcie"; 1252 status = "disabled"; 1253 }; 1254 1255 nsscc: clock-controller@39b00000 { 1256 compatible = "qcom,ipq9574-nsscc"; 1257 reg = <0x39b00000 0x80000>; 1258 clocks = <&xo_board_clk>, 1259 <&cmn_pll NSS_1200MHZ_CLK>, 1260 <&cmn_pll PPE_353MHZ_CLK>, 1261 <&gcc GPLL0_OUT_AUX>, 1262 <0>, 1263 <0>, 1264 <0>, 1265 <0>, 1266 <0>, 1267 <0>, 1268 <&gcc GCC_NSSCC_CLK>; 1269 clock-names = "xo", 1270 "nss_1200", 1271 "ppe_353", 1272 "gpll0_out", 1273 "uniphy0_rx", 1274 "uniphy0_tx", 1275 "uniphy1_rx", 1276 "uniphy1_tx", 1277 "uniphy2_rx", 1278 "uniphy2_tx", 1279 "bus"; 1280 #clock-cells = <1>; 1281 #reset-cells = <1>; 1282 #interconnect-cells = <1>; 1283 }; 1284 }; 1285 1286 thermal-zones { 1287 nss-top-thermal { 1288 thermal-sensors = <&tsens 3>; 1289 1290 trips { 1291 nss-top-critical { 1292 temperature = <125000>; 1293 hysteresis = <1000>; 1294 type = "critical"; 1295 }; 1296 }; 1297 }; 1298 1299 ubi-0-thermal { 1300 thermal-sensors = <&tsens 4>; 1301 1302 trips { 1303 ubi_0-critical { 1304 temperature = <125000>; 1305 hysteresis = <1000>; 1306 type = "critical"; 1307 }; 1308 }; 1309 }; 1310 1311 ubi-1-thermal { 1312 thermal-sensors = <&tsens 5>; 1313 1314 trips { 1315 ubi_1-critical { 1316 temperature = <125000>; 1317 hysteresis = <1000>; 1318 type = "critical"; 1319 }; 1320 }; 1321 }; 1322 1323 ubi-2-thermal { 1324 thermal-sensors = <&tsens 6>; 1325 1326 trips { 1327 ubi_2-critical { 1328 temperature = <125000>; 1329 hysteresis = <1000>; 1330 type = "critical"; 1331 }; 1332 }; 1333 }; 1334 1335 ubi-3-thermal { 1336 thermal-sensors = <&tsens 7>; 1337 1338 trips { 1339 ubi_3-critical { 1340 temperature = <125000>; 1341 hysteresis = <1000>; 1342 type = "critical"; 1343 }; 1344 }; 1345 }; 1346 1347 cpuss0-thermal { 1348 thermal-sensors = <&tsens 8>; 1349 1350 trips { 1351 cpu-critical { 1352 temperature = <125000>; 1353 hysteresis = <1000>; 1354 type = "critical"; 1355 }; 1356 }; 1357 }; 1358 1359 cpuss1-thermal { 1360 thermal-sensors = <&tsens 9>; 1361 1362 trips { 1363 cpu-critical { 1364 temperature = <125000>; 1365 hysteresis = <1000>; 1366 type = "critical"; 1367 }; 1368 }; 1369 }; 1370 1371 cpu0-thermal { 1372 thermal-sensors = <&tsens 10>; 1373 1374 trips { 1375 cpu0_crit: cpu-critical { 1376 temperature = <120000>; 1377 hysteresis = <10000>; 1378 type = "critical"; 1379 }; 1380 1381 cpu0_alert: cpu-passive { 1382 temperature = <110000>; 1383 hysteresis = <1000>; 1384 type = "passive"; 1385 }; 1386 }; 1387 1388 cooling-maps { 1389 map0 { 1390 trip = <&cpu0_alert>; 1391 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1392 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1393 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1394 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1395 }; 1396 }; 1397 }; 1398 1399 cpu1-thermal { 1400 thermal-sensors = <&tsens 11>; 1401 1402 trips { 1403 cpu1_crit: cpu-critical { 1404 temperature = <120000>; 1405 hysteresis = <10000>; 1406 type = "critical"; 1407 }; 1408 1409 cpu1_alert: cpu-passive { 1410 temperature = <110000>; 1411 hysteresis = <1000>; 1412 type = "passive"; 1413 }; 1414 }; 1415 1416 cooling-maps { 1417 map0 { 1418 trip = <&cpu1_alert>; 1419 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1420 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1421 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1422 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1423 }; 1424 }; 1425 }; 1426 1427 cpu2-thermal { 1428 thermal-sensors = <&tsens 12>; 1429 1430 trips { 1431 cpu2_crit: cpu-critical { 1432 temperature = <120000>; 1433 hysteresis = <10000>; 1434 type = "critical"; 1435 }; 1436 1437 cpu2_alert: cpu-passive { 1438 temperature = <110000>; 1439 hysteresis = <1000>; 1440 type = "passive"; 1441 }; 1442 }; 1443 1444 cooling-maps { 1445 map0 { 1446 trip = <&cpu2_alert>; 1447 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1448 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1449 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1450 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1451 }; 1452 }; 1453 }; 1454 1455 cpu3-thermal { 1456 thermal-sensors = <&tsens 13>; 1457 1458 trips { 1459 cpu3_crit: cpu-critical { 1460 temperature = <120000>; 1461 hysteresis = <10000>; 1462 type = "critical"; 1463 }; 1464 1465 cpu3_alert: cpu-passive { 1466 temperature = <110000>; 1467 hysteresis = <1000>; 1468 type = "passive"; 1469 }; 1470 }; 1471 1472 cooling-maps { 1473 map0 { 1474 trip = <&cpu3_alert>; 1475 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1476 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1477 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1478 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1479 }; 1480 }; 1481 }; 1482 1483 wcss-phyb-thermal { 1484 thermal-sensors = <&tsens 14>; 1485 1486 trips { 1487 wcss_phyb-critical { 1488 temperature = <125000>; 1489 hysteresis = <1000>; 1490 type = "critical"; 1491 }; 1492 }; 1493 }; 1494 1495 top-glue-thermal { 1496 thermal-sensors = <&tsens 15>; 1497 1498 trips { 1499 top_glue-critical { 1500 temperature = <125000>; 1501 hysteresis = <1000>; 1502 type = "critical"; 1503 }; 1504 }; 1505 }; 1506 }; 1507 1508 timer { 1509 compatible = "arm,armv8-timer"; 1510 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1511 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1512 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1513 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1514 }; 1515}; 1516