1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ9574 SoC device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,apss-ipq.h> 10#include <dt-bindings/clock/qcom,ipq9574-gcc.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/qcom,ipq9574-gcc.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clocks { 21 sleep_clk: sleep-clk { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 }; 25 26 xo_board_clk: xo-board-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a73"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&L2_0>; 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu_opp_table>; 45 cpu-supply = <&ipq9574_s1>; 46 #cooling-cells = <2>; 47 }; 48 49 CPU1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a73"; 52 reg = <0x1>; 53 enable-method = "psci"; 54 next-level-cache = <&L2_0>; 55 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 56 clock-names = "cpu"; 57 operating-points-v2 = <&cpu_opp_table>; 58 cpu-supply = <&ipq9574_s1>; 59 #cooling-cells = <2>; 60 }; 61 62 CPU2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a73"; 65 reg = <0x2>; 66 enable-method = "psci"; 67 next-level-cache = <&L2_0>; 68 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 69 clock-names = "cpu"; 70 operating-points-v2 = <&cpu_opp_table>; 71 cpu-supply = <&ipq9574_s1>; 72 #cooling-cells = <2>; 73 }; 74 75 CPU3: cpu@3 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a73"; 78 reg = <0x3>; 79 enable-method = "psci"; 80 next-level-cache = <&L2_0>; 81 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 82 clock-names = "cpu"; 83 operating-points-v2 = <&cpu_opp_table>; 84 cpu-supply = <&ipq9574_s1>; 85 #cooling-cells = <2>; 86 }; 87 88 L2_0: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 }; 93 }; 94 95 firmware { 96 scm { 97 compatible = "qcom,scm-ipq9574", "qcom,scm"; 98 qcom,dload-mode = <&tcsr 0x6100>; 99 }; 100 }; 101 102 memory@40000000 { 103 device_type = "memory"; 104 /* We expect the bootloader to fill in the size */ 105 reg = <0x0 0x40000000 0x0 0x0>; 106 }; 107 108 cpu_opp_table: opp-table-cpu { 109 compatible = "operating-points-v2-kryo-cpu"; 110 opp-shared; 111 nvmem-cells = <&cpu_speed_bin>; 112 113 opp-936000000 { 114 opp-hz = /bits/ 64 <936000000>; 115 opp-microvolt = <725000>; 116 opp-supported-hw = <0xf>; 117 clock-latency-ns = <200000>; 118 }; 119 120 opp-1104000000 { 121 opp-hz = /bits/ 64 <1104000000>; 122 opp-microvolt = <787500>; 123 opp-supported-hw = <0xf>; 124 clock-latency-ns = <200000>; 125 }; 126 127 opp-1200000000 { 128 opp-hz = /bits/ 64 <1200000000>; 129 opp-microvolt = <862500>; 130 opp-supported-hw = <0xf>; 131 clock-latency-ns = <200000>; 132 }; 133 134 opp-1416000000 { 135 opp-hz = /bits/ 64 <1416000000>; 136 opp-microvolt = <862500>; 137 opp-supported-hw = <0x7>; 138 clock-latency-ns = <200000>; 139 }; 140 141 opp-1488000000 { 142 opp-hz = /bits/ 64 <1488000000>; 143 opp-microvolt = <925000>; 144 opp-supported-hw = <0x7>; 145 clock-latency-ns = <200000>; 146 }; 147 148 opp-1800000000 { 149 opp-hz = /bits/ 64 <1800000000>; 150 opp-microvolt = <987500>; 151 opp-supported-hw = <0x5>; 152 clock-latency-ns = <200000>; 153 }; 154 155 opp-2208000000 { 156 opp-hz = /bits/ 64 <2208000000>; 157 opp-microvolt = <1062500>; 158 opp-supported-hw = <0x1>; 159 clock-latency-ns = <200000>; 160 }; 161 }; 162 163 pmu { 164 compatible = "arm,cortex-a73-pmu"; 165 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 166 }; 167 168 psci { 169 compatible = "arm,psci-1.0"; 170 method = "smc"; 171 }; 172 173 rpm: remoteproc { 174 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc"; 175 176 glink-edge { 177 compatible = "qcom,glink-rpm"; 178 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 179 qcom,rpm-msg-ram = <&rpm_msg_ram>; 180 mboxes = <&apcs_glb 0>; 181 182 rpm_requests: rpm-requests { 183 compatible = "qcom,rpm-ipq9574"; 184 qcom,glink-channels = "rpm_requests"; 185 }; 186 }; 187 }; 188 189 reserved-memory { 190 #address-cells = <2>; 191 #size-cells = <2>; 192 ranges; 193 194 bootloader@4a100000 { 195 reg = <0x0 0x4a100000 0x0 0x400000>; 196 no-map; 197 }; 198 199 sbl@4a500000 { 200 reg = <0x0 0x4a500000 0x0 0x100000>; 201 no-map; 202 }; 203 204 tz_region: tz@4a600000 { 205 reg = <0x0 0x4a600000 0x0 0x400000>; 206 no-map; 207 }; 208 209 smem@4aa00000 { 210 compatible = "qcom,smem"; 211 reg = <0x0 0x4aa00000 0x0 0x100000>; 212 hwlocks = <&tcsr_mutex 3>; 213 no-map; 214 }; 215 }; 216 217 soc: soc@0 { 218 compatible = "simple-bus"; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 ranges = <0 0 0 0xffffffff>; 222 223 rpm_msg_ram: sram@60000 { 224 compatible = "qcom,rpm-msg-ram"; 225 reg = <0x00060000 0x6000>; 226 }; 227 228 rng: rng@e3000 { 229 compatible = "qcom,prng-ee"; 230 reg = <0x000e3000 0x1000>; 231 clocks = <&gcc GCC_PRNG_AHB_CLK>; 232 clock-names = "core"; 233 }; 234 235 qfprom: efuse@a4000 { 236 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; 237 reg = <0x000a4000 0x5a1>; 238 #address-cells = <1>; 239 #size-cells = <1>; 240 241 cpu_speed_bin: cpu-speed-bin@15 { 242 reg = <0x15 0x2>; 243 bits = <7 2>; 244 }; 245 }; 246 247 cryptobam: dma-controller@704000 { 248 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 249 reg = <0x00704000 0x20000>; 250 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 251 #dma-cells = <1>; 252 qcom,ee = <1>; 253 qcom,controlled-remotely; 254 }; 255 256 crypto: crypto@73a000 { 257 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce"; 258 reg = <0x0073a000 0x6000>; 259 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 260 <&gcc GCC_CRYPTO_AXI_CLK>, 261 <&gcc GCC_CRYPTO_CLK>; 262 clock-names = "iface", "bus", "core"; 263 dmas = <&cryptobam 2>, <&cryptobam 3>; 264 dma-names = "rx", "tx"; 265 }; 266 267 tsens: thermal-sensor@4a9000 { 268 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens"; 269 reg = <0x004a9000 0x1000>, 270 <0x004a8000 0x1000>; 271 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 272 interrupt-names = "combined"; 273 #qcom,sensors = <16>; 274 #thermal-sensor-cells = <1>; 275 }; 276 277 tlmm: pinctrl@1000000 { 278 compatible = "qcom,ipq9574-tlmm"; 279 reg = <0x01000000 0x300000>; 280 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 281 gpio-controller; 282 #gpio-cells = <2>; 283 gpio-ranges = <&tlmm 0 0 65>; 284 interrupt-controller; 285 #interrupt-cells = <2>; 286 287 uart2_pins: uart2-state { 288 pins = "gpio34", "gpio35"; 289 function = "blsp2_uart"; 290 drive-strength = <8>; 291 bias-disable; 292 }; 293 }; 294 295 gcc: clock-controller@1800000 { 296 compatible = "qcom,ipq9574-gcc"; 297 reg = <0x01800000 0x80000>; 298 clocks = <&xo_board_clk>, 299 <&sleep_clk>, 300 <0>, 301 <0>, 302 <0>, 303 <0>, 304 <0>, 305 <0>; 306 #clock-cells = <1>; 307 #reset-cells = <1>; 308 #power-domain-cells = <1>; 309 }; 310 311 tcsr_mutex: hwlock@1905000 { 312 compatible = "qcom,tcsr-mutex"; 313 reg = <0x01905000 0x20000>; 314 #hwlock-cells = <1>; 315 }; 316 317 tcsr: syscon@1937000 { 318 compatible = "qcom,tcsr-ipq9574", "syscon"; 319 reg = <0x01937000 0x21000>; 320 }; 321 322 sdhc_1: mmc@7804000 { 323 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; 324 reg = <0x07804000 0x1000>, 325 <0x07805000 0x1000>, 326 <0x07808000 0x2000>; 327 reg-names = "hc", "cqhci", "ice"; 328 329 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 331 interrupt-names = "hc_irq", "pwr_irq"; 332 333 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 334 <&gcc GCC_SDCC1_APPS_CLK>, 335 <&xo_board_clk>, 336 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 337 clock-names = "iface", "core", "xo", "ice"; 338 non-removable; 339 supports-cqe; 340 status = "disabled"; 341 }; 342 343 blsp_dma: dma-controller@7884000 { 344 compatible = "qcom,bam-v1.7.0"; 345 reg = <0x07884000 0x2b000>; 346 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 348 clock-names = "bam_clk"; 349 #dma-cells = <1>; 350 qcom,ee = <0>; 351 }; 352 353 blsp1_uart0: serial@78af000 { 354 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 355 reg = <0x078af000 0x200>; 356 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 358 <&gcc GCC_BLSP1_AHB_CLK>; 359 clock-names = "core", "iface"; 360 status = "disabled"; 361 }; 362 363 blsp1_uart1: serial@78b0000 { 364 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 365 reg = <0x078b0000 0x200>; 366 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 368 <&gcc GCC_BLSP1_AHB_CLK>; 369 clock-names = "core", "iface"; 370 status = "disabled"; 371 }; 372 373 blsp1_uart2: serial@78b1000 { 374 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 375 reg = <0x078b1000 0x200>; 376 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 378 <&gcc GCC_BLSP1_AHB_CLK>; 379 clock-names = "core", "iface"; 380 status = "disabled"; 381 }; 382 383 blsp1_uart3: serial@78b2000 { 384 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 385 reg = <0x078b2000 0x200>; 386 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, 388 <&gcc GCC_BLSP1_AHB_CLK>; 389 clock-names = "core", "iface"; 390 status = "disabled"; 391 }; 392 393 blsp1_uart4: serial@78b3000 { 394 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 395 reg = <0x078b3000 0x200>; 396 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 398 <&gcc GCC_BLSP1_AHB_CLK>; 399 clock-names = "core", "iface"; 400 status = "disabled"; 401 }; 402 403 blsp1_uart5: serial@78b4000 { 404 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 405 reg = <0x078b4000 0x200>; 406 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, 408 <&gcc GCC_BLSP1_AHB_CLK>; 409 clock-names = "core", "iface"; 410 status = "disabled"; 411 }; 412 413 blsp1_spi0: spi@78b5000 { 414 compatible = "qcom,spi-qup-v2.2.1"; 415 reg = <0x078b5000 0x600>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 420 <&gcc GCC_BLSP1_AHB_CLK>; 421 clock-names = "core", "iface"; 422 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 423 dma-names = "tx", "rx"; 424 status = "disabled"; 425 }; 426 427 blsp1_i2c1: i2c@78b6000 { 428 compatible = "qcom,i2c-qup-v2.2.1"; 429 reg = <0x078b6000 0x600>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 434 <&gcc GCC_BLSP1_AHB_CLK>; 435 clock-names = "core", "iface"; 436 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 437 assigned-clock-rates = <50000000>; 438 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 439 dma-names = "tx", "rx"; 440 status = "disabled"; 441 }; 442 443 blsp1_spi1: spi@78b6000 { 444 compatible = "qcom,spi-qup-v2.2.1"; 445 reg = <0x078b6000 0x600>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 450 <&gcc GCC_BLSP1_AHB_CLK>; 451 clock-names = "core", "iface"; 452 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 453 dma-names = "tx", "rx"; 454 status = "disabled"; 455 }; 456 457 blsp1_i2c2: i2c@78b7000 { 458 compatible = "qcom,i2c-qup-v2.2.1"; 459 reg = <0x078b7000 0x600>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 464 <&gcc GCC_BLSP1_AHB_CLK>; 465 clock-names = "core", "iface"; 466 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 467 assigned-clock-rates = <50000000>; 468 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 469 dma-names = "tx", "rx"; 470 status = "disabled"; 471 }; 472 473 blsp1_spi2: spi@78b7000 { 474 compatible = "qcom,spi-qup-v2.2.1"; 475 reg = <0x078b7000 0x600>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 480 <&gcc GCC_BLSP1_AHB_CLK>; 481 clock-names = "core", "iface"; 482 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 483 dma-names = "tx", "rx"; 484 status = "disabled"; 485 }; 486 487 blsp1_i2c3: i2c@78b8000 { 488 compatible = "qcom,i2c-qup-v2.2.1"; 489 reg = <0x078b8000 0x600>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 494 <&gcc GCC_BLSP1_AHB_CLK>; 495 clock-names = "core", "iface"; 496 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 497 assigned-clock-rates = <50000000>; 498 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 499 dma-names = "tx", "rx"; 500 status = "disabled"; 501 }; 502 503 blsp1_spi3: spi@78b8000 { 504 compatible = "qcom,spi-qup-v2.2.1"; 505 reg = <0x078b8000 0x600>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 509 spi-max-frequency = <50000000>; 510 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 511 <&gcc GCC_BLSP1_AHB_CLK>; 512 clock-names = "core", "iface"; 513 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 514 dma-names = "tx", "rx"; 515 status = "disabled"; 516 }; 517 518 blsp1_i2c4: i2c@78b9000 { 519 compatible = "qcom,i2c-qup-v2.2.1"; 520 reg = <0x078b9000 0x600>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 525 <&gcc GCC_BLSP1_AHB_CLK>; 526 clock-names = "core", "iface"; 527 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 528 assigned-clock-rates = <50000000>; 529 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 530 dma-names = "tx", "rx"; 531 status = "disabled"; 532 }; 533 534 blsp1_spi4: spi@78b9000 { 535 compatible = "qcom,spi-qup-v2.2.1"; 536 reg = <0x078b9000 0x600>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 541 <&gcc GCC_BLSP1_AHB_CLK>; 542 clock-names = "core", "iface"; 543 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 544 dma-names = "tx", "rx"; 545 status = "disabled"; 546 }; 547 548 usb_0_qusbphy: phy@7b000 { 549 compatible = "qcom,ipq9574-qusb2-phy"; 550 reg = <0x0007b000 0x180>; 551 #phy-cells = <0>; 552 553 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 554 <&xo_board_clk>; 555 clock-names = "cfg_ahb", 556 "ref"; 557 558 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 559 status = "disabled"; 560 }; 561 562 usb_0_qmpphy: phy@7d000 { 563 compatible = "qcom,ipq9574-qmp-usb3-phy"; 564 reg = <0x0007d000 0xa00>; 565 #phy-cells = <0>; 566 567 clocks = <&gcc GCC_USB0_AUX_CLK>, 568 <&xo_board_clk>, 569 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 570 <&gcc GCC_USB0_PIPE_CLK>; 571 clock-names = "aux", 572 "ref", 573 "cfg_ahb", 574 "pipe"; 575 576 resets = <&gcc GCC_USB0_PHY_BCR>, 577 <&gcc GCC_USB3PHY_0_PHY_BCR>; 578 reset-names = "phy", 579 "phy_phy"; 580 581 #clock-cells = <0>; 582 clock-output-names = "usb0_pipe_clk"; 583 584 status = "disabled"; 585 }; 586 587 usb3: usb@8af8800 { 588 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; 589 reg = <0x08af8800 0x400>; 590 #address-cells = <1>; 591 #size-cells = <1>; 592 ranges; 593 594 clocks = <&gcc GCC_SNOC_USB_CLK>, 595 <&gcc GCC_USB0_MASTER_CLK>, 596 <&gcc GCC_ANOC_USB_AXI_CLK>, 597 <&gcc GCC_USB0_SLEEP_CLK>, 598 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 599 600 clock-names = "cfg_noc", 601 "core", 602 "iface", 603 "sleep", 604 "mock_utmi"; 605 606 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, 607 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 608 assigned-clock-rates = <200000000>, 609 <24000000>; 610 611 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 612 interrupt-names = "pwr_event"; 613 614 resets = <&gcc GCC_USB_BCR>; 615 status = "disabled"; 616 617 usb_0_dwc3: usb@8a00000 { 618 compatible = "snps,dwc3"; 619 reg = <0x8a00000 0xcd00>; 620 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 621 clock-names = "ref"; 622 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 623 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>; 624 phy-names = "usb2-phy", "usb3-phy"; 625 tx-fifo-resize; 626 snps,is-utmi-l1-suspend; 627 snps,hird-threshold = /bits/ 8 <0x0>; 628 snps,dis_u2_susphy_quirk; 629 snps,dis_u3_susphy_quirk; 630 }; 631 }; 632 633 intc: interrupt-controller@b000000 { 634 compatible = "qcom,msm-qgic2"; 635 reg = <0x0b000000 0x1000>, /* GICD */ 636 <0x0b002000 0x2000>, /* GICC */ 637 <0x0b001000 0x1000>, /* GICH */ 638 <0x0b004000 0x2000>; /* GICV */ 639 #address-cells = <1>; 640 #size-cells = <1>; 641 interrupt-controller; 642 #interrupt-cells = <3>; 643 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 644 ranges = <0 0x0b00c000 0x3000>; 645 646 v2m0: v2m@0 { 647 compatible = "arm,gic-v2m-frame"; 648 reg = <0x00000000 0xffd>; 649 msi-controller; 650 }; 651 652 v2m1: v2m@1000 { 653 compatible = "arm,gic-v2m-frame"; 654 reg = <0x00001000 0xffd>; 655 msi-controller; 656 }; 657 658 v2m2: v2m@2000 { 659 compatible = "arm,gic-v2m-frame"; 660 reg = <0x00002000 0xffd>; 661 msi-controller; 662 }; 663 }; 664 665 watchdog: watchdog@b017000 { 666 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt"; 667 reg = <0x0b017000 0x1000>; 668 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 669 clocks = <&sleep_clk>; 670 timeout-sec = <30>; 671 }; 672 673 apcs_glb: mailbox@b111000 { 674 compatible = "qcom,ipq9574-apcs-apps-global", 675 "qcom,ipq6018-apcs-apps-global"; 676 reg = <0x0b111000 0x1000>; 677 #clock-cells = <1>; 678 clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>; 679 clock-names = "pll", "xo", "gpll0"; 680 #mbox-cells = <1>; 681 }; 682 683 a73pll: clock@b116000 { 684 compatible = "qcom,ipq9574-a73pll"; 685 reg = <0x0b116000 0x40>; 686 #clock-cells = <0>; 687 clocks = <&xo_board_clk>; 688 clock-names = "xo"; 689 }; 690 691 timer@b120000 { 692 compatible = "arm,armv7-timer-mem"; 693 reg = <0x0b120000 0x1000>; 694 #address-cells = <1>; 695 #size-cells = <1>; 696 ranges; 697 698 frame@b120000 { 699 reg = <0x0b121000 0x1000>, 700 <0x0b122000 0x1000>; 701 frame-number = <0>; 702 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 704 }; 705 706 frame@b123000 { 707 reg = <0x0b123000 0x1000>; 708 frame-number = <1>; 709 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 710 status = "disabled"; 711 }; 712 713 frame@b124000 { 714 reg = <0x0b124000 0x1000>; 715 frame-number = <2>; 716 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 717 status = "disabled"; 718 }; 719 720 frame@b125000 { 721 reg = <0x0b125000 0x1000>; 722 frame-number = <3>; 723 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 724 status = "disabled"; 725 }; 726 727 frame@b126000 { 728 reg = <0x0b126000 0x1000>; 729 frame-number = <4>; 730 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 731 status = "disabled"; 732 }; 733 734 frame@b127000 { 735 reg = <0x0b127000 0x1000>; 736 frame-number = <5>; 737 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 738 status = "disabled"; 739 }; 740 741 frame@b128000 { 742 reg = <0x0b128000 0x1000>; 743 frame-number = <6>; 744 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 745 status = "disabled"; 746 }; 747 }; 748 }; 749 750 thermal-zones { 751 nss-top-thermal { 752 polling-delay-passive = <0>; 753 polling-delay = <0>; 754 thermal-sensors = <&tsens 3>; 755 756 trips { 757 nss-top-critical { 758 temperature = <125000>; 759 hysteresis = <1000>; 760 type = "critical"; 761 }; 762 }; 763 }; 764 765 ubi-0-thermal { 766 polling-delay-passive = <0>; 767 polling-delay = <0>; 768 thermal-sensors = <&tsens 4>; 769 770 trips { 771 ubi_0-critical { 772 temperature = <125000>; 773 hysteresis = <1000>; 774 type = "critical"; 775 }; 776 }; 777 }; 778 779 ubi-1-thermal { 780 polling-delay-passive = <0>; 781 polling-delay = <0>; 782 thermal-sensors = <&tsens 5>; 783 784 trips { 785 ubi_1-critical { 786 temperature = <125000>; 787 hysteresis = <1000>; 788 type = "critical"; 789 }; 790 }; 791 }; 792 793 ubi-2-thermal { 794 polling-delay-passive = <0>; 795 polling-delay = <0>; 796 thermal-sensors = <&tsens 6>; 797 798 trips { 799 ubi_2-critical { 800 temperature = <125000>; 801 hysteresis = <1000>; 802 type = "critical"; 803 }; 804 }; 805 }; 806 807 ubi-3-thermal { 808 polling-delay-passive = <0>; 809 polling-delay = <0>; 810 thermal-sensors = <&tsens 7>; 811 812 trips { 813 ubi_3-critical { 814 temperature = <125000>; 815 hysteresis = <1000>; 816 type = "critical"; 817 }; 818 }; 819 }; 820 821 cpuss0-thermal { 822 polling-delay-passive = <0>; 823 polling-delay = <0>; 824 thermal-sensors = <&tsens 8>; 825 826 trips { 827 cpu-critical { 828 temperature = <125000>; 829 hysteresis = <1000>; 830 type = "critical"; 831 }; 832 }; 833 }; 834 835 cpuss1-thermal { 836 polling-delay-passive = <0>; 837 polling-delay = <0>; 838 thermal-sensors = <&tsens 9>; 839 840 trips { 841 cpu-critical { 842 temperature = <125000>; 843 hysteresis = <1000>; 844 type = "critical"; 845 }; 846 }; 847 }; 848 849 cpu0-thermal { 850 polling-delay-passive = <0>; 851 polling-delay = <0>; 852 thermal-sensors = <&tsens 10>; 853 854 trips { 855 cpu0_crit: cpu-critical { 856 temperature = <120000>; 857 hysteresis = <10000>; 858 type = "critical"; 859 }; 860 861 cpu0_alert: cpu-passive { 862 temperature = <110000>; 863 hysteresis = <1000>; 864 type = "passive"; 865 }; 866 }; 867 868 cooling-maps { 869 map0 { 870 trip = <&cpu0_alert>; 871 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 872 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 873 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 874 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 875 }; 876 }; 877 }; 878 879 cpu1-thermal { 880 polling-delay-passive = <0>; 881 polling-delay = <0>; 882 thermal-sensors = <&tsens 11>; 883 884 trips { 885 cpu1_crit: cpu-critical { 886 temperature = <120000>; 887 hysteresis = <10000>; 888 type = "critical"; 889 }; 890 891 cpu1_alert: cpu-passive { 892 temperature = <110000>; 893 hysteresis = <1000>; 894 type = "passive"; 895 }; 896 }; 897 898 cooling-maps { 899 map0 { 900 trip = <&cpu1_alert>; 901 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 902 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 903 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 904 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 905 }; 906 }; 907 }; 908 909 cpu2-thermal { 910 polling-delay-passive = <0>; 911 polling-delay = <0>; 912 thermal-sensors = <&tsens 12>; 913 914 trips { 915 cpu2_crit: cpu-critical { 916 temperature = <120000>; 917 hysteresis = <10000>; 918 type = "critical"; 919 }; 920 921 cpu2_alert: cpu-passive { 922 temperature = <110000>; 923 hysteresis = <1000>; 924 type = "passive"; 925 }; 926 }; 927 928 cooling-maps { 929 map0 { 930 trip = <&cpu2_alert>; 931 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 932 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 933 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 934 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 935 }; 936 }; 937 }; 938 939 cpu3-thermal { 940 polling-delay-passive = <0>; 941 polling-delay = <0>; 942 thermal-sensors = <&tsens 13>; 943 944 trips { 945 cpu3_crit: cpu-critical { 946 temperature = <120000>; 947 hysteresis = <10000>; 948 type = "critical"; 949 }; 950 951 cpu3_alert: cpu-passive { 952 temperature = <110000>; 953 hysteresis = <1000>; 954 type = "passive"; 955 }; 956 }; 957 958 cooling-maps { 959 map0 { 960 trip = <&cpu3_alert>; 961 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 962 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 963 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 964 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 965 }; 966 }; 967 }; 968 969 wcss-phyb-thermal { 970 polling-delay-passive = <0>; 971 polling-delay = <0>; 972 thermal-sensors = <&tsens 14>; 973 974 trips { 975 wcss_phyb-critical { 976 temperature = <125000>; 977 hysteresis = <1000>; 978 type = "critical"; 979 }; 980 }; 981 }; 982 983 top-glue-thermal { 984 polling-delay-passive = <0>; 985 polling-delay = <0>; 986 thermal-sensors = <&tsens 15>; 987 988 trips { 989 top_glue-critical { 990 temperature = <125000>; 991 hysteresis = <1000>; 992 type = "critical"; 993 }; 994 }; 995 }; 996 }; 997 998 timer { 999 compatible = "arm,armv8-timer"; 1000 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1001 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1002 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1003 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1004 }; 1005}; 1006