1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ9574 SoC device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,apss-ipq.h> 10#include <dt-bindings/clock/qcom,ipq9574-gcc.h> 11#include <dt-bindings/interconnect/qcom,ipq9574.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/qcom,ipq9574-gcc.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 clocks { 22 sleep_clk: sleep-clk { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 }; 26 27 xo_board_clk: xo-board-clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 CPU0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a73"; 40 reg = <0x0>; 41 enable-method = "psci"; 42 next-level-cache = <&L2_0>; 43 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 44 clock-names = "cpu"; 45 operating-points-v2 = <&cpu_opp_table>; 46 cpu-supply = <&ipq9574_s1>; 47 #cooling-cells = <2>; 48 }; 49 50 CPU1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a73"; 53 reg = <0x1>; 54 enable-method = "psci"; 55 next-level-cache = <&L2_0>; 56 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 57 clock-names = "cpu"; 58 operating-points-v2 = <&cpu_opp_table>; 59 cpu-supply = <&ipq9574_s1>; 60 #cooling-cells = <2>; 61 }; 62 63 CPU2: cpu@2 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a73"; 66 reg = <0x2>; 67 enable-method = "psci"; 68 next-level-cache = <&L2_0>; 69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 70 clock-names = "cpu"; 71 operating-points-v2 = <&cpu_opp_table>; 72 cpu-supply = <&ipq9574_s1>; 73 #cooling-cells = <2>; 74 }; 75 76 CPU3: cpu@3 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a73"; 79 reg = <0x3>; 80 enable-method = "psci"; 81 next-level-cache = <&L2_0>; 82 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 83 clock-names = "cpu"; 84 operating-points-v2 = <&cpu_opp_table>; 85 cpu-supply = <&ipq9574_s1>; 86 #cooling-cells = <2>; 87 }; 88 89 L2_0: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 }; 94 }; 95 96 firmware { 97 scm { 98 compatible = "qcom,scm-ipq9574", "qcom,scm"; 99 qcom,dload-mode = <&tcsr 0x6100>; 100 }; 101 }; 102 103 memory@40000000 { 104 device_type = "memory"; 105 /* We expect the bootloader to fill in the size */ 106 reg = <0x0 0x40000000 0x0 0x0>; 107 }; 108 109 cpu_opp_table: opp-table-cpu { 110 compatible = "operating-points-v2-kryo-cpu"; 111 opp-shared; 112 nvmem-cells = <&cpu_speed_bin>; 113 114 opp-936000000 { 115 opp-hz = /bits/ 64 <936000000>; 116 opp-microvolt = <725000>; 117 opp-supported-hw = <0xf>; 118 clock-latency-ns = <200000>; 119 }; 120 121 opp-1104000000 { 122 opp-hz = /bits/ 64 <1104000000>; 123 opp-microvolt = <787500>; 124 opp-supported-hw = <0xf>; 125 clock-latency-ns = <200000>; 126 }; 127 128 opp-1200000000 { 129 opp-hz = /bits/ 64 <1200000000>; 130 opp-microvolt = <862500>; 131 opp-supported-hw = <0xf>; 132 clock-latency-ns = <200000>; 133 }; 134 135 opp-1416000000 { 136 opp-hz = /bits/ 64 <1416000000>; 137 opp-microvolt = <862500>; 138 opp-supported-hw = <0x7>; 139 clock-latency-ns = <200000>; 140 }; 141 142 opp-1488000000 { 143 opp-hz = /bits/ 64 <1488000000>; 144 opp-microvolt = <925000>; 145 opp-supported-hw = <0x7>; 146 clock-latency-ns = <200000>; 147 }; 148 149 opp-1800000000 { 150 opp-hz = /bits/ 64 <1800000000>; 151 opp-microvolt = <987500>; 152 opp-supported-hw = <0x5>; 153 clock-latency-ns = <200000>; 154 }; 155 156 opp-2208000000 { 157 opp-hz = /bits/ 64 <2208000000>; 158 opp-microvolt = <1062500>; 159 opp-supported-hw = <0x1>; 160 clock-latency-ns = <200000>; 161 }; 162 }; 163 164 pmu { 165 compatible = "arm,cortex-a73-pmu"; 166 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 167 }; 168 169 psci { 170 compatible = "arm,psci-1.0"; 171 method = "smc"; 172 }; 173 174 rpm: remoteproc { 175 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc"; 176 177 glink-edge { 178 compatible = "qcom,glink-rpm"; 179 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 180 qcom,rpm-msg-ram = <&rpm_msg_ram>; 181 mboxes = <&apcs_glb 0>; 182 183 rpm_requests: rpm-requests { 184 compatible = "qcom,rpm-ipq9574", "qcom,glink-smd-rpm"; 185 qcom,glink-channels = "rpm_requests"; 186 }; 187 }; 188 }; 189 190 reserved-memory { 191 #address-cells = <2>; 192 #size-cells = <2>; 193 ranges; 194 195 bootloader@4a100000 { 196 reg = <0x0 0x4a100000 0x0 0x400000>; 197 no-map; 198 }; 199 200 sbl@4a500000 { 201 reg = <0x0 0x4a500000 0x0 0x100000>; 202 no-map; 203 }; 204 205 tz_region: tz@4a600000 { 206 reg = <0x0 0x4a600000 0x0 0x400000>; 207 no-map; 208 }; 209 210 smem@4aa00000 { 211 compatible = "qcom,smem"; 212 reg = <0x0 0x4aa00000 0x0 0x100000>; 213 hwlocks = <&tcsr_mutex 3>; 214 no-map; 215 }; 216 }; 217 218 soc: soc@0 { 219 compatible = "simple-bus"; 220 #address-cells = <1>; 221 #size-cells = <1>; 222 ranges = <0 0 0 0xffffffff>; 223 224 rpm_msg_ram: sram@60000 { 225 compatible = "qcom,rpm-msg-ram"; 226 reg = <0x00060000 0x6000>; 227 }; 228 229 rng: rng@e3000 { 230 compatible = "qcom,prng-ee"; 231 reg = <0x000e3000 0x1000>; 232 clocks = <&gcc GCC_PRNG_AHB_CLK>; 233 clock-names = "core"; 234 }; 235 236 mdio: mdio@90000 { 237 compatible = "qcom,ipq9574-mdio", "qcom,ipq4019-mdio"; 238 reg = <0x00090000 0x64>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 clocks = <&gcc GCC_MDIO_AHB_CLK>; 242 clock-names = "gcc_mdio_ahb_clk"; 243 status = "disabled"; 244 }; 245 246 qfprom: efuse@a4000 { 247 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom"; 248 reg = <0x000a4000 0x5a1>; 249 #address-cells = <1>; 250 #size-cells = <1>; 251 252 cpu_speed_bin: cpu-speed-bin@15 { 253 reg = <0x15 0x2>; 254 bits = <7 2>; 255 }; 256 }; 257 258 cryptobam: dma-controller@704000 { 259 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 260 reg = <0x00704000 0x20000>; 261 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 262 #dma-cells = <1>; 263 qcom,ee = <1>; 264 qcom,controlled-remotely; 265 }; 266 267 crypto: crypto@73a000 { 268 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce"; 269 reg = <0x0073a000 0x6000>; 270 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 271 <&gcc GCC_CRYPTO_AXI_CLK>, 272 <&gcc GCC_CRYPTO_CLK>; 273 clock-names = "iface", "bus", "core"; 274 dmas = <&cryptobam 2>, <&cryptobam 3>; 275 dma-names = "rx", "tx"; 276 }; 277 278 tsens: thermal-sensor@4a9000 { 279 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens"; 280 reg = <0x004a9000 0x1000>, 281 <0x004a8000 0x1000>; 282 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 283 interrupt-names = "combined"; 284 #qcom,sensors = <16>; 285 #thermal-sensor-cells = <1>; 286 }; 287 288 tlmm: pinctrl@1000000 { 289 compatible = "qcom,ipq9574-tlmm"; 290 reg = <0x01000000 0x300000>; 291 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 292 gpio-controller; 293 #gpio-cells = <2>; 294 gpio-ranges = <&tlmm 0 0 65>; 295 interrupt-controller; 296 #interrupt-cells = <2>; 297 298 uart2_pins: uart2-state { 299 pins = "gpio34", "gpio35"; 300 function = "blsp2_uart"; 301 drive-strength = <8>; 302 bias-disable; 303 }; 304 }; 305 306 gcc: clock-controller@1800000 { 307 compatible = "qcom,ipq9574-gcc"; 308 reg = <0x01800000 0x80000>; 309 clocks = <&xo_board_clk>, 310 <&sleep_clk>, 311 <0>, 312 <0>, 313 <0>, 314 <0>, 315 <0>, 316 <0>; 317 #clock-cells = <1>; 318 #reset-cells = <1>; 319 #interconnect-cells = <1>; 320 }; 321 322 tcsr_mutex: hwlock@1905000 { 323 compatible = "qcom,tcsr-mutex"; 324 reg = <0x01905000 0x20000>; 325 #hwlock-cells = <1>; 326 }; 327 328 tcsr: syscon@1937000 { 329 compatible = "qcom,tcsr-ipq9574", "syscon"; 330 reg = <0x01937000 0x21000>; 331 }; 332 333 sdhc_1: mmc@7804000 { 334 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5"; 335 reg = <0x07804000 0x1000>, 336 <0x07805000 0x1000>, 337 <0x07808000 0x2000>; 338 reg-names = "hc", "cqhci", "ice"; 339 340 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 342 interrupt-names = "hc_irq", "pwr_irq"; 343 344 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 345 <&gcc GCC_SDCC1_APPS_CLK>, 346 <&xo_board_clk>, 347 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 348 clock-names = "iface", "core", "xo", "ice"; 349 non-removable; 350 supports-cqe; 351 status = "disabled"; 352 }; 353 354 blsp_dma: dma-controller@7884000 { 355 compatible = "qcom,bam-v1.7.0"; 356 reg = <0x07884000 0x2b000>; 357 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 358 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 359 clock-names = "bam_clk"; 360 #dma-cells = <1>; 361 qcom,ee = <0>; 362 }; 363 364 blsp1_uart0: serial@78af000 { 365 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 366 reg = <0x078af000 0x200>; 367 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 369 <&gcc GCC_BLSP1_AHB_CLK>; 370 clock-names = "core", "iface"; 371 status = "disabled"; 372 }; 373 374 blsp1_uart1: serial@78b0000 { 375 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 376 reg = <0x078b0000 0x200>; 377 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 379 <&gcc GCC_BLSP1_AHB_CLK>; 380 clock-names = "core", "iface"; 381 status = "disabled"; 382 }; 383 384 blsp1_uart2: serial@78b1000 { 385 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 386 reg = <0x078b1000 0x200>; 387 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 389 <&gcc GCC_BLSP1_AHB_CLK>; 390 clock-names = "core", "iface"; 391 status = "disabled"; 392 }; 393 394 blsp1_uart3: serial@78b2000 { 395 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 396 reg = <0x078b2000 0x200>; 397 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, 399 <&gcc GCC_BLSP1_AHB_CLK>; 400 clock-names = "core", "iface"; 401 status = "disabled"; 402 }; 403 404 blsp1_uart4: serial@78b3000 { 405 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 406 reg = <0x078b3000 0x200>; 407 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 409 <&gcc GCC_BLSP1_AHB_CLK>; 410 clock-names = "core", "iface"; 411 status = "disabled"; 412 }; 413 414 blsp1_uart5: serial@78b4000 { 415 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 416 reg = <0x078b4000 0x200>; 417 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, 419 <&gcc GCC_BLSP1_AHB_CLK>; 420 clock-names = "core", "iface"; 421 status = "disabled"; 422 }; 423 424 blsp1_spi0: spi@78b5000 { 425 compatible = "qcom,spi-qup-v2.2.1"; 426 reg = <0x078b5000 0x600>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 431 <&gcc GCC_BLSP1_AHB_CLK>; 432 clock-names = "core", "iface"; 433 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 434 dma-names = "tx", "rx"; 435 status = "disabled"; 436 }; 437 438 blsp1_i2c1: i2c@78b6000 { 439 compatible = "qcom,i2c-qup-v2.2.1"; 440 reg = <0x078b6000 0x600>; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 445 <&gcc GCC_BLSP1_AHB_CLK>; 446 clock-names = "core", "iface"; 447 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; 448 assigned-clock-rates = <50000000>; 449 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 450 dma-names = "tx", "rx"; 451 status = "disabled"; 452 }; 453 454 blsp1_spi1: spi@78b6000 { 455 compatible = "qcom,spi-qup-v2.2.1"; 456 reg = <0x078b6000 0x600>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 461 <&gcc GCC_BLSP1_AHB_CLK>; 462 clock-names = "core", "iface"; 463 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 464 dma-names = "tx", "rx"; 465 status = "disabled"; 466 }; 467 468 blsp1_i2c2: i2c@78b7000 { 469 compatible = "qcom,i2c-qup-v2.2.1"; 470 reg = <0x078b7000 0x600>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 475 <&gcc GCC_BLSP1_AHB_CLK>; 476 clock-names = "core", "iface"; 477 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; 478 assigned-clock-rates = <50000000>; 479 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 480 dma-names = "tx", "rx"; 481 status = "disabled"; 482 }; 483 484 blsp1_spi2: spi@78b7000 { 485 compatible = "qcom,spi-qup-v2.2.1"; 486 reg = <0x078b7000 0x600>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 491 <&gcc GCC_BLSP1_AHB_CLK>; 492 clock-names = "core", "iface"; 493 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 494 dma-names = "tx", "rx"; 495 status = "disabled"; 496 }; 497 498 blsp1_i2c3: i2c@78b8000 { 499 compatible = "qcom,i2c-qup-v2.2.1"; 500 reg = <0x078b8000 0x600>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 505 <&gcc GCC_BLSP1_AHB_CLK>; 506 clock-names = "core", "iface"; 507 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; 508 assigned-clock-rates = <50000000>; 509 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 510 dma-names = "tx", "rx"; 511 status = "disabled"; 512 }; 513 514 blsp1_spi3: spi@78b8000 { 515 compatible = "qcom,spi-qup-v2.2.1"; 516 reg = <0x078b8000 0x600>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 520 spi-max-frequency = <50000000>; 521 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 522 <&gcc GCC_BLSP1_AHB_CLK>; 523 clock-names = "core", "iface"; 524 dmas = <&blsp_dma 18>, <&blsp_dma 19>; 525 dma-names = "tx", "rx"; 526 status = "disabled"; 527 }; 528 529 blsp1_i2c4: i2c@78b9000 { 530 compatible = "qcom,i2c-qup-v2.2.1"; 531 reg = <0x078b9000 0x600>; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 536 <&gcc GCC_BLSP1_AHB_CLK>; 537 clock-names = "core", "iface"; 538 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; 539 assigned-clock-rates = <50000000>; 540 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 541 dma-names = "tx", "rx"; 542 status = "disabled"; 543 }; 544 545 blsp1_spi4: spi@78b9000 { 546 compatible = "qcom,spi-qup-v2.2.1"; 547 reg = <0x078b9000 0x600>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 552 <&gcc GCC_BLSP1_AHB_CLK>; 553 clock-names = "core", "iface"; 554 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 555 dma-names = "tx", "rx"; 556 status = "disabled"; 557 }; 558 559 usb_0_qusbphy: phy@7b000 { 560 compatible = "qcom,ipq9574-qusb2-phy"; 561 reg = <0x0007b000 0x180>; 562 #phy-cells = <0>; 563 564 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 565 <&xo_board_clk>; 566 clock-names = "cfg_ahb", 567 "ref"; 568 569 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 570 status = "disabled"; 571 }; 572 573 usb_0_qmpphy: phy@7d000 { 574 compatible = "qcom,ipq9574-qmp-usb3-phy"; 575 reg = <0x0007d000 0xa00>; 576 #phy-cells = <0>; 577 578 clocks = <&gcc GCC_USB0_AUX_CLK>, 579 <&xo_board_clk>, 580 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 581 <&gcc GCC_USB0_PIPE_CLK>; 582 clock-names = "aux", 583 "ref", 584 "cfg_ahb", 585 "pipe"; 586 587 resets = <&gcc GCC_USB0_PHY_BCR>, 588 <&gcc GCC_USB3PHY_0_PHY_BCR>; 589 reset-names = "phy", 590 "phy_phy"; 591 592 #clock-cells = <0>; 593 clock-output-names = "usb0_pipe_clk"; 594 595 status = "disabled"; 596 }; 597 598 usb3: usb@8af8800 { 599 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; 600 reg = <0x08af8800 0x400>; 601 #address-cells = <1>; 602 #size-cells = <1>; 603 ranges; 604 605 clocks = <&gcc GCC_SNOC_USB_CLK>, 606 <&gcc GCC_USB0_MASTER_CLK>, 607 <&gcc GCC_ANOC_USB_AXI_CLK>, 608 <&gcc GCC_USB0_SLEEP_CLK>, 609 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 610 611 clock-names = "cfg_noc", 612 "core", 613 "iface", 614 "sleep", 615 "mock_utmi"; 616 617 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, 618 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 619 assigned-clock-rates = <200000000>, 620 <24000000>; 621 622 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 623 interrupt-names = "pwr_event"; 624 625 resets = <&gcc GCC_USB_BCR>; 626 status = "disabled"; 627 628 usb_0_dwc3: usb@8a00000 { 629 compatible = "snps,dwc3"; 630 reg = <0x8a00000 0xcd00>; 631 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 632 clock-names = "ref"; 633 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 634 phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>; 635 phy-names = "usb2-phy", "usb3-phy"; 636 tx-fifo-resize; 637 snps,is-utmi-l1-suspend; 638 snps,hird-threshold = /bits/ 8 <0x0>; 639 snps,dis_u2_susphy_quirk; 640 snps,dis_u3_susphy_quirk; 641 }; 642 }; 643 644 intc: interrupt-controller@b000000 { 645 compatible = "qcom,msm-qgic2"; 646 reg = <0x0b000000 0x1000>, /* GICD */ 647 <0x0b002000 0x2000>, /* GICC */ 648 <0x0b001000 0x1000>, /* GICH */ 649 <0x0b004000 0x2000>; /* GICV */ 650 #address-cells = <1>; 651 #size-cells = <1>; 652 interrupt-controller; 653 #interrupt-cells = <3>; 654 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 655 ranges = <0 0x0b00c000 0x3000>; 656 657 v2m0: v2m@0 { 658 compatible = "arm,gic-v2m-frame"; 659 reg = <0x00000000 0xffd>; 660 msi-controller; 661 }; 662 663 v2m1: v2m@1000 { 664 compatible = "arm,gic-v2m-frame"; 665 reg = <0x00001000 0xffd>; 666 msi-controller; 667 }; 668 669 v2m2: v2m@2000 { 670 compatible = "arm,gic-v2m-frame"; 671 reg = <0x00002000 0xffd>; 672 msi-controller; 673 }; 674 }; 675 676 watchdog: watchdog@b017000 { 677 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt"; 678 reg = <0x0b017000 0x1000>; 679 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 680 clocks = <&sleep_clk>; 681 timeout-sec = <30>; 682 }; 683 684 apcs_glb: mailbox@b111000 { 685 compatible = "qcom,ipq9574-apcs-apps-global", 686 "qcom,ipq6018-apcs-apps-global"; 687 reg = <0x0b111000 0x1000>; 688 #clock-cells = <1>; 689 clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>; 690 clock-names = "pll", "xo", "gpll0"; 691 #mbox-cells = <1>; 692 }; 693 694 a73pll: clock@b116000 { 695 compatible = "qcom,ipq9574-a73pll"; 696 reg = <0x0b116000 0x40>; 697 #clock-cells = <0>; 698 clocks = <&xo_board_clk>; 699 clock-names = "xo"; 700 }; 701 702 timer@b120000 { 703 compatible = "arm,armv7-timer-mem"; 704 reg = <0x0b120000 0x1000>; 705 #address-cells = <1>; 706 #size-cells = <1>; 707 ranges; 708 709 frame@b120000 { 710 reg = <0x0b121000 0x1000>, 711 <0x0b122000 0x1000>; 712 frame-number = <0>; 713 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 715 }; 716 717 frame@b123000 { 718 reg = <0x0b123000 0x1000>; 719 frame-number = <1>; 720 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 721 status = "disabled"; 722 }; 723 724 frame@b124000 { 725 reg = <0x0b124000 0x1000>; 726 frame-number = <2>; 727 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 728 status = "disabled"; 729 }; 730 731 frame@b125000 { 732 reg = <0x0b125000 0x1000>; 733 frame-number = <3>; 734 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 735 status = "disabled"; 736 }; 737 738 frame@b126000 { 739 reg = <0x0b126000 0x1000>; 740 frame-number = <4>; 741 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 742 status = "disabled"; 743 }; 744 745 frame@b127000 { 746 reg = <0x0b127000 0x1000>; 747 frame-number = <5>; 748 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 749 status = "disabled"; 750 }; 751 752 frame@b128000 { 753 reg = <0x0b128000 0x1000>; 754 frame-number = <6>; 755 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 756 status = "disabled"; 757 }; 758 }; 759 }; 760 761 thermal-zones { 762 nss-top-thermal { 763 thermal-sensors = <&tsens 3>; 764 765 trips { 766 nss-top-critical { 767 temperature = <125000>; 768 hysteresis = <1000>; 769 type = "critical"; 770 }; 771 }; 772 }; 773 774 ubi-0-thermal { 775 thermal-sensors = <&tsens 4>; 776 777 trips { 778 ubi_0-critical { 779 temperature = <125000>; 780 hysteresis = <1000>; 781 type = "critical"; 782 }; 783 }; 784 }; 785 786 ubi-1-thermal { 787 thermal-sensors = <&tsens 5>; 788 789 trips { 790 ubi_1-critical { 791 temperature = <125000>; 792 hysteresis = <1000>; 793 type = "critical"; 794 }; 795 }; 796 }; 797 798 ubi-2-thermal { 799 thermal-sensors = <&tsens 6>; 800 801 trips { 802 ubi_2-critical { 803 temperature = <125000>; 804 hysteresis = <1000>; 805 type = "critical"; 806 }; 807 }; 808 }; 809 810 ubi-3-thermal { 811 thermal-sensors = <&tsens 7>; 812 813 trips { 814 ubi_3-critical { 815 temperature = <125000>; 816 hysteresis = <1000>; 817 type = "critical"; 818 }; 819 }; 820 }; 821 822 cpuss0-thermal { 823 thermal-sensors = <&tsens 8>; 824 825 trips { 826 cpu-critical { 827 temperature = <125000>; 828 hysteresis = <1000>; 829 type = "critical"; 830 }; 831 }; 832 }; 833 834 cpuss1-thermal { 835 thermal-sensors = <&tsens 9>; 836 837 trips { 838 cpu-critical { 839 temperature = <125000>; 840 hysteresis = <1000>; 841 type = "critical"; 842 }; 843 }; 844 }; 845 846 cpu0-thermal { 847 thermal-sensors = <&tsens 10>; 848 849 trips { 850 cpu0_crit: cpu-critical { 851 temperature = <120000>; 852 hysteresis = <10000>; 853 type = "critical"; 854 }; 855 856 cpu0_alert: cpu-passive { 857 temperature = <110000>; 858 hysteresis = <1000>; 859 type = "passive"; 860 }; 861 }; 862 863 cooling-maps { 864 map0 { 865 trip = <&cpu0_alert>; 866 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 867 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 868 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 869 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 870 }; 871 }; 872 }; 873 874 cpu1-thermal { 875 thermal-sensors = <&tsens 11>; 876 877 trips { 878 cpu1_crit: cpu-critical { 879 temperature = <120000>; 880 hysteresis = <10000>; 881 type = "critical"; 882 }; 883 884 cpu1_alert: cpu-passive { 885 temperature = <110000>; 886 hysteresis = <1000>; 887 type = "passive"; 888 }; 889 }; 890 891 cooling-maps { 892 map0 { 893 trip = <&cpu1_alert>; 894 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 895 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 896 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 897 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 898 }; 899 }; 900 }; 901 902 cpu2-thermal { 903 thermal-sensors = <&tsens 12>; 904 905 trips { 906 cpu2_crit: cpu-critical { 907 temperature = <120000>; 908 hysteresis = <10000>; 909 type = "critical"; 910 }; 911 912 cpu2_alert: cpu-passive { 913 temperature = <110000>; 914 hysteresis = <1000>; 915 type = "passive"; 916 }; 917 }; 918 919 cooling-maps { 920 map0 { 921 trip = <&cpu2_alert>; 922 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 923 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 924 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 925 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 926 }; 927 }; 928 }; 929 930 cpu3-thermal { 931 thermal-sensors = <&tsens 13>; 932 933 trips { 934 cpu3_crit: cpu-critical { 935 temperature = <120000>; 936 hysteresis = <10000>; 937 type = "critical"; 938 }; 939 940 cpu3_alert: cpu-passive { 941 temperature = <110000>; 942 hysteresis = <1000>; 943 type = "passive"; 944 }; 945 }; 946 947 cooling-maps { 948 map0 { 949 trip = <&cpu3_alert>; 950 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 951 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 952 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 953 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 954 }; 955 }; 956 }; 957 958 wcss-phyb-thermal { 959 thermal-sensors = <&tsens 14>; 960 961 trips { 962 wcss_phyb-critical { 963 temperature = <125000>; 964 hysteresis = <1000>; 965 type = "critical"; 966 }; 967 }; 968 }; 969 970 top-glue-thermal { 971 thermal-sensors = <&tsens 15>; 972 973 trips { 974 top_glue-critical { 975 temperature = <125000>; 976 hysteresis = <1000>; 977 type = "critical"; 978 }; 979 }; 980 }; 981 }; 982 983 timer { 984 compatible = "arm,armv8-timer"; 985 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 986 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 987 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 988 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 989 }; 990}; 991