1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 model = "Qualcomm Technologies, Inc. IPQ8074"; 14 compatible = "qcom,ipq8074"; 15 interrupt-parent = <&intc>; 16 17 clocks { 18 sleep_clk: sleep_clk { 19 compatible = "fixed-clock"; 20 clock-frequency = <32768>; 21 #clock-cells = <0>; 22 }; 23 24 xo: xo { 25 compatible = "fixed-clock"; 26 clock-frequency = <19200000>; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 CPU0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0>; 39 next-level-cache = <&L2_0>; 40 enable-method = "psci"; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 enable-method = "psci"; 47 reg = <0x1>; 48 next-level-cache = <&L2_0>; 49 }; 50 51 CPU2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 enable-method = "psci"; 55 reg = <0x2>; 56 next-level-cache = <&L2_0>; 57 }; 58 59 CPU3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 enable-method = "psci"; 63 reg = <0x3>; 64 next-level-cache = <&L2_0>; 65 }; 66 67 L2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <2>; 70 cache-unified; 71 }; 72 }; 73 74 pmu { 75 compatible = "arm,cortex-a53-pmu"; 76 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 77 }; 78 79 psci { 80 compatible = "arm,psci-1.0"; 81 method = "smc"; 82 }; 83 84 reserved-memory { 85 #address-cells = <2>; 86 #size-cells = <2>; 87 ranges; 88 89 bootloader@4a600000 { 90 reg = <0x0 0x4a600000 0x0 0x400000>; 91 no-map; 92 }; 93 94 sbl@4aa00000 { 95 reg = <0x0 0x4aa00000 0x0 0x100000>; 96 no-map; 97 }; 98 99 smem@4ab00000 { 100 compatible = "qcom,smem"; 101 reg = <0x0 0x4ab00000 0x0 0x100000>; 102 no-map; 103 104 hwlocks = <&tcsr_mutex 0>; 105 }; 106 107 memory@4ac00000 { 108 reg = <0x0 0x4ac00000 0x0 0x400000>; 109 no-map; 110 }; 111 }; 112 113 firmware { 114 scm { 115 compatible = "qcom,scm-ipq8074", "qcom,scm"; 116 qcom,dload-mode = <&tcsr 0x6100>; 117 }; 118 }; 119 120 soc: soc@0 { 121 #address-cells = <1>; 122 #size-cells = <1>; 123 ranges = <0 0 0 0xffffffff>; 124 compatible = "simple-bus"; 125 126 ssphy_1: phy@58000 { 127 compatible = "qcom,ipq8074-qmp-usb3-phy"; 128 reg = <0x00058000 0x1c4>; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 ranges; 132 133 clocks = <&gcc GCC_USB1_AUX_CLK>, 134 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 135 <&xo>; 136 clock-names = "aux", "cfg_ahb", "ref"; 137 138 resets = <&gcc GCC_USB1_PHY_BCR>, 139 <&gcc GCC_USB3PHY_1_PHY_BCR>; 140 reset-names = "phy","common"; 141 status = "disabled"; 142 143 usb1_ssphy: phy@58200 { 144 reg = <0x00058200 0x130>, /* Tx */ 145 <0x00058400 0x200>, /* Rx */ 146 <0x00058800 0x1f8>, /* PCS */ 147 <0x00058600 0x044>; /* PCS misc */ 148 #phy-cells = <0>; 149 #clock-cells = <0>; 150 clocks = <&gcc GCC_USB1_PIPE_CLK>; 151 clock-names = "pipe0"; 152 clock-output-names = "usb3phy_1_cc_pipe_clk"; 153 }; 154 }; 155 156 qusb_phy_1: phy@59000 { 157 compatible = "qcom,ipq8074-qusb2-phy"; 158 reg = <0x00059000 0x180>; 159 #phy-cells = <0>; 160 161 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 162 <&xo>; 163 clock-names = "cfg_ahb", "ref"; 164 165 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 166 status = "disabled"; 167 }; 168 169 ssphy_0: phy@78000 { 170 compatible = "qcom,ipq8074-qmp-usb3-phy"; 171 reg = <0x00078000 0x1c4>; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 ranges; 175 176 clocks = <&gcc GCC_USB0_AUX_CLK>, 177 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 178 <&xo>; 179 clock-names = "aux", "cfg_ahb", "ref"; 180 181 resets = <&gcc GCC_USB0_PHY_BCR>, 182 <&gcc GCC_USB3PHY_0_PHY_BCR>; 183 reset-names = "phy","common"; 184 status = "disabled"; 185 186 usb0_ssphy: phy@78200 { 187 reg = <0x00078200 0x130>, /* Tx */ 188 <0x00078400 0x200>, /* Rx */ 189 <0x00078800 0x1f8>, /* PCS */ 190 <0x00078600 0x044>; /* PCS misc */ 191 #phy-cells = <0>; 192 #clock-cells = <0>; 193 clocks = <&gcc GCC_USB0_PIPE_CLK>; 194 clock-names = "pipe0"; 195 clock-output-names = "usb3phy_0_cc_pipe_clk"; 196 }; 197 }; 198 199 qusb_phy_0: phy@79000 { 200 compatible = "qcom,ipq8074-qusb2-phy"; 201 reg = <0x00079000 0x180>; 202 #phy-cells = <0>; 203 204 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 205 <&xo>; 206 clock-names = "cfg_ahb", "ref"; 207 208 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 209 status = "disabled"; 210 }; 211 212 pcie_qmp0: phy@84000 { 213 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; 214 reg = <0x00084000 0x1bc>; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges; 218 219 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 220 <&gcc GCC_PCIE0_AHB_CLK>; 221 clock-names = "aux", "cfg_ahb"; 222 resets = <&gcc GCC_PCIE0_PHY_BCR>, 223 <&gcc GCC_PCIE0PHY_PHY_BCR>; 224 reset-names = "phy", 225 "common"; 226 status = "disabled"; 227 228 pcie_phy0: phy@84200 { 229 reg = <0x84200 0x16c>, 230 <0x84400 0x200>, 231 <0x84800 0x1f0>, 232 <0x84c00 0xf4>; 233 #phy-cells = <0>; 234 #clock-cells = <0>; 235 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 236 clock-names = "pipe0"; 237 clock-output-names = "pcie20_phy0_pipe_clk"; 238 }; 239 }; 240 241 pcie_qmp1: phy@8e000 { 242 compatible = "qcom,ipq8074-qmp-pcie-phy"; 243 reg = <0x0008e000 0x1c4>; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 ranges; 247 248 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 249 <&gcc GCC_PCIE1_AHB_CLK>; 250 clock-names = "aux", "cfg_ahb"; 251 resets = <&gcc GCC_PCIE1_PHY_BCR>, 252 <&gcc GCC_PCIE1PHY_PHY_BCR>; 253 reset-names = "phy", 254 "common"; 255 status = "disabled"; 256 257 pcie_phy1: phy@8e200 { 258 reg = <0x8e200 0x130>, 259 <0x8e400 0x200>, 260 <0x8e800 0x1f8>; 261 #phy-cells = <0>; 262 #clock-cells = <0>; 263 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 264 clock-names = "pipe0"; 265 clock-output-names = "pcie20_phy1_pipe_clk"; 266 }; 267 }; 268 269 mdio: mdio@90000 { 270 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio"; 271 reg = <0x00090000 0x64>; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 275 clocks = <&gcc GCC_MDIO_AHB_CLK>; 276 clock-names = "gcc_mdio_ahb_clk"; 277 278 status = "disabled"; 279 }; 280 281 qfprom: efuse@a4000 { 282 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom"; 283 reg = <0x000a4000 0x2000>; 284 #address-cells = <1>; 285 #size-cells = <1>; 286 }; 287 288 prng: rng@e3000 { 289 compatible = "qcom,prng-ee"; 290 reg = <0x000e3000 0x1000>; 291 clocks = <&gcc GCC_PRNG_AHB_CLK>; 292 clock-names = "core"; 293 status = "disabled"; 294 }; 295 296 tsens: thermal-sensor@4a9000 { 297 compatible = "qcom,ipq8074-tsens"; 298 reg = <0x4a9000 0x1000>, /* TM */ 299 <0x4a8000 0x1000>; /* SROT */ 300 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 301 interrupt-names = "combined"; 302 #qcom,sensors = <16>; 303 #thermal-sensor-cells = <1>; 304 }; 305 306 cryptobam: dma-controller@704000 { 307 compatible = "qcom,bam-v1.7.0"; 308 reg = <0x00704000 0x20000>; 309 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 311 clock-names = "bam_clk"; 312 #dma-cells = <1>; 313 qcom,ee = <1>; 314 qcom,controlled-remotely; 315 status = "disabled"; 316 }; 317 318 crypto: crypto@73a000 { 319 compatible = "qcom,crypto-v5.1"; 320 reg = <0x0073a000 0x6000>; 321 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 322 <&gcc GCC_CRYPTO_AXI_CLK>, 323 <&gcc GCC_CRYPTO_CLK>; 324 clock-names = "iface", "bus", "core"; 325 dmas = <&cryptobam 2>, <&cryptobam 3>; 326 dma-names = "rx", "tx"; 327 status = "disabled"; 328 }; 329 330 tlmm: pinctrl@1000000 { 331 compatible = "qcom,ipq8074-pinctrl"; 332 reg = <0x01000000 0x300000>; 333 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 334 gpio-controller; 335 gpio-ranges = <&tlmm 0 0 70>; 336 #gpio-cells = <2>; 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 340 serial_4_pins: serial4-state { 341 pins = "gpio23", "gpio24"; 342 function = "blsp4_uart1"; 343 drive-strength = <8>; 344 bias-disable; 345 }; 346 347 i2c_0_pins: i2c-0-state { 348 pins = "gpio42", "gpio43"; 349 function = "blsp1_i2c"; 350 drive-strength = <8>; 351 bias-disable; 352 }; 353 354 spi_0_pins: spi-0-state { 355 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 356 function = "blsp0_spi"; 357 drive-strength = <8>; 358 bias-disable; 359 }; 360 361 hsuart_pins: hsuart-state { 362 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 363 function = "blsp2_uart"; 364 drive-strength = <8>; 365 bias-disable; 366 }; 367 368 qpic_pins: qpic-state { 369 pins = "gpio1", "gpio3", "gpio4", 370 "gpio5", "gpio6", "gpio7", 371 "gpio8", "gpio10", "gpio11", 372 "gpio12", "gpio13", "gpio14", 373 "gpio15", "gpio16", "gpio17"; 374 function = "qpic"; 375 drive-strength = <8>; 376 bias-disable; 377 }; 378 }; 379 380 gcc: gcc@1800000 { 381 compatible = "qcom,gcc-ipq8074"; 382 reg = <0x01800000 0x80000>; 383 clocks = <&xo>, <&sleep_clk>; 384 clock-names = "xo", "sleep_clk"; 385 #clock-cells = <1>; 386 #power-domain-cells = <1>; 387 #reset-cells = <1>; 388 }; 389 390 tcsr_mutex: hwlock@1905000 { 391 compatible = "qcom,tcsr-mutex"; 392 reg = <0x01905000 0x20000>; 393 #hwlock-cells = <1>; 394 }; 395 396 tcsr: syscon@1937000 { 397 compatible = "qcom,tcsr-ipq8074", "syscon"; 398 reg = <0x01937000 0x21000>; 399 }; 400 401 spmi_bus: spmi@200f000 { 402 compatible = "qcom,spmi-pmic-arb"; 403 reg = <0x0200f000 0x001000>, 404 <0x02400000 0x800000>, 405 <0x02c00000 0x800000>, 406 <0x03800000 0x200000>, 407 <0x0200a000 0x000700>; 408 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 409 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 410 interrupt-names = "periph_irq"; 411 qcom,ee = <0>; 412 qcom,channel = <0>; 413 #address-cells = <2>; 414 #size-cells = <0>; 415 interrupt-controller; 416 #interrupt-cells = <4>; 417 }; 418 419 sdhc_1: mmc@7824900 { 420 compatible = "qcom,sdhci-msm-v4"; 421 reg = <0x7824900 0x500>, <0x7824000 0x800>; 422 reg-names = "hc", "core"; 423 424 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 426 interrupt-names = "hc_irq", "pwr_irq"; 427 428 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 429 <&gcc GCC_SDCC1_APPS_CLK>, 430 <&xo>; 431 clock-names = "iface", "core", "xo"; 432 resets = <&gcc GCC_SDCC1_BCR>; 433 max-frequency = <384000000>; 434 mmc-ddr-1_8v; 435 mmc-hs200-1_8v; 436 mmc-hs400-1_8v; 437 bus-width = <8>; 438 439 status = "disabled"; 440 }; 441 442 blsp_dma: dma-controller@7884000 { 443 compatible = "qcom,bam-v1.7.0"; 444 reg = <0x07884000 0x2b000>; 445 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 447 clock-names = "bam_clk"; 448 #dma-cells = <1>; 449 qcom,ee = <0>; 450 }; 451 452 blsp1_uart1: serial@78af000 { 453 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 454 reg = <0x078af000 0x200>; 455 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 457 <&gcc GCC_BLSP1_AHB_CLK>; 458 clock-names = "core", "iface"; 459 status = "disabled"; 460 }; 461 462 blsp1_uart3: serial@78b1000 { 463 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 464 reg = <0x078b1000 0x200>; 465 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 467 <&gcc GCC_BLSP1_AHB_CLK>; 468 clock-names = "core", "iface"; 469 dmas = <&blsp_dma 4>, 470 <&blsp_dma 5>; 471 dma-names = "tx", "rx"; 472 pinctrl-0 = <&hsuart_pins>; 473 pinctrl-names = "default"; 474 status = "disabled"; 475 }; 476 477 blsp1_uart5: serial@78b3000 { 478 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 479 reg = <0x078b3000 0x200>; 480 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 482 <&gcc GCC_BLSP1_AHB_CLK>; 483 clock-names = "core", "iface"; 484 pinctrl-0 = <&serial_4_pins>; 485 pinctrl-names = "default"; 486 status = "disabled"; 487 }; 488 489 blsp1_spi1: spi@78b5000 { 490 compatible = "qcom,spi-qup-v2.2.1"; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 reg = <0x078b5000 0x600>; 494 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 496 <&gcc GCC_BLSP1_AHB_CLK>; 497 clock-names = "core", "iface"; 498 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 499 dma-names = "tx", "rx"; 500 pinctrl-0 = <&spi_0_pins>; 501 pinctrl-names = "default"; 502 status = "disabled"; 503 }; 504 505 blsp1_i2c2: i2c@78b6000 { 506 compatible = "qcom,i2c-qup-v2.2.1"; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 reg = <0x078b6000 0x600>; 510 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 512 <&gcc GCC_BLSP1_AHB_CLK>; 513 clock-names = "core", "iface"; 514 clock-frequency = <400000>; 515 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 516 dma-names = "tx", "rx"; 517 pinctrl-0 = <&i2c_0_pins>; 518 pinctrl-names = "default"; 519 status = "disabled"; 520 }; 521 522 blsp1_i2c3: i2c@78b7000 { 523 compatible = "qcom,i2c-qup-v2.2.1"; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 reg = <0x078b7000 0x600>; 527 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 529 <&gcc GCC_BLSP1_AHB_CLK>; 530 clock-names = "core", "iface"; 531 clock-frequency = <100000>; 532 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 533 dma-names = "tx", "rx"; 534 status = "disabled"; 535 }; 536 537 blsp1_i2c5: i2c@78b9000 { 538 compatible = "qcom,i2c-qup-v2.2.1"; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 reg = <0x78b9000 0x600>; 542 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 544 <&gcc GCC_BLSP1_AHB_CLK>; 545 clock-names = "core", "iface"; 546 clock-frequency = <400000>; 547 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 548 dma-names = "tx", "rx"; 549 status = "disabled"; 550 }; 551 552 blsp1_spi5: spi@78b9000 { 553 compatible = "qcom,spi-qup-v2.2.1"; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 reg = <0x78b9000 0x600>; 557 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 559 <&gcc GCC_BLSP1_AHB_CLK>; 560 clock-names = "core", "iface"; 561 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 562 dma-names = "tx", "rx"; 563 status = "disabled"; 564 }; 565 566 blsp1_i2c6: i2c@78ba000 { 567 compatible = "qcom,i2c-qup-v2.2.1"; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 reg = <0x078ba000 0x600>; 571 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 573 <&gcc GCC_BLSP1_AHB_CLK>; 574 clock-names = "core", "iface"; 575 clock-frequency = <100000>; 576 dmas = <&blsp_dma 22>, <&blsp_dma 23>; 577 dma-names = "tx", "rx"; 578 status = "disabled"; 579 }; 580 581 qpic_bam: dma-controller@7984000 { 582 compatible = "qcom,bam-v1.7.0"; 583 reg = <0x07984000 0x1a000>; 584 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&gcc GCC_QPIC_AHB_CLK>; 586 clock-names = "bam_clk"; 587 #dma-cells = <1>; 588 qcom,ee = <0>; 589 status = "disabled"; 590 }; 591 592 qpic_nand: nand-controller@79b0000 { 593 compatible = "qcom,ipq8074-nand"; 594 reg = <0x079b0000 0x10000>; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 clocks = <&gcc GCC_QPIC_CLK>, 598 <&gcc GCC_QPIC_AHB_CLK>; 599 clock-names = "core", "aon"; 600 601 dmas = <&qpic_bam 0>, 602 <&qpic_bam 1>, 603 <&qpic_bam 2>; 604 dma-names = "tx", "rx", "cmd"; 605 pinctrl-0 = <&qpic_pins>; 606 pinctrl-names = "default"; 607 status = "disabled"; 608 }; 609 610 usb_0: usb@8af8800 { 611 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 612 reg = <0x08af8800 0x400>; 613 #address-cells = <1>; 614 #size-cells = <1>; 615 ranges; 616 617 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 618 <&gcc GCC_USB0_MASTER_CLK>, 619 <&gcc GCC_USB0_SLEEP_CLK>, 620 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 621 clock-names = "cfg_noc", 622 "core", 623 "sleep", 624 "mock_utmi"; 625 626 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 627 <&gcc GCC_USB0_MASTER_CLK>, 628 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 629 assigned-clock-rates = <133330000>, 630 <133330000>, 631 <19200000>; 632 633 power-domains = <&gcc USB0_GDSC>; 634 635 resets = <&gcc GCC_USB0_BCR>; 636 status = "disabled"; 637 638 dwc_0: usb@8a00000 { 639 compatible = "snps,dwc3"; 640 reg = <0x8a00000 0xcd00>; 641 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 642 phys = <&qusb_phy_0>, <&usb0_ssphy>; 643 phy-names = "usb2-phy", "usb3-phy"; 644 snps,is-utmi-l1-suspend; 645 snps,hird-threshold = /bits/ 8 <0x0>; 646 snps,dis_u2_susphy_quirk; 647 snps,dis_u3_susphy_quirk; 648 dr_mode = "host"; 649 }; 650 }; 651 652 usb_1: usb@8cf8800 { 653 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 654 reg = <0x08cf8800 0x400>; 655 #address-cells = <1>; 656 #size-cells = <1>; 657 ranges; 658 659 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 660 <&gcc GCC_USB1_MASTER_CLK>, 661 <&gcc GCC_USB1_SLEEP_CLK>, 662 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 663 clock-names = "cfg_noc", 664 "core", 665 "sleep", 666 "mock_utmi"; 667 668 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 669 <&gcc GCC_USB1_MASTER_CLK>, 670 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 671 assigned-clock-rates = <133330000>, 672 <133330000>, 673 <19200000>; 674 675 power-domains = <&gcc USB1_GDSC>; 676 677 resets = <&gcc GCC_USB1_BCR>; 678 status = "disabled"; 679 680 dwc_1: usb@8c00000 { 681 compatible = "snps,dwc3"; 682 reg = <0x8c00000 0xcd00>; 683 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 684 phys = <&qusb_phy_1>, <&usb1_ssphy>; 685 phy-names = "usb2-phy", "usb3-phy"; 686 snps,is-utmi-l1-suspend; 687 snps,hird-threshold = /bits/ 8 <0x0>; 688 snps,dis_u2_susphy_quirk; 689 snps,dis_u3_susphy_quirk; 690 dr_mode = "host"; 691 }; 692 }; 693 694 intc: interrupt-controller@b000000 { 695 compatible = "qcom,msm-qgic2"; 696 #address-cells = <1>; 697 #size-cells = <1>; 698 interrupt-controller; 699 #interrupt-cells = <3>; 700 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 701 ranges = <0 0xb00a000 0xffd>; 702 703 v2m@0 { 704 compatible = "arm,gic-v2m-frame"; 705 msi-controller; 706 reg = <0x0 0xffd>; 707 }; 708 }; 709 710 watchdog: watchdog@b017000 { 711 compatible = "qcom,kpss-wdt"; 712 reg = <0xb017000 0x1000>; 713 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 714 clocks = <&sleep_clk>; 715 timeout-sec = <30>; 716 }; 717 718 apcs_glb: mailbox@b111000 { 719 compatible = "qcom,ipq8074-apcs-apps-global", 720 "qcom,ipq6018-apcs-apps-global"; 721 reg = <0x0b111000 0x1000>; 722 clocks = <&a53pll>, <&xo>; 723 clock-names = "pll", "xo"; 724 725 #clock-cells = <1>; 726 #mbox-cells = <1>; 727 }; 728 729 a53pll: clock@b116000 { 730 compatible = "qcom,ipq8074-a53pll"; 731 reg = <0x0b116000 0x40>; 732 #clock-cells = <0>; 733 clocks = <&xo>; 734 clock-names = "xo"; 735 }; 736 737 timer@b120000 { 738 #address-cells = <1>; 739 #size-cells = <1>; 740 ranges; 741 compatible = "arm,armv7-timer-mem"; 742 reg = <0x0b120000 0x1000>; 743 744 frame@b120000 { 745 frame-number = <0>; 746 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 748 reg = <0x0b121000 0x1000>, 749 <0x0b122000 0x1000>; 750 }; 751 752 frame@b123000 { 753 frame-number = <1>; 754 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 755 reg = <0x0b123000 0x1000>; 756 status = "disabled"; 757 }; 758 759 frame@b124000 { 760 frame-number = <2>; 761 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 762 reg = <0x0b124000 0x1000>; 763 status = "disabled"; 764 }; 765 766 frame@b125000 { 767 frame-number = <3>; 768 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 769 reg = <0x0b125000 0x1000>; 770 status = "disabled"; 771 }; 772 773 frame@b126000 { 774 frame-number = <4>; 775 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 776 reg = <0x0b126000 0x1000>; 777 status = "disabled"; 778 }; 779 780 frame@b127000 { 781 frame-number = <5>; 782 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 783 reg = <0x0b127000 0x1000>; 784 status = "disabled"; 785 }; 786 787 frame@b128000 { 788 frame-number = <6>; 789 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 790 reg = <0x0b128000 0x1000>; 791 status = "disabled"; 792 }; 793 }; 794 795 pcie1: pci@10000000 { 796 compatible = "qcom,pcie-ipq8074"; 797 reg = <0x10000000 0xf1d>, 798 <0x10000f20 0xa8>, 799 <0x00088000 0x2000>, 800 <0x10100000 0x1000>; 801 reg-names = "dbi", "elbi", "parf", "config"; 802 device_type = "pci"; 803 linux,pci-domain = <1>; 804 bus-range = <0x00 0xff>; 805 num-lanes = <1>; 806 max-link-speed = <2>; 807 #address-cells = <3>; 808 #size-cells = <2>; 809 810 phys = <&pcie_phy1>; 811 phy-names = "pciephy"; 812 813 ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ 814 <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ 815 816 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 817 interrupt-names = "msi"; 818 #interrupt-cells = <1>; 819 interrupt-map-mask = <0 0 0 0x7>; 820 interrupt-map = <0 0 0 1 &intc 0 142 821 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 822 <0 0 0 2 &intc 0 143 823 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 824 <0 0 0 3 &intc 0 144 825 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 826 <0 0 0 4 &intc 0 145 827 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 828 829 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 830 <&gcc GCC_PCIE1_AXI_M_CLK>, 831 <&gcc GCC_PCIE1_AXI_S_CLK>, 832 <&gcc GCC_PCIE1_AHB_CLK>, 833 <&gcc GCC_PCIE1_AUX_CLK>; 834 clock-names = "iface", 835 "axi_m", 836 "axi_s", 837 "ahb", 838 "aux"; 839 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 840 <&gcc GCC_PCIE1_SLEEP_ARES>, 841 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 842 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 843 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 844 <&gcc GCC_PCIE1_AHB_ARES>, 845 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 846 reset-names = "pipe", 847 "sleep", 848 "sticky", 849 "axi_m", 850 "axi_s", 851 "ahb", 852 "axi_m_sticky"; 853 status = "disabled"; 854 }; 855 856 pcie0: pci@20000000 { 857 compatible = "qcom,pcie-ipq8074-gen3"; 858 reg = <0x20000000 0xf1d>, 859 <0x20000f20 0xa8>, 860 <0x20001000 0x1000>, 861 <0x00080000 0x4000>, 862 <0x20100000 0x1000>; 863 reg-names = "dbi", "elbi", "atu", "parf", "config"; 864 device_type = "pci"; 865 linux,pci-domain = <0>; 866 bus-range = <0x00 0xff>; 867 num-lanes = <1>; 868 max-link-speed = <3>; 869 #address-cells = <3>; 870 #size-cells = <2>; 871 872 phys = <&pcie_phy0>; 873 phy-names = "pciephy"; 874 875 ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ 876 <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ 877 878 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 879 interrupt-names = "msi"; 880 #interrupt-cells = <1>; 881 interrupt-map-mask = <0 0 0 0x7>; 882 interrupt-map = <0 0 0 1 &intc 0 75 883 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 884 <0 0 0 2 &intc 0 78 885 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 886 <0 0 0 3 &intc 0 79 887 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 888 <0 0 0 4 &intc 0 83 889 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 890 891 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 892 <&gcc GCC_PCIE0_AXI_M_CLK>, 893 <&gcc GCC_PCIE0_AXI_S_CLK>, 894 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 895 <&gcc GCC_PCIE0_RCHNG_CLK>; 896 clock-names = "iface", 897 "axi_m", 898 "axi_s", 899 "axi_bridge", 900 "rchng"; 901 902 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 903 <&gcc GCC_PCIE0_SLEEP_ARES>, 904 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 905 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 906 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 907 <&gcc GCC_PCIE0_AHB_ARES>, 908 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 909 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 910 reset-names = "pipe", 911 "sleep", 912 "sticky", 913 "axi_m", 914 "axi_s", 915 "ahb", 916 "axi_m_sticky", 917 "axi_s_sticky"; 918 status = "disabled"; 919 }; 920 }; 921 922 timer { 923 compatible = "arm,armv8-timer"; 924 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 925 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 926 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 927 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 928 }; 929 930 thermal-zones { 931 nss-top-thermal { 932 polling-delay-passive = <250>; 933 polling-delay = <1000>; 934 935 thermal-sensors = <&tsens 4>; 936 937 trips { 938 nss-top-crit { 939 temperature = <110000>; 940 hysteresis = <1000>; 941 type = "critical"; 942 }; 943 }; 944 }; 945 946 nss0-thermal { 947 polling-delay-passive = <250>; 948 polling-delay = <1000>; 949 950 thermal-sensors = <&tsens 5>; 951 952 trips { 953 nss-0-crit { 954 temperature = <110000>; 955 hysteresis = <1000>; 956 type = "critical"; 957 }; 958 }; 959 }; 960 961 nss1-thermal { 962 polling-delay-passive = <250>; 963 polling-delay = <1000>; 964 965 thermal-sensors = <&tsens 6>; 966 967 trips { 968 nss-1-crit { 969 temperature = <110000>; 970 hysteresis = <1000>; 971 type = "critical"; 972 }; 973 }; 974 }; 975 976 wcss-phya0-thermal { 977 polling-delay-passive = <250>; 978 polling-delay = <1000>; 979 980 thermal-sensors = <&tsens 7>; 981 982 trips { 983 wcss-phya0-crit { 984 temperature = <110000>; 985 hysteresis = <1000>; 986 type = "critical"; 987 }; 988 }; 989 }; 990 991 wcss-phya1-thermal { 992 polling-delay-passive = <250>; 993 polling-delay = <1000>; 994 995 thermal-sensors = <&tsens 8>; 996 997 trips { 998 wcss-phya1-crit { 999 temperature = <110000>; 1000 hysteresis = <1000>; 1001 type = "critical"; 1002 }; 1003 }; 1004 }; 1005 1006 cpu0_thermal: cpu0-thermal { 1007 polling-delay-passive = <250>; 1008 polling-delay = <1000>; 1009 1010 thermal-sensors = <&tsens 9>; 1011 1012 trips { 1013 cpu0-crit { 1014 temperature = <110000>; 1015 hysteresis = <1000>; 1016 type = "critical"; 1017 }; 1018 }; 1019 }; 1020 1021 cpu1_thermal: cpu1-thermal { 1022 polling-delay-passive = <250>; 1023 polling-delay = <1000>; 1024 1025 thermal-sensors = <&tsens 10>; 1026 1027 trips { 1028 cpu1-crit { 1029 temperature = <110000>; 1030 hysteresis = <1000>; 1031 type = "critical"; 1032 }; 1033 }; 1034 }; 1035 1036 cpu2_thermal: cpu2-thermal { 1037 polling-delay-passive = <250>; 1038 polling-delay = <1000>; 1039 1040 thermal-sensors = <&tsens 11>; 1041 1042 trips { 1043 cpu2-crit { 1044 temperature = <110000>; 1045 hysteresis = <1000>; 1046 type = "critical"; 1047 }; 1048 }; 1049 }; 1050 1051 cpu3_thermal: cpu3-thermal { 1052 polling-delay-passive = <250>; 1053 polling-delay = <1000>; 1054 1055 thermal-sensors = <&tsens 12>; 1056 1057 trips { 1058 cpu3-crit { 1059 temperature = <110000>; 1060 hysteresis = <1000>; 1061 type = "critical"; 1062 }; 1063 }; 1064 }; 1065 1066 cluster_thermal: cluster-thermal { 1067 polling-delay-passive = <250>; 1068 polling-delay = <1000>; 1069 1070 thermal-sensors = <&tsens 13>; 1071 1072 trips { 1073 cluster-crit { 1074 temperature = <110000>; 1075 hysteresis = <1000>; 1076 type = "critical"; 1077 }; 1078 }; 1079 }; 1080 1081 wcss-phyb0-thermal { 1082 polling-delay-passive = <250>; 1083 polling-delay = <1000>; 1084 1085 thermal-sensors = <&tsens 14>; 1086 1087 trips { 1088 wcss-phyb0-crit { 1089 temperature = <110000>; 1090 hysteresis = <1000>; 1091 type = "critical"; 1092 }; 1093 }; 1094 }; 1095 1096 wcss-phyb1-thermal { 1097 polling-delay-passive = <250>; 1098 polling-delay = <1000>; 1099 1100 thermal-sensors = <&tsens 15>; 1101 1102 trips { 1103 wcss-phyb1-crit { 1104 temperature = <110000>; 1105 hysteresis = <1000>; 1106 type = "critical"; 1107 }; 1108 }; 1109 }; 1110 }; 1111}; 1112