1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-ipq8074.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 model = "Qualcomm Technologies, Inc. IPQ8074"; 14 compatible = "qcom,ipq8074"; 15 interrupt-parent = <&intc>; 16 17 clocks { 18 sleep_clk: sleep_clk { 19 compatible = "fixed-clock"; 20 clock-frequency = <32768>; 21 #clock-cells = <0>; 22 }; 23 24 xo: xo { 25 compatible = "fixed-clock"; 26 clock-frequency = <19200000>; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <0x1>; 33 #size-cells = <0x0>; 34 35 CPU0: cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a53"; 38 reg = <0x0>; 39 next-level-cache = <&L2_0>; 40 enable-method = "psci"; 41 }; 42 43 CPU1: cpu@1 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 enable-method = "psci"; 47 reg = <0x1>; 48 next-level-cache = <&L2_0>; 49 }; 50 51 CPU2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 enable-method = "psci"; 55 reg = <0x2>; 56 next-level-cache = <&L2_0>; 57 }; 58 59 CPU3: cpu@3 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 enable-method = "psci"; 63 reg = <0x3>; 64 next-level-cache = <&L2_0>; 65 }; 66 67 L2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <0x2>; 70 }; 71 }; 72 73 pmu { 74 compatible = "arm,cortex-a53-pmu"; 75 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 76 }; 77 78 psci { 79 compatible = "arm,psci-1.0"; 80 method = "smc"; 81 }; 82 83 reserved-memory { 84 #address-cells = <2>; 85 #size-cells = <2>; 86 ranges; 87 88 smem@4ab00000 { 89 compatible = "qcom,smem"; 90 reg = <0x0 0x4ab00000 0x0 0x00100000>; 91 no-map; 92 93 hwlocks = <&tcsr_mutex 0>; 94 }; 95 96 memory@4ac00000 { 97 no-map; 98 reg = <0x0 0x4ac00000 0x0 0x00400000>; 99 }; 100 }; 101 102 firmware { 103 scm { 104 compatible = "qcom,scm-ipq8074", "qcom,scm"; 105 }; 106 }; 107 108 soc: soc { 109 #address-cells = <0x1>; 110 #size-cells = <0x1>; 111 ranges = <0 0 0 0xffffffff>; 112 compatible = "simple-bus"; 113 114 ssphy_1: phy@58000 { 115 compatible = "qcom,ipq8074-qmp-usb3-phy"; 116 reg = <0x00058000 0x1c4>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges; 120 121 clocks = <&gcc GCC_USB1_AUX_CLK>, 122 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 123 <&xo>; 124 clock-names = "aux", "cfg_ahb", "ref"; 125 126 resets = <&gcc GCC_USB1_PHY_BCR>, 127 <&gcc GCC_USB3PHY_1_PHY_BCR>; 128 reset-names = "phy","common"; 129 status = "disabled"; 130 131 usb1_ssphy: phy@58200 { 132 reg = <0x00058200 0x130>, /* Tx */ 133 <0x00058400 0x200>, /* Rx */ 134 <0x00058800 0x1f8>, /* PCS */ 135 <0x00058600 0x044>; /* PCS misc */ 136 #phy-cells = <0>; 137 #clock-cells = <0>; 138 clocks = <&gcc GCC_USB1_PIPE_CLK>; 139 clock-names = "pipe0"; 140 clock-output-names = "usb3phy_1_cc_pipe_clk"; 141 }; 142 }; 143 144 qusb_phy_1: phy@59000 { 145 compatible = "qcom,ipq8074-qusb2-phy"; 146 reg = <0x00059000 0x180>; 147 #phy-cells = <0>; 148 149 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 150 <&xo>; 151 clock-names = "cfg_ahb", "ref"; 152 153 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 154 status = "disabled"; 155 }; 156 157 ssphy_0: phy@78000 { 158 compatible = "qcom,ipq8074-qmp-usb3-phy"; 159 reg = <0x00078000 0x1c4>; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 ranges; 163 164 clocks = <&gcc GCC_USB0_AUX_CLK>, 165 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 166 <&xo>; 167 clock-names = "aux", "cfg_ahb", "ref"; 168 169 resets = <&gcc GCC_USB0_PHY_BCR>, 170 <&gcc GCC_USB3PHY_0_PHY_BCR>; 171 reset-names = "phy","common"; 172 status = "disabled"; 173 174 usb0_ssphy: phy@78200 { 175 reg = <0x00078200 0x130>, /* Tx */ 176 <0x00078400 0x200>, /* Rx */ 177 <0x00078800 0x1f8>, /* PCS */ 178 <0x00078600 0x044>; /* PCS misc */ 179 #phy-cells = <0>; 180 #clock-cells = <0>; 181 clocks = <&gcc GCC_USB0_PIPE_CLK>; 182 clock-names = "pipe0"; 183 clock-output-names = "usb3phy_0_cc_pipe_clk"; 184 }; 185 }; 186 187 qusb_phy_0: phy@79000 { 188 compatible = "qcom,ipq8074-qusb2-phy"; 189 reg = <0x00079000 0x180>; 190 #phy-cells = <0>; 191 192 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 193 <&xo>; 194 clock-names = "cfg_ahb", "ref"; 195 196 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 197 status = "disabled"; 198 }; 199 200 pcie_qmp0: phy@84000 { 201 compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; 202 reg = <0x00084000 0x1bc>; 203 #address-cells = <1>; 204 #size-cells = <1>; 205 ranges; 206 207 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 208 <&gcc GCC_PCIE0_AHB_CLK>; 209 clock-names = "aux", "cfg_ahb"; 210 resets = <&gcc GCC_PCIE0_PHY_BCR>, 211 <&gcc GCC_PCIE0PHY_PHY_BCR>; 212 reset-names = "phy", 213 "common"; 214 status = "disabled"; 215 216 pcie_phy0: phy@84200 { 217 reg = <0x84200 0x16c>, 218 <0x84400 0x200>, 219 <0x84800 0x1f0>, 220 <0x84c00 0xf4>; 221 #phy-cells = <0>; 222 #clock-cells = <0>; 223 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 224 clock-names = "pipe0"; 225 clock-output-names = "pcie20_phy0_pipe_clk"; 226 }; 227 }; 228 229 pcie_qmp1: phy@8e000 { 230 compatible = "qcom,ipq8074-qmp-pcie-phy"; 231 reg = <0x0008e000 0x1c4>; 232 #address-cells = <1>; 233 #size-cells = <1>; 234 ranges; 235 236 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 237 <&gcc GCC_PCIE1_AHB_CLK>; 238 clock-names = "aux", "cfg_ahb"; 239 resets = <&gcc GCC_PCIE1_PHY_BCR>, 240 <&gcc GCC_PCIE1PHY_PHY_BCR>; 241 reset-names = "phy", 242 "common"; 243 status = "disabled"; 244 245 pcie_phy1: phy@8e200 { 246 reg = <0x8e200 0x130>, 247 <0x8e400 0x200>, 248 <0x8e800 0x1f8>; 249 #phy-cells = <0>; 250 #clock-cells = <0>; 251 clocks = <&gcc GCC_PCIE1_PIPE_CLK>; 252 clock-names = "pipe0"; 253 clock-output-names = "pcie20_phy1_pipe_clk"; 254 }; 255 }; 256 257 mdio: mdio@90000 { 258 compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio"; 259 reg = <0x00090000 0x64>; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 263 clocks = <&gcc GCC_MDIO_AHB_CLK>; 264 clock-names = "gcc_mdio_ahb_clk"; 265 266 status = "disabled"; 267 }; 268 269 qfprom: efuse@a4000 { 270 compatible = "qcom,ipq8074-qfprom", "qcom,qfprom"; 271 reg = <0x000a4000 0x2000>; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 }; 275 276 prng: rng@e3000 { 277 compatible = "qcom,prng-ee"; 278 reg = <0x000e3000 0x1000>; 279 clocks = <&gcc GCC_PRNG_AHB_CLK>; 280 clock-names = "core"; 281 status = "disabled"; 282 }; 283 284 tsens: thermal-sensor@4a9000 { 285 compatible = "qcom,ipq8074-tsens"; 286 reg = <0x4a9000 0x1000>, /* TM */ 287 <0x4a8000 0x1000>; /* SROT */ 288 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 289 interrupt-names = "combined"; 290 #qcom,sensors = <16>; 291 #thermal-sensor-cells = <1>; 292 }; 293 294 cryptobam: dma-controller@704000 { 295 compatible = "qcom,bam-v1.7.0"; 296 reg = <0x00704000 0x20000>; 297 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 298 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 299 clock-names = "bam_clk"; 300 #dma-cells = <1>; 301 qcom,ee = <1>; 302 qcom,controlled-remotely; 303 status = "disabled"; 304 }; 305 306 crypto: crypto@73a000 { 307 compatible = "qcom,crypto-v5.1"; 308 reg = <0x0073a000 0x6000>; 309 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 310 <&gcc GCC_CRYPTO_AXI_CLK>, 311 <&gcc GCC_CRYPTO_CLK>; 312 clock-names = "iface", "bus", "core"; 313 dmas = <&cryptobam 2>, <&cryptobam 3>; 314 dma-names = "rx", "tx"; 315 status = "disabled"; 316 }; 317 318 tlmm: pinctrl@1000000 { 319 compatible = "qcom,ipq8074-pinctrl"; 320 reg = <0x01000000 0x300000>; 321 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 322 gpio-controller; 323 gpio-ranges = <&tlmm 0 0 70>; 324 #gpio-cells = <0x2>; 325 interrupt-controller; 326 #interrupt-cells = <0x2>; 327 328 serial_4_pins: serial4-state { 329 pins = "gpio23", "gpio24"; 330 function = "blsp4_uart1"; 331 drive-strength = <8>; 332 bias-disable; 333 }; 334 335 i2c_0_pins: i2c-0-state { 336 pins = "gpio42", "gpio43"; 337 function = "blsp1_i2c"; 338 drive-strength = <8>; 339 bias-disable; 340 }; 341 342 spi_0_pins: spi-0-state { 343 pins = "gpio38", "gpio39", "gpio40", "gpio41"; 344 function = "blsp0_spi"; 345 drive-strength = <8>; 346 bias-disable; 347 }; 348 349 hsuart_pins: hsuart-state { 350 pins = "gpio46", "gpio47", "gpio48", "gpio49"; 351 function = "blsp2_uart"; 352 drive-strength = <8>; 353 bias-disable; 354 }; 355 356 qpic_pins: qpic-state { 357 pins = "gpio1", "gpio3", "gpio4", 358 "gpio5", "gpio6", "gpio7", 359 "gpio8", "gpio10", "gpio11", 360 "gpio12", "gpio13", "gpio14", 361 "gpio15", "gpio16", "gpio17"; 362 function = "qpic"; 363 drive-strength = <8>; 364 bias-disable; 365 }; 366 }; 367 368 gcc: gcc@1800000 { 369 compatible = "qcom,gcc-ipq8074"; 370 reg = <0x01800000 0x80000>; 371 clocks = <&xo>, <&sleep_clk>; 372 clock-names = "xo", "sleep_clk"; 373 #clock-cells = <1>; 374 #power-domain-cells = <1>; 375 #reset-cells = <1>; 376 }; 377 378 tcsr_mutex: hwlock@1905000 { 379 compatible = "qcom,tcsr-mutex"; 380 reg = <0x01905000 0x20000>; 381 #hwlock-cells = <1>; 382 }; 383 384 spmi_bus: spmi@200f000 { 385 compatible = "qcom,spmi-pmic-arb"; 386 reg = <0x0200f000 0x001000>, 387 <0x02400000 0x800000>, 388 <0x02c00000 0x800000>, 389 <0x03800000 0x200000>, 390 <0x0200a000 0x000700>; 391 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 392 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 393 interrupt-names = "periph_irq"; 394 qcom,ee = <0>; 395 qcom,channel = <0>; 396 #address-cells = <2>; 397 #size-cells = <0>; 398 interrupt-controller; 399 #interrupt-cells = <4>; 400 cell-index = <0>; 401 }; 402 403 sdhc_1: mmc@7824900 { 404 compatible = "qcom,sdhci-msm-v4"; 405 reg = <0x7824900 0x500>, <0x7824000 0x800>; 406 reg-names = "hc", "core"; 407 408 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 410 interrupt-names = "hc_irq", "pwr_irq"; 411 412 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 413 <&gcc GCC_SDCC1_APPS_CLK>, 414 <&xo>; 415 clock-names = "iface", "core", "xo"; 416 resets = <&gcc GCC_SDCC1_BCR>; 417 max-frequency = <384000000>; 418 mmc-ddr-1_8v; 419 mmc-hs200-1_8v; 420 mmc-hs400-1_8v; 421 bus-width = <8>; 422 423 status = "disabled"; 424 }; 425 426 blsp_dma: dma-controller@7884000 { 427 compatible = "qcom,bam-v1.7.0"; 428 reg = <0x07884000 0x2b000>; 429 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 431 clock-names = "bam_clk"; 432 #dma-cells = <1>; 433 qcom,ee = <0>; 434 }; 435 436 blsp1_uart1: serial@78af000 { 437 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 438 reg = <0x078af000 0x200>; 439 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 441 <&gcc GCC_BLSP1_AHB_CLK>; 442 clock-names = "core", "iface"; 443 status = "disabled"; 444 }; 445 446 blsp1_uart3: serial@78b1000 { 447 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 448 reg = <0x078b1000 0x200>; 449 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 451 <&gcc GCC_BLSP1_AHB_CLK>; 452 clock-names = "core", "iface"; 453 dmas = <&blsp_dma 4>, 454 <&blsp_dma 5>; 455 dma-names = "tx", "rx"; 456 pinctrl-0 = <&hsuart_pins>; 457 pinctrl-names = "default"; 458 status = "disabled"; 459 }; 460 461 blsp1_uart5: serial@78b3000 { 462 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 463 reg = <0x078b3000 0x200>; 464 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 466 <&gcc GCC_BLSP1_AHB_CLK>; 467 clock-names = "core", "iface"; 468 pinctrl-0 = <&serial_4_pins>; 469 pinctrl-names = "default"; 470 status = "disabled"; 471 }; 472 473 blsp1_spi1: spi@78b5000 { 474 compatible = "qcom,spi-qup-v2.2.1"; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 reg = <0x078b5000 0x600>; 478 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 479 spi-max-frequency = <50000000>; 480 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 481 <&gcc GCC_BLSP1_AHB_CLK>; 482 clock-names = "core", "iface"; 483 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 484 dma-names = "tx", "rx"; 485 pinctrl-0 = <&spi_0_pins>; 486 pinctrl-names = "default"; 487 status = "disabled"; 488 }; 489 490 blsp1_i2c2: i2c@78b6000 { 491 compatible = "qcom,i2c-qup-v2.2.1"; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 reg = <0x078b6000 0x600>; 495 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 497 <&gcc GCC_BLSP1_AHB_CLK>; 498 clock-names = "core", "iface"; 499 clock-frequency = <400000>; 500 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 501 dma-names = "tx", "rx"; 502 pinctrl-0 = <&i2c_0_pins>; 503 pinctrl-names = "default"; 504 status = "disabled"; 505 }; 506 507 blsp1_i2c3: i2c@78b7000 { 508 compatible = "qcom,i2c-qup-v2.2.1"; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 reg = <0x078b7000 0x600>; 512 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 514 <&gcc GCC_BLSP1_AHB_CLK>; 515 clock-names = "core", "iface"; 516 clock-frequency = <100000>; 517 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 518 dma-names = "tx", "rx"; 519 status = "disabled"; 520 }; 521 522 blsp1_i2c5: i2c@78b9000 { 523 compatible = "qcom,i2c-qup-v2.2.1"; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 reg = <0x78b9000 0x600>; 527 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 529 <&gcc GCC_BLSP1_AHB_CLK>; 530 clock-names = "core", "iface"; 531 clock-frequency = <400000>; 532 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 533 dma-names = "tx", "rx"; 534 status = "disabled"; 535 }; 536 537 blsp1_i2c6: i2c@78ba000 { 538 compatible = "qcom,i2c-qup-v2.2.1"; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 reg = <0x078ba000 0x600>; 542 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 544 <&gcc GCC_BLSP1_AHB_CLK>; 545 clock-names = "core", "iface"; 546 clock-frequency = <100000>; 547 dmas = <&blsp_dma 22>, <&blsp_dma 23>; 548 dma-names = "tx", "rx"; 549 status = "disabled"; 550 }; 551 552 qpic_bam: dma-controller@7984000 { 553 compatible = "qcom,bam-v1.7.0"; 554 reg = <0x07984000 0x1a000>; 555 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&gcc GCC_QPIC_AHB_CLK>; 557 clock-names = "bam_clk"; 558 #dma-cells = <1>; 559 qcom,ee = <0>; 560 status = "disabled"; 561 }; 562 563 qpic_nand: nand-controller@79b0000 { 564 compatible = "qcom,ipq8074-nand"; 565 reg = <0x079b0000 0x10000>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 clocks = <&gcc GCC_QPIC_CLK>, 569 <&gcc GCC_QPIC_AHB_CLK>; 570 clock-names = "core", "aon"; 571 572 dmas = <&qpic_bam 0>, 573 <&qpic_bam 1>, 574 <&qpic_bam 2>; 575 dma-names = "tx", "rx", "cmd"; 576 pinctrl-0 = <&qpic_pins>; 577 pinctrl-names = "default"; 578 status = "disabled"; 579 }; 580 581 usb_0: usb@8af8800 { 582 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 583 reg = <0x08af8800 0x400>; 584 #address-cells = <1>; 585 #size-cells = <1>; 586 ranges; 587 588 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 589 <&gcc GCC_USB0_MASTER_CLK>, 590 <&gcc GCC_USB0_SLEEP_CLK>, 591 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 592 clock-names = "cfg_noc", 593 "core", 594 "sleep", 595 "mock_utmi"; 596 597 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 598 <&gcc GCC_USB0_MASTER_CLK>, 599 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 600 assigned-clock-rates = <133330000>, 601 <133330000>, 602 <19200000>; 603 604 power-domains = <&gcc USB0_GDSC>; 605 606 resets = <&gcc GCC_USB0_BCR>; 607 status = "disabled"; 608 609 dwc_0: usb@8a00000 { 610 compatible = "snps,dwc3"; 611 reg = <0x8a00000 0xcd00>; 612 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 613 phys = <&qusb_phy_0>, <&usb0_ssphy>; 614 phy-names = "usb2-phy", "usb3-phy"; 615 snps,is-utmi-l1-suspend; 616 snps,hird-threshold = /bits/ 8 <0x0>; 617 snps,dis_u2_susphy_quirk; 618 snps,dis_u3_susphy_quirk; 619 dr_mode = "host"; 620 }; 621 }; 622 623 usb_1: usb@8cf8800 { 624 compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; 625 reg = <0x08cf8800 0x400>; 626 #address-cells = <1>; 627 #size-cells = <1>; 628 ranges; 629 630 clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 631 <&gcc GCC_USB1_MASTER_CLK>, 632 <&gcc GCC_USB1_SLEEP_CLK>, 633 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 634 clock-names = "cfg_noc", 635 "core", 636 "sleep", 637 "mock_utmi"; 638 639 assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, 640 <&gcc GCC_USB1_MASTER_CLK>, 641 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 642 assigned-clock-rates = <133330000>, 643 <133330000>, 644 <19200000>; 645 646 power-domains = <&gcc USB1_GDSC>; 647 648 resets = <&gcc GCC_USB1_BCR>; 649 status = "disabled"; 650 651 dwc_1: usb@8c00000 { 652 compatible = "snps,dwc3"; 653 reg = <0x8c00000 0xcd00>; 654 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 655 phys = <&qusb_phy_1>, <&usb1_ssphy>; 656 phy-names = "usb2-phy", "usb3-phy"; 657 snps,is-utmi-l1-suspend; 658 snps,hird-threshold = /bits/ 8 <0x0>; 659 snps,dis_u2_susphy_quirk; 660 snps,dis_u3_susphy_quirk; 661 dr_mode = "host"; 662 }; 663 }; 664 665 intc: interrupt-controller@b000000 { 666 compatible = "qcom,msm-qgic2"; 667 #address-cells = <1>; 668 #size-cells = <1>; 669 interrupt-controller; 670 #interrupt-cells = <0x3>; 671 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 672 ranges = <0 0xb00a000 0xffd>; 673 674 v2m@0 { 675 compatible = "arm,gic-v2m-frame"; 676 msi-controller; 677 reg = <0x0 0xffd>; 678 }; 679 }; 680 681 watchdog: watchdog@b017000 { 682 compatible = "qcom,kpss-wdt"; 683 reg = <0xb017000 0x1000>; 684 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 685 clocks = <&sleep_clk>; 686 timeout-sec = <30>; 687 }; 688 689 apcs_glb: mailbox@b111000 { 690 compatible = "qcom,ipq8074-apcs-apps-global"; 691 reg = <0x0b111000 0x1000>; 692 clocks = <&a53pll>, <&xo>; 693 clock-names = "pll", "xo"; 694 695 #clock-cells = <1>; 696 #mbox-cells = <1>; 697 }; 698 699 a53pll: clock@b116000 { 700 compatible = "qcom,ipq8074-a53pll"; 701 reg = <0x0b116000 0x40>; 702 #clock-cells = <0>; 703 clocks = <&xo>; 704 clock-names = "xo"; 705 }; 706 707 timer@b120000 { 708 #address-cells = <1>; 709 #size-cells = <1>; 710 ranges; 711 compatible = "arm,armv7-timer-mem"; 712 reg = <0x0b120000 0x1000>; 713 714 frame@b120000 { 715 frame-number = <0>; 716 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 718 reg = <0x0b121000 0x1000>, 719 <0x0b122000 0x1000>; 720 }; 721 722 frame@b123000 { 723 frame-number = <1>; 724 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 725 reg = <0x0b123000 0x1000>; 726 status = "disabled"; 727 }; 728 729 frame@b124000 { 730 frame-number = <2>; 731 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 732 reg = <0x0b124000 0x1000>; 733 status = "disabled"; 734 }; 735 736 frame@b125000 { 737 frame-number = <3>; 738 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 739 reg = <0x0b125000 0x1000>; 740 status = "disabled"; 741 }; 742 743 frame@b126000 { 744 frame-number = <4>; 745 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 746 reg = <0x0b126000 0x1000>; 747 status = "disabled"; 748 }; 749 750 frame@b127000 { 751 frame-number = <5>; 752 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 753 reg = <0x0b127000 0x1000>; 754 status = "disabled"; 755 }; 756 757 frame@b128000 { 758 frame-number = <6>; 759 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 760 reg = <0x0b128000 0x1000>; 761 status = "disabled"; 762 }; 763 }; 764 765 pcie1: pci@10000000 { 766 compatible = "qcom,pcie-ipq8074"; 767 reg = <0x10000000 0xf1d>, 768 <0x10000f20 0xa8>, 769 <0x00088000 0x2000>, 770 <0x10100000 0x1000>; 771 reg-names = "dbi", "elbi", "parf", "config"; 772 device_type = "pci"; 773 linux,pci-domain = <1>; 774 bus-range = <0x00 0xff>; 775 num-lanes = <1>; 776 max-link-speed = <2>; 777 #address-cells = <3>; 778 #size-cells = <2>; 779 780 phys = <&pcie_phy1>; 781 phy-names = "pciephy"; 782 783 ranges = <0x81000000 0 0x10200000 0x10200000 784 0 0x10000>, /* downstream I/O */ 785 <0x82000000 0 0x10220000 0x10220000 786 0 0xfde0000>; /* non-prefetchable memory */ 787 788 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 789 interrupt-names = "msi"; 790 #interrupt-cells = <1>; 791 interrupt-map-mask = <0 0 0 0x7>; 792 interrupt-map = <0 0 0 1 &intc 0 142 793 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 794 <0 0 0 2 &intc 0 143 795 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 796 <0 0 0 3 &intc 0 144 797 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 798 <0 0 0 4 &intc 0 145 799 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 800 801 clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, 802 <&gcc GCC_PCIE1_AXI_M_CLK>, 803 <&gcc GCC_PCIE1_AXI_S_CLK>, 804 <&gcc GCC_PCIE1_AHB_CLK>, 805 <&gcc GCC_PCIE1_AUX_CLK>; 806 clock-names = "iface", 807 "axi_m", 808 "axi_s", 809 "ahb", 810 "aux"; 811 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 812 <&gcc GCC_PCIE1_SLEEP_ARES>, 813 <&gcc GCC_PCIE1_CORE_STICKY_ARES>, 814 <&gcc GCC_PCIE1_AXI_MASTER_ARES>, 815 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, 816 <&gcc GCC_PCIE1_AHB_ARES>, 817 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; 818 reset-names = "pipe", 819 "sleep", 820 "sticky", 821 "axi_m", 822 "axi_s", 823 "ahb", 824 "axi_m_sticky"; 825 status = "disabled"; 826 }; 827 828 pcie0: pci@20000000 { 829 compatible = "qcom,pcie-ipq8074-gen3"; 830 reg = <0x20000000 0xf1d>, 831 <0x20000f20 0xa8>, 832 <0x20001000 0x1000>, 833 <0x00080000 0x4000>, 834 <0x20100000 0x1000>; 835 reg-names = "dbi", "elbi", "atu", "parf", "config"; 836 device_type = "pci"; 837 linux,pci-domain = <0>; 838 bus-range = <0x00 0xff>; 839 num-lanes = <1>; 840 max-link-speed = <3>; 841 #address-cells = <3>; 842 #size-cells = <2>; 843 844 phys = <&pcie_phy0>; 845 phy-names = "pciephy"; 846 847 ranges = <0x81000000 0 0x20200000 0x20200000 848 0 0x10000>, /* downstream I/O */ 849 <0x82000000 0 0x20220000 0x20220000 850 0 0xfde0000>; /* non-prefetchable memory */ 851 852 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 853 interrupt-names = "msi"; 854 #interrupt-cells = <1>; 855 interrupt-map-mask = <0 0 0 0x7>; 856 interrupt-map = <0 0 0 1 &intc 0 75 857 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 858 <0 0 0 2 &intc 0 78 859 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 860 <0 0 0 3 &intc 0 79 861 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 862 <0 0 0 4 &intc 0 83 863 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 864 865 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 866 <&gcc GCC_PCIE0_AXI_M_CLK>, 867 <&gcc GCC_PCIE0_AXI_S_CLK>, 868 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 869 <&gcc GCC_PCIE0_RCHNG_CLK>; 870 clock-names = "iface", 871 "axi_m", 872 "axi_s", 873 "axi_bridge", 874 "rchng"; 875 876 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 877 <&gcc GCC_PCIE0_SLEEP_ARES>, 878 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 879 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 880 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 881 <&gcc GCC_PCIE0_AHB_ARES>, 882 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 883 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 884 reset-names = "pipe", 885 "sleep", 886 "sticky", 887 "axi_m", 888 "axi_s", 889 "ahb", 890 "axi_m_sticky", 891 "axi_s_sticky"; 892 status = "disabled"; 893 }; 894 }; 895 896 timer { 897 compatible = "arm,armv8-timer"; 898 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 899 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 900 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 901 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 902 }; 903 904 thermal-zones { 905 nss-top-thermal { 906 polling-delay-passive = <250>; 907 polling-delay = <1000>; 908 909 thermal-sensors = <&tsens 4>; 910 }; 911 912 nss0-thermal { 913 polling-delay-passive = <250>; 914 polling-delay = <1000>; 915 916 thermal-sensors = <&tsens 5>; 917 }; 918 919 nss1-thermal { 920 polling-delay-passive = <250>; 921 polling-delay = <1000>; 922 923 thermal-sensors = <&tsens 6>; 924 }; 925 926 wcss-phya0-thermal { 927 polling-delay-passive = <250>; 928 polling-delay = <1000>; 929 930 thermal-sensors = <&tsens 7>; 931 }; 932 933 wcss-phya1-thermal { 934 polling-delay-passive = <250>; 935 polling-delay = <1000>; 936 937 thermal-sensors = <&tsens 8>; 938 }; 939 940 cpu0_thermal: cpu0-thermal { 941 polling-delay-passive = <250>; 942 polling-delay = <1000>; 943 944 thermal-sensors = <&tsens 9>; 945 }; 946 947 cpu1_thermal: cpu1-thermal { 948 polling-delay-passive = <250>; 949 polling-delay = <1000>; 950 951 thermal-sensors = <&tsens 10>; 952 }; 953 954 cpu2_thermal: cpu2-thermal { 955 polling-delay-passive = <250>; 956 polling-delay = <1000>; 957 958 thermal-sensors = <&tsens 11>; 959 }; 960 961 cpu3_thermal: cpu3-thermal { 962 polling-delay-passive = <250>; 963 polling-delay = <1000>; 964 965 thermal-sensors = <&tsens 12>; 966 }; 967 968 cluster_thermal: cluster-thermal { 969 polling-delay-passive = <250>; 970 polling-delay = <1000>; 971 972 thermal-sensors = <&tsens 13>; 973 }; 974 975 wcss-phyb0-thermal { 976 polling-delay-passive = <250>; 977 polling-delay = <1000>; 978 979 thermal-sensors = <&tsens 14>; 980 }; 981 982 wcss-phyb1-thermal { 983 polling-delay-passive = <250>; 984 polling-delay = <1000>; 985 986 thermal-sensors = <&tsens 15>; 987 }; 988 }; 989}; 990