1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ6018 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10#include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11#include <dt-bindings/clock/qcom,apss-ipq.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&intc>; 18 19 clocks { 20 sleep_clk: sleep-clk { 21 compatible = "fixed-clock"; 22 clock-frequency = <32000>; 23 #clock-cells = <0>; 24 }; 25 26 xo: xo { 27 compatible = "fixed-clock"; 28 clock-frequency = <24000000>; 29 #clock-cells = <0>; 30 }; 31 }; 32 33 cpus: cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 CPU0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 reg = <0x0>; 41 enable-method = "psci"; 42 next-level-cache = <&L2_0>; 43 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 44 clock-names = "cpu"; 45 operating-points-v2 = <&cpu_opp_table>; 46 cpu-supply = <&ipq6018_s2>; 47 #cooling-cells = <2>; 48 }; 49 50 CPU1: cpu@1 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 enable-method = "psci"; 54 reg = <0x1>; 55 next-level-cache = <&L2_0>; 56 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 57 clock-names = "cpu"; 58 operating-points-v2 = <&cpu_opp_table>; 59 cpu-supply = <&ipq6018_s2>; 60 #cooling-cells = <2>; 61 }; 62 63 CPU2: cpu@2 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 enable-method = "psci"; 67 reg = <0x2>; 68 next-level-cache = <&L2_0>; 69 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 70 clock-names = "cpu"; 71 operating-points-v2 = <&cpu_opp_table>; 72 cpu-supply = <&ipq6018_s2>; 73 #cooling-cells = <2>; 74 }; 75 76 CPU3: cpu@3 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a53"; 79 enable-method = "psci"; 80 reg = <0x3>; 81 next-level-cache = <&L2_0>; 82 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 83 clock-names = "cpu"; 84 operating-points-v2 = <&cpu_opp_table>; 85 cpu-supply = <&ipq6018_s2>; 86 #cooling-cells = <2>; 87 }; 88 89 L2_0: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 }; 94 }; 95 96 firmware { 97 scm { 98 compatible = "qcom,scm-ipq6018", "qcom,scm"; 99 qcom,dload-mode = <&tcsr 0x6100>; 100 }; 101 }; 102 103 cpu_opp_table: opp-table-cpu { 104 compatible = "operating-points-v2-kryo-cpu"; 105 nvmem-cells = <&cpu_speed_bin>; 106 opp-shared; 107 108 opp-864000000 { 109 opp-hz = /bits/ 64 <864000000>; 110 opp-microvolt = <725000>; 111 opp-supported-hw = <0xf>; 112 clock-latency-ns = <200000>; 113 }; 114 115 opp-1056000000 { 116 opp-hz = /bits/ 64 <1056000000>; 117 opp-microvolt = <787500>; 118 opp-supported-hw = <0xf>; 119 clock-latency-ns = <200000>; 120 }; 121 122 opp-1320000000 { 123 opp-hz = /bits/ 64 <1320000000>; 124 opp-microvolt = <862500>; 125 opp-supported-hw = <0x3>; 126 clock-latency-ns = <200000>; 127 }; 128 129 opp-1440000000 { 130 opp-hz = /bits/ 64 <1440000000>; 131 opp-microvolt = <925000>; 132 opp-supported-hw = <0x3>; 133 clock-latency-ns = <200000>; 134 }; 135 136 opp-1608000000 { 137 opp-hz = /bits/ 64 <1608000000>; 138 opp-microvolt = <987500>; 139 opp-supported-hw = <0x1>; 140 clock-latency-ns = <200000>; 141 }; 142 143 opp-1800000000 { 144 opp-hz = /bits/ 64 <1800000000>; 145 opp-microvolt = <1062500>; 146 opp-supported-hw = <0x1>; 147 clock-latency-ns = <200000>; 148 }; 149 }; 150 151 pmuv8: pmu { 152 compatible = "arm,cortex-a53-pmu"; 153 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 154 }; 155 156 psci: psci { 157 compatible = "arm,psci-1.0"; 158 method = "smc"; 159 }; 160 161 rpm: remoteproc { 162 compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc"; 163 164 glink-edge { 165 compatible = "qcom,glink-rpm"; 166 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 167 qcom,rpm-msg-ram = <&rpm_msg_ram>; 168 mboxes = <&apcs_glb 0>; 169 170 rpm_requests: rpm-requests { 171 compatible = "qcom,rpm-ipq6018"; 172 qcom,glink-channels = "rpm_requests"; 173 174 regulators { 175 compatible = "qcom,rpm-mp5496-regulators"; 176 177 ipq6018_s2: s2 { 178 regulator-min-microvolt = <725000>; 179 regulator-max-microvolt = <1062500>; 180 regulator-always-on; 181 }; 182 }; 183 }; 184 }; 185 }; 186 187 reserved-memory { 188 #address-cells = <2>; 189 #size-cells = <2>; 190 ranges; 191 192 rpm_msg_ram: memory@60000 { 193 reg = <0x0 0x00060000 0x0 0x6000>; 194 no-map; 195 }; 196 197 bootloader@4a100000 { 198 reg = <0x0 0x4a100000 0x0 0x400000>; 199 no-map; 200 }; 201 202 sbl@4a500000 { 203 reg = <0x0 0x4a500000 0x0 0x100000>; 204 no-map; 205 }; 206 207 tz: memory@4a600000 { 208 reg = <0x0 0x4a600000 0x0 0x400000>; 209 no-map; 210 }; 211 212 smem_region: memory@4aa00000 { 213 reg = <0x0 0x4aa00000 0x0 0x100000>; 214 no-map; 215 }; 216 217 q6_region: memory@4ab00000 { 218 reg = <0x0 0x4ab00000 0x0 0x5500000>; 219 no-map; 220 }; 221 }; 222 223 smem { 224 compatible = "qcom,smem"; 225 memory-region = <&smem_region>; 226 hwlocks = <&tcsr_mutex 3>; 227 }; 228 229 soc: soc@0 { 230 #address-cells = <2>; 231 #size-cells = <2>; 232 ranges = <0 0 0 0 0x0 0xffffffff>; 233 dma-ranges; 234 compatible = "simple-bus"; 235 236 qusb_phy_1: qusb@59000 { 237 compatible = "qcom,ipq6018-qusb2-phy"; 238 reg = <0x0 0x00059000 0x0 0x180>; 239 #phy-cells = <0>; 240 241 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 242 <&xo>; 243 clock-names = "cfg_ahb", "ref"; 244 245 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 246 status = "disabled"; 247 }; 248 249 ssphy_0: ssphy@78000 { 250 compatible = "qcom,ipq6018-qmp-usb3-phy"; 251 reg = <0x0 0x00078000 0x0 0x1000>; 252 253 clocks = <&gcc GCC_USB0_AUX_CLK>, 254 <&xo>, 255 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 256 <&gcc GCC_USB0_PIPE_CLK>; 257 clock-names = "aux", 258 "ref", 259 "cfg_ahb", 260 "pipe"; 261 clock-output-names = "gcc_usb0_pipe_clk_src"; 262 #clock-cells = <0>; 263 #phy-cells = <0>; 264 265 resets = <&gcc GCC_USB0_PHY_BCR>, 266 <&gcc GCC_USB3PHY_0_PHY_BCR>; 267 reset-names = "phy", 268 "phy_phy"; 269 270 status = "disabled"; 271 }; 272 273 qusb_phy_0: qusb@79000 { 274 compatible = "qcom,ipq6018-qusb2-phy"; 275 reg = <0x0 0x00079000 0x0 0x180>; 276 #phy-cells = <0>; 277 278 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 279 <&xo>; 280 clock-names = "cfg_ahb", "ref"; 281 282 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 283 status = "disabled"; 284 }; 285 286 pcie_phy: phy@84000 { 287 compatible = "qcom,ipq6018-qmp-pcie-phy"; 288 reg = <0x0 0x00084000 0x0 0x1000>; 289 status = "disabled"; 290 291 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 292 <&gcc GCC_PCIE0_AHB_CLK>, 293 <&gcc GCC_PCIE0_PIPE_CLK>; 294 clock-names = "aux", 295 "cfg_ahb", 296 "pipe"; 297 298 clock-output-names = "gcc_pcie0_pipe_clk_src"; 299 #clock-cells = <0>; 300 301 #phy-cells = <0>; 302 303 resets = <&gcc GCC_PCIE0_PHY_BCR>, 304 <&gcc GCC_PCIE0PHY_PHY_BCR>; 305 reset-names = "phy", 306 "common"; 307 }; 308 309 mdio: mdio@90000 { 310 #address-cells = <1>; 311 #size-cells = <0>; 312 compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; 313 reg = <0x0 0x00090000 0x0 0x64>; 314 clocks = <&gcc GCC_MDIO_AHB_CLK>; 315 clock-names = "gcc_mdio_ahb_clk"; 316 status = "disabled"; 317 }; 318 319 qfprom: efuse@a4000 { 320 compatible = "qcom,ipq6018-qfprom", "qcom,qfprom"; 321 reg = <0x0 0x000a4000 0x0 0x2000>; 322 #address-cells = <1>; 323 #size-cells = <1>; 324 325 cpu_speed_bin: cpu-speed-bin@135 { 326 reg = <0x135 0x1>; 327 bits = <7 1>; 328 }; 329 }; 330 331 prng: qrng@e3000 { 332 compatible = "qcom,prng-ee"; 333 reg = <0x0 0x000e3000 0x0 0x1000>; 334 clocks = <&gcc GCC_PRNG_AHB_CLK>; 335 clock-names = "core"; 336 }; 337 338 tsens: thermal-sensor@4a9000 { 339 compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens"; 340 reg = <0x0 0x004a9000 0x0 0x1000>, 341 <0x0 0x004a8000 0x0 0x1000>; 342 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-names = "combined"; 344 #qcom,sensors = <16>; 345 #thermal-sensor-cells = <1>; 346 }; 347 348 cryptobam: dma-controller@704000 { 349 compatible = "qcom,bam-v1.7.0"; 350 reg = <0x0 0x00704000 0x0 0x20000>; 351 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 353 clock-names = "bam_clk"; 354 #dma-cells = <1>; 355 qcom,ee = <1>; 356 qcom,controlled-remotely; 357 }; 358 359 crypto: crypto@73a000 { 360 compatible = "qcom,crypto-v5.1"; 361 reg = <0x0 0x0073a000 0x0 0x6000>; 362 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 363 <&gcc GCC_CRYPTO_AXI_CLK>, 364 <&gcc GCC_CRYPTO_CLK>; 365 clock-names = "iface", "bus", "core"; 366 dmas = <&cryptobam 2>, <&cryptobam 3>; 367 dma-names = "rx", "tx"; 368 }; 369 370 tlmm: pinctrl@1000000 { 371 compatible = "qcom,ipq6018-pinctrl"; 372 reg = <0x0 0x01000000 0x0 0x300000>; 373 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 374 gpio-controller; 375 #gpio-cells = <2>; 376 gpio-ranges = <&tlmm 0 0 80>; 377 interrupt-controller; 378 #interrupt-cells = <2>; 379 380 serial_3_pins: serial3-state { 381 pins = "gpio44", "gpio45"; 382 function = "blsp2_uart"; 383 drive-strength = <8>; 384 bias-pull-down; 385 }; 386 387 qpic_pins: qpic-state { 388 pins = "gpio1", "gpio3", "gpio4", 389 "gpio5", "gpio6", "gpio7", 390 "gpio8", "gpio10", "gpio11", 391 "gpio12", "gpio13", "gpio14", 392 "gpio15", "gpio17"; 393 function = "qpic_pad"; 394 drive-strength = <8>; 395 bias-disable; 396 }; 397 }; 398 399 gcc: clock-controller@1800000 { 400 compatible = "qcom,gcc-ipq6018"; 401 reg = <0x0 0x01800000 0x0 0x80000>; 402 clocks = <&xo>, <&sleep_clk>; 403 clock-names = "xo", "sleep_clk"; 404 #clock-cells = <1>; 405 #reset-cells = <1>; 406 }; 407 408 tcsr_mutex: hwlock@1905000 { 409 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex"; 410 reg = <0x0 0x01905000 0x0 0x20000>; 411 #hwlock-cells = <1>; 412 }; 413 414 tcsr: syscon@1937000 { 415 compatible = "qcom,tcsr-ipq6018", "syscon"; 416 reg = <0x0 0x01937000 0x0 0x21000>; 417 }; 418 419 usb2: usb@70f8800 { 420 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 421 reg = <0x0 0x070f8800 0x0 0x400>; 422 #address-cells = <2>; 423 #size-cells = <2>; 424 ranges; 425 clocks = <&gcc GCC_USB1_MASTER_CLK>, 426 <&gcc GCC_USB1_SLEEP_CLK>, 427 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 428 clock-names = "core", 429 "sleep", 430 "mock_utmi"; 431 432 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, 433 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 434 assigned-clock-rates = <133330000>, 435 <24000000>; 436 437 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 439 interrupt-names = "pwr_event", 440 "qusb2_phy"; 441 442 resets = <&gcc GCC_USB1_BCR>; 443 status = "disabled"; 444 445 dwc_1: usb@7000000 { 446 compatible = "snps,dwc3"; 447 reg = <0x0 0x07000000 0x0 0xcd00>; 448 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 449 phys = <&qusb_phy_1>; 450 phy-names = "usb2-phy"; 451 tx-fifo-resize; 452 snps,is-utmi-l1-suspend; 453 snps,hird-threshold = /bits/ 8 <0x0>; 454 snps,dis_u2_susphy_quirk; 455 snps,dis_u3_susphy_quirk; 456 dr_mode = "host"; 457 }; 458 }; 459 460 sdhc: mmc@7804000 { 461 compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5"; 462 reg = <0x0 0x07804000 0x0 0x1000>, 463 <0x0 0x07805000 0x0 0x1000>; 464 reg-names = "hc", "cqhci"; 465 466 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 468 interrupt-names = "hc_irq", "pwr_irq"; 469 470 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 471 <&gcc GCC_SDCC1_APPS_CLK>, 472 <&xo>; 473 clock-names = "iface", "core", "xo"; 474 resets = <&gcc GCC_SDCC1_BCR>; 475 max-frequency = <192000000>; 476 status = "disabled"; 477 }; 478 479 blsp_dma: dma-controller@7884000 { 480 compatible = "qcom,bam-v1.7.0"; 481 reg = <0x0 0x07884000 0x0 0x2b000>; 482 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 483 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 484 clock-names = "bam_clk"; 485 #dma-cells = <1>; 486 qcom,ee = <0>; 487 }; 488 489 blsp1_uart1: serial@78af000 { 490 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 491 reg = <0x0 0x78af000 0x0 0x200>; 492 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 494 <&gcc GCC_BLSP1_AHB_CLK>; 495 clock-names = "core", "iface"; 496 status = "disabled"; 497 }; 498 499 blsp1_uart2: serial@78b0000 { 500 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 501 reg = <0x0 0x78b0000 0x0 0x200>; 502 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 504 <&gcc GCC_BLSP1_AHB_CLK>; 505 clock-names = "core", "iface"; 506 status = "disabled"; 507 }; 508 509 blsp1_uart3: serial@78b1000 { 510 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 511 reg = <0x0 0x078b1000 0x0 0x200>; 512 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 514 <&gcc GCC_BLSP1_AHB_CLK>; 515 clock-names = "core", "iface"; 516 status = "disabled"; 517 }; 518 519 blsp1_uart4: serial@78b2000 { 520 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 521 reg = <0x0 0x078b2000 0x0 0x200>; 522 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, 524 <&gcc GCC_BLSP1_AHB_CLK>; 525 clock-names = "core", "iface"; 526 status = "disabled"; 527 }; 528 529 blsp1_uart5: serial@78b3000 { 530 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 531 reg = <0x0 0x78b3000 0x0 0x200>; 532 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 534 <&gcc GCC_BLSP1_AHB_CLK>; 535 clock-names = "core", "iface"; 536 status = "disabled"; 537 }; 538 539 blsp1_uart6: serial@78b4000 { 540 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 541 reg = <0x0 0x078b4000 0x0 0x200>; 542 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, 544 <&gcc GCC_BLSP1_AHB_CLK>; 545 clock-names = "core", "iface"; 546 status = "disabled"; 547 }; 548 549 blsp1_spi1: spi@78b5000 { 550 compatible = "qcom,spi-qup-v2.2.1"; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 reg = <0x0 0x078b5000 0x0 0x600>; 554 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 556 <&gcc GCC_BLSP1_AHB_CLK>; 557 clock-names = "core", "iface"; 558 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 559 dma-names = "tx", "rx"; 560 status = "disabled"; 561 }; 562 563 blsp1_spi2: spi@78b6000 { 564 compatible = "qcom,spi-qup-v2.2.1"; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 reg = <0x0 0x078b6000 0x0 0x600>; 568 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 570 <&gcc GCC_BLSP1_AHB_CLK>; 571 clock-names = "core", "iface"; 572 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 573 dma-names = "tx", "rx"; 574 status = "disabled"; 575 }; 576 577 blsp1_spi5: spi@78b9000 { 578 compatible = "qcom,spi-qup-v2.2.1"; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 reg = <0x0 0x078b9000 0x0 0x600>; 582 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 584 <&gcc GCC_BLSP1_AHB_CLK>; 585 clock-names = "core", "iface"; 586 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 587 dma-names = "tx", "rx"; 588 status = "disabled"; 589 }; 590 591 blsp1_i2c2: i2c@78b6000 { 592 compatible = "qcom,i2c-qup-v2.2.1"; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 reg = <0x0 0x078b6000 0x0 0x600>; 596 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 597 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 598 <&gcc GCC_BLSP1_AHB_CLK>; 599 clock-names = "core", "iface"; 600 clock-frequency = <400000>; 601 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 602 dma-names = "tx", "rx"; 603 status = "disabled"; 604 }; 605 606 blsp1_i2c3: i2c@78b7000 { 607 compatible = "qcom,i2c-qup-v2.2.1"; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 reg = <0x0 0x078b7000 0x0 0x600>; 611 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 613 <&gcc GCC_BLSP1_AHB_CLK>; 614 clock-names = "core", "iface"; 615 clock-frequency = <400000>; 616 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 617 dma-names = "tx", "rx"; 618 status = "disabled"; 619 }; 620 621 blsp1_i2c6: i2c@78ba000 { 622 compatible = "qcom,i2c-qup-v2.2.1"; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 reg = <0x0 0x078ba000 0x0 0x600>; 626 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 628 <&gcc GCC_BLSP1_AHB_CLK>; 629 clock-names = "core", "iface"; 630 clock-frequency = <400000>; 631 dmas = <&blsp_dma 22>, <&blsp_dma 23>; 632 dma-names = "tx", "rx"; 633 status = "disabled"; 634 }; 635 636 qpic_bam: dma-controller@7984000 { 637 compatible = "qcom,bam-v1.7.0"; 638 reg = <0x0 0x07984000 0x0 0x1a000>; 639 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&gcc GCC_QPIC_AHB_CLK>; 641 clock-names = "bam_clk"; 642 #dma-cells = <1>; 643 qcom,ee = <0>; 644 status = "disabled"; 645 }; 646 647 qpic_nand: nand-controller@79b0000 { 648 compatible = "qcom,ipq6018-nand"; 649 reg = <0x0 0x079b0000 0x0 0x10000>; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 clocks = <&gcc GCC_QPIC_CLK>, 653 <&gcc GCC_QPIC_AHB_CLK>; 654 clock-names = "core", "aon"; 655 656 dmas = <&qpic_bam 0>, 657 <&qpic_bam 1>, 658 <&qpic_bam 2>; 659 dma-names = "tx", "rx", "cmd"; 660 pinctrl-0 = <&qpic_pins>; 661 pinctrl-names = "default"; 662 status = "disabled"; 663 }; 664 665 usb3: usb@8af8800 { 666 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 667 reg = <0x0 0x08af8800 0x0 0x400>; 668 #address-cells = <2>; 669 #size-cells = <2>; 670 ranges; 671 672 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 673 <&gcc GCC_USB0_MASTER_CLK>, 674 <&gcc GCC_USB0_SLEEP_CLK>, 675 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 676 clock-names = "cfg_noc", 677 "core", 678 "sleep", 679 "mock_utmi"; 680 681 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 682 <&gcc GCC_USB0_MASTER_CLK>, 683 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 684 assigned-clock-rates = <133330000>, 685 <133330000>, 686 <24000000>; 687 688 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 691 interrupt-names = "pwr_event", 692 "qusb2_phy", 693 "ss_phy_irq"; 694 695 resets = <&gcc GCC_USB0_BCR>; 696 status = "disabled"; 697 698 dwc_0: usb@8a00000 { 699 compatible = "snps,dwc3"; 700 reg = <0x0 0x08a00000 0x0 0xcd00>; 701 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 702 phys = <&qusb_phy_0>, <&ssphy_0>; 703 phy-names = "usb2-phy", "usb3-phy"; 704 clocks = <&xo>; 705 clock-names = "ref"; 706 tx-fifo-resize; 707 snps,parkmode-disable-ss-quirk; 708 snps,is-utmi-l1-suspend; 709 snps,hird-threshold = /bits/ 8 <0x0>; 710 snps,dis_u2_susphy_quirk; 711 snps,dis_u3_susphy_quirk; 712 dr_mode = "host"; 713 }; 714 }; 715 716 intc: interrupt-controller@b000000 { 717 compatible = "qcom,msm-qgic2"; 718 #address-cells = <2>; 719 #size-cells = <2>; 720 interrupt-controller; 721 #interrupt-cells = <3>; 722 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ 723 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ 724 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ 725 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ 726 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 727 ranges = <0 0 0 0xb00a000 0 0xffd>; 728 729 v2m@0 { 730 compatible = "arm,gic-v2m-frame"; 731 msi-controller; 732 reg = <0x0 0x0 0x0 0xffd>; 733 }; 734 }; 735 736 watchdog@b017000 { 737 compatible = "qcom,kpss-wdt"; 738 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 739 reg = <0x0 0x0b017000 0x0 0x40>; 740 clocks = <&sleep_clk>; 741 timeout-sec = <10>; 742 }; 743 744 apcs_glb: mailbox@b111000 { 745 compatible = "qcom,ipq6018-apcs-apps-global"; 746 reg = <0x0 0x0b111000 0x0 0x1000>; 747 #clock-cells = <1>; 748 clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; 749 clock-names = "pll", "xo", "gpll0"; 750 #mbox-cells = <1>; 751 }; 752 753 a53pll: clock@b116000 { 754 compatible = "qcom,ipq6018-a53pll"; 755 reg = <0x0 0x0b116000 0x0 0x40>; 756 #clock-cells = <0>; 757 clocks = <&xo>; 758 clock-names = "xo"; 759 }; 760 761 timer@b120000 { 762 #address-cells = <1>; 763 #size-cells = <1>; 764 ranges = <0 0 0 0x10000000>; 765 compatible = "arm,armv7-timer-mem"; 766 reg = <0x0 0x0b120000 0x0 0x1000>; 767 768 frame@b120000 { 769 frame-number = <0>; 770 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 772 reg = <0x0b121000 0x1000>, 773 <0x0b122000 0x1000>; 774 }; 775 776 frame@b123000 { 777 frame-number = <1>; 778 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 779 reg = <0x0b123000 0x1000>; 780 status = "disabled"; 781 }; 782 783 frame@b124000 { 784 frame-number = <2>; 785 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 786 reg = <0x0b124000 0x1000>; 787 status = "disabled"; 788 }; 789 790 frame@b125000 { 791 frame-number = <3>; 792 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 793 reg = <0x0b125000 0x1000>; 794 status = "disabled"; 795 }; 796 797 frame@b126000 { 798 frame-number = <4>; 799 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 800 reg = <0x0b126000 0x1000>; 801 status = "disabled"; 802 }; 803 804 frame@b127000 { 805 frame-number = <5>; 806 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 807 reg = <0x0b127000 0x1000>; 808 status = "disabled"; 809 }; 810 811 frame@b128000 { 812 frame-number = <6>; 813 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 814 reg = <0x0b128000 0x1000>; 815 status = "disabled"; 816 }; 817 }; 818 819 q6v5_wcss: remoteproc@cd00000 { 820 compatible = "qcom,ipq6018-wcss-pil"; 821 reg = <0x0 0x0cd00000 0x0 0x4040>, 822 <0x0 0x004ab000 0x0 0x20>; 823 reg-names = "qdsp6", 824 "rmb"; 825 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 826 <&wcss_smp2p_in 0 0>, 827 <&wcss_smp2p_in 1 0>, 828 <&wcss_smp2p_in 2 0>, 829 <&wcss_smp2p_in 3 0>; 830 interrupt-names = "wdog", 831 "fatal", 832 "ready", 833 "handover", 834 "stop-ack"; 835 836 resets = <&gcc GCC_WCSSAON_RESET>, 837 <&gcc GCC_WCSS_BCR>, 838 <&gcc GCC_WCSS_Q6_BCR>; 839 840 reset-names = "wcss_aon_reset", 841 "wcss_reset", 842 "wcss_q6_reset"; 843 844 clocks = <&gcc GCC_PRNG_AHB_CLK>; 845 clock-names = "prng"; 846 847 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>; 848 849 qcom,smem-states = <&wcss_smp2p_out 0>, 850 <&wcss_smp2p_out 1>; 851 qcom,smem-state-names = "shutdown", 852 "stop"; 853 854 memory-region = <&q6_region>; 855 856 glink-edge { 857 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; 858 label = "rtr"; 859 qcom,remote-pid = <1>; 860 mboxes = <&apcs_glb 8>; 861 862 qrtr_requests { 863 qcom,glink-channels = "IPCRTR"; 864 }; 865 }; 866 }; 867 868 pcie0: pcie@20000000 { 869 compatible = "qcom,pcie-ipq6018"; 870 reg = <0x0 0x20000000 0x0 0xf1d>, 871 <0x0 0x20000f20 0x0 0xa8>, 872 <0x0 0x20001000 0x0 0x1000>, 873 <0x0 0x80000 0x0 0x4000>, 874 <0x0 0x20100000 0x0 0x1000>; 875 reg-names = "dbi", "elbi", "atu", "parf", "config"; 876 877 device_type = "pci"; 878 linux,pci-domain = <0>; 879 bus-range = <0x00 0xff>; 880 num-lanes = <1>; 881 max-link-speed = <3>; 882 #address-cells = <3>; 883 #size-cells = <2>; 884 885 phys = <&pcie_phy>; 886 phy-names = "pciephy"; 887 888 ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>, 889 <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>; 890 891 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 892 interrupt-names = "msi"; 893 894 #interrupt-cells = <1>; 895 interrupt-map-mask = <0 0 0 0x7>; 896 interrupt-map = <0 0 0 1 &intc 0 0 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 897 <0 0 0 2 &intc 0 0 0 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 898 <0 0 0 3 &intc 0 0 0 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 899 <0 0 0 4 &intc 0 0 0 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 900 901 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 902 <&gcc GCC_PCIE0_AXI_M_CLK>, 903 <&gcc GCC_PCIE0_AXI_S_CLK>, 904 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 905 <&gcc PCIE0_RCHNG_CLK>; 906 clock-names = "iface", 907 "axi_m", 908 "axi_s", 909 "axi_bridge", 910 "rchng"; 911 912 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 913 <&gcc GCC_PCIE0_SLEEP_ARES>, 914 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 915 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 916 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 917 <&gcc GCC_PCIE0_AHB_ARES>, 918 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 919 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 920 reset-names = "pipe", 921 "sleep", 922 "sticky", 923 "axi_m", 924 "axi_s", 925 "ahb", 926 "axi_m_sticky", 927 "axi_s_sticky"; 928 929 status = "disabled"; 930 931 pcie@0 { 932 device_type = "pci"; 933 reg = <0x0 0x0 0x0 0x0 0x0>; 934 bus-range = <0x01 0xff>; 935 936 #address-cells = <3>; 937 #size-cells = <2>; 938 ranges; 939 }; 940 }; 941 }; 942 943 thermal-zones { 944 nss-top-thermal { 945 polling-delay-passive = <250>; 946 thermal-sensors = <&tsens 4>; 947 948 trips { 949 nss-top-critical { 950 temperature = <125000>; 951 hysteresis = <1000>; 952 type = "critical"; 953 }; 954 }; 955 }; 956 957 nss-thermal { 958 polling-delay-passive = <250>; 959 thermal-sensors = <&tsens 5>; 960 961 trips { 962 nss-critical { 963 temperature = <125000>; 964 hysteresis = <1000>; 965 type = "critical"; 966 }; 967 }; 968 }; 969 970 wcss-phya0-thermal { 971 polling-delay-passive = <250>; 972 thermal-sensors = <&tsens 7>; 973 974 trips { 975 wcss-phya0-critical { 976 temperature = <125000>; 977 hysteresis = <1000>; 978 type = "critical"; 979 }; 980 }; 981 }; 982 983 wcss-phya1-thermal { 984 polling-delay-passive = <250>; 985 polling-delay = <1000>; 986 thermal-sensors = <&tsens 8>; 987 988 trips { 989 wcss-phya1-critical { 990 temperature = <125000>; 991 hysteresis = <1000>; 992 type = "critical"; 993 }; 994 }; 995 }; 996 997 cpu-thermal { 998 polling-delay-passive = <250>; 999 thermal-sensors = <&tsens 13>; 1000 1001 trips { 1002 cpu-critical { 1003 temperature = <125000>; 1004 hysteresis = <1000>; 1005 type = "critical"; 1006 }; 1007 1008 cpu_alert: cpu-passive { 1009 temperature = <110000>; 1010 hysteresis = <1000>; 1011 type = "passive"; 1012 }; 1013 }; 1014 1015 cooling-maps { 1016 map0 { 1017 trip = <&cpu_alert>; 1018 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1019 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1020 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1021 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1022 }; 1023 }; 1024 }; 1025 1026 lpass-thermal { 1027 polling-delay-passive = <250>; 1028 thermal-sensors = <&tsens 14>; 1029 1030 trips { 1031 lpass-critical { 1032 temperature = <125000>; 1033 hysteresis = <1000>; 1034 type = "critical"; 1035 }; 1036 }; 1037 }; 1038 1039 ddrss-top-thermal { 1040 polling-delay-passive = <250>; 1041 thermal-sensors = <&tsens 15>; 1042 1043 trips { 1044 ddrss-top-critical { 1045 temperature = <125000>; 1046 hysteresis = <1000>; 1047 type = "critical"; 1048 }; 1049 }; 1050 }; 1051 }; 1052 1053 timer { 1054 compatible = "arm,armv8-timer"; 1055 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1056 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1057 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1058 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1059 }; 1060 1061 wcss: wcss-smp2p { 1062 compatible = "qcom,smp2p"; 1063 qcom,smem = <435>, <428>; 1064 1065 interrupt-parent = <&intc>; 1066 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>; 1067 1068 mboxes = <&apcs_glb 9>; 1069 1070 qcom,local-pid = <0>; 1071 qcom,remote-pid = <1>; 1072 1073 wcss_smp2p_out: master-kernel { 1074 qcom,entry-name = "master-kernel"; 1075 #qcom,smem-state-cells = <1>; 1076 }; 1077 1078 wcss_smp2p_in: slave-kernel { 1079 qcom,entry-name = "slave-kernel"; 1080 interrupt-controller; 1081 #interrupt-cells = <2>; 1082 }; 1083 }; 1084}; 1085