1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ6018 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10#include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11#include <dt-bindings/clock/qcom,apss-ipq.h> 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&intc>; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 clock-frequency = <32000>; 22 #clock-cells = <0>; 23 }; 24 25 xo: xo { 26 compatible = "fixed-clock"; 27 clock-frequency = <24000000>; 28 #clock-cells = <0>; 29 }; 30 }; 31 32 cpus: cpus { 33 #address-cells = <1>; 34 #size-cells = <0>; 35 36 CPU0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53"; 39 reg = <0x0>; 40 enable-method = "psci"; 41 next-level-cache = <&L2_0>; 42 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 43 clock-names = "cpu"; 44 operating-points-v2 = <&cpu_opp_table>; 45 cpu-supply = <&ipq6018_s2>; 46 }; 47 48 CPU1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 enable-method = "psci"; 52 reg = <0x1>; 53 next-level-cache = <&L2_0>; 54 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 55 clock-names = "cpu"; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-supply = <&ipq6018_s2>; 58 }; 59 60 CPU2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53"; 63 enable-method = "psci"; 64 reg = <0x2>; 65 next-level-cache = <&L2_0>; 66 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 67 clock-names = "cpu"; 68 operating-points-v2 = <&cpu_opp_table>; 69 cpu-supply = <&ipq6018_s2>; 70 }; 71 72 CPU3: cpu@3 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 enable-method = "psci"; 76 reg = <0x3>; 77 next-level-cache = <&L2_0>; 78 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 79 clock-names = "cpu"; 80 operating-points-v2 = <&cpu_opp_table>; 81 cpu-supply = <&ipq6018_s2>; 82 }; 83 84 L2_0: l2-cache { 85 compatible = "cache"; 86 cache-level = <0x2>; 87 }; 88 }; 89 90 cpu_opp_table: opp-table-cpu { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 94 opp-864000000 { 95 opp-hz = /bits/ 64 <864000000>; 96 opp-microvolt = <725000>; 97 clock-latency-ns = <200000>; 98 }; 99 opp-1056000000 { 100 opp-hz = /bits/ 64 <1056000000>; 101 opp-microvolt = <787500>; 102 clock-latency-ns = <200000>; 103 }; 104 opp-1320000000 { 105 opp-hz = /bits/ 64 <1320000000>; 106 opp-microvolt = <862500>; 107 clock-latency-ns = <200000>; 108 }; 109 opp-1440000000 { 110 opp-hz = /bits/ 64 <1440000000>; 111 opp-microvolt = <925000>; 112 clock-latency-ns = <200000>; 113 }; 114 opp-1608000000 { 115 opp-hz = /bits/ 64 <1608000000>; 116 opp-microvolt = <987500>; 117 clock-latency-ns = <200000>; 118 }; 119 opp-1800000000 { 120 opp-hz = /bits/ 64 <1800000000>; 121 opp-microvolt = <1062500>; 122 clock-latency-ns = <200000>; 123 }; 124 }; 125 126 firmware { 127 scm { 128 compatible = "qcom,scm-ipq6018", "qcom,scm"; 129 }; 130 }; 131 132 pmuv8: pmu { 133 compatible = "arm,cortex-a53-pmu"; 134 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 135 IRQ_TYPE_LEVEL_HIGH)>; 136 }; 137 138 psci: psci { 139 compatible = "arm,psci-1.0"; 140 method = "smc"; 141 }; 142 143 reserved-memory { 144 #address-cells = <2>; 145 #size-cells = <2>; 146 ranges; 147 148 rpm_msg_ram: memory@60000 { 149 reg = <0x0 0x60000 0x0 0x6000>; 150 no-map; 151 }; 152 153 tz: memory@4a600000 { 154 reg = <0x0 0x4a600000 0x0 0x00400000>; 155 no-map; 156 }; 157 158 smem_region: memory@4aa00000 { 159 reg = <0x0 0x4aa00000 0x0 0x00100000>; 160 no-map; 161 }; 162 163 q6_region: memory@4ab00000 { 164 reg = <0x0 0x4ab00000 0x0 0x05500000>; 165 no-map; 166 }; 167 }; 168 169 smem { 170 compatible = "qcom,smem"; 171 memory-region = <&smem_region>; 172 hwlocks = <&tcsr_mutex 0>; 173 }; 174 175 soc: soc { 176 #address-cells = <2>; 177 #size-cells = <2>; 178 ranges = <0 0 0 0 0x0 0xffffffff>; 179 dma-ranges; 180 compatible = "simple-bus"; 181 182 prng: qrng@e1000 { 183 compatible = "qcom,prng-ee"; 184 reg = <0x0 0xe3000 0x0 0x1000>; 185 clocks = <&gcc GCC_PRNG_AHB_CLK>; 186 clock-names = "core"; 187 }; 188 189 cryptobam: dma-controller@704000 { 190 compatible = "qcom,bam-v1.7.0"; 191 reg = <0x0 0x00704000 0x0 0x20000>; 192 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 194 clock-names = "bam_clk"; 195 #dma-cells = <1>; 196 qcom,ee = <1>; 197 qcom,controlled-remotely; 198 }; 199 200 crypto: crypto@73a000 { 201 compatible = "qcom,crypto-v5.1"; 202 reg = <0x0 0x0073a000 0x0 0x6000>; 203 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 204 <&gcc GCC_CRYPTO_AXI_CLK>, 205 <&gcc GCC_CRYPTO_CLK>; 206 clock-names = "iface", "bus", "core"; 207 dmas = <&cryptobam 2>, <&cryptobam 3>; 208 dma-names = "rx", "tx"; 209 }; 210 211 tlmm: pinctrl@1000000 { 212 compatible = "qcom,ipq6018-pinctrl"; 213 reg = <0x0 0x01000000 0x0 0x300000>; 214 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 215 gpio-controller; 216 #gpio-cells = <2>; 217 gpio-ranges = <&tlmm 0 0 80>; 218 interrupt-controller; 219 #interrupt-cells = <2>; 220 221 serial_3_pins: serial3-state { 222 pins = "gpio44", "gpio45"; 223 function = "blsp2_uart"; 224 drive-strength = <8>; 225 bias-pull-down; 226 }; 227 228 qpic_pins: qpic-state { 229 pins = "gpio1", "gpio3", "gpio4", 230 "gpio5", "gpio6", "gpio7", 231 "gpio8", "gpio10", "gpio11", 232 "gpio12", "gpio13", "gpio14", 233 "gpio15", "gpio17"; 234 function = "qpic_pad"; 235 drive-strength = <8>; 236 bias-disable; 237 }; 238 }; 239 240 gcc: gcc@1800000 { 241 compatible = "qcom,gcc-ipq6018"; 242 reg = <0x0 0x01800000 0x0 0x80000>; 243 clocks = <&xo>, <&sleep_clk>; 244 clock-names = "xo", "sleep_clk"; 245 #clock-cells = <1>; 246 #reset-cells = <1>; 247 }; 248 249 tcsr_mutex: hwlock@1905000 { 250 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex"; 251 reg = <0x0 0x01905000 0x0 0x1000>; 252 #hwlock-cells = <1>; 253 }; 254 255 tcsr: syscon@1937000 { 256 compatible = "qcom,tcsr-ipq6018", "syscon"; 257 reg = <0x0 0x01937000 0x0 0x21000>; 258 }; 259 260 blsp_dma: dma-controller@7884000 { 261 compatible = "qcom,bam-v1.7.0"; 262 reg = <0x0 0x07884000 0x0 0x2b000>; 263 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 265 clock-names = "bam_clk"; 266 #dma-cells = <1>; 267 qcom,ee = <0>; 268 }; 269 270 blsp1_uart3: serial@78b1000 { 271 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 272 reg = <0x0 0x078b1000 0x0 0x200>; 273 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 275 <&gcc GCC_BLSP1_AHB_CLK>; 276 clock-names = "core", "iface"; 277 status = "disabled"; 278 }; 279 280 blsp1_spi1: spi@78b5000 { 281 compatible = "qcom,spi-qup-v2.2.1"; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 reg = <0x0 0x078b5000 0x0 0x600>; 285 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 286 spi-max-frequency = <50000000>; 287 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 288 <&gcc GCC_BLSP1_AHB_CLK>; 289 clock-names = "core", "iface"; 290 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 291 dma-names = "tx", "rx"; 292 status = "disabled"; 293 }; 294 295 blsp1_spi2: spi@78b6000 { 296 compatible = "qcom,spi-qup-v2.2.1"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 reg = <0x0 0x078b6000 0x0 0x600>; 300 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 301 spi-max-frequency = <50000000>; 302 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 303 <&gcc GCC_BLSP1_AHB_CLK>; 304 clock-names = "core", "iface"; 305 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 306 dma-names = "tx", "rx"; 307 status = "disabled"; 308 }; 309 310 blsp1_i2c2: i2c@78b6000 { 311 compatible = "qcom,i2c-qup-v2.2.1"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 reg = <0x0 0x078b6000 0x0 0x600>; 315 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 317 <&gcc GCC_BLSP1_AHB_CLK>; 318 clock-names = "core", "iface"; 319 clock-frequency = <400000>; 320 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 321 dma-names = "tx", "rx"; 322 status = "disabled"; 323 }; 324 325 blsp1_i2c3: i2c@78b7000 { 326 compatible = "qcom,i2c-qup-v2.2.1"; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 reg = <0x0 0x078b7000 0x0 0x600>; 330 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 332 <&gcc GCC_BLSP1_AHB_CLK>; 333 clock-names = "core", "iface"; 334 clock-frequency = <400000>; 335 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 336 dma-names = "tx", "rx"; 337 status = "disabled"; 338 }; 339 340 qpic_bam: dma-controller@7984000 { 341 compatible = "qcom,bam-v1.7.0"; 342 reg = <0x0 0x07984000 0x0 0x1a000>; 343 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&gcc GCC_QPIC_AHB_CLK>; 345 clock-names = "bam_clk"; 346 #dma-cells = <1>; 347 qcom,ee = <0>; 348 status = "disabled"; 349 }; 350 351 qpic_nand: nand-controller@79b0000 { 352 compatible = "qcom,ipq6018-nand"; 353 reg = <0x0 0x079b0000 0x0 0x10000>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 clocks = <&gcc GCC_QPIC_CLK>, 357 <&gcc GCC_QPIC_AHB_CLK>; 358 clock-names = "core", "aon"; 359 360 dmas = <&qpic_bam 0>, 361 <&qpic_bam 1>, 362 <&qpic_bam 2>; 363 dma-names = "tx", "rx", "cmd"; 364 pinctrl-0 = <&qpic_pins>; 365 pinctrl-names = "default"; 366 status = "disabled"; 367 }; 368 369 intc: interrupt-controller@b000000 { 370 compatible = "qcom,msm-qgic2"; 371 #address-cells = <2>; 372 #size-cells = <2>; 373 interrupt-controller; 374 #interrupt-cells = <0x3>; 375 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ 376 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ 377 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ 378 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ 379 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 380 ranges = <0 0 0 0xb00a000 0 0xffd>; 381 382 v2m@0 { 383 compatible = "arm,gic-v2m-frame"; 384 msi-controller; 385 reg = <0x0 0x0 0x0 0xffd>; 386 }; 387 }; 388 389 pcie_phy: phy@84000 { 390 compatible = "qcom,ipq6018-qmp-pcie-phy"; 391 reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */ 392 status = "disabled"; 393 #address-cells = <2>; 394 #size-cells = <2>; 395 ranges; 396 397 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 398 <&gcc GCC_PCIE0_AHB_CLK>; 399 clock-names = "aux", "cfg_ahb"; 400 401 resets = <&gcc GCC_PCIE0_PHY_BCR>, 402 <&gcc GCC_PCIE0PHY_PHY_BCR>; 403 reset-names = "phy", 404 "common"; 405 406 pcie_phy0: phy@84200 { 407 reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */ 408 <0x0 0x84400 0x0 0x200>, /* Serdes Rx */ 409 <0x0 0x84800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ 410 <0x0 0x84c00 0x0 0xf4>; /* pcs_misc */ 411 #phy-cells = <0>; 412 413 clocks = <&gcc GCC_PCIE0_PIPE_CLK>; 414 clock-names = "pipe0"; 415 clock-output-names = "gcc_pcie0_pipe_clk_src"; 416 #clock-cells = <0>; 417 }; 418 }; 419 420 pcie0: pci@20000000 { 421 compatible = "qcom,pcie-ipq6018"; 422 reg = <0x0 0x20000000 0x0 0xf1d>, 423 <0x0 0x20000f20 0x0 0xa8>, 424 <0x0 0x20001000 0x0 0x1000>, 425 <0x0 0x80000 0x0 0x4000>, 426 <0x0 0x20100000 0x0 0x1000>; 427 reg-names = "dbi", "elbi", "atu", "parf", "config"; 428 429 device_type = "pci"; 430 linux,pci-domain = <0>; 431 bus-range = <0x00 0xff>; 432 num-lanes = <1>; 433 max-link-speed = <3>; 434 #address-cells = <3>; 435 #size-cells = <2>; 436 437 phys = <&pcie_phy0>; 438 phy-names = "pciephy"; 439 440 ranges = <0x81000000 0 0x20200000 0 0x20200000 441 0 0x10000>, /* downstream I/O */ 442 <0x82000000 0 0x20220000 0 0x20220000 443 0 0xfde0000>; /* non-prefetchable memory */ 444 445 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 446 interrupt-names = "msi"; 447 448 #interrupt-cells = <1>; 449 interrupt-map-mask = <0 0 0 0x7>; 450 interrupt-map = <0 0 0 1 &intc 0 75 451 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 452 <0 0 0 2 &intc 0 78 453 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 454 <0 0 0 3 &intc 0 79 455 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 456 <0 0 0 4 &intc 0 83 457 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 458 459 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 460 <&gcc GCC_PCIE0_AXI_M_CLK>, 461 <&gcc GCC_PCIE0_AXI_S_CLK>, 462 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 463 <&gcc PCIE0_RCHNG_CLK>; 464 clock-names = "iface", 465 "axi_m", 466 "axi_s", 467 "axi_bridge", 468 "rchng"; 469 470 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 471 <&gcc GCC_PCIE0_SLEEP_ARES>, 472 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 473 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 474 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 475 <&gcc GCC_PCIE0_AHB_ARES>, 476 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 477 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 478 reset-names = "pipe", 479 "sleep", 480 "sticky", 481 "axi_m", 482 "axi_s", 483 "ahb", 484 "axi_m_sticky", 485 "axi_s_sticky"; 486 487 status = "disabled"; 488 }; 489 490 watchdog@b017000 { 491 compatible = "qcom,kpss-wdt"; 492 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 493 reg = <0x0 0x0b017000 0x0 0x40>; 494 clocks = <&sleep_clk>; 495 timeout-sec = <10>; 496 }; 497 498 apcs_glb: mailbox@b111000 { 499 compatible = "qcom,ipq6018-apcs-apps-global"; 500 reg = <0x0 0x0b111000 0x0 0x1000>; 501 #clock-cells = <1>; 502 clocks = <&a53pll>, <&xo>; 503 clock-names = "pll", "xo"; 504 #mbox-cells = <1>; 505 }; 506 507 a53pll: clock@b116000 { 508 compatible = "qcom,ipq6018-a53pll"; 509 reg = <0x0 0x0b116000 0x0 0x40>; 510 #clock-cells = <0>; 511 clocks = <&xo>; 512 clock-names = "xo"; 513 }; 514 515 timer@b120000 { 516 #address-cells = <1>; 517 #size-cells = <1>; 518 ranges = <0 0 0 0x10000000>; 519 compatible = "arm,armv7-timer-mem"; 520 reg = <0x0 0x0b120000 0x0 0x1000>; 521 522 frame@b120000 { 523 frame-number = <0>; 524 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 526 reg = <0x0b121000 0x1000>, 527 <0x0b122000 0x1000>; 528 }; 529 530 frame@b123000 { 531 frame-number = <1>; 532 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 533 reg = <0x0b123000 0x1000>; 534 status = "disabled"; 535 }; 536 537 frame@b124000 { 538 frame-number = <2>; 539 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 540 reg = <0x0b124000 0x1000>; 541 status = "disabled"; 542 }; 543 544 frame@b125000 { 545 frame-number = <3>; 546 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 547 reg = <0x0b125000 0x1000>; 548 status = "disabled"; 549 }; 550 551 frame@b126000 { 552 frame-number = <4>; 553 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 554 reg = <0x0b126000 0x1000>; 555 status = "disabled"; 556 }; 557 558 frame@b127000 { 559 frame-number = <5>; 560 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 561 reg = <0x0b127000 0x1000>; 562 status = "disabled"; 563 }; 564 565 frame@b128000 { 566 frame-number = <6>; 567 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 568 reg = <0x0b128000 0x1000>; 569 status = "disabled"; 570 }; 571 }; 572 573 q6v5_wcss: remoteproc@cd00000 { 574 compatible = "qcom,ipq6018-wcss-pil"; 575 reg = <0x0 0x0cd00000 0x0 0x4040>, 576 <0x0 0x004ab000 0x0 0x20>; 577 reg-names = "qdsp6", 578 "rmb"; 579 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 580 <&wcss_smp2p_in 0 0>, 581 <&wcss_smp2p_in 1 0>, 582 <&wcss_smp2p_in 2 0>, 583 <&wcss_smp2p_in 3 0>; 584 interrupt-names = "wdog", 585 "fatal", 586 "ready", 587 "handover", 588 "stop-ack"; 589 590 resets = <&gcc GCC_WCSSAON_RESET>, 591 <&gcc GCC_WCSS_BCR>, 592 <&gcc GCC_WCSS_Q6_BCR>; 593 594 reset-names = "wcss_aon_reset", 595 "wcss_reset", 596 "wcss_q6_reset"; 597 598 clocks = <&gcc GCC_PRNG_AHB_CLK>; 599 clock-names = "prng"; 600 601 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>; 602 603 qcom,smem-states = <&wcss_smp2p_out 0>, 604 <&wcss_smp2p_out 1>; 605 qcom,smem-state-names = "shutdown", 606 "stop"; 607 608 memory-region = <&q6_region>; 609 610 glink-edge { 611 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; 612 label = "rtr"; 613 qcom,remote-pid = <1>; 614 mboxes = <&apcs_glb 8>; 615 616 qrtr_requests { 617 qcom,glink-channels = "IPCRTR"; 618 }; 619 }; 620 }; 621 622 mdio: mdio@90000 { 623 #address-cells = <1>; 624 #size-cells = <0>; 625 compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; 626 reg = <0x0 0x90000 0x0 0x64>; 627 clocks = <&gcc GCC_MDIO_AHB_CLK>; 628 clock-names = "gcc_mdio_ahb_clk"; 629 status = "disabled"; 630 }; 631 632 qusb_phy_1: qusb@59000 { 633 compatible = "qcom,ipq6018-qusb2-phy"; 634 reg = <0x0 0x059000 0x0 0x180>; 635 #phy-cells = <0>; 636 637 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 638 <&xo>; 639 clock-names = "cfg_ahb", "ref"; 640 641 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 642 status = "disabled"; 643 }; 644 645 usb2: usb@70f8800 { 646 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 647 reg = <0x0 0x070F8800 0x0 0x400>; 648 #address-cells = <2>; 649 #size-cells = <2>; 650 ranges; 651 clocks = <&gcc GCC_USB1_MASTER_CLK>, 652 <&gcc GCC_USB1_SLEEP_CLK>, 653 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 654 clock-names = "core", 655 "sleep", 656 "mock_utmi"; 657 658 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, 659 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 660 assigned-clock-rates = <133330000>, 661 <24000000>; 662 resets = <&gcc GCC_USB1_BCR>; 663 status = "disabled"; 664 665 dwc_1: usb@7000000 { 666 compatible = "snps,dwc3"; 667 reg = <0x0 0x7000000 0x0 0xcd00>; 668 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 669 phys = <&qusb_phy_1>; 670 phy-names = "usb2-phy"; 671 tx-fifo-resize; 672 snps,is-utmi-l1-suspend; 673 snps,hird-threshold = /bits/ 8 <0x0>; 674 snps,dis_u2_susphy_quirk; 675 snps,dis_u3_susphy_quirk; 676 dr_mode = "host"; 677 }; 678 }; 679 680 ssphy_0: ssphy@78000 { 681 compatible = "qcom,ipq6018-qmp-usb3-phy"; 682 reg = <0x0 0x78000 0x0 0x1C4>; 683 #address-cells = <2>; 684 #size-cells = <2>; 685 ranges; 686 687 clocks = <&gcc GCC_USB0_AUX_CLK>, 688 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>; 689 clock-names = "aux", "cfg_ahb", "ref"; 690 691 resets = <&gcc GCC_USB0_PHY_BCR>, 692 <&gcc GCC_USB3PHY_0_PHY_BCR>; 693 reset-names = "phy","common"; 694 status = "disabled"; 695 696 usb0_ssphy: phy@78200 { 697 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ 698 <0x0 0x00078400 0x0 0x200>, /* Rx */ 699 <0x0 0x00078800 0x0 0x1F8>, /* PCS */ 700 <0x0 0x00078600 0x0 0x044>; /* PCS misc */ 701 #phy-cells = <0>; 702 #clock-cells = <0>; 703 clocks = <&gcc GCC_USB0_PIPE_CLK>; 704 clock-names = "pipe0"; 705 clock-output-names = "gcc_usb0_pipe_clk_src"; 706 }; 707 }; 708 709 qusb_phy_0: qusb@79000 { 710 compatible = "qcom,ipq6018-qusb2-phy"; 711 reg = <0x0 0x079000 0x0 0x180>; 712 #phy-cells = <0>; 713 714 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 715 <&xo>; 716 clock-names = "cfg_ahb", "ref"; 717 718 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 719 status = "disabled"; 720 }; 721 722 usb3: usb@8af8800 { 723 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 724 reg = <0x0 0x8AF8800 0x0 0x400>; 725 #address-cells = <2>; 726 #size-cells = <2>; 727 ranges; 728 729 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 730 <&gcc GCC_USB0_MASTER_CLK>, 731 <&gcc GCC_USB0_SLEEP_CLK>, 732 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 733 clock-names = "cfg_noc", 734 "core", 735 "sleep", 736 "mock_utmi"; 737 738 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 739 <&gcc GCC_USB0_MASTER_CLK>, 740 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 741 assigned-clock-rates = <133330000>, 742 <133330000>, 743 <20000000>; 744 745 resets = <&gcc GCC_USB0_BCR>; 746 status = "disabled"; 747 748 dwc_0: usb@8a00000 { 749 compatible = "snps,dwc3"; 750 reg = <0x0 0x8A00000 0x0 0xcd00>; 751 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 752 phys = <&qusb_phy_0>, <&usb0_ssphy>; 753 phy-names = "usb2-phy", "usb3-phy"; 754 clocks = <&xo>; 755 clock-names = "ref"; 756 tx-fifo-resize; 757 snps,is-utmi-l1-suspend; 758 snps,hird-threshold = /bits/ 8 <0x0>; 759 snps,dis_u2_susphy_quirk; 760 snps,dis_u3_susphy_quirk; 761 dr_mode = "host"; 762 }; 763 }; 764 }; 765 766 timer { 767 compatible = "arm,armv8-timer"; 768 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 769 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 770 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 771 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 772 }; 773 774 wcss: wcss-smp2p { 775 compatible = "qcom,smp2p"; 776 qcom,smem = <435>, <428>; 777 778 interrupt-parent = <&intc>; 779 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>; 780 781 mboxes = <&apcs_glb 9>; 782 783 qcom,local-pid = <0>; 784 qcom,remote-pid = <1>; 785 786 wcss_smp2p_out: master-kernel { 787 qcom,entry-name = "master-kernel"; 788 #qcom,smem-state-cells = <1>; 789 }; 790 791 wcss_smp2p_in: slave-kernel { 792 qcom,entry-name = "slave-kernel"; 793 interrupt-controller; 794 #interrupt-cells = <2>; 795 }; 796 }; 797 798 rpm-glink { 799 compatible = "qcom,glink-rpm"; 800 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 801 qcom,rpm-msg-ram = <&rpm_msg_ram>; 802 mboxes = <&apcs_glb 0>; 803 804 rpm_requests: glink-channel { 805 compatible = "qcom,rpm-ipq6018"; 806 qcom,glink-channels = "rpm_requests"; 807 808 regulators { 809 compatible = "qcom,rpm-mp5496-regulators"; 810 811 ipq6018_s2: s2 { 812 regulator-min-microvolt = <725000>; 813 regulator-max-microvolt = <1062500>; 814 regulator-always-on; 815 }; 816 }; 817 }; 818 }; 819}; 820