1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ5424 device tree source 4 * 5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. 6 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/qcom,apss-ipq.h> 11#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h> 12#include <dt-bindings/clock/qcom,ipq5424-gcc.h> 13#include <dt-bindings/reset/qcom,ipq5424-gcc.h> 14#include <dt-bindings/interconnect/qcom,ipq5424.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 interrupt-parent = <&intc>; 22 23 clocks { 24 ref_48mhz_clk: ref-48mhz-clk { 25 compatible = "fixed-factor-clock"; 26 clocks = <&xo_clk>; 27 #clock-cells = <0>; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 }; 34 35 xo_board: xo-board-clk { 36 compatible = "fixed-factor-clock"; 37 clocks = <&ref_48mhz_clk>; 38 #clock-cells = <0>; 39 }; 40 41 xo_clk: xo-clk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 }; 45 }; 46 47 cpus: cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a55"; 54 reg = <0x0>; 55 enable-method = "psci"; 56 next-level-cache = <&l2_0>; 57 clocks = <&apss_clk APSS_SILVER_CORE_CLK>; 58 clock-names = "cpu"; 59 operating-points-v2 = <&cpu_opp_table>; 60 interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; 61 #cooling-cells = <2>; 62 63 l2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&l3_0>; 68 69 l3_0: l3-cache { 70 compatible = "cache"; 71 cache-level = <3>; 72 cache-unified; 73 }; 74 }; 75 }; 76 77 cpu1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a55"; 80 enable-method = "psci"; 81 reg = <0x100>; 82 next-level-cache = <&l2_100>; 83 clocks = <&apss_clk APSS_SILVER_CORE_CLK>; 84 clock-names = "cpu"; 85 operating-points-v2 = <&cpu_opp_table>; 86 interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; 87 #cooling-cells = <2>; 88 89 l2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&l3_0>; 94 }; 95 }; 96 97 cpu2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a55"; 100 enable-method = "psci"; 101 reg = <0x200>; 102 next-level-cache = <&l2_200>; 103 clocks = <&apss_clk APSS_SILVER_CORE_CLK>; 104 clock-names = "cpu"; 105 operating-points-v2 = <&cpu_opp_table>; 106 interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; 107 #cooling-cells = <2>; 108 109 l2_200: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 next-level-cache = <&l3_0>; 114 }; 115 }; 116 117 cpu3: cpu@300 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a55"; 120 enable-method = "psci"; 121 reg = <0x300>; 122 next-level-cache = <&l2_300>; 123 clocks = <&apss_clk APSS_SILVER_CORE_CLK>; 124 clock-names = "cpu"; 125 operating-points-v2 = <&cpu_opp_table>; 126 interconnects = <&apss_clk MASTER_CPU &apss_clk SLAVE_L3>; 127 #cooling-cells = <2>; 128 129 l2_300: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&l3_0>; 134 }; 135 }; 136 }; 137 138 firmware { 139 scm { 140 compatible = "qcom,scm-ipq5424", "qcom,scm"; 141 qcom,dload-mode = <&tcsr 0x25100>; 142 }; 143 }; 144 145 cpu_opp_table: opp-table-cpu { 146 compatible = "operating-points-v2-kryo-cpu"; 147 opp-shared; 148 nvmem-cells = <&cpu_speed_bin>; 149 150 opp-816000000 { 151 opp-hz = /bits/ 64 <816000000>; 152 opp-microvolt = <850000>; 153 opp-supported-hw = <0x3>; 154 clock-latency-ns = <200000>; 155 opp-peak-kBps = <816000>; 156 }; 157 158 opp-1416000000 { 159 opp-hz = /bits/ 64 <1416000000>; 160 opp-microvolt = <850000>; 161 opp-supported-hw = <0x3>; 162 clock-latency-ns = <200000>; 163 opp-peak-kBps = <984000>; 164 }; 165 166 opp-1800000000 { 167 opp-hz = /bits/ 64 <1800000000>; 168 opp-microvolt = <1000000>; 169 opp-supported-hw = <0x1>; 170 clock-latency-ns = <200000>; 171 opp-peak-kBps = <1272000>; 172 }; 173 }; 174 175 memory@80000000 { 176 device_type = "memory"; 177 /* We expect the bootloader to fill in the size */ 178 reg = <0x0 0x80000000 0x0 0x0>; 179 }; 180 181 pmu-a55 { 182 compatible = "arm,cortex-a55-pmu"; 183 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 184 }; 185 186 pmu-dsu { 187 compatible = "arm,dsu-pmu"; 188 interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 189 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 190 }; 191 192 psci { 193 compatible = "arm,psci-1.0"; 194 method = "smc"; 195 }; 196 197 reserved-memory { 198 #address-cells = <2>; 199 #size-cells = <2>; 200 ranges; 201 202 bootloader@8a200000 { 203 reg = <0x0 0x8a200000 0x0 0x400000>; 204 no-map; 205 }; 206 207 tz@8a600000 { 208 reg = <0x0 0x8a600000 0x0 0x200000>; 209 no-map; 210 }; 211 212 smem@8a800000 { 213 compatible = "qcom,smem"; 214 reg = <0x0 0x8a800000 0x0 0x32000>; 215 no-map; 216 217 hwlocks = <&tcsr_mutex 3>; 218 }; 219 220 tfa@8a832000 { 221 reg = <0x0 0x8a832000 0x0 0x80000>; 222 no-map; 223 status = "disabled"; 224 }; 225 }; 226 227 soc@0 { 228 compatible = "simple-bus"; 229 #address-cells = <2>; 230 #size-cells = <2>; 231 ranges = <0 0 0 0 0x10 0>; 232 233 pcie0_phy: phy@84000 { 234 compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy", 235 "qcom,ipq9574-qmp-gen3x1-pcie-phy"; 236 reg = <0x0 0x00084000 0x0 0x1000>; 237 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 238 <&gcc GCC_PCIE0_AHB_CLK>, 239 <&gcc GCC_PCIE0_PIPE_CLK>; 240 clock-names = "aux", 241 "cfg_ahb", 242 "pipe"; 243 244 assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>; 245 assigned-clock-rates = <20000000>; 246 247 resets = <&gcc GCC_PCIE0_PHY_BCR>, 248 <&gcc GCC_PCIE0PHY_PHY_BCR>; 249 reset-names = "phy", 250 "common"; 251 252 #clock-cells = <0>; 253 clock-output-names = "gcc_pcie0_pipe_clk_src"; 254 255 #phy-cells = <0>; 256 status = "disabled"; 257 }; 258 259 pcie1_phy: phy@8c000 { 260 compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy", 261 "qcom,ipq9574-qmp-gen3x1-pcie-phy"; 262 reg = <0x0 0x0008c000 0x0 0x1000>; 263 clocks = <&gcc GCC_PCIE1_AUX_CLK>, 264 <&gcc GCC_PCIE1_AHB_CLK>, 265 <&gcc GCC_PCIE1_PIPE_CLK>; 266 clock-names = "aux", 267 "cfg_ahb", 268 "pipe"; 269 270 assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>; 271 assigned-clock-rates = <20000000>; 272 273 resets = <&gcc GCC_PCIE1_PHY_BCR>, 274 <&gcc GCC_PCIE1PHY_PHY_BCR>; 275 reset-names = "phy", 276 "common"; 277 278 #clock-cells = <0>; 279 clock-output-names = "gcc_pcie1_pipe_clk_src"; 280 281 #phy-cells = <0>; 282 status = "disabled"; 283 }; 284 285 cmn_pll: clock-controller@9b000 { 286 compatible = "qcom,ipq5424-cmn-pll"; 287 reg = <0 0x0009b000 0 0x800>; 288 clocks = <&ref_48mhz_clk>, 289 <&gcc GCC_CMN_12GPLL_AHB_CLK>, 290 <&gcc GCC_CMN_12GPLL_SYS_CLK>; 291 clock-names = "ref", "ahb", "sys"; 292 #clock-cells = <1>; 293 assigned-clocks = <&cmn_pll IPQ5424_CMN_PLL_CLK>; 294 assigned-clock-rates-u64 = /bits/ 64 <12000000000>; 295 }; 296 297 efuse@a4000 { 298 compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; 299 reg = <0 0x000a4000 0 0x741>; 300 #address-cells = <1>; 301 #size-cells = <1>; 302 303 tsens_sens9_off: s9@3dc { 304 reg = <0x3dc 0x1>; 305 bits = <4 4>; 306 }; 307 308 tsens_sens10_off: s10@3dd { 309 reg = <0x3dd 0x1>; 310 bits = <0 4>; 311 }; 312 313 tsens_sens11_off: s11@3dd { 314 reg = <0x3dd 0x1>; 315 bits = <4 4>; 316 }; 317 318 tsens_sens12_off: s12@3de { 319 reg = <0x3de 0x1>; 320 bits = <0 4>; 321 }; 322 323 tsens_sens13_off: s13@3de { 324 reg = <0x3de 0x1>; 325 bits = <4 4>; 326 }; 327 328 tsens_sens14_off: s14@3e5 { 329 reg = <0x3e5 0x2>; 330 bits = <7 4>; 331 }; 332 333 tsens_sens15_off: s15@3e6 { 334 reg = <0x3e6 0x1>; 335 bits = <3 4>; 336 }; 337 338 tsens_mode: mode@419 { 339 reg = <0x419 0x1>; 340 bits = <0 3>; 341 }; 342 343 tsens_base0: base0@419 { 344 reg = <0x419 0x2>; 345 bits = <3 10>; 346 }; 347 348 tsens_base1: base1@41a { 349 reg = <0x41a 0x2>; 350 bits = <5 10>; 351 }; 352 }; 353 354 pcie2_phy: phy@f4000 { 355 compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy", 356 "qcom,ipq9574-qmp-gen3x2-pcie-phy"; 357 reg = <0x0 0x000f4000 0x0 0x2000>; 358 clocks = <&gcc GCC_PCIE2_AUX_CLK>, 359 <&gcc GCC_PCIE2_AHB_CLK>, 360 <&gcc GCC_PCIE2_PIPE_CLK>; 361 clock-names = "aux", 362 "cfg_ahb", 363 "pipe"; 364 365 assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>; 366 assigned-clock-rates = <20000000>; 367 368 resets = <&gcc GCC_PCIE2_PHY_BCR>, 369 <&gcc GCC_PCIE2PHY_PHY_BCR>; 370 reset-names = "phy", 371 "common"; 372 373 #clock-cells = <0>; 374 clock-output-names = "gcc_pcie2_pipe_clk_src"; 375 376 #phy-cells = <0>; 377 status = "disabled"; 378 }; 379 380 pcie3_phy: phy@fc000 { 381 compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy", 382 "qcom,ipq9574-qmp-gen3x2-pcie-phy"; 383 reg = <0x0 0x000fc000 0x0 0x2000>; 384 clocks = <&gcc GCC_PCIE3_AUX_CLK>, 385 <&gcc GCC_PCIE3_AHB_CLK>, 386 <&gcc GCC_PCIE3_PIPE_CLK>; 387 clock-names = "aux", 388 "cfg_ahb", 389 "pipe"; 390 391 assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>; 392 assigned-clock-rates = <20000000>; 393 394 resets = <&gcc GCC_PCIE3_PHY_BCR>, 395 <&gcc GCC_PCIE3PHY_PHY_BCR>; 396 reset-names = "phy", 397 "common"; 398 399 #clock-cells = <0>; 400 clock-output-names = "gcc_pcie3_pipe_clk_src"; 401 402 #phy-cells = <0>; 403 status = "disabled"; 404 }; 405 406 tsens: thermal-sensor@4a9000 { 407 compatible = "qcom,ipq5424-tsens"; 408 reg = <0 0x004a9000 0 0x1000>, 409 <0 0x004a8000 0 0x1000>; 410 interrupts = <GIC_SPI 105 IRQ_TYPE_EDGE_RISING>; 411 interrupt-names = "combined"; 412 nvmem-cells = <&tsens_mode>, 413 <&tsens_base0>, 414 <&tsens_base1>, 415 <&tsens_sens9_off>, 416 <&tsens_sens10_off>, 417 <&tsens_sens11_off>, 418 <&tsens_sens12_off>, 419 <&tsens_sens13_off>, 420 <&tsens_sens14_off>, 421 <&tsens_sens15_off>; 422 nvmem-cell-names = "mode", 423 "base0", 424 "base1", 425 "tsens_sens9_off", 426 "tsens_sens10_off", 427 "tsens_sens11_off", 428 "tsens_sens12_off", 429 "tsens_sens13_off", 430 "tsens_sens14_off", 431 "tsens_sens15_off"; 432 #qcom,sensors = <7>; 433 #thermal-sensor-cells = <1>; 434 }; 435 436 rng: rng@4c3000 { 437 compatible = "qcom,ipq5424-trng", "qcom,trng"; 438 reg = <0 0x004c3000 0 0x1000>; 439 clocks = <&gcc GCC_PRNG_AHB_CLK>; 440 clock-names = "core"; 441 }; 442 443 system-cache-controller@800000 { 444 compatible = "qcom,ipq5424-llcc"; 445 reg = <0 0x00800000 0 0x200000>; 446 reg-names = "llcc0_base"; 447 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 448 }; 449 450 qfprom@a6000 { 451 compatible = "qcom,ipq5424-qfprom", "qcom,qfprom"; 452 reg = <0x0 0x000a6000 0x0 0x1000>; 453 #address-cells = <1>; 454 #size-cells = <1>; 455 456 cpu_speed_bin: cpu-speed-bin@234 { 457 reg = <0x234 0x1>; 458 bits = <0 8>; 459 }; 460 }; 461 462 tlmm: pinctrl@1000000 { 463 compatible = "qcom,ipq5424-tlmm"; 464 reg = <0 0x01000000 0 0x300000>; 465 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 466 gpio-controller; 467 #gpio-cells = <2>; 468 gpio-ranges = <&tlmm 0 0 50>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 472 uart1_pins: uart1-state { 473 pins = "gpio43", "gpio44"; 474 function = "uart1"; 475 drive-strength = <8>; 476 bias-pull-up; 477 }; 478 }; 479 480 gcc: clock-controller@1800000 { 481 compatible = "qcom,ipq5424-gcc"; 482 reg = <0 0x01800000 0 0x40000>; 483 clocks = <&xo_board>, 484 <&sleep_clk>, 485 <&pcie0_phy>, 486 <&pcie1_phy>, 487 <&pcie2_phy>, 488 <&pcie3_phy>, 489 <0>; 490 #clock-cells = <1>; 491 #reset-cells = <1>; 492 #interconnect-cells = <1>; 493 }; 494 495 tcsr_mutex: hwlock@1905000 { 496 compatible = "qcom,tcsr-mutex"; 497 reg = <0 0x01905000 0 0x20000>; 498 #hwlock-cells = <1>; 499 }; 500 501 tcsr: syscon@1937000 { 502 compatible = "qcom,tcsr-ipq5424", "syscon"; 503 reg = <0 0x01937000 0 0x2a000>; 504 }; 505 506 qupv3: geniqup@1ac0000 { 507 compatible = "qcom,geni-se-qup"; 508 reg = <0 0x01ac0000 0 0x2000>; 509 ranges; 510 clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>, 511 <&gcc GCC_QUPV3_AHB_SLV_CLK>; 512 clock-names = "m-ahb", "s-ahb"; 513 #address-cells = <2>; 514 #size-cells = <2>; 515 516 uart0: serial@1a80000 { 517 compatible = "qcom,geni-uart"; 518 reg = <0 0x01a80000 0 0x4000>; 519 clocks = <&gcc GCC_QUPV3_UART0_CLK>; 520 clock-names = "se"; 521 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 522 status = "disabled"; 523 }; 524 525 uart1: serial@1a84000 { 526 compatible = "qcom,geni-debug-uart"; 527 reg = <0 0x01a84000 0 0x4000>; 528 clocks = <&gcc GCC_QUPV3_UART1_CLK>; 529 clock-names = "se"; 530 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 531 }; 532 533 spi0: spi@1a90000 { 534 compatible = "qcom,geni-spi"; 535 reg = <0 0x01a90000 0 0x4000>; 536 clocks = <&gcc GCC_QUPV3_SPI0_CLK>; 537 clock-names = "se"; 538 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 status = "disabled"; 542 }; 543 544 spi1: spi@1a94000 { 545 compatible = "qcom,geni-spi"; 546 reg = <0 0x01a94000 0 0x4000>; 547 clocks = <&gcc GCC_QUPV3_SPI1_CLK>; 548 clock-names = "se"; 549 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 status = "disabled"; 553 }; 554 }; 555 556 sdhc: mmc@7804000 { 557 compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5"; 558 reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>; 559 reg-names = "hc", "cqhci"; 560 561 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 563 interrupt-names = "hc_irq", "pwr_irq"; 564 565 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 566 <&gcc GCC_SDCC1_APPS_CLK>, 567 <&xo_board>; 568 clock-names = "iface", "core", "xo"; 569 570 supports-cqe; 571 572 status = "disabled"; 573 }; 574 575 qpic_bam: dma-controller@7984000 { 576 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 577 reg = <0x0 0x07984000 0x0 0x1c000>; 578 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&gcc GCC_QPIC_AHB_CLK>; 580 clock-names = "bam_clk"; 581 #dma-cells = <1>; 582 qcom,ee = <0>; 583 status = "disabled"; 584 }; 585 586 qpic_nand: spi@79b0000 { 587 compatible = "qcom,ipq5424-snand", "qcom,ipq9574-snand"; 588 reg = <0x0 0x079b0000 0x0 0x10000>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 clocks = <&gcc GCC_QPIC_CLK>, 592 <&gcc GCC_QPIC_AHB_CLK>, 593 <&gcc GCC_QPIC_IO_MACRO_CLK>; 594 clock-names = "core", 595 "aon", 596 "iom"; 597 598 dmas = <&qpic_bam 0>, 599 <&qpic_bam 1>, 600 <&qpic_bam 2>; 601 dma-names = "tx", 602 "rx", 603 "cmd"; 604 605 status = "disabled"; 606 }; 607 608 intc: interrupt-controller@f200000 { 609 compatible = "arm,gic-v3"; 610 reg = <0 0xf200000 0 0x10000>, /* GICD */ 611 <0 0xf240000 0 0x80000>; /* GICR * 4 regions */ 612 #address-cells = <0>; 613 #interrupt-cells = <0x3>; 614 interrupt-controller; 615 #redistributor-regions = <1>; 616 redistributor-stride = <0x0 0x20000>; 617 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 618 mbi-ranges = <672 128>; 619 msi-controller; 620 }; 621 622 watchdog@f410000 { 623 compatible = "qcom,apss-wdt-ipq5424", "qcom,kpss-wdt"; 624 reg = <0 0x0f410000 0 0x1000>; 625 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 626 clocks = <&sleep_clk>; 627 }; 628 629 qusb_phy_1: phy@71000 { 630 compatible = "qcom,ipq5424-qusb2-phy"; 631 reg = <0 0x00071000 0 0x180>; 632 #phy-cells = <0>; 633 634 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 635 <&xo_board>; 636 clock-names = "cfg_ahb", "ref"; 637 638 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 639 status = "disabled"; 640 }; 641 642 usb2: usb2@1e00000 { 643 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; 644 reg = <0 0x01ef8800 0 0x400>; 645 #address-cells = <2>; 646 #size-cells = <2>; 647 ranges; 648 649 clocks = <&gcc GCC_USB1_MASTER_CLK>, 650 <&gcc GCC_USB1_SLEEP_CLK>, 651 <&gcc GCC_USB1_MOCK_UTMI_CLK>, 652 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 653 <&gcc GCC_CNOC_USB_CLK>; 654 655 clock-names = "core", 656 "sleep", 657 "mock_utmi", 658 "iface", 659 "cfg_noc"; 660 661 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, 662 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 663 assigned-clock-rates = <200000000>, 664 <24000000>; 665 666 interrupts-extended = <&intc GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 667 <&intc GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 668 <&intc GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 669 <&intc GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>; 670 interrupt-names = "pwr_event", 671 "qusb2_phy", 672 "dm_hs_phy_irq", 673 "dp_hs_phy_irq"; 674 675 resets = <&gcc GCC_USB1_BCR>; 676 qcom,select-utmi-as-pipe-clk; 677 status = "disabled"; 678 679 dwc_1: usb@1e00000 { 680 compatible = "snps,dwc3"; 681 reg = <0 0x01e00000 0 0xe000>; 682 clocks = <&gcc GCC_USB1_MOCK_UTMI_CLK>; 683 clock-names = "ref"; 684 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 685 phys = <&qusb_phy_1>; 686 phy-names = "usb2-phy"; 687 tx-fifo-resize; 688 snps,is-utmi-l1-suspend; 689 snps,hird-threshold = /bits/ 8 <0x0>; 690 snps,dis_u2_susphy_quirk; 691 snps,dis_u3_susphy_quirk; 692 }; 693 }; 694 695 qusb_phy_0: phy@7b000 { 696 compatible = "qcom,ipq5424-qusb2-phy"; 697 reg = <0 0x0007b000 0 0x180>; 698 #phy-cells = <0>; 699 700 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 701 <&xo_board>; 702 clock-names = "cfg_ahb", "ref"; 703 704 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 705 status = "disabled"; 706 }; 707 708 ssphy_0: phy@7d000 { 709 compatible = "qcom,ipq5424-qmp-usb3-phy"; 710 reg = <0 0x0007d000 0 0xa00>; 711 #phy-cells = <0>; 712 713 clocks = <&gcc GCC_USB0_AUX_CLK>, 714 <&xo_board>, 715 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 716 <&gcc GCC_USB0_PIPE_CLK>; 717 clock-names = "aux", 718 "ref", 719 "cfg_ahb", 720 "pipe"; 721 722 resets = <&gcc GCC_USB0_PHY_BCR>, 723 <&gcc GCC_USB3PHY_0_PHY_BCR>; 724 reset-names = "phy", 725 "phy_phy"; 726 727 #clock-cells = <0>; 728 clock-output-names = "usb0_pipe_clk"; 729 730 status = "disabled"; 731 }; 732 733 usb3: usb3@8a00000 { 734 compatible = "qcom,ipq5424-dwc3", "qcom,dwc3"; 735 reg = <0 0x08af8800 0 0x400>; 736 737 #address-cells = <2>; 738 #size-cells = <2>; 739 ranges; 740 741 clocks = <&gcc GCC_USB0_MASTER_CLK>, 742 <&gcc GCC_USB0_SLEEP_CLK>, 743 <&gcc GCC_USB0_MOCK_UTMI_CLK>, 744 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 745 <&gcc GCC_CNOC_USB_CLK>; 746 747 clock-names = "core", 748 "sleep", 749 "mock_utmi", 750 "iface", 751 "cfg_noc"; 752 753 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, 754 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 755 assigned-clock-rates = <200000000>, 756 <24000000>; 757 758 interrupts-extended = <&intc GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 759 <&intc GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 760 <&intc GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 761 <&intc GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 762 interrupt-names = "pwr_event", 763 "qusb2_phy", 764 "dm_hs_phy_irq", 765 "dp_hs_phy_irq"; 766 767 resets = <&gcc GCC_USB_BCR>; 768 status = "disabled"; 769 770 dwc_0: usb@8a00000 { 771 compatible = "snps,dwc3"; 772 reg = <0 0x08a00000 0 0xcd00>; 773 clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; 774 clock-names = "ref"; 775 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 776 phys = <&qusb_phy_0>, <&ssphy_0>; 777 phy-names = "usb2-phy", "usb3-phy"; 778 tx-fifo-resize; 779 snps,is-utmi-l1-suspend; 780 snps,hird-threshold = /bits/ 8 <0x0>; 781 snps,dis_u2_susphy_quirk; 782 snps,dis_u3_susphy_quirk; 783 snps,dis-u1-entry-quirk; 784 snps,dis-u2-entry-quirk; 785 }; 786 }; 787 788 timer@f420000 { 789 compatible = "arm,armv7-timer-mem"; 790 reg = <0 0xf420000 0 0x1000>; 791 ranges = <0 0 0 0x10000000>; 792 #address-cells = <1>; 793 #size-cells = <1>; 794 795 frame@f421000 { 796 reg = <0xf421000 0x1000>, 797 <0xf422000 0x1000>; 798 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 800 frame-number = <0>; 801 }; 802 803 frame@f423000 { 804 reg = <0xf423000 0x1000>; 805 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 806 frame-number = <1>; 807 status = "disabled"; 808 }; 809 810 frame@f425000 { 811 reg = <0xf425000 0x1000>, 812 <0xf426000 0x1000>; 813 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 814 frame-number = <2>; 815 status = "disabled"; 816 }; 817 818 frame@f427000 { 819 reg = <0xf427000 0x1000>; 820 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 821 frame-number = <3>; 822 status = "disabled"; 823 }; 824 825 frame@f429000 { 826 reg = <0xf429000 0x1000>; 827 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 828 frame-number = <4>; 829 status = "disabled"; 830 }; 831 832 frame@f42b000 { 833 reg = <0xf42b000 0x1000>; 834 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 835 frame-number = <5>; 836 status = "disabled"; 837 }; 838 839 frame@f42d000 { 840 reg = <0xf42d000 0x1000>; 841 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 842 frame-number = <6>; 843 status = "disabled"; 844 }; 845 }; 846 847 apss_clk: clock-controller@fa80000 { 848 compatible = "qcom,ipq5424-apss-clk"; 849 reg = <0x0 0x0fa80000 0x0 0x20000>; 850 clocks = <&xo_board>, 851 <&gcc GPLL0>; 852 #clock-cells = <1>; 853 #interconnect-cells = <1>; 854 }; 855 856 clock-controller@39b00000 { 857 compatible = "qcom,ipq5424-nsscc"; 858 reg = <0 0x39b00000 0 0x100000>; 859 clocks = <&cmn_pll IPQ5424_XO_24MHZ_CLK>, 860 <&cmn_pll IPQ5424_NSS_300MHZ_CLK>, 861 <&cmn_pll IPQ5424_PPE_375MHZ_CLK>, 862 <&gcc GPLL0_OUT_AUX>, 863 <0>, 864 <0>, 865 <0>, 866 <0>, 867 <0>, 868 <0>, 869 <&gcc GCC_NSSCC_CLK>; 870 clock-names = "xo", 871 "nss", 872 "ppe", 873 "gpll0_out", 874 "uniphy0_rx", 875 "uniphy0_tx", 876 "uniphy1_rx", 877 "uniphy1_tx", 878 "uniphy2_rx", 879 "uniphy2_tx", 880 "bus"; 881 #clock-cells = <1>; 882 #reset-cells = <1>; 883 #interconnect-cells = <1>; 884 }; 885 886 pcie3: pcie@40000000 { 887 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; 888 reg = <0x0 0x40000000 0x0 0xf1c>, 889 <0x0 0x40000f20 0x0 0xa8>, 890 <0x0 0x40001000 0x0 0x1000>, 891 <0x0 0x000f8000 0x0 0x3000>, 892 <0x0 0x40100000 0x0 0x1000>, 893 <0x0 0x000fe000 0x0 0x1000>; 894 reg-names = "dbi", 895 "elbi", 896 "atu", 897 "parf", 898 "config", 899 "mhi"; 900 device_type = "pci"; 901 linux,pci-domain = <3>; 902 num-lanes = <2>; 903 #address-cells = <3>; 904 #size-cells = <2>; 905 906 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x00100000>, 907 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x0fd00000>; 908 909 msi-map = <0x0 &intc 0x0 0x1000>; 910 911 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>; 920 921 interrupt-names = "msi0", 922 "msi1", 923 "msi2", 924 "msi3", 925 "msi4", 926 "msi5", 927 "msi6", 928 "msi7", 929 "global"; 930 931 #interrupt-cells = <1>; 932 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 933 interrupt-map = <0 0 0 1 &intc GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 934 <0 0 0 2 &intc GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>, 935 <0 0 0 3 &intc GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, 936 <0 0 0 4 &intc GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>; 937 938 clocks = <&gcc GCC_PCIE3_AXI_M_CLK>, 939 <&gcc GCC_PCIE3_AXI_S_CLK>, 940 <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, 941 <&gcc GCC_PCIE3_RCHNG_CLK>, 942 <&gcc GCC_PCIE3_AHB_CLK>, 943 <&gcc GCC_PCIE3_AUX_CLK>; 944 clock-names = "axi_m", 945 "axi_s", 946 "axi_bridge", 947 "rchng", 948 "ahb", 949 "aux"; 950 951 assigned-clocks = <&gcc GCC_PCIE3_RCHNG_CLK>; 952 assigned-clock-rates = <100000000>; 953 954 resets = <&gcc GCC_PCIE3_PIPE_ARES>, 955 <&gcc GCC_PCIE3_CORE_STICKY_RESET>, 956 <&gcc GCC_PCIE3_AXI_S_STICKY_RESET>, 957 <&gcc GCC_PCIE3_AXI_S_ARES>, 958 <&gcc GCC_PCIE3_AXI_M_STICKY_RESET>, 959 <&gcc GCC_PCIE3_AXI_M_ARES>, 960 <&gcc GCC_PCIE3_AUX_ARES>, 961 <&gcc GCC_PCIE3_AHB_ARES>; 962 reset-names = "pipe", 963 "sticky", 964 "axi_s_sticky", 965 "axi_s", 966 "axi_m_sticky", 967 "axi_m", 968 "aux", 969 "ahb"; 970 971 phys = <&pcie3_phy>; 972 phy-names = "pciephy"; 973 interconnects = <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, 974 <&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>; 975 interconnect-names = "pcie-mem", "cpu-pcie"; 976 977 status = "disabled"; 978 979 pcie@0 { 980 device_type = "pci"; 981 reg = <0x0 0x0 0x0 0x0 0x0>; 982 bus-range = <0x01 0xff>; 983 984 #address-cells = <3>; 985 #size-cells = <2>; 986 ranges; 987 }; 988 }; 989 990 pcie2: pcie@50000000 { 991 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; 992 reg = <0x0 0x50000000 0x0 0xf1c>, 993 <0x0 0x50000f20 0x0 0xa8>, 994 <0x0 0x50001000 0x0 0x1000>, 995 <0x0 0x000f0000 0x0 0x3000>, 996 <0x0 0x50100000 0x0 0x1000>, 997 <0x0 0x000f6000 0x0 0x1000>; 998 reg-names = "dbi", 999 "elbi", 1000 "atu", 1001 "parf", 1002 "config", 1003 "mhi"; 1004 device_type = "pci"; 1005 linux,pci-domain = <2>; 1006 num-lanes = <2>; 1007 #address-cells = <3>; 1008 #size-cells = <2>; 1009 1010 ranges = <0x01000000 0x0 0x00000000 0x0 0x50200000 0x0 0x00100000>, 1011 <0x02000000 0x0 0x50300000 0x0 0x50300000 0x0 0x0fd00000>; 1012 1013 msi-map = <0x0 &intc 0x0 0x1000>; 1014 1015 interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>; 1024 interrupt-names = "msi0", 1025 "msi1", 1026 "msi2", 1027 "msi3", 1028 "msi4", 1029 "msi5", 1030 "msi6", 1031 "msi7", 1032 "global"; 1033 1034 #interrupt-cells = <1>; 1035 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 1036 interrupt-map = <0 0 0 1 &intc GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 1037 <0 0 0 2 &intc GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 1038 <0 0 0 3 &intc GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 1039 <0 0 0 4 &intc GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1040 1041 clocks = <&gcc GCC_PCIE2_AXI_M_CLK>, 1042 <&gcc GCC_PCIE2_AXI_S_CLK>, 1043 <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, 1044 <&gcc GCC_PCIE2_RCHNG_CLK>, 1045 <&gcc GCC_PCIE2_AHB_CLK>, 1046 <&gcc GCC_PCIE2_AUX_CLK>; 1047 clock-names = "axi_m", 1048 "axi_s", 1049 "axi_bridge", 1050 "rchng", 1051 "ahb", 1052 "aux"; 1053 1054 assigned-clocks = <&gcc GCC_PCIE2_RCHNG_CLK>; 1055 assigned-clock-rates = <100000000>; 1056 1057 resets = <&gcc GCC_PCIE2_PIPE_ARES>, 1058 <&gcc GCC_PCIE2_CORE_STICKY_RESET>, 1059 <&gcc GCC_PCIE2_AXI_S_STICKY_RESET>, 1060 <&gcc GCC_PCIE2_AXI_S_ARES>, 1061 <&gcc GCC_PCIE2_AXI_M_STICKY_RESET>, 1062 <&gcc GCC_PCIE2_AXI_M_ARES>, 1063 <&gcc GCC_PCIE2_AUX_ARES>, 1064 <&gcc GCC_PCIE2_AHB_ARES>; 1065 reset-names = "pipe", 1066 "sticky", 1067 "axi_s_sticky", 1068 "axi_s", 1069 "axi_m_sticky", 1070 "axi_m", 1071 "aux", 1072 "ahb"; 1073 1074 phys = <&pcie2_phy>; 1075 phy-names = "pciephy"; 1076 interconnects = <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, 1077 <&gcc MASTER_CNOC_PCIE2 &gcc SLAVE_CNOC_PCIE2>; 1078 interconnect-names = "pcie-mem", "cpu-pcie"; 1079 1080 status = "disabled"; 1081 1082 pcie@0 { 1083 device_type = "pci"; 1084 reg = <0x0 0x0 0x0 0x0 0x0>; 1085 bus-range = <0x01 0xff>; 1086 1087 #address-cells = <3>; 1088 #size-cells = <2>; 1089 ranges; 1090 }; 1091 }; 1092 1093 pcie1: pcie@60000000 { 1094 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; 1095 reg = <0x0 0x60000000 0x0 0xf1c>, 1096 <0x0 0x60000f20 0x0 0xa8>, 1097 <0x0 0x60001000 0x0 0x1000>, 1098 <0x0 0x00088000 0x0 0x3000>, 1099 <0x0 0x60100000 0x0 0x1000>, 1100 <0x0 0x0008e000 0x0 0x1000>; 1101 reg-names = "dbi", 1102 "elbi", 1103 "atu", 1104 "parf", 1105 "config", 1106 "mhi"; 1107 device_type = "pci"; 1108 linux,pci-domain = <1>; 1109 num-lanes = <1>; 1110 #address-cells = <3>; 1111 #size-cells = <2>; 1112 1113 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x00100000>, 1114 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x0fd00000>; 1115 1116 msi-map = <0x0 &intc 0x0 0x1000>; 1117 1118 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>; 1127 interrupt-names = "msi0", 1128 "msi1", 1129 "msi2", 1130 "msi3", 1131 "msi4", 1132 "msi5", 1133 "msi6", 1134 "msi7", 1135 "global"; 1136 1137 #interrupt-cells = <1>; 1138 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 1139 interrupt-map = <0 0 0 1 &intc GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 1140 <0 0 0 2 &intc GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 1141 <0 0 0 3 &intc GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 1142 <0 0 0 4 &intc GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>; 1143 1144 clocks = <&gcc GCC_PCIE1_AXI_M_CLK>, 1145 <&gcc GCC_PCIE1_AXI_S_CLK>, 1146 <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, 1147 <&gcc GCC_PCIE1_RCHNG_CLK>, 1148 <&gcc GCC_PCIE1_AHB_CLK>, 1149 <&gcc GCC_PCIE1_AUX_CLK>; 1150 clock-names = "axi_m", 1151 "axi_s", 1152 "axi_bridge", 1153 "rchng", 1154 "ahb", 1155 "aux"; 1156 1157 assigned-clocks = <&gcc GCC_PCIE1_RCHNG_CLK>; 1158 assigned-clock-rates = <100000000>; 1159 1160 resets = <&gcc GCC_PCIE1_PIPE_ARES>, 1161 <&gcc GCC_PCIE1_CORE_STICKY_RESET>, 1162 <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>, 1163 <&gcc GCC_PCIE1_AXI_S_ARES>, 1164 <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>, 1165 <&gcc GCC_PCIE1_AXI_M_ARES>, 1166 <&gcc GCC_PCIE1_AUX_ARES>, 1167 <&gcc GCC_PCIE1_AHB_ARES>; 1168 reset-names = "pipe", 1169 "sticky", 1170 "axi_s_sticky", 1171 "axi_s", 1172 "axi_m_sticky", 1173 "axi_m", 1174 "aux", 1175 "ahb"; 1176 1177 phys = <&pcie1_phy>; 1178 phy-names = "pciephy"; 1179 interconnects = <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, 1180 <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>; 1181 interconnect-names = "pcie-mem", "cpu-pcie"; 1182 1183 status = "disabled"; 1184 1185 pcie@0 { 1186 device_type = "pci"; 1187 reg = <0x0 0x0 0x0 0x0 0x0>; 1188 bus-range = <0x01 0xff>; 1189 1190 #address-cells = <3>; 1191 #size-cells = <2>; 1192 ranges; 1193 }; 1194 }; 1195 1196 pcie0: pcie@70000000 { 1197 compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574"; 1198 reg = <0x0 0x70000000 0x0 0xf1c>, 1199 <0x0 0x70000f20 0x0 0xa8>, 1200 <0x0 0x70001000 0x0 0x1000>, 1201 <0x0 0x00080000 0x0 0x3000>, 1202 <0x0 0x70100000 0x0 0x1000>, 1203 <0x0 0x00086000 0x0 0x1000>; 1204 reg-names = "dbi", 1205 "elbi", 1206 "atu", 1207 "parf", 1208 "config", 1209 "mhi"; 1210 device_type = "pci"; 1211 linux,pci-domain = <0>; 1212 num-lanes = <1>; 1213 #address-cells = <3>; 1214 #size-cells = <2>; 1215 1216 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x00100000>, 1217 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x0fd00000>; 1218 1219 msi-map = <0x0 &intc 0x0 0x1000>; 1220 1221 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>; 1230 interrupt-names = "msi0", 1231 "msi1", 1232 "msi2", 1233 "msi3", 1234 "msi4", 1235 "msi5", 1236 "msi6", 1237 "msi7", 1238 "global"; 1239 1240 #interrupt-cells = <1>; 1241 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 1242 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 1243 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 1244 <0 0 0 3 &intc GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 1245 <0 0 0 4 &intc GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; 1246 1247 clocks = <&gcc GCC_PCIE0_AXI_M_CLK>, 1248 <&gcc GCC_PCIE0_AXI_S_CLK>, 1249 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 1250 <&gcc GCC_PCIE0_RCHNG_CLK>, 1251 <&gcc GCC_PCIE0_AHB_CLK>, 1252 <&gcc GCC_PCIE0_AUX_CLK>; 1253 clock-names = "axi_m", 1254 "axi_s", 1255 "axi_bridge", 1256 "rchng", 1257 "ahb", 1258 "aux"; 1259 1260 assigned-clocks = <&gcc GCC_PCIE0_RCHNG_CLK>; 1261 assigned-clock-rates = <100000000>; 1262 1263 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 1264 <&gcc GCC_PCIE0_CORE_STICKY_RESET>, 1265 <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>, 1266 <&gcc GCC_PCIE0_AXI_S_ARES>, 1267 <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>, 1268 <&gcc GCC_PCIE0_AXI_M_ARES>, 1269 <&gcc GCC_PCIE0_AUX_ARES>, 1270 <&gcc GCC_PCIE0_AHB_ARES>; 1271 reset-names = "pipe", 1272 "sticky", 1273 "axi_s_sticky", 1274 "axi_s", 1275 "axi_m_sticky", 1276 "axi_m", 1277 "aux", 1278 "ahb"; 1279 1280 phys = <&pcie0_phy>; 1281 phy-names = "pciephy"; 1282 interconnects = <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, 1283 <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>; 1284 interconnect-names = "pcie-mem", "cpu-pcie"; 1285 1286 status = "disabled"; 1287 1288 pcie@0 { 1289 device_type = "pci"; 1290 reg = <0x0 0x0 0x0 0x0 0x0>; 1291 bus-range = <0x01 0xff>; 1292 1293 #address-cells = <3>; 1294 #size-cells = <2>; 1295 ranges; 1296 }; 1297 }; 1298 }; 1299 1300 thermal_zones: thermal-zones { 1301 cpu0-thermal { 1302 polling-delay-passive = <100>; 1303 thermal-sensors = <&tsens 14>; 1304 1305 trips { 1306 cpu0_crit: cpu-critical { 1307 temperature = <120000>; 1308 hysteresis = <9000>; 1309 type = "critical"; 1310 }; 1311 1312 cpu0_alert: cpu-passive { 1313 temperature = <110000>; 1314 hysteresis = <9000>; 1315 type = "passive"; 1316 }; 1317 }; 1318 1319 cooling-maps { 1320 map0 { 1321 trip = <&cpu0_alert>; 1322 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1323 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1324 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1325 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1326 }; 1327 }; 1328 }; 1329 1330 cpu1-thermal { 1331 polling-delay-passive = <100>; 1332 thermal-sensors = <&tsens 12>; 1333 1334 trips { 1335 cpu1_crit: cpu-critical { 1336 temperature = <120000>; 1337 hysteresis = <9000>; 1338 type = "critical"; 1339 }; 1340 1341 cpu1_alert: cpu-passive { 1342 temperature = <110000>; 1343 hysteresis = <9000>; 1344 type = "passive"; 1345 }; 1346 }; 1347 1348 cooling-maps { 1349 map0 { 1350 trip = <&cpu1_alert>; 1351 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1352 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1353 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1354 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1355 }; 1356 }; 1357 }; 1358 1359 cpu2-thermal { 1360 polling-delay-passive = <100>; 1361 thermal-sensors = <&tsens 11>; 1362 1363 trips { 1364 cpu2_crit: cpu-critical { 1365 temperature = <120000>; 1366 hysteresis = <9000>; 1367 type = "critical"; 1368 }; 1369 1370 cpu2_alert: cpu-passive { 1371 temperature = <110000>; 1372 hysteresis = <9000>; 1373 type = "passive"; 1374 }; 1375 }; 1376 1377 cooling-maps { 1378 map0 { 1379 trip = <&cpu2_alert>; 1380 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1381 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1382 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1383 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1384 }; 1385 }; 1386 }; 1387 1388 cpu3-thermal { 1389 polling-delay-passive = <100>; 1390 thermal-sensors = <&tsens 13>; 1391 1392 trips { 1393 cpu3_crit: cpu-critical { 1394 temperature = <120000>; 1395 hysteresis = <9000>; 1396 type = "critical"; 1397 }; 1398 1399 cpu3_alert: cpu-passive { 1400 temperature = <110000>; 1401 hysteresis = <9000>; 1402 type = "passive"; 1403 }; 1404 }; 1405 1406 cooling-maps { 1407 map0 { 1408 trip = <&cpu3_alert>; 1409 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1410 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1411 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1412 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1413 }; 1414 }; 1415 }; 1416 1417 wcss-tile2-thermal { 1418 thermal-sensors = <&tsens 9>; 1419 1420 trips { 1421 wcss-tile2-critical { 1422 temperature = <125000>; 1423 hysteresis = <9000>; 1424 type = "critical"; 1425 }; 1426 }; 1427 }; 1428 1429 wcss-tile3-thermal { 1430 thermal-sensors = <&tsens 10>; 1431 1432 trips { 1433 wcss-tile3-critical { 1434 temperature = <125000>; 1435 hysteresis = <9000>; 1436 type = "critical"; 1437 }; 1438 }; 1439 }; 1440 1441 top-glue-thermal { 1442 thermal-sensors = <&tsens 15>; 1443 1444 trips { 1445 top-glue-critical { 1446 temperature = <125000>; 1447 hysteresis = <9000>; 1448 type = "critical"; 1449 }; 1450 }; 1451 }; 1452 }; 1453 1454 timer { 1455 compatible = "arm,armv8-timer"; 1456 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1457 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1458 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1459 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1460 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1461 }; 1462}; 1463