1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2/* 3 * IPQ5424 RDP466 board device tree source 4 * 5 * Copyright (c) 2024-2025 The Linux Foundation. All rights reserved. 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/leds/common.h> 12#include "ipq5424.dtsi" 13 14/ { 15 model = "Qualcomm Technologies, Inc. IPQ5424 RDP466"; 16 compatible = "qcom,ipq5424-rdp466", "qcom,ipq5424"; 17 18 aliases { 19 serial0 = &uart1; 20 }; 21 22 gpio-keys { 23 compatible = "gpio-keys"; 24 pinctrl-0 = <&gpio_keys_default>; 25 pinctrl-names = "default"; 26 27 button-wps { 28 label = "wps"; 29 linux,code = <KEY_WPS_BUTTON>; 30 gpios = <&tlmm 19 GPIO_ACTIVE_LOW>; 31 debounce-interval = <60>; 32 }; 33 }; 34 35 leds { 36 compatible = "gpio-leds"; 37 pinctrl-0 = <&gpio_leds_default>; 38 pinctrl-names = "default"; 39 40 led-0 { 41 color = <LED_COLOR_ID_GREEN>; 42 function = LED_FUNCTION_WLAN; 43 gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>; 44 linux,default-trigger = "phy0tx"; 45 default-state = "off"; 46 }; 47 }; 48 49 vreg_misc_3p3: regulator-usb-3p3 { 50 compatible = "regulator-fixed"; 51 regulator-min-microvolt = <3300000>; 52 regulator-max-microvolt = <3300000>; 53 regulator-boot-on; 54 regulator-always-on; 55 regulator-name = "usb_hs_vdda_3p3"; 56 }; 57 58 vreg_misc_1p8: regulator-usb-1p8 { 59 compatible = "regulator-fixed"; 60 regulator-min-microvolt = <1800000>; 61 regulator-max-microvolt = <1800000>; 62 regulator-boot-on; 63 regulator-always-on; 64 regulator-name = "vdda_1p8_usb"; 65 }; 66 67 vreg_misc_0p925: regulator-usb-0p925 { 68 compatible = "regulator-fixed"; 69 regulator-min-microvolt = <925000>; 70 regulator-max-microvolt = <925000>; 71 regulator-boot-on; 72 regulator-always-on; 73 regulator-name = "vdd_core_usb"; 74 }; 75}; 76 77&dwc_0 { 78 dr_mode = "host"; 79}; 80 81&dwc_1 { 82 dr_mode = "host"; 83}; 84 85&pcie2 { 86 pinctrl-0 = <&pcie2_default_state>; 87 pinctrl-names = "default"; 88 89 perst-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; 90 91 status = "okay"; 92}; 93 94&pcie2_phy { 95 status = "okay"; 96}; 97 98&pcie3 { 99 pinctrl-0 = <&pcie3_default_state>; 100 pinctrl-names = "default"; 101 102 perst-gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; 103 104 status = "okay"; 105}; 106 107&pcie3_phy { 108 status = "okay"; 109}; 110 111&qusb_phy_0 { 112 vdd-supply = <&vreg_misc_0p925>; 113 vdda-pll-supply = <&vreg_misc_1p8>; 114 vdda-phy-dpdm-supply = <&vreg_misc_3p3>; 115 116 status = "okay"; 117}; 118 119&qusb_phy_1 { 120 vdd-supply = <&vreg_misc_0p925>; 121 vdda-pll-supply = <&vreg_misc_1p8>; 122 vdda-phy-dpdm-supply = <&vreg_misc_3p3>; 123 124 status = "okay"; 125}; 126 127&sdhc { 128 pinctrl-0 = <&sdc_default_state>; 129 pinctrl-names = "default"; 130 131 status = "okay"; 132}; 133 134&sleep_clk { 135 clock-frequency = <32000>; 136}; 137 138&spi0 { 139 pinctrl-0 = <&spi0_default_state>; 140 pinctrl-names = "default"; 141 status = "okay"; 142 143 flash@0 { 144 compatible = "micron,n25q128a11", "jedec,spi-nor"; 145 reg = <0>; 146 #address-cells = <1>; 147 #size-cells = <1>; 148 spi-max-frequency = <50000000>; 149 }; 150}; 151 152&ssphy_0 { 153 vdda-pll-supply = <&vreg_misc_1p8>; 154 vdda-phy-supply = <&vreg_misc_0p925>; 155 156 status = "okay"; 157}; 158 159&tlmm { 160 gpio_keys_default: gpio-keys-default-state { 161 pins = "gpio19"; 162 function = "gpio"; 163 drive-strength = <8>; 164 bias-pull-up; 165 }; 166 167 gpio_leds_default: gpio-leds-default-state { 168 pins = "gpio42"; 169 function = "gpio"; 170 drive-strength = <8>; 171 bias-pull-down; 172 }; 173 174 spi0_default_state: spi0-default-state { 175 clk-pins { 176 pins = "gpio6"; 177 function = "spi0_clk"; 178 drive-strength = <8>; 179 bias-pull-down; 180 }; 181 182 cs-pins { 183 pins = "gpio7"; 184 function = "spi0_cs"; 185 drive-strength = <8>; 186 bias-pull-up; 187 }; 188 189 miso-pins { 190 pins = "gpio8"; 191 function = "spi0_miso"; 192 drive-strength = <8>; 193 bias-pull-down; 194 }; 195 196 mosi-pins { 197 pins = "gpio9"; 198 function = "spi0_mosi"; 199 drive-strength = <8>; 200 bias-pull-down; 201 }; 202 }; 203 204 sdc_default_state: sdc-default-state { 205 clk-pins { 206 pins = "gpio5"; 207 function = "sdc_clk"; 208 drive-strength = <8>; 209 bias-disable; 210 }; 211 212 cmd-pins { 213 pins = "gpio4"; 214 function = "sdc_cmd"; 215 drive-strength = <8>; 216 bias-pull-up; 217 }; 218 219 data-pins { 220 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 221 function = "sdc_data"; 222 drive-strength = <8>; 223 bias-pull-up; 224 }; 225 }; 226 227 uart0_pins: uart0-default-state { 228 pins = "gpio10", "gpio11", "gpio12", "gpio13"; 229 function = "uart0"; 230 drive-strength = <8>; 231 bias-pull-down; 232 }; 233 234 pcie2_default_state: pcie2-default-state { 235 pins = "gpio31"; 236 function = "gpio"; 237 drive-strength = <8>; 238 bias-pull-up; 239 }; 240 241 pcie3_default_state: pcie3-default-state { 242 pins = "gpio34"; 243 function = "gpio"; 244 drive-strength = <8>; 245 bias-pull-up; 246 }; 247}; 248 249&uart0 { 250 pinctrl-0 = <&uart0_pins>; 251 pinctrl-names = "default"; 252 /* 253 * The required initialization for this SE is not handled by the 254 * bootloader. Therefore, keep the device in "reserved" state until 255 * linux gains support for configuring the SE. 256 */ 257 status = "reserved"; 258}; 259 260&uart1 { 261 pinctrl-0 = <&uart1_pins>; 262 pinctrl-names = "default"; 263 status = "okay"; 264}; 265 266&usb2 { 267 status = "okay"; 268}; 269 270&usb3 { 271 status = "okay"; 272}; 273 274/* 275 * The bootstrap pins for the board select the XO clock frequency that 276 * supports 48 MHZ, 96 MHZ or 192 MHZ. This setting automatically 277 * enables the right dividers, to ensure the reference clock output 278 * from WiFi to the CMN PLL is 48 MHZ. 279 */ 280&ref_48mhz_clk { 281 clock-div = <1>; 282 clock-mult = <1>; 283}; 284 285/* 286 * The frequency of xo_board is fixed to 24 MHZ, which is routed 287 * from WiFi output clock 48 MHZ divided by 2. 288 */ 289&xo_board { 290 clock-div = <2>; 291 clock-mult = <1>; 292}; 293 294&xo_clk { 295 clock-frequency = <48000000>; 296}; 297